atlx.h revision ff772b27e5f65c1a186e9f0741f0d00ef7002799
1305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* atlx_hw.h -- common hardware definitions for Attansic network drivers 2305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 3305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved. 4305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com> 5305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * Copyright(c) 2006 Jay Cliburn <jcliburn@gmail.com> 6305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * Copyright(c) 2007 Atheros Corporation. All rights reserved. 7305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 8305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * Derived from Intel e1000 driver 9305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. 10305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 11305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * This program is free software; you can redistribute it and/or modify it 12305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * under the terms of the GNU General Public License as published by the Free 13305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * Software Foundation; either version 2 of the License, or (at your option) 14305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * any later version. 15305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 16305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * This program is distributed in the hope that it will be useful, but WITHOUT 17305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * more details. 20305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 21305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * You should have received a copy of the GNU General Public License along with 22305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * this program; if not, write to the Free Software Foundation, Inc., 59 23305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * Temple Place - Suite 330, Boston, MA 02111-1307, USA. 24305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn */ 25305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 26305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#ifndef ATLX_H 27305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ATLX_H 28305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 29305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#include <linux/module.h> 30305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#include <linux/types.h> 31305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 32305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ATLX_DRIVER_VERSION "2.1.1" 33305282ba19f81e571bd6d2dcc10ebb02e59a06efJay CliburnMODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, \ 34305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn Chris Snook <csnook@redhat.com>, Jay Cliburn <jcliburn@gmail.com>"); 35305282ba19f81e571bd6d2dcc10ebb02e59a06efJay CliburnMODULE_LICENSE("GPL"); 36305282ba19f81e571bd6d2dcc10ebb02e59a06efJay CliburnMODULE_VERSION(ATLX_DRIVER_VERSION); 37305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 38305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ATLX_ERR_PHY 2 39305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ATLX_ERR_PHY_SPEED 7 40305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ATLX_ERR_PHY_RES 8 41305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 42305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPEED_0 0xffff 43305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPEED_10 10 44305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPEED_100 100 45305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPEED_1000 1000 46305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define HALF_DUPLEX 1 47305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define FULL_DUPLEX 2 48305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 49305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MEDIA_TYPE_AUTO_SENSOR 0 50305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 51305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* register definitions */ 52305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_PM_CTRLSTAT 0x44 53305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 54305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_PCIE_CAP_LIST 0x58 55305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 56305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_VPD_CAP 0x6C 57305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define VPD_CAP_ID_MASK 0xFF 58305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define VPD_CAP_ID_SHIFT 0 59305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define VPD_CAP_NEXT_PTR_MASK 0xFF 60305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define VPD_CAP_NEXT_PTR_SHIFT 8 61305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define VPD_CAP_VPD_ADDR_MASK 0x7FFF 62305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define VPD_CAP_VPD_ADDR_SHIFT 16 63305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define VPD_CAP_VPD_FLAG 0x80000000 64305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 65305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_VPD_DATA 0x70 66305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 67305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_SPI_FLASH_CTRL 0x200 68305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_STS_NON_RDY 0x1 69305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_STS_WEN 0x2 70305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_STS_WPEN 0x80 71305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF 72305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0 73305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_INS_MASK 0x7 74305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_INS_SHIFT 8 75305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_START 0x800 76305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_EN_VPD 0x2000 77305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_LDSTART 0x8000 78305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_CS_HI_MASK 0x3 79305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_CS_HI_SHIFT 16 80305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3 81305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18 82305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3 83305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20 84305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3 85305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22 86305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3 87305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24 88305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3 89305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26 90305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CTRL_WAIT_READY 0x10000000 91305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 92305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_SPI_ADDR 0x204 93305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 94305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_SPI_DATA 0x208 95305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 96305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_SPI_FLASH_CONFIG 0x20C 97305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF 98305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0 99305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3 100305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24 101305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000 102305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 103305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_SPI_FLASH_OP_PROGRAM 0x210 104305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_SPI_FLASH_OP_SC_ERASE 0x211 105305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212 106305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_SPI_FLASH_OP_RDID 0x213 107305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_SPI_FLASH_OP_WREN 0x214 108305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_SPI_FLASH_OP_RDSR 0x215 109305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_SPI_FLASH_OP_WRSR 0x216 110305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_SPI_FLASH_OP_READ 0x217 111305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 112305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_TWSI_CTRL 0x218 113305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_LD_OFFSET_MASK 0xFF 114305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_LD_OFFSET_SHIFT 0 115305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7 116305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8 117305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_SW_LDSTART 0x800 118305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_HW_LDSTART 0x1000 119305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x7F 120305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15 121305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_LD_EXIST 0x400000 122305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3 123305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23 124305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_FREQ_SEL_100K 0 125305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_FREQ_SEL_200K 1 126305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_FREQ_SEL_300K 2 127305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_FREQ_SEL_400K 3 128305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_SMB_SLV_ADDR /* FIXME: define or remove */ 129305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3 130305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24 131305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 132305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_PCIE_DEV_MISC_CTRL 0x21C 133305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2 134305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1 135305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4 136305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8 137305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10 138305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 139305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_PCIE_PHYMISC 0x1000 140305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define PCIE_PHYMISC_FORCE_RCV_DET 0x4 141305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 142305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_PCIE_DLL_TX_CTRL1 0x1104 143305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define PCIE_DLL_TX_CTRL1_SEL_NOR_CLK 0x400 144305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define PCIE_DLL_TX_CTRL1_DEF 0x568 145305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 146305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_LTSSM_TEST_MODE 0x12FC 147305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define LTSSM_TEST_MODE_DEF 0x6500 148305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 149305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* Master Control Register */ 150305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_MASTER_CTRL 0x1400 151305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MASTER_CTRL_SOFT_RST 0x1 152305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MASTER_CTRL_MTIMER_EN 0x2 153305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MASTER_CTRL_ITIMER_EN 0x4 154305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MASTER_CTRL_MANUAL_INT 0x8 155305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MASTER_CTRL_REV_NUM_SHIFT 16 156305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MASTER_CTRL_REV_NUM_MASK 0xFF 157305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MASTER_CTRL_DEV_ID_SHIFT 24 158305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MASTER_CTRL_DEV_ID_MASK 0xFF 159305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 160305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* Timer Initial Value Register */ 161305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_MANUAL_TIMER_INIT 0x1404 162305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 163305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* IRQ Moderator Timer Initial Value Register */ 164305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_IRQ_MODU_TIMER_INIT 0x1408 165305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 166305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_PHY_ENABLE 0x140C 167305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 168305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* IRQ Anti-Lost Timer Initial Value Register */ 169305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_CMBDISDMA_TIMER 0x140E 170305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 171305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* Block IDLE Status Register */ 172305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_IDLE_STATUS 0x1410 173305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 174305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* MDIO Control Register */ 175305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_MDIO_CTRL 0x1414 176305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_DATA_MASK 0xFFFF 177305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_DATA_SHIFT 0 178305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_REG_ADDR_MASK 0x1F 179305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_REG_ADDR_SHIFT 16 180305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_RW 0x200000 181305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_SUP_PREAMBLE 0x400000 182305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_START 0x800000 183305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_CLK_SEL_SHIFT 24 184305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_CLK_25_4 0 185305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_CLK_25_6 2 186305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_CLK_25_8 3 187305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_CLK_25_10 4 188305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_CLK_25_14 5 189305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_CLK_25_20 6 190305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_CLK_25_28 7 191305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MDIO_BUSY 0x8000000 192305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 193305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* MII PHY Status Register */ 194305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_PHY_STATUS 0x1418 195305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 196305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* BIST Control and Status Register0 (for the Packet Memory) */ 197305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_BIST0_CTRL 0x141C 198305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define BIST0_NOW 0x1 199305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define BIST0_SRAM_FAIL 0x2 200305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define BIST0_FUSE_FLAG 0x4 201305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_BIST1_CTRL 0x1420 202305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define BIST1_NOW 0x1 203305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define BIST1_SRAM_FAIL 0x2 204305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define BIST1_FUSE_FLAG 0x4 205305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 206305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* SerDes Lock Detect Control and Status Register */ 207305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_SERDES_LOCK 0x1424 208305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SERDES_LOCK_DETECT 1 209305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define SERDES_LOCK_DETECT_EN 2 210305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 211305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* MAC Control Register */ 212305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_MAC_CTRL 0x1480 213305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_TX_EN 1 214305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_RX_EN 2 215305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_TX_FLOW 4 216305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_RX_FLOW 8 217305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_LOOPBACK 0x10 218305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_DUPLX 0x20 219305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_ADD_CRC 0x40 220305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_PAD 0x80 221305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_LENCHK 0x100 222305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_HUGE_EN 0x200 223305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_PRMLEN_SHIFT 10 224305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_PRMLEN_MASK 0xF 225305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_RMV_VLAN 0x4000 226305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_PROMIS_EN 0x8000 227305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_MC_ALL_EN 0x2000000 228305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_CTRL_BC_EN 0x4000000 229305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 230305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* MAC IPG/IFG Control Register */ 231305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_MAC_IPG_IFG 0x1484 232305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_IPG_IFG_IPGT_SHIFT 0 233305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_IPG_IFG_IPGT_MASK 0x7F 234305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_IPG_IFG_MIFG_SHIFT 8 235305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_IPG_IFG_MIFG_MASK 0xFF 236305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_IPG_IFG_IPGR1_SHIFT 16 237305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_IPG_IFG_IPGR1_MASK 0x7F 238305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_IPG_IFG_IPGR2_SHIFT 24 239305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_IPG_IFG_IPGR2_MASK 0x7F 240305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 241305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* MAC STATION ADDRESS */ 242305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_MAC_STA_ADDR 0x1488 243305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 244305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* Hash table for multicast address */ 245305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_RX_HASH_TABLE 0x1490 246305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 247305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* MAC Half-Duplex Control Register */ 248305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_MAC_HALF_DUPLX_CTRL 0x1498 249305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 250305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3FF 251305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 252305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xF 253305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 254305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 255305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 256305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 257305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 258305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xF 259305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 260305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xF 261305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 262305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* Maximum Frame Length Control Register */ 263305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_MTU 0x149C 264305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 265305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* Wake-On-Lan control register */ 266305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_WOL_CTRL 0x14A0 267305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_PATTERN_EN 0x1 268305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_PATTERN_PME_EN 0x2 269305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_MAGIC_EN 0x4 270305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_MAGIC_PME_EN 0x8 271305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_LINK_CHG_EN 0x10 272305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_LINK_CHG_PME_EN 0x20 273305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_PATTERN_ST 0x100 274305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_MAGIC_ST 0x200 275305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_LINKCHG_ST 0x400 276305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_PT0_EN 0x10000 277305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_PT1_EN 0x20000 278305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_PT2_EN 0x40000 279305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_PT3_EN 0x80000 280305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_PT4_EN 0x100000 281305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_PT0_MATCH 0x1000000 282305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_PT1_MATCH 0x2000000 283305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_PT2_MATCH 0x4000000 284305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_PT3_MATCH 0x8000000 285305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define WOL_PT4_MATCH 0x10000000 286305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 287305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* Internal SRAM Partition Register, high 32 bits */ 288305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_SRAM_RFD_ADDR 0x1500 289305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 290305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* Descriptor Control register, high 32 bits */ 291305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_DESC_BASE_ADDR_HI 0x1540 292305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 293305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* Interrupt Status Register */ 294305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_ISR 0x1600 295305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ISR_UR_DETECTED 0x1000000 296305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ISR_FERR_DETECTED 0x2000000 297305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ISR_NFERR_DETECTED 0x4000000 298305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ISR_CERR_DETECTED 0x8000000 299305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ISR_PHY_LINKDOWN 0x10000000 300305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ISR_DIS_INT 0x80000000 301305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 302305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* Interrupt Mask Register */ 303305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_IMR 0x1604 304305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 305305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_RFD_RRD_IDX 0x1800 306305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define REG_TPD_IDX 0x1804 307305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 308305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* MII definitions */ 309305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 310305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* PHY Common Register */ 311305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_CR 0x09 312305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_SR 0x0A 313305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_ESR 0x0F 314305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR 0x10 315305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSSR 0x11 316305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 317305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* PHY Control Register */ 318305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 319305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 00=10 320305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn */ 321305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 322305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 323305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 324305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 325305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 326305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 327305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 328305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 00=10 329305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn */ 330305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 331305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 332305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_CR_SPEED_MASK 0x2040 333305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_CR_SPEED_1000 0x0040 334305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_CR_SPEED_100 0x2000 335305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_CR_SPEED_10 0x0000 336305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 337305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* PHY Status Register */ 338305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_EXTENDED_CAPS 0x0001 /* Ext register capabilities */ 339305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 340305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 341305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 342305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 343305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 344305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 345305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext stat info in Reg 0x0F */ 346305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 347305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 348305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 349305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 350305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 351305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 352305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 353305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 354305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* Link partner ability register */ 355305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_LPA_SLCT 0x001f /* Same as advertise selector */ 356305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ 357305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ 358305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ 359305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ 360305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */ 361305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_LPA_PAUSE 0x0400 /* PAUSE */ 362305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */ 363305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */ 364305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_LPA_LPACK 0x4000 /* Link partner acked us */ 365305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_LPA_NPAGE 0x8000 /* Next page bit */ 366305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 367305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* Autoneg Advertisement Register */ 368305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_AR_SELECTOR_FIELD 0x0001 /* IEEE 802.3 CSMA/CD */ 369305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 370305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 371305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 372305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 373305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 374305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_AR_PAUSE 0x0400 /* Pause operation desired */ 375305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Dir bit */ 376305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 377305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability support */ 378305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_AR_SPEED_MASK 0x01E0 379305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_AR_DEFAULT_CAP_MASK 0x0DE0 380305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 381305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* 1000BASE-T Control Register */ 382305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_CR_1000T_HD_CAPS 0x0100 /* Adv 1000T HD cap */ 383305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_CR_1000T_FD_CAPS 0x0200 /* Adv 1000T FD cap */ 384305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device, 385305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 0=DTE device */ 386305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_CR_1000T_MS_VALUE 0x0800 /* 1=Config PHY as Master, 387305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 0=Configure PHY as Slave */ 388305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_CR_1000T_MS_ENABLE 0x1000 /* 1=Man Master/Slave config, 389305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 0=Auto Master/Slave config 390305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn */ 391305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 392305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 393305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_CR_1000T_TEST_MODE_2 0x4000 /* Master Xmit Jitter test */ 394305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_CR_1000T_TEST_MODE_3 0x6000 /* Slave Xmit Jitter test */ 395305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_CR_1000T_TEST_MODE_4 0x8000 /* Xmitter Distortion test */ 396305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_CR_1000T_SPEED_MASK 0x0300 397305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_CR_1000T_DEFAULT_CAP_MASK 0x0300 398305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 399305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* 1000BASE-T Status Register */ 400305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 401305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 402305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 403305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 404305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master 405305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 0=Slave 406305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn */ 407305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config 408305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * fault */ 409305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_SR_1000T_REMOTE_RX_STATUS_SHIFT 12 410305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_SR_1000T_LOCAL_RX_STATUS_SHIFT 13 411305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 412305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* Extended Status Register */ 413305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 414305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 415305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 416305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 417305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 418305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* ATLX PHY Specific Control Register */ 419305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Func disabled */ 420305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enbld */ 421305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 422305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_MAC_POWERDOWN 0x0008 423305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low 424305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 0=CLK125 toggling 425305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn */ 426305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5, 427305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * Manual MDI configuration 428305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn */ 429305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 430305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover 431305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 100BASE-TX/10BASE-T: MDI 432305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * Mode */ 433305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled 434305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * all speeds. 435305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn */ 436305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE 0x0080 /* 1=Enable Extended 437305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 10BASE-T distance 438305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * (Lower 10BASE-T RX 439305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * Threshold) 440305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 0=Normal 10BASE-T RX 441305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * Threshold 442305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn */ 443305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_MII_5BIT_ENABLE 0x0100 /* 1=5-Bit interface in 444305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 100BASE-TX 445305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 0=MII interface in 446305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn * 100BASE-TX 447305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn */ 448305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler dsbl */ 449305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 450305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 451305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_POLARITY_REVERSAL_SHIFT 1 452305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_AUTO_X_MODE_SHIFT 5 453305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 454305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 455305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* ATLX PHY Specific Status Register */ 456305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 457305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 458305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 459305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSSR_10MBS 0x0000 /* 00=10Mbs */ 460305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSSR_100MBS 0x4000 /* 01=100Mbs */ 461305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define MII_ATLX_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 462305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 463ff772b27e5f65c1a186e9f0741f0d00ef7002799Jay Cliburn#define MII_DBG_ADDR 0x1D 464ff772b27e5f65c1a186e9f0741f0d00ef7002799Jay Cliburn#define MII_DBG_DATA 0x1E 465ff772b27e5f65c1a186e9f0741f0d00ef7002799Jay Cliburn 466305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* PCI Command Register Bit Definitions */ 467305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define PCI_REG_COMMAND 0x04 /* PCI Command Register */ 468305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define CMD_IO_SPACE 0x0001 469305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define CMD_MEMORY_SPACE 0x0002 470305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define CMD_BUS_MASTER 0x0004 471305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 472305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* Wake Up Filter Control */ 473305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ATLX_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 474305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ATLX_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 475305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ATLX_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 476305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ATLX_WUFC_MC 0x00000008 /* Multicast Wakeup Enable */ 477305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ATLX_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 478305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 479305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ADVERTISE_10_HALF 0x0001 480305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ADVERTISE_10_FULL 0x0002 481305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ADVERTISE_100_HALF 0x0004 482305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ADVERTISE_100_FULL 0x0008 483305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ADVERTISE_1000_HALF 0x0010 484305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define ADVERTISE_1000_FULL 0x0020 485305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds */ 486305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds */ 487305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 488305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 489305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define PHY_FORCE_TIME 20 /* 2.0 Seconds */ 490305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 491305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA */ 492305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define EEPROM_SUM 0xBABA 493305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#define NODE_ADDRESS_SIZE 6 494305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 495305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburnstruct atlx_spi_flash_dev { 496305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn const char *manu_name; /* manufacturer id */ 497305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn /* op-code */ 498305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn u8 cmd_wrsr; 499305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn u8 cmd_read; 500305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn u8 cmd_program; 501305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn u8 cmd_wren; 502305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn u8 cmd_wrdi; 503305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn u8 cmd_rdsr; 504305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn u8 cmd_rdid; 505305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn u8 cmd_sector_erase; 506305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn u8 cmd_chip_erase; 507305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn}; 508305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn 509305282ba19f81e571bd6d2dcc10ebb02e59a06efJay Cliburn#endif /* ATLX_H */ 510