bnx2x.h revision 0c23ad37a220b6a58b90e36203fe915c80dbd403 
1/* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14#ifndef BNX2X_H
15#define BNX2X_H
16
17#include <linux/pci.h>
18#include <linux/netdevice.h>
19#include <linux/dma-mapping.h>
20#include <linux/types.h>
21#include <linux/pci_regs.h>
22
23#include <linux/ptp_clock_kernel.h>
24#include <linux/net_tstamp.h>
25#include <linux/clocksource.h>
26
27/* compilation time flags */
28
29/* define this to make the driver freeze on error to allow getting debug info
30 * (you will need to reboot afterwards) */
31/* #define BNX2X_STOP_ON_ERROR */
32
33#define DRV_MODULE_VERSION      "1.78.19-0"
34#define DRV_MODULE_RELDATE      "2014/02/10"
35#define BNX2X_BC_VER            0x040200
36
37#if defined(CONFIG_DCB)
38#define BCM_DCBNL
39#endif
40
41#include "bnx2x_hsi.h"
42
43#include "../cnic_if.h"
44
45#define BNX2X_MIN_MSIX_VEC_CNT(bp)		((bp)->min_msix_vec_cnt)
46
47#include <linux/mdio.h>
48
49#include "bnx2x_reg.h"
50#include "bnx2x_fw_defs.h"
51#include "bnx2x_mfw_req.h"
52#include "bnx2x_link.h"
53#include "bnx2x_sp.h"
54#include "bnx2x_dcb.h"
55#include "bnx2x_stats.h"
56#include "bnx2x_vfpf.h"
57
58enum bnx2x_int_mode {
59	BNX2X_INT_MODE_MSIX,
60	BNX2X_INT_MODE_INTX,
61	BNX2X_INT_MODE_MSI
62};
63
64/* error/debug prints */
65
66#define DRV_MODULE_NAME		"bnx2x"
67
68/* for messages that are currently off */
69#define BNX2X_MSG_OFF			0x0
70#define BNX2X_MSG_MCP			0x0010000 /* was: NETIF_MSG_HW */
71#define BNX2X_MSG_STATS			0x0020000 /* was: NETIF_MSG_TIMER */
72#define BNX2X_MSG_NVM			0x0040000 /* was: NETIF_MSG_HW */
73#define BNX2X_MSG_DMAE			0x0080000 /* was: NETIF_MSG_HW */
74#define BNX2X_MSG_SP			0x0100000 /* was: NETIF_MSG_INTR */
75#define BNX2X_MSG_FP			0x0200000 /* was: NETIF_MSG_INTR */
76#define BNX2X_MSG_IOV			0x0800000
77#define BNX2X_MSG_PTP			0x1000000
78#define BNX2X_MSG_IDLE			0x2000000 /* used for idle check*/
79#define BNX2X_MSG_ETHTOOL		0x4000000
80#define BNX2X_MSG_DCB			0x8000000
81
82/* regular debug print */
83#define DP_INNER(fmt, ...)					\
84	pr_notice("[%s:%d(%s)]" fmt,				\
85		  __func__, __LINE__,				\
86		  bp->dev ? (bp->dev->name) : "?",		\
87		  ##__VA_ARGS__);
88
89#define DP(__mask, fmt, ...)					\
90do {								\
91	if (unlikely(bp->msg_enable & (__mask)))		\
92		DP_INNER(fmt, ##__VA_ARGS__);			\
93} while (0)
94
95#define DP_AND(__mask, fmt, ...)				\
96do {								\
97	if (unlikely((bp->msg_enable & (__mask)) == __mask))	\
98		DP_INNER(fmt, ##__VA_ARGS__);			\
99} while (0)
100
101#define DP_CONT(__mask, fmt, ...)				\
102do {								\
103	if (unlikely(bp->msg_enable & (__mask)))		\
104		pr_cont(fmt, ##__VA_ARGS__);			\
105} while (0)
106
107/* errors debug print */
108#define BNX2X_DBG_ERR(fmt, ...)					\
109do {								\
110	if (unlikely(netif_msg_probe(bp)))			\
111		pr_err("[%s:%d(%s)]" fmt,			\
112		       __func__, __LINE__,			\
113		       bp->dev ? (bp->dev->name) : "?",		\
114		       ##__VA_ARGS__);				\
115} while (0)
116
117/* for errors (never masked) */
118#define BNX2X_ERR(fmt, ...)					\
119do {								\
120	pr_err("[%s:%d(%s)]" fmt,				\
121	       __func__, __LINE__,				\
122	       bp->dev ? (bp->dev->name) : "?",			\
123	       ##__VA_ARGS__);					\
124} while (0)
125
126#define BNX2X_ERROR(fmt, ...)					\
127	pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
128
129/* before we have a dev->name use dev_info() */
130#define BNX2X_DEV_INFO(fmt, ...)				 \
131do {								 \
132	if (unlikely(netif_msg_probe(bp)))			 \
133		dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__);	 \
134} while (0)
135
136/* Error handling */
137void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
138#ifdef BNX2X_STOP_ON_ERROR
139#define bnx2x_panic()				\
140do {						\
141	bp->panic = 1;				\
142	BNX2X_ERR("driver assert\n");		\
143	bnx2x_panic_dump(bp, true);		\
144} while (0)
145#else
146#define bnx2x_panic()				\
147do {						\
148	bp->panic = 1;				\
149	BNX2X_ERR("driver assert\n");		\
150	bnx2x_panic_dump(bp, false);		\
151} while (0)
152#endif
153
154#define bnx2x_mc_addr(ha)      ((ha)->addr)
155#define bnx2x_uc_addr(ha)      ((ha)->addr)
156
157#define U64_LO(x)			((u32)(((u64)(x)) & 0xffffffff))
158#define U64_HI(x)			((u32)(((u64)(x)) >> 32))
159#define HILO_U64(hi, lo)		((((u64)(hi)) << 32) + (lo))
160
161#define REG_ADDR(bp, offset)		((bp->regview) + (offset))
162
163#define REG_RD(bp, offset)		readl(REG_ADDR(bp, offset))
164#define REG_RD8(bp, offset)		readb(REG_ADDR(bp, offset))
165#define REG_RD16(bp, offset)		readw(REG_ADDR(bp, offset))
166
167#define REG_WR(bp, offset, val)		writel((u32)val, REG_ADDR(bp, offset))
168#define REG_WR8(bp, offset, val)	writeb((u8)val, REG_ADDR(bp, offset))
169#define REG_WR16(bp, offset, val)	writew((u16)val, REG_ADDR(bp, offset))
170
171#define REG_RD_IND(bp, offset)		bnx2x_reg_rd_ind(bp, offset)
172#define REG_WR_IND(bp, offset, val)	bnx2x_reg_wr_ind(bp, offset, val)
173
174#define REG_RD_DMAE(bp, offset, valp, len32) \
175	do { \
176		bnx2x_read_dmae(bp, offset, len32);\
177		memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
178	} while (0)
179
180#define REG_WR_DMAE(bp, offset, valp, len32) \
181	do { \
182		memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
183		bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
184				 offset, len32); \
185	} while (0)
186
187#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
188	REG_WR_DMAE(bp, offset, valp, len32)
189
190#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
191	do { \
192		memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
193		bnx2x_write_big_buf_wb(bp, addr, len32); \
194	} while (0)
195
196#define SHMEM_ADDR(bp, field)		(bp->common.shmem_base + \
197					 offsetof(struct shmem_region, field))
198#define SHMEM_RD(bp, field)		REG_RD(bp, SHMEM_ADDR(bp, field))
199#define SHMEM_WR(bp, field, val)	REG_WR(bp, SHMEM_ADDR(bp, field), val)
200
201#define SHMEM2_ADDR(bp, field)		(bp->common.shmem2_base + \
202					 offsetof(struct shmem2_region, field))
203#define SHMEM2_RD(bp, field)		REG_RD(bp, SHMEM2_ADDR(bp, field))
204#define SHMEM2_WR(bp, field, val)	REG_WR(bp, SHMEM2_ADDR(bp, field), val)
205#define MF_CFG_ADDR(bp, field)		(bp->common.mf_cfg_base + \
206					 offsetof(struct mf_cfg, field))
207#define MF2_CFG_ADDR(bp, field)		(bp->common.mf2_cfg_base + \
208					 offsetof(struct mf2_cfg, field))
209
210#define MF_CFG_RD(bp, field)		REG_RD(bp, MF_CFG_ADDR(bp, field))
211#define MF_CFG_WR(bp, field, val)	REG_WR(bp,\
212					       MF_CFG_ADDR(bp, field), (val))
213#define MF2_CFG_RD(bp, field)		REG_RD(bp, MF2_CFG_ADDR(bp, field))
214
215#define SHMEM2_HAS(bp, field)		((bp)->common.shmem2_base &&	\
216					 (SHMEM2_RD((bp), size) >	\
217					 offsetof(struct shmem2_region, field)))
218
219#define EMAC_RD(bp, reg)		REG_RD(bp, emac_base + reg)
220#define EMAC_WR(bp, reg, val)		REG_WR(bp, emac_base + reg, val)
221
222/* SP SB indices */
223
224/* General SP events - stats query, cfc delete, etc  */
225#define HC_SP_INDEX_ETH_DEF_CONS		3
226
227/* EQ completions */
228#define HC_SP_INDEX_EQ_CONS			7
229
230/* FCoE L2 connection completions */
231#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS		6
232#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS		4
233/* iSCSI L2 */
234#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS		5
235#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS	1
236
237/* Special clients parameters */
238
239/* SB indices */
240/* FCoE L2 */
241#define BNX2X_FCOE_L2_RX_INDEX \
242	(&bp->def_status_blk->sp_sb.\
243	index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
244
245#define BNX2X_FCOE_L2_TX_INDEX \
246	(&bp->def_status_blk->sp_sb.\
247	index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
248
249/**
250 *  CIDs and CLIDs:
251 *  CLIDs below is a CLID for func 0, then the CLID for other
252 *  functions will be calculated by the formula:
253 *
254 *  FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
255 *
256 */
257enum {
258	BNX2X_ISCSI_ETH_CL_ID_IDX,
259	BNX2X_FCOE_ETH_CL_ID_IDX,
260	BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
261};
262
263/* use a value high enough to be above all the PFs, which has least significant
264 * nibble as 8, so when cnic needs to come up with a CID for UIO to use to
265 * calculate doorbell address according to old doorbell configuration scheme
266 * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number
267 * We must avoid coming up with cid 8 for iscsi since according to this method
268 * the designated UIO cid will come out 0 and it has a special handling for that
269 * case which doesn't suit us. Therefore will will cieling to closes cid which
270 * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18.
271 */
272
273#define BNX2X_1st_NON_L2_ETH_CID(bp)	(BNX2X_NUM_NON_CNIC_QUEUES(bp) * \
274					 (bp)->max_cos)
275/* amount of cids traversed by UIO's DPM addition to doorbell */
276#define UIO_DPM				8
277/* roundup to DPM offset */
278#define UIO_ROUNDUP(bp)			(roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \
279					 UIO_DPM))
280/* offset to nearest value which has lsb nibble matching DPM */
281#define UIO_CID_OFFSET(bp)		((UIO_ROUNDUP(bp) + UIO_DPM) % \
282					 (UIO_DPM * 2))
283/* add offset to rounded-up cid to get a value which could be used with UIO */
284#define UIO_DPM_ALIGN(bp)		(UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp))
285/* but wait - avoid UIO special case for cid 0 */
286#define UIO_DPM_CID0_OFFSET(bp)		((UIO_DPM * 2) * \
287					 (UIO_DPM_ALIGN(bp) == UIO_DPM))
288/* Properly DPM aligned CID dajusted to cid 0 secal case */
289#define BNX2X_CNIC_START_ETH_CID(bp)	(UIO_DPM_ALIGN(bp) + \
290					 (UIO_DPM_CID0_OFFSET(bp)))
291/* how many cids were wasted  - need this value for cid allocation */
292#define UIO_CID_PAD(bp)			(BNX2X_CNIC_START_ETH_CID(bp) - \
293					 BNX2X_1st_NON_L2_ETH_CID(bp))
294	/* iSCSI L2 */
295#define	BNX2X_ISCSI_ETH_CID(bp)		(BNX2X_CNIC_START_ETH_CID(bp))
296	/* FCoE L2 */
297#define	BNX2X_FCOE_ETH_CID(bp)		(BNX2X_CNIC_START_ETH_CID(bp) + 1)
298
299#define CNIC_SUPPORT(bp)		((bp)->cnic_support)
300#define CNIC_ENABLED(bp)		((bp)->cnic_enabled)
301#define CNIC_LOADED(bp)			((bp)->cnic_loaded)
302#define FCOE_INIT(bp)			((bp)->fcoe_init)
303
304#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
305	AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
306
307#define SM_RX_ID			0
308#define SM_TX_ID			1
309
310/* defines for multiple tx priority indices */
311#define FIRST_TX_ONLY_COS_INDEX		1
312#define FIRST_TX_COS_INDEX		0
313
314/* rules for calculating the cids of tx-only connections */
315#define CID_TO_FP(cid, bp)		((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
316#define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
317				(cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
318
319/* fp index inside class of service range */
320#define FP_COS_TO_TXQ(fp, cos, bp) \
321			((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
322
323/* Indexes for transmission queues array:
324 * txdata for RSS i CoS j is at location i + (j * num of RSS)
325 * txdata for FCoE (if exist) is at location max cos * num of RSS
326 * txdata for FWD (if exist) is one location after FCoE
327 * txdata for OOO (if exist) is one location after FWD
328 */
329enum {
330	FCOE_TXQ_IDX_OFFSET,
331	FWD_TXQ_IDX_OFFSET,
332	OOO_TXQ_IDX_OFFSET,
333};
334#define MAX_ETH_TXQ_IDX(bp)	(BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
335#define FCOE_TXQ_IDX(bp)	(MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
336
337/* fast path */
338/*
339 * This driver uses new build_skb() API :
340 * RX ring buffer contains pointer to kmalloc() data only,
341 * skb are built only after Hardware filled the frame.
342 */
343struct sw_rx_bd {
344	u8		*data;
345	DEFINE_DMA_UNMAP_ADDR(mapping);
346};
347
348struct sw_tx_bd {
349	struct sk_buff	*skb;
350	u16		first_bd;
351	u8		flags;
352/* Set on the first BD descriptor when there is a split BD */
353#define BNX2X_TSO_SPLIT_BD		(1<<0)
354#define BNX2X_HAS_SECOND_PBD		(1<<1)
355};
356
357struct sw_rx_page {
358	struct page	*page;
359	DEFINE_DMA_UNMAP_ADDR(mapping);
360};
361
362union db_prod {
363	struct doorbell_set_prod data;
364	u32		raw;
365};
366
367/* dropless fc FW/HW related params */
368#define BRB_SIZE(bp)		(CHIP_IS_E3(bp) ? 1024 : 512)
369#define MAX_AGG_QS(bp)		(CHIP_IS_E1(bp) ? \
370					ETH_MAX_AGGREGATION_QUEUES_E1 :\
371					ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
372#define FW_DROP_LEVEL(bp)	(3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
373#define FW_PREFETCH_CNT		16
374#define DROPLESS_FC_HEADROOM	100
375
376/* MC hsi */
377#define BCM_PAGE_SHIFT		12
378#define BCM_PAGE_SIZE		(1 << BCM_PAGE_SHIFT)
379#define BCM_PAGE_MASK		(~(BCM_PAGE_SIZE - 1))
380#define BCM_PAGE_ALIGN(addr)	(((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
381
382#define PAGES_PER_SGE_SHIFT	0
383#define PAGES_PER_SGE		(1 << PAGES_PER_SGE_SHIFT)
384#define SGE_PAGE_SIZE		PAGE_SIZE
385#define SGE_PAGE_SHIFT		PAGE_SHIFT
386#define SGE_PAGE_ALIGN(addr)	PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
387#define SGE_PAGES		(SGE_PAGE_SIZE * PAGES_PER_SGE)
388#define TPA_AGG_SIZE		min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
389					    SGE_PAGES), 0xffff)
390
391/* SGE ring related macros */
392#define NUM_RX_SGE_PAGES	2
393#define RX_SGE_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
394#define NEXT_PAGE_SGE_DESC_CNT	2
395#define MAX_RX_SGE_CNT		(RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
396/* RX_SGE_CNT is promised to be a power of 2 */
397#define RX_SGE_MASK		(RX_SGE_CNT - 1)
398#define NUM_RX_SGE		(RX_SGE_CNT * NUM_RX_SGE_PAGES)
399#define MAX_RX_SGE		(NUM_RX_SGE - 1)
400#define NEXT_SGE_IDX(x)		((((x) & RX_SGE_MASK) == \
401				  (MAX_RX_SGE_CNT - 1)) ? \
402					(x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
403					(x) + 1)
404#define RX_SGE(x)		((x) & MAX_RX_SGE)
405
406/*
407 * Number of required  SGEs is the sum of two:
408 * 1. Number of possible opened aggregations (next packet for
409 *    these aggregations will probably consume SGE immediately)
410 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
411 *    after placement on BD for new TPA aggregation)
412 *
413 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
414 */
415#define NUM_SGE_REQ		(MAX_AGG_QS(bp) + \
416					(BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
417#define NUM_SGE_PG_REQ		((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
418						MAX_RX_SGE_CNT)
419#define SGE_TH_LO(bp)		(NUM_SGE_REQ + \
420				 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
421#define SGE_TH_HI(bp)		(SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
422
423/* Manipulate a bit vector defined as an array of u64 */
424
425/* Number of bits in one sge_mask array element */
426#define BIT_VEC64_ELEM_SZ		64
427#define BIT_VEC64_ELEM_SHIFT		6
428#define BIT_VEC64_ELEM_MASK		((u64)BIT_VEC64_ELEM_SZ - 1)
429
430#define __BIT_VEC64_SET_BIT(el, bit) \
431	do { \
432		el = ((el) | ((u64)0x1 << (bit))); \
433	} while (0)
434
435#define __BIT_VEC64_CLEAR_BIT(el, bit) \
436	do { \
437		el = ((el) & (~((u64)0x1 << (bit)))); \
438	} while (0)
439
440#define BIT_VEC64_SET_BIT(vec64, idx) \
441	__BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
442			   (idx) & BIT_VEC64_ELEM_MASK)
443
444#define BIT_VEC64_CLEAR_BIT(vec64, idx) \
445	__BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
446			     (idx) & BIT_VEC64_ELEM_MASK)
447
448#define BIT_VEC64_TEST_BIT(vec64, idx) \
449	(((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
450	((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
451
452/* Creates a bitmask of all ones in less significant bits.
453   idx - index of the most significant bit in the created mask */
454#define BIT_VEC64_ONES_MASK(idx) \
455		(((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
456#define BIT_VEC64_ELEM_ONE_MASK	((u64)(~0))
457
458/*******************************************************/
459
460/* Number of u64 elements in SGE mask array */
461#define RX_SGE_MASK_LEN			(NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
462#define RX_SGE_MASK_LEN_MASK		(RX_SGE_MASK_LEN - 1)
463#define NEXT_SGE_MASK_ELEM(el)		(((el) + 1) & RX_SGE_MASK_LEN_MASK)
464
465union host_hc_status_block {
466	/* pointer to fp status block e1x */
467	struct host_hc_status_block_e1x *e1x_sb;
468	/* pointer to fp status block e2 */
469	struct host_hc_status_block_e2  *e2_sb;
470};
471
472struct bnx2x_agg_info {
473	/*
474	 * First aggregation buffer is a data buffer, the following - are pages.
475	 * We will preallocate the data buffer for each aggregation when
476	 * we open the interface and will replace the BD at the consumer
477	 * with this one when we receive the TPA_START CQE in order to
478	 * keep the Rx BD ring consistent.
479	 */
480	struct sw_rx_bd		first_buf;
481	u8			tpa_state;
482#define BNX2X_TPA_START			1
483#define BNX2X_TPA_STOP			2
484#define BNX2X_TPA_ERROR			3
485	u8			placement_offset;
486	u16			parsing_flags;
487	u16			vlan_tag;
488	u16			len_on_bd;
489	u32			rxhash;
490	enum pkt_hash_types	rxhash_type;
491	u16			gro_size;
492	u16			full_page;
493};
494
495#define Q_STATS_OFFSET32(stat_name) \
496			(offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
497
498struct bnx2x_fp_txdata {
499
500	struct sw_tx_bd		*tx_buf_ring;
501
502	union eth_tx_bd_types	*tx_desc_ring;
503	dma_addr_t		tx_desc_mapping;
504
505	u32			cid;
506
507	union db_prod		tx_db;
508
509	u16			tx_pkt_prod;
510	u16			tx_pkt_cons;
511	u16			tx_bd_prod;
512	u16			tx_bd_cons;
513
514	unsigned long		tx_pkt;
515
516	__le16			*tx_cons_sb;
517
518	int			txq_index;
519	struct bnx2x_fastpath	*parent_fp;
520	int			tx_ring_size;
521};
522
523enum bnx2x_tpa_mode_t {
524	TPA_MODE_LRO,
525	TPA_MODE_GRO
526};
527
528struct bnx2x_fastpath {
529	struct bnx2x		*bp; /* parent */
530
531	struct napi_struct	napi;
532
533#ifdef CONFIG_NET_RX_BUSY_POLL
534	unsigned int state;
535#define BNX2X_FP_STATE_IDLE		      0
536#define BNX2X_FP_STATE_NAPI		(1 << 0)    /* NAPI owns this FP */
537#define BNX2X_FP_STATE_POLL		(1 << 1)    /* poll owns this FP */
538#define BNX2X_FP_STATE_DISABLED		(1 << 2)
539#define BNX2X_FP_STATE_NAPI_YIELD	(1 << 3)    /* NAPI yielded this FP */
540#define BNX2X_FP_STATE_POLL_YIELD	(1 << 4)    /* poll yielded this FP */
541#define BNX2X_FP_OWNED	(BNX2X_FP_STATE_NAPI | BNX2X_FP_STATE_POLL)
542#define BNX2X_FP_YIELD	(BNX2X_FP_STATE_NAPI_YIELD | BNX2X_FP_STATE_POLL_YIELD)
543#define BNX2X_FP_LOCKED	(BNX2X_FP_OWNED | BNX2X_FP_STATE_DISABLED)
544#define BNX2X_FP_USER_PEND (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_POLL_YIELD)
545	/* protect state */
546	spinlock_t lock;
547#endif /* CONFIG_NET_RX_BUSY_POLL */
548
549	union host_hc_status_block	status_blk;
550	/* chip independent shortcuts into sb structure */
551	__le16			*sb_index_values;
552	__le16			*sb_running_index;
553	/* chip independent shortcut into rx_prods_offset memory */
554	u32			ustorm_rx_prods_offset;
555
556	u32			rx_buf_size;
557	u32			rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
558	dma_addr_t		status_blk_mapping;
559
560	enum bnx2x_tpa_mode_t	mode;
561
562	u8			max_cos; /* actual number of active tx coses */
563	struct bnx2x_fp_txdata	*txdata_ptr[BNX2X_MULTI_TX_COS];
564
565	struct sw_rx_bd		*rx_buf_ring;	/* BDs mappings ring */
566	struct sw_rx_page	*rx_page_ring;	/* SGE pages mappings ring */
567
568	struct eth_rx_bd	*rx_desc_ring;
569	dma_addr_t		rx_desc_mapping;
570
571	union eth_rx_cqe	*rx_comp_ring;
572	dma_addr_t		rx_comp_mapping;
573
574	/* SGE ring */
575	struct eth_rx_sge	*rx_sge_ring;
576	dma_addr_t		rx_sge_mapping;
577
578	u64			sge_mask[RX_SGE_MASK_LEN];
579
580	u32			cid;
581
582	__le16			fp_hc_idx;
583
584	u8			index;		/* number in fp array */
585	u8			rx_queue;	/* index for skb_record */
586	u8			cl_id;		/* eth client id */
587	u8			cl_qzone_id;
588	u8			fw_sb_id;	/* status block number in FW */
589	u8			igu_sb_id;	/* status block number in HW */
590
591	u16			rx_bd_prod;
592	u16			rx_bd_cons;
593	u16			rx_comp_prod;
594	u16			rx_comp_cons;
595	u16			rx_sge_prod;
596	/* The last maximal completed SGE */
597	u16			last_max_sge;
598	__le16			*rx_cons_sb;
599	unsigned long		rx_pkt,
600				rx_calls;
601
602	/* TPA related */
603	struct bnx2x_agg_info	*tpa_info;
604	u8			disable_tpa;
605#ifdef BNX2X_STOP_ON_ERROR
606	u64			tpa_queue_used;
607#endif
608	/* The size is calculated using the following:
609	     sizeof name field from netdev structure +
610	     4 ('-Xx-' string) +
611	     4 (for the digits and to make it DWORD aligned) */
612#define FP_NAME_SIZE		(sizeof(((struct net_device *)0)->name) + 8)
613	char			name[FP_NAME_SIZE];
614};
615
616#define bnx2x_fp(bp, nr, var)	((bp)->fp[(nr)].var)
617#define bnx2x_sp_obj(bp, fp)	((bp)->sp_objs[(fp)->index])
618#define bnx2x_fp_stats(bp, fp)	(&((bp)->fp_stats[(fp)->index]))
619#define bnx2x_fp_qstats(bp, fp)	(&((bp)->fp_stats[(fp)->index].eth_q_stats))
620
621#ifdef CONFIG_NET_RX_BUSY_POLL
622static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp)
623{
624	spin_lock_init(&fp->lock);
625	fp->state = BNX2X_FP_STATE_IDLE;
626}
627
628/* called from the device poll routine to get ownership of a FP */
629static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp)
630{
631	bool rc = true;
632
633	spin_lock_bh(&fp->lock);
634	if (fp->state & BNX2X_FP_LOCKED) {
635		WARN_ON(fp->state & BNX2X_FP_STATE_NAPI);
636		fp->state |= BNX2X_FP_STATE_NAPI_YIELD;
637		rc = false;
638	} else {
639		/* we don't care if someone yielded */
640		fp->state = BNX2X_FP_STATE_NAPI;
641	}
642	spin_unlock_bh(&fp->lock);
643	return rc;
644}
645
646/* returns true is someone tried to get the FP while napi had it */
647static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp)
648{
649	bool rc = false;
650
651	spin_lock_bh(&fp->lock);
652	WARN_ON(fp->state &
653		(BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_NAPI_YIELD));
654
655	if (fp->state & BNX2X_FP_STATE_POLL_YIELD)
656		rc = true;
657
658	/* state ==> idle, unless currently disabled */
659	fp->state &= BNX2X_FP_STATE_DISABLED;
660	spin_unlock_bh(&fp->lock);
661	return rc;
662}
663
664/* called from bnx2x_low_latency_poll() */
665static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp)
666{
667	bool rc = true;
668
669	spin_lock_bh(&fp->lock);
670	if ((fp->state & BNX2X_FP_LOCKED)) {
671		fp->state |= BNX2X_FP_STATE_POLL_YIELD;
672		rc = false;
673	} else {
674		/* preserve yield marks */
675		fp->state |= BNX2X_FP_STATE_POLL;
676	}
677	spin_unlock_bh(&fp->lock);
678	return rc;
679}
680
681/* returns true if someone tried to get the FP while it was locked */
682static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp)
683{
684	bool rc = false;
685
686	spin_lock_bh(&fp->lock);
687	WARN_ON(fp->state & BNX2X_FP_STATE_NAPI);
688
689	if (fp->state & BNX2X_FP_STATE_POLL_YIELD)
690		rc = true;
691
692	/* state ==> idle, unless currently disabled */
693	fp->state &= BNX2X_FP_STATE_DISABLED;
694	spin_unlock_bh(&fp->lock);
695	return rc;
696}
697
698/* true if a socket is polling, even if it did not get the lock */
699static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp)
700{
701	WARN_ON(!(fp->state & BNX2X_FP_OWNED));
702	return fp->state & BNX2X_FP_USER_PEND;
703}
704
705/* false if fp is currently owned */
706static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp)
707{
708	int rc = true;
709
710	spin_lock_bh(&fp->lock);
711	if (fp->state & BNX2X_FP_OWNED)
712		rc = false;
713	fp->state |= BNX2X_FP_STATE_DISABLED;
714	spin_unlock_bh(&fp->lock);
715
716	return rc;
717}
718#else
719static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp)
720{
721}
722
723static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp)
724{
725	return true;
726}
727
728static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp)
729{
730	return false;
731}
732
733static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp)
734{
735	return false;
736}
737
738static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp)
739{
740	return false;
741}
742
743static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp)
744{
745	return false;
746}
747static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp)
748{
749	return true;
750}
751#endif /* CONFIG_NET_RX_BUSY_POLL */
752
753/* Use 2500 as a mini-jumbo MTU for FCoE */
754#define BNX2X_FCOE_MINI_JUMBO_MTU	2500
755
756#define	FCOE_IDX_OFFSET		0
757
758#define FCOE_IDX(bp)		(BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
759				 FCOE_IDX_OFFSET)
760#define bnx2x_fcoe_fp(bp)	(&bp->fp[FCOE_IDX(bp)])
761#define bnx2x_fcoe(bp, var)	(bnx2x_fcoe_fp(bp)->var)
762#define bnx2x_fcoe_inner_sp_obj(bp)	(&bp->sp_objs[FCOE_IDX(bp)])
763#define bnx2x_fcoe_sp_obj(bp, var)	(bnx2x_fcoe_inner_sp_obj(bp)->var)
764#define bnx2x_fcoe_tx(bp, var)	(bnx2x_fcoe_fp(bp)-> \
765						txdata_ptr[FIRST_TX_COS_INDEX] \
766						->var)
767
768#define IS_ETH_FP(fp)		((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
769#define IS_FCOE_FP(fp)		((fp)->index == FCOE_IDX((fp)->bp))
770#define IS_FCOE_IDX(idx)	((idx) == FCOE_IDX(bp))
771
772/* MC hsi */
773#define MAX_FETCH_BD		13	/* HW max BDs per packet */
774#define RX_COPY_THRESH		92
775
776#define NUM_TX_RINGS		16
777#define TX_DESC_CNT		(BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
778#define NEXT_PAGE_TX_DESC_CNT	1
779#define MAX_TX_DESC_CNT		(TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
780#define NUM_TX_BD		(TX_DESC_CNT * NUM_TX_RINGS)
781#define MAX_TX_BD		(NUM_TX_BD - 1)
782#define MAX_TX_AVAIL		(MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
783#define NEXT_TX_IDX(x)		((((x) & MAX_TX_DESC_CNT) == \
784				  (MAX_TX_DESC_CNT - 1)) ? \
785					(x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
786					(x) + 1)
787#define TX_BD(x)		((x) & MAX_TX_BD)
788#define TX_BD_POFF(x)		((x) & MAX_TX_DESC_CNT)
789
790/* number of NEXT_PAGE descriptors may be required during placement */
791#define NEXT_CNT_PER_TX_PKT(bds)	\
792				(((bds) + MAX_TX_DESC_CNT - 1) / \
793				 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
794/* max BDs per tx packet w/o next_pages:
795 * START_BD		- describes packed
796 * START_BD(splitted)	- includes unpaged data segment for GSO
797 * PARSING_BD		- for TSO and CSUM data
798 * PARSING_BD2		- for encapsulation data
799 * Frag BDs		- describes pages for frags
800 */
801#define BDS_PER_TX_PKT		4
802#define MAX_BDS_PER_TX_PKT	(MAX_SKB_FRAGS + BDS_PER_TX_PKT)
803/* max BDs per tx packet including next pages */
804#define MAX_DESC_PER_TX_PKT	(MAX_BDS_PER_TX_PKT + \
805				 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
806
807/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
808#define NUM_RX_RINGS		8
809#define RX_DESC_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
810#define NEXT_PAGE_RX_DESC_CNT	2
811#define MAX_RX_DESC_CNT		(RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
812#define RX_DESC_MASK		(RX_DESC_CNT - 1)
813#define NUM_RX_BD		(RX_DESC_CNT * NUM_RX_RINGS)
814#define MAX_RX_BD		(NUM_RX_BD - 1)
815#define MAX_RX_AVAIL		(MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
816
817/* dropless fc calculations for BDs
818 *
819 * Number of BDs should as number of buffers in BRB:
820 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
821 * "next" elements on each page
822 */
823#define NUM_BD_REQ		BRB_SIZE(bp)
824#define NUM_BD_PG_REQ		((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
825					      MAX_RX_DESC_CNT)
826#define BD_TH_LO(bp)		(NUM_BD_REQ + \
827				 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
828				 FW_DROP_LEVEL(bp))
829#define BD_TH_HI(bp)		(BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
830
831#define MIN_RX_AVAIL		((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
832
833#define MIN_RX_SIZE_TPA_HW	(CHIP_IS_E1(bp) ? \
834					ETH_MIN_RX_CQES_WITH_TPA_E1 : \
835					ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
836#define MIN_RX_SIZE_NONTPA_HW   ETH_MIN_RX_CQES_WITHOUT_TPA
837#define MIN_RX_SIZE_TPA		(max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
838#define MIN_RX_SIZE_NONTPA	(max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
839								MIN_RX_AVAIL))
840
841#define NEXT_RX_IDX(x)		((((x) & RX_DESC_MASK) == \
842				  (MAX_RX_DESC_CNT - 1)) ? \
843					(x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
844					(x) + 1)
845#define RX_BD(x)		((x) & MAX_RX_BD)
846
847/*
848 * As long as CQE is X times bigger than BD entry we have to allocate X times
849 * more pages for CQ ring in order to keep it balanced with BD ring
850 */
851#define CQE_BD_REL	(sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
852#define NUM_RCQ_RINGS		(NUM_RX_RINGS * CQE_BD_REL)
853#define RCQ_DESC_CNT		(BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
854#define NEXT_PAGE_RCQ_DESC_CNT	1
855#define MAX_RCQ_DESC_CNT	(RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
856#define NUM_RCQ_BD		(RCQ_DESC_CNT * NUM_RCQ_RINGS)
857#define MAX_RCQ_BD		(NUM_RCQ_BD - 1)
858#define MAX_RCQ_AVAIL		(MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
859#define NEXT_RCQ_IDX(x)		((((x) & MAX_RCQ_DESC_CNT) == \
860				  (MAX_RCQ_DESC_CNT - 1)) ? \
861					(x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
862					(x) + 1)
863#define RCQ_BD(x)		((x) & MAX_RCQ_BD)
864
865/* dropless fc calculations for RCQs
866 *
867 * Number of RCQs should be as number of buffers in BRB:
868 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
869 * "next" elements on each page
870 */
871#define NUM_RCQ_REQ		BRB_SIZE(bp)
872#define NUM_RCQ_PG_REQ		((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
873					      MAX_RCQ_DESC_CNT)
874#define RCQ_TH_LO(bp)		(NUM_RCQ_REQ + \
875				 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
876				 FW_DROP_LEVEL(bp))
877#define RCQ_TH_HI(bp)		(RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
878
879/* This is needed for determining of last_max */
880#define SUB_S16(a, b)		(s16)((s16)(a) - (s16)(b))
881#define SUB_S32(a, b)		(s32)((s32)(a) - (s32)(b))
882
883#define BNX2X_SWCID_SHIFT	17
884#define BNX2X_SWCID_MASK	((0x1 << BNX2X_SWCID_SHIFT) - 1)
885
886/* used on a CID received from the HW */
887#define SW_CID(x)			(le32_to_cpu(x) & BNX2X_SWCID_MASK)
888#define CQE_CMD(x)			(le32_to_cpu(x) >> \
889					COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
890
891#define BD_UNMAP_ADDR(bd)		HILO_U64(le32_to_cpu((bd)->addr_hi), \
892						 le32_to_cpu((bd)->addr_lo))
893#define BD_UNMAP_LEN(bd)		(le16_to_cpu((bd)->nbytes))
894
895#define BNX2X_DB_MIN_SHIFT		3	/* 8 bytes */
896#define BNX2X_DB_SHIFT			3	/* 8 bytes*/
897#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
898#error "Min DB doorbell stride is 8"
899#endif
900#define DOORBELL(bp, cid, val) \
901	do { \
902		writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \
903	} while (0)
904
905/* TX CSUM helpers */
906#define SKB_CS_OFF(skb)		(offsetof(struct tcphdr, check) - \
907				 skb->csum_offset)
908#define SKB_CS(skb)		(*(u16 *)(skb_transport_header(skb) + \
909					  skb->csum_offset))
910
911#define pbd_tcp_flags(tcp_hdr)	(ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff)
912
913#define XMIT_PLAIN		0
914#define XMIT_CSUM_V4		(1 << 0)
915#define XMIT_CSUM_V6		(1 << 1)
916#define XMIT_CSUM_TCP		(1 << 2)
917#define XMIT_GSO_V4		(1 << 3)
918#define XMIT_GSO_V6		(1 << 4)
919#define XMIT_CSUM_ENC_V4	(1 << 5)
920#define XMIT_CSUM_ENC_V6	(1 << 6)
921#define XMIT_GSO_ENC_V4		(1 << 7)
922#define XMIT_GSO_ENC_V6		(1 << 8)
923
924#define XMIT_CSUM_ENC		(XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6)
925#define XMIT_GSO_ENC		(XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6)
926
927#define XMIT_CSUM		(XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC)
928#define XMIT_GSO		(XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC)
929
930/* stuff added to make the code fit 80Col */
931#define CQE_TYPE(cqe_fp_flags)	 ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
932#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
933#define CQE_TYPE_STOP(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
934#define CQE_TYPE_SLOW(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
935#define CQE_TYPE_FAST(cqe_type)  ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
936
937#define ETH_RX_ERROR_FALGS		ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
938
939#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
940				(((le16_to_cpu(flags) & \
941				   PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
942				  PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
943				 == PRS_FLAG_OVERETH_IPV4)
944#define BNX2X_RX_SUM_FIX(cqe) \
945	BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
946
947#define FP_USB_FUNC_OFF	\
948			offsetof(struct cstorm_status_block_u, func)
949#define FP_CSB_FUNC_OFF	\
950			offsetof(struct cstorm_status_block_c, func)
951
952#define HC_INDEX_ETH_RX_CQ_CONS		1
953
954#define HC_INDEX_OOO_TX_CQ_CONS		4
955
956#define HC_INDEX_ETH_TX_CQ_CONS_COS0	5
957
958#define HC_INDEX_ETH_TX_CQ_CONS_COS1	6
959
960#define HC_INDEX_ETH_TX_CQ_CONS_COS2	7
961
962#define HC_INDEX_ETH_FIRST_TX_CQ_CONS	HC_INDEX_ETH_TX_CQ_CONS_COS0
963
964#define BNX2X_RX_SB_INDEX \
965	(&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
966
967#define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
968
969#define BNX2X_TX_SB_INDEX_COS0 \
970	(&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
971
972/* end of fast path */
973
974/* common */
975
976struct bnx2x_common {
977
978	u32			chip_id;
979/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
980#define CHIP_ID(bp)			(bp->common.chip_id & 0xfffffff0)
981
982#define CHIP_NUM(bp)			(bp->common.chip_id >> 16)
983#define CHIP_NUM_57710			0x164e
984#define CHIP_NUM_57711			0x164f
985#define CHIP_NUM_57711E			0x1650
986#define CHIP_NUM_57712			0x1662
987#define CHIP_NUM_57712_MF		0x1663
988#define CHIP_NUM_57712_VF		0x166f
989#define CHIP_NUM_57713			0x1651
990#define CHIP_NUM_57713E			0x1652
991#define CHIP_NUM_57800			0x168a
992#define CHIP_NUM_57800_MF		0x16a5
993#define CHIP_NUM_57800_VF		0x16a9
994#define CHIP_NUM_57810			0x168e
995#define CHIP_NUM_57810_MF		0x16ae
996#define CHIP_NUM_57810_VF		0x16af
997#define CHIP_NUM_57811			0x163d
998#define CHIP_NUM_57811_MF		0x163e
999#define CHIP_NUM_57811_VF		0x163f
1000#define CHIP_NUM_57840_OBSOLETE		0x168d
1001#define CHIP_NUM_57840_MF_OBSOLETE	0x16ab
1002#define CHIP_NUM_57840_4_10		0x16a1
1003#define CHIP_NUM_57840_2_20		0x16a2
1004#define CHIP_NUM_57840_MF		0x16a4
1005#define CHIP_NUM_57840_VF		0x16ad
1006#define CHIP_IS_E1(bp)			(CHIP_NUM(bp) == CHIP_NUM_57710)
1007#define CHIP_IS_57711(bp)		(CHIP_NUM(bp) == CHIP_NUM_57711)
1008#define CHIP_IS_57711E(bp)		(CHIP_NUM(bp) == CHIP_NUM_57711E)
1009#define CHIP_IS_57712(bp)		(CHIP_NUM(bp) == CHIP_NUM_57712)
1010#define CHIP_IS_57712_VF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57712_VF)
1011#define CHIP_IS_57712_MF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57712_MF)
1012#define CHIP_IS_57800(bp)		(CHIP_NUM(bp) == CHIP_NUM_57800)
1013#define CHIP_IS_57800_MF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57800_MF)
1014#define CHIP_IS_57800_VF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57800_VF)
1015#define CHIP_IS_57810(bp)		(CHIP_NUM(bp) == CHIP_NUM_57810)
1016#define CHIP_IS_57810_MF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57810_MF)
1017#define CHIP_IS_57810_VF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57810_VF)
1018#define CHIP_IS_57811(bp)		(CHIP_NUM(bp) == CHIP_NUM_57811)
1019#define CHIP_IS_57811_MF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57811_MF)
1020#define CHIP_IS_57811_VF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57811_VF)
1021#define CHIP_IS_57840(bp)		\
1022		((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
1023		 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
1024		 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
1025#define CHIP_IS_57840_MF(bp)	((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
1026				 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
1027#define CHIP_IS_57840_VF(bp)		(CHIP_NUM(bp) == CHIP_NUM_57840_VF)
1028#define CHIP_IS_E1H(bp)			(CHIP_IS_57711(bp) || \
1029					 CHIP_IS_57711E(bp))
1030#define CHIP_IS_57811xx(bp)		(CHIP_IS_57811(bp) || \
1031					 CHIP_IS_57811_MF(bp) || \
1032					 CHIP_IS_57811_VF(bp))
1033#define CHIP_IS_E2(bp)			(CHIP_IS_57712(bp) || \
1034					 CHIP_IS_57712_MF(bp) || \
1035					 CHIP_IS_57712_VF(bp))
1036#define CHIP_IS_E3(bp)			(CHIP_IS_57800(bp) || \
1037					 CHIP_IS_57800_MF(bp) || \
1038					 CHIP_IS_57800_VF(bp) || \
1039					 CHIP_IS_57810(bp) || \
1040					 CHIP_IS_57810_MF(bp) || \
1041					 CHIP_IS_57810_VF(bp) || \
1042					 CHIP_IS_57811xx(bp) || \
1043					 CHIP_IS_57840(bp) || \
1044					 CHIP_IS_57840_MF(bp) || \
1045					 CHIP_IS_57840_VF(bp))
1046#define CHIP_IS_E1x(bp)			(CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
1047#define USES_WARPCORE(bp)		(CHIP_IS_E3(bp))
1048#define IS_E1H_OFFSET			(!CHIP_IS_E1(bp))
1049
1050#define CHIP_REV_SHIFT			12
1051#define CHIP_REV_MASK			(0xF << CHIP_REV_SHIFT)
1052#define CHIP_REV_VAL(bp)		(bp->common.chip_id & CHIP_REV_MASK)
1053#define CHIP_REV_Ax			(0x0 << CHIP_REV_SHIFT)
1054#define CHIP_REV_Bx			(0x1 << CHIP_REV_SHIFT)
1055/* assume maximum 5 revisions */
1056#define CHIP_REV_IS_SLOW(bp)		(CHIP_REV_VAL(bp) > 0x00005000)
1057/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
1058#define CHIP_REV_IS_EMUL(bp)		((CHIP_REV_IS_SLOW(bp)) && \
1059					 !(CHIP_REV_VAL(bp) & 0x00001000))
1060/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
1061#define CHIP_REV_IS_FPGA(bp)		((CHIP_REV_IS_SLOW(bp)) && \
1062					 (CHIP_REV_VAL(bp) & 0x00001000))
1063
1064#define CHIP_TIME(bp)			((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
1065					((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
1066
1067#define CHIP_METAL(bp)			(bp->common.chip_id & 0x00000ff0)
1068#define CHIP_BOND_ID(bp)		(bp->common.chip_id & 0x0000000f)
1069#define CHIP_REV_SIM(bp)		(((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
1070					   (CHIP_REV_SHIFT + 1)) \
1071						<< CHIP_REV_SHIFT)
1072#define CHIP_REV(bp)			(CHIP_REV_IS_SLOW(bp) ? \
1073						CHIP_REV_SIM(bp) :\
1074						CHIP_REV_VAL(bp))
1075#define CHIP_IS_E3B0(bp)		(CHIP_IS_E3(bp) && \
1076					 (CHIP_REV(bp) == CHIP_REV_Bx))
1077#define CHIP_IS_E3A0(bp)		(CHIP_IS_E3(bp) && \
1078					 (CHIP_REV(bp) == CHIP_REV_Ax))
1079/* This define is used in two main places:
1080 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher
1081 * to nic-only mode or to offload mode. Offload mode is configured if either the
1082 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
1083 * registered for this port (which means that the user wants storage services).
1084 * 2. During cnic-related load, to know if offload mode is already configured in
1085 * the HW or needs to be configured.
1086 * Since the transition from nic-mode to offload-mode in HW causes traffic
1087 * corruption, nic-mode is configured only in ports on which storage services
1088 * where never requested.
1089 */
1090#define CONFIGURE_NIC_MODE(bp)		(!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
1091
1092	int			flash_size;
1093#define BNX2X_NVRAM_1MB_SIZE			0x20000	/* 1M bit in bytes */
1094#define BNX2X_NVRAM_TIMEOUT_COUNT		30000
1095#define BNX2X_NVRAM_PAGE_SIZE			256
1096
1097	u32			shmem_base;
1098	u32			shmem2_base;
1099	u32			mf_cfg_base;
1100	u32			mf2_cfg_base;
1101
1102	u32			hw_config;
1103
1104	u32			bc_ver;
1105
1106	u8			int_block;
1107#define INT_BLOCK_HC			0
1108#define INT_BLOCK_IGU			1
1109#define INT_BLOCK_MODE_NORMAL		0
1110#define INT_BLOCK_MODE_BW_COMP		2
1111#define CHIP_INT_MODE_IS_NBC(bp)		\
1112			(!CHIP_IS_E1x(bp) &&	\
1113			!((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
1114#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
1115
1116	u8			chip_port_mode;
1117#define CHIP_4_PORT_MODE			0x0
1118#define CHIP_2_PORT_MODE			0x1
1119#define CHIP_PORT_MODE_NONE			0x2
1120#define CHIP_MODE(bp)			(bp->common.chip_port_mode)
1121#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
1122
1123	u32			boot_mode;
1124};
1125
1126/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
1127#define BNX2X_IGU_STAS_MSG_VF_CNT 64
1128#define BNX2X_IGU_STAS_MSG_PF_CNT 4
1129
1130#define MAX_IGU_ATTN_ACK_TO       100
1131/* end of common */
1132
1133/* port */
1134
1135struct bnx2x_port {
1136	u32			pmf;
1137
1138	u32			link_config[LINK_CONFIG_SIZE];
1139
1140	u32			supported[LINK_CONFIG_SIZE];
1141/* link settings - missing defines */
1142#define SUPPORTED_2500baseX_Full	(1 << 15)
1143
1144	u32			advertising[LINK_CONFIG_SIZE];
1145/* link settings - missing defines */
1146#define ADVERTISED_2500baseX_Full	(1 << 15)
1147
1148	u32			phy_addr;
1149
1150	/* used to synchronize phy accesses */
1151	struct mutex		phy_mutex;
1152
1153	u32			port_stx;
1154
1155	struct nig_stats	old_nig_stats;
1156};
1157
1158/* end of port */
1159
1160#define STATS_OFFSET32(stat_name) \
1161			(offsetof(struct bnx2x_eth_stats, stat_name) / 4)
1162
1163/* slow path */
1164#define BNX2X_MAX_NUM_OF_VFS	64
1165#define BNX2X_VF_CID_WND	4 /* log num of queues per VF. HW config. */
1166#define BNX2X_CIDS_PER_VF	(1 << BNX2X_VF_CID_WND)
1167
1168/* We need to reserve doorbell addresses for all VF and queue combinations */
1169#define BNX2X_VF_CIDS		(BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
1170
1171/* The doorbell is configured to have the same number of CIDs for PFs and for
1172 * VFs. For this reason the PF CID zone is as large as the VF zone.
1173 */
1174#define BNX2X_FIRST_VF_CID	BNX2X_VF_CIDS
1175#define BNX2X_MAX_NUM_VF_QUEUES	64
1176#define BNX2X_VF_ID_INVALID	0xFF
1177
1178/* the number of VF CIDS multiplied by the amount of bytes reserved for each
1179 * cid must not exceed the size of the VF doorbell
1180 */
1181#define BNX2X_VF_BAR_SIZE	512
1182#if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT))
1183#error "VF doorbell bar size is 512"
1184#endif
1185
1186/*
1187 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
1188 * control by the number of fast-path status blocks supported by the
1189 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
1190 * status block represents an independent interrupts context that can
1191 * serve a regular L2 networking queue. However special L2 queues such
1192 * as the FCoE queue do not require a FP-SB and other components like
1193 * the CNIC may consume FP-SB reducing the number of possible L2 queues
1194 *
1195 * If the maximum number of FP-SB available is X then:
1196 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
1197 *    regular L2 queues is Y=X-1
1198 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
1199 * c. If the FCoE L2 queue is supported the actual number of L2 queues
1200 *    is Y+1
1201 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
1202 *    slow-path interrupts) or Y+2 if CNIC is supported (one additional
1203 *    FP interrupt context for the CNIC).
1204 * e. The number of HW context (CID count) is always X or X+1 if FCoE
1205 *    L2 queue is supported. The cid for the FCoE L2 queue is always X.
1206 */
1207
1208/* fast-path interrupt contexts E1x */
1209#define FP_SB_MAX_E1x		16
1210/* fast-path interrupt contexts E2 */
1211#define FP_SB_MAX_E2		HC_SB_MAX_SB_E2
1212
1213union cdu_context {
1214	struct eth_context eth;
1215	char pad[1024];
1216};
1217
1218/* CDU host DB constants */
1219#define CDU_ILT_PAGE_SZ_HW	2
1220#define CDU_ILT_PAGE_SZ		(8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1221#define ILT_PAGE_CIDS		(CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1222
1223#define CNIC_ISCSI_CID_MAX	256
1224#define CNIC_FCOE_CID_MAX	2048
1225#define CNIC_CID_MAX		(CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1226#define CNIC_ILT_LINES		DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1227
1228#define QM_ILT_PAGE_SZ_HW	0
1229#define QM_ILT_PAGE_SZ		(4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1230#define QM_CID_ROUND		1024
1231
1232/* TM (timers) host DB constants */
1233#define TM_ILT_PAGE_SZ_HW	0
1234#define TM_ILT_PAGE_SZ		(4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1235#define TM_CONN_NUM		(BNX2X_FIRST_VF_CID + \
1236				 BNX2X_VF_CIDS + \
1237				 CNIC_ISCSI_CID_MAX)
1238#define TM_ILT_SZ		(8 * TM_CONN_NUM)
1239#define TM_ILT_LINES		DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1240
1241/* SRC (Searcher) host DB constants */
1242#define SRC_ILT_PAGE_SZ_HW	0
1243#define SRC_ILT_PAGE_SZ		(4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1244#define SRC_HASH_BITS		10
1245#define SRC_CONN_NUM		(1 << SRC_HASH_BITS) /* 1024 */
1246#define SRC_ILT_SZ		(sizeof(struct src_ent) * SRC_CONN_NUM)
1247#define SRC_T2_SZ		SRC_ILT_SZ
1248#define SRC_ILT_LINES		DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1249
1250#define MAX_DMAE_C		8
1251
1252/* DMA memory not used in fastpath */
1253struct bnx2x_slowpath {
1254	union {
1255		struct mac_configuration_cmd		e1x;
1256		struct eth_classify_rules_ramrod_data	e2;
1257	} mac_rdata;
1258
1259	union {
1260		struct tstorm_eth_mac_filter_config	e1x;
1261		struct eth_filter_rules_ramrod_data	e2;
1262	} rx_mode_rdata;
1263
1264	union {
1265		struct mac_configuration_cmd		e1;
1266		struct eth_multicast_rules_ramrod_data  e2;
1267	} mcast_rdata;
1268
1269	struct eth_rss_update_ramrod_data	rss_rdata;
1270
1271	/* Queue State related ramrods are always sent under rtnl_lock */
1272	union {
1273		struct client_init_ramrod_data  init_data;
1274		struct client_update_ramrod_data update_data;
1275		struct tpa_update_ramrod_data tpa_data;
1276	} q_rdata;
1277
1278	union {
1279		struct function_start_data	func_start;
1280		/* pfc configuration for DCBX ramrod */
1281		struct flow_control_configuration pfc_config;
1282	} func_rdata;
1283
1284	/* afex ramrod can not be a part of func_rdata union because these
1285	 * events might arrive in parallel to other events from func_rdata.
1286	 * Therefore, if they would have been defined in the same union,
1287	 * data can get corrupted.
1288	 */
1289	union {
1290		struct afex_vif_list_ramrod_data	viflist_data;
1291		struct function_update_data		func_update;
1292	} func_afex_rdata;
1293
1294	/* used by dmae command executer */
1295	struct dmae_command		dmae[MAX_DMAE_C];
1296
1297	u32				stats_comp;
1298	union mac_stats			mac_stats;
1299	struct nig_stats		nig_stats;
1300	struct host_port_stats		port_stats;
1301	struct host_func_stats		func_stats;
1302
1303	u32				wb_comp;
1304	u32				wb_data[4];
1305
1306	union drv_info_to_mcp		drv_info_to_mcp;
1307};
1308
1309#define bnx2x_sp(bp, var)		(&bp->slowpath->var)
1310#define bnx2x_sp_mapping(bp, var) \
1311		(bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1312
1313/* attn group wiring */
1314#define MAX_DYNAMIC_ATTN_GRPS		8
1315
1316struct attn_route {
1317	u32 sig[5];
1318};
1319
1320struct iro {
1321	u32 base;
1322	u16 m1;
1323	u16 m2;
1324	u16 m3;
1325	u16 size;
1326};
1327
1328struct hw_context {
1329	union cdu_context *vcxt;
1330	dma_addr_t cxt_mapping;
1331	size_t size;
1332};
1333
1334/* forward */
1335struct bnx2x_ilt;
1336
1337struct bnx2x_vfdb;
1338
1339enum bnx2x_recovery_state {
1340	BNX2X_RECOVERY_DONE,
1341	BNX2X_RECOVERY_INIT,
1342	BNX2X_RECOVERY_WAIT,
1343	BNX2X_RECOVERY_FAILED,
1344	BNX2X_RECOVERY_NIC_LOADING
1345};
1346
1347/*
1348 * Event queue (EQ or event ring) MC hsi
1349 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1350 */
1351#define NUM_EQ_PAGES		1
1352#define EQ_DESC_CNT_PAGE	(BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1353#define EQ_DESC_MAX_PAGE	(EQ_DESC_CNT_PAGE - 1)
1354#define NUM_EQ_DESC		(EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1355#define EQ_DESC_MASK		(NUM_EQ_DESC - 1)
1356#define MAX_EQ_AVAIL		(EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1357
1358/* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1359#define NEXT_EQ_IDX(x)		((((x) & EQ_DESC_MAX_PAGE) == \
1360				  (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1361
1362/* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1363#define EQ_DESC(x)		((x) & EQ_DESC_MASK)
1364
1365#define BNX2X_EQ_INDEX \
1366	(&bp->def_status_blk->sp_sb.\
1367	index_values[HC_SP_INDEX_EQ_CONS])
1368
1369/* This is a data that will be used to create a link report message.
1370 * We will keep the data used for the last link report in order
1371 * to prevent reporting the same link parameters twice.
1372 */
1373struct bnx2x_link_report_data {
1374	u16 line_speed;			/* Effective line speed */
1375	unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1376};
1377
1378enum {
1379	BNX2X_LINK_REPORT_FD,		/* Full DUPLEX */
1380	BNX2X_LINK_REPORT_LINK_DOWN,
1381	BNX2X_LINK_REPORT_RX_FC_ON,
1382	BNX2X_LINK_REPORT_TX_FC_ON,
1383};
1384
1385enum {
1386	BNX2X_PORT_QUERY_IDX,
1387	BNX2X_PF_QUERY_IDX,
1388	BNX2X_FCOE_QUERY_IDX,
1389	BNX2X_FIRST_QUEUE_QUERY_IDX,
1390};
1391
1392struct bnx2x_fw_stats_req {
1393	struct stats_query_header hdr;
1394	struct stats_query_entry query[FP_SB_MAX_E1x+
1395		BNX2X_FIRST_QUEUE_QUERY_IDX];
1396};
1397
1398struct bnx2x_fw_stats_data {
1399	struct stats_counter		storm_counters;
1400	struct per_port_stats		port;
1401	struct per_pf_stats		pf;
1402	struct fcoe_statistics_params	fcoe;
1403	struct per_queue_stats		queue_stats[1];
1404};
1405
1406/* Public slow path states */
1407enum sp_rtnl_flag {
1408	BNX2X_SP_RTNL_SETUP_TC,
1409	BNX2X_SP_RTNL_TX_TIMEOUT,
1410	BNX2X_SP_RTNL_FAN_FAILURE,
1411	BNX2X_SP_RTNL_AFEX_F_UPDATE,
1412	BNX2X_SP_RTNL_ENABLE_SRIOV,
1413	BNX2X_SP_RTNL_VFPF_MCAST,
1414	BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
1415	BNX2X_SP_RTNL_RX_MODE,
1416	BNX2X_SP_RTNL_HYPERVISOR_VLAN,
1417	BNX2X_SP_RTNL_TX_STOP,
1418	BNX2X_SP_RTNL_GET_DRV_VERSION,
1419};
1420
1421enum bnx2x_iov_flag {
1422	BNX2X_IOV_HANDLE_VF_MSG,
1423	BNX2X_IOV_HANDLE_FLR,
1424};
1425
1426struct bnx2x_prev_path_list {
1427	struct list_head list;
1428	u8 bus;
1429	u8 slot;
1430	u8 path;
1431	u8 aer;
1432	u8 undi;
1433};
1434
1435struct bnx2x_sp_objs {
1436	/* MACs object */
1437	struct bnx2x_vlan_mac_obj mac_obj;
1438
1439	/* Queue State object */
1440	struct bnx2x_queue_sp_obj q_obj;
1441};
1442
1443struct bnx2x_fp_stats {
1444	struct tstorm_per_queue_stats old_tclient;
1445	struct ustorm_per_queue_stats old_uclient;
1446	struct xstorm_per_queue_stats old_xclient;
1447	struct bnx2x_eth_q_stats eth_q_stats;
1448	struct bnx2x_eth_q_stats_old eth_q_stats_old;
1449};
1450
1451struct bnx2x {
1452	/* Fields used in the tx and intr/napi performance paths
1453	 * are grouped together in the beginning of the structure
1454	 */
1455	struct bnx2x_fastpath	*fp;
1456	struct bnx2x_sp_objs	*sp_objs;
1457	struct bnx2x_fp_stats	*fp_stats;
1458	struct bnx2x_fp_txdata	*bnx2x_txq;
1459	void __iomem		*regview;
1460	void __iomem		*doorbells;
1461	u16			db_size;
1462
1463	u8			pf_num;	/* absolute PF number */
1464	u8			pfid;	/* per-path PF number */
1465	int			base_fw_ndsb; /**/
1466#define BP_PATH(bp)			(CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1467#define BP_PORT(bp)			(bp->pfid & 1)
1468#define BP_FUNC(bp)			(bp->pfid)
1469#define BP_ABS_FUNC(bp)			(bp->pf_num)
1470#define BP_VN(bp)			((bp)->pfid >> 1)
1471#define BP_MAX_VN_NUM(bp)		(CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1472#define BP_L_ID(bp)			(BP_VN(bp) << 2)
1473#define BP_FW_MB_IDX_VN(bp, vn)		(BP_PORT(bp) +\
1474	  (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2  : 1))
1475#define BP_FW_MB_IDX(bp)		BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1476
1477#ifdef CONFIG_BNX2X_SRIOV
1478	/* protects vf2pf mailbox from simultaneous access */
1479	struct mutex		vf2pf_mutex;
1480	/* vf pf channel mailbox contains request and response buffers */
1481	struct bnx2x_vf_mbx_msg	*vf2pf_mbox;
1482	dma_addr_t		vf2pf_mbox_mapping;
1483
1484	/* we set aside a copy of the acquire response */
1485	struct pfvf_acquire_resp_tlv acquire_resp;
1486
1487	/* bulletin board for messages from pf to vf */
1488	union pf_vf_bulletin   *pf2vf_bulletin;
1489	dma_addr_t		pf2vf_bulletin_mapping;
1490
1491	union pf_vf_bulletin		shadow_bulletin;
1492	struct pf_vf_bulletin_content	old_bulletin;
1493
1494	u16 requested_nr_virtfn;
1495#endif /* CONFIG_BNX2X_SRIOV */
1496
1497	struct net_device	*dev;
1498	struct pci_dev		*pdev;
1499
1500	const struct iro	*iro_arr;
1501#define IRO (bp->iro_arr)
1502
1503	enum bnx2x_recovery_state recovery_state;
1504	int			is_leader;
1505	struct msix_entry	*msix_table;
1506
1507	int			tx_ring_size;
1508
1509/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1510#define ETH_OVREHEAD		(ETH_HLEN + 8 + 8)
1511#define ETH_MIN_PACKET_SIZE		60
1512#define ETH_MAX_PACKET_SIZE		1500
1513#define ETH_MAX_JUMBO_PACKET_SIZE	9600
1514/* TCP with Timestamp Option (32) + IPv6 (40) */
1515#define ETH_MAX_TPA_HEADER_SIZE		72
1516
1517	/* Max supported alignment is 256 (8 shift)
1518	 * minimal alignment shift 6 is optimal for 57xxx HW performance
1519	 */
1520#define BNX2X_RX_ALIGN_SHIFT		max(6, min(8, L1_CACHE_SHIFT))
1521
1522	/* FW uses 2 Cache lines Alignment for start packet and size
1523	 *
1524	 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1525	 * at the end of skb->data, to avoid wasting a full cache line.
1526	 * This reduces memory use (skb->truesize).
1527	 */
1528#define BNX2X_FW_RX_ALIGN_START	(1UL << BNX2X_RX_ALIGN_SHIFT)
1529
1530#define BNX2X_FW_RX_ALIGN_END					\
1531	max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT,			\
1532	    SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1533
1534#define BNX2X_PXP_DRAM_ALIGN		(BNX2X_RX_ALIGN_SHIFT - 5)
1535
1536	struct host_sp_status_block *def_status_blk;
1537#define DEF_SB_IGU_ID			16
1538#define DEF_SB_ID			HC_SP_SB_ID
1539	__le16			def_idx;
1540	__le16			def_att_idx;
1541	u32			attn_state;
1542	struct attn_route	attn_group[MAX_DYNAMIC_ATTN_GRPS];
1543
1544	/* slow path ring */
1545	struct eth_spe		*spq;
1546	dma_addr_t		spq_mapping;
1547	u16			spq_prod_idx;
1548	struct eth_spe		*spq_prod_bd;
1549	struct eth_spe		*spq_last_bd;
1550	__le16			*dsb_sp_prod;
1551	atomic_t		cq_spq_left; /* ETH_XXX ramrods credit */
1552	/* used to synchronize spq accesses */
1553	spinlock_t		spq_lock;
1554
1555	/* event queue */
1556	union event_ring_elem	*eq_ring;
1557	dma_addr_t		eq_mapping;
1558	u16			eq_prod;
1559	u16			eq_cons;
1560	__le16			*eq_cons_sb;
1561	atomic_t		eq_spq_left; /* COMMON_XXX ramrods credit */
1562
1563	/* Counter for marking that there is a STAT_QUERY ramrod pending */
1564	u16			stats_pending;
1565	/*  Counter for completed statistics ramrods */
1566	u16			stats_comp;
1567
1568	/* End of fields used in the performance code paths */
1569
1570	int			panic;
1571	int			msg_enable;
1572
1573	u32			flags;
1574#define PCIX_FLAG			(1 << 0)
1575#define PCI_32BIT_FLAG			(1 << 1)
1576#define ONE_PORT_FLAG			(1 << 2)
1577#define NO_WOL_FLAG			(1 << 3)
1578#define USING_MSIX_FLAG			(1 << 5)
1579#define USING_MSI_FLAG			(1 << 6)
1580#define DISABLE_MSI_FLAG		(1 << 7)
1581#define TPA_ENABLE_FLAG			(1 << 8)
1582#define NO_MCP_FLAG			(1 << 9)
1583#define GRO_ENABLE_FLAG			(1 << 10)
1584#define MF_FUNC_DIS			(1 << 11)
1585#define OWN_CNIC_IRQ			(1 << 12)
1586#define NO_ISCSI_OOO_FLAG		(1 << 13)
1587#define NO_ISCSI_FLAG			(1 << 14)
1588#define NO_FCOE_FLAG			(1 << 15)
1589#define BC_SUPPORTS_PFC_STATS		(1 << 17)
1590#define TX_SWITCHING			(1 << 18)
1591#define BC_SUPPORTS_FCOE_FEATURES	(1 << 19)
1592#define USING_SINGLE_MSIX_FLAG		(1 << 20)
1593#define BC_SUPPORTS_DCBX_MSG_NON_PMF	(1 << 21)
1594#define IS_VF_FLAG			(1 << 22)
1595#define BC_SUPPORTS_RMMOD_CMD		(1 << 23)
1596#define HAS_PHYS_PORT_ID		(1 << 24)
1597#define AER_ENABLED			(1 << 25)
1598#define PTP_SUPPORTED			(1 << 26)
1599#define TX_TIMESTAMPING_EN		(1 << 27)
1600
1601#define BP_NOMCP(bp)			((bp)->flags & NO_MCP_FLAG)
1602
1603#ifdef CONFIG_BNX2X_SRIOV
1604#define IS_VF(bp)			((bp)->flags & IS_VF_FLAG)
1605#define IS_PF(bp)			(!((bp)->flags & IS_VF_FLAG))
1606#else
1607#define IS_VF(bp)			false
1608#define IS_PF(bp)			true
1609#endif
1610
1611#define NO_ISCSI(bp)		((bp)->flags & NO_ISCSI_FLAG)
1612#define NO_ISCSI_OOO(bp)	((bp)->flags & NO_ISCSI_OOO_FLAG)
1613#define NO_FCOE(bp)		((bp)->flags & NO_FCOE_FLAG)
1614
1615	u8			cnic_support;
1616	bool			cnic_enabled;
1617	bool			cnic_loaded;
1618	struct cnic_eth_dev	*(*cnic_probe)(struct net_device *);
1619
1620	/* Flag that indicates that we can start looking for FCoE L2 queue
1621	 * completions in the default status block.
1622	 */
1623	bool			fcoe_init;
1624
1625	int			mrrs;
1626
1627	struct delayed_work	sp_task;
1628	struct delayed_work	iov_task;
1629
1630	atomic_t		interrupt_occurred;
1631	struct delayed_work	sp_rtnl_task;
1632
1633	struct delayed_work	period_task;
1634	struct timer_list	timer;
1635	int			current_interval;
1636
1637	u16			fw_seq;
1638	u16			fw_drv_pulse_wr_seq;
1639	u32			func_stx;
1640
1641	struct link_params	link_params;
1642	struct link_vars	link_vars;
1643	u32			link_cnt;
1644	struct bnx2x_link_report_data last_reported_link;
1645
1646	struct mdio_if_info	mdio;
1647
1648	struct bnx2x_common	common;
1649	struct bnx2x_port	port;
1650
1651	struct cmng_init	cmng;
1652
1653	u32			mf_config[E1HVN_MAX];
1654	u32			mf_ext_config;
1655	u32			path_has_ovlan; /* E3 */
1656	u16			mf_ov;
1657	u8			mf_mode;
1658#define IS_MF(bp)		(bp->mf_mode != 0)
1659#define IS_MF_SI(bp)		(bp->mf_mode == MULTI_FUNCTION_SI)
1660#define IS_MF_SD(bp)		(bp->mf_mode == MULTI_FUNCTION_SD)
1661#define IS_MF_AFEX(bp)		(bp->mf_mode == MULTI_FUNCTION_AFEX)
1662
1663	u8			wol;
1664
1665	int			rx_ring_size;
1666
1667	u16			tx_quick_cons_trip_int;
1668	u16			tx_quick_cons_trip;
1669	u16			tx_ticks_int;
1670	u16			tx_ticks;
1671
1672	u16			rx_quick_cons_trip_int;
1673	u16			rx_quick_cons_trip;
1674	u16			rx_ticks_int;
1675	u16			rx_ticks;
1676/* Maximal coalescing timeout in us */
1677#define BNX2X_MAX_COALESCE_TOUT		(0xff*BNX2X_BTR)
1678
1679	u32			lin_cnt;
1680
1681	u16			state;
1682#define BNX2X_STATE_CLOSED		0
1683#define BNX2X_STATE_OPENING_WAIT4_LOAD	0x1000
1684#define BNX2X_STATE_OPENING_WAIT4_PORT	0x2000
1685#define BNX2X_STATE_OPEN		0x3000
1686#define BNX2X_STATE_CLOSING_WAIT4_HALT	0x4000
1687#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1688
1689#define BNX2X_STATE_DIAG		0xe000
1690#define BNX2X_STATE_ERROR		0xf000
1691
1692#define BNX2X_MAX_PRIORITY		8
1693	int			num_queues;
1694	uint			num_ethernet_queues;
1695	uint			num_cnic_queues;
1696	int			disable_tpa;
1697
1698	u32			rx_mode;
1699#define BNX2X_RX_MODE_NONE		0
1700#define BNX2X_RX_MODE_NORMAL		1
1701#define BNX2X_RX_MODE_ALLMULTI		2
1702#define BNX2X_RX_MODE_PROMISC		3
1703#define BNX2X_MAX_MULTICAST		64
1704
1705	u8			igu_dsb_id;
1706	u8			igu_base_sb;
1707	u8			igu_sb_cnt;
1708	u8			min_msix_vec_cnt;
1709
1710	u32			igu_base_addr;
1711	dma_addr_t		def_status_blk_mapping;
1712
1713	struct bnx2x_slowpath	*slowpath;
1714	dma_addr_t		slowpath_mapping;
1715
1716	/* Mechanism protecting the drv_info_to_mcp */
1717	struct mutex		drv_info_mutex;
1718	bool			drv_info_mng_owner;
1719
1720	/* Total number of FW statistics requests */
1721	u8			fw_stats_num;
1722
1723	/*
1724	 * This is a memory buffer that will contain both statistics
1725	 * ramrod request and data.
1726	 */
1727	void			*fw_stats;
1728	dma_addr_t		fw_stats_mapping;
1729
1730	/*
1731	 * FW statistics request shortcut (points at the
1732	 * beginning of fw_stats buffer).
1733	 */
1734	struct bnx2x_fw_stats_req	*fw_stats_req;
1735	dma_addr_t			fw_stats_req_mapping;
1736	int				fw_stats_req_sz;
1737
1738	/*
1739	 * FW statistics data shortcut (points at the beginning of
1740	 * fw_stats buffer + fw_stats_req_sz).
1741	 */
1742	struct bnx2x_fw_stats_data	*fw_stats_data;
1743	dma_addr_t			fw_stats_data_mapping;
1744	int				fw_stats_data_sz;
1745
1746	/* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB
1747	 * context size we need 8 ILT entries.
1748	 */
1749#define ILT_MAX_L2_LINES	32
1750	struct hw_context	context[ILT_MAX_L2_LINES];
1751
1752	struct bnx2x_ilt	*ilt;
1753#define BP_ILT(bp)		((bp)->ilt)
1754#define ILT_MAX_LINES		256
1755/*
1756 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1757 * to CNIC.
1758 */
1759#define BNX2X_MAX_RSS_COUNT(bp)	((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1760
1761/*
1762 * Maximum CID count that might be required by the bnx2x:
1763 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1764 */
1765
1766#define BNX2X_L2_CID_COUNT(bp)	(BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1767				+ CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1768#define BNX2X_L2_MAX_CID(bp)	(BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1769				+ CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp)))
1770#define L2_ILT_LINES(bp)	(DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1771					ILT_PAGE_CIDS))
1772
1773	int			qm_cid_count;
1774
1775	bool			dropless_fc;
1776
1777	void			*t2;
1778	dma_addr_t		t2_mapping;
1779	struct cnic_ops	__rcu	*cnic_ops;
1780	void			*cnic_data;
1781	u32			cnic_tag;
1782	struct cnic_eth_dev	cnic_eth_dev;
1783	union host_hc_status_block cnic_sb;
1784	dma_addr_t		cnic_sb_mapping;
1785	struct eth_spe		*cnic_kwq;
1786	struct eth_spe		*cnic_kwq_prod;
1787	struct eth_spe		*cnic_kwq_cons;
1788	struct eth_spe		*cnic_kwq_last;
1789	u16			cnic_kwq_pending;
1790	u16			cnic_spq_pending;
1791	u8			fip_mac[ETH_ALEN];
1792	struct mutex		cnic_mutex;
1793	struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1794
1795	/* Start index of the "special" (CNIC related) L2 clients */
1796	u8				cnic_base_cl_id;
1797
1798	int			dmae_ready;
1799	/* used to synchronize dmae accesses */
1800	spinlock_t		dmae_lock;
1801
1802	/* used to protect the FW mail box */
1803	struct mutex		fw_mb_mutex;
1804
1805	/* used to synchronize stats collecting */
1806	int			stats_state;
1807
1808	/* used for synchronization of concurrent threads statistics handling */
1809	spinlock_t		stats_lock;
1810
1811	/* used by dmae command loader */
1812	struct dmae_command	stats_dmae;
1813	int			executer_idx;
1814
1815	u16			stats_counter;
1816	struct bnx2x_eth_stats	eth_stats;
1817	struct host_func_stats		func_stats;
1818	struct bnx2x_eth_stats_old	eth_stats_old;
1819	struct bnx2x_net_stats_old	net_stats_old;
1820	struct bnx2x_fw_port_stats_old	fw_stats_old;
1821	bool			stats_init;
1822
1823	struct z_stream_s	*strm;
1824	void			*gunzip_buf;
1825	dma_addr_t		gunzip_mapping;
1826	int			gunzip_outlen;
1827#define FW_BUF_SIZE			0x8000
1828#define GUNZIP_BUF(bp)			(bp->gunzip_buf)
1829#define GUNZIP_PHYS(bp)			(bp->gunzip_mapping)
1830#define GUNZIP_OUTLEN(bp)		(bp->gunzip_outlen)
1831
1832	struct raw_op		*init_ops;
1833	/* Init blocks offsets inside init_ops */
1834	u16			*init_ops_offsets;
1835	/* Data blob - has 32 bit granularity */
1836	u32			*init_data;
1837	u32			init_mode_flags;
1838#define INIT_MODE_FLAGS(bp)	(bp->init_mode_flags)
1839	/* Zipped PRAM blobs - raw data */
1840	const u8		*tsem_int_table_data;
1841	const u8		*tsem_pram_data;
1842	const u8		*usem_int_table_data;
1843	const u8		*usem_pram_data;
1844	const u8		*xsem_int_table_data;
1845	const u8		*xsem_pram_data;
1846	const u8		*csem_int_table_data;
1847	const u8		*csem_pram_data;
1848#define INIT_OPS(bp)			(bp->init_ops)
1849#define INIT_OPS_OFFSETS(bp)		(bp->init_ops_offsets)
1850#define INIT_DATA(bp)			(bp->init_data)
1851#define INIT_TSEM_INT_TABLE_DATA(bp)	(bp->tsem_int_table_data)
1852#define INIT_TSEM_PRAM_DATA(bp)		(bp->tsem_pram_data)
1853#define INIT_USEM_INT_TABLE_DATA(bp)	(bp->usem_int_table_data)
1854#define INIT_USEM_PRAM_DATA(bp)		(bp->usem_pram_data)
1855#define INIT_XSEM_INT_TABLE_DATA(bp)	(bp->xsem_int_table_data)
1856#define INIT_XSEM_PRAM_DATA(bp)		(bp->xsem_pram_data)
1857#define INIT_CSEM_INT_TABLE_DATA(bp)	(bp->csem_int_table_data)
1858#define INIT_CSEM_PRAM_DATA(bp)		(bp->csem_pram_data)
1859
1860#define PHY_FW_VER_LEN			20
1861	char			fw_ver[32];
1862	const struct firmware	*firmware;
1863
1864	struct bnx2x_vfdb	*vfdb;
1865#define IS_SRIOV(bp)		((bp)->vfdb)
1866
1867	/* DCB support on/off */
1868	u16 dcb_state;
1869#define BNX2X_DCB_STATE_OFF			0
1870#define BNX2X_DCB_STATE_ON			1
1871
1872	/* DCBX engine mode */
1873	int dcbx_enabled;
1874#define BNX2X_DCBX_ENABLED_OFF			0
1875#define BNX2X_DCBX_ENABLED_ON_NEG_OFF		1
1876#define BNX2X_DCBX_ENABLED_ON_NEG_ON		2
1877#define BNX2X_DCBX_ENABLED_INVALID		(-1)
1878
1879	bool dcbx_mode_uset;
1880
1881	struct bnx2x_config_dcbx_params		dcbx_config_params;
1882	struct bnx2x_dcbx_port_params		dcbx_port_params;
1883	int					dcb_version;
1884
1885	/* CAM credit pools */
1886
1887	/* used only in sriov */
1888	struct bnx2x_credit_pool_obj		vlans_pool;
1889
1890	struct bnx2x_credit_pool_obj		macs_pool;
1891
1892	/* RX_MODE object */
1893	struct bnx2x_rx_mode_obj		rx_mode_obj;
1894
1895	/* MCAST object */
1896	struct bnx2x_mcast_obj			mcast_obj;
1897
1898	/* RSS configuration object */
1899	struct bnx2x_rss_config_obj		rss_conf_obj;
1900
1901	/* Function State controlling object */
1902	struct bnx2x_func_sp_obj		func_obj;
1903
1904	unsigned long				sp_state;
1905
1906	/* operation indication for the sp_rtnl task */
1907	unsigned long				sp_rtnl_state;
1908
1909	/* Indication of the IOV tasks */
1910	unsigned long				iov_task_state;
1911
1912	/* DCBX Negotiation results */
1913	struct dcbx_features			dcbx_local_feat;
1914	u32					dcbx_error;
1915
1916#ifdef BCM_DCBNL
1917	struct dcbx_features			dcbx_remote_feat;
1918	u32					dcbx_remote_flags;
1919#endif
1920	/* AFEX: store default vlan used */
1921	int					afex_def_vlan_tag;
1922	enum mf_cfg_afex_vlan_mode		afex_vlan_mode;
1923	u32					pending_max;
1924
1925	/* multiple tx classes of service */
1926	u8					max_cos;
1927
1928	/* priority to cos mapping */
1929	u8					prio_to_cos[8];
1930
1931	int fp_array_size;
1932	u32 dump_preset_idx;
1933	bool					stats_started;
1934	struct semaphore			stats_sema;
1935
1936	u8					phys_port_id[ETH_ALEN];
1937
1938	/* PTP related context */
1939	struct ptp_clock *ptp_clock;
1940	struct ptp_clock_info ptp_clock_info;
1941	struct work_struct ptp_task;
1942	struct cyclecounter cyclecounter;
1943	struct timecounter timecounter;
1944	bool timecounter_init_done;
1945	struct sk_buff *ptp_tx_skb;
1946	unsigned long ptp_tx_start;
1947	bool hwtstamp_ioctl_called;
1948	u16 tx_type;
1949	u16 rx_filter;
1950
1951	struct bnx2x_link_report_data		vf_link_vars;
1952};
1953
1954/* Tx queues may be less or equal to Rx queues */
1955extern int num_queues;
1956#define BNX2X_NUM_QUEUES(bp)	(bp->num_queues)
1957#define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1958#define BNX2X_NUM_NON_CNIC_QUEUES(bp)	(BNX2X_NUM_QUEUES(bp) - \
1959					 (bp)->num_cnic_queues)
1960#define BNX2X_NUM_RX_QUEUES(bp)	BNX2X_NUM_QUEUES(bp)
1961
1962#define is_multi(bp)		(BNX2X_NUM_QUEUES(bp) > 1)
1963
1964#define BNX2X_MAX_QUEUES(bp)	BNX2X_MAX_RSS_COUNT(bp)
1965/* #define is_eth_multi(bp)	(BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1966
1967#define RSS_IPV4_CAP_MASK						\
1968	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1969
1970#define RSS_IPV4_TCP_CAP_MASK						\
1971	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1972
1973#define RSS_IPV6_CAP_MASK						\
1974	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1975
1976#define RSS_IPV6_TCP_CAP_MASK						\
1977	TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1978
1979/* func init flags */
1980#define FUNC_FLG_RSS		0x0001
1981#define FUNC_FLG_STATS		0x0002
1982/* removed  FUNC_FLG_UNMATCHED	0x0004 */
1983#define FUNC_FLG_TPA		0x0008
1984#define FUNC_FLG_SPQ		0x0010
1985#define FUNC_FLG_LEADING	0x0020	/* PF only */
1986#define FUNC_FLG_LEADING_STATS	0x0040
1987struct bnx2x_func_init_params {
1988	/* dma */
1989	dma_addr_t	fw_stat_map;	/* valid iff FUNC_FLG_STATS */
1990	dma_addr_t	spq_map;	/* valid iff FUNC_FLG_SPQ */
1991
1992	u16		func_flgs;
1993	u16		func_id;	/* abs fid */
1994	u16		pf_id;
1995	u16		spq_prod;	/* valid iff FUNC_FLG_SPQ */
1996};
1997
1998#define for_each_cnic_queue(bp, var) \
1999	for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
2000	     (var)++) \
2001		if (skip_queue(bp, var))	\
2002			continue;		\
2003		else
2004
2005#define for_each_eth_queue(bp, var) \
2006	for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
2007
2008#define for_each_nondefault_eth_queue(bp, var) \
2009	for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
2010
2011#define for_each_queue(bp, var) \
2012	for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2013		if (skip_queue(bp, var))	\
2014			continue;		\
2015		else
2016
2017/* Skip forwarding FP */
2018#define for_each_valid_rx_queue(bp, var)			\
2019	for ((var) = 0;						\
2020	     (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) :	\
2021		      BNX2X_NUM_ETH_QUEUES(bp));		\
2022	     (var)++)						\
2023		if (skip_rx_queue(bp, var))			\
2024			continue;				\
2025		else
2026
2027#define for_each_rx_queue_cnic(bp, var) \
2028	for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
2029	     (var)++) \
2030		if (skip_rx_queue(bp, var))	\
2031			continue;		\
2032		else
2033
2034#define for_each_rx_queue(bp, var) \
2035	for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2036		if (skip_rx_queue(bp, var))	\
2037			continue;		\
2038		else
2039
2040/* Skip OOO FP */
2041#define for_each_valid_tx_queue(bp, var)			\
2042	for ((var) = 0;						\
2043	     (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) :	\
2044		      BNX2X_NUM_ETH_QUEUES(bp));		\
2045	     (var)++)						\
2046		if (skip_tx_queue(bp, var))			\
2047			continue;				\
2048		else
2049
2050#define for_each_tx_queue_cnic(bp, var) \
2051	for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
2052	     (var)++) \
2053		if (skip_tx_queue(bp, var))	\
2054			continue;		\
2055		else
2056
2057#define for_each_tx_queue(bp, var) \
2058	for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2059		if (skip_tx_queue(bp, var))	\
2060			continue;		\
2061		else
2062
2063#define for_each_nondefault_queue(bp, var) \
2064	for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
2065		if (skip_queue(bp, var))	\
2066			continue;		\
2067		else
2068
2069#define for_each_cos_in_tx_queue(fp, var) \
2070	for ((var) = 0; (var) < (fp)->max_cos; (var)++)
2071
2072/* skip rx queue
2073 * if FCOE l2 support is disabled and this is the fcoe L2 queue
2074 */
2075#define skip_rx_queue(bp, idx)	(NO_FCOE(bp) && IS_FCOE_IDX(idx))
2076
2077/* skip tx queue
2078 * if FCOE l2 support is disabled and this is the fcoe L2 queue
2079 */
2080#define skip_tx_queue(bp, idx)	(NO_FCOE(bp) && IS_FCOE_IDX(idx))
2081
2082#define skip_queue(bp, idx)	(NO_FCOE(bp) && IS_FCOE_IDX(idx))
2083
2084/**
2085 * bnx2x_set_mac_one - configure a single MAC address
2086 *
2087 * @bp:			driver handle
2088 * @mac:		MAC to configure
2089 * @obj:		MAC object handle
2090 * @set:		if 'true' add a new MAC, otherwise - delete
2091 * @mac_type:		the type of the MAC to configure (e.g. ETH, UC list)
2092 * @ramrod_flags:	RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
2093 *
2094 * Configures one MAC according to provided parameters or continues the
2095 * execution of previously scheduled commands if RAMROD_CONT is set in
2096 * ramrod_flags.
2097 *
2098 * Returns zero if operation has successfully completed, a positive value if the
2099 * operation has been successfully scheduled and a negative - if a requested
2100 * operations has failed.
2101 */
2102int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
2103		      struct bnx2x_vlan_mac_obj *obj, bool set,
2104		      int mac_type, unsigned long *ramrod_flags);
2105/**
2106 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
2107 *
2108 * @bp:			driver handle
2109 * @mac_obj:		MAC object handle
2110 * @mac_type:		type of the MACs to clear (BNX2X_XXX_MAC)
2111 * @wait_for_comp:	if 'true' block until completion
2112 *
2113 * Deletes all MACs of the specific type (e.g. ETH, UC list).
2114 *
2115 * Returns zero if operation has successfully completed, a positive value if the
2116 * operation has been successfully scheduled and a negative - if a requested
2117 * operations has failed.
2118 */
2119int bnx2x_del_all_macs(struct bnx2x *bp,
2120		       struct bnx2x_vlan_mac_obj *mac_obj,
2121		       int mac_type, bool wait_for_comp);
2122
2123/* Init Function API  */
2124void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
2125void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
2126		    u8 vf_valid, int fw_sb_id, int igu_sb_id);
2127int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
2128int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2129int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
2130int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2131void bnx2x_read_mf_cfg(struct bnx2x *bp);
2132
2133int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
2134
2135/* dmae */
2136void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
2137void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
2138		      u32 len32);
2139void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
2140u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
2141u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
2142u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
2143		      bool with_comp, u8 comp_type);
2144
2145void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2146			       u8 src_type, u8 dst_type);
2147int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2148			       u32 *comp);
2149
2150/* FLR related routines */
2151u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
2152void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
2153int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
2154u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
2155int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
2156				    char *msg, u32 poll_cnt);
2157
2158void bnx2x_calc_fc_adv(struct bnx2x *bp);
2159int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2160		  u32 data_hi, u32 data_lo, int cmd_type);
2161void bnx2x_update_coalesce(struct bnx2x *bp);
2162int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
2163
2164bool bnx2x_port_after_undi(struct bnx2x *bp);
2165
2166static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
2167			   int wait)
2168{
2169	u32 val;
2170
2171	do {
2172		val = REG_RD(bp, reg);
2173		if (val == expected)
2174			break;
2175		ms -= wait;
2176		msleep(wait);
2177
2178	} while (ms > 0);
2179
2180	return val;
2181}
2182
2183void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
2184			    bool is_pf);
2185
2186#define BNX2X_ILT_ZALLOC(x, y, size)					\
2187	x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL)
2188
2189#define BNX2X_ILT_FREE(x, y, size) \
2190	do { \
2191		if (x) { \
2192			dma_free_coherent(&bp->pdev->dev, size, x, y); \
2193			x = NULL; \
2194			y = 0; \
2195		} \
2196	} while (0)
2197
2198#define ILOG2(x)	(ilog2((x)))
2199
2200#define ILT_NUM_PAGE_ENTRIES	(3072)
2201/* In 57710/11 we use whole table since we have 8 func
2202 * In 57712 we have only 4 func, but use same size per func, then only half of
2203 * the table in use
2204 */
2205#define ILT_PER_FUNC		(ILT_NUM_PAGE_ENTRIES/8)
2206
2207#define FUNC_ILT_BASE(func)	(func * ILT_PER_FUNC)
2208/*
2209 * the phys address is shifted right 12 bits and has an added
2210 * 1=valid bit added to the 53rd bit
2211 * then since this is a wide register(TM)
2212 * we split it into two 32 bit writes
2213 */
2214#define ONCHIP_ADDR1(x)		((u32)(((u64)x >> 12) & 0xFFFFFFFF))
2215#define ONCHIP_ADDR2(x)		((u32)((1 << 20) | ((u64)x >> 44)))
2216
2217/* load/unload mode */
2218#define LOAD_NORMAL			0
2219#define LOAD_OPEN			1
2220#define LOAD_DIAG			2
2221#define LOAD_LOOPBACK_EXT		3
2222#define UNLOAD_NORMAL			0
2223#define UNLOAD_CLOSE			1
2224#define UNLOAD_RECOVERY			2
2225
2226/* DMAE command defines */
2227#define DMAE_TIMEOUT			-1
2228#define DMAE_PCI_ERROR			-2	/* E2 and onward */
2229#define DMAE_NOT_RDY			-3
2230#define DMAE_PCI_ERR_FLAG		0x80000000
2231
2232#define DMAE_SRC_PCI			0
2233#define DMAE_SRC_GRC			1
2234
2235#define DMAE_DST_NONE			0
2236#define DMAE_DST_PCI			1
2237#define DMAE_DST_GRC			2
2238
2239#define DMAE_COMP_PCI			0
2240#define DMAE_COMP_GRC			1
2241
2242/* E2 and onward - PCI error handling in the completion */
2243
2244#define DMAE_COMP_REGULAR		0
2245#define DMAE_COM_SET_ERR		1
2246
2247#define DMAE_CMD_SRC_PCI		(DMAE_SRC_PCI << \
2248						DMAE_COMMAND_SRC_SHIFT)
2249#define DMAE_CMD_SRC_GRC		(DMAE_SRC_GRC << \
2250						DMAE_COMMAND_SRC_SHIFT)
2251
2252#define DMAE_CMD_DST_PCI		(DMAE_DST_PCI << \
2253						DMAE_COMMAND_DST_SHIFT)
2254#define DMAE_CMD_DST_GRC		(DMAE_DST_GRC << \
2255						DMAE_COMMAND_DST_SHIFT)
2256
2257#define DMAE_CMD_C_DST_PCI		(DMAE_COMP_PCI << \
2258						DMAE_COMMAND_C_DST_SHIFT)
2259#define DMAE_CMD_C_DST_GRC		(DMAE_COMP_GRC << \
2260						DMAE_COMMAND_C_DST_SHIFT)
2261
2262#define DMAE_CMD_C_ENABLE		DMAE_COMMAND_C_TYPE_ENABLE
2263
2264#define DMAE_CMD_ENDIANITY_NO_SWAP	(0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2265#define DMAE_CMD_ENDIANITY_B_SWAP	(1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2266#define DMAE_CMD_ENDIANITY_DW_SWAP	(2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2267#define DMAE_CMD_ENDIANITY_B_DW_SWAP	(3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2268
2269#define DMAE_CMD_PORT_0			0
2270#define DMAE_CMD_PORT_1			DMAE_COMMAND_PORT
2271
2272#define DMAE_CMD_SRC_RESET		DMAE_COMMAND_SRC_RESET
2273#define DMAE_CMD_DST_RESET		DMAE_COMMAND_DST_RESET
2274#define DMAE_CMD_E1HVN_SHIFT		DMAE_COMMAND_E1HVN_SHIFT
2275
2276#define DMAE_SRC_PF			0
2277#define DMAE_SRC_VF			1
2278
2279#define DMAE_DST_PF			0
2280#define DMAE_DST_VF			1
2281
2282#define DMAE_C_SRC			0
2283#define DMAE_C_DST			1
2284
2285#define DMAE_LEN32_RD_MAX		0x80
2286#define DMAE_LEN32_WR_MAX(bp)		(CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2287
2288#define DMAE_COMP_VAL			0x60d0d0ae /* E2 and on - upper bit
2289						    * indicates error
2290						    */
2291
2292#define MAX_DMAE_C_PER_PORT		8
2293#define INIT_DMAE_C(bp)			(BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2294					 BP_VN(bp))
2295#define PMF_DMAE_C(bp)			(BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2296					 E1HVN_MAX)
2297
2298/* PCIE link and speed */
2299#define PCICFG_LINK_WIDTH		0x1f00000
2300#define PCICFG_LINK_WIDTH_SHIFT		20
2301#define PCICFG_LINK_SPEED		0xf0000
2302#define PCICFG_LINK_SPEED_SHIFT		16
2303
2304#define BNX2X_NUM_TESTS_SF		7
2305#define BNX2X_NUM_TESTS_MF		3
2306#define BNX2X_NUM_TESTS(bp)		(IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
2307					     IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF)
2308
2309#define BNX2X_PHY_LOOPBACK		0
2310#define BNX2X_MAC_LOOPBACK		1
2311#define BNX2X_EXT_LOOPBACK		2
2312#define BNX2X_PHY_LOOPBACK_FAILED	1
2313#define BNX2X_MAC_LOOPBACK_FAILED	2
2314#define BNX2X_EXT_LOOPBACK_FAILED	3
2315#define BNX2X_LOOPBACK_FAILED		(BNX2X_MAC_LOOPBACK_FAILED | \
2316					 BNX2X_PHY_LOOPBACK_FAILED)
2317
2318#define STROM_ASSERT_ARRAY_SIZE		50
2319
2320/* must be used on a CID before placing it on a HW ring */
2321#define HW_CID(bp, x)			((BP_PORT(bp) << 23) | \
2322					 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2323					 (x))
2324
2325#define SP_DESC_CNT		(BCM_PAGE_SIZE / sizeof(struct eth_spe))
2326#define MAX_SP_DESC_CNT			(SP_DESC_CNT - 1)
2327
2328#define BNX2X_BTR			4
2329#define MAX_SPQ_PENDING			8
2330
2331/* CMNG constants, as derived from system spec calculations */
2332/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2333#define DEF_MIN_RATE					100
2334/* resolution of the rate shaping timer - 400 usec */
2335#define RS_PERIODIC_TIMEOUT_USEC			400
2336/* number of bytes in single QM arbitration cycle -
2337 * coefficient for calculating the fairness timer */
2338#define QM_ARB_BYTES					160000
2339/* resolution of Min algorithm 1:100 */
2340#define MIN_RES						100
2341/* how many bytes above threshold for the minimal credit of Min algorithm*/
2342#define MIN_ABOVE_THRESH				32768
2343/* Fairness algorithm integration time coefficient -
2344 * for calculating the actual Tfair */
2345#define T_FAIR_COEF	((MIN_ABOVE_THRESH +  QM_ARB_BYTES) * 8 * MIN_RES)
2346/* Memory of fairness algorithm . 2 cycles */
2347#define FAIR_MEM					2
2348
2349#define ATTN_NIG_FOR_FUNC		(1L << 8)
2350#define ATTN_SW_TIMER_4_FUNC		(1L << 9)
2351#define GPIO_2_FUNC			(1L << 10)
2352#define GPIO_3_FUNC			(1L << 11)
2353#define GPIO_4_FUNC			(1L << 12)
2354#define ATTN_GENERAL_ATTN_1		(1L << 13)
2355#define ATTN_GENERAL_ATTN_2		(1L << 14)
2356#define ATTN_GENERAL_ATTN_3		(1L << 15)
2357#define ATTN_GENERAL_ATTN_4		(1L << 13)
2358#define ATTN_GENERAL_ATTN_5		(1L << 14)
2359#define ATTN_GENERAL_ATTN_6		(1L << 15)
2360
2361#define ATTN_HARD_WIRED_MASK		0xff00
2362#define ATTENTION_ID			4
2363
2364#define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_SD(bp) || \
2365				 IS_MF_FCOE_AFEX(bp))
2366
2367/* stuff added to make the code fit 80Col */
2368
2369#define BNX2X_PMF_LINK_ASSERT \
2370	GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2371
2372#define BNX2X_MC_ASSERT_BITS \
2373	(GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2374	 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2375	 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2376	 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2377
2378#define BNX2X_MCP_ASSERT \
2379	GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2380
2381#define BNX2X_GRC_TIMEOUT	GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2382#define BNX2X_GRC_RSV		(GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2383				 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2384				 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2385				 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2386				 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2387				 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2388
2389#define HW_INTERRUT_ASSERT_SET_0 \
2390				(AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2391				 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2392				 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2393				 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
2394				 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2395#define HW_PRTY_ASSERT_SET_0	(AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2396				 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2397				 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2398				 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2399				 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2400				 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2401				 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2402#define HW_INTERRUT_ASSERT_SET_1 \
2403				(AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2404				 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2405				 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2406				 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2407				 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2408				 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2409				 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2410				 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2411				 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2412				 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2413				 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2414#define HW_PRTY_ASSERT_SET_1	(AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2415				 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2416				 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2417				 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2418				 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2419				 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2420				 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2421				 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2422			     AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2423				 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2424				 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2425				 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2426				 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2427				 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2428				 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2429				 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2430#define HW_INTERRUT_ASSERT_SET_2 \
2431				(AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2432				 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2433				 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2434			AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2435				 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2436#define HW_PRTY_ASSERT_SET_2	(AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2437				 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2438			AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2439				 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2440				 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2441				 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2442				 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2443				 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2444
2445#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2446		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2447		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2448		AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2449
2450#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2451			      AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2452
2453#define MULTI_MASK			0x7f
2454
2455#define DEF_USB_FUNC_OFF	offsetof(struct cstorm_def_status_block_u, func)
2456#define DEF_CSB_FUNC_OFF	offsetof(struct cstorm_def_status_block_c, func)
2457#define DEF_XSB_FUNC_OFF	offsetof(struct xstorm_def_status_block, func)
2458#define DEF_TSB_FUNC_OFF	offsetof(struct tstorm_def_status_block, func)
2459
2460#define DEF_USB_IGU_INDEX_OFF \
2461			offsetof(struct cstorm_def_status_block_u, igu_index)
2462#define DEF_CSB_IGU_INDEX_OFF \
2463			offsetof(struct cstorm_def_status_block_c, igu_index)
2464#define DEF_XSB_IGU_INDEX_OFF \
2465			offsetof(struct xstorm_def_status_block, igu_index)
2466#define DEF_TSB_IGU_INDEX_OFF \
2467			offsetof(struct tstorm_def_status_block, igu_index)
2468
2469#define DEF_USB_SEGMENT_OFF \
2470			offsetof(struct cstorm_def_status_block_u, segment)
2471#define DEF_CSB_SEGMENT_OFF \
2472			offsetof(struct cstorm_def_status_block_c, segment)
2473#define DEF_XSB_SEGMENT_OFF \
2474			offsetof(struct xstorm_def_status_block, segment)
2475#define DEF_TSB_SEGMENT_OFF \
2476			offsetof(struct tstorm_def_status_block, segment)
2477
2478#define BNX2X_SP_DSB_INDEX \
2479		(&bp->def_status_blk->sp_sb.\
2480					index_values[HC_SP_INDEX_ETH_DEF_CONS])
2481
2482#define CAM_IS_INVALID(x) \
2483	(GET_FLAG(x.flags, \
2484	MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2485	(T_ETH_MAC_COMMAND_INVALIDATE))
2486
2487/* Number of u32 elements in MC hash array */
2488#define MC_HASH_SIZE			8
2489#define MC_HASH_OFFSET(bp, i)		(BAR_TSTRORM_INTMEM + \
2490	TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2491
2492#ifndef PXP2_REG_PXP2_INT_STS
2493#define PXP2_REG_PXP2_INT_STS		PXP2_REG_PXP2_INT_STS_0
2494#endif
2495
2496#ifndef ETH_MAX_RX_CLIENTS_E2
2497#define ETH_MAX_RX_CLIENTS_E2		ETH_MAX_RX_CLIENTS_E1H
2498#endif
2499
2500#define BNX2X_VPD_LEN			128
2501#define VENDOR_ID_LEN			4
2502
2503#define VF_ACQUIRE_THRESH		3
2504#define VF_ACQUIRE_MAC_FILTERS		1
2505#define VF_ACQUIRE_MC_FILTERS		10
2506
2507#define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2508			    (!((me_reg) & ME_REG_VF_ERR)))
2509int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err);
2510
2511/* Congestion management fairness mode */
2512#define CMNG_FNS_NONE			0
2513#define CMNG_FNS_MINMAX			1
2514
2515#define HC_SEG_ACCESS_DEF		0   /*Driver decision 0-3*/
2516#define HC_SEG_ACCESS_ATTN		4
2517#define HC_SEG_ACCESS_NORM		0   /*Driver decision 0-1*/
2518
2519static const u32 dmae_reg_go_c[] = {
2520	DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2521	DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2522	DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2523	DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2524};
2525
2526void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);
2527void bnx2x_notify_link_changed(struct bnx2x *bp);
2528
2529#define BNX2X_MF_SD_PROTOCOL(bp) \
2530	((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2531
2532#define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2533	(BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2534
2535#define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2536	(BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2537
2538#define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2539#define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2540
2541#define BNX2X_MF_EXT_PROTOCOL_FCOE(bp)  ((bp)->mf_ext_config & \
2542					 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2543
2544#define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp))
2545#define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \
2546				(BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2547				 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2548
2549#define SET_FLAG(value, mask, flag) \
2550	do {\
2551		(value) &= ~(mask);\
2552		(value) |= ((flag) << (mask##_SHIFT));\
2553	} while (0)
2554
2555#define GET_FLAG(value, mask) \
2556	(((value) & (mask)) >> (mask##_SHIFT))
2557
2558#define GET_FIELD(value, fname) \
2559	(((value) & (fname##_MASK)) >> (fname##_SHIFT))
2560
2561enum {
2562	SWITCH_UPDATE,
2563	AFEX_UPDATE,
2564};
2565
2566#define NUM_MACS	8
2567
2568void bnx2x_set_local_cmng(struct bnx2x *bp);
2569
2570void bnx2x_update_mng_version(struct bnx2x *bp);
2571
2572#define MCPR_SCRATCH_BASE(bp) \
2573	(CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
2574
2575#define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX))
2576
2577void bnx2x_init_ptp(struct bnx2x *bp);
2578int bnx2x_configure_ptp_filters(struct bnx2x *bp);
2579void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb);
2580
2581#define BNX2X_MAX_PHC_DRIFT 31000000
2582#define BNX2X_PTP_TX_TIMEOUT
2583
2584#endif /* bnx2x.h */
2585