bnx2x.h revision 2de67439c1f50e32fb54ca70786fcfa96c5bfd53
1/* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14#ifndef BNX2X_H 15#define BNX2X_H 16 17#include <linux/pci.h> 18#include <linux/netdevice.h> 19#include <linux/dma-mapping.h> 20#include <linux/types.h> 21#include <linux/pci_regs.h> 22 23/* compilation time flags */ 24 25/* define this to make the driver freeze on error to allow getting debug info 26 * (you will need to reboot afterwards) */ 27/* #define BNX2X_STOP_ON_ERROR */ 28 29#define DRV_MODULE_VERSION "1.78.02-0" 30#define DRV_MODULE_RELDATE "2013/01/14" 31#define BNX2X_BC_VER 0x040200 32 33#if defined(CONFIG_DCB) 34#define BCM_DCBNL 35#endif 36 37 38#include "bnx2x_hsi.h" 39 40#include "../cnic_if.h" 41 42 43#define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 44 45#include <linux/mdio.h> 46 47#include "bnx2x_reg.h" 48#include "bnx2x_fw_defs.h" 49#include "bnx2x_mfw_req.h" 50#include "bnx2x_link.h" 51#include "bnx2x_sp.h" 52#include "bnx2x_dcb.h" 53#include "bnx2x_stats.h" 54#include "bnx2x_vfpf.h" 55 56enum bnx2x_int_mode { 57 BNX2X_INT_MODE_MSIX, 58 BNX2X_INT_MODE_INTX, 59 BNX2X_INT_MODE_MSI 60}; 61 62/* error/debug prints */ 63 64#define DRV_MODULE_NAME "bnx2x" 65 66/* for messages that are currently off */ 67#define BNX2X_MSG_OFF 0x0 68#define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 69#define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 70#define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 71#define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 72#define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 73#define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 74#define BNX2X_MSG_IOV 0x0800000 75#define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 76#define BNX2X_MSG_ETHTOOL 0x4000000 77#define BNX2X_MSG_DCB 0x8000000 78 79/* regular debug print */ 80#define DP(__mask, fmt, ...) \ 81do { \ 82 if (unlikely(bp->msg_enable & (__mask))) \ 83 pr_notice("[%s:%d(%s)]" fmt, \ 84 __func__, __LINE__, \ 85 bp->dev ? (bp->dev->name) : "?", \ 86 ##__VA_ARGS__); \ 87} while (0) 88 89#define DP_CONT(__mask, fmt, ...) \ 90do { \ 91 if (unlikely(bp->msg_enable & (__mask))) \ 92 pr_cont(fmt, ##__VA_ARGS__); \ 93} while (0) 94 95/* errors debug print */ 96#define BNX2X_DBG_ERR(fmt, ...) \ 97do { \ 98 if (unlikely(netif_msg_probe(bp))) \ 99 pr_err("[%s:%d(%s)]" fmt, \ 100 __func__, __LINE__, \ 101 bp->dev ? (bp->dev->name) : "?", \ 102 ##__VA_ARGS__); \ 103} while (0) 104 105/* for errors (never masked) */ 106#define BNX2X_ERR(fmt, ...) \ 107do { \ 108 pr_err("[%s:%d(%s)]" fmt, \ 109 __func__, __LINE__, \ 110 bp->dev ? (bp->dev->name) : "?", \ 111 ##__VA_ARGS__); \ 112} while (0) 113 114#define BNX2X_ERROR(fmt, ...) \ 115 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 116 117 118/* before we have a dev->name use dev_info() */ 119#define BNX2X_DEV_INFO(fmt, ...) \ 120do { \ 121 if (unlikely(netif_msg_probe(bp))) \ 122 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 123} while (0) 124 125#ifdef BNX2X_STOP_ON_ERROR 126#define bnx2x_panic() \ 127do { \ 128 bp->panic = 1; \ 129 BNX2X_ERR("driver assert\n"); \ 130 bnx2x_panic_dump(bp, true); \ 131} while (0) 132#else 133#define bnx2x_panic() \ 134do { \ 135 bp->panic = 1; \ 136 BNX2X_ERR("driver assert\n"); \ 137 bnx2x_panic_dump(bp, false); \ 138} while (0) 139#endif 140 141#define bnx2x_mc_addr(ha) ((ha)->addr) 142#define bnx2x_uc_addr(ha) ((ha)->addr) 143 144#define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff)) 145#define U64_HI(x) ((u32)(((u64)(x)) >> 32)) 146#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 147 148 149#define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 150 151#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 152#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 153#define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 154 155#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 156#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 157#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 158 159#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 160#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 161 162#define REG_RD_DMAE(bp, offset, valp, len32) \ 163 do { \ 164 bnx2x_read_dmae(bp, offset, len32);\ 165 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 166 } while (0) 167 168#define REG_WR_DMAE(bp, offset, valp, len32) \ 169 do { \ 170 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 171 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 172 offset, len32); \ 173 } while (0) 174 175#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 176 REG_WR_DMAE(bp, offset, valp, len32) 177 178#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 179 do { \ 180 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 181 bnx2x_write_big_buf_wb(bp, addr, len32); \ 182 } while (0) 183 184#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 185 offsetof(struct shmem_region, field)) 186#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 187#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 188 189#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 190 offsetof(struct shmem2_region, field)) 191#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 192#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 193#define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 194 offsetof(struct mf_cfg, field)) 195#define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 196 offsetof(struct mf2_cfg, field)) 197 198#define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 199#define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 200 MF_CFG_ADDR(bp, field), (val)) 201#define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 202 203#define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 204 (SHMEM2_RD((bp), size) > \ 205 offsetof(struct shmem2_region, field))) 206 207#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 208#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 209 210/* SP SB indices */ 211 212/* General SP events - stats query, cfc delete, etc */ 213#define HC_SP_INDEX_ETH_DEF_CONS 3 214 215/* EQ completions */ 216#define HC_SP_INDEX_EQ_CONS 7 217 218/* FCoE L2 connection completions */ 219#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 220#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 221/* iSCSI L2 */ 222#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 223#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 224 225/* Special clients parameters */ 226 227/* SB indices */ 228/* FCoE L2 */ 229#define BNX2X_FCOE_L2_RX_INDEX \ 230 (&bp->def_status_blk->sp_sb.\ 231 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 232 233#define BNX2X_FCOE_L2_TX_INDEX \ 234 (&bp->def_status_blk->sp_sb.\ 235 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 236 237/** 238 * CIDs and CLIDs: 239 * CLIDs below is a CLID for func 0, then the CLID for other 240 * functions will be calculated by the formula: 241 * 242 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 243 * 244 */ 245enum { 246 BNX2X_ISCSI_ETH_CL_ID_IDX, 247 BNX2X_FCOE_ETH_CL_ID_IDX, 248 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 249}; 250 251#define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\ 252 (bp)->max_cos) 253 /* iSCSI L2 */ 254#define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 255 /* FCoE L2 */ 256#define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 257 258#define CNIC_SUPPORT(bp) ((bp)->cnic_support) 259#define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 260#define CNIC_LOADED(bp) ((bp)->cnic_loaded) 261#define FCOE_INIT(bp) ((bp)->fcoe_init) 262 263#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 264 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 265 266#define SM_RX_ID 0 267#define SM_TX_ID 1 268 269/* defines for multiple tx priority indices */ 270#define FIRST_TX_ONLY_COS_INDEX 1 271#define FIRST_TX_COS_INDEX 0 272 273/* rules for calculating the cids of tx-only connections */ 274#define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 275#define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 276 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 277 278/* fp index inside class of service range */ 279#define FP_COS_TO_TXQ(fp, cos, bp) \ 280 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 281 282/* Indexes for transmission queues array: 283 * txdata for RSS i CoS j is at location i + (j * num of RSS) 284 * txdata for FCoE (if exist) is at location max cos * num of RSS 285 * txdata for FWD (if exist) is one location after FCoE 286 * txdata for OOO (if exist) is one location after FWD 287 */ 288enum { 289 FCOE_TXQ_IDX_OFFSET, 290 FWD_TXQ_IDX_OFFSET, 291 OOO_TXQ_IDX_OFFSET, 292}; 293#define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 294#define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 295 296/* fast path */ 297/* 298 * This driver uses new build_skb() API : 299 * RX ring buffer contains pointer to kmalloc() data only, 300 * skb are built only after Hardware filled the frame. 301 */ 302struct sw_rx_bd { 303 u8 *data; 304 DEFINE_DMA_UNMAP_ADDR(mapping); 305}; 306 307struct sw_tx_bd { 308 struct sk_buff *skb; 309 u16 first_bd; 310 u8 flags; 311/* Set on the first BD descriptor when there is a split BD */ 312#define BNX2X_TSO_SPLIT_BD (1<<0) 313}; 314 315struct sw_rx_page { 316 struct page *page; 317 DEFINE_DMA_UNMAP_ADDR(mapping); 318}; 319 320union db_prod { 321 struct doorbell_set_prod data; 322 u32 raw; 323}; 324 325/* dropless fc FW/HW related params */ 326#define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 327#define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 328 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 329 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 330#define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 331#define FW_PREFETCH_CNT 16 332#define DROPLESS_FC_HEADROOM 100 333 334/* MC hsi */ 335#define BCM_PAGE_SHIFT 12 336#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 337#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 338#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 339 340#define PAGES_PER_SGE_SHIFT 0 341#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 342#define SGE_PAGE_SIZE PAGE_SIZE 343#define SGE_PAGE_SHIFT PAGE_SHIFT 344#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 345#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 346#define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ 347 SGE_PAGES), 0xffff) 348 349/* SGE ring related macros */ 350#define NUM_RX_SGE_PAGES 2 351#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 352#define NEXT_PAGE_SGE_DESC_CNT 2 353#define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 354/* RX_SGE_CNT is promised to be a power of 2 */ 355#define RX_SGE_MASK (RX_SGE_CNT - 1) 356#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 357#define MAX_RX_SGE (NUM_RX_SGE - 1) 358#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 359 (MAX_RX_SGE_CNT - 1)) ? \ 360 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 361 (x) + 1) 362#define RX_SGE(x) ((x) & MAX_RX_SGE) 363 364/* 365 * Number of required SGEs is the sum of two: 366 * 1. Number of possible opened aggregations (next packet for 367 * these aggregations will probably consume SGE immidiatelly) 368 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 369 * after placement on BD for new TPA aggregation) 370 * 371 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 372 */ 373#define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 374 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 375#define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 376 MAX_RX_SGE_CNT) 377#define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 378 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 379#define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 380 381/* Manipulate a bit vector defined as an array of u64 */ 382 383/* Number of bits in one sge_mask array element */ 384#define BIT_VEC64_ELEM_SZ 64 385#define BIT_VEC64_ELEM_SHIFT 6 386#define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 387 388 389#define __BIT_VEC64_SET_BIT(el, bit) \ 390 do { \ 391 el = ((el) | ((u64)0x1 << (bit))); \ 392 } while (0) 393 394#define __BIT_VEC64_CLEAR_BIT(el, bit) \ 395 do { \ 396 el = ((el) & (~((u64)0x1 << (bit)))); \ 397 } while (0) 398 399 400#define BIT_VEC64_SET_BIT(vec64, idx) \ 401 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 402 (idx) & BIT_VEC64_ELEM_MASK) 403 404#define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 405 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 406 (idx) & BIT_VEC64_ELEM_MASK) 407 408#define BIT_VEC64_TEST_BIT(vec64, idx) \ 409 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 410 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 411 412/* Creates a bitmask of all ones in less significant bits. 413 idx - index of the most significant bit in the created mask */ 414#define BIT_VEC64_ONES_MASK(idx) \ 415 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 416#define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 417 418/*******************************************************/ 419 420 421 422/* Number of u64 elements in SGE mask array */ 423#define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 424#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 425#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 426 427union host_hc_status_block { 428 /* pointer to fp status block e1x */ 429 struct host_hc_status_block_e1x *e1x_sb; 430 /* pointer to fp status block e2 */ 431 struct host_hc_status_block_e2 *e2_sb; 432}; 433 434struct bnx2x_agg_info { 435 /* 436 * First aggregation buffer is a data buffer, the following - are pages. 437 * We will preallocate the data buffer for each aggregation when 438 * we open the interface and will replace the BD at the consumer 439 * with this one when we receive the TPA_START CQE in order to 440 * keep the Rx BD ring consistent. 441 */ 442 struct sw_rx_bd first_buf; 443 u8 tpa_state; 444#define BNX2X_TPA_START 1 445#define BNX2X_TPA_STOP 2 446#define BNX2X_TPA_ERROR 3 447 u8 placement_offset; 448 u16 parsing_flags; 449 u16 vlan_tag; 450 u16 len_on_bd; 451 u32 rxhash; 452 bool l4_rxhash; 453 u16 gro_size; 454 u16 full_page; 455}; 456 457#define Q_STATS_OFFSET32(stat_name) \ 458 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 459 460struct bnx2x_fp_txdata { 461 462 struct sw_tx_bd *tx_buf_ring; 463 464 union eth_tx_bd_types *tx_desc_ring; 465 dma_addr_t tx_desc_mapping; 466 467 u32 cid; 468 469 union db_prod tx_db; 470 471 u16 tx_pkt_prod; 472 u16 tx_pkt_cons; 473 u16 tx_bd_prod; 474 u16 tx_bd_cons; 475 476 unsigned long tx_pkt; 477 478 __le16 *tx_cons_sb; 479 480 int txq_index; 481 struct bnx2x_fastpath *parent_fp; 482 int tx_ring_size; 483}; 484 485enum bnx2x_tpa_mode_t { 486 TPA_MODE_LRO, 487 TPA_MODE_GRO 488}; 489 490struct bnx2x_fastpath { 491 struct bnx2x *bp; /* parent */ 492 493#define BNX2X_NAPI_WEIGHT 128 494 struct napi_struct napi; 495 union host_hc_status_block status_blk; 496 /* chip independed shortcuts into sb structure */ 497 __le16 *sb_index_values; 498 __le16 *sb_running_index; 499 /* chip independed shortcut into rx_prods_offset memory */ 500 u32 ustorm_rx_prods_offset; 501 502 u32 rx_buf_size; 503 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 504 dma_addr_t status_blk_mapping; 505 506 enum bnx2x_tpa_mode_t mode; 507 508 u8 max_cos; /* actual number of active tx coses */ 509 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 510 511 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 512 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 513 514 struct eth_rx_bd *rx_desc_ring; 515 dma_addr_t rx_desc_mapping; 516 517 union eth_rx_cqe *rx_comp_ring; 518 dma_addr_t rx_comp_mapping; 519 520 /* SGE ring */ 521 struct eth_rx_sge *rx_sge_ring; 522 dma_addr_t rx_sge_mapping; 523 524 u64 sge_mask[RX_SGE_MASK_LEN]; 525 526 u32 cid; 527 528 __le16 fp_hc_idx; 529 530 u8 index; /* number in fp array */ 531 u8 rx_queue; /* index for skb_record */ 532 u8 cl_id; /* eth client id */ 533 u8 cl_qzone_id; 534 u8 fw_sb_id; /* status block number in FW */ 535 u8 igu_sb_id; /* status block number in HW */ 536 537 u16 rx_bd_prod; 538 u16 rx_bd_cons; 539 u16 rx_comp_prod; 540 u16 rx_comp_cons; 541 u16 rx_sge_prod; 542 /* The last maximal completed SGE */ 543 u16 last_max_sge; 544 __le16 *rx_cons_sb; 545 unsigned long rx_pkt, 546 rx_calls; 547 548 /* TPA related */ 549 struct bnx2x_agg_info *tpa_info; 550 u8 disable_tpa; 551#ifdef BNX2X_STOP_ON_ERROR 552 u64 tpa_queue_used; 553#endif 554 /* The size is calculated using the following: 555 sizeof name field from netdev structure + 556 4 ('-Xx-' string) + 557 4 (for the digits and to make it DWORD aligned) */ 558#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 559 char name[FP_NAME_SIZE]; 560}; 561 562#define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 563#define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 564#define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 565#define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 566 567/* Use 2500 as a mini-jumbo MTU for FCoE */ 568#define BNX2X_FCOE_MINI_JUMBO_MTU 2500 569 570#define FCOE_IDX_OFFSET 0 571 572#define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 573 FCOE_IDX_OFFSET) 574#define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 575#define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 576#define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 577#define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 578#define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 579 txdata_ptr[FIRST_TX_COS_INDEX] \ 580 ->var) 581 582 583#define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 584#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 585#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 586 587 588/* MC hsi */ 589#define MAX_FETCH_BD 13 /* HW max BDs per packet */ 590#define RX_COPY_THRESH 92 591 592#define NUM_TX_RINGS 16 593#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 594#define NEXT_PAGE_TX_DESC_CNT 1 595#define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 596#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 597#define MAX_TX_BD (NUM_TX_BD - 1) 598#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 599#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 600 (MAX_TX_DESC_CNT - 1)) ? \ 601 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 602 (x) + 1) 603#define TX_BD(x) ((x) & MAX_TX_BD) 604#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 605 606/* number of NEXT_PAGE descriptors may be required during placement */ 607#define NEXT_CNT_PER_TX_PKT(bds) \ 608 (((bds) + MAX_TX_DESC_CNT - 1) / \ 609 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 610/* max BDs per tx packet w/o next_pages: 611 * START_BD - describes packed 612 * START_BD(splitted) - includes unpaged data segment for GSO 613 * PARSING_BD - for TSO and CSUM data 614 * Frag BDs - decribes pages for frags 615 */ 616#define BDS_PER_TX_PKT 3 617#define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 618/* max BDs per tx packet including next pages */ 619#define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 620 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 621 622/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 623#define NUM_RX_RINGS 8 624#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 625#define NEXT_PAGE_RX_DESC_CNT 2 626#define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 627#define RX_DESC_MASK (RX_DESC_CNT - 1) 628#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 629#define MAX_RX_BD (NUM_RX_BD - 1) 630#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 631 632/* dropless fc calculations for BDs 633 * 634 * Number of BDs should as number of buffers in BRB: 635 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 636 * "next" elements on each page 637 */ 638#define NUM_BD_REQ BRB_SIZE(bp) 639#define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 640 MAX_RX_DESC_CNT) 641#define BD_TH_LO(bp) (NUM_BD_REQ + \ 642 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 643 FW_DROP_LEVEL(bp)) 644#define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 645 646#define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 647 648#define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 649 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 650 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 651#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 652#define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 653#define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 654 MIN_RX_AVAIL)) 655 656#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 657 (MAX_RX_DESC_CNT - 1)) ? \ 658 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 659 (x) + 1) 660#define RX_BD(x) ((x) & MAX_RX_BD) 661 662/* 663 * As long as CQE is X times bigger than BD entry we have to allocate X times 664 * more pages for CQ ring in order to keep it balanced with BD ring 665 */ 666#define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 667#define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 668#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 669#define NEXT_PAGE_RCQ_DESC_CNT 1 670#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 671#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 672#define MAX_RCQ_BD (NUM_RCQ_BD - 1) 673#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 674#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 675 (MAX_RCQ_DESC_CNT - 1)) ? \ 676 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 677 (x) + 1) 678#define RCQ_BD(x) ((x) & MAX_RCQ_BD) 679 680/* dropless fc calculations for RCQs 681 * 682 * Number of RCQs should be as number of buffers in BRB: 683 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 684 * "next" elements on each page 685 */ 686#define NUM_RCQ_REQ BRB_SIZE(bp) 687#define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 688 MAX_RCQ_DESC_CNT) 689#define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 690 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 691 FW_DROP_LEVEL(bp)) 692#define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 693 694 695/* This is needed for determining of last_max */ 696#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 697#define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 698 699 700#define BNX2X_SWCID_SHIFT 17 701#define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 702 703/* used on a CID received from the HW */ 704#define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 705#define CQE_CMD(x) (le32_to_cpu(x) >> \ 706 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 707 708#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 709 le32_to_cpu((bd)->addr_lo)) 710#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 711 712#define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 713#define BNX2X_DB_SHIFT 7 /* 128 bytes*/ 714#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 715#error "Min DB doorbell stride is 8" 716#endif 717#define DPM_TRIGER_TYPE 0x40 718#define DOORBELL(bp, cid, val) \ 719 do { \ 720 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ 721 DPM_TRIGER_TYPE); \ 722 } while (0) 723 724 725/* TX CSUM helpers */ 726#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 727 skb->csum_offset) 728#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 729 skb->csum_offset)) 730 731#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) 732 733#define XMIT_PLAIN 0 734#define XMIT_CSUM_V4 0x1 735#define XMIT_CSUM_V6 0x2 736#define XMIT_CSUM_TCP 0x4 737#define XMIT_GSO_V4 0x8 738#define XMIT_GSO_V6 0x10 739 740#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) 741#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) 742 743 744/* stuff added to make the code fit 80Col */ 745#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 746#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 747#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 748#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 749#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 750 751#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 752 753#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 754 (((le16_to_cpu(flags) & \ 755 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 756 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 757 == PRS_FLAG_OVERETH_IPV4) 758#define BNX2X_RX_SUM_FIX(cqe) \ 759 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 760 761 762#define FP_USB_FUNC_OFF \ 763 offsetof(struct cstorm_status_block_u, func) 764#define FP_CSB_FUNC_OFF \ 765 offsetof(struct cstorm_status_block_c, func) 766 767#define HC_INDEX_ETH_RX_CQ_CONS 1 768 769#define HC_INDEX_OOO_TX_CQ_CONS 4 770 771#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 772 773#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 774 775#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 776 777#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 778 779#define BNX2X_RX_SB_INDEX \ 780 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 781 782#define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 783 784#define BNX2X_TX_SB_INDEX_COS0 \ 785 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 786 787/* end of fast path */ 788 789/* common */ 790 791struct bnx2x_common { 792 793 u32 chip_id; 794/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 795#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 796 797#define CHIP_NUM(bp) (bp->common.chip_id >> 16) 798#define CHIP_NUM_57710 0x164e 799#define CHIP_NUM_57711 0x164f 800#define CHIP_NUM_57711E 0x1650 801#define CHIP_NUM_57712 0x1662 802#define CHIP_NUM_57712_MF 0x1663 803#define CHIP_NUM_57712_VF 0x166f 804#define CHIP_NUM_57713 0x1651 805#define CHIP_NUM_57713E 0x1652 806#define CHIP_NUM_57800 0x168a 807#define CHIP_NUM_57800_MF 0x16a5 808#define CHIP_NUM_57800_VF 0x16a9 809#define CHIP_NUM_57810 0x168e 810#define CHIP_NUM_57810_MF 0x16ae 811#define CHIP_NUM_57810_VF 0x16af 812#define CHIP_NUM_57811 0x163d 813#define CHIP_NUM_57811_MF 0x163e 814#define CHIP_NUM_57811_VF 0x163f 815#define CHIP_NUM_57840_OBSOLETE 0x168d 816#define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 817#define CHIP_NUM_57840_4_10 0x16a1 818#define CHIP_NUM_57840_2_20 0x16a2 819#define CHIP_NUM_57840_MF 0x16a4 820#define CHIP_NUM_57840_VF 0x16ad 821#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 822#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 823#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 824#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 825#define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) 826#define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 827#define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 828#define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 829#define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) 830#define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 831#define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 832#define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) 833#define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 834#define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 835#define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) 836#define CHIP_IS_57840(bp) \ 837 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 838 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 839 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 840#define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 841 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 842#define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) 843#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 844 CHIP_IS_57711E(bp)) 845#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 846 CHIP_IS_57712_MF(bp)) 847#define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 848 CHIP_IS_57800_MF(bp) || \ 849 CHIP_IS_57810(bp) || \ 850 CHIP_IS_57810_MF(bp) || \ 851 CHIP_IS_57810_VF(bp) || \ 852 CHIP_IS_57811(bp) || \ 853 CHIP_IS_57811_MF(bp) || \ 854 CHIP_IS_57811_VF(bp) || \ 855 CHIP_IS_57840(bp) || \ 856 CHIP_IS_57840_MF(bp) || \ 857 CHIP_IS_57840_VF(bp)) 858#define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 859#define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 860#define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 861 862#define CHIP_REV_SHIFT 12 863#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 864#define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 865#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 866#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 867/* assume maximum 5 revisions */ 868#define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 869/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 870#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 871 !(CHIP_REV_VAL(bp) & 0x00001000)) 872/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 873#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 874 (CHIP_REV_VAL(bp) & 0x00001000)) 875 876#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 877 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 878 879#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 880#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 881#define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 882 (CHIP_REV_SHIFT + 1)) \ 883 << CHIP_REV_SHIFT) 884#define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 885 CHIP_REV_SIM(bp) :\ 886 CHIP_REV_VAL(bp)) 887#define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 888 (CHIP_REV(bp) == CHIP_REV_Bx)) 889#define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 890 (CHIP_REV(bp) == CHIP_REV_Ax)) 891/* This define is used in two main places: 892 * 1. In the early stages of nic_load, to know if to configrue Parser / Searcher 893 * to nic-only mode or to offload mode. Offload mode is configured if either the 894 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 895 * registered for this port (which means that the user wants storage services). 896 * 2. During cnic-related load, to know if offload mode is already configured in 897 * the HW or needs to be configrued. 898 * Since the transition from nic-mode to offload-mode in HW causes traffic 899 * coruption, nic-mode is configured only in ports on which storage services 900 * where never requested. 901 */ 902#define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 903 904 int flash_size; 905#define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 906#define BNX2X_NVRAM_TIMEOUT_COUNT 30000 907#define BNX2X_NVRAM_PAGE_SIZE 256 908 909 u32 shmem_base; 910 u32 shmem2_base; 911 u32 mf_cfg_base; 912 u32 mf2_cfg_base; 913 914 u32 hw_config; 915 916 u32 bc_ver; 917 918 u8 int_block; 919#define INT_BLOCK_HC 0 920#define INT_BLOCK_IGU 1 921#define INT_BLOCK_MODE_NORMAL 0 922#define INT_BLOCK_MODE_BW_COMP 2 923#define CHIP_INT_MODE_IS_NBC(bp) \ 924 (!CHIP_IS_E1x(bp) && \ 925 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 926#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 927 928 u8 chip_port_mode; 929#define CHIP_4_PORT_MODE 0x0 930#define CHIP_2_PORT_MODE 0x1 931#define CHIP_PORT_MODE_NONE 0x2 932#define CHIP_MODE(bp) (bp->common.chip_port_mode) 933#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 934 935 u32 boot_mode; 936}; 937 938/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 939#define BNX2X_IGU_STAS_MSG_VF_CNT 64 940#define BNX2X_IGU_STAS_MSG_PF_CNT 4 941 942#define MAX_IGU_ATTN_ACK_TO 100 943/* end of common */ 944 945/* port */ 946 947struct bnx2x_port { 948 u32 pmf; 949 950 u32 link_config[LINK_CONFIG_SIZE]; 951 952 u32 supported[LINK_CONFIG_SIZE]; 953/* link settings - missing defines */ 954#define SUPPORTED_2500baseX_Full (1 << 15) 955 956 u32 advertising[LINK_CONFIG_SIZE]; 957/* link settings - missing defines */ 958#define ADVERTISED_2500baseX_Full (1 << 15) 959 960 u32 phy_addr; 961 962 /* used to synchronize phy accesses */ 963 struct mutex phy_mutex; 964 965 u32 port_stx; 966 967 struct nig_stats old_nig_stats; 968}; 969 970/* end of port */ 971 972#define STATS_OFFSET32(stat_name) \ 973 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 974 975/* slow path */ 976 977/* slow path work-queue */ 978extern struct workqueue_struct *bnx2x_wq; 979 980#define BNX2X_MAX_NUM_OF_VFS 64 981#define BNX2X_VF_CID_WND 0 982#define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 983#define BNX2X_CLIENTS_PER_VF 1 984#define BNX2X_FIRST_VF_CID 256 985#define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 986#define BNX2X_VF_ID_INVALID 0xFF 987 988/* 989 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 990 * control by the number of fast-path status blocks supported by the 991 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 992 * status block represents an independent interrupts context that can 993 * serve a regular L2 networking queue. However special L2 queues such 994 * as the FCoE queue do not require a FP-SB and other components like 995 * the CNIC may consume FP-SB reducing the number of possible L2 queues 996 * 997 * If the maximum number of FP-SB available is X then: 998 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 999 * regular L2 queues is Y=X-1 1000 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 1001 * c. If the FCoE L2 queue is supported the actual number of L2 queues 1002 * is Y+1 1003 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 1004 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 1005 * FP interrupt context for the CNIC). 1006 * e. The number of HW context (CID count) is always X or X+1 if FCoE 1007 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 1008 */ 1009 1010/* fast-path interrupt contexts E1x */ 1011#define FP_SB_MAX_E1x 16 1012/* fast-path interrupt contexts E2 */ 1013#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 1014 1015union cdu_context { 1016 struct eth_context eth; 1017 char pad[1024]; 1018}; 1019 1020/* CDU host DB constants */ 1021#define CDU_ILT_PAGE_SZ_HW 2 1022#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1023#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1024 1025#define CNIC_ISCSI_CID_MAX 256 1026#define CNIC_FCOE_CID_MAX 2048 1027#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1028#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1029 1030#define QM_ILT_PAGE_SZ_HW 0 1031#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1032#define QM_CID_ROUND 1024 1033 1034/* TM (timers) host DB constants */ 1035#define TM_ILT_PAGE_SZ_HW 0 1036#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1037/* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 1038#define TM_CONN_NUM 1024 1039#define TM_ILT_SZ (8 * TM_CONN_NUM) 1040#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1041 1042/* SRC (Searcher) host DB constants */ 1043#define SRC_ILT_PAGE_SZ_HW 0 1044#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1045#define SRC_HASH_BITS 10 1046#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1047#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1048#define SRC_T2_SZ SRC_ILT_SZ 1049#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1050 1051#define MAX_DMAE_C 8 1052 1053/* DMA memory not used in fastpath */ 1054struct bnx2x_slowpath { 1055 union { 1056 struct mac_configuration_cmd e1x; 1057 struct eth_classify_rules_ramrod_data e2; 1058 } mac_rdata; 1059 1060 1061 union { 1062 struct tstorm_eth_mac_filter_config e1x; 1063 struct eth_filter_rules_ramrod_data e2; 1064 } rx_mode_rdata; 1065 1066 union { 1067 struct mac_configuration_cmd e1; 1068 struct eth_multicast_rules_ramrod_data e2; 1069 } mcast_rdata; 1070 1071 struct eth_rss_update_ramrod_data rss_rdata; 1072 1073 /* Queue State related ramrods are always sent under rtnl_lock */ 1074 union { 1075 struct client_init_ramrod_data init_data; 1076 struct client_update_ramrod_data update_data; 1077 } q_rdata; 1078 1079 union { 1080 struct function_start_data func_start; 1081 /* pfc configuration for DCBX ramrod */ 1082 struct flow_control_configuration pfc_config; 1083 } func_rdata; 1084 1085 /* afex ramrod can not be a part of func_rdata union because these 1086 * events might arrive in parallel to other events from func_rdata. 1087 * Therefore, if they would have been defined in the same union, 1088 * data can get corrupted. 1089 */ 1090 struct afex_vif_list_ramrod_data func_afex_rdata; 1091 1092 /* used by dmae command executer */ 1093 struct dmae_command dmae[MAX_DMAE_C]; 1094 1095 u32 stats_comp; 1096 union mac_stats mac_stats; 1097 struct nig_stats nig_stats; 1098 struct host_port_stats port_stats; 1099 struct host_func_stats func_stats; 1100 1101 u32 wb_comp; 1102 u32 wb_data[4]; 1103 1104 union drv_info_to_mcp drv_info_to_mcp; 1105}; 1106 1107#define bnx2x_sp(bp, var) (&bp->slowpath->var) 1108#define bnx2x_sp_mapping(bp, var) \ 1109 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1110 1111 1112/* attn group wiring */ 1113#define MAX_DYNAMIC_ATTN_GRPS 8 1114 1115struct attn_route { 1116 u32 sig[5]; 1117}; 1118 1119struct iro { 1120 u32 base; 1121 u16 m1; 1122 u16 m2; 1123 u16 m3; 1124 u16 size; 1125}; 1126 1127struct hw_context { 1128 union cdu_context *vcxt; 1129 dma_addr_t cxt_mapping; 1130 size_t size; 1131}; 1132 1133/* forward */ 1134struct bnx2x_ilt; 1135 1136struct bnx2x_vfdb; 1137 1138enum bnx2x_recovery_state { 1139 BNX2X_RECOVERY_DONE, 1140 BNX2X_RECOVERY_INIT, 1141 BNX2X_RECOVERY_WAIT, 1142 BNX2X_RECOVERY_FAILED, 1143 BNX2X_RECOVERY_NIC_LOADING 1144}; 1145 1146/* 1147 * Event queue (EQ or event ring) MC hsi 1148 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1149 */ 1150#define NUM_EQ_PAGES 1 1151#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1152#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1153#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1154#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1155#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1156 1157/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1158#define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1159 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1160 1161/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1162#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1163 1164#define BNX2X_EQ_INDEX \ 1165 (&bp->def_status_blk->sp_sb.\ 1166 index_values[HC_SP_INDEX_EQ_CONS]) 1167 1168/* This is a data that will be used to create a link report message. 1169 * We will keep the data used for the last link report in order 1170 * to prevent reporting the same link parameters twice. 1171 */ 1172struct bnx2x_link_report_data { 1173 u16 line_speed; /* Effective line speed */ 1174 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1175}; 1176 1177enum { 1178 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1179 BNX2X_LINK_REPORT_LINK_DOWN, 1180 BNX2X_LINK_REPORT_RX_FC_ON, 1181 BNX2X_LINK_REPORT_TX_FC_ON, 1182}; 1183 1184enum { 1185 BNX2X_PORT_QUERY_IDX, 1186 BNX2X_PF_QUERY_IDX, 1187 BNX2X_FCOE_QUERY_IDX, 1188 BNX2X_FIRST_QUEUE_QUERY_IDX, 1189}; 1190 1191struct bnx2x_fw_stats_req { 1192 struct stats_query_header hdr; 1193 struct stats_query_entry query[FP_SB_MAX_E1x+ 1194 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1195}; 1196 1197struct bnx2x_fw_stats_data { 1198 struct stats_counter storm_counters; 1199 struct per_port_stats port; 1200 struct per_pf_stats pf; 1201 struct fcoe_statistics_params fcoe; 1202 struct per_queue_stats queue_stats[1]; 1203}; 1204 1205/* Public slow path states */ 1206enum { 1207 BNX2X_SP_RTNL_SETUP_TC, 1208 BNX2X_SP_RTNL_TX_TIMEOUT, 1209 BNX2X_SP_RTNL_FAN_FAILURE, 1210 BNX2X_SP_RTNL_AFEX_F_UPDATE, 1211 BNX2X_SP_RTNL_ENABLE_SRIOV, 1212 BNX2X_SP_RTNL_VFPF_MCAST, 1213 BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, 1214}; 1215 1216 1217struct bnx2x_prev_path_list { 1218 u8 bus; 1219 u8 slot; 1220 u8 path; 1221 struct list_head list; 1222 u8 undi; 1223}; 1224 1225struct bnx2x_sp_objs { 1226 /* MACs object */ 1227 struct bnx2x_vlan_mac_obj mac_obj; 1228 1229 /* Queue State object */ 1230 struct bnx2x_queue_sp_obj q_obj; 1231}; 1232 1233struct bnx2x_fp_stats { 1234 struct tstorm_per_queue_stats old_tclient; 1235 struct ustorm_per_queue_stats old_uclient; 1236 struct xstorm_per_queue_stats old_xclient; 1237 struct bnx2x_eth_q_stats eth_q_stats; 1238 struct bnx2x_eth_q_stats_old eth_q_stats_old; 1239}; 1240 1241struct bnx2x { 1242 /* Fields used in the tx and intr/napi performance paths 1243 * are grouped together in the beginning of the structure 1244 */ 1245 struct bnx2x_fastpath *fp; 1246 struct bnx2x_sp_objs *sp_objs; 1247 struct bnx2x_fp_stats *fp_stats; 1248 struct bnx2x_fp_txdata *bnx2x_txq; 1249 void __iomem *regview; 1250 void __iomem *doorbells; 1251 u16 db_size; 1252 1253 u8 pf_num; /* absolute PF number */ 1254 u8 pfid; /* per-path PF number */ 1255 int base_fw_ndsb; /**/ 1256#define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1257#define BP_PORT(bp) (bp->pfid & 1) 1258#define BP_FUNC(bp) (bp->pfid) 1259#define BP_ABS_FUNC(bp) (bp->pf_num) 1260#define BP_VN(bp) ((bp)->pfid >> 1) 1261#define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1262#define BP_L_ID(bp) (BP_VN(bp) << 2) 1263#define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1264 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1265#define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1266 1267#ifdef CONFIG_BNX2X_SRIOV 1268 /* vf pf channel mailbox contains request and response buffers */ 1269 struct bnx2x_vf_mbx_msg *vf2pf_mbox; 1270 dma_addr_t vf2pf_mbox_mapping; 1271 1272 /* we set aside a copy of the acquire response */ 1273 struct pfvf_acquire_resp_tlv acquire_resp; 1274 1275 /* bulletin board for messages from pf to vf */ 1276 union pf_vf_bulletin *pf2vf_bulletin; 1277 dma_addr_t pf2vf_bulletin_mapping; 1278 1279 struct pf_vf_bulletin_content old_bulletin; 1280#endif /* CONFIG_BNX2X_SRIOV */ 1281 1282 struct net_device *dev; 1283 struct pci_dev *pdev; 1284 1285 const struct iro *iro_arr; 1286#define IRO (bp->iro_arr) 1287 1288 enum bnx2x_recovery_state recovery_state; 1289 int is_leader; 1290 struct msix_entry *msix_table; 1291 1292 int tx_ring_size; 1293 1294/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1295#define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1296#define ETH_MIN_PACKET_SIZE 60 1297#define ETH_MAX_PACKET_SIZE 1500 1298#define ETH_MAX_JUMBO_PACKET_SIZE 9600 1299/* TCP with Timestamp Option (32) + IPv6 (40) */ 1300#define ETH_MAX_TPA_HEADER_SIZE 72 1301 1302 /* Max supported alignment is 256 (8 shift) */ 1303#define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1304 1305 /* FW uses 2 Cache lines Alignment for start packet and size 1306 * 1307 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1308 * at the end of skb->data, to avoid wasting a full cache line. 1309 * This reduces memory use (skb->truesize). 1310 */ 1311#define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1312 1313#define BNX2X_FW_RX_ALIGN_END \ 1314 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1315 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1316 1317#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1318 1319 struct host_sp_status_block *def_status_blk; 1320#define DEF_SB_IGU_ID 16 1321#define DEF_SB_ID HC_SP_SB_ID 1322 __le16 def_idx; 1323 __le16 def_att_idx; 1324 u32 attn_state; 1325 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1326 1327 /* slow path ring */ 1328 struct eth_spe *spq; 1329 dma_addr_t spq_mapping; 1330 u16 spq_prod_idx; 1331 struct eth_spe *spq_prod_bd; 1332 struct eth_spe *spq_last_bd; 1333 __le16 *dsb_sp_prod; 1334 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1335 /* used to synchronize spq accesses */ 1336 spinlock_t spq_lock; 1337 1338 /* event queue */ 1339 union event_ring_elem *eq_ring; 1340 dma_addr_t eq_mapping; 1341 u16 eq_prod; 1342 u16 eq_cons; 1343 __le16 *eq_cons_sb; 1344 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1345 1346 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1347 u16 stats_pending; 1348 /* Counter for completed statistics ramrods */ 1349 u16 stats_comp; 1350 1351 /* End of fields used in the performance code paths */ 1352 1353 int panic; 1354 int msg_enable; 1355 1356 u32 flags; 1357#define PCIX_FLAG (1 << 0) 1358#define PCI_32BIT_FLAG (1 << 1) 1359#define ONE_PORT_FLAG (1 << 2) 1360#define NO_WOL_FLAG (1 << 3) 1361#define USING_DAC_FLAG (1 << 4) 1362#define USING_MSIX_FLAG (1 << 5) 1363#define USING_MSI_FLAG (1 << 6) 1364#define DISABLE_MSI_FLAG (1 << 7) 1365#define TPA_ENABLE_FLAG (1 << 8) 1366#define NO_MCP_FLAG (1 << 9) 1367#define GRO_ENABLE_FLAG (1 << 10) 1368#define MF_FUNC_DIS (1 << 11) 1369#define OWN_CNIC_IRQ (1 << 12) 1370#define NO_ISCSI_OOO_FLAG (1 << 13) 1371#define NO_ISCSI_FLAG (1 << 14) 1372#define NO_FCOE_FLAG (1 << 15) 1373#define BC_SUPPORTS_PFC_STATS (1 << 17) 1374#define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 1375#define USING_SINGLE_MSIX_FLAG (1 << 20) 1376#define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 1377#define IS_VF_FLAG (1 << 22) 1378 1379#define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 1380 1381#ifdef CONFIG_BNX2X_SRIOV 1382#define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 1383#define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 1384#else 1385#define IS_VF(bp) false 1386#define IS_PF(bp) true 1387#endif 1388 1389#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1390#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1391#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1392 1393 u8 cnic_support; 1394 bool cnic_enabled; 1395 bool cnic_loaded; 1396 struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 1397 1398 /* Flag that indicates that we can start looking for FCoE L2 queue 1399 * completions in the default status block. 1400 */ 1401 bool fcoe_init; 1402 1403 int pm_cap; 1404 int mrrs; 1405 1406 struct delayed_work sp_task; 1407 atomic_t interrupt_occurred; 1408 struct delayed_work sp_rtnl_task; 1409 1410 struct delayed_work period_task; 1411 struct timer_list timer; 1412 int current_interval; 1413 1414 u16 fw_seq; 1415 u16 fw_drv_pulse_wr_seq; 1416 u32 func_stx; 1417 1418 struct link_params link_params; 1419 struct link_vars link_vars; 1420 u32 link_cnt; 1421 struct bnx2x_link_report_data last_reported_link; 1422 1423 struct mdio_if_info mdio; 1424 1425 struct bnx2x_common common; 1426 struct bnx2x_port port; 1427 1428 struct cmng_init cmng; 1429 1430 u32 mf_config[E1HVN_MAX]; 1431 u32 mf_ext_config; 1432 u32 path_has_ovlan; /* E3 */ 1433 u16 mf_ov; 1434 u8 mf_mode; 1435#define IS_MF(bp) (bp->mf_mode != 0) 1436#define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1437#define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1438#define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1439 1440 u8 wol; 1441 1442 int rx_ring_size; 1443 1444 u16 tx_quick_cons_trip_int; 1445 u16 tx_quick_cons_trip; 1446 u16 tx_ticks_int; 1447 u16 tx_ticks; 1448 1449 u16 rx_quick_cons_trip_int; 1450 u16 rx_quick_cons_trip; 1451 u16 rx_ticks_int; 1452 u16 rx_ticks; 1453/* Maximal coalescing timeout in us */ 1454#define BNX2X_MAX_COALESCE_TOUT (0xf0*12) 1455 1456 u32 lin_cnt; 1457 1458 u16 state; 1459#define BNX2X_STATE_CLOSED 0 1460#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1461#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1462#define BNX2X_STATE_OPEN 0x3000 1463#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1464#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1465 1466#define BNX2X_STATE_DIAG 0xe000 1467#define BNX2X_STATE_ERROR 0xf000 1468 1469#define BNX2X_MAX_PRIORITY 8 1470#define BNX2X_MAX_ENTRIES_PER_PRI 16 1471#define BNX2X_MAX_COS 3 1472#define BNX2X_MAX_TX_COS 2 1473 int num_queues; 1474 uint num_ethernet_queues; 1475 uint num_cnic_queues; 1476 int num_napi_queues; 1477 int disable_tpa; 1478 1479 u32 rx_mode; 1480#define BNX2X_RX_MODE_NONE 0 1481#define BNX2X_RX_MODE_NORMAL 1 1482#define BNX2X_RX_MODE_ALLMULTI 2 1483#define BNX2X_RX_MODE_PROMISC 3 1484#define BNX2X_MAX_MULTICAST 64 1485 1486 u8 igu_dsb_id; 1487 u8 igu_base_sb; 1488 u8 igu_sb_cnt; 1489 u8 min_msix_vec_cnt; 1490 1491 u32 igu_base_addr; 1492 dma_addr_t def_status_blk_mapping; 1493 1494 struct bnx2x_slowpath *slowpath; 1495 dma_addr_t slowpath_mapping; 1496 1497 /* Total number of FW statistics requests */ 1498 u8 fw_stats_num; 1499 1500 /* 1501 * This is a memory buffer that will contain both statistics 1502 * ramrod request and data. 1503 */ 1504 void *fw_stats; 1505 dma_addr_t fw_stats_mapping; 1506 1507 /* 1508 * FW statistics request shortcut (points at the 1509 * beginning of fw_stats buffer). 1510 */ 1511 struct bnx2x_fw_stats_req *fw_stats_req; 1512 dma_addr_t fw_stats_req_mapping; 1513 int fw_stats_req_sz; 1514 1515 /* 1516 * FW statistics data shortcut (points at the beginning of 1517 * fw_stats buffer + fw_stats_req_sz). 1518 */ 1519 struct bnx2x_fw_stats_data *fw_stats_data; 1520 dma_addr_t fw_stats_data_mapping; 1521 int fw_stats_data_sz; 1522 1523 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1524 * context size we need 8 ILT entries. 1525 */ 1526#define ILT_MAX_L2_LINES 8 1527 struct hw_context context[ILT_MAX_L2_LINES]; 1528 1529 struct bnx2x_ilt *ilt; 1530#define BP_ILT(bp) ((bp)->ilt) 1531#define ILT_MAX_LINES 256 1532/* 1533 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1534 * to CNIC. 1535 */ 1536#define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1537 1538/* 1539 * Maximum CID count that might be required by the bnx2x: 1540 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1541 */ 1542#define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1543 + 2 * CNIC_SUPPORT(bp)) 1544#define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1545 + 2 * CNIC_SUPPORT(bp)) 1546#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1547 ILT_PAGE_CIDS)) 1548 1549 int qm_cid_count; 1550 1551 bool dropless_fc; 1552 1553 void *t2; 1554 dma_addr_t t2_mapping; 1555 struct cnic_ops __rcu *cnic_ops; 1556 void *cnic_data; 1557 u32 cnic_tag; 1558 struct cnic_eth_dev cnic_eth_dev; 1559 union host_hc_status_block cnic_sb; 1560 dma_addr_t cnic_sb_mapping; 1561 struct eth_spe *cnic_kwq; 1562 struct eth_spe *cnic_kwq_prod; 1563 struct eth_spe *cnic_kwq_cons; 1564 struct eth_spe *cnic_kwq_last; 1565 u16 cnic_kwq_pending; 1566 u16 cnic_spq_pending; 1567 u8 fip_mac[ETH_ALEN]; 1568 struct mutex cnic_mutex; 1569 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1570 1571 /* Start index of the "special" (CNIC related) L2 cleints */ 1572 u8 cnic_base_cl_id; 1573 1574 int dmae_ready; 1575 /* used to synchronize dmae accesses */ 1576 spinlock_t dmae_lock; 1577 1578 /* used to protect the FW mail box */ 1579 struct mutex fw_mb_mutex; 1580 1581 /* used to synchronize stats collecting */ 1582 int stats_state; 1583 1584 /* used for synchronization of concurrent threads statistics handling */ 1585 spinlock_t stats_lock; 1586 1587 /* used by dmae command loader */ 1588 struct dmae_command stats_dmae; 1589 int executer_idx; 1590 1591 u16 stats_counter; 1592 struct bnx2x_eth_stats eth_stats; 1593 struct host_func_stats func_stats; 1594 struct bnx2x_eth_stats_old eth_stats_old; 1595 struct bnx2x_net_stats_old net_stats_old; 1596 struct bnx2x_fw_port_stats_old fw_stats_old; 1597 bool stats_init; 1598 1599 struct z_stream_s *strm; 1600 void *gunzip_buf; 1601 dma_addr_t gunzip_mapping; 1602 int gunzip_outlen; 1603#define FW_BUF_SIZE 0x8000 1604#define GUNZIP_BUF(bp) (bp->gunzip_buf) 1605#define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1606#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1607 1608 struct raw_op *init_ops; 1609 /* Init blocks offsets inside init_ops */ 1610 u16 *init_ops_offsets; 1611 /* Data blob - has 32 bit granularity */ 1612 u32 *init_data; 1613 u32 init_mode_flags; 1614#define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1615 /* Zipped PRAM blobs - raw data */ 1616 const u8 *tsem_int_table_data; 1617 const u8 *tsem_pram_data; 1618 const u8 *usem_int_table_data; 1619 const u8 *usem_pram_data; 1620 const u8 *xsem_int_table_data; 1621 const u8 *xsem_pram_data; 1622 const u8 *csem_int_table_data; 1623 const u8 *csem_pram_data; 1624#define INIT_OPS(bp) (bp->init_ops) 1625#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1626#define INIT_DATA(bp) (bp->init_data) 1627#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1628#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1629#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1630#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1631#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1632#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1633#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1634#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1635 1636#define PHY_FW_VER_LEN 20 1637 char fw_ver[32]; 1638 const struct firmware *firmware; 1639 1640 struct bnx2x_vfdb *vfdb; 1641#define IS_SRIOV(bp) ((bp)->vfdb) 1642 1643 /* DCB support on/off */ 1644 u16 dcb_state; 1645#define BNX2X_DCB_STATE_OFF 0 1646#define BNX2X_DCB_STATE_ON 1 1647 1648 /* DCBX engine mode */ 1649 int dcbx_enabled; 1650#define BNX2X_DCBX_ENABLED_OFF 0 1651#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1652#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1653#define BNX2X_DCBX_ENABLED_INVALID (-1) 1654 1655 bool dcbx_mode_uset; 1656 1657 struct bnx2x_config_dcbx_params dcbx_config_params; 1658 struct bnx2x_dcbx_port_params dcbx_port_params; 1659 int dcb_version; 1660 1661 /* CAM credit pools */ 1662 1663 /* used only in sriov */ 1664 struct bnx2x_credit_pool_obj vlans_pool; 1665 1666 struct bnx2x_credit_pool_obj macs_pool; 1667 1668 /* RX_MODE object */ 1669 struct bnx2x_rx_mode_obj rx_mode_obj; 1670 1671 /* MCAST object */ 1672 struct bnx2x_mcast_obj mcast_obj; 1673 1674 /* RSS configuration object */ 1675 struct bnx2x_rss_config_obj rss_conf_obj; 1676 1677 /* Function State controlling object */ 1678 struct bnx2x_func_sp_obj func_obj; 1679 1680 unsigned long sp_state; 1681 1682 /* operation indication for the sp_rtnl task */ 1683 unsigned long sp_rtnl_state; 1684 1685 /* DCBX Negotation results */ 1686 struct dcbx_features dcbx_local_feat; 1687 u32 dcbx_error; 1688 1689#ifdef BCM_DCBNL 1690 struct dcbx_features dcbx_remote_feat; 1691 u32 dcbx_remote_flags; 1692#endif 1693 /* AFEX: store default vlan used */ 1694 int afex_def_vlan_tag; 1695 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1696 u32 pending_max; 1697 1698 /* multiple tx classes of service */ 1699 u8 max_cos; 1700 1701 /* priority to cos mapping */ 1702 u8 prio_to_cos[8]; 1703 u32 dump_preset_idx; 1704}; 1705 1706/* Tx queues may be less or equal to Rx queues */ 1707extern int num_queues; 1708#define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1709#define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 1710#define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 1711 (bp)->num_cnic_queues) 1712#define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1713 1714#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1715 1716#define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1717/* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1718 1719#define RSS_IPV4_CAP_MASK \ 1720 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1721 1722#define RSS_IPV4_TCP_CAP_MASK \ 1723 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1724 1725#define RSS_IPV6_CAP_MASK \ 1726 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1727 1728#define RSS_IPV6_TCP_CAP_MASK \ 1729 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1730 1731/* func init flags */ 1732#define FUNC_FLG_RSS 0x0001 1733#define FUNC_FLG_STATS 0x0002 1734/* removed FUNC_FLG_UNMATCHED 0x0004 */ 1735#define FUNC_FLG_TPA 0x0008 1736#define FUNC_FLG_SPQ 0x0010 1737#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1738 1739 1740struct bnx2x_func_init_params { 1741 /* dma */ 1742 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1743 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1744 1745 u16 func_flgs; 1746 u16 func_id; /* abs fid */ 1747 u16 pf_id; 1748 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1749}; 1750 1751#define for_each_cnic_queue(bp, var) \ 1752 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1753 (var)++) \ 1754 if (skip_queue(bp, var)) \ 1755 continue; \ 1756 else 1757 1758#define for_each_eth_queue(bp, var) \ 1759 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1760 1761#define for_each_nondefault_eth_queue(bp, var) \ 1762 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1763 1764#define for_each_queue(bp, var) \ 1765 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1766 if (skip_queue(bp, var)) \ 1767 continue; \ 1768 else 1769 1770/* Skip forwarding FP */ 1771#define for_each_valid_rx_queue(bp, var) \ 1772 for ((var) = 0; \ 1773 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1774 BNX2X_NUM_ETH_QUEUES(bp)); \ 1775 (var)++) \ 1776 if (skip_rx_queue(bp, var)) \ 1777 continue; \ 1778 else 1779 1780#define for_each_rx_queue_cnic(bp, var) \ 1781 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1782 (var)++) \ 1783 if (skip_rx_queue(bp, var)) \ 1784 continue; \ 1785 else 1786 1787#define for_each_rx_queue(bp, var) \ 1788 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1789 if (skip_rx_queue(bp, var)) \ 1790 continue; \ 1791 else 1792 1793/* Skip OOO FP */ 1794#define for_each_valid_tx_queue(bp, var) \ 1795 for ((var) = 0; \ 1796 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1797 BNX2X_NUM_ETH_QUEUES(bp)); \ 1798 (var)++) \ 1799 if (skip_tx_queue(bp, var)) \ 1800 continue; \ 1801 else 1802 1803#define for_each_tx_queue_cnic(bp, var) \ 1804 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1805 (var)++) \ 1806 if (skip_tx_queue(bp, var)) \ 1807 continue; \ 1808 else 1809 1810#define for_each_tx_queue(bp, var) \ 1811 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1812 if (skip_tx_queue(bp, var)) \ 1813 continue; \ 1814 else 1815 1816#define for_each_nondefault_queue(bp, var) \ 1817 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1818 if (skip_queue(bp, var)) \ 1819 continue; \ 1820 else 1821 1822#define for_each_cos_in_tx_queue(fp, var) \ 1823 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1824 1825/* skip rx queue 1826 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1827 */ 1828#define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1829 1830/* skip tx queue 1831 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1832 */ 1833#define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1834 1835#define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1836 1837 1838 1839 1840/** 1841 * bnx2x_set_mac_one - configure a single MAC address 1842 * 1843 * @bp: driver handle 1844 * @mac: MAC to configure 1845 * @obj: MAC object handle 1846 * @set: if 'true' add a new MAC, otherwise - delete 1847 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 1848 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 1849 * 1850 * Configures one MAC according to provided parameters or continues the 1851 * execution of previously scheduled commands if RAMROD_CONT is set in 1852 * ramrod_flags. 1853 * 1854 * Returns zero if operation has successfully completed, a positive value if the 1855 * operation has been successfully scheduled and a negative - if a requested 1856 * operations has failed. 1857 */ 1858int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 1859 struct bnx2x_vlan_mac_obj *obj, bool set, 1860 int mac_type, unsigned long *ramrod_flags); 1861/** 1862 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 1863 * 1864 * @bp: driver handle 1865 * @mac_obj: MAC object handle 1866 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 1867 * @wait_for_comp: if 'true' block until completion 1868 * 1869 * Deletes all MACs of the specific type (e.g. ETH, UC list). 1870 * 1871 * Returns zero if operation has successfully completed, a positive value if the 1872 * operation has been successfully scheduled and a negative - if a requested 1873 * operations has failed. 1874 */ 1875int bnx2x_del_all_macs(struct bnx2x *bp, 1876 struct bnx2x_vlan_mac_obj *mac_obj, 1877 int mac_type, bool wait_for_comp); 1878 1879/* Init Function API */ 1880void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 1881void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 1882 u8 vf_valid, int fw_sb_id, int igu_sb_id); 1883u32 bnx2x_get_pretend_reg(struct bnx2x *bp); 1884int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 1885int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1886int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 1887int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1888void bnx2x_read_mf_cfg(struct bnx2x *bp); 1889 1890int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 1891 1892/* dmae */ 1893void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 1894void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 1895 u32 len32); 1896void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 1897u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 1898u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 1899u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 1900 bool with_comp, u8 comp_type); 1901 1902void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 1903 u8 src_type, u8 dst_type); 1904int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae); 1905void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl); 1906 1907/* FLR related routines */ 1908u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); 1909void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); 1910int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); 1911u8 bnx2x_is_pcie_pending(struct pci_dev *dev); 1912int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 1913 char *msg, u32 poll_cnt); 1914 1915void bnx2x_calc_fc_adv(struct bnx2x *bp); 1916int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 1917 u32 data_hi, u32 data_lo, int cmd_type); 1918void bnx2x_update_coalesce(struct bnx2x *bp); 1919int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 1920 1921static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 1922 int wait) 1923{ 1924 u32 val; 1925 1926 do { 1927 val = REG_RD(bp, reg); 1928 if (val == expected) 1929 break; 1930 ms -= wait; 1931 msleep(wait); 1932 1933 } while (ms > 0); 1934 1935 return val; 1936} 1937 1938void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, 1939 bool is_pf); 1940 1941#define BNX2X_ILT_ZALLOC(x, y, size) \ 1942 do { \ 1943 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 1944 if (x) \ 1945 memset(x, 0, size); \ 1946 } while (0) 1947 1948#define BNX2X_ILT_FREE(x, y, size) \ 1949 do { \ 1950 if (x) { \ 1951 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 1952 x = NULL; \ 1953 y = 0; \ 1954 } \ 1955 } while (0) 1956 1957#define ILOG2(x) (ilog2((x))) 1958 1959#define ILT_NUM_PAGE_ENTRIES (3072) 1960/* In 57710/11 we use whole table since we have 8 func 1961 * In 57712 we have only 4 func, but use same size per func, then only half of 1962 * the table in use 1963 */ 1964#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 1965 1966#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 1967/* 1968 * the phys address is shifted right 12 bits and has an added 1969 * 1=valid bit added to the 53rd bit 1970 * then since this is a wide register(TM) 1971 * we split it into two 32 bit writes 1972 */ 1973#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 1974#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 1975 1976/* load/unload mode */ 1977#define LOAD_NORMAL 0 1978#define LOAD_OPEN 1 1979#define LOAD_DIAG 2 1980#define LOAD_LOOPBACK_EXT 3 1981#define UNLOAD_NORMAL 0 1982#define UNLOAD_CLOSE 1 1983#define UNLOAD_RECOVERY 2 1984 1985 1986/* DMAE command defines */ 1987#define DMAE_TIMEOUT -1 1988#define DMAE_PCI_ERROR -2 /* E2 and onward */ 1989#define DMAE_NOT_RDY -3 1990#define DMAE_PCI_ERR_FLAG 0x80000000 1991 1992#define DMAE_SRC_PCI 0 1993#define DMAE_SRC_GRC 1 1994 1995#define DMAE_DST_NONE 0 1996#define DMAE_DST_PCI 1 1997#define DMAE_DST_GRC 2 1998 1999#define DMAE_COMP_PCI 0 2000#define DMAE_COMP_GRC 1 2001 2002/* E2 and onward - PCI error handling in the completion */ 2003 2004#define DMAE_COMP_REGULAR 0 2005#define DMAE_COM_SET_ERR 1 2006 2007#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 2008 DMAE_COMMAND_SRC_SHIFT) 2009#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 2010 DMAE_COMMAND_SRC_SHIFT) 2011 2012#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 2013 DMAE_COMMAND_DST_SHIFT) 2014#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 2015 DMAE_COMMAND_DST_SHIFT) 2016 2017#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 2018 DMAE_COMMAND_C_DST_SHIFT) 2019#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 2020 DMAE_COMMAND_C_DST_SHIFT) 2021 2022#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 2023 2024#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2025#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2026#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2027#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2028 2029#define DMAE_CMD_PORT_0 0 2030#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2031 2032#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 2033#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 2034#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 2035 2036#define DMAE_SRC_PF 0 2037#define DMAE_SRC_VF 1 2038 2039#define DMAE_DST_PF 0 2040#define DMAE_DST_VF 1 2041 2042#define DMAE_C_SRC 0 2043#define DMAE_C_DST 1 2044 2045#define DMAE_LEN32_RD_MAX 0x80 2046#define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 2047 2048#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 2049 indicates eror */ 2050 2051#define MAX_DMAE_C_PER_PORT 8 2052#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2053 BP_VN(bp)) 2054#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2055 E1HVN_MAX) 2056 2057/* PCIE link and speed */ 2058#define PCICFG_LINK_WIDTH 0x1f00000 2059#define PCICFG_LINK_WIDTH_SHIFT 20 2060#define PCICFG_LINK_SPEED 0xf0000 2061#define PCICFG_LINK_SPEED_SHIFT 16 2062 2063#define BNX2X_NUM_TESTS_SF 7 2064#define BNX2X_NUM_TESTS_MF 3 2065#define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 2066 BNX2X_NUM_TESTS_SF) 2067 2068#define BNX2X_PHY_LOOPBACK 0 2069#define BNX2X_MAC_LOOPBACK 1 2070#define BNX2X_EXT_LOOPBACK 2 2071#define BNX2X_PHY_LOOPBACK_FAILED 1 2072#define BNX2X_MAC_LOOPBACK_FAILED 2 2073#define BNX2X_EXT_LOOPBACK_FAILED 3 2074#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2075 BNX2X_PHY_LOOPBACK_FAILED) 2076 2077#define STROM_ASSERT_ARRAY_SIZE 50 2078 2079/* must be used on a CID before placing it on a HW ring */ 2080#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 2081 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2082 (x)) 2083 2084#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2085#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2086 2087 2088#define BNX2X_BTR 4 2089#define MAX_SPQ_PENDING 8 2090 2091/* CMNG constants, as derived from system spec calculations */ 2092/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2093#define DEF_MIN_RATE 100 2094/* resolution of the rate shaping timer - 400 usec */ 2095#define RS_PERIODIC_TIMEOUT_USEC 400 2096/* number of bytes in single QM arbitration cycle - 2097 * coefficient for calculating the fairness timer */ 2098#define QM_ARB_BYTES 160000 2099/* resolution of Min algorithm 1:100 */ 2100#define MIN_RES 100 2101/* how many bytes above threshold for the minimal credit of Min algorithm*/ 2102#define MIN_ABOVE_THRESH 32768 2103/* Fairness algorithm integration time coefficient - 2104 * for calculating the actual Tfair */ 2105#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2106/* Memory of fairness algorithm . 2 cycles */ 2107#define FAIR_MEM 2 2108 2109#define ATTN_NIG_FOR_FUNC (1L << 8) 2110#define ATTN_SW_TIMER_4_FUNC (1L << 9) 2111#define GPIO_2_FUNC (1L << 10) 2112#define GPIO_3_FUNC (1L << 11) 2113#define GPIO_4_FUNC (1L << 12) 2114#define ATTN_GENERAL_ATTN_1 (1L << 13) 2115#define ATTN_GENERAL_ATTN_2 (1L << 14) 2116#define ATTN_GENERAL_ATTN_3 (1L << 15) 2117#define ATTN_GENERAL_ATTN_4 (1L << 13) 2118#define ATTN_GENERAL_ATTN_5 (1L << 14) 2119#define ATTN_GENERAL_ATTN_6 (1L << 15) 2120 2121#define ATTN_HARD_WIRED_MASK 0xff00 2122#define ATTENTION_ID 4 2123 2124 2125/* stuff added to make the code fit 80Col */ 2126 2127#define BNX2X_PMF_LINK_ASSERT \ 2128 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2129 2130#define BNX2X_MC_ASSERT_BITS \ 2131 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2132 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2133 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2134 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2135 2136#define BNX2X_MCP_ASSERT \ 2137 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2138 2139#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2140#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2141 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2142 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2143 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2144 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2145 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2146 2147#define HW_INTERRUT_ASSERT_SET_0 \ 2148 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2149 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2150 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2151 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ 2152 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2153#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2154 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2155 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2156 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2157 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2158 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2159 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2160#define HW_INTERRUT_ASSERT_SET_1 \ 2161 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2162 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2163 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2164 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2165 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2166 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2167 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2168 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2169 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2170 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2171 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2172#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2173 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2174 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2175 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2176 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2177 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2178 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2179 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2180 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2181 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2182 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2183 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2184 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2185 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2186 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2187 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2188#define HW_INTERRUT_ASSERT_SET_2 \ 2189 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2190 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2191 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2192 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2193 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2194#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2195 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2196 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2197 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2198 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2199 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2200 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2201 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2202 2203#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2204 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2205 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2206 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2207 2208#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2209 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2210 2211#define MULTI_MASK 0x7f 2212 2213#define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2214#define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2215#define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2216#define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2217 2218#define DEF_USB_IGU_INDEX_OFF \ 2219 offsetof(struct cstorm_def_status_block_u, igu_index) 2220#define DEF_CSB_IGU_INDEX_OFF \ 2221 offsetof(struct cstorm_def_status_block_c, igu_index) 2222#define DEF_XSB_IGU_INDEX_OFF \ 2223 offsetof(struct xstorm_def_status_block, igu_index) 2224#define DEF_TSB_IGU_INDEX_OFF \ 2225 offsetof(struct tstorm_def_status_block, igu_index) 2226 2227#define DEF_USB_SEGMENT_OFF \ 2228 offsetof(struct cstorm_def_status_block_u, segment) 2229#define DEF_CSB_SEGMENT_OFF \ 2230 offsetof(struct cstorm_def_status_block_c, segment) 2231#define DEF_XSB_SEGMENT_OFF \ 2232 offsetof(struct xstorm_def_status_block, segment) 2233#define DEF_TSB_SEGMENT_OFF \ 2234 offsetof(struct tstorm_def_status_block, segment) 2235 2236#define BNX2X_SP_DSB_INDEX \ 2237 (&bp->def_status_blk->sp_sb.\ 2238 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2239 2240#define CAM_IS_INVALID(x) \ 2241 (GET_FLAG(x.flags, \ 2242 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2243 (T_ETH_MAC_COMMAND_INVALIDATE)) 2244 2245/* Number of u32 elements in MC hash array */ 2246#define MC_HASH_SIZE 8 2247#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2248 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2249 2250#ifndef PXP2_REG_PXP2_INT_STS 2251#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2252#endif 2253 2254#ifndef ETH_MAX_RX_CLIENTS_E2 2255#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2256#endif 2257 2258#define BNX2X_VPD_LEN 128 2259#define VENDOR_ID_LEN 4 2260 2261#define VF_ACQUIRE_THRESH 3 2262#define VF_ACQUIRE_MAC_FILTERS 1 2263#define VF_ACQUIRE_MC_FILTERS 10 2264 2265#define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2266 (!((me_reg) & ME_REG_VF_ERR))) 2267int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code); 2268/* Congestion management fairness mode */ 2269#define CMNG_FNS_NONE 0 2270#define CMNG_FNS_MINMAX 1 2271 2272#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2273#define HC_SEG_ACCESS_ATTN 4 2274#define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2275 2276static const u32 dmae_reg_go_c[] = { 2277 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2278 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2279 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2280 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2281}; 2282 2283void bnx2x_set_ethtool_ops(struct net_device *netdev); 2284void bnx2x_notify_link_changed(struct bnx2x *bp); 2285 2286#define BNX2X_MF_SD_PROTOCOL(bp) \ 2287 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2288 2289#define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 2290 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2291 2292#define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 2293 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 2294 2295#define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 2296#define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 2297 2298#define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \ 2299 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2300 2301#define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp)) 2302#define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \ 2303 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 2304 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2305 2306#define SET_FLAG(value, mask, flag) \ 2307 do {\ 2308 (value) &= ~(mask);\ 2309 (value) |= ((flag) << (mask##_SHIFT));\ 2310 } while (0) 2311 2312#define GET_FLAG(value, mask) \ 2313 (((value) & (mask)) >> (mask##_SHIFT)) 2314 2315#define GET_FIELD(value, fname) \ 2316 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2317 2318enum { 2319 SWITCH_UPDATE, 2320 AFEX_UPDATE, 2321}; 2322 2323#define NUM_MACS 8 2324 2325#endif /* bnx2x.h */ 2326