bnx2x.h revision 3156b8eb9d85ee475de20352c07cb386a53255c2
1/* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14#ifndef BNX2X_H 15#define BNX2X_H 16 17#include <linux/pci.h> 18#include <linux/netdevice.h> 19#include <linux/dma-mapping.h> 20#include <linux/types.h> 21#include <linux/pci_regs.h> 22 23/* compilation time flags */ 24 25/* define this to make the driver freeze on error to allow getting debug info 26 * (you will need to reboot afterwards) */ 27/* #define BNX2X_STOP_ON_ERROR */ 28 29#define DRV_MODULE_VERSION "1.78.19-0" 30#define DRV_MODULE_RELDATE "2014/02/10" 31#define BNX2X_BC_VER 0x040200 32 33#if defined(CONFIG_DCB) 34#define BCM_DCBNL 35#endif 36 37#include "bnx2x_hsi.h" 38 39#include "../cnic_if.h" 40 41#define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 42 43#include <linux/mdio.h> 44 45#include "bnx2x_reg.h" 46#include "bnx2x_fw_defs.h" 47#include "bnx2x_mfw_req.h" 48#include "bnx2x_link.h" 49#include "bnx2x_sp.h" 50#include "bnx2x_dcb.h" 51#include "bnx2x_stats.h" 52#include "bnx2x_vfpf.h" 53 54enum bnx2x_int_mode { 55 BNX2X_INT_MODE_MSIX, 56 BNX2X_INT_MODE_INTX, 57 BNX2X_INT_MODE_MSI 58}; 59 60/* error/debug prints */ 61 62#define DRV_MODULE_NAME "bnx2x" 63 64/* for messages that are currently off */ 65#define BNX2X_MSG_OFF 0x0 66#define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 67#define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 68#define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 69#define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 70#define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 71#define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 72#define BNX2X_MSG_IOV 0x0800000 73#define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 74#define BNX2X_MSG_ETHTOOL 0x4000000 75#define BNX2X_MSG_DCB 0x8000000 76 77/* regular debug print */ 78#define DP_INNER(fmt, ...) \ 79 pr_notice("[%s:%d(%s)]" fmt, \ 80 __func__, __LINE__, \ 81 bp->dev ? (bp->dev->name) : "?", \ 82 ##__VA_ARGS__); 83 84#define DP(__mask, fmt, ...) \ 85do { \ 86 if (unlikely(bp->msg_enable & (__mask))) \ 87 DP_INNER(fmt, ##__VA_ARGS__); \ 88} while (0) 89 90#define DP_AND(__mask, fmt, ...) \ 91do { \ 92 if (unlikely((bp->msg_enable & (__mask)) == __mask)) \ 93 DP_INNER(fmt, ##__VA_ARGS__); \ 94} while (0) 95 96#define DP_CONT(__mask, fmt, ...) \ 97do { \ 98 if (unlikely(bp->msg_enable & (__mask))) \ 99 pr_cont(fmt, ##__VA_ARGS__); \ 100} while (0) 101 102/* errors debug print */ 103#define BNX2X_DBG_ERR(fmt, ...) \ 104do { \ 105 if (unlikely(netif_msg_probe(bp))) \ 106 pr_err("[%s:%d(%s)]" fmt, \ 107 __func__, __LINE__, \ 108 bp->dev ? (bp->dev->name) : "?", \ 109 ##__VA_ARGS__); \ 110} while (0) 111 112/* for errors (never masked) */ 113#define BNX2X_ERR(fmt, ...) \ 114do { \ 115 pr_err("[%s:%d(%s)]" fmt, \ 116 __func__, __LINE__, \ 117 bp->dev ? (bp->dev->name) : "?", \ 118 ##__VA_ARGS__); \ 119} while (0) 120 121#define BNX2X_ERROR(fmt, ...) \ 122 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 123 124/* before we have a dev->name use dev_info() */ 125#define BNX2X_DEV_INFO(fmt, ...) \ 126do { \ 127 if (unlikely(netif_msg_probe(bp))) \ 128 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 129} while (0) 130 131/* Error handling */ 132void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int); 133#ifdef BNX2X_STOP_ON_ERROR 134#define bnx2x_panic() \ 135do { \ 136 bp->panic = 1; \ 137 BNX2X_ERR("driver assert\n"); \ 138 bnx2x_panic_dump(bp, true); \ 139} while (0) 140#else 141#define bnx2x_panic() \ 142do { \ 143 bp->panic = 1; \ 144 BNX2X_ERR("driver assert\n"); \ 145 bnx2x_panic_dump(bp, false); \ 146} while (0) 147#endif 148 149#define bnx2x_mc_addr(ha) ((ha)->addr) 150#define bnx2x_uc_addr(ha) ((ha)->addr) 151 152#define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff)) 153#define U64_HI(x) ((u32)(((u64)(x)) >> 32)) 154#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 155 156#define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 157 158#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 159#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 160#define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 161 162#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 163#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 164#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 165 166#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 167#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 168 169#define REG_RD_DMAE(bp, offset, valp, len32) \ 170 do { \ 171 bnx2x_read_dmae(bp, offset, len32);\ 172 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 173 } while (0) 174 175#define REG_WR_DMAE(bp, offset, valp, len32) \ 176 do { \ 177 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 178 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 179 offset, len32); \ 180 } while (0) 181 182#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 183 REG_WR_DMAE(bp, offset, valp, len32) 184 185#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 186 do { \ 187 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 188 bnx2x_write_big_buf_wb(bp, addr, len32); \ 189 } while (0) 190 191#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 192 offsetof(struct shmem_region, field)) 193#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 194#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 195 196#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 197 offsetof(struct shmem2_region, field)) 198#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 199#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 200#define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 201 offsetof(struct mf_cfg, field)) 202#define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 203 offsetof(struct mf2_cfg, field)) 204 205#define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 206#define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 207 MF_CFG_ADDR(bp, field), (val)) 208#define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 209 210#define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 211 (SHMEM2_RD((bp), size) > \ 212 offsetof(struct shmem2_region, field))) 213 214#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 215#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 216 217/* SP SB indices */ 218 219/* General SP events - stats query, cfc delete, etc */ 220#define HC_SP_INDEX_ETH_DEF_CONS 3 221 222/* EQ completions */ 223#define HC_SP_INDEX_EQ_CONS 7 224 225/* FCoE L2 connection completions */ 226#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 227#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 228/* iSCSI L2 */ 229#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 230#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 231 232/* Special clients parameters */ 233 234/* SB indices */ 235/* FCoE L2 */ 236#define BNX2X_FCOE_L2_RX_INDEX \ 237 (&bp->def_status_blk->sp_sb.\ 238 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 239 240#define BNX2X_FCOE_L2_TX_INDEX \ 241 (&bp->def_status_blk->sp_sb.\ 242 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 243 244/** 245 * CIDs and CLIDs: 246 * CLIDs below is a CLID for func 0, then the CLID for other 247 * functions will be calculated by the formula: 248 * 249 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 250 * 251 */ 252enum { 253 BNX2X_ISCSI_ETH_CL_ID_IDX, 254 BNX2X_FCOE_ETH_CL_ID_IDX, 255 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 256}; 257 258/* use a value high enough to be above all the PFs, which has least significant 259 * nibble as 8, so when cnic needs to come up with a CID for UIO to use to 260 * calculate doorbell address according to old doorbell configuration scheme 261 * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number 262 * We must avoid coming up with cid 8 for iscsi since according to this method 263 * the designated UIO cid will come out 0 and it has a special handling for that 264 * case which doesn't suit us. Therefore will will cieling to closes cid which 265 * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18. 266 */ 267 268#define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \ 269 (bp)->max_cos) 270/* amount of cids traversed by UIO's DPM addition to doorbell */ 271#define UIO_DPM 8 272/* roundup to DPM offset */ 273#define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \ 274 UIO_DPM)) 275/* offset to nearest value which has lsb nibble matching DPM */ 276#define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \ 277 (UIO_DPM * 2)) 278/* add offset to rounded-up cid to get a value which could be used with UIO */ 279#define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp)) 280/* but wait - avoid UIO special case for cid 0 */ 281#define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \ 282 (UIO_DPM_ALIGN(bp) == UIO_DPM)) 283/* Properly DPM aligned CID dajusted to cid 0 secal case */ 284#define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \ 285 (UIO_DPM_CID0_OFFSET(bp))) 286/* how many cids were wasted - need this value for cid allocation */ 287#define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \ 288 BNX2X_1st_NON_L2_ETH_CID(bp)) 289 /* iSCSI L2 */ 290#define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 291 /* FCoE L2 */ 292#define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 293 294#define CNIC_SUPPORT(bp) ((bp)->cnic_support) 295#define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 296#define CNIC_LOADED(bp) ((bp)->cnic_loaded) 297#define FCOE_INIT(bp) ((bp)->fcoe_init) 298 299#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 300 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 301 302#define SM_RX_ID 0 303#define SM_TX_ID 1 304 305/* defines for multiple tx priority indices */ 306#define FIRST_TX_ONLY_COS_INDEX 1 307#define FIRST_TX_COS_INDEX 0 308 309/* rules for calculating the cids of tx-only connections */ 310#define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 311#define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 312 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 313 314/* fp index inside class of service range */ 315#define FP_COS_TO_TXQ(fp, cos, bp) \ 316 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 317 318/* Indexes for transmission queues array: 319 * txdata for RSS i CoS j is at location i + (j * num of RSS) 320 * txdata for FCoE (if exist) is at location max cos * num of RSS 321 * txdata for FWD (if exist) is one location after FCoE 322 * txdata for OOO (if exist) is one location after FWD 323 */ 324enum { 325 FCOE_TXQ_IDX_OFFSET, 326 FWD_TXQ_IDX_OFFSET, 327 OOO_TXQ_IDX_OFFSET, 328}; 329#define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 330#define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 331 332/* fast path */ 333/* 334 * This driver uses new build_skb() API : 335 * RX ring buffer contains pointer to kmalloc() data only, 336 * skb are built only after Hardware filled the frame. 337 */ 338struct sw_rx_bd { 339 u8 *data; 340 DEFINE_DMA_UNMAP_ADDR(mapping); 341}; 342 343struct sw_tx_bd { 344 struct sk_buff *skb; 345 u16 first_bd; 346 u8 flags; 347/* Set on the first BD descriptor when there is a split BD */ 348#define BNX2X_TSO_SPLIT_BD (1<<0) 349}; 350 351struct sw_rx_page { 352 struct page *page; 353 DEFINE_DMA_UNMAP_ADDR(mapping); 354}; 355 356union db_prod { 357 struct doorbell_set_prod data; 358 u32 raw; 359}; 360 361/* dropless fc FW/HW related params */ 362#define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 363#define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 364 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 365 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 366#define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 367#define FW_PREFETCH_CNT 16 368#define DROPLESS_FC_HEADROOM 100 369 370/* MC hsi */ 371#define BCM_PAGE_SHIFT 12 372#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 373#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 374#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 375 376#define PAGES_PER_SGE_SHIFT 0 377#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 378#define SGE_PAGE_SIZE PAGE_SIZE 379#define SGE_PAGE_SHIFT PAGE_SHIFT 380#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 381#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 382#define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ 383 SGE_PAGES), 0xffff) 384 385/* SGE ring related macros */ 386#define NUM_RX_SGE_PAGES 2 387#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 388#define NEXT_PAGE_SGE_DESC_CNT 2 389#define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 390/* RX_SGE_CNT is promised to be a power of 2 */ 391#define RX_SGE_MASK (RX_SGE_CNT - 1) 392#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 393#define MAX_RX_SGE (NUM_RX_SGE - 1) 394#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 395 (MAX_RX_SGE_CNT - 1)) ? \ 396 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 397 (x) + 1) 398#define RX_SGE(x) ((x) & MAX_RX_SGE) 399 400/* 401 * Number of required SGEs is the sum of two: 402 * 1. Number of possible opened aggregations (next packet for 403 * these aggregations will probably consume SGE immediately) 404 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 405 * after placement on BD for new TPA aggregation) 406 * 407 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 408 */ 409#define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 410 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 411#define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 412 MAX_RX_SGE_CNT) 413#define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 414 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 415#define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 416 417/* Manipulate a bit vector defined as an array of u64 */ 418 419/* Number of bits in one sge_mask array element */ 420#define BIT_VEC64_ELEM_SZ 64 421#define BIT_VEC64_ELEM_SHIFT 6 422#define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 423 424#define __BIT_VEC64_SET_BIT(el, bit) \ 425 do { \ 426 el = ((el) | ((u64)0x1 << (bit))); \ 427 } while (0) 428 429#define __BIT_VEC64_CLEAR_BIT(el, bit) \ 430 do { \ 431 el = ((el) & (~((u64)0x1 << (bit)))); \ 432 } while (0) 433 434#define BIT_VEC64_SET_BIT(vec64, idx) \ 435 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 436 (idx) & BIT_VEC64_ELEM_MASK) 437 438#define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 439 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 440 (idx) & BIT_VEC64_ELEM_MASK) 441 442#define BIT_VEC64_TEST_BIT(vec64, idx) \ 443 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 444 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 445 446/* Creates a bitmask of all ones in less significant bits. 447 idx - index of the most significant bit in the created mask */ 448#define BIT_VEC64_ONES_MASK(idx) \ 449 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 450#define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 451 452/*******************************************************/ 453 454/* Number of u64 elements in SGE mask array */ 455#define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 456#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 457#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 458 459union host_hc_status_block { 460 /* pointer to fp status block e1x */ 461 struct host_hc_status_block_e1x *e1x_sb; 462 /* pointer to fp status block e2 */ 463 struct host_hc_status_block_e2 *e2_sb; 464}; 465 466struct bnx2x_agg_info { 467 /* 468 * First aggregation buffer is a data buffer, the following - are pages. 469 * We will preallocate the data buffer for each aggregation when 470 * we open the interface and will replace the BD at the consumer 471 * with this one when we receive the TPA_START CQE in order to 472 * keep the Rx BD ring consistent. 473 */ 474 struct sw_rx_bd first_buf; 475 u8 tpa_state; 476#define BNX2X_TPA_START 1 477#define BNX2X_TPA_STOP 2 478#define BNX2X_TPA_ERROR 3 479 u8 placement_offset; 480 u16 parsing_flags; 481 u16 vlan_tag; 482 u16 len_on_bd; 483 u32 rxhash; 484 enum pkt_hash_types rxhash_type; 485 u16 gro_size; 486 u16 full_page; 487}; 488 489#define Q_STATS_OFFSET32(stat_name) \ 490 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 491 492struct bnx2x_fp_txdata { 493 494 struct sw_tx_bd *tx_buf_ring; 495 496 union eth_tx_bd_types *tx_desc_ring; 497 dma_addr_t tx_desc_mapping; 498 499 u32 cid; 500 501 union db_prod tx_db; 502 503 u16 tx_pkt_prod; 504 u16 tx_pkt_cons; 505 u16 tx_bd_prod; 506 u16 tx_bd_cons; 507 508 unsigned long tx_pkt; 509 510 __le16 *tx_cons_sb; 511 512 int txq_index; 513 struct bnx2x_fastpath *parent_fp; 514 int tx_ring_size; 515}; 516 517enum bnx2x_tpa_mode_t { 518 TPA_MODE_LRO, 519 TPA_MODE_GRO 520}; 521 522struct bnx2x_fastpath { 523 struct bnx2x *bp; /* parent */ 524 525 struct napi_struct napi; 526 527#ifdef CONFIG_NET_RX_BUSY_POLL 528 unsigned int state; 529#define BNX2X_FP_STATE_IDLE 0 530#define BNX2X_FP_STATE_NAPI (1 << 0) /* NAPI owns this FP */ 531#define BNX2X_FP_STATE_POLL (1 << 1) /* poll owns this FP */ 532#define BNX2X_FP_STATE_DISABLED (1 << 2) 533#define BNX2X_FP_STATE_NAPI_YIELD (1 << 3) /* NAPI yielded this FP */ 534#define BNX2X_FP_STATE_POLL_YIELD (1 << 4) /* poll yielded this FP */ 535#define BNX2X_FP_OWNED (BNX2X_FP_STATE_NAPI | BNX2X_FP_STATE_POLL) 536#define BNX2X_FP_YIELD (BNX2X_FP_STATE_NAPI_YIELD | BNX2X_FP_STATE_POLL_YIELD) 537#define BNX2X_FP_LOCKED (BNX2X_FP_OWNED | BNX2X_FP_STATE_DISABLED) 538#define BNX2X_FP_USER_PEND (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_POLL_YIELD) 539 /* protect state */ 540 spinlock_t lock; 541#endif /* CONFIG_NET_RX_BUSY_POLL */ 542 543 union host_hc_status_block status_blk; 544 /* chip independent shortcuts into sb structure */ 545 __le16 *sb_index_values; 546 __le16 *sb_running_index; 547 /* chip independent shortcut into rx_prods_offset memory */ 548 u32 ustorm_rx_prods_offset; 549 550 u32 rx_buf_size; 551 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 552 dma_addr_t status_blk_mapping; 553 554 enum bnx2x_tpa_mode_t mode; 555 556 u8 max_cos; /* actual number of active tx coses */ 557 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 558 559 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 560 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 561 562 struct eth_rx_bd *rx_desc_ring; 563 dma_addr_t rx_desc_mapping; 564 565 union eth_rx_cqe *rx_comp_ring; 566 dma_addr_t rx_comp_mapping; 567 568 /* SGE ring */ 569 struct eth_rx_sge *rx_sge_ring; 570 dma_addr_t rx_sge_mapping; 571 572 u64 sge_mask[RX_SGE_MASK_LEN]; 573 574 u32 cid; 575 576 __le16 fp_hc_idx; 577 578 u8 index; /* number in fp array */ 579 u8 rx_queue; /* index for skb_record */ 580 u8 cl_id; /* eth client id */ 581 u8 cl_qzone_id; 582 u8 fw_sb_id; /* status block number in FW */ 583 u8 igu_sb_id; /* status block number in HW */ 584 585 u16 rx_bd_prod; 586 u16 rx_bd_cons; 587 u16 rx_comp_prod; 588 u16 rx_comp_cons; 589 u16 rx_sge_prod; 590 /* The last maximal completed SGE */ 591 u16 last_max_sge; 592 __le16 *rx_cons_sb; 593 unsigned long rx_pkt, 594 rx_calls; 595 596 /* TPA related */ 597 struct bnx2x_agg_info *tpa_info; 598 u8 disable_tpa; 599#ifdef BNX2X_STOP_ON_ERROR 600 u64 tpa_queue_used; 601#endif 602 /* The size is calculated using the following: 603 sizeof name field from netdev structure + 604 4 ('-Xx-' string) + 605 4 (for the digits and to make it DWORD aligned) */ 606#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 607 char name[FP_NAME_SIZE]; 608}; 609 610#define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 611#define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 612#define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 613#define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 614 615#ifdef CONFIG_NET_RX_BUSY_POLL 616static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp) 617{ 618 spin_lock_init(&fp->lock); 619 fp->state = BNX2X_FP_STATE_IDLE; 620} 621 622/* called from the device poll routine to get ownership of a FP */ 623static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 624{ 625 bool rc = true; 626 627 spin_lock_bh(&fp->lock); 628 if (fp->state & BNX2X_FP_LOCKED) { 629 WARN_ON(fp->state & BNX2X_FP_STATE_NAPI); 630 fp->state |= BNX2X_FP_STATE_NAPI_YIELD; 631 rc = false; 632 } else { 633 /* we don't care if someone yielded */ 634 fp->state = BNX2X_FP_STATE_NAPI; 635 } 636 spin_unlock_bh(&fp->lock); 637 return rc; 638} 639 640/* returns true is someone tried to get the FP while napi had it */ 641static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 642{ 643 bool rc = false; 644 645 spin_lock_bh(&fp->lock); 646 WARN_ON(fp->state & 647 (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_NAPI_YIELD)); 648 649 if (fp->state & BNX2X_FP_STATE_POLL_YIELD) 650 rc = true; 651 652 /* state ==> idle, unless currently disabled */ 653 fp->state &= BNX2X_FP_STATE_DISABLED; 654 spin_unlock_bh(&fp->lock); 655 return rc; 656} 657 658/* called from bnx2x_low_latency_poll() */ 659static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 660{ 661 bool rc = true; 662 663 spin_lock_bh(&fp->lock); 664 if ((fp->state & BNX2X_FP_LOCKED)) { 665 fp->state |= BNX2X_FP_STATE_POLL_YIELD; 666 rc = false; 667 } else { 668 /* preserve yield marks */ 669 fp->state |= BNX2X_FP_STATE_POLL; 670 } 671 spin_unlock_bh(&fp->lock); 672 return rc; 673} 674 675/* returns true if someone tried to get the FP while it was locked */ 676static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 677{ 678 bool rc = false; 679 680 spin_lock_bh(&fp->lock); 681 WARN_ON(fp->state & BNX2X_FP_STATE_NAPI); 682 683 if (fp->state & BNX2X_FP_STATE_POLL_YIELD) 684 rc = true; 685 686 /* state ==> idle, unless currently disabled */ 687 fp->state &= BNX2X_FP_STATE_DISABLED; 688 spin_unlock_bh(&fp->lock); 689 return rc; 690} 691 692/* true if a socket is polling, even if it did not get the lock */ 693static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 694{ 695 WARN_ON(!(fp->state & BNX2X_FP_OWNED)); 696 return fp->state & BNX2X_FP_USER_PEND; 697} 698 699/* false if fp is currently owned */ 700static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp) 701{ 702 int rc = true; 703 704 spin_lock_bh(&fp->lock); 705 if (fp->state & BNX2X_FP_OWNED) 706 rc = false; 707 fp->state |= BNX2X_FP_STATE_DISABLED; 708 spin_unlock_bh(&fp->lock); 709 710 return rc; 711} 712#else 713static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp) 714{ 715} 716 717static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 718{ 719 return true; 720} 721 722static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 723{ 724 return false; 725} 726 727static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 728{ 729 return false; 730} 731 732static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 733{ 734 return false; 735} 736 737static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 738{ 739 return false; 740} 741static inline bool bnx2x_fp_ll_disable(struct bnx2x_fastpath *fp) 742{ 743 return true; 744} 745#endif /* CONFIG_NET_RX_BUSY_POLL */ 746 747/* Use 2500 as a mini-jumbo MTU for FCoE */ 748#define BNX2X_FCOE_MINI_JUMBO_MTU 2500 749 750#define FCOE_IDX_OFFSET 0 751 752#define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 753 FCOE_IDX_OFFSET) 754#define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 755#define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 756#define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 757#define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 758#define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 759 txdata_ptr[FIRST_TX_COS_INDEX] \ 760 ->var) 761 762#define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 763#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 764#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 765 766/* MC hsi */ 767#define MAX_FETCH_BD 13 /* HW max BDs per packet */ 768#define RX_COPY_THRESH 92 769 770#define NUM_TX_RINGS 16 771#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 772#define NEXT_PAGE_TX_DESC_CNT 1 773#define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 774#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 775#define MAX_TX_BD (NUM_TX_BD - 1) 776#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 777#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 778 (MAX_TX_DESC_CNT - 1)) ? \ 779 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 780 (x) + 1) 781#define TX_BD(x) ((x) & MAX_TX_BD) 782#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 783 784/* number of NEXT_PAGE descriptors may be required during placement */ 785#define NEXT_CNT_PER_TX_PKT(bds) \ 786 (((bds) + MAX_TX_DESC_CNT - 1) / \ 787 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 788/* max BDs per tx packet w/o next_pages: 789 * START_BD - describes packed 790 * START_BD(splitted) - includes unpaged data segment for GSO 791 * PARSING_BD - for TSO and CSUM data 792 * PARSING_BD2 - for encapsulation data 793 * Frag BDs - describes pages for frags 794 */ 795#define BDS_PER_TX_PKT 4 796#define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 797/* max BDs per tx packet including next pages */ 798#define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 799 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 800 801/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 802#define NUM_RX_RINGS 8 803#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 804#define NEXT_PAGE_RX_DESC_CNT 2 805#define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 806#define RX_DESC_MASK (RX_DESC_CNT - 1) 807#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 808#define MAX_RX_BD (NUM_RX_BD - 1) 809#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 810 811/* dropless fc calculations for BDs 812 * 813 * Number of BDs should as number of buffers in BRB: 814 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 815 * "next" elements on each page 816 */ 817#define NUM_BD_REQ BRB_SIZE(bp) 818#define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 819 MAX_RX_DESC_CNT) 820#define BD_TH_LO(bp) (NUM_BD_REQ + \ 821 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 822 FW_DROP_LEVEL(bp)) 823#define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 824 825#define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 826 827#define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 828 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 829 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 830#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 831#define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 832#define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 833 MIN_RX_AVAIL)) 834 835#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 836 (MAX_RX_DESC_CNT - 1)) ? \ 837 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 838 (x) + 1) 839#define RX_BD(x) ((x) & MAX_RX_BD) 840 841/* 842 * As long as CQE is X times bigger than BD entry we have to allocate X times 843 * more pages for CQ ring in order to keep it balanced with BD ring 844 */ 845#define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 846#define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 847#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 848#define NEXT_PAGE_RCQ_DESC_CNT 1 849#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 850#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 851#define MAX_RCQ_BD (NUM_RCQ_BD - 1) 852#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 853#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 854 (MAX_RCQ_DESC_CNT - 1)) ? \ 855 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 856 (x) + 1) 857#define RCQ_BD(x) ((x) & MAX_RCQ_BD) 858 859/* dropless fc calculations for RCQs 860 * 861 * Number of RCQs should be as number of buffers in BRB: 862 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 863 * "next" elements on each page 864 */ 865#define NUM_RCQ_REQ BRB_SIZE(bp) 866#define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 867 MAX_RCQ_DESC_CNT) 868#define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 869 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 870 FW_DROP_LEVEL(bp)) 871#define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 872 873/* This is needed for determining of last_max */ 874#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 875#define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 876 877#define BNX2X_SWCID_SHIFT 17 878#define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 879 880/* used on a CID received from the HW */ 881#define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 882#define CQE_CMD(x) (le32_to_cpu(x) >> \ 883 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 884 885#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 886 le32_to_cpu((bd)->addr_lo)) 887#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 888 889#define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 890#define BNX2X_DB_SHIFT 3 /* 8 bytes*/ 891#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 892#error "Min DB doorbell stride is 8" 893#endif 894#define DOORBELL(bp, cid, val) \ 895 do { \ 896 writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \ 897 } while (0) 898 899/* TX CSUM helpers */ 900#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 901 skb->csum_offset) 902#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 903 skb->csum_offset)) 904 905#define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff) 906 907#define XMIT_PLAIN 0 908#define XMIT_CSUM_V4 (1 << 0) 909#define XMIT_CSUM_V6 (1 << 1) 910#define XMIT_CSUM_TCP (1 << 2) 911#define XMIT_GSO_V4 (1 << 3) 912#define XMIT_GSO_V6 (1 << 4) 913#define XMIT_CSUM_ENC_V4 (1 << 5) 914#define XMIT_CSUM_ENC_V6 (1 << 6) 915#define XMIT_GSO_ENC_V4 (1 << 7) 916#define XMIT_GSO_ENC_V6 (1 << 8) 917 918#define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6) 919#define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6) 920 921#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC) 922#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC) 923 924/* stuff added to make the code fit 80Col */ 925#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 926#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 927#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 928#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 929#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 930 931#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 932 933#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 934 (((le16_to_cpu(flags) & \ 935 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 936 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 937 == PRS_FLAG_OVERETH_IPV4) 938#define BNX2X_RX_SUM_FIX(cqe) \ 939 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 940 941#define FP_USB_FUNC_OFF \ 942 offsetof(struct cstorm_status_block_u, func) 943#define FP_CSB_FUNC_OFF \ 944 offsetof(struct cstorm_status_block_c, func) 945 946#define HC_INDEX_ETH_RX_CQ_CONS 1 947 948#define HC_INDEX_OOO_TX_CQ_CONS 4 949 950#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 951 952#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 953 954#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 955 956#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 957 958#define BNX2X_RX_SB_INDEX \ 959 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 960 961#define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 962 963#define BNX2X_TX_SB_INDEX_COS0 \ 964 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 965 966/* end of fast path */ 967 968/* common */ 969 970struct bnx2x_common { 971 972 u32 chip_id; 973/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 974#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 975 976#define CHIP_NUM(bp) (bp->common.chip_id >> 16) 977#define CHIP_NUM_57710 0x164e 978#define CHIP_NUM_57711 0x164f 979#define CHIP_NUM_57711E 0x1650 980#define CHIP_NUM_57712 0x1662 981#define CHIP_NUM_57712_MF 0x1663 982#define CHIP_NUM_57712_VF 0x166f 983#define CHIP_NUM_57713 0x1651 984#define CHIP_NUM_57713E 0x1652 985#define CHIP_NUM_57800 0x168a 986#define CHIP_NUM_57800_MF 0x16a5 987#define CHIP_NUM_57800_VF 0x16a9 988#define CHIP_NUM_57810 0x168e 989#define CHIP_NUM_57810_MF 0x16ae 990#define CHIP_NUM_57810_VF 0x16af 991#define CHIP_NUM_57811 0x163d 992#define CHIP_NUM_57811_MF 0x163e 993#define CHIP_NUM_57811_VF 0x163f 994#define CHIP_NUM_57840_OBSOLETE 0x168d 995#define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 996#define CHIP_NUM_57840_4_10 0x16a1 997#define CHIP_NUM_57840_2_20 0x16a2 998#define CHIP_NUM_57840_MF 0x16a4 999#define CHIP_NUM_57840_VF 0x16ad 1000#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 1001#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 1002#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 1003#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 1004#define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) 1005#define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 1006#define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 1007#define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 1008#define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) 1009#define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 1010#define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 1011#define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) 1012#define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 1013#define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 1014#define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) 1015#define CHIP_IS_57840(bp) \ 1016 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 1017 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 1018 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 1019#define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 1020 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 1021#define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) 1022#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 1023 CHIP_IS_57711E(bp)) 1024#define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ 1025 CHIP_IS_57811_MF(bp) || \ 1026 CHIP_IS_57811_VF(bp)) 1027#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 1028 CHIP_IS_57712_MF(bp) || \ 1029 CHIP_IS_57712_VF(bp)) 1030#define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 1031 CHIP_IS_57800_MF(bp) || \ 1032 CHIP_IS_57800_VF(bp) || \ 1033 CHIP_IS_57810(bp) || \ 1034 CHIP_IS_57810_MF(bp) || \ 1035 CHIP_IS_57810_VF(bp) || \ 1036 CHIP_IS_57811xx(bp) || \ 1037 CHIP_IS_57840(bp) || \ 1038 CHIP_IS_57840_MF(bp) || \ 1039 CHIP_IS_57840_VF(bp)) 1040#define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 1041#define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 1042#define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 1043 1044#define CHIP_REV_SHIFT 12 1045#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1046#define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 1047#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1048#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1049/* assume maximum 5 revisions */ 1050#define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 1051/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 1052#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1053 !(CHIP_REV_VAL(bp) & 0x00001000)) 1054/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 1055#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1056 (CHIP_REV_VAL(bp) & 0x00001000)) 1057 1058#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 1059 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 1060 1061#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 1062#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 1063#define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 1064 (CHIP_REV_SHIFT + 1)) \ 1065 << CHIP_REV_SHIFT) 1066#define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 1067 CHIP_REV_SIM(bp) :\ 1068 CHIP_REV_VAL(bp)) 1069#define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 1070 (CHIP_REV(bp) == CHIP_REV_Bx)) 1071#define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 1072 (CHIP_REV(bp) == CHIP_REV_Ax)) 1073/* This define is used in two main places: 1074 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher 1075 * to nic-only mode or to offload mode. Offload mode is configured if either the 1076 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 1077 * registered for this port (which means that the user wants storage services). 1078 * 2. During cnic-related load, to know if offload mode is already configured in 1079 * the HW or needs to be configured. 1080 * Since the transition from nic-mode to offload-mode in HW causes traffic 1081 * corruption, nic-mode is configured only in ports on which storage services 1082 * where never requested. 1083 */ 1084#define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 1085 1086 int flash_size; 1087#define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 1088#define BNX2X_NVRAM_TIMEOUT_COUNT 30000 1089#define BNX2X_NVRAM_PAGE_SIZE 256 1090 1091 u32 shmem_base; 1092 u32 shmem2_base; 1093 u32 mf_cfg_base; 1094 u32 mf2_cfg_base; 1095 1096 u32 hw_config; 1097 1098 u32 bc_ver; 1099 1100 u8 int_block; 1101#define INT_BLOCK_HC 0 1102#define INT_BLOCK_IGU 1 1103#define INT_BLOCK_MODE_NORMAL 0 1104#define INT_BLOCK_MODE_BW_COMP 2 1105#define CHIP_INT_MODE_IS_NBC(bp) \ 1106 (!CHIP_IS_E1x(bp) && \ 1107 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 1108#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 1109 1110 u8 chip_port_mode; 1111#define CHIP_4_PORT_MODE 0x0 1112#define CHIP_2_PORT_MODE 0x1 1113#define CHIP_PORT_MODE_NONE 0x2 1114#define CHIP_MODE(bp) (bp->common.chip_port_mode) 1115#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 1116 1117 u32 boot_mode; 1118}; 1119 1120/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 1121#define BNX2X_IGU_STAS_MSG_VF_CNT 64 1122#define BNX2X_IGU_STAS_MSG_PF_CNT 4 1123 1124#define MAX_IGU_ATTN_ACK_TO 100 1125/* end of common */ 1126 1127/* port */ 1128 1129struct bnx2x_port { 1130 u32 pmf; 1131 1132 u32 link_config[LINK_CONFIG_SIZE]; 1133 1134 u32 supported[LINK_CONFIG_SIZE]; 1135/* link settings - missing defines */ 1136#define SUPPORTED_2500baseX_Full (1 << 15) 1137 1138 u32 advertising[LINK_CONFIG_SIZE]; 1139/* link settings - missing defines */ 1140#define ADVERTISED_2500baseX_Full (1 << 15) 1141 1142 u32 phy_addr; 1143 1144 /* used to synchronize phy accesses */ 1145 struct mutex phy_mutex; 1146 1147 u32 port_stx; 1148 1149 struct nig_stats old_nig_stats; 1150}; 1151 1152/* end of port */ 1153 1154#define STATS_OFFSET32(stat_name) \ 1155 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 1156 1157/* slow path */ 1158 1159/* slow path work-queue */ 1160extern struct workqueue_struct *bnx2x_wq; 1161 1162#define BNX2X_MAX_NUM_OF_VFS 64 1163#define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */ 1164#define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 1165 1166/* We need to reserve doorbell addresses for all VF and queue combinations */ 1167#define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 1168 1169/* The doorbell is configured to have the same number of CIDs for PFs and for 1170 * VFs. For this reason the PF CID zone is as large as the VF zone. 1171 */ 1172#define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS 1173#define BNX2X_MAX_NUM_VF_QUEUES 64 1174#define BNX2X_VF_ID_INVALID 0xFF 1175 1176/* the number of VF CIDS multiplied by the amount of bytes reserved for each 1177 * cid must not exceed the size of the VF doorbell 1178 */ 1179#define BNX2X_VF_BAR_SIZE 512 1180#if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT)) 1181#error "VF doorbell bar size is 512" 1182#endif 1183 1184/* 1185 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 1186 * control by the number of fast-path status blocks supported by the 1187 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 1188 * status block represents an independent interrupts context that can 1189 * serve a regular L2 networking queue. However special L2 queues such 1190 * as the FCoE queue do not require a FP-SB and other components like 1191 * the CNIC may consume FP-SB reducing the number of possible L2 queues 1192 * 1193 * If the maximum number of FP-SB available is X then: 1194 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 1195 * regular L2 queues is Y=X-1 1196 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 1197 * c. If the FCoE L2 queue is supported the actual number of L2 queues 1198 * is Y+1 1199 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 1200 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 1201 * FP interrupt context for the CNIC). 1202 * e. The number of HW context (CID count) is always X or X+1 if FCoE 1203 * L2 queue is supported. The cid for the FCoE L2 queue is always X. 1204 */ 1205 1206/* fast-path interrupt contexts E1x */ 1207#define FP_SB_MAX_E1x 16 1208/* fast-path interrupt contexts E2 */ 1209#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 1210 1211union cdu_context { 1212 struct eth_context eth; 1213 char pad[1024]; 1214}; 1215 1216/* CDU host DB constants */ 1217#define CDU_ILT_PAGE_SZ_HW 2 1218#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1219#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1220 1221#define CNIC_ISCSI_CID_MAX 256 1222#define CNIC_FCOE_CID_MAX 2048 1223#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1224#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1225 1226#define QM_ILT_PAGE_SZ_HW 0 1227#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1228#define QM_CID_ROUND 1024 1229 1230/* TM (timers) host DB constants */ 1231#define TM_ILT_PAGE_SZ_HW 0 1232#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1233#define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \ 1234 BNX2X_VF_CIDS + \ 1235 CNIC_ISCSI_CID_MAX) 1236#define TM_ILT_SZ (8 * TM_CONN_NUM) 1237#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1238 1239/* SRC (Searcher) host DB constants */ 1240#define SRC_ILT_PAGE_SZ_HW 0 1241#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1242#define SRC_HASH_BITS 10 1243#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1244#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1245#define SRC_T2_SZ SRC_ILT_SZ 1246#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1247 1248#define MAX_DMAE_C 8 1249 1250/* DMA memory not used in fastpath */ 1251struct bnx2x_slowpath { 1252 union { 1253 struct mac_configuration_cmd e1x; 1254 struct eth_classify_rules_ramrod_data e2; 1255 } mac_rdata; 1256 1257 union { 1258 struct tstorm_eth_mac_filter_config e1x; 1259 struct eth_filter_rules_ramrod_data e2; 1260 } rx_mode_rdata; 1261 1262 union { 1263 struct mac_configuration_cmd e1; 1264 struct eth_multicast_rules_ramrod_data e2; 1265 } mcast_rdata; 1266 1267 struct eth_rss_update_ramrod_data rss_rdata; 1268 1269 /* Queue State related ramrods are always sent under rtnl_lock */ 1270 union { 1271 struct client_init_ramrod_data init_data; 1272 struct client_update_ramrod_data update_data; 1273 struct tpa_update_ramrod_data tpa_data; 1274 } q_rdata; 1275 1276 union { 1277 struct function_start_data func_start; 1278 /* pfc configuration for DCBX ramrod */ 1279 struct flow_control_configuration pfc_config; 1280 } func_rdata; 1281 1282 /* afex ramrod can not be a part of func_rdata union because these 1283 * events might arrive in parallel to other events from func_rdata. 1284 * Therefore, if they would have been defined in the same union, 1285 * data can get corrupted. 1286 */ 1287 union { 1288 struct afex_vif_list_ramrod_data viflist_data; 1289 struct function_update_data func_update; 1290 } func_afex_rdata; 1291 1292 /* used by dmae command executer */ 1293 struct dmae_command dmae[MAX_DMAE_C]; 1294 1295 u32 stats_comp; 1296 union mac_stats mac_stats; 1297 struct nig_stats nig_stats; 1298 struct host_port_stats port_stats; 1299 struct host_func_stats func_stats; 1300 1301 u32 wb_comp; 1302 u32 wb_data[4]; 1303 1304 union drv_info_to_mcp drv_info_to_mcp; 1305}; 1306 1307#define bnx2x_sp(bp, var) (&bp->slowpath->var) 1308#define bnx2x_sp_mapping(bp, var) \ 1309 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1310 1311/* attn group wiring */ 1312#define MAX_DYNAMIC_ATTN_GRPS 8 1313 1314struct attn_route { 1315 u32 sig[5]; 1316}; 1317 1318struct iro { 1319 u32 base; 1320 u16 m1; 1321 u16 m2; 1322 u16 m3; 1323 u16 size; 1324}; 1325 1326struct hw_context { 1327 union cdu_context *vcxt; 1328 dma_addr_t cxt_mapping; 1329 size_t size; 1330}; 1331 1332/* forward */ 1333struct bnx2x_ilt; 1334 1335struct bnx2x_vfdb; 1336 1337enum bnx2x_recovery_state { 1338 BNX2X_RECOVERY_DONE, 1339 BNX2X_RECOVERY_INIT, 1340 BNX2X_RECOVERY_WAIT, 1341 BNX2X_RECOVERY_FAILED, 1342 BNX2X_RECOVERY_NIC_LOADING 1343}; 1344 1345/* 1346 * Event queue (EQ or event ring) MC hsi 1347 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1348 */ 1349#define NUM_EQ_PAGES 1 1350#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1351#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1352#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1353#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1354#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1355 1356/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1357#define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1358 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1359 1360/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1361#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1362 1363#define BNX2X_EQ_INDEX \ 1364 (&bp->def_status_blk->sp_sb.\ 1365 index_values[HC_SP_INDEX_EQ_CONS]) 1366 1367/* This is a data that will be used to create a link report message. 1368 * We will keep the data used for the last link report in order 1369 * to prevent reporting the same link parameters twice. 1370 */ 1371struct bnx2x_link_report_data { 1372 u16 line_speed; /* Effective line speed */ 1373 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1374}; 1375 1376enum { 1377 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1378 BNX2X_LINK_REPORT_LINK_DOWN, 1379 BNX2X_LINK_REPORT_RX_FC_ON, 1380 BNX2X_LINK_REPORT_TX_FC_ON, 1381}; 1382 1383enum { 1384 BNX2X_PORT_QUERY_IDX, 1385 BNX2X_PF_QUERY_IDX, 1386 BNX2X_FCOE_QUERY_IDX, 1387 BNX2X_FIRST_QUEUE_QUERY_IDX, 1388}; 1389 1390struct bnx2x_fw_stats_req { 1391 struct stats_query_header hdr; 1392 struct stats_query_entry query[FP_SB_MAX_E1x+ 1393 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1394}; 1395 1396struct bnx2x_fw_stats_data { 1397 struct stats_counter storm_counters; 1398 struct per_port_stats port; 1399 struct per_pf_stats pf; 1400 struct fcoe_statistics_params fcoe; 1401 struct per_queue_stats queue_stats[1]; 1402}; 1403 1404/* Public slow path states */ 1405enum sp_rtnl_flag { 1406 BNX2X_SP_RTNL_SETUP_TC, 1407 BNX2X_SP_RTNL_TX_TIMEOUT, 1408 BNX2X_SP_RTNL_FAN_FAILURE, 1409 BNX2X_SP_RTNL_AFEX_F_UPDATE, 1410 BNX2X_SP_RTNL_ENABLE_SRIOV, 1411 BNX2X_SP_RTNL_VFPF_MCAST, 1412 BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 1413 BNX2X_SP_RTNL_RX_MODE, 1414 BNX2X_SP_RTNL_HYPERVISOR_VLAN, 1415 BNX2X_SP_RTNL_TX_STOP, 1416}; 1417 1418struct bnx2x_prev_path_list { 1419 struct list_head list; 1420 u8 bus; 1421 u8 slot; 1422 u8 path; 1423 u8 aer; 1424 u8 undi; 1425}; 1426 1427struct bnx2x_sp_objs { 1428 /* MACs object */ 1429 struct bnx2x_vlan_mac_obj mac_obj; 1430 1431 /* Queue State object */ 1432 struct bnx2x_queue_sp_obj q_obj; 1433}; 1434 1435struct bnx2x_fp_stats { 1436 struct tstorm_per_queue_stats old_tclient; 1437 struct ustorm_per_queue_stats old_uclient; 1438 struct xstorm_per_queue_stats old_xclient; 1439 struct bnx2x_eth_q_stats eth_q_stats; 1440 struct bnx2x_eth_q_stats_old eth_q_stats_old; 1441}; 1442 1443struct bnx2x { 1444 /* Fields used in the tx and intr/napi performance paths 1445 * are grouped together in the beginning of the structure 1446 */ 1447 struct bnx2x_fastpath *fp; 1448 struct bnx2x_sp_objs *sp_objs; 1449 struct bnx2x_fp_stats *fp_stats; 1450 struct bnx2x_fp_txdata *bnx2x_txq; 1451 void __iomem *regview; 1452 void __iomem *doorbells; 1453 u16 db_size; 1454 1455 u8 pf_num; /* absolute PF number */ 1456 u8 pfid; /* per-path PF number */ 1457 int base_fw_ndsb; /**/ 1458#define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1459#define BP_PORT(bp) (bp->pfid & 1) 1460#define BP_FUNC(bp) (bp->pfid) 1461#define BP_ABS_FUNC(bp) (bp->pf_num) 1462#define BP_VN(bp) ((bp)->pfid >> 1) 1463#define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1464#define BP_L_ID(bp) (BP_VN(bp) << 2) 1465#define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1466 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1467#define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1468 1469#ifdef CONFIG_BNX2X_SRIOV 1470 /* protects vf2pf mailbox from simultaneous access */ 1471 struct mutex vf2pf_mutex; 1472 /* vf pf channel mailbox contains request and response buffers */ 1473 struct bnx2x_vf_mbx_msg *vf2pf_mbox; 1474 dma_addr_t vf2pf_mbox_mapping; 1475 1476 /* we set aside a copy of the acquire response */ 1477 struct pfvf_acquire_resp_tlv acquire_resp; 1478 1479 /* bulletin board for messages from pf to vf */ 1480 union pf_vf_bulletin *pf2vf_bulletin; 1481 dma_addr_t pf2vf_bulletin_mapping; 1482 1483 struct pf_vf_bulletin_content old_bulletin; 1484 1485 u16 requested_nr_virtfn; 1486#endif /* CONFIG_BNX2X_SRIOV */ 1487 1488 struct net_device *dev; 1489 struct pci_dev *pdev; 1490 1491 const struct iro *iro_arr; 1492#define IRO (bp->iro_arr) 1493 1494 enum bnx2x_recovery_state recovery_state; 1495 int is_leader; 1496 struct msix_entry *msix_table; 1497 1498 int tx_ring_size; 1499 1500/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1501#define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1502#define ETH_MIN_PACKET_SIZE 60 1503#define ETH_MAX_PACKET_SIZE 1500 1504#define ETH_MAX_JUMBO_PACKET_SIZE 9600 1505/* TCP with Timestamp Option (32) + IPv6 (40) */ 1506#define ETH_MAX_TPA_HEADER_SIZE 72 1507 1508 /* Max supported alignment is 256 (8 shift) */ 1509#define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1510 1511 /* FW uses 2 Cache lines Alignment for start packet and size 1512 * 1513 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1514 * at the end of skb->data, to avoid wasting a full cache line. 1515 * This reduces memory use (skb->truesize). 1516 */ 1517#define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1518 1519#define BNX2X_FW_RX_ALIGN_END \ 1520 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1521 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1522 1523#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1524 1525 struct host_sp_status_block *def_status_blk; 1526#define DEF_SB_IGU_ID 16 1527#define DEF_SB_ID HC_SP_SB_ID 1528 __le16 def_idx; 1529 __le16 def_att_idx; 1530 u32 attn_state; 1531 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1532 1533 /* slow path ring */ 1534 struct eth_spe *spq; 1535 dma_addr_t spq_mapping; 1536 u16 spq_prod_idx; 1537 struct eth_spe *spq_prod_bd; 1538 struct eth_spe *spq_last_bd; 1539 __le16 *dsb_sp_prod; 1540 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1541 /* used to synchronize spq accesses */ 1542 spinlock_t spq_lock; 1543 1544 /* event queue */ 1545 union event_ring_elem *eq_ring; 1546 dma_addr_t eq_mapping; 1547 u16 eq_prod; 1548 u16 eq_cons; 1549 __le16 *eq_cons_sb; 1550 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1551 1552 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1553 u16 stats_pending; 1554 /* Counter for completed statistics ramrods */ 1555 u16 stats_comp; 1556 1557 /* End of fields used in the performance code paths */ 1558 1559 int panic; 1560 int msg_enable; 1561 1562 u32 flags; 1563#define PCIX_FLAG (1 << 0) 1564#define PCI_32BIT_FLAG (1 << 1) 1565#define ONE_PORT_FLAG (1 << 2) 1566#define NO_WOL_FLAG (1 << 3) 1567#define USING_MSIX_FLAG (1 << 5) 1568#define USING_MSI_FLAG (1 << 6) 1569#define DISABLE_MSI_FLAG (1 << 7) 1570#define TPA_ENABLE_FLAG (1 << 8) 1571#define NO_MCP_FLAG (1 << 9) 1572#define GRO_ENABLE_FLAG (1 << 10) 1573#define MF_FUNC_DIS (1 << 11) 1574#define OWN_CNIC_IRQ (1 << 12) 1575#define NO_ISCSI_OOO_FLAG (1 << 13) 1576#define NO_ISCSI_FLAG (1 << 14) 1577#define NO_FCOE_FLAG (1 << 15) 1578#define BC_SUPPORTS_PFC_STATS (1 << 17) 1579#define TX_SWITCHING (1 << 18) 1580#define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 1581#define USING_SINGLE_MSIX_FLAG (1 << 20) 1582#define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 1583#define IS_VF_FLAG (1 << 22) 1584#define INTERRUPTS_ENABLED_FLAG (1 << 23) 1585#define BC_SUPPORTS_RMMOD_CMD (1 << 24) 1586#define HAS_PHYS_PORT_ID (1 << 25) 1587#define AER_ENABLED (1 << 26) 1588 1589#define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 1590 1591#ifdef CONFIG_BNX2X_SRIOV 1592#define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 1593#define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 1594#else 1595#define IS_VF(bp) false 1596#define IS_PF(bp) true 1597#endif 1598 1599#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1600#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1601#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1602 1603 u8 cnic_support; 1604 bool cnic_enabled; 1605 bool cnic_loaded; 1606 struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 1607 1608 /* Flag that indicates that we can start looking for FCoE L2 queue 1609 * completions in the default status block. 1610 */ 1611 bool fcoe_init; 1612 1613 int mrrs; 1614 1615 struct delayed_work sp_task; 1616 atomic_t interrupt_occurred; 1617 struct delayed_work sp_rtnl_task; 1618 1619 struct delayed_work period_task; 1620 struct timer_list timer; 1621 int current_interval; 1622 1623 u16 fw_seq; 1624 u16 fw_drv_pulse_wr_seq; 1625 u32 func_stx; 1626 1627 struct link_params link_params; 1628 struct link_vars link_vars; 1629 u32 link_cnt; 1630 struct bnx2x_link_report_data last_reported_link; 1631 1632 struct mdio_if_info mdio; 1633 1634 struct bnx2x_common common; 1635 struct bnx2x_port port; 1636 1637 struct cmng_init cmng; 1638 1639 u32 mf_config[E1HVN_MAX]; 1640 u32 mf_ext_config; 1641 u32 path_has_ovlan; /* E3 */ 1642 u16 mf_ov; 1643 u8 mf_mode; 1644#define IS_MF(bp) (bp->mf_mode != 0) 1645#define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1646#define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1647#define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1648 1649 u8 wol; 1650 1651 int rx_ring_size; 1652 1653 u16 tx_quick_cons_trip_int; 1654 u16 tx_quick_cons_trip; 1655 u16 tx_ticks_int; 1656 u16 tx_ticks; 1657 1658 u16 rx_quick_cons_trip_int; 1659 u16 rx_quick_cons_trip; 1660 u16 rx_ticks_int; 1661 u16 rx_ticks; 1662/* Maximal coalescing timeout in us */ 1663#define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR) 1664 1665 u32 lin_cnt; 1666 1667 u16 state; 1668#define BNX2X_STATE_CLOSED 0 1669#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1670#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1671#define BNX2X_STATE_OPEN 0x3000 1672#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1673#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1674 1675#define BNX2X_STATE_DIAG 0xe000 1676#define BNX2X_STATE_ERROR 0xf000 1677 1678#define BNX2X_MAX_PRIORITY 8 1679#define BNX2X_MAX_ENTRIES_PER_PRI 16 1680#define BNX2X_MAX_COS 3 1681#define BNX2X_MAX_TX_COS 2 1682 int num_queues; 1683 uint num_ethernet_queues; 1684 uint num_cnic_queues; 1685 int num_napi_queues; 1686 int disable_tpa; 1687 1688 u32 rx_mode; 1689#define BNX2X_RX_MODE_NONE 0 1690#define BNX2X_RX_MODE_NORMAL 1 1691#define BNX2X_RX_MODE_ALLMULTI 2 1692#define BNX2X_RX_MODE_PROMISC 3 1693#define BNX2X_MAX_MULTICAST 64 1694 1695 u8 igu_dsb_id; 1696 u8 igu_base_sb; 1697 u8 igu_sb_cnt; 1698 u8 min_msix_vec_cnt; 1699 1700 u32 igu_base_addr; 1701 dma_addr_t def_status_blk_mapping; 1702 1703 struct bnx2x_slowpath *slowpath; 1704 dma_addr_t slowpath_mapping; 1705 1706 /* Total number of FW statistics requests */ 1707 u8 fw_stats_num; 1708 1709 /* 1710 * This is a memory buffer that will contain both statistics 1711 * ramrod request and data. 1712 */ 1713 void *fw_stats; 1714 dma_addr_t fw_stats_mapping; 1715 1716 /* 1717 * FW statistics request shortcut (points at the 1718 * beginning of fw_stats buffer). 1719 */ 1720 struct bnx2x_fw_stats_req *fw_stats_req; 1721 dma_addr_t fw_stats_req_mapping; 1722 int fw_stats_req_sz; 1723 1724 /* 1725 * FW statistics data shortcut (points at the beginning of 1726 * fw_stats buffer + fw_stats_req_sz). 1727 */ 1728 struct bnx2x_fw_stats_data *fw_stats_data; 1729 dma_addr_t fw_stats_data_mapping; 1730 int fw_stats_data_sz; 1731 1732 /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB 1733 * context size we need 8 ILT entries. 1734 */ 1735#define ILT_MAX_L2_LINES 32 1736 struct hw_context context[ILT_MAX_L2_LINES]; 1737 1738 struct bnx2x_ilt *ilt; 1739#define BP_ILT(bp) ((bp)->ilt) 1740#define ILT_MAX_LINES 256 1741/* 1742 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1743 * to CNIC. 1744 */ 1745#define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1746 1747/* 1748 * Maximum CID count that might be required by the bnx2x: 1749 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1750 */ 1751 1752#define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1753 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1754#define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1755 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1756#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1757 ILT_PAGE_CIDS)) 1758 1759 int qm_cid_count; 1760 1761 bool dropless_fc; 1762 1763 void *t2; 1764 dma_addr_t t2_mapping; 1765 struct cnic_ops __rcu *cnic_ops; 1766 void *cnic_data; 1767 u32 cnic_tag; 1768 struct cnic_eth_dev cnic_eth_dev; 1769 union host_hc_status_block cnic_sb; 1770 dma_addr_t cnic_sb_mapping; 1771 struct eth_spe *cnic_kwq; 1772 struct eth_spe *cnic_kwq_prod; 1773 struct eth_spe *cnic_kwq_cons; 1774 struct eth_spe *cnic_kwq_last; 1775 u16 cnic_kwq_pending; 1776 u16 cnic_spq_pending; 1777 u8 fip_mac[ETH_ALEN]; 1778 struct mutex cnic_mutex; 1779 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1780 1781 /* Start index of the "special" (CNIC related) L2 clients */ 1782 u8 cnic_base_cl_id; 1783 1784 int dmae_ready; 1785 /* used to synchronize dmae accesses */ 1786 spinlock_t dmae_lock; 1787 1788 /* used to protect the FW mail box */ 1789 struct mutex fw_mb_mutex; 1790 1791 /* used to synchronize stats collecting */ 1792 int stats_state; 1793 1794 /* used for synchronization of concurrent threads statistics handling */ 1795 spinlock_t stats_lock; 1796 1797 /* used by dmae command loader */ 1798 struct dmae_command stats_dmae; 1799 int executer_idx; 1800 1801 u16 stats_counter; 1802 struct bnx2x_eth_stats eth_stats; 1803 struct host_func_stats func_stats; 1804 struct bnx2x_eth_stats_old eth_stats_old; 1805 struct bnx2x_net_stats_old net_stats_old; 1806 struct bnx2x_fw_port_stats_old fw_stats_old; 1807 bool stats_init; 1808 1809 struct z_stream_s *strm; 1810 void *gunzip_buf; 1811 dma_addr_t gunzip_mapping; 1812 int gunzip_outlen; 1813#define FW_BUF_SIZE 0x8000 1814#define GUNZIP_BUF(bp) (bp->gunzip_buf) 1815#define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1816#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1817 1818 struct raw_op *init_ops; 1819 /* Init blocks offsets inside init_ops */ 1820 u16 *init_ops_offsets; 1821 /* Data blob - has 32 bit granularity */ 1822 u32 *init_data; 1823 u32 init_mode_flags; 1824#define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1825 /* Zipped PRAM blobs - raw data */ 1826 const u8 *tsem_int_table_data; 1827 const u8 *tsem_pram_data; 1828 const u8 *usem_int_table_data; 1829 const u8 *usem_pram_data; 1830 const u8 *xsem_int_table_data; 1831 const u8 *xsem_pram_data; 1832 const u8 *csem_int_table_data; 1833 const u8 *csem_pram_data; 1834#define INIT_OPS(bp) (bp->init_ops) 1835#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1836#define INIT_DATA(bp) (bp->init_data) 1837#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1838#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1839#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1840#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1841#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1842#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1843#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1844#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1845 1846#define PHY_FW_VER_LEN 20 1847 char fw_ver[32]; 1848 const struct firmware *firmware; 1849 1850 struct bnx2x_vfdb *vfdb; 1851#define IS_SRIOV(bp) ((bp)->vfdb) 1852 1853 /* DCB support on/off */ 1854 u16 dcb_state; 1855#define BNX2X_DCB_STATE_OFF 0 1856#define BNX2X_DCB_STATE_ON 1 1857 1858 /* DCBX engine mode */ 1859 int dcbx_enabled; 1860#define BNX2X_DCBX_ENABLED_OFF 0 1861#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1862#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1863#define BNX2X_DCBX_ENABLED_INVALID (-1) 1864 1865 bool dcbx_mode_uset; 1866 1867 struct bnx2x_config_dcbx_params dcbx_config_params; 1868 struct bnx2x_dcbx_port_params dcbx_port_params; 1869 int dcb_version; 1870 1871 /* CAM credit pools */ 1872 1873 /* used only in sriov */ 1874 struct bnx2x_credit_pool_obj vlans_pool; 1875 1876 struct bnx2x_credit_pool_obj macs_pool; 1877 1878 /* RX_MODE object */ 1879 struct bnx2x_rx_mode_obj rx_mode_obj; 1880 1881 /* MCAST object */ 1882 struct bnx2x_mcast_obj mcast_obj; 1883 1884 /* RSS configuration object */ 1885 struct bnx2x_rss_config_obj rss_conf_obj; 1886 1887 /* Function State controlling object */ 1888 struct bnx2x_func_sp_obj func_obj; 1889 1890 unsigned long sp_state; 1891 1892 /* operation indication for the sp_rtnl task */ 1893 unsigned long sp_rtnl_state; 1894 1895 /* DCBX Negotiation results */ 1896 struct dcbx_features dcbx_local_feat; 1897 u32 dcbx_error; 1898 1899#ifdef BCM_DCBNL 1900 struct dcbx_features dcbx_remote_feat; 1901 u32 dcbx_remote_flags; 1902#endif 1903 /* AFEX: store default vlan used */ 1904 int afex_def_vlan_tag; 1905 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1906 u32 pending_max; 1907 1908 /* multiple tx classes of service */ 1909 u8 max_cos; 1910 1911 /* priority to cos mapping */ 1912 u8 prio_to_cos[8]; 1913 1914 int fp_array_size; 1915 u32 dump_preset_idx; 1916 bool stats_started; 1917 struct semaphore stats_sema; 1918 1919 u8 phys_port_id[ETH_ALEN]; 1920}; 1921 1922/* Tx queues may be less or equal to Rx queues */ 1923extern int num_queues; 1924#define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1925#define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 1926#define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 1927 (bp)->num_cnic_queues) 1928#define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1929 1930#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1931 1932#define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1933/* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1934 1935#define RSS_IPV4_CAP_MASK \ 1936 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1937 1938#define RSS_IPV4_TCP_CAP_MASK \ 1939 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1940 1941#define RSS_IPV6_CAP_MASK \ 1942 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1943 1944#define RSS_IPV6_TCP_CAP_MASK \ 1945 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1946 1947/* func init flags */ 1948#define FUNC_FLG_RSS 0x0001 1949#define FUNC_FLG_STATS 0x0002 1950/* removed FUNC_FLG_UNMATCHED 0x0004 */ 1951#define FUNC_FLG_TPA 0x0008 1952#define FUNC_FLG_SPQ 0x0010 1953#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1954#define FUNC_FLG_LEADING_STATS 0x0040 1955struct bnx2x_func_init_params { 1956 /* dma */ 1957 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1958 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1959 1960 u16 func_flgs; 1961 u16 func_id; /* abs fid */ 1962 u16 pf_id; 1963 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1964}; 1965 1966#define for_each_cnic_queue(bp, var) \ 1967 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1968 (var)++) \ 1969 if (skip_queue(bp, var)) \ 1970 continue; \ 1971 else 1972 1973#define for_each_eth_queue(bp, var) \ 1974 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1975 1976#define for_each_nondefault_eth_queue(bp, var) \ 1977 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1978 1979#define for_each_queue(bp, var) \ 1980 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1981 if (skip_queue(bp, var)) \ 1982 continue; \ 1983 else 1984 1985/* Skip forwarding FP */ 1986#define for_each_valid_rx_queue(bp, var) \ 1987 for ((var) = 0; \ 1988 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1989 BNX2X_NUM_ETH_QUEUES(bp)); \ 1990 (var)++) \ 1991 if (skip_rx_queue(bp, var)) \ 1992 continue; \ 1993 else 1994 1995#define for_each_rx_queue_cnic(bp, var) \ 1996 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1997 (var)++) \ 1998 if (skip_rx_queue(bp, var)) \ 1999 continue; \ 2000 else 2001 2002#define for_each_rx_queue(bp, var) \ 2003 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2004 if (skip_rx_queue(bp, var)) \ 2005 continue; \ 2006 else 2007 2008/* Skip OOO FP */ 2009#define for_each_valid_tx_queue(bp, var) \ 2010 for ((var) = 0; \ 2011 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 2012 BNX2X_NUM_ETH_QUEUES(bp)); \ 2013 (var)++) \ 2014 if (skip_tx_queue(bp, var)) \ 2015 continue; \ 2016 else 2017 2018#define for_each_tx_queue_cnic(bp, var) \ 2019 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 2020 (var)++) \ 2021 if (skip_tx_queue(bp, var)) \ 2022 continue; \ 2023 else 2024 2025#define for_each_tx_queue(bp, var) \ 2026 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2027 if (skip_tx_queue(bp, var)) \ 2028 continue; \ 2029 else 2030 2031#define for_each_nondefault_queue(bp, var) \ 2032 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 2033 if (skip_queue(bp, var)) \ 2034 continue; \ 2035 else 2036 2037#define for_each_cos_in_tx_queue(fp, var) \ 2038 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 2039 2040/* skip rx queue 2041 * if FCOE l2 support is disabled and this is the fcoe L2 queue 2042 */ 2043#define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2044 2045/* skip tx queue 2046 * if FCOE l2 support is disabled and this is the fcoe L2 queue 2047 */ 2048#define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2049 2050#define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2051 2052/** 2053 * bnx2x_set_mac_one - configure a single MAC address 2054 * 2055 * @bp: driver handle 2056 * @mac: MAC to configure 2057 * @obj: MAC object handle 2058 * @set: if 'true' add a new MAC, otherwise - delete 2059 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 2060 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 2061 * 2062 * Configures one MAC according to provided parameters or continues the 2063 * execution of previously scheduled commands if RAMROD_CONT is set in 2064 * ramrod_flags. 2065 * 2066 * Returns zero if operation has successfully completed, a positive value if the 2067 * operation has been successfully scheduled and a negative - if a requested 2068 * operations has failed. 2069 */ 2070int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 2071 struct bnx2x_vlan_mac_obj *obj, bool set, 2072 int mac_type, unsigned long *ramrod_flags); 2073/** 2074 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 2075 * 2076 * @bp: driver handle 2077 * @mac_obj: MAC object handle 2078 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 2079 * @wait_for_comp: if 'true' block until completion 2080 * 2081 * Deletes all MACs of the specific type (e.g. ETH, UC list). 2082 * 2083 * Returns zero if operation has successfully completed, a positive value if the 2084 * operation has been successfully scheduled and a negative - if a requested 2085 * operations has failed. 2086 */ 2087int bnx2x_del_all_macs(struct bnx2x *bp, 2088 struct bnx2x_vlan_mac_obj *mac_obj, 2089 int mac_type, bool wait_for_comp); 2090 2091/* Init Function API */ 2092void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 2093void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 2094 u8 vf_valid, int fw_sb_id, int igu_sb_id); 2095int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 2096int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2097int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 2098int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2099void bnx2x_read_mf_cfg(struct bnx2x *bp); 2100 2101int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 2102 2103/* dmae */ 2104void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 2105void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 2106 u32 len32); 2107void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 2108u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 2109u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 2110u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 2111 bool with_comp, u8 comp_type); 2112 2113void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2114 u8 src_type, u8 dst_type); 2115int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2116 u32 *comp); 2117 2118/* FLR related routines */ 2119u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); 2120void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); 2121int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); 2122u8 bnx2x_is_pcie_pending(struct pci_dev *dev); 2123int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 2124 char *msg, u32 poll_cnt); 2125 2126void bnx2x_calc_fc_adv(struct bnx2x *bp); 2127int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 2128 u32 data_hi, u32 data_lo, int cmd_type); 2129void bnx2x_update_coalesce(struct bnx2x *bp); 2130int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 2131 2132bool bnx2x_port_after_undi(struct bnx2x *bp); 2133 2134static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 2135 int wait) 2136{ 2137 u32 val; 2138 2139 do { 2140 val = REG_RD(bp, reg); 2141 if (val == expected) 2142 break; 2143 ms -= wait; 2144 msleep(wait); 2145 2146 } while (ms > 0); 2147 2148 return val; 2149} 2150 2151void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, 2152 bool is_pf); 2153 2154#define BNX2X_ILT_ZALLOC(x, y, size) \ 2155 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL) 2156 2157#define BNX2X_ILT_FREE(x, y, size) \ 2158 do { \ 2159 if (x) { \ 2160 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 2161 x = NULL; \ 2162 y = 0; \ 2163 } \ 2164 } while (0) 2165 2166#define ILOG2(x) (ilog2((x))) 2167 2168#define ILT_NUM_PAGE_ENTRIES (3072) 2169/* In 57710/11 we use whole table since we have 8 func 2170 * In 57712 we have only 4 func, but use same size per func, then only half of 2171 * the table in use 2172 */ 2173#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 2174 2175#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 2176/* 2177 * the phys address is shifted right 12 bits and has an added 2178 * 1=valid bit added to the 53rd bit 2179 * then since this is a wide register(TM) 2180 * we split it into two 32 bit writes 2181 */ 2182#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 2183#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 2184 2185/* load/unload mode */ 2186#define LOAD_NORMAL 0 2187#define LOAD_OPEN 1 2188#define LOAD_DIAG 2 2189#define LOAD_LOOPBACK_EXT 3 2190#define UNLOAD_NORMAL 0 2191#define UNLOAD_CLOSE 1 2192#define UNLOAD_RECOVERY 2 2193 2194/* DMAE command defines */ 2195#define DMAE_TIMEOUT -1 2196#define DMAE_PCI_ERROR -2 /* E2 and onward */ 2197#define DMAE_NOT_RDY -3 2198#define DMAE_PCI_ERR_FLAG 0x80000000 2199 2200#define DMAE_SRC_PCI 0 2201#define DMAE_SRC_GRC 1 2202 2203#define DMAE_DST_NONE 0 2204#define DMAE_DST_PCI 1 2205#define DMAE_DST_GRC 2 2206 2207#define DMAE_COMP_PCI 0 2208#define DMAE_COMP_GRC 1 2209 2210/* E2 and onward - PCI error handling in the completion */ 2211 2212#define DMAE_COMP_REGULAR 0 2213#define DMAE_COM_SET_ERR 1 2214 2215#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 2216 DMAE_COMMAND_SRC_SHIFT) 2217#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 2218 DMAE_COMMAND_SRC_SHIFT) 2219 2220#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 2221 DMAE_COMMAND_DST_SHIFT) 2222#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 2223 DMAE_COMMAND_DST_SHIFT) 2224 2225#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 2226 DMAE_COMMAND_C_DST_SHIFT) 2227#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 2228 DMAE_COMMAND_C_DST_SHIFT) 2229 2230#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 2231 2232#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2233#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2234#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2235#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2236 2237#define DMAE_CMD_PORT_0 0 2238#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2239 2240#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 2241#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 2242#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 2243 2244#define DMAE_SRC_PF 0 2245#define DMAE_SRC_VF 1 2246 2247#define DMAE_DST_PF 0 2248#define DMAE_DST_VF 1 2249 2250#define DMAE_C_SRC 0 2251#define DMAE_C_DST 1 2252 2253#define DMAE_LEN32_RD_MAX 0x80 2254#define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 2255 2256#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 2257 * indicates error 2258 */ 2259 2260#define MAX_DMAE_C_PER_PORT 8 2261#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2262 BP_VN(bp)) 2263#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2264 E1HVN_MAX) 2265 2266/* PCIE link and speed */ 2267#define PCICFG_LINK_WIDTH 0x1f00000 2268#define PCICFG_LINK_WIDTH_SHIFT 20 2269#define PCICFG_LINK_SPEED 0xf0000 2270#define PCICFG_LINK_SPEED_SHIFT 16 2271 2272#define BNX2X_NUM_TESTS_SF 7 2273#define BNX2X_NUM_TESTS_MF 3 2274#define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 2275 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF) 2276 2277#define BNX2X_PHY_LOOPBACK 0 2278#define BNX2X_MAC_LOOPBACK 1 2279#define BNX2X_EXT_LOOPBACK 2 2280#define BNX2X_PHY_LOOPBACK_FAILED 1 2281#define BNX2X_MAC_LOOPBACK_FAILED 2 2282#define BNX2X_EXT_LOOPBACK_FAILED 3 2283#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2284 BNX2X_PHY_LOOPBACK_FAILED) 2285 2286#define STROM_ASSERT_ARRAY_SIZE 50 2287 2288/* must be used on a CID before placing it on a HW ring */ 2289#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 2290 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2291 (x)) 2292 2293#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2294#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2295 2296#define BNX2X_BTR 4 2297#define MAX_SPQ_PENDING 8 2298 2299/* CMNG constants, as derived from system spec calculations */ 2300/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2301#define DEF_MIN_RATE 100 2302/* resolution of the rate shaping timer - 400 usec */ 2303#define RS_PERIODIC_TIMEOUT_USEC 400 2304/* number of bytes in single QM arbitration cycle - 2305 * coefficient for calculating the fairness timer */ 2306#define QM_ARB_BYTES 160000 2307/* resolution of Min algorithm 1:100 */ 2308#define MIN_RES 100 2309/* how many bytes above threshold for the minimal credit of Min algorithm*/ 2310#define MIN_ABOVE_THRESH 32768 2311/* Fairness algorithm integration time coefficient - 2312 * for calculating the actual Tfair */ 2313#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2314/* Memory of fairness algorithm . 2 cycles */ 2315#define FAIR_MEM 2 2316 2317#define ATTN_NIG_FOR_FUNC (1L << 8) 2318#define ATTN_SW_TIMER_4_FUNC (1L << 9) 2319#define GPIO_2_FUNC (1L << 10) 2320#define GPIO_3_FUNC (1L << 11) 2321#define GPIO_4_FUNC (1L << 12) 2322#define ATTN_GENERAL_ATTN_1 (1L << 13) 2323#define ATTN_GENERAL_ATTN_2 (1L << 14) 2324#define ATTN_GENERAL_ATTN_3 (1L << 15) 2325#define ATTN_GENERAL_ATTN_4 (1L << 13) 2326#define ATTN_GENERAL_ATTN_5 (1L << 14) 2327#define ATTN_GENERAL_ATTN_6 (1L << 15) 2328 2329#define ATTN_HARD_WIRED_MASK 0xff00 2330#define ATTENTION_ID 4 2331 2332#define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_SD(bp) || \ 2333 IS_MF_FCOE_AFEX(bp)) 2334 2335/* stuff added to make the code fit 80Col */ 2336 2337#define BNX2X_PMF_LINK_ASSERT \ 2338 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2339 2340#define BNX2X_MC_ASSERT_BITS \ 2341 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2342 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2343 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2344 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2345 2346#define BNX2X_MCP_ASSERT \ 2347 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2348 2349#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2350#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2351 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2352 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2353 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2354 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2355 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2356 2357#define HW_INTERRUT_ASSERT_SET_0 \ 2358 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2359 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2360 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2361 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ 2362 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2363#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2364 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2365 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2366 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2367 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2368 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2369 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2370#define HW_INTERRUT_ASSERT_SET_1 \ 2371 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2372 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2373 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2374 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2375 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2376 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2377 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2378 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2379 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2380 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2381 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2382#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2383 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2384 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2385 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2386 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2387 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2388 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2389 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2390 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2391 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2392 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2393 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2394 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2395 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2396 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2397 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2398#define HW_INTERRUT_ASSERT_SET_2 \ 2399 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2400 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2401 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2402 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2403 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2404#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2405 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2406 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2407 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2408 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2409 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2410 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2411 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2412 2413#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2414 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2415 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2416 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2417 2418#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2419 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2420 2421#define MULTI_MASK 0x7f 2422 2423#define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2424#define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2425#define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2426#define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2427 2428#define DEF_USB_IGU_INDEX_OFF \ 2429 offsetof(struct cstorm_def_status_block_u, igu_index) 2430#define DEF_CSB_IGU_INDEX_OFF \ 2431 offsetof(struct cstorm_def_status_block_c, igu_index) 2432#define DEF_XSB_IGU_INDEX_OFF \ 2433 offsetof(struct xstorm_def_status_block, igu_index) 2434#define DEF_TSB_IGU_INDEX_OFF \ 2435 offsetof(struct tstorm_def_status_block, igu_index) 2436 2437#define DEF_USB_SEGMENT_OFF \ 2438 offsetof(struct cstorm_def_status_block_u, segment) 2439#define DEF_CSB_SEGMENT_OFF \ 2440 offsetof(struct cstorm_def_status_block_c, segment) 2441#define DEF_XSB_SEGMENT_OFF \ 2442 offsetof(struct xstorm_def_status_block, segment) 2443#define DEF_TSB_SEGMENT_OFF \ 2444 offsetof(struct tstorm_def_status_block, segment) 2445 2446#define BNX2X_SP_DSB_INDEX \ 2447 (&bp->def_status_blk->sp_sb.\ 2448 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2449 2450#define CAM_IS_INVALID(x) \ 2451 (GET_FLAG(x.flags, \ 2452 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2453 (T_ETH_MAC_COMMAND_INVALIDATE)) 2454 2455/* Number of u32 elements in MC hash array */ 2456#define MC_HASH_SIZE 8 2457#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2458 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2459 2460#ifndef PXP2_REG_PXP2_INT_STS 2461#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2462#endif 2463 2464#ifndef ETH_MAX_RX_CLIENTS_E2 2465#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2466#endif 2467 2468#define BNX2X_VPD_LEN 128 2469#define VENDOR_ID_LEN 4 2470 2471#define VF_ACQUIRE_THRESH 3 2472#define VF_ACQUIRE_MAC_FILTERS 1 2473#define VF_ACQUIRE_MC_FILTERS 10 2474 2475#define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2476 (!((me_reg) & ME_REG_VF_ERR))) 2477int bnx2x_compare_fw_ver(struct bnx2x *bp, u32 load_code, bool print_err); 2478 2479/* Congestion management fairness mode */ 2480#define CMNG_FNS_NONE 0 2481#define CMNG_FNS_MINMAX 1 2482 2483#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2484#define HC_SEG_ACCESS_ATTN 4 2485#define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2486 2487static const u32 dmae_reg_go_c[] = { 2488 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2489 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2490 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2491 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2492}; 2493 2494void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); 2495void bnx2x_notify_link_changed(struct bnx2x *bp); 2496 2497#define BNX2X_MF_SD_PROTOCOL(bp) \ 2498 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2499 2500#define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 2501 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2502 2503#define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 2504 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 2505 2506#define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 2507#define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 2508 2509#define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \ 2510 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2511 2512#define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp)) 2513#define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \ 2514 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 2515 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2516 2517#define SET_FLAG(value, mask, flag) \ 2518 do {\ 2519 (value) &= ~(mask);\ 2520 (value) |= ((flag) << (mask##_SHIFT));\ 2521 } while (0) 2522 2523#define GET_FLAG(value, mask) \ 2524 (((value) & (mask)) >> (mask##_SHIFT)) 2525 2526#define GET_FIELD(value, fname) \ 2527 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2528 2529enum { 2530 SWITCH_UPDATE, 2531 AFEX_UPDATE, 2532}; 2533 2534#define NUM_MACS 8 2535 2536void bnx2x_set_local_cmng(struct bnx2x *bp); 2537 2538#define MCPR_SCRATCH_BASE(bp) \ 2539 (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 2540 2541#define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX)) 2542 2543#endif /* bnx2x.h */ 2544