bnx2x.h revision 55c11941e382cb26010138ab824216f47af37606
1/* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14#ifndef BNX2X_H 15#define BNX2X_H 16#include <linux/netdevice.h> 17#include <linux/dma-mapping.h> 18#include <linux/types.h> 19 20/* compilation time flags */ 21 22/* define this to make the driver freeze on error to allow getting debug info 23 * (you will need to reboot afterwards) */ 24/* #define BNX2X_STOP_ON_ERROR */ 25 26#define DRV_MODULE_VERSION "1.78.00-0" 27#define DRV_MODULE_RELDATE "2012/09/27" 28#define BNX2X_BC_VER 0x040200 29 30#if defined(CONFIG_DCB) 31#define BCM_DCBNL 32#endif 33 34 35#include "bnx2x_hsi.h" 36 37#include "../cnic_if.h" 38 39 40#define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 41 42#include <linux/mdio.h> 43 44#include "bnx2x_reg.h" 45#include "bnx2x_fw_defs.h" 46#include "bnx2x_mfw_req.h" 47#include "bnx2x_hsi.h" 48#include "bnx2x_link.h" 49#include "bnx2x_sp.h" 50#include "bnx2x_dcb.h" 51#include "bnx2x_stats.h" 52 53/* error/debug prints */ 54 55#define DRV_MODULE_NAME "bnx2x" 56 57/* for messages that are currently off */ 58#define BNX2X_MSG_OFF 0x0 59#define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 60#define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 61#define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 62#define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 63#define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 64#define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 65#define BNX2X_MSG_IOV 0x0800000 66#define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 67#define BNX2X_MSG_ETHTOOL 0x4000000 68#define BNX2X_MSG_DCB 0x8000000 69 70/* regular debug print */ 71#define DP(__mask, fmt, ...) \ 72do { \ 73 if (unlikely(bp->msg_enable & (__mask))) \ 74 pr_notice("[%s:%d(%s)]" fmt, \ 75 __func__, __LINE__, \ 76 bp->dev ? (bp->dev->name) : "?", \ 77 ##__VA_ARGS__); \ 78} while (0) 79 80#define DP_CONT(__mask, fmt, ...) \ 81do { \ 82 if (unlikely(bp->msg_enable & (__mask))) \ 83 pr_cont(fmt, ##__VA_ARGS__); \ 84} while (0) 85 86/* errors debug print */ 87#define BNX2X_DBG_ERR(fmt, ...) \ 88do { \ 89 if (unlikely(netif_msg_probe(bp))) \ 90 pr_err("[%s:%d(%s)]" fmt, \ 91 __func__, __LINE__, \ 92 bp->dev ? (bp->dev->name) : "?", \ 93 ##__VA_ARGS__); \ 94} while (0) 95 96/* for errors (never masked) */ 97#define BNX2X_ERR(fmt, ...) \ 98do { \ 99 pr_err("[%s:%d(%s)]" fmt, \ 100 __func__, __LINE__, \ 101 bp->dev ? (bp->dev->name) : "?", \ 102 ##__VA_ARGS__); \ 103} while (0) 104 105#define BNX2X_ERROR(fmt, ...) \ 106 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 107 108 109/* before we have a dev->name use dev_info() */ 110#define BNX2X_DEV_INFO(fmt, ...) \ 111do { \ 112 if (unlikely(netif_msg_probe(bp))) \ 113 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 114} while (0) 115 116#ifdef BNX2X_STOP_ON_ERROR 117void bnx2x_int_disable(struct bnx2x *bp); 118#define bnx2x_panic() \ 119do { \ 120 bp->panic = 1; \ 121 BNX2X_ERR("driver assert\n"); \ 122 bnx2x_int_disable(bp); \ 123 bnx2x_panic_dump(bp); \ 124} while (0) 125#else 126#define bnx2x_panic() \ 127do { \ 128 bp->panic = 1; \ 129 BNX2X_ERR("driver assert\n"); \ 130 bnx2x_panic_dump(bp); \ 131} while (0) 132#endif 133 134#define bnx2x_mc_addr(ha) ((ha)->addr) 135#define bnx2x_uc_addr(ha) ((ha)->addr) 136 137#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) 138#define U64_HI(x) (u32)(((u64)(x)) >> 32) 139#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 140 141 142#define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 143 144#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 145#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 146#define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 147 148#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 149#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 150#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 151 152#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 153#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 154 155#define REG_RD_DMAE(bp, offset, valp, len32) \ 156 do { \ 157 bnx2x_read_dmae(bp, offset, len32);\ 158 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 159 } while (0) 160 161#define REG_WR_DMAE(bp, offset, valp, len32) \ 162 do { \ 163 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 164 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 165 offset, len32); \ 166 } while (0) 167 168#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 169 REG_WR_DMAE(bp, offset, valp, len32) 170 171#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 172 do { \ 173 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 174 bnx2x_write_big_buf_wb(bp, addr, len32); \ 175 } while (0) 176 177#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 178 offsetof(struct shmem_region, field)) 179#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 180#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 181 182#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 183 offsetof(struct shmem2_region, field)) 184#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 185#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 186#define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 187 offsetof(struct mf_cfg, field)) 188#define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 189 offsetof(struct mf2_cfg, field)) 190 191#define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 192#define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 193 MF_CFG_ADDR(bp, field), (val)) 194#define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 195 196#define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 197 (SHMEM2_RD((bp), size) > \ 198 offsetof(struct shmem2_region, field))) 199 200#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 201#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 202 203/* SP SB indices */ 204 205/* General SP events - stats query, cfc delete, etc */ 206#define HC_SP_INDEX_ETH_DEF_CONS 3 207 208/* EQ completions */ 209#define HC_SP_INDEX_EQ_CONS 7 210 211/* FCoE L2 connection completions */ 212#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 213#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 214/* iSCSI L2 */ 215#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 216#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 217 218/* Special clients parameters */ 219 220/* SB indices */ 221/* FCoE L2 */ 222#define BNX2X_FCOE_L2_RX_INDEX \ 223 (&bp->def_status_blk->sp_sb.\ 224 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 225 226#define BNX2X_FCOE_L2_TX_INDEX \ 227 (&bp->def_status_blk->sp_sb.\ 228 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 229 230/** 231 * CIDs and CLIDs: 232 * CLIDs below is a CLID for func 0, then the CLID for other 233 * functions will be calculated by the formula: 234 * 235 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 236 * 237 */ 238enum { 239 BNX2X_ISCSI_ETH_CL_ID_IDX, 240 BNX2X_FCOE_ETH_CL_ID_IDX, 241 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 242}; 243 244#define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\ 245 (bp)->max_cos) 246 /* iSCSI L2 */ 247#define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 248 /* FCoE L2 */ 249#define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 250 251#define CNIC_SUPPORT(bp) ((bp)->cnic_support) 252#define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 253#define CNIC_LOADED(bp) ((bp)->cnic_loaded) 254#define FCOE_INIT(bp) ((bp)->fcoe_init) 255 256#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 257 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 258 259#define SM_RX_ID 0 260#define SM_TX_ID 1 261 262/* defines for multiple tx priority indices */ 263#define FIRST_TX_ONLY_COS_INDEX 1 264#define FIRST_TX_COS_INDEX 0 265 266/* rules for calculating the cids of tx-only connections */ 267#define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 268#define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 269 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 270 271/* fp index inside class of service range */ 272#define FP_COS_TO_TXQ(fp, cos, bp) \ 273 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 274 275/* Indexes for transmission queues array: 276 * txdata for RSS i CoS j is at location i + (j * num of RSS) 277 * txdata for FCoE (if exist) is at location max cos * num of RSS 278 * txdata for FWD (if exist) is one location after FCoE 279 * txdata for OOO (if exist) is one location after FWD 280 */ 281enum { 282 FCOE_TXQ_IDX_OFFSET, 283 FWD_TXQ_IDX_OFFSET, 284 OOO_TXQ_IDX_OFFSET, 285}; 286#define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 287#define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 288 289/* fast path */ 290/* 291 * This driver uses new build_skb() API : 292 * RX ring buffer contains pointer to kmalloc() data only, 293 * skb are built only after Hardware filled the frame. 294 */ 295struct sw_rx_bd { 296 u8 *data; 297 DEFINE_DMA_UNMAP_ADDR(mapping); 298}; 299 300struct sw_tx_bd { 301 struct sk_buff *skb; 302 u16 first_bd; 303 u8 flags; 304/* Set on the first BD descriptor when there is a split BD */ 305#define BNX2X_TSO_SPLIT_BD (1<<0) 306}; 307 308struct sw_rx_page { 309 struct page *page; 310 DEFINE_DMA_UNMAP_ADDR(mapping); 311}; 312 313union db_prod { 314 struct doorbell_set_prod data; 315 u32 raw; 316}; 317 318/* dropless fc FW/HW related params */ 319#define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 320#define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 321 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 322 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 323#define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 324#define FW_PREFETCH_CNT 16 325#define DROPLESS_FC_HEADROOM 100 326 327/* MC hsi */ 328#define BCM_PAGE_SHIFT 12 329#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 330#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 331#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 332 333#define PAGES_PER_SGE_SHIFT 0 334#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 335#define SGE_PAGE_SIZE PAGE_SIZE 336#define SGE_PAGE_SHIFT PAGE_SHIFT 337#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 338 339/* SGE ring related macros */ 340#define NUM_RX_SGE_PAGES 2 341#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 342#define NEXT_PAGE_SGE_DESC_CNT 2 343#define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 344/* RX_SGE_CNT is promised to be a power of 2 */ 345#define RX_SGE_MASK (RX_SGE_CNT - 1) 346#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 347#define MAX_RX_SGE (NUM_RX_SGE - 1) 348#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 349 (MAX_RX_SGE_CNT - 1)) ? \ 350 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 351 (x) + 1) 352#define RX_SGE(x) ((x) & MAX_RX_SGE) 353 354/* 355 * Number of required SGEs is the sum of two: 356 * 1. Number of possible opened aggregations (next packet for 357 * these aggregations will probably consume SGE immidiatelly) 358 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 359 * after placement on BD for new TPA aggregation) 360 * 361 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 362 */ 363#define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 364 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 365#define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 366 MAX_RX_SGE_CNT) 367#define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 368 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 369#define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 370 371/* Manipulate a bit vector defined as an array of u64 */ 372 373/* Number of bits in one sge_mask array element */ 374#define BIT_VEC64_ELEM_SZ 64 375#define BIT_VEC64_ELEM_SHIFT 6 376#define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 377 378 379#define __BIT_VEC64_SET_BIT(el, bit) \ 380 do { \ 381 el = ((el) | ((u64)0x1 << (bit))); \ 382 } while (0) 383 384#define __BIT_VEC64_CLEAR_BIT(el, bit) \ 385 do { \ 386 el = ((el) & (~((u64)0x1 << (bit)))); \ 387 } while (0) 388 389 390#define BIT_VEC64_SET_BIT(vec64, idx) \ 391 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 392 (idx) & BIT_VEC64_ELEM_MASK) 393 394#define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 395 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 396 (idx) & BIT_VEC64_ELEM_MASK) 397 398#define BIT_VEC64_TEST_BIT(vec64, idx) \ 399 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 400 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 401 402/* Creates a bitmask of all ones in less significant bits. 403 idx - index of the most significant bit in the created mask */ 404#define BIT_VEC64_ONES_MASK(idx) \ 405 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 406#define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 407 408/*******************************************************/ 409 410 411 412/* Number of u64 elements in SGE mask array */ 413#define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 414#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 415#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 416 417union host_hc_status_block { 418 /* pointer to fp status block e1x */ 419 struct host_hc_status_block_e1x *e1x_sb; 420 /* pointer to fp status block e2 */ 421 struct host_hc_status_block_e2 *e2_sb; 422}; 423 424struct bnx2x_agg_info { 425 /* 426 * First aggregation buffer is a data buffer, the following - are pages. 427 * We will preallocate the data buffer for each aggregation when 428 * we open the interface and will replace the BD at the consumer 429 * with this one when we receive the TPA_START CQE in order to 430 * keep the Rx BD ring consistent. 431 */ 432 struct sw_rx_bd first_buf; 433 u8 tpa_state; 434#define BNX2X_TPA_START 1 435#define BNX2X_TPA_STOP 2 436#define BNX2X_TPA_ERROR 3 437 u8 placement_offset; 438 u16 parsing_flags; 439 u16 vlan_tag; 440 u16 len_on_bd; 441 u32 rxhash; 442 bool l4_rxhash; 443 u16 gro_size; 444 u16 full_page; 445}; 446 447#define Q_STATS_OFFSET32(stat_name) \ 448 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 449 450struct bnx2x_fp_txdata { 451 452 struct sw_tx_bd *tx_buf_ring; 453 454 union eth_tx_bd_types *tx_desc_ring; 455 dma_addr_t tx_desc_mapping; 456 457 u32 cid; 458 459 union db_prod tx_db; 460 461 u16 tx_pkt_prod; 462 u16 tx_pkt_cons; 463 u16 tx_bd_prod; 464 u16 tx_bd_cons; 465 466 unsigned long tx_pkt; 467 468 __le16 *tx_cons_sb; 469 470 int txq_index; 471 struct bnx2x_fastpath *parent_fp; 472 int tx_ring_size; 473}; 474 475enum bnx2x_tpa_mode_t { 476 TPA_MODE_LRO, 477 TPA_MODE_GRO 478}; 479 480struct bnx2x_fastpath { 481 struct bnx2x *bp; /* parent */ 482 483#define BNX2X_NAPI_WEIGHT 128 484 struct napi_struct napi; 485 union host_hc_status_block status_blk; 486 /* chip independed shortcuts into sb structure */ 487 __le16 *sb_index_values; 488 __le16 *sb_running_index; 489 /* chip independed shortcut into rx_prods_offset memory */ 490 u32 ustorm_rx_prods_offset; 491 492 u32 rx_buf_size; 493 494 dma_addr_t status_blk_mapping; 495 496 enum bnx2x_tpa_mode_t mode; 497 498 u8 max_cos; /* actual number of active tx coses */ 499 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 500 501 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 502 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 503 504 struct eth_rx_bd *rx_desc_ring; 505 dma_addr_t rx_desc_mapping; 506 507 union eth_rx_cqe *rx_comp_ring; 508 dma_addr_t rx_comp_mapping; 509 510 /* SGE ring */ 511 struct eth_rx_sge *rx_sge_ring; 512 dma_addr_t rx_sge_mapping; 513 514 u64 sge_mask[RX_SGE_MASK_LEN]; 515 516 u32 cid; 517 518 __le16 fp_hc_idx; 519 520 u8 index; /* number in fp array */ 521 u8 rx_queue; /* index for skb_record */ 522 u8 cl_id; /* eth client id */ 523 u8 cl_qzone_id; 524 u8 fw_sb_id; /* status block number in FW */ 525 u8 igu_sb_id; /* status block number in HW */ 526 527 u16 rx_bd_prod; 528 u16 rx_bd_cons; 529 u16 rx_comp_prod; 530 u16 rx_comp_cons; 531 u16 rx_sge_prod; 532 /* The last maximal completed SGE */ 533 u16 last_max_sge; 534 __le16 *rx_cons_sb; 535 unsigned long rx_pkt, 536 rx_calls; 537 538 /* TPA related */ 539 struct bnx2x_agg_info *tpa_info; 540 u8 disable_tpa; 541#ifdef BNX2X_STOP_ON_ERROR 542 u64 tpa_queue_used; 543#endif 544 /* The size is calculated using the following: 545 sizeof name field from netdev structure + 546 4 ('-Xx-' string) + 547 4 (for the digits and to make it DWORD aligned) */ 548#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 549 char name[FP_NAME_SIZE]; 550}; 551 552#define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 553#define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 554#define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 555#define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 556 557/* Use 2500 as a mini-jumbo MTU for FCoE */ 558#define BNX2X_FCOE_MINI_JUMBO_MTU 2500 559 560#define FCOE_IDX_OFFSET 0 561 562#define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 563 FCOE_IDX_OFFSET) 564#define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 565#define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 566#define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 567#define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 568#define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 569 txdata_ptr[FIRST_TX_COS_INDEX] \ 570 ->var) 571 572 573#define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 574#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 575#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 576 577 578/* MC hsi */ 579#define MAX_FETCH_BD 13 /* HW max BDs per packet */ 580#define RX_COPY_THRESH 92 581 582#define NUM_TX_RINGS 16 583#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 584#define NEXT_PAGE_TX_DESC_CNT 1 585#define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 586#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 587#define MAX_TX_BD (NUM_TX_BD - 1) 588#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 589#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 590 (MAX_TX_DESC_CNT - 1)) ? \ 591 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 592 (x) + 1) 593#define TX_BD(x) ((x) & MAX_TX_BD) 594#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 595 596/* number of NEXT_PAGE descriptors may be required during placement */ 597#define NEXT_CNT_PER_TX_PKT(bds) \ 598 (((bds) + MAX_TX_DESC_CNT - 1) / \ 599 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 600/* max BDs per tx packet w/o next_pages: 601 * START_BD - describes packed 602 * START_BD(splitted) - includes unpaged data segment for GSO 603 * PARSING_BD - for TSO and CSUM data 604 * Frag BDs - decribes pages for frags 605 */ 606#define BDS_PER_TX_PKT 3 607#define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 608/* max BDs per tx packet including next pages */ 609#define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 610 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 611 612/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 613#define NUM_RX_RINGS 8 614#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 615#define NEXT_PAGE_RX_DESC_CNT 2 616#define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 617#define RX_DESC_MASK (RX_DESC_CNT - 1) 618#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 619#define MAX_RX_BD (NUM_RX_BD - 1) 620#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 621 622/* dropless fc calculations for BDs 623 * 624 * Number of BDs should as number of buffers in BRB: 625 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 626 * "next" elements on each page 627 */ 628#define NUM_BD_REQ BRB_SIZE(bp) 629#define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 630 MAX_RX_DESC_CNT) 631#define BD_TH_LO(bp) (NUM_BD_REQ + \ 632 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 633 FW_DROP_LEVEL(bp)) 634#define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 635 636#define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 637 638#define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 639 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 640 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 641#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 642#define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 643#define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 644 MIN_RX_AVAIL)) 645 646#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 647 (MAX_RX_DESC_CNT - 1)) ? \ 648 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 649 (x) + 1) 650#define RX_BD(x) ((x) & MAX_RX_BD) 651 652/* 653 * As long as CQE is X times bigger than BD entry we have to allocate X times 654 * more pages for CQ ring in order to keep it balanced with BD ring 655 */ 656#define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 657#define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 658#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 659#define NEXT_PAGE_RCQ_DESC_CNT 1 660#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 661#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 662#define MAX_RCQ_BD (NUM_RCQ_BD - 1) 663#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 664#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 665 (MAX_RCQ_DESC_CNT - 1)) ? \ 666 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 667 (x) + 1) 668#define RCQ_BD(x) ((x) & MAX_RCQ_BD) 669 670/* dropless fc calculations for RCQs 671 * 672 * Number of RCQs should be as number of buffers in BRB: 673 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 674 * "next" elements on each page 675 */ 676#define NUM_RCQ_REQ BRB_SIZE(bp) 677#define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 678 MAX_RCQ_DESC_CNT) 679#define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 680 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 681 FW_DROP_LEVEL(bp)) 682#define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 683 684 685/* This is needed for determining of last_max */ 686#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 687#define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 688 689 690#define BNX2X_SWCID_SHIFT 17 691#define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 692 693/* used on a CID received from the HW */ 694#define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 695#define CQE_CMD(x) (le32_to_cpu(x) >> \ 696 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 697 698#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 699 le32_to_cpu((bd)->addr_lo)) 700#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 701 702#define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 703#define BNX2X_DB_SHIFT 7 /* 128 bytes*/ 704#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 705#error "Min DB doorbell stride is 8" 706#endif 707#define DPM_TRIGER_TYPE 0x40 708#define DOORBELL(bp, cid, val) \ 709 do { \ 710 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ 711 DPM_TRIGER_TYPE); \ 712 } while (0) 713 714 715/* TX CSUM helpers */ 716#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 717 skb->csum_offset) 718#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 719 skb->csum_offset)) 720 721#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) 722 723#define XMIT_PLAIN 0 724#define XMIT_CSUM_V4 0x1 725#define XMIT_CSUM_V6 0x2 726#define XMIT_CSUM_TCP 0x4 727#define XMIT_GSO_V4 0x8 728#define XMIT_GSO_V6 0x10 729 730#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) 731#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) 732 733 734/* stuff added to make the code fit 80Col */ 735#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 736#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 737#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 738#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 739#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 740 741#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 742 743#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 744 (((le16_to_cpu(flags) & \ 745 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 746 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 747 == PRS_FLAG_OVERETH_IPV4) 748#define BNX2X_RX_SUM_FIX(cqe) \ 749 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 750 751 752#define FP_USB_FUNC_OFF \ 753 offsetof(struct cstorm_status_block_u, func) 754#define FP_CSB_FUNC_OFF \ 755 offsetof(struct cstorm_status_block_c, func) 756 757#define HC_INDEX_ETH_RX_CQ_CONS 1 758 759#define HC_INDEX_OOO_TX_CQ_CONS 4 760 761#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 762 763#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 764 765#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 766 767#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 768 769#define BNX2X_RX_SB_INDEX \ 770 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 771 772#define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 773 774#define BNX2X_TX_SB_INDEX_COS0 \ 775 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 776 777/* end of fast path */ 778 779/* common */ 780 781struct bnx2x_common { 782 783 u32 chip_id; 784/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 785#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 786 787#define CHIP_NUM(bp) (bp->common.chip_id >> 16) 788#define CHIP_NUM_57710 0x164e 789#define CHIP_NUM_57711 0x164f 790#define CHIP_NUM_57711E 0x1650 791#define CHIP_NUM_57712 0x1662 792#define CHIP_NUM_57712_MF 0x1663 793#define CHIP_NUM_57713 0x1651 794#define CHIP_NUM_57713E 0x1652 795#define CHIP_NUM_57800 0x168a 796#define CHIP_NUM_57800_MF 0x16a5 797#define CHIP_NUM_57810 0x168e 798#define CHIP_NUM_57810_MF 0x16ae 799#define CHIP_NUM_57811 0x163d 800#define CHIP_NUM_57811_MF 0x163e 801#define CHIP_NUM_57840_OBSOLETE 0x168d 802#define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 803#define CHIP_NUM_57840_4_10 0x16a1 804#define CHIP_NUM_57840_2_20 0x16a2 805#define CHIP_NUM_57840_MF 0x16a4 806#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 807#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 808#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 809#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 810#define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 811#define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 812#define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 813#define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 814#define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 815#define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 816#define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 817#define CHIP_IS_57840(bp) \ 818 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 819 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 820 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 821#define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 822 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 823#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 824 CHIP_IS_57711E(bp)) 825#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 826 CHIP_IS_57712_MF(bp)) 827#define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 828 CHIP_IS_57800_MF(bp) || \ 829 CHIP_IS_57810(bp) || \ 830 CHIP_IS_57810_MF(bp) || \ 831 CHIP_IS_57811(bp) || \ 832 CHIP_IS_57811_MF(bp) || \ 833 CHIP_IS_57840(bp) || \ 834 CHIP_IS_57840_MF(bp)) 835#define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 836#define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 837#define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 838 839#define CHIP_REV_SHIFT 12 840#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 841#define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 842#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 843#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 844/* assume maximum 5 revisions */ 845#define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 846/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 847#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 848 !(CHIP_REV_VAL(bp) & 0x00001000)) 849/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 850#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 851 (CHIP_REV_VAL(bp) & 0x00001000)) 852 853#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 854 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 855 856#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 857#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 858#define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 859 (CHIP_REV_SHIFT + 1)) \ 860 << CHIP_REV_SHIFT) 861#define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 862 CHIP_REV_SIM(bp) :\ 863 CHIP_REV_VAL(bp)) 864#define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 865 (CHIP_REV(bp) == CHIP_REV_Bx)) 866#define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 867 (CHIP_REV(bp) == CHIP_REV_Ax)) 868/* This define is used in two main places: 869 * 1. In the early stages of nic_load, to know if to configrue Parser / Searcher 870 * to nic-only mode or to offload mode. Offload mode is configured if either the 871 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 872 * registered for this port (which means that the user wants storage services). 873 * 2. During cnic-related load, to know if offload mode is already configured in 874 * the HW or needs to be configrued. 875 * Since the transition from nic-mode to offload-mode in HW causes traffic 876 * coruption, nic-mode is configured only in ports on which storage services 877 * where never requested. 878 */ 879#define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 880 881 int flash_size; 882#define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 883#define BNX2X_NVRAM_TIMEOUT_COUNT 30000 884#define BNX2X_NVRAM_PAGE_SIZE 256 885 886 u32 shmem_base; 887 u32 shmem2_base; 888 u32 mf_cfg_base; 889 u32 mf2_cfg_base; 890 891 u32 hw_config; 892 893 u32 bc_ver; 894 895 u8 int_block; 896#define INT_BLOCK_HC 0 897#define INT_BLOCK_IGU 1 898#define INT_BLOCK_MODE_NORMAL 0 899#define INT_BLOCK_MODE_BW_COMP 2 900#define CHIP_INT_MODE_IS_NBC(bp) \ 901 (!CHIP_IS_E1x(bp) && \ 902 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 903#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 904 905 u8 chip_port_mode; 906#define CHIP_4_PORT_MODE 0x0 907#define CHIP_2_PORT_MODE 0x1 908#define CHIP_PORT_MODE_NONE 0x2 909#define CHIP_MODE(bp) (bp->common.chip_port_mode) 910#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 911 912 u32 boot_mode; 913}; 914 915/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 916#define BNX2X_IGU_STAS_MSG_VF_CNT 64 917#define BNX2X_IGU_STAS_MSG_PF_CNT 4 918 919/* end of common */ 920 921/* port */ 922 923struct bnx2x_port { 924 u32 pmf; 925 926 u32 link_config[LINK_CONFIG_SIZE]; 927 928 u32 supported[LINK_CONFIG_SIZE]; 929/* link settings - missing defines */ 930#define SUPPORTED_2500baseX_Full (1 << 15) 931 932 u32 advertising[LINK_CONFIG_SIZE]; 933/* link settings - missing defines */ 934#define ADVERTISED_2500baseX_Full (1 << 15) 935 936 u32 phy_addr; 937 938 /* used to synchronize phy accesses */ 939 struct mutex phy_mutex; 940 int need_hw_lock; 941 942 u32 port_stx; 943 944 struct nig_stats old_nig_stats; 945}; 946 947/* end of port */ 948 949#define STATS_OFFSET32(stat_name) \ 950 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 951 952/* slow path */ 953 954/* slow path work-queue */ 955extern struct workqueue_struct *bnx2x_wq; 956 957#define BNX2X_MAX_NUM_OF_VFS 64 958#define BNX2X_VF_ID_INVALID 0xFF 959 960/* 961 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 962 * control by the number of fast-path status blocks supported by the 963 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 964 * status block represents an independent interrupts context that can 965 * serve a regular L2 networking queue. However special L2 queues such 966 * as the FCoE queue do not require a FP-SB and other components like 967 * the CNIC may consume FP-SB reducing the number of possible L2 queues 968 * 969 * If the maximum number of FP-SB available is X then: 970 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 971 * regular L2 queues is Y=X-1 972 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 973 * c. If the FCoE L2 queue is supported the actual number of L2 queues 974 * is Y+1 975 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 976 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 977 * FP interrupt context for the CNIC). 978 * e. The number of HW context (CID count) is always X or X+1 if FCoE 979 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 980 */ 981 982/* fast-path interrupt contexts E1x */ 983#define FP_SB_MAX_E1x 16 984/* fast-path interrupt contexts E2 */ 985#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 986 987union cdu_context { 988 struct eth_context eth; 989 char pad[1024]; 990}; 991 992/* CDU host DB constants */ 993#define CDU_ILT_PAGE_SZ_HW 2 994#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 995#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 996 997#define CNIC_ISCSI_CID_MAX 256 998#define CNIC_FCOE_CID_MAX 2048 999#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1000#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1001 1002#define QM_ILT_PAGE_SZ_HW 0 1003#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1004#define QM_CID_ROUND 1024 1005 1006/* TM (timers) host DB constants */ 1007#define TM_ILT_PAGE_SZ_HW 0 1008#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1009/* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 1010#define TM_CONN_NUM 1024 1011#define TM_ILT_SZ (8 * TM_CONN_NUM) 1012#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1013 1014/* SRC (Searcher) host DB constants */ 1015#define SRC_ILT_PAGE_SZ_HW 0 1016#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1017#define SRC_HASH_BITS 10 1018#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1019#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1020#define SRC_T2_SZ SRC_ILT_SZ 1021#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1022 1023#define MAX_DMAE_C 8 1024 1025/* DMA memory not used in fastpath */ 1026struct bnx2x_slowpath { 1027 union { 1028 struct mac_configuration_cmd e1x; 1029 struct eth_classify_rules_ramrod_data e2; 1030 } mac_rdata; 1031 1032 1033 union { 1034 struct tstorm_eth_mac_filter_config e1x; 1035 struct eth_filter_rules_ramrod_data e2; 1036 } rx_mode_rdata; 1037 1038 union { 1039 struct mac_configuration_cmd e1; 1040 struct eth_multicast_rules_ramrod_data e2; 1041 } mcast_rdata; 1042 1043 struct eth_rss_update_ramrod_data rss_rdata; 1044 1045 /* Queue State related ramrods are always sent under rtnl_lock */ 1046 union { 1047 struct client_init_ramrod_data init_data; 1048 struct client_update_ramrod_data update_data; 1049 } q_rdata; 1050 1051 union { 1052 struct function_start_data func_start; 1053 /* pfc configuration for DCBX ramrod */ 1054 struct flow_control_configuration pfc_config; 1055 } func_rdata; 1056 1057 /* afex ramrod can not be a part of func_rdata union because these 1058 * events might arrive in parallel to other events from func_rdata. 1059 * Therefore, if they would have been defined in the same union, 1060 * data can get corrupted. 1061 */ 1062 struct afex_vif_list_ramrod_data func_afex_rdata; 1063 1064 /* used by dmae command executer */ 1065 struct dmae_command dmae[MAX_DMAE_C]; 1066 1067 u32 stats_comp; 1068 union mac_stats mac_stats; 1069 struct nig_stats nig_stats; 1070 struct host_port_stats port_stats; 1071 struct host_func_stats func_stats; 1072 1073 u32 wb_comp; 1074 u32 wb_data[4]; 1075 1076 union drv_info_to_mcp drv_info_to_mcp; 1077}; 1078 1079#define bnx2x_sp(bp, var) (&bp->slowpath->var) 1080#define bnx2x_sp_mapping(bp, var) \ 1081 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1082 1083 1084/* attn group wiring */ 1085#define MAX_DYNAMIC_ATTN_GRPS 8 1086 1087struct attn_route { 1088 u32 sig[5]; 1089}; 1090 1091struct iro { 1092 u32 base; 1093 u16 m1; 1094 u16 m2; 1095 u16 m3; 1096 u16 size; 1097}; 1098 1099struct hw_context { 1100 union cdu_context *vcxt; 1101 dma_addr_t cxt_mapping; 1102 size_t size; 1103}; 1104 1105/* forward */ 1106struct bnx2x_ilt; 1107 1108 1109enum bnx2x_recovery_state { 1110 BNX2X_RECOVERY_DONE, 1111 BNX2X_RECOVERY_INIT, 1112 BNX2X_RECOVERY_WAIT, 1113 BNX2X_RECOVERY_FAILED, 1114 BNX2X_RECOVERY_NIC_LOADING 1115}; 1116 1117/* 1118 * Event queue (EQ or event ring) MC hsi 1119 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1120 */ 1121#define NUM_EQ_PAGES 1 1122#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1123#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1124#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1125#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1126#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1127 1128/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1129#define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1130 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1131 1132/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1133#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1134 1135#define BNX2X_EQ_INDEX \ 1136 (&bp->def_status_blk->sp_sb.\ 1137 index_values[HC_SP_INDEX_EQ_CONS]) 1138 1139/* This is a data that will be used to create a link report message. 1140 * We will keep the data used for the last link report in order 1141 * to prevent reporting the same link parameters twice. 1142 */ 1143struct bnx2x_link_report_data { 1144 u16 line_speed; /* Effective line speed */ 1145 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1146}; 1147 1148enum { 1149 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1150 BNX2X_LINK_REPORT_LINK_DOWN, 1151 BNX2X_LINK_REPORT_RX_FC_ON, 1152 BNX2X_LINK_REPORT_TX_FC_ON, 1153}; 1154 1155enum { 1156 BNX2X_PORT_QUERY_IDX, 1157 BNX2X_PF_QUERY_IDX, 1158 BNX2X_FCOE_QUERY_IDX, 1159 BNX2X_FIRST_QUEUE_QUERY_IDX, 1160}; 1161 1162struct bnx2x_fw_stats_req { 1163 struct stats_query_header hdr; 1164 struct stats_query_entry query[FP_SB_MAX_E1x+ 1165 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1166}; 1167 1168struct bnx2x_fw_stats_data { 1169 struct stats_counter storm_counters; 1170 struct per_port_stats port; 1171 struct per_pf_stats pf; 1172 struct fcoe_statistics_params fcoe; 1173 struct per_queue_stats queue_stats[1]; 1174}; 1175 1176/* Public slow path states */ 1177enum { 1178 BNX2X_SP_RTNL_SETUP_TC, 1179 BNX2X_SP_RTNL_TX_TIMEOUT, 1180 BNX2X_SP_RTNL_AFEX_F_UPDATE, 1181 BNX2X_SP_RTNL_FAN_FAILURE, 1182}; 1183 1184 1185struct bnx2x_prev_path_list { 1186 u8 bus; 1187 u8 slot; 1188 u8 path; 1189 struct list_head list; 1190}; 1191 1192struct bnx2x_sp_objs { 1193 /* MACs object */ 1194 struct bnx2x_vlan_mac_obj mac_obj; 1195 1196 /* Queue State object */ 1197 struct bnx2x_queue_sp_obj q_obj; 1198}; 1199 1200struct bnx2x_fp_stats { 1201 struct tstorm_per_queue_stats old_tclient; 1202 struct ustorm_per_queue_stats old_uclient; 1203 struct xstorm_per_queue_stats old_xclient; 1204 struct bnx2x_eth_q_stats eth_q_stats; 1205 struct bnx2x_eth_q_stats_old eth_q_stats_old; 1206}; 1207 1208struct bnx2x { 1209 /* Fields used in the tx and intr/napi performance paths 1210 * are grouped together in the beginning of the structure 1211 */ 1212 struct bnx2x_fastpath *fp; 1213 struct bnx2x_sp_objs *sp_objs; 1214 struct bnx2x_fp_stats *fp_stats; 1215 struct bnx2x_fp_txdata *bnx2x_txq; 1216 void __iomem *regview; 1217 void __iomem *doorbells; 1218 u16 db_size; 1219 1220 u8 pf_num; /* absolute PF number */ 1221 u8 pfid; /* per-path PF number */ 1222 int base_fw_ndsb; /**/ 1223#define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1224#define BP_PORT(bp) (bp->pfid & 1) 1225#define BP_FUNC(bp) (bp->pfid) 1226#define BP_ABS_FUNC(bp) (bp->pf_num) 1227#define BP_VN(bp) ((bp)->pfid >> 1) 1228#define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1229#define BP_L_ID(bp) (BP_VN(bp) << 2) 1230#define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1231 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1232#define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1233 1234 struct net_device *dev; 1235 struct pci_dev *pdev; 1236 1237 const struct iro *iro_arr; 1238#define IRO (bp->iro_arr) 1239 1240 enum bnx2x_recovery_state recovery_state; 1241 int is_leader; 1242 struct msix_entry *msix_table; 1243 1244 int tx_ring_size; 1245 1246/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1247#define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1248#define ETH_MIN_PACKET_SIZE 60 1249#define ETH_MAX_PACKET_SIZE 1500 1250#define ETH_MAX_JUMBO_PACKET_SIZE 9600 1251/* TCP with Timestamp Option (32) + IPv6 (40) */ 1252#define ETH_MAX_TPA_HEADER_SIZE 72 1253 1254 /* Max supported alignment is 256 (8 shift) */ 1255#define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1256 1257 /* FW uses 2 Cache lines Alignment for start packet and size 1258 * 1259 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1260 * at the end of skb->data, to avoid wasting a full cache line. 1261 * This reduces memory use (skb->truesize). 1262 */ 1263#define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1264 1265#define BNX2X_FW_RX_ALIGN_END \ 1266 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1267 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1268 1269#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1270 1271 struct host_sp_status_block *def_status_blk; 1272#define DEF_SB_IGU_ID 16 1273#define DEF_SB_ID HC_SP_SB_ID 1274 __le16 def_idx; 1275 __le16 def_att_idx; 1276 u32 attn_state; 1277 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1278 1279 /* slow path ring */ 1280 struct eth_spe *spq; 1281 dma_addr_t spq_mapping; 1282 u16 spq_prod_idx; 1283 struct eth_spe *spq_prod_bd; 1284 struct eth_spe *spq_last_bd; 1285 __le16 *dsb_sp_prod; 1286 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1287 /* used to synchronize spq accesses */ 1288 spinlock_t spq_lock; 1289 1290 /* event queue */ 1291 union event_ring_elem *eq_ring; 1292 dma_addr_t eq_mapping; 1293 u16 eq_prod; 1294 u16 eq_cons; 1295 __le16 *eq_cons_sb; 1296 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1297 1298 1299 1300 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1301 u16 stats_pending; 1302 /* Counter for completed statistics ramrods */ 1303 u16 stats_comp; 1304 1305 /* End of fields used in the performance code paths */ 1306 1307 int panic; 1308 int msg_enable; 1309 1310 u32 flags; 1311#define PCIX_FLAG (1 << 0) 1312#define PCI_32BIT_FLAG (1 << 1) 1313#define ONE_PORT_FLAG (1 << 2) 1314#define NO_WOL_FLAG (1 << 3) 1315#define USING_DAC_FLAG (1 << 4) 1316#define USING_MSIX_FLAG (1 << 5) 1317#define USING_MSI_FLAG (1 << 6) 1318#define DISABLE_MSI_FLAG (1 << 7) 1319#define TPA_ENABLE_FLAG (1 << 8) 1320#define NO_MCP_FLAG (1 << 9) 1321 1322#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) 1323#define GRO_ENABLE_FLAG (1 << 10) 1324#define MF_FUNC_DIS (1 << 11) 1325#define OWN_CNIC_IRQ (1 << 12) 1326#define NO_ISCSI_OOO_FLAG (1 << 13) 1327#define NO_ISCSI_FLAG (1 << 14) 1328#define NO_FCOE_FLAG (1 << 15) 1329#define BC_SUPPORTS_PFC_STATS (1 << 17) 1330#define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 1331#define USING_SINGLE_MSIX_FLAG (1 << 20) 1332#define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 1333 1334#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1335#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1336#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1337 1338 u8 cnic_support; 1339 bool cnic_enabled; 1340 bool cnic_loaded; 1341 1342 /* Flag that indicates that we can start looking for FCoE L2 queue 1343 * completions in the default status block. 1344 */ 1345 bool fcoe_init; 1346 1347 int pm_cap; 1348 int mrrs; 1349 1350 struct delayed_work sp_task; 1351 struct delayed_work sp_rtnl_task; 1352 1353 struct delayed_work period_task; 1354 struct timer_list timer; 1355 int current_interval; 1356 1357 u16 fw_seq; 1358 u16 fw_drv_pulse_wr_seq; 1359 u32 func_stx; 1360 1361 struct link_params link_params; 1362 struct link_vars link_vars; 1363 u32 link_cnt; 1364 struct bnx2x_link_report_data last_reported_link; 1365 1366 struct mdio_if_info mdio; 1367 1368 struct bnx2x_common common; 1369 struct bnx2x_port port; 1370 1371 struct cmng_init cmng; 1372 1373 u32 mf_config[E1HVN_MAX]; 1374 u32 mf_ext_config; 1375 u32 path_has_ovlan; /* E3 */ 1376 u16 mf_ov; 1377 u8 mf_mode; 1378#define IS_MF(bp) (bp->mf_mode != 0) 1379#define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1380#define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1381#define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1382 1383 u8 wol; 1384 1385 int rx_ring_size; 1386 1387 u16 tx_quick_cons_trip_int; 1388 u16 tx_quick_cons_trip; 1389 u16 tx_ticks_int; 1390 u16 tx_ticks; 1391 1392 u16 rx_quick_cons_trip_int; 1393 u16 rx_quick_cons_trip; 1394 u16 rx_ticks_int; 1395 u16 rx_ticks; 1396/* Maximal coalescing timeout in us */ 1397#define BNX2X_MAX_COALESCE_TOUT (0xf0*12) 1398 1399 u32 lin_cnt; 1400 1401 u16 state; 1402#define BNX2X_STATE_CLOSED 0 1403#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1404#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1405#define BNX2X_STATE_OPEN 0x3000 1406#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1407#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1408 1409#define BNX2X_STATE_DIAG 0xe000 1410#define BNX2X_STATE_ERROR 0xf000 1411 1412#define BNX2X_MAX_PRIORITY 8 1413#define BNX2X_MAX_ENTRIES_PER_PRI 16 1414#define BNX2X_MAX_COS 3 1415#define BNX2X_MAX_TX_COS 2 1416 int num_queues; 1417 uint num_ethernet_queues; 1418 uint num_cnic_queues; 1419 int num_napi_queues; 1420 int disable_tpa; 1421 1422 u32 rx_mode; 1423#define BNX2X_RX_MODE_NONE 0 1424#define BNX2X_RX_MODE_NORMAL 1 1425#define BNX2X_RX_MODE_ALLMULTI 2 1426#define BNX2X_RX_MODE_PROMISC 3 1427#define BNX2X_MAX_MULTICAST 64 1428 1429 u8 igu_dsb_id; 1430 u8 igu_base_sb; 1431 u8 igu_sb_cnt; 1432 u8 min_msix_vec_cnt; 1433 1434 dma_addr_t def_status_blk_mapping; 1435 1436 struct bnx2x_slowpath *slowpath; 1437 dma_addr_t slowpath_mapping; 1438 1439 /* Total number of FW statistics requests */ 1440 u8 fw_stats_num; 1441 1442 /* 1443 * This is a memory buffer that will contain both statistics 1444 * ramrod request and data. 1445 */ 1446 void *fw_stats; 1447 dma_addr_t fw_stats_mapping; 1448 1449 /* 1450 * FW statistics request shortcut (points at the 1451 * beginning of fw_stats buffer). 1452 */ 1453 struct bnx2x_fw_stats_req *fw_stats_req; 1454 dma_addr_t fw_stats_req_mapping; 1455 int fw_stats_req_sz; 1456 1457 /* 1458 * FW statistics data shortcut (points at the beginning of 1459 * fw_stats buffer + fw_stats_req_sz). 1460 */ 1461 struct bnx2x_fw_stats_data *fw_stats_data; 1462 dma_addr_t fw_stats_data_mapping; 1463 int fw_stats_data_sz; 1464 1465 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1466 * context size we need 8 ILT entries. 1467 */ 1468#define ILT_MAX_L2_LINES 8 1469 struct hw_context context[ILT_MAX_L2_LINES]; 1470 1471 struct bnx2x_ilt *ilt; 1472#define BP_ILT(bp) ((bp)->ilt) 1473#define ILT_MAX_LINES 256 1474/* 1475 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1476 * to CNIC. 1477 */ 1478#define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1479 1480/* 1481 * Maximum CID count that might be required by the bnx2x: 1482 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1483 */ 1484#define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1485 + 2 * CNIC_SUPPORT(bp)) 1486#define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1487 + 2 * CNIC_SUPPORT(bp)) 1488#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1489 ILT_PAGE_CIDS)) 1490 1491 int qm_cid_count; 1492 1493 int dropless_fc; 1494 1495 void *t2; 1496 dma_addr_t t2_mapping; 1497 struct cnic_ops __rcu *cnic_ops; 1498 void *cnic_data; 1499 u32 cnic_tag; 1500 struct cnic_eth_dev cnic_eth_dev; 1501 union host_hc_status_block cnic_sb; 1502 dma_addr_t cnic_sb_mapping; 1503 struct eth_spe *cnic_kwq; 1504 struct eth_spe *cnic_kwq_prod; 1505 struct eth_spe *cnic_kwq_cons; 1506 struct eth_spe *cnic_kwq_last; 1507 u16 cnic_kwq_pending; 1508 u16 cnic_spq_pending; 1509 u8 fip_mac[ETH_ALEN]; 1510 struct mutex cnic_mutex; 1511 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1512 1513 /* Start index of the "special" (CNIC related) L2 cleints */ 1514 u8 cnic_base_cl_id; 1515 1516 int dmae_ready; 1517 /* used to synchronize dmae accesses */ 1518 spinlock_t dmae_lock; 1519 1520 /* used to protect the FW mail box */ 1521 struct mutex fw_mb_mutex; 1522 1523 /* used to synchronize stats collecting */ 1524 int stats_state; 1525 1526 /* used for synchronization of concurrent threads statistics handling */ 1527 spinlock_t stats_lock; 1528 1529 /* used by dmae command loader */ 1530 struct dmae_command stats_dmae; 1531 int executer_idx; 1532 1533 u16 stats_counter; 1534 struct bnx2x_eth_stats eth_stats; 1535 struct host_func_stats func_stats; 1536 struct bnx2x_eth_stats_old eth_stats_old; 1537 struct bnx2x_net_stats_old net_stats_old; 1538 struct bnx2x_fw_port_stats_old fw_stats_old; 1539 bool stats_init; 1540 1541 struct z_stream_s *strm; 1542 void *gunzip_buf; 1543 dma_addr_t gunzip_mapping; 1544 int gunzip_outlen; 1545#define FW_BUF_SIZE 0x8000 1546#define GUNZIP_BUF(bp) (bp->gunzip_buf) 1547#define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1548#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1549 1550 struct raw_op *init_ops; 1551 /* Init blocks offsets inside init_ops */ 1552 u16 *init_ops_offsets; 1553 /* Data blob - has 32 bit granularity */ 1554 u32 *init_data; 1555 u32 init_mode_flags; 1556#define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1557 /* Zipped PRAM blobs - raw data */ 1558 const u8 *tsem_int_table_data; 1559 const u8 *tsem_pram_data; 1560 const u8 *usem_int_table_data; 1561 const u8 *usem_pram_data; 1562 const u8 *xsem_int_table_data; 1563 const u8 *xsem_pram_data; 1564 const u8 *csem_int_table_data; 1565 const u8 *csem_pram_data; 1566#define INIT_OPS(bp) (bp->init_ops) 1567#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1568#define INIT_DATA(bp) (bp->init_data) 1569#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1570#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1571#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1572#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1573#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1574#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1575#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1576#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1577 1578#define PHY_FW_VER_LEN 20 1579 char fw_ver[32]; 1580 const struct firmware *firmware; 1581 1582 /* DCB support on/off */ 1583 u16 dcb_state; 1584#define BNX2X_DCB_STATE_OFF 0 1585#define BNX2X_DCB_STATE_ON 1 1586 1587 /* DCBX engine mode */ 1588 int dcbx_enabled; 1589#define BNX2X_DCBX_ENABLED_OFF 0 1590#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1591#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1592#define BNX2X_DCBX_ENABLED_INVALID (-1) 1593 1594 bool dcbx_mode_uset; 1595 1596 struct bnx2x_config_dcbx_params dcbx_config_params; 1597 struct bnx2x_dcbx_port_params dcbx_port_params; 1598 int dcb_version; 1599 1600 /* CAM credit pools */ 1601 struct bnx2x_credit_pool_obj macs_pool; 1602 1603 /* RX_MODE object */ 1604 struct bnx2x_rx_mode_obj rx_mode_obj; 1605 1606 /* MCAST object */ 1607 struct bnx2x_mcast_obj mcast_obj; 1608 1609 /* RSS configuration object */ 1610 struct bnx2x_rss_config_obj rss_conf_obj; 1611 1612 /* Function State controlling object */ 1613 struct bnx2x_func_sp_obj func_obj; 1614 1615 unsigned long sp_state; 1616 1617 /* operation indication for the sp_rtnl task */ 1618 unsigned long sp_rtnl_state; 1619 1620 /* DCBX Negotation results */ 1621 struct dcbx_features dcbx_local_feat; 1622 u32 dcbx_error; 1623 1624#ifdef BCM_DCBNL 1625 struct dcbx_features dcbx_remote_feat; 1626 u32 dcbx_remote_flags; 1627#endif 1628 /* AFEX: store default vlan used */ 1629 int afex_def_vlan_tag; 1630 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1631 u32 pending_max; 1632 1633 /* multiple tx classes of service */ 1634 u8 max_cos; 1635 1636 /* priority to cos mapping */ 1637 u8 prio_to_cos[8]; 1638}; 1639 1640/* Tx queues may be less or equal to Rx queues */ 1641extern int num_queues; 1642#define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1643#define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 1644#define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 1645 (bp)->num_cnic_queues) 1646#define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1647 1648#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1649 1650#define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1651/* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1652 1653#define RSS_IPV4_CAP_MASK \ 1654 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1655 1656#define RSS_IPV4_TCP_CAP_MASK \ 1657 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1658 1659#define RSS_IPV6_CAP_MASK \ 1660 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1661 1662#define RSS_IPV6_TCP_CAP_MASK \ 1663 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1664 1665/* func init flags */ 1666#define FUNC_FLG_RSS 0x0001 1667#define FUNC_FLG_STATS 0x0002 1668/* removed FUNC_FLG_UNMATCHED 0x0004 */ 1669#define FUNC_FLG_TPA 0x0008 1670#define FUNC_FLG_SPQ 0x0010 1671#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1672 1673 1674struct bnx2x_func_init_params { 1675 /* dma */ 1676 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1677 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1678 1679 u16 func_flgs; 1680 u16 func_id; /* abs fid */ 1681 u16 pf_id; 1682 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1683}; 1684 1685#define for_each_cnic_queue(bp, var) \ 1686 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1687 (var)++) \ 1688 if (skip_queue(bp, var)) \ 1689 continue; \ 1690 else 1691 1692#define for_each_eth_queue(bp, var) \ 1693 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1694 1695#define for_each_nondefault_eth_queue(bp, var) \ 1696 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1697 1698#define for_each_queue(bp, var) \ 1699 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1700 if (skip_queue(bp, var)) \ 1701 continue; \ 1702 else 1703 1704/* Skip forwarding FP */ 1705#define for_each_valid_rx_queue(bp, var) \ 1706 for ((var) = 0; \ 1707 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1708 BNX2X_NUM_ETH_QUEUES(bp)); \ 1709 (var)++) \ 1710 if (skip_rx_queue(bp, var)) \ 1711 continue; \ 1712 else 1713 1714#define for_each_rx_queue_cnic(bp, var) \ 1715 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1716 (var)++) \ 1717 if (skip_rx_queue(bp, var)) \ 1718 continue; \ 1719 else 1720 1721#define for_each_rx_queue(bp, var) \ 1722 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1723 if (skip_rx_queue(bp, var)) \ 1724 continue; \ 1725 else 1726 1727/* Skip OOO FP */ 1728#define for_each_valid_tx_queue(bp, var) \ 1729 for ((var) = 0; \ 1730 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1731 BNX2X_NUM_ETH_QUEUES(bp)); \ 1732 (var)++) \ 1733 if (skip_tx_queue(bp, var)) \ 1734 continue; \ 1735 else 1736 1737#define for_each_tx_queue_cnic(bp, var) \ 1738 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1739 (var)++) \ 1740 if (skip_tx_queue(bp, var)) \ 1741 continue; \ 1742 else 1743 1744#define for_each_tx_queue(bp, var) \ 1745 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1746 if (skip_tx_queue(bp, var)) \ 1747 continue; \ 1748 else 1749 1750#define for_each_nondefault_queue(bp, var) \ 1751 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1752 if (skip_queue(bp, var)) \ 1753 continue; \ 1754 else 1755 1756#define for_each_cos_in_tx_queue(fp, var) \ 1757 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1758 1759/* skip rx queue 1760 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1761 */ 1762#define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1763 1764/* skip tx queue 1765 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1766 */ 1767#define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1768 1769#define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1770 1771 1772 1773 1774/** 1775 * bnx2x_set_mac_one - configure a single MAC address 1776 * 1777 * @bp: driver handle 1778 * @mac: MAC to configure 1779 * @obj: MAC object handle 1780 * @set: if 'true' add a new MAC, otherwise - delete 1781 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 1782 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 1783 * 1784 * Configures one MAC according to provided parameters or continues the 1785 * execution of previously scheduled commands if RAMROD_CONT is set in 1786 * ramrod_flags. 1787 * 1788 * Returns zero if operation has successfully completed, a positive value if the 1789 * operation has been successfully scheduled and a negative - if a requested 1790 * operations has failed. 1791 */ 1792int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 1793 struct bnx2x_vlan_mac_obj *obj, bool set, 1794 int mac_type, unsigned long *ramrod_flags); 1795/** 1796 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 1797 * 1798 * @bp: driver handle 1799 * @mac_obj: MAC object handle 1800 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 1801 * @wait_for_comp: if 'true' block until completion 1802 * 1803 * Deletes all MACs of the specific type (e.g. ETH, UC list). 1804 * 1805 * Returns zero if operation has successfully completed, a positive value if the 1806 * operation has been successfully scheduled and a negative - if a requested 1807 * operations has failed. 1808 */ 1809int bnx2x_del_all_macs(struct bnx2x *bp, 1810 struct bnx2x_vlan_mac_obj *mac_obj, 1811 int mac_type, bool wait_for_comp); 1812 1813/* Init Function API */ 1814void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 1815int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 1816int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1817int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 1818int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1819void bnx2x_read_mf_cfg(struct bnx2x *bp); 1820 1821 1822/* dmae */ 1823void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 1824void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 1825 u32 len32); 1826void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 1827u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 1828u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 1829u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 1830 bool with_comp, u8 comp_type); 1831 1832 1833void bnx2x_calc_fc_adv(struct bnx2x *bp); 1834int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 1835 u32 data_hi, u32 data_lo, int cmd_type); 1836void bnx2x_update_coalesce(struct bnx2x *bp); 1837int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 1838 1839static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 1840 int wait) 1841{ 1842 u32 val; 1843 1844 do { 1845 val = REG_RD(bp, reg); 1846 if (val == expected) 1847 break; 1848 ms -= wait; 1849 msleep(wait); 1850 1851 } while (ms > 0); 1852 1853 return val; 1854} 1855 1856#define BNX2X_ILT_ZALLOC(x, y, size) \ 1857 do { \ 1858 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 1859 if (x) \ 1860 memset(x, 0, size); \ 1861 } while (0) 1862 1863#define BNX2X_ILT_FREE(x, y, size) \ 1864 do { \ 1865 if (x) { \ 1866 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 1867 x = NULL; \ 1868 y = 0; \ 1869 } \ 1870 } while (0) 1871 1872#define ILOG2(x) (ilog2((x))) 1873 1874#define ILT_NUM_PAGE_ENTRIES (3072) 1875/* In 57710/11 we use whole table since we have 8 func 1876 * In 57712 we have only 4 func, but use same size per func, then only half of 1877 * the table in use 1878 */ 1879#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 1880 1881#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 1882/* 1883 * the phys address is shifted right 12 bits and has an added 1884 * 1=valid bit added to the 53rd bit 1885 * then since this is a wide register(TM) 1886 * we split it into two 32 bit writes 1887 */ 1888#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 1889#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 1890 1891/* load/unload mode */ 1892#define LOAD_NORMAL 0 1893#define LOAD_OPEN 1 1894#define LOAD_DIAG 2 1895#define LOAD_LOOPBACK_EXT 3 1896#define UNLOAD_NORMAL 0 1897#define UNLOAD_CLOSE 1 1898#define UNLOAD_RECOVERY 2 1899 1900 1901/* DMAE command defines */ 1902#define DMAE_TIMEOUT -1 1903#define DMAE_PCI_ERROR -2 /* E2 and onward */ 1904#define DMAE_NOT_RDY -3 1905#define DMAE_PCI_ERR_FLAG 0x80000000 1906 1907#define DMAE_SRC_PCI 0 1908#define DMAE_SRC_GRC 1 1909 1910#define DMAE_DST_NONE 0 1911#define DMAE_DST_PCI 1 1912#define DMAE_DST_GRC 2 1913 1914#define DMAE_COMP_PCI 0 1915#define DMAE_COMP_GRC 1 1916 1917/* E2 and onward - PCI error handling in the completion */ 1918 1919#define DMAE_COMP_REGULAR 0 1920#define DMAE_COM_SET_ERR 1 1921 1922#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 1923 DMAE_COMMAND_SRC_SHIFT) 1924#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 1925 DMAE_COMMAND_SRC_SHIFT) 1926 1927#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 1928 DMAE_COMMAND_DST_SHIFT) 1929#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 1930 DMAE_COMMAND_DST_SHIFT) 1931 1932#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 1933 DMAE_COMMAND_C_DST_SHIFT) 1934#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 1935 DMAE_COMMAND_C_DST_SHIFT) 1936 1937#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 1938 1939#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 1940#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 1941#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 1942#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 1943 1944#define DMAE_CMD_PORT_0 0 1945#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 1946 1947#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 1948#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 1949#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 1950 1951#define DMAE_SRC_PF 0 1952#define DMAE_SRC_VF 1 1953 1954#define DMAE_DST_PF 0 1955#define DMAE_DST_VF 1 1956 1957#define DMAE_C_SRC 0 1958#define DMAE_C_DST 1 1959 1960#define DMAE_LEN32_RD_MAX 0x80 1961#define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 1962 1963#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 1964 indicates eror */ 1965 1966#define MAX_DMAE_C_PER_PORT 8 1967#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1968 BP_VN(bp)) 1969#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1970 E1HVN_MAX) 1971 1972/* PCIE link and speed */ 1973#define PCICFG_LINK_WIDTH 0x1f00000 1974#define PCICFG_LINK_WIDTH_SHIFT 20 1975#define PCICFG_LINK_SPEED 0xf0000 1976#define PCICFG_LINK_SPEED_SHIFT 16 1977 1978#define BNX2X_NUM_TESTS_SF 7 1979#define BNX2X_NUM_TESTS_MF 3 1980#define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 1981 BNX2X_NUM_TESTS_SF) 1982 1983#define BNX2X_PHY_LOOPBACK 0 1984#define BNX2X_MAC_LOOPBACK 1 1985#define BNX2X_EXT_LOOPBACK 2 1986#define BNX2X_PHY_LOOPBACK_FAILED 1 1987#define BNX2X_MAC_LOOPBACK_FAILED 2 1988#define BNX2X_EXT_LOOPBACK_FAILED 3 1989#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 1990 BNX2X_PHY_LOOPBACK_FAILED) 1991 1992 1993#define STROM_ASSERT_ARRAY_SIZE 50 1994 1995 1996/* must be used on a CID before placing it on a HW ring */ 1997#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 1998 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 1999 (x)) 2000 2001#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2002#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2003 2004 2005#define BNX2X_BTR 4 2006#define MAX_SPQ_PENDING 8 2007 2008/* CMNG constants, as derived from system spec calculations */ 2009/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2010#define DEF_MIN_RATE 100 2011/* resolution of the rate shaping timer - 400 usec */ 2012#define RS_PERIODIC_TIMEOUT_USEC 400 2013/* number of bytes in single QM arbitration cycle - 2014 * coefficient for calculating the fairness timer */ 2015#define QM_ARB_BYTES 160000 2016/* resolution of Min algorithm 1:100 */ 2017#define MIN_RES 100 2018/* how many bytes above threshold for the minimal credit of Min algorithm*/ 2019#define MIN_ABOVE_THRESH 32768 2020/* Fairness algorithm integration time coefficient - 2021 * for calculating the actual Tfair */ 2022#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2023/* Memory of fairness algorithm . 2 cycles */ 2024#define FAIR_MEM 2 2025 2026 2027#define ATTN_NIG_FOR_FUNC (1L << 8) 2028#define ATTN_SW_TIMER_4_FUNC (1L << 9) 2029#define GPIO_2_FUNC (1L << 10) 2030#define GPIO_3_FUNC (1L << 11) 2031#define GPIO_4_FUNC (1L << 12) 2032#define ATTN_GENERAL_ATTN_1 (1L << 13) 2033#define ATTN_GENERAL_ATTN_2 (1L << 14) 2034#define ATTN_GENERAL_ATTN_3 (1L << 15) 2035#define ATTN_GENERAL_ATTN_4 (1L << 13) 2036#define ATTN_GENERAL_ATTN_5 (1L << 14) 2037#define ATTN_GENERAL_ATTN_6 (1L << 15) 2038 2039#define ATTN_HARD_WIRED_MASK 0xff00 2040#define ATTENTION_ID 4 2041 2042 2043/* stuff added to make the code fit 80Col */ 2044 2045#define BNX2X_PMF_LINK_ASSERT \ 2046 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2047 2048#define BNX2X_MC_ASSERT_BITS \ 2049 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2050 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2051 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2052 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2053 2054#define BNX2X_MCP_ASSERT \ 2055 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2056 2057#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2058#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2059 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2060 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2061 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2062 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2063 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2064 2065#define HW_INTERRUT_ASSERT_SET_0 \ 2066 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2067 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2068 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2069 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2070#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2071 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2072 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2073 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2074 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2075 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2076 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2077#define HW_INTERRUT_ASSERT_SET_1 \ 2078 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2079 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2080 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2081 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2082 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2083 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2084 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2085 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2086 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2087 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2088 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2089#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2090 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2091 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2092 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2093 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2094 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2095 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2096 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2097 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2098 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2099 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2100 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2101 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2102 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2103 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2104 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2105#define HW_INTERRUT_ASSERT_SET_2 \ 2106 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2107 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2108 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2109 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2110 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2111#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2112 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2113 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2114 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2115 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2116 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2117 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2118 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2119 2120#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2121 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2122 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2123 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2124 2125#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2126 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2127 2128#define MULTI_MASK 0x7f 2129 2130 2131#define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2132#define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2133#define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2134#define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2135 2136#define DEF_USB_IGU_INDEX_OFF \ 2137 offsetof(struct cstorm_def_status_block_u, igu_index) 2138#define DEF_CSB_IGU_INDEX_OFF \ 2139 offsetof(struct cstorm_def_status_block_c, igu_index) 2140#define DEF_XSB_IGU_INDEX_OFF \ 2141 offsetof(struct xstorm_def_status_block, igu_index) 2142#define DEF_TSB_IGU_INDEX_OFF \ 2143 offsetof(struct tstorm_def_status_block, igu_index) 2144 2145#define DEF_USB_SEGMENT_OFF \ 2146 offsetof(struct cstorm_def_status_block_u, segment) 2147#define DEF_CSB_SEGMENT_OFF \ 2148 offsetof(struct cstorm_def_status_block_c, segment) 2149#define DEF_XSB_SEGMENT_OFF \ 2150 offsetof(struct xstorm_def_status_block, segment) 2151#define DEF_TSB_SEGMENT_OFF \ 2152 offsetof(struct tstorm_def_status_block, segment) 2153 2154#define BNX2X_SP_DSB_INDEX \ 2155 (&bp->def_status_blk->sp_sb.\ 2156 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2157 2158#define SET_FLAG(value, mask, flag) \ 2159 do {\ 2160 (value) &= ~(mask);\ 2161 (value) |= ((flag) << (mask##_SHIFT));\ 2162 } while (0) 2163 2164#define GET_FLAG(value, mask) \ 2165 (((value) & (mask)) >> (mask##_SHIFT)) 2166 2167#define GET_FIELD(value, fname) \ 2168 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2169 2170#define CAM_IS_INVALID(x) \ 2171 (GET_FLAG(x.flags, \ 2172 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2173 (T_ETH_MAC_COMMAND_INVALIDATE)) 2174 2175/* Number of u32 elements in MC hash array */ 2176#define MC_HASH_SIZE 8 2177#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2178 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2179 2180 2181#ifndef PXP2_REG_PXP2_INT_STS 2182#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2183#endif 2184 2185#ifndef ETH_MAX_RX_CLIENTS_E2 2186#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2187#endif 2188 2189#define BNX2X_VPD_LEN 128 2190#define VENDOR_ID_LEN 4 2191 2192/* Congestion management fairness mode */ 2193#define CMNG_FNS_NONE 0 2194#define CMNG_FNS_MINMAX 1 2195 2196#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2197#define HC_SEG_ACCESS_ATTN 4 2198#define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2199 2200static const u32 dmae_reg_go_c[] = { 2201 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2202 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2203 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2204 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2205}; 2206 2207void bnx2x_set_ethtool_ops(struct net_device *netdev); 2208void bnx2x_notify_link_changed(struct bnx2x *bp); 2209 2210 2211#define BNX2X_MF_SD_PROTOCOL(bp) \ 2212 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2213 2214#define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 2215 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2216 2217#define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 2218 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 2219 2220#define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 2221#define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 2222 2223#define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \ 2224 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2225 2226#define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp)) 2227#define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \ 2228 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 2229 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2230 2231enum { 2232 SWITCH_UPDATE, 2233 AFEX_UPDATE, 2234}; 2235 2236#define NUM_MACS 8 2237 2238#endif /* bnx2x.h */ 2239