bnx2x.h revision 65565884fba67d9254f32d239b0fb6c38fae88aa
1/* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14#ifndef BNX2X_H 15#define BNX2X_H 16#include <linux/netdevice.h> 17#include <linux/dma-mapping.h> 18#include <linux/types.h> 19 20/* compilation time flags */ 21 22/* define this to make the driver freeze on error to allow getting debug info 23 * (you will need to reboot afterwards) */ 24/* #define BNX2X_STOP_ON_ERROR */ 25 26#define DRV_MODULE_VERSION "1.72.50-0" 27#define DRV_MODULE_RELDATE "2012/04/23" 28#define BNX2X_BC_VER 0x040200 29 30#if defined(CONFIG_DCB) 31#define BCM_DCBNL 32#endif 33 34 35#include "bnx2x_hsi.h" 36 37#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) 38#define BCM_CNIC 1 39#include "../cnic_if.h" 40#endif 41 42#ifdef BCM_CNIC 43#define BNX2X_MIN_MSIX_VEC_CNT 3 44#define BNX2X_MSIX_VEC_FP_START 2 45#else 46#define BNX2X_MIN_MSIX_VEC_CNT 2 47#define BNX2X_MSIX_VEC_FP_START 1 48#endif 49 50#include <linux/mdio.h> 51 52#include "bnx2x_reg.h" 53#include "bnx2x_fw_defs.h" 54#include "bnx2x_hsi.h" 55#include "bnx2x_link.h" 56#include "bnx2x_sp.h" 57#include "bnx2x_dcb.h" 58#include "bnx2x_stats.h" 59 60/* error/debug prints */ 61 62#define DRV_MODULE_NAME "bnx2x" 63 64/* for messages that are currently off */ 65#define BNX2X_MSG_OFF 0x0 66#define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 67#define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 68#define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 69#define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 70#define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 71#define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 72#define BNX2X_MSG_IOV 0x0800000 73#define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 74#define BNX2X_MSG_ETHTOOL 0x4000000 75#define BNX2X_MSG_DCB 0x8000000 76 77/* regular debug print */ 78#define DP(__mask, fmt, ...) \ 79do { \ 80 if (unlikely(bp->msg_enable & (__mask))) \ 81 pr_notice("[%s:%d(%s)]" fmt, \ 82 __func__, __LINE__, \ 83 bp->dev ? (bp->dev->name) : "?", \ 84 ##__VA_ARGS__); \ 85} while (0) 86 87#define DP_CONT(__mask, fmt, ...) \ 88do { \ 89 if (unlikely(bp->msg_enable & (__mask))) \ 90 pr_cont(fmt, ##__VA_ARGS__); \ 91} while (0) 92 93/* errors debug print */ 94#define BNX2X_DBG_ERR(fmt, ...) \ 95do { \ 96 if (unlikely(netif_msg_probe(bp))) \ 97 pr_err("[%s:%d(%s)]" fmt, \ 98 __func__, __LINE__, \ 99 bp->dev ? (bp->dev->name) : "?", \ 100 ##__VA_ARGS__); \ 101} while (0) 102 103/* for errors (never masked) */ 104#define BNX2X_ERR(fmt, ...) \ 105do { \ 106 pr_err("[%s:%d(%s)]" fmt, \ 107 __func__, __LINE__, \ 108 bp->dev ? (bp->dev->name) : "?", \ 109 ##__VA_ARGS__); \ 110} while (0) 111 112#define BNX2X_ERROR(fmt, ...) \ 113 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 114 115 116/* before we have a dev->name use dev_info() */ 117#define BNX2X_DEV_INFO(fmt, ...) \ 118do { \ 119 if (unlikely(netif_msg_probe(bp))) \ 120 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 121} while (0) 122 123#ifdef BNX2X_STOP_ON_ERROR 124void bnx2x_int_disable(struct bnx2x *bp); 125#define bnx2x_panic() \ 126do { \ 127 bp->panic = 1; \ 128 BNX2X_ERR("driver assert\n"); \ 129 bnx2x_int_disable(bp); \ 130 bnx2x_panic_dump(bp); \ 131} while (0) 132#else 133#define bnx2x_panic() \ 134do { \ 135 bp->panic = 1; \ 136 BNX2X_ERR("driver assert\n"); \ 137 bnx2x_panic_dump(bp); \ 138} while (0) 139#endif 140 141#define bnx2x_mc_addr(ha) ((ha)->addr) 142#define bnx2x_uc_addr(ha) ((ha)->addr) 143 144#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) 145#define U64_HI(x) (u32)(((u64)(x)) >> 32) 146#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 147 148 149#define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 150 151#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 152#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 153#define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 154 155#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 156#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 157#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 158 159#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 160#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 161 162#define REG_RD_DMAE(bp, offset, valp, len32) \ 163 do { \ 164 bnx2x_read_dmae(bp, offset, len32);\ 165 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 166 } while (0) 167 168#define REG_WR_DMAE(bp, offset, valp, len32) \ 169 do { \ 170 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 171 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 172 offset, len32); \ 173 } while (0) 174 175#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 176 REG_WR_DMAE(bp, offset, valp, len32) 177 178#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 179 do { \ 180 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 181 bnx2x_write_big_buf_wb(bp, addr, len32); \ 182 } while (0) 183 184#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 185 offsetof(struct shmem_region, field)) 186#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 187#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 188 189#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 190 offsetof(struct shmem2_region, field)) 191#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 192#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 193#define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 194 offsetof(struct mf_cfg, field)) 195#define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 196 offsetof(struct mf2_cfg, field)) 197 198#define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 199#define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 200 MF_CFG_ADDR(bp, field), (val)) 201#define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 202 203#define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 204 (SHMEM2_RD((bp), size) > \ 205 offsetof(struct shmem2_region, field))) 206 207#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 208#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 209 210/* SP SB indices */ 211 212/* General SP events - stats query, cfc delete, etc */ 213#define HC_SP_INDEX_ETH_DEF_CONS 3 214 215/* EQ completions */ 216#define HC_SP_INDEX_EQ_CONS 7 217 218/* FCoE L2 connection completions */ 219#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 220#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 221/* iSCSI L2 */ 222#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 223#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 224 225/* Special clients parameters */ 226 227/* SB indices */ 228/* FCoE L2 */ 229#define BNX2X_FCOE_L2_RX_INDEX \ 230 (&bp->def_status_blk->sp_sb.\ 231 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 232 233#define BNX2X_FCOE_L2_TX_INDEX \ 234 (&bp->def_status_blk->sp_sb.\ 235 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 236 237/** 238 * CIDs and CLIDs: 239 * CLIDs below is a CLID for func 0, then the CLID for other 240 * functions will be calculated by the formula: 241 * 242 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 243 * 244 */ 245enum { 246 BNX2X_ISCSI_ETH_CL_ID_IDX, 247 BNX2X_FCOE_ETH_CL_ID_IDX, 248 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 249}; 250 251#define BNX2X_CNIC_START_ETH_CID 48 252enum { 253 /* iSCSI L2 */ 254 BNX2X_ISCSI_ETH_CID = BNX2X_CNIC_START_ETH_CID, 255 /* FCoE L2 */ 256 BNX2X_FCOE_ETH_CID, 257}; 258 259/** Additional rings budgeting */ 260#ifdef BCM_CNIC 261#define CNIC_PRESENT 1 262#define FCOE_PRESENT 1 263#else 264#define CNIC_PRESENT 0 265#define FCOE_PRESENT 0 266#endif /* BCM_CNIC */ 267#define NON_ETH_CONTEXT_USE (FCOE_PRESENT) 268 269#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 270 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 271 272#define SM_RX_ID 0 273#define SM_TX_ID 1 274 275/* defines for multiple tx priority indices */ 276#define FIRST_TX_ONLY_COS_INDEX 1 277#define FIRST_TX_COS_INDEX 0 278 279#define MAX_TXQS_PER_COS FP_SB_MAX_E1x 280 281/* rules for calculating the cids of tx-only connections */ 282#define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 283#define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 284 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 285 286/* fp index inside class of service range */ 287#define FP_COS_TO_TXQ(fp, cos, bp) \ 288 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 289 290/* Indexes for transmission queues array: 291 * txdata for RSS i CoS j is at location i + (j * num of RSS) 292 * txdata for FCoE (if exist) is at location max cos * num of RSS 293 * txdata for FWD (if exist) is one location after FCoE 294 * txdata for OOO (if exist) is one location after FWD 295 */ 296enum { 297 FCOE_TXQ_IDX_OFFSET, 298 FWD_TXQ_IDX_OFFSET, 299 OOO_TXQ_IDX_OFFSET, 300}; 301#define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 302#ifdef BCM_CNIC 303#define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 304#endif 305 306/* fast path */ 307/* 308 * This driver uses new build_skb() API : 309 * RX ring buffer contains pointer to kmalloc() data only, 310 * skb are built only after Hardware filled the frame. 311 */ 312struct sw_rx_bd { 313 u8 *data; 314 DEFINE_DMA_UNMAP_ADDR(mapping); 315}; 316 317struct sw_tx_bd { 318 struct sk_buff *skb; 319 u16 first_bd; 320 u8 flags; 321/* Set on the first BD descriptor when there is a split BD */ 322#define BNX2X_TSO_SPLIT_BD (1<<0) 323}; 324 325struct sw_rx_page { 326 struct page *page; 327 DEFINE_DMA_UNMAP_ADDR(mapping); 328}; 329 330union db_prod { 331 struct doorbell_set_prod data; 332 u32 raw; 333}; 334 335/* dropless fc FW/HW related params */ 336#define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 337#define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 338 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 339 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 340#define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 341#define FW_PREFETCH_CNT 16 342#define DROPLESS_FC_HEADROOM 100 343 344/* MC hsi */ 345#define BCM_PAGE_SHIFT 12 346#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 347#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 348#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 349 350#define PAGES_PER_SGE_SHIFT 0 351#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 352#define SGE_PAGE_SIZE PAGE_SIZE 353#define SGE_PAGE_SHIFT PAGE_SHIFT 354#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 355 356/* SGE ring related macros */ 357#define NUM_RX_SGE_PAGES 2 358#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 359#define NEXT_PAGE_SGE_DESC_CNT 2 360#define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 361/* RX_SGE_CNT is promised to be a power of 2 */ 362#define RX_SGE_MASK (RX_SGE_CNT - 1) 363#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 364#define MAX_RX_SGE (NUM_RX_SGE - 1) 365#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 366 (MAX_RX_SGE_CNT - 1)) ? \ 367 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 368 (x) + 1) 369#define RX_SGE(x) ((x) & MAX_RX_SGE) 370 371/* 372 * Number of required SGEs is the sum of two: 373 * 1. Number of possible opened aggregations (next packet for 374 * these aggregations will probably consume SGE immidiatelly) 375 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 376 * after placement on BD for new TPA aggregation) 377 * 378 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 379 */ 380#define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 381 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 382#define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 383 MAX_RX_SGE_CNT) 384#define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 385 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 386#define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 387 388/* Manipulate a bit vector defined as an array of u64 */ 389 390/* Number of bits in one sge_mask array element */ 391#define BIT_VEC64_ELEM_SZ 64 392#define BIT_VEC64_ELEM_SHIFT 6 393#define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 394 395 396#define __BIT_VEC64_SET_BIT(el, bit) \ 397 do { \ 398 el = ((el) | ((u64)0x1 << (bit))); \ 399 } while (0) 400 401#define __BIT_VEC64_CLEAR_BIT(el, bit) \ 402 do { \ 403 el = ((el) & (~((u64)0x1 << (bit)))); \ 404 } while (0) 405 406 407#define BIT_VEC64_SET_BIT(vec64, idx) \ 408 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 409 (idx) & BIT_VEC64_ELEM_MASK) 410 411#define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 412 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 413 (idx) & BIT_VEC64_ELEM_MASK) 414 415#define BIT_VEC64_TEST_BIT(vec64, idx) \ 416 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 417 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 418 419/* Creates a bitmask of all ones in less significant bits. 420 idx - index of the most significant bit in the created mask */ 421#define BIT_VEC64_ONES_MASK(idx) \ 422 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 423#define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 424 425/*******************************************************/ 426 427 428 429/* Number of u64 elements in SGE mask array */ 430#define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 431#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 432#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 433 434union host_hc_status_block { 435 /* pointer to fp status block e1x */ 436 struct host_hc_status_block_e1x *e1x_sb; 437 /* pointer to fp status block e2 */ 438 struct host_hc_status_block_e2 *e2_sb; 439}; 440 441struct bnx2x_agg_info { 442 /* 443 * First aggregation buffer is a data buffer, the following - are pages. 444 * We will preallocate the data buffer for each aggregation when 445 * we open the interface and will replace the BD at the consumer 446 * with this one when we receive the TPA_START CQE in order to 447 * keep the Rx BD ring consistent. 448 */ 449 struct sw_rx_bd first_buf; 450 u8 tpa_state; 451#define BNX2X_TPA_START 1 452#define BNX2X_TPA_STOP 2 453#define BNX2X_TPA_ERROR 3 454 u8 placement_offset; 455 u16 parsing_flags; 456 u16 vlan_tag; 457 u16 len_on_bd; 458 u32 rxhash; 459 u16 gro_size; 460 u16 full_page; 461}; 462 463#define Q_STATS_OFFSET32(stat_name) \ 464 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 465 466struct bnx2x_fp_txdata { 467 468 struct sw_tx_bd *tx_buf_ring; 469 470 union eth_tx_bd_types *tx_desc_ring; 471 dma_addr_t tx_desc_mapping; 472 473 u32 cid; 474 475 union db_prod tx_db; 476 477 u16 tx_pkt_prod; 478 u16 tx_pkt_cons; 479 u16 tx_bd_prod; 480 u16 tx_bd_cons; 481 482 unsigned long tx_pkt; 483 484 __le16 *tx_cons_sb; 485 486 int txq_index; 487 struct bnx2x_fastpath *parent_fp; 488 int tx_ring_size; 489}; 490 491enum bnx2x_tpa_mode_t { 492 TPA_MODE_LRO, 493 TPA_MODE_GRO 494}; 495 496struct bnx2x_fastpath { 497 struct bnx2x *bp; /* parent */ 498 499#define BNX2X_NAPI_WEIGHT 128 500 struct napi_struct napi; 501 union host_hc_status_block status_blk; 502 /* chip independed shortcuts into sb structure */ 503 __le16 *sb_index_values; 504 __le16 *sb_running_index; 505 /* chip independed shortcut into rx_prods_offset memory */ 506 u32 ustorm_rx_prods_offset; 507 508 u32 rx_buf_size; 509 510 dma_addr_t status_blk_mapping; 511 512 enum bnx2x_tpa_mode_t mode; 513 514 u8 max_cos; /* actual number of active tx coses */ 515 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 516 517 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 518 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 519 520 struct eth_rx_bd *rx_desc_ring; 521 dma_addr_t rx_desc_mapping; 522 523 union eth_rx_cqe *rx_comp_ring; 524 dma_addr_t rx_comp_mapping; 525 526 /* SGE ring */ 527 struct eth_rx_sge *rx_sge_ring; 528 dma_addr_t rx_sge_mapping; 529 530 u64 sge_mask[RX_SGE_MASK_LEN]; 531 532 u32 cid; 533 534 __le16 fp_hc_idx; 535 536 u8 index; /* number in fp array */ 537 u8 rx_queue; /* index for skb_record */ 538 u8 cl_id; /* eth client id */ 539 u8 cl_qzone_id; 540 u8 fw_sb_id; /* status block number in FW */ 541 u8 igu_sb_id; /* status block number in HW */ 542 543 u16 rx_bd_prod; 544 u16 rx_bd_cons; 545 u16 rx_comp_prod; 546 u16 rx_comp_cons; 547 u16 rx_sge_prod; 548 /* The last maximal completed SGE */ 549 u16 last_max_sge; 550 __le16 *rx_cons_sb; 551 unsigned long rx_pkt, 552 rx_calls; 553 554 /* TPA related */ 555 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 556 u8 disable_tpa; 557#ifdef BNX2X_STOP_ON_ERROR 558 u64 tpa_queue_used; 559#endif 560 561 struct tstorm_per_queue_stats old_tclient; 562 struct ustorm_per_queue_stats old_uclient; 563 struct xstorm_per_queue_stats old_xclient; 564 struct bnx2x_eth_q_stats eth_q_stats; 565 struct bnx2x_eth_q_stats_old eth_q_stats_old; 566 567 /* The size is calculated using the following: 568 sizeof name field from netdev structure + 569 4 ('-Xx-' string) + 570 4 (for the digits and to make it DWORD aligned) */ 571#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 572 char name[FP_NAME_SIZE]; 573 574 /* MACs object */ 575 struct bnx2x_vlan_mac_obj mac_obj; 576 577 /* Queue State object */ 578 struct bnx2x_queue_sp_obj q_obj; 579 580}; 581 582#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) 583 584/* Use 2500 as a mini-jumbo MTU for FCoE */ 585#define BNX2X_FCOE_MINI_JUMBO_MTU 2500 586 587#define FCOE_IDX_OFFSET 0 588 589#define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 590 FCOE_IDX_OFFSET) 591#define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 592#define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 593#define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 594 txdata_ptr[FIRST_TX_COS_INDEX] \ 595 ->var) 596 597 598#define IS_ETH_FP(fp) (fp->index < \ 599 BNX2X_NUM_ETH_QUEUES(fp->bp)) 600#ifdef BCM_CNIC 601#define IS_FCOE_FP(fp) (fp->index == FCOE_IDX(fp->bp)) 602#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 603#else 604#define IS_FCOE_FP(fp) false 605#define IS_FCOE_IDX(idx) false 606#endif 607 608 609/* MC hsi */ 610#define MAX_FETCH_BD 13 /* HW max BDs per packet */ 611#define RX_COPY_THRESH 92 612 613#define NUM_TX_RINGS 16 614#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 615#define NEXT_PAGE_TX_DESC_CNT 1 616#define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 617#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 618#define MAX_TX_BD (NUM_TX_BD - 1) 619#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 620#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 621 (MAX_TX_DESC_CNT - 1)) ? \ 622 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 623 (x) + 1) 624#define TX_BD(x) ((x) & MAX_TX_BD) 625#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 626 627/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 628#define NUM_RX_RINGS 8 629#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 630#define NEXT_PAGE_RX_DESC_CNT 2 631#define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 632#define RX_DESC_MASK (RX_DESC_CNT - 1) 633#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 634#define MAX_RX_BD (NUM_RX_BD - 1) 635#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 636 637/* dropless fc calculations for BDs 638 * 639 * Number of BDs should as number of buffers in BRB: 640 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 641 * "next" elements on each page 642 */ 643#define NUM_BD_REQ BRB_SIZE(bp) 644#define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 645 MAX_RX_DESC_CNT) 646#define BD_TH_LO(bp) (NUM_BD_REQ + \ 647 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 648 FW_DROP_LEVEL(bp)) 649#define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 650 651#define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 652 653#define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 654 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 655 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 656#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 657#define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 658#define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 659 MIN_RX_AVAIL)) 660 661#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 662 (MAX_RX_DESC_CNT - 1)) ? \ 663 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 664 (x) + 1) 665#define RX_BD(x) ((x) & MAX_RX_BD) 666 667/* 668 * As long as CQE is X times bigger than BD entry we have to allocate X times 669 * more pages for CQ ring in order to keep it balanced with BD ring 670 */ 671#define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 672#define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 673#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 674#define NEXT_PAGE_RCQ_DESC_CNT 1 675#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 676#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 677#define MAX_RCQ_BD (NUM_RCQ_BD - 1) 678#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 679#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 680 (MAX_RCQ_DESC_CNT - 1)) ? \ 681 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 682 (x) + 1) 683#define RCQ_BD(x) ((x) & MAX_RCQ_BD) 684 685/* dropless fc calculations for RCQs 686 * 687 * Number of RCQs should be as number of buffers in BRB: 688 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 689 * "next" elements on each page 690 */ 691#define NUM_RCQ_REQ BRB_SIZE(bp) 692#define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 693 MAX_RCQ_DESC_CNT) 694#define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 695 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 696 FW_DROP_LEVEL(bp)) 697#define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 698 699 700/* This is needed for determining of last_max */ 701#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 702#define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 703 704 705#define BNX2X_SWCID_SHIFT 17 706#define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 707 708/* used on a CID received from the HW */ 709#define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 710#define CQE_CMD(x) (le32_to_cpu(x) >> \ 711 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 712 713#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 714 le32_to_cpu((bd)->addr_lo)) 715#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 716 717#define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 718#define BNX2X_DB_SHIFT 7 /* 128 bytes*/ 719#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 720#error "Min DB doorbell stride is 8" 721#endif 722#define DPM_TRIGER_TYPE 0x40 723#define DOORBELL(bp, cid, val) \ 724 do { \ 725 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ 726 DPM_TRIGER_TYPE); \ 727 } while (0) 728 729 730/* TX CSUM helpers */ 731#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 732 skb->csum_offset) 733#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 734 skb->csum_offset)) 735 736#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) 737 738#define XMIT_PLAIN 0 739#define XMIT_CSUM_V4 0x1 740#define XMIT_CSUM_V6 0x2 741#define XMIT_CSUM_TCP 0x4 742#define XMIT_GSO_V4 0x8 743#define XMIT_GSO_V6 0x10 744 745#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) 746#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) 747 748 749/* stuff added to make the code fit 80Col */ 750#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 751#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 752#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 753#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 754#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 755 756#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 757 758#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 759 (((le16_to_cpu(flags) & \ 760 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 761 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 762 == PRS_FLAG_OVERETH_IPV4) 763#define BNX2X_RX_SUM_FIX(cqe) \ 764 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 765 766 767#define FP_USB_FUNC_OFF \ 768 offsetof(struct cstorm_status_block_u, func) 769#define FP_CSB_FUNC_OFF \ 770 offsetof(struct cstorm_status_block_c, func) 771 772#define HC_INDEX_ETH_RX_CQ_CONS 1 773 774#define HC_INDEX_OOO_TX_CQ_CONS 4 775 776#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 777 778#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 779 780#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 781 782#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 783 784#define BNX2X_RX_SB_INDEX \ 785 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 786 787#define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 788 789#define BNX2X_TX_SB_INDEX_COS0 \ 790 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 791 792/* end of fast path */ 793 794/* common */ 795 796struct bnx2x_common { 797 798 u32 chip_id; 799/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 800#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 801 802#define CHIP_NUM(bp) (bp->common.chip_id >> 16) 803#define CHIP_NUM_57710 0x164e 804#define CHIP_NUM_57711 0x164f 805#define CHIP_NUM_57711E 0x1650 806#define CHIP_NUM_57712 0x1662 807#define CHIP_NUM_57712_MF 0x1663 808#define CHIP_NUM_57713 0x1651 809#define CHIP_NUM_57713E 0x1652 810#define CHIP_NUM_57800 0x168a 811#define CHIP_NUM_57800_MF 0x16a5 812#define CHIP_NUM_57810 0x168e 813#define CHIP_NUM_57810_MF 0x16ae 814#define CHIP_NUM_57811 0x163d 815#define CHIP_NUM_57811_MF 0x163e 816#define CHIP_NUM_57840 0x168d 817#define CHIP_NUM_57840_MF 0x16ab 818#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 819#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 820#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 821#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 822#define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 823#define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 824#define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 825#define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 826#define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 827#define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 828#define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 829#define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840) 830#define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF) 831#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 832 CHIP_IS_57711E(bp)) 833#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 834 CHIP_IS_57712_MF(bp)) 835#define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 836 CHIP_IS_57800_MF(bp) || \ 837 CHIP_IS_57810(bp) || \ 838 CHIP_IS_57810_MF(bp) || \ 839 CHIP_IS_57811(bp) || \ 840 CHIP_IS_57811_MF(bp) || \ 841 CHIP_IS_57840(bp) || \ 842 CHIP_IS_57840_MF(bp)) 843#define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 844#define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 845#define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 846 847#define CHIP_REV_SHIFT 12 848#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 849#define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 850#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 851#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 852/* assume maximum 5 revisions */ 853#define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 854/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 855#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 856 !(CHIP_REV_VAL(bp) & 0x00001000)) 857/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 858#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 859 (CHIP_REV_VAL(bp) & 0x00001000)) 860 861#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 862 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 863 864#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 865#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 866#define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 867 (CHIP_REV_SHIFT + 1)) \ 868 << CHIP_REV_SHIFT) 869#define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 870 CHIP_REV_SIM(bp) :\ 871 CHIP_REV_VAL(bp)) 872#define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 873 (CHIP_REV(bp) == CHIP_REV_Bx)) 874#define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 875 (CHIP_REV(bp) == CHIP_REV_Ax)) 876 877 int flash_size; 878#define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 879#define BNX2X_NVRAM_TIMEOUT_COUNT 30000 880#define BNX2X_NVRAM_PAGE_SIZE 256 881 882 u32 shmem_base; 883 u32 shmem2_base; 884 u32 mf_cfg_base; 885 u32 mf2_cfg_base; 886 887 u32 hw_config; 888 889 u32 bc_ver; 890 891 u8 int_block; 892#define INT_BLOCK_HC 0 893#define INT_BLOCK_IGU 1 894#define INT_BLOCK_MODE_NORMAL 0 895#define INT_BLOCK_MODE_BW_COMP 2 896#define CHIP_INT_MODE_IS_NBC(bp) \ 897 (!CHIP_IS_E1x(bp) && \ 898 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 899#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 900 901 u8 chip_port_mode; 902#define CHIP_4_PORT_MODE 0x0 903#define CHIP_2_PORT_MODE 0x1 904#define CHIP_PORT_MODE_NONE 0x2 905#define CHIP_MODE(bp) (bp->common.chip_port_mode) 906#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 907 908 u32 boot_mode; 909}; 910 911/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 912#define BNX2X_IGU_STAS_MSG_VF_CNT 64 913#define BNX2X_IGU_STAS_MSG_PF_CNT 4 914 915/* end of common */ 916 917/* port */ 918 919struct bnx2x_port { 920 u32 pmf; 921 922 u32 link_config[LINK_CONFIG_SIZE]; 923 924 u32 supported[LINK_CONFIG_SIZE]; 925/* link settings - missing defines */ 926#define SUPPORTED_2500baseX_Full (1 << 15) 927 928 u32 advertising[LINK_CONFIG_SIZE]; 929/* link settings - missing defines */ 930#define ADVERTISED_2500baseX_Full (1 << 15) 931 932 u32 phy_addr; 933 934 /* used to synchronize phy accesses */ 935 struct mutex phy_mutex; 936 int need_hw_lock; 937 938 u32 port_stx; 939 940 struct nig_stats old_nig_stats; 941}; 942 943/* end of port */ 944 945#define STATS_OFFSET32(stat_name) \ 946 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 947 948/* slow path */ 949 950/* slow path work-queue */ 951extern struct workqueue_struct *bnx2x_wq; 952 953#define BNX2X_MAX_NUM_OF_VFS 64 954#define BNX2X_VF_ID_INVALID 0xFF 955 956/* 957 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 958 * control by the number of fast-path status blocks supported by the 959 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 960 * status block represents an independent interrupts context that can 961 * serve a regular L2 networking queue. However special L2 queues such 962 * as the FCoE queue do not require a FP-SB and other components like 963 * the CNIC may consume FP-SB reducing the number of possible L2 queues 964 * 965 * If the maximum number of FP-SB available is X then: 966 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 967 * regular L2 queues is Y=X-1 968 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 969 * c. If the FCoE L2 queue is supported the actual number of L2 queues 970 * is Y+1 971 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 972 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 973 * FP interrupt context for the CNIC). 974 * e. The number of HW context (CID count) is always X or X+1 if FCoE 975 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 976 */ 977 978/* fast-path interrupt contexts E1x */ 979#define FP_SB_MAX_E1x 16 980/* fast-path interrupt contexts E2 */ 981#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 982 983union cdu_context { 984 struct eth_context eth; 985 char pad[1024]; 986}; 987 988/* CDU host DB constants */ 989#define CDU_ILT_PAGE_SZ_HW 2 990#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 991#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 992 993#ifdef BCM_CNIC 994#define CNIC_ISCSI_CID_MAX 256 995#define CNIC_FCOE_CID_MAX 2048 996#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 997#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 998#endif 999 1000#define QM_ILT_PAGE_SZ_HW 0 1001#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1002#define QM_CID_ROUND 1024 1003 1004#ifdef BCM_CNIC 1005/* TM (timers) host DB constants */ 1006#define TM_ILT_PAGE_SZ_HW 0 1007#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1008/* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 1009#define TM_CONN_NUM 1024 1010#define TM_ILT_SZ (8 * TM_CONN_NUM) 1011#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1012 1013/* SRC (Searcher) host DB constants */ 1014#define SRC_ILT_PAGE_SZ_HW 0 1015#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1016#define SRC_HASH_BITS 10 1017#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1018#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1019#define SRC_T2_SZ SRC_ILT_SZ 1020#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1021 1022#endif 1023 1024#define MAX_DMAE_C 8 1025 1026/* DMA memory not used in fastpath */ 1027struct bnx2x_slowpath { 1028 union { 1029 struct mac_configuration_cmd e1x; 1030 struct eth_classify_rules_ramrod_data e2; 1031 } mac_rdata; 1032 1033 1034 union { 1035 struct tstorm_eth_mac_filter_config e1x; 1036 struct eth_filter_rules_ramrod_data e2; 1037 } rx_mode_rdata; 1038 1039 union { 1040 struct mac_configuration_cmd e1; 1041 struct eth_multicast_rules_ramrod_data e2; 1042 } mcast_rdata; 1043 1044 struct eth_rss_update_ramrod_data rss_rdata; 1045 1046 /* Queue State related ramrods are always sent under rtnl_lock */ 1047 union { 1048 struct client_init_ramrod_data init_data; 1049 struct client_update_ramrod_data update_data; 1050 } q_rdata; 1051 1052 union { 1053 struct function_start_data func_start; 1054 /* pfc configuration for DCBX ramrod */ 1055 struct flow_control_configuration pfc_config; 1056 } func_rdata; 1057 1058 /* afex ramrod can not be a part of func_rdata union because these 1059 * events might arrive in parallel to other events from func_rdata. 1060 * Therefore, if they would have been defined in the same union, 1061 * data can get corrupted. 1062 */ 1063 struct afex_vif_list_ramrod_data func_afex_rdata; 1064 1065 /* used by dmae command executer */ 1066 struct dmae_command dmae[MAX_DMAE_C]; 1067 1068 u32 stats_comp; 1069 union mac_stats mac_stats; 1070 struct nig_stats nig_stats; 1071 struct host_port_stats port_stats; 1072 struct host_func_stats func_stats; 1073 1074 u32 wb_comp; 1075 u32 wb_data[4]; 1076 1077 union drv_info_to_mcp drv_info_to_mcp; 1078}; 1079 1080#define bnx2x_sp(bp, var) (&bp->slowpath->var) 1081#define bnx2x_sp_mapping(bp, var) \ 1082 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1083 1084 1085/* attn group wiring */ 1086#define MAX_DYNAMIC_ATTN_GRPS 8 1087 1088struct attn_route { 1089 u32 sig[5]; 1090}; 1091 1092struct iro { 1093 u32 base; 1094 u16 m1; 1095 u16 m2; 1096 u16 m3; 1097 u16 size; 1098}; 1099 1100struct hw_context { 1101 union cdu_context *vcxt; 1102 dma_addr_t cxt_mapping; 1103 size_t size; 1104}; 1105 1106/* forward */ 1107struct bnx2x_ilt; 1108 1109 1110enum bnx2x_recovery_state { 1111 BNX2X_RECOVERY_DONE, 1112 BNX2X_RECOVERY_INIT, 1113 BNX2X_RECOVERY_WAIT, 1114 BNX2X_RECOVERY_FAILED, 1115 BNX2X_RECOVERY_NIC_LOADING 1116}; 1117 1118/* 1119 * Event queue (EQ or event ring) MC hsi 1120 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1121 */ 1122#define NUM_EQ_PAGES 1 1123#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1124#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1125#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1126#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1127#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1128 1129/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1130#define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1131 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1132 1133/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1134#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1135 1136#define BNX2X_EQ_INDEX \ 1137 (&bp->def_status_blk->sp_sb.\ 1138 index_values[HC_SP_INDEX_EQ_CONS]) 1139 1140/* This is a data that will be used to create a link report message. 1141 * We will keep the data used for the last link report in order 1142 * to prevent reporting the same link parameters twice. 1143 */ 1144struct bnx2x_link_report_data { 1145 u16 line_speed; /* Effective line speed */ 1146 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1147}; 1148 1149enum { 1150 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1151 BNX2X_LINK_REPORT_LINK_DOWN, 1152 BNX2X_LINK_REPORT_RX_FC_ON, 1153 BNX2X_LINK_REPORT_TX_FC_ON, 1154}; 1155 1156enum { 1157 BNX2X_PORT_QUERY_IDX, 1158 BNX2X_PF_QUERY_IDX, 1159 BNX2X_FCOE_QUERY_IDX, 1160 BNX2X_FIRST_QUEUE_QUERY_IDX, 1161}; 1162 1163struct bnx2x_fw_stats_req { 1164 struct stats_query_header hdr; 1165 struct stats_query_entry query[FP_SB_MAX_E1x+ 1166 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1167}; 1168 1169struct bnx2x_fw_stats_data { 1170 struct stats_counter storm_counters; 1171 struct per_port_stats port; 1172 struct per_pf_stats pf; 1173 struct fcoe_statistics_params fcoe; 1174 struct per_queue_stats queue_stats[1]; 1175}; 1176 1177/* Public slow path states */ 1178enum { 1179 BNX2X_SP_RTNL_SETUP_TC, 1180 BNX2X_SP_RTNL_TX_TIMEOUT, 1181 BNX2X_SP_RTNL_AFEX_F_UPDATE, 1182 BNX2X_SP_RTNL_FAN_FAILURE, 1183}; 1184 1185 1186struct bnx2x_prev_path_list { 1187 u8 bus; 1188 u8 slot; 1189 u8 path; 1190 struct list_head list; 1191}; 1192 1193struct bnx2x { 1194 /* Fields used in the tx and intr/napi performance paths 1195 * are grouped together in the beginning of the structure 1196 */ 1197 struct bnx2x_fastpath *fp; 1198 struct bnx2x_fp_txdata *bnx2x_txq; 1199 int bnx2x_txq_size; 1200 void __iomem *regview; 1201 void __iomem *doorbells; 1202 u16 db_size; 1203 1204 u8 pf_num; /* absolute PF number */ 1205 u8 pfid; /* per-path PF number */ 1206 int base_fw_ndsb; /**/ 1207#define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1208#define BP_PORT(bp) (bp->pfid & 1) 1209#define BP_FUNC(bp) (bp->pfid) 1210#define BP_ABS_FUNC(bp) (bp->pf_num) 1211#define BP_VN(bp) ((bp)->pfid >> 1) 1212#define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1213#define BP_L_ID(bp) (BP_VN(bp) << 2) 1214#define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1215 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1216#define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1217 1218 struct net_device *dev; 1219 struct pci_dev *pdev; 1220 1221 const struct iro *iro_arr; 1222#define IRO (bp->iro_arr) 1223 1224 enum bnx2x_recovery_state recovery_state; 1225 int is_leader; 1226 struct msix_entry *msix_table; 1227 1228 int tx_ring_size; 1229 1230/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1231#define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1232#define ETH_MIN_PACKET_SIZE 60 1233#define ETH_MAX_PACKET_SIZE 1500 1234#define ETH_MAX_JUMBO_PACKET_SIZE 9600 1235/* TCP with Timestamp Option (32) + IPv6 (40) */ 1236#define ETH_MAX_TPA_HEADER_SIZE 72 1237 1238 /* Max supported alignment is 256 (8 shift) */ 1239#define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1240 1241 /* FW uses 2 Cache lines Alignment for start packet and size 1242 * 1243 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1244 * at the end of skb->data, to avoid wasting a full cache line. 1245 * This reduces memory use (skb->truesize). 1246 */ 1247#define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1248 1249#define BNX2X_FW_RX_ALIGN_END \ 1250 max(1UL << BNX2X_RX_ALIGN_SHIFT, \ 1251 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1252 1253#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1254 1255 struct host_sp_status_block *def_status_blk; 1256#define DEF_SB_IGU_ID 16 1257#define DEF_SB_ID HC_SP_SB_ID 1258 __le16 def_idx; 1259 __le16 def_att_idx; 1260 u32 attn_state; 1261 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1262 1263 /* slow path ring */ 1264 struct eth_spe *spq; 1265 dma_addr_t spq_mapping; 1266 u16 spq_prod_idx; 1267 struct eth_spe *spq_prod_bd; 1268 struct eth_spe *spq_last_bd; 1269 __le16 *dsb_sp_prod; 1270 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1271 /* used to synchronize spq accesses */ 1272 spinlock_t spq_lock; 1273 1274 /* event queue */ 1275 union event_ring_elem *eq_ring; 1276 dma_addr_t eq_mapping; 1277 u16 eq_prod; 1278 u16 eq_cons; 1279 __le16 *eq_cons_sb; 1280 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1281 1282 1283 1284 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1285 u16 stats_pending; 1286 /* Counter for completed statistics ramrods */ 1287 u16 stats_comp; 1288 1289 /* End of fields used in the performance code paths */ 1290 1291 int panic; 1292 int msg_enable; 1293 1294 u32 flags; 1295#define PCIX_FLAG (1 << 0) 1296#define PCI_32BIT_FLAG (1 << 1) 1297#define ONE_PORT_FLAG (1 << 2) 1298#define NO_WOL_FLAG (1 << 3) 1299#define USING_DAC_FLAG (1 << 4) 1300#define USING_MSIX_FLAG (1 << 5) 1301#define USING_MSI_FLAG (1 << 6) 1302#define DISABLE_MSI_FLAG (1 << 7) 1303#define TPA_ENABLE_FLAG (1 << 8) 1304#define NO_MCP_FLAG (1 << 9) 1305 1306#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) 1307#define GRO_ENABLE_FLAG (1 << 10) 1308#define MF_FUNC_DIS (1 << 11) 1309#define OWN_CNIC_IRQ (1 << 12) 1310#define NO_ISCSI_OOO_FLAG (1 << 13) 1311#define NO_ISCSI_FLAG (1 << 14) 1312#define NO_FCOE_FLAG (1 << 15) 1313#define BC_SUPPORTS_PFC_STATS (1 << 17) 1314#define USING_SINGLE_MSIX_FLAG (1 << 20) 1315 1316#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1317#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1318#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1319 1320 int pm_cap; 1321 int mrrs; 1322 1323 struct delayed_work sp_task; 1324 struct delayed_work sp_rtnl_task; 1325 1326 struct delayed_work period_task; 1327 struct timer_list timer; 1328 int current_interval; 1329 1330 u16 fw_seq; 1331 u16 fw_drv_pulse_wr_seq; 1332 u32 func_stx; 1333 1334 struct link_params link_params; 1335 struct link_vars link_vars; 1336 u32 link_cnt; 1337 struct bnx2x_link_report_data last_reported_link; 1338 1339 struct mdio_if_info mdio; 1340 1341 struct bnx2x_common common; 1342 struct bnx2x_port port; 1343 1344 struct cmng_init cmng; 1345 1346 u32 mf_config[E1HVN_MAX]; 1347 u32 mf_ext_config; 1348 u32 path_has_ovlan; /* E3 */ 1349 u16 mf_ov; 1350 u8 mf_mode; 1351#define IS_MF(bp) (bp->mf_mode != 0) 1352#define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1353#define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1354#define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1355 1356 u8 wol; 1357 1358 int rx_ring_size; 1359 1360 u16 tx_quick_cons_trip_int; 1361 u16 tx_quick_cons_trip; 1362 u16 tx_ticks_int; 1363 u16 tx_ticks; 1364 1365 u16 rx_quick_cons_trip_int; 1366 u16 rx_quick_cons_trip; 1367 u16 rx_ticks_int; 1368 u16 rx_ticks; 1369/* Maximal coalescing timeout in us */ 1370#define BNX2X_MAX_COALESCE_TOUT (0xf0*12) 1371 1372 u32 lin_cnt; 1373 1374 u16 state; 1375#define BNX2X_STATE_CLOSED 0 1376#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1377#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1378#define BNX2X_STATE_OPEN 0x3000 1379#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1380#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1381 1382#define BNX2X_STATE_DIAG 0xe000 1383#define BNX2X_STATE_ERROR 0xf000 1384 1385#define BNX2X_MAX_PRIORITY 8 1386#define BNX2X_MAX_ENTRIES_PER_PRI 16 1387#define BNX2X_MAX_COS 3 1388#define BNX2X_MAX_TX_COS 2 1389 int num_queues; 1390 int disable_tpa; 1391 1392 u32 rx_mode; 1393#define BNX2X_RX_MODE_NONE 0 1394#define BNX2X_RX_MODE_NORMAL 1 1395#define BNX2X_RX_MODE_ALLMULTI 2 1396#define BNX2X_RX_MODE_PROMISC 3 1397#define BNX2X_MAX_MULTICAST 64 1398 1399 u8 igu_dsb_id; 1400 u8 igu_base_sb; 1401 u8 igu_sb_cnt; 1402 1403 dma_addr_t def_status_blk_mapping; 1404 1405 struct bnx2x_slowpath *slowpath; 1406 dma_addr_t slowpath_mapping; 1407 1408 /* Total number of FW statistics requests */ 1409 u8 fw_stats_num; 1410 1411 /* 1412 * This is a memory buffer that will contain both statistics 1413 * ramrod request and data. 1414 */ 1415 void *fw_stats; 1416 dma_addr_t fw_stats_mapping; 1417 1418 /* 1419 * FW statistics request shortcut (points at the 1420 * beginning of fw_stats buffer). 1421 */ 1422 struct bnx2x_fw_stats_req *fw_stats_req; 1423 dma_addr_t fw_stats_req_mapping; 1424 int fw_stats_req_sz; 1425 1426 /* 1427 * FW statistics data shortcut (points at the begining of 1428 * fw_stats buffer + fw_stats_req_sz). 1429 */ 1430 struct bnx2x_fw_stats_data *fw_stats_data; 1431 dma_addr_t fw_stats_data_mapping; 1432 int fw_stats_data_sz; 1433 1434 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1435 * context size we need 8 ILT entries. 1436 */ 1437#define ILT_MAX_L2_LINES 8 1438 struct hw_context context[ILT_MAX_L2_LINES]; 1439 1440 struct bnx2x_ilt *ilt; 1441#define BP_ILT(bp) ((bp)->ilt) 1442#define ILT_MAX_LINES 256 1443/* 1444 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1445 * to CNIC. 1446 */ 1447#define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT) 1448 1449/* 1450 * Maximum CID count that might be required by the bnx2x: 1451 * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related) 1452 */ 1453#define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\ 1454 NON_ETH_CONTEXT_USE + CNIC_PRESENT) 1455#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1456 ILT_PAGE_CIDS)) 1457 1458 int qm_cid_count; 1459 1460 int dropless_fc; 1461 1462#ifdef BCM_CNIC 1463 u32 cnic_flags; 1464#define BNX2X_CNIC_FLAG_MAC_SET 1 1465 void *t2; 1466 dma_addr_t t2_mapping; 1467 struct cnic_ops __rcu *cnic_ops; 1468 void *cnic_data; 1469 u32 cnic_tag; 1470 struct cnic_eth_dev cnic_eth_dev; 1471 union host_hc_status_block cnic_sb; 1472 dma_addr_t cnic_sb_mapping; 1473 struct eth_spe *cnic_kwq; 1474 struct eth_spe *cnic_kwq_prod; 1475 struct eth_spe *cnic_kwq_cons; 1476 struct eth_spe *cnic_kwq_last; 1477 u16 cnic_kwq_pending; 1478 u16 cnic_spq_pending; 1479 u8 fip_mac[ETH_ALEN]; 1480 struct mutex cnic_mutex; 1481 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1482 1483 /* Start index of the "special" (CNIC related) L2 cleints */ 1484 u8 cnic_base_cl_id; 1485#endif 1486 1487 int dmae_ready; 1488 /* used to synchronize dmae accesses */ 1489 spinlock_t dmae_lock; 1490 1491 /* used to protect the FW mail box */ 1492 struct mutex fw_mb_mutex; 1493 1494 /* used to synchronize stats collecting */ 1495 int stats_state; 1496 1497 /* used for synchronization of concurrent threads statistics handling */ 1498 spinlock_t stats_lock; 1499 1500 /* used by dmae command loader */ 1501 struct dmae_command stats_dmae; 1502 int executer_idx; 1503 1504 u16 stats_counter; 1505 struct bnx2x_eth_stats eth_stats; 1506 struct host_func_stats func_stats; 1507 struct bnx2x_eth_stats_old eth_stats_old; 1508 struct bnx2x_net_stats_old net_stats_old; 1509 struct bnx2x_fw_port_stats_old fw_stats_old; 1510 bool stats_init; 1511 1512 struct z_stream_s *strm; 1513 void *gunzip_buf; 1514 dma_addr_t gunzip_mapping; 1515 int gunzip_outlen; 1516#define FW_BUF_SIZE 0x8000 1517#define GUNZIP_BUF(bp) (bp->gunzip_buf) 1518#define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1519#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1520 1521 struct raw_op *init_ops; 1522 /* Init blocks offsets inside init_ops */ 1523 u16 *init_ops_offsets; 1524 /* Data blob - has 32 bit granularity */ 1525 u32 *init_data; 1526 u32 init_mode_flags; 1527#define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1528 /* Zipped PRAM blobs - raw data */ 1529 const u8 *tsem_int_table_data; 1530 const u8 *tsem_pram_data; 1531 const u8 *usem_int_table_data; 1532 const u8 *usem_pram_data; 1533 const u8 *xsem_int_table_data; 1534 const u8 *xsem_pram_data; 1535 const u8 *csem_int_table_data; 1536 const u8 *csem_pram_data; 1537#define INIT_OPS(bp) (bp->init_ops) 1538#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1539#define INIT_DATA(bp) (bp->init_data) 1540#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1541#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1542#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1543#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1544#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1545#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1546#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1547#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1548 1549#define PHY_FW_VER_LEN 20 1550 char fw_ver[32]; 1551 const struct firmware *firmware; 1552 1553 /* DCB support on/off */ 1554 u16 dcb_state; 1555#define BNX2X_DCB_STATE_OFF 0 1556#define BNX2X_DCB_STATE_ON 1 1557 1558 /* DCBX engine mode */ 1559 int dcbx_enabled; 1560#define BNX2X_DCBX_ENABLED_OFF 0 1561#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1562#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1563#define BNX2X_DCBX_ENABLED_INVALID (-1) 1564 1565 bool dcbx_mode_uset; 1566 1567 struct bnx2x_config_dcbx_params dcbx_config_params; 1568 struct bnx2x_dcbx_port_params dcbx_port_params; 1569 int dcb_version; 1570 1571 /* CAM credit pools */ 1572 struct bnx2x_credit_pool_obj macs_pool; 1573 1574 /* RX_MODE object */ 1575 struct bnx2x_rx_mode_obj rx_mode_obj; 1576 1577 /* MCAST object */ 1578 struct bnx2x_mcast_obj mcast_obj; 1579 1580 /* RSS configuration object */ 1581 struct bnx2x_rss_config_obj rss_conf_obj; 1582 1583 /* Function State controlling object */ 1584 struct bnx2x_func_sp_obj func_obj; 1585 1586 unsigned long sp_state; 1587 1588 /* operation indication for the sp_rtnl task */ 1589 unsigned long sp_rtnl_state; 1590 1591 /* DCBX Negotation results */ 1592 struct dcbx_features dcbx_local_feat; 1593 u32 dcbx_error; 1594 1595#ifdef BCM_DCBNL 1596 struct dcbx_features dcbx_remote_feat; 1597 u32 dcbx_remote_flags; 1598#endif 1599 /* AFEX: store default vlan used */ 1600 int afex_def_vlan_tag; 1601 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1602 u32 pending_max; 1603 1604 /* multiple tx classes of service */ 1605 u8 max_cos; 1606 1607 /* priority to cos mapping */ 1608 u8 prio_to_cos[8]; 1609}; 1610 1611/* Tx queues may be less or equal to Rx queues */ 1612extern int num_queues; 1613#define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1614#define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE) 1615#define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 1616 NON_ETH_CONTEXT_USE) 1617#define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1618 1619#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1620 1621#define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1622/* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1623 1624#define RSS_IPV4_CAP_MASK \ 1625 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1626 1627#define RSS_IPV4_TCP_CAP_MASK \ 1628 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1629 1630#define RSS_IPV6_CAP_MASK \ 1631 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1632 1633#define RSS_IPV6_TCP_CAP_MASK \ 1634 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1635 1636/* func init flags */ 1637#define FUNC_FLG_RSS 0x0001 1638#define FUNC_FLG_STATS 0x0002 1639/* removed FUNC_FLG_UNMATCHED 0x0004 */ 1640#define FUNC_FLG_TPA 0x0008 1641#define FUNC_FLG_SPQ 0x0010 1642#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1643 1644 1645struct bnx2x_func_init_params { 1646 /* dma */ 1647 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1648 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1649 1650 u16 func_flgs; 1651 u16 func_id; /* abs fid */ 1652 u16 pf_id; 1653 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1654}; 1655 1656#define for_each_eth_queue(bp, var) \ 1657 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1658 1659#define for_each_nondefault_eth_queue(bp, var) \ 1660 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1661 1662#define for_each_queue(bp, var) \ 1663 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1664 if (skip_queue(bp, var)) \ 1665 continue; \ 1666 else 1667 1668/* Skip forwarding FP */ 1669#define for_each_rx_queue(bp, var) \ 1670 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1671 if (skip_rx_queue(bp, var)) \ 1672 continue; \ 1673 else 1674 1675/* Skip OOO FP */ 1676#define for_each_tx_queue(bp, var) \ 1677 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1678 if (skip_tx_queue(bp, var)) \ 1679 continue; \ 1680 else 1681 1682#define for_each_nondefault_queue(bp, var) \ 1683 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1684 if (skip_queue(bp, var)) \ 1685 continue; \ 1686 else 1687 1688#define for_each_cos_in_tx_queue(fp, var) \ 1689 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1690 1691/* skip rx queue 1692 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1693 */ 1694#define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1695 1696/* skip tx queue 1697 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1698 */ 1699#define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1700 1701#define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1702 1703 1704 1705 1706/** 1707 * bnx2x_set_mac_one - configure a single MAC address 1708 * 1709 * @bp: driver handle 1710 * @mac: MAC to configure 1711 * @obj: MAC object handle 1712 * @set: if 'true' add a new MAC, otherwise - delete 1713 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 1714 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 1715 * 1716 * Configures one MAC according to provided parameters or continues the 1717 * execution of previously scheduled commands if RAMROD_CONT is set in 1718 * ramrod_flags. 1719 * 1720 * Returns zero if operation has successfully completed, a positive value if the 1721 * operation has been successfully scheduled and a negative - if a requested 1722 * operations has failed. 1723 */ 1724int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 1725 struct bnx2x_vlan_mac_obj *obj, bool set, 1726 int mac_type, unsigned long *ramrod_flags); 1727/** 1728 * Deletes all MACs configured for the specific MAC object. 1729 * 1730 * @param bp Function driver instance 1731 * @param mac_obj MAC object to cleanup 1732 * 1733 * @return zero if all MACs were cleaned 1734 */ 1735 1736/** 1737 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 1738 * 1739 * @bp: driver handle 1740 * @mac_obj: MAC object handle 1741 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 1742 * @wait_for_comp: if 'true' block until completion 1743 * 1744 * Deletes all MACs of the specific type (e.g. ETH, UC list). 1745 * 1746 * Returns zero if operation has successfully completed, a positive value if the 1747 * operation has been successfully scheduled and a negative - if a requested 1748 * operations has failed. 1749 */ 1750int bnx2x_del_all_macs(struct bnx2x *bp, 1751 struct bnx2x_vlan_mac_obj *mac_obj, 1752 int mac_type, bool wait_for_comp); 1753 1754/* Init Function API */ 1755void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 1756int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 1757int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1758int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 1759int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1760void bnx2x_read_mf_cfg(struct bnx2x *bp); 1761 1762 1763/* dmae */ 1764void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 1765void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 1766 u32 len32); 1767void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 1768u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 1769u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 1770u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 1771 bool with_comp, u8 comp_type); 1772 1773 1774void bnx2x_calc_fc_adv(struct bnx2x *bp); 1775int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 1776 u32 data_hi, u32 data_lo, int cmd_type); 1777void bnx2x_update_coalesce(struct bnx2x *bp); 1778int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 1779 1780static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 1781 int wait) 1782{ 1783 u32 val; 1784 1785 do { 1786 val = REG_RD(bp, reg); 1787 if (val == expected) 1788 break; 1789 ms -= wait; 1790 msleep(wait); 1791 1792 } while (ms > 0); 1793 1794 return val; 1795} 1796 1797#define BNX2X_ILT_ZALLOC(x, y, size) \ 1798 do { \ 1799 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 1800 if (x) \ 1801 memset(x, 0, size); \ 1802 } while (0) 1803 1804#define BNX2X_ILT_FREE(x, y, size) \ 1805 do { \ 1806 if (x) { \ 1807 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 1808 x = NULL; \ 1809 y = 0; \ 1810 } \ 1811 } while (0) 1812 1813#define ILOG2(x) (ilog2((x))) 1814 1815#define ILT_NUM_PAGE_ENTRIES (3072) 1816/* In 57710/11 we use whole table since we have 8 func 1817 * In 57712 we have only 4 func, but use same size per func, then only half of 1818 * the table in use 1819 */ 1820#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 1821 1822#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 1823/* 1824 * the phys address is shifted right 12 bits and has an added 1825 * 1=valid bit added to the 53rd bit 1826 * then since this is a wide register(TM) 1827 * we split it into two 32 bit writes 1828 */ 1829#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 1830#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 1831 1832/* load/unload mode */ 1833#define LOAD_NORMAL 0 1834#define LOAD_OPEN 1 1835#define LOAD_DIAG 2 1836#define LOAD_LOOPBACK_EXT 3 1837#define UNLOAD_NORMAL 0 1838#define UNLOAD_CLOSE 1 1839#define UNLOAD_RECOVERY 2 1840 1841 1842/* DMAE command defines */ 1843#define DMAE_TIMEOUT -1 1844#define DMAE_PCI_ERROR -2 /* E2 and onward */ 1845#define DMAE_NOT_RDY -3 1846#define DMAE_PCI_ERR_FLAG 0x80000000 1847 1848#define DMAE_SRC_PCI 0 1849#define DMAE_SRC_GRC 1 1850 1851#define DMAE_DST_NONE 0 1852#define DMAE_DST_PCI 1 1853#define DMAE_DST_GRC 2 1854 1855#define DMAE_COMP_PCI 0 1856#define DMAE_COMP_GRC 1 1857 1858/* E2 and onward - PCI error handling in the completion */ 1859 1860#define DMAE_COMP_REGULAR 0 1861#define DMAE_COM_SET_ERR 1 1862 1863#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 1864 DMAE_COMMAND_SRC_SHIFT) 1865#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 1866 DMAE_COMMAND_SRC_SHIFT) 1867 1868#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 1869 DMAE_COMMAND_DST_SHIFT) 1870#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 1871 DMAE_COMMAND_DST_SHIFT) 1872 1873#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 1874 DMAE_COMMAND_C_DST_SHIFT) 1875#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 1876 DMAE_COMMAND_C_DST_SHIFT) 1877 1878#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 1879 1880#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 1881#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 1882#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 1883#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 1884 1885#define DMAE_CMD_PORT_0 0 1886#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 1887 1888#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 1889#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 1890#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 1891 1892#define DMAE_SRC_PF 0 1893#define DMAE_SRC_VF 1 1894 1895#define DMAE_DST_PF 0 1896#define DMAE_DST_VF 1 1897 1898#define DMAE_C_SRC 0 1899#define DMAE_C_DST 1 1900 1901#define DMAE_LEN32_RD_MAX 0x80 1902#define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 1903 1904#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 1905 indicates eror */ 1906 1907#define MAX_DMAE_C_PER_PORT 8 1908#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1909 BP_VN(bp)) 1910#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1911 E1HVN_MAX) 1912 1913/* PCIE link and speed */ 1914#define PCICFG_LINK_WIDTH 0x1f00000 1915#define PCICFG_LINK_WIDTH_SHIFT 20 1916#define PCICFG_LINK_SPEED 0xf0000 1917#define PCICFG_LINK_SPEED_SHIFT 16 1918 1919#define BNX2X_NUM_TESTS_SF 7 1920#define BNX2X_NUM_TESTS_MF 3 1921#define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 1922 BNX2X_NUM_TESTS_SF) 1923 1924#define BNX2X_PHY_LOOPBACK 0 1925#define BNX2X_MAC_LOOPBACK 1 1926#define BNX2X_EXT_LOOPBACK 2 1927#define BNX2X_PHY_LOOPBACK_FAILED 1 1928#define BNX2X_MAC_LOOPBACK_FAILED 2 1929#define BNX2X_EXT_LOOPBACK_FAILED 3 1930#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 1931 BNX2X_PHY_LOOPBACK_FAILED) 1932 1933 1934#define STROM_ASSERT_ARRAY_SIZE 50 1935 1936 1937/* must be used on a CID before placing it on a HW ring */ 1938#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 1939 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 1940 (x)) 1941 1942#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1943#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1944 1945 1946#define BNX2X_BTR 4 1947#define MAX_SPQ_PENDING 8 1948 1949/* CMNG constants, as derived from system spec calculations */ 1950/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 1951#define DEF_MIN_RATE 100 1952/* resolution of the rate shaping timer - 400 usec */ 1953#define RS_PERIODIC_TIMEOUT_USEC 400 1954/* number of bytes in single QM arbitration cycle - 1955 * coefficient for calculating the fairness timer */ 1956#define QM_ARB_BYTES 160000 1957/* resolution of Min algorithm 1:100 */ 1958#define MIN_RES 100 1959/* how many bytes above threshold for the minimal credit of Min algorithm*/ 1960#define MIN_ABOVE_THRESH 32768 1961/* Fairness algorithm integration time coefficient - 1962 * for calculating the actual Tfair */ 1963#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 1964/* Memory of fairness algorithm . 2 cycles */ 1965#define FAIR_MEM 2 1966 1967 1968#define ATTN_NIG_FOR_FUNC (1L << 8) 1969#define ATTN_SW_TIMER_4_FUNC (1L << 9) 1970#define GPIO_2_FUNC (1L << 10) 1971#define GPIO_3_FUNC (1L << 11) 1972#define GPIO_4_FUNC (1L << 12) 1973#define ATTN_GENERAL_ATTN_1 (1L << 13) 1974#define ATTN_GENERAL_ATTN_2 (1L << 14) 1975#define ATTN_GENERAL_ATTN_3 (1L << 15) 1976#define ATTN_GENERAL_ATTN_4 (1L << 13) 1977#define ATTN_GENERAL_ATTN_5 (1L << 14) 1978#define ATTN_GENERAL_ATTN_6 (1L << 15) 1979 1980#define ATTN_HARD_WIRED_MASK 0xff00 1981#define ATTENTION_ID 4 1982 1983 1984/* stuff added to make the code fit 80Col */ 1985 1986#define BNX2X_PMF_LINK_ASSERT \ 1987 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 1988 1989#define BNX2X_MC_ASSERT_BITS \ 1990 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1991 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1992 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1993 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 1994 1995#define BNX2X_MCP_ASSERT \ 1996 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 1997 1998#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 1999#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2000 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2001 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2002 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2003 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2004 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2005 2006#define HW_INTERRUT_ASSERT_SET_0 \ 2007 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2008 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2009 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2010 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2011#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2012 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2013 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2014 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2015 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2016 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2017 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2018#define HW_INTERRUT_ASSERT_SET_1 \ 2019 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2020 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2021 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2022 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2023 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2024 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2025 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2026 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2027 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2028 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2029 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2030#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2031 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2032 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2033 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2034 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2035 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2036 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2037 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2038 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2039 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2040 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2041 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2042 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2043 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2044 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2045 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2046#define HW_INTERRUT_ASSERT_SET_2 \ 2047 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2048 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2049 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2050 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2051 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2052#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2053 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2054 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2055 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2056 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2057 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2058 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2059 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2060 2061#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2062 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2063 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2064 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2065 2066#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2067 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2068 2069#define MULTI_MASK 0x7f 2070 2071 2072#define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2073#define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2074#define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2075#define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2076 2077#define DEF_USB_IGU_INDEX_OFF \ 2078 offsetof(struct cstorm_def_status_block_u, igu_index) 2079#define DEF_CSB_IGU_INDEX_OFF \ 2080 offsetof(struct cstorm_def_status_block_c, igu_index) 2081#define DEF_XSB_IGU_INDEX_OFF \ 2082 offsetof(struct xstorm_def_status_block, igu_index) 2083#define DEF_TSB_IGU_INDEX_OFF \ 2084 offsetof(struct tstorm_def_status_block, igu_index) 2085 2086#define DEF_USB_SEGMENT_OFF \ 2087 offsetof(struct cstorm_def_status_block_u, segment) 2088#define DEF_CSB_SEGMENT_OFF \ 2089 offsetof(struct cstorm_def_status_block_c, segment) 2090#define DEF_XSB_SEGMENT_OFF \ 2091 offsetof(struct xstorm_def_status_block, segment) 2092#define DEF_TSB_SEGMENT_OFF \ 2093 offsetof(struct tstorm_def_status_block, segment) 2094 2095#define BNX2X_SP_DSB_INDEX \ 2096 (&bp->def_status_blk->sp_sb.\ 2097 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2098 2099#define SET_FLAG(value, mask, flag) \ 2100 do {\ 2101 (value) &= ~(mask);\ 2102 (value) |= ((flag) << (mask##_SHIFT));\ 2103 } while (0) 2104 2105#define GET_FLAG(value, mask) \ 2106 (((value) & (mask)) >> (mask##_SHIFT)) 2107 2108#define GET_FIELD(value, fname) \ 2109 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2110 2111#define CAM_IS_INVALID(x) \ 2112 (GET_FLAG(x.flags, \ 2113 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2114 (T_ETH_MAC_COMMAND_INVALIDATE)) 2115 2116/* Number of u32 elements in MC hash array */ 2117#define MC_HASH_SIZE 8 2118#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2119 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2120 2121 2122#ifndef PXP2_REG_PXP2_INT_STS 2123#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2124#endif 2125 2126#ifndef ETH_MAX_RX_CLIENTS_E2 2127#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2128#endif 2129 2130#define BNX2X_VPD_LEN 128 2131#define VENDOR_ID_LEN 4 2132 2133/* Congestion management fairness mode */ 2134#define CMNG_FNS_NONE 0 2135#define CMNG_FNS_MINMAX 1 2136 2137#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2138#define HC_SEG_ACCESS_ATTN 4 2139#define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2140 2141static const u32 dmae_reg_go_c[] = { 2142 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2143 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2144 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2145 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2146}; 2147 2148void bnx2x_set_ethtool_ops(struct net_device *netdev); 2149void bnx2x_notify_link_changed(struct bnx2x *bp); 2150 2151 2152#define BNX2X_MF_SD_PROTOCOL(bp) \ 2153 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2154 2155#ifdef BCM_CNIC 2156#define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 2157 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2158 2159#define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 2160 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 2161 2162#define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 2163#define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 2164 2165#define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \ 2166 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2167 2168#define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp)) 2169#define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \ 2170 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 2171 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2172#else 2173#define IS_MF_FCOE_AFEX(bp) false 2174#endif 2175 2176 2177#endif /* bnx2x.h */ 2178