bnx2x.h revision 9dfef3adaebb42163d691be73e05b12da440cbe5
1/* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14#ifndef BNX2X_H 15#define BNX2X_H 16 17#include <linux/pci.h> 18#include <linux/netdevice.h> 19#include <linux/dma-mapping.h> 20#include <linux/types.h> 21#include <linux/pci_regs.h> 22 23/* compilation time flags */ 24 25/* define this to make the driver freeze on error to allow getting debug info 26 * (you will need to reboot afterwards) */ 27/* #define BNX2X_STOP_ON_ERROR */ 28 29#define DRV_MODULE_VERSION "1.78.17-0" 30#define DRV_MODULE_RELDATE "2013/04/11" 31#define BNX2X_BC_VER 0x040200 32 33#if defined(CONFIG_DCB) 34#define BCM_DCBNL 35#endif 36 37#include "bnx2x_hsi.h" 38 39#include "../cnic_if.h" 40 41#define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 42 43#include <linux/mdio.h> 44 45#include "bnx2x_reg.h" 46#include "bnx2x_fw_defs.h" 47#include "bnx2x_mfw_req.h" 48#include "bnx2x_link.h" 49#include "bnx2x_sp.h" 50#include "bnx2x_dcb.h" 51#include "bnx2x_stats.h" 52#include "bnx2x_vfpf.h" 53 54enum bnx2x_int_mode { 55 BNX2X_INT_MODE_MSIX, 56 BNX2X_INT_MODE_INTX, 57 BNX2X_INT_MODE_MSI 58}; 59 60/* error/debug prints */ 61 62#define DRV_MODULE_NAME "bnx2x" 63 64/* for messages that are currently off */ 65#define BNX2X_MSG_OFF 0x0 66#define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 67#define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 68#define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 69#define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 70#define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 71#define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 72#define BNX2X_MSG_IOV 0x0800000 73#define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 74#define BNX2X_MSG_ETHTOOL 0x4000000 75#define BNX2X_MSG_DCB 0x8000000 76 77/* regular debug print */ 78#define DP(__mask, fmt, ...) \ 79do { \ 80 if (unlikely(bp->msg_enable & (__mask))) \ 81 pr_notice("[%s:%d(%s)]" fmt, \ 82 __func__, __LINE__, \ 83 bp->dev ? (bp->dev->name) : "?", \ 84 ##__VA_ARGS__); \ 85} while (0) 86 87#define DP_CONT(__mask, fmt, ...) \ 88do { \ 89 if (unlikely(bp->msg_enable & (__mask))) \ 90 pr_cont(fmt, ##__VA_ARGS__); \ 91} while (0) 92 93/* errors debug print */ 94#define BNX2X_DBG_ERR(fmt, ...) \ 95do { \ 96 if (unlikely(netif_msg_probe(bp))) \ 97 pr_err("[%s:%d(%s)]" fmt, \ 98 __func__, __LINE__, \ 99 bp->dev ? (bp->dev->name) : "?", \ 100 ##__VA_ARGS__); \ 101} while (0) 102 103/* for errors (never masked) */ 104#define BNX2X_ERR(fmt, ...) \ 105do { \ 106 pr_err("[%s:%d(%s)]" fmt, \ 107 __func__, __LINE__, \ 108 bp->dev ? (bp->dev->name) : "?", \ 109 ##__VA_ARGS__); \ 110} while (0) 111 112#define BNX2X_ERROR(fmt, ...) \ 113 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 114 115/* before we have a dev->name use dev_info() */ 116#define BNX2X_DEV_INFO(fmt, ...) \ 117do { \ 118 if (unlikely(netif_msg_probe(bp))) \ 119 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 120} while (0) 121 122/* Error handling */ 123void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int); 124#ifdef BNX2X_STOP_ON_ERROR 125#define bnx2x_panic() \ 126do { \ 127 bp->panic = 1; \ 128 BNX2X_ERR("driver assert\n"); \ 129 bnx2x_panic_dump(bp, true); \ 130} while (0) 131#else 132#define bnx2x_panic() \ 133do { \ 134 bp->panic = 1; \ 135 BNX2X_ERR("driver assert\n"); \ 136 bnx2x_panic_dump(bp, false); \ 137} while (0) 138#endif 139 140#define bnx2x_mc_addr(ha) ((ha)->addr) 141#define bnx2x_uc_addr(ha) ((ha)->addr) 142 143#define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff)) 144#define U64_HI(x) ((u32)(((u64)(x)) >> 32)) 145#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 146 147#define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 148 149#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 150#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 151#define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 152 153#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 154#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 155#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 156 157#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 158#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 159 160#define REG_RD_DMAE(bp, offset, valp, len32) \ 161 do { \ 162 bnx2x_read_dmae(bp, offset, len32);\ 163 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 164 } while (0) 165 166#define REG_WR_DMAE(bp, offset, valp, len32) \ 167 do { \ 168 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 169 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 170 offset, len32); \ 171 } while (0) 172 173#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 174 REG_WR_DMAE(bp, offset, valp, len32) 175 176#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 177 do { \ 178 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 179 bnx2x_write_big_buf_wb(bp, addr, len32); \ 180 } while (0) 181 182#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 183 offsetof(struct shmem_region, field)) 184#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 185#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 186 187#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 188 offsetof(struct shmem2_region, field)) 189#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 190#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 191#define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 192 offsetof(struct mf_cfg, field)) 193#define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 194 offsetof(struct mf2_cfg, field)) 195 196#define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 197#define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 198 MF_CFG_ADDR(bp, field), (val)) 199#define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 200 201#define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 202 (SHMEM2_RD((bp), size) > \ 203 offsetof(struct shmem2_region, field))) 204 205#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 206#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 207 208/* SP SB indices */ 209 210/* General SP events - stats query, cfc delete, etc */ 211#define HC_SP_INDEX_ETH_DEF_CONS 3 212 213/* EQ completions */ 214#define HC_SP_INDEX_EQ_CONS 7 215 216/* FCoE L2 connection completions */ 217#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 218#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 219/* iSCSI L2 */ 220#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 221#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 222 223/* Special clients parameters */ 224 225/* SB indices */ 226/* FCoE L2 */ 227#define BNX2X_FCOE_L2_RX_INDEX \ 228 (&bp->def_status_blk->sp_sb.\ 229 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 230 231#define BNX2X_FCOE_L2_TX_INDEX \ 232 (&bp->def_status_blk->sp_sb.\ 233 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 234 235/** 236 * CIDs and CLIDs: 237 * CLIDs below is a CLID for func 0, then the CLID for other 238 * functions will be calculated by the formula: 239 * 240 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 241 * 242 */ 243enum { 244 BNX2X_ISCSI_ETH_CL_ID_IDX, 245 BNX2X_FCOE_ETH_CL_ID_IDX, 246 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 247}; 248 249/* use a value high enough to be above all the PFs, which has least significant 250 * nibble as 8, so when cnic needs to come up with a CID for UIO to use to 251 * calculate doorbell address according to old doorbell configuration scheme 252 * (db_msg_sz 1 << 7 * cid + 0x40 DPM offset) it can come up with a valid number 253 * We must avoid coming up with cid 8 for iscsi since according to this method 254 * the designated UIO cid will come out 0 and it has a special handling for that 255 * case which doesn't suit us. Therefore will will cieling to closes cid which 256 * has least signigifcant nibble 8 and if it is 8 we will move forward to 0x18. 257 */ 258 259#define BNX2X_1st_NON_L2_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * \ 260 (bp)->max_cos) 261/* amount of cids traversed by UIO's DPM addition to doorbell */ 262#define UIO_DPM 8 263/* roundup to DPM offset */ 264#define UIO_ROUNDUP(bp) (roundup(BNX2X_1st_NON_L2_ETH_CID(bp), \ 265 UIO_DPM)) 266/* offset to nearest value which has lsb nibble matching DPM */ 267#define UIO_CID_OFFSET(bp) ((UIO_ROUNDUP(bp) + UIO_DPM) % \ 268 (UIO_DPM * 2)) 269/* add offset to rounded-up cid to get a value which could be used with UIO */ 270#define UIO_DPM_ALIGN(bp) (UIO_ROUNDUP(bp) + UIO_CID_OFFSET(bp)) 271/* but wait - avoid UIO special case for cid 0 */ 272#define UIO_DPM_CID0_OFFSET(bp) ((UIO_DPM * 2) * \ 273 (UIO_DPM_ALIGN(bp) == UIO_DPM)) 274/* Properly DPM aligned CID dajusted to cid 0 secal case */ 275#define BNX2X_CNIC_START_ETH_CID(bp) (UIO_DPM_ALIGN(bp) + \ 276 (UIO_DPM_CID0_OFFSET(bp))) 277/* how many cids were wasted - need this value for cid allocation */ 278#define UIO_CID_PAD(bp) (BNX2X_CNIC_START_ETH_CID(bp) - \ 279 BNX2X_1st_NON_L2_ETH_CID(bp)) 280 /* iSCSI L2 */ 281#define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 282 /* FCoE L2 */ 283#define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 284 285#define CNIC_SUPPORT(bp) ((bp)->cnic_support) 286#define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 287#define CNIC_LOADED(bp) ((bp)->cnic_loaded) 288#define FCOE_INIT(bp) ((bp)->fcoe_init) 289 290#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 291 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 292 293#define SM_RX_ID 0 294#define SM_TX_ID 1 295 296/* defines for multiple tx priority indices */ 297#define FIRST_TX_ONLY_COS_INDEX 1 298#define FIRST_TX_COS_INDEX 0 299 300/* rules for calculating the cids of tx-only connections */ 301#define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 302#define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 303 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 304 305/* fp index inside class of service range */ 306#define FP_COS_TO_TXQ(fp, cos, bp) \ 307 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 308 309/* Indexes for transmission queues array: 310 * txdata for RSS i CoS j is at location i + (j * num of RSS) 311 * txdata for FCoE (if exist) is at location max cos * num of RSS 312 * txdata for FWD (if exist) is one location after FCoE 313 * txdata for OOO (if exist) is one location after FWD 314 */ 315enum { 316 FCOE_TXQ_IDX_OFFSET, 317 FWD_TXQ_IDX_OFFSET, 318 OOO_TXQ_IDX_OFFSET, 319}; 320#define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 321#define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 322 323/* fast path */ 324/* 325 * This driver uses new build_skb() API : 326 * RX ring buffer contains pointer to kmalloc() data only, 327 * skb are built only after Hardware filled the frame. 328 */ 329struct sw_rx_bd { 330 u8 *data; 331 DEFINE_DMA_UNMAP_ADDR(mapping); 332}; 333 334struct sw_tx_bd { 335 struct sk_buff *skb; 336 u16 first_bd; 337 u8 flags; 338/* Set on the first BD descriptor when there is a split BD */ 339#define BNX2X_TSO_SPLIT_BD (1<<0) 340}; 341 342struct sw_rx_page { 343 struct page *page; 344 DEFINE_DMA_UNMAP_ADDR(mapping); 345}; 346 347union db_prod { 348 struct doorbell_set_prod data; 349 u32 raw; 350}; 351 352/* dropless fc FW/HW related params */ 353#define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 354#define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 355 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 356 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 357#define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 358#define FW_PREFETCH_CNT 16 359#define DROPLESS_FC_HEADROOM 100 360 361/* MC hsi */ 362#define BCM_PAGE_SHIFT 12 363#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 364#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 365#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 366 367#define PAGES_PER_SGE_SHIFT 0 368#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 369#define SGE_PAGE_SIZE PAGE_SIZE 370#define SGE_PAGE_SHIFT PAGE_SHIFT 371#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 372#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 373#define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ 374 SGE_PAGES), 0xffff) 375 376/* SGE ring related macros */ 377#define NUM_RX_SGE_PAGES 2 378#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 379#define NEXT_PAGE_SGE_DESC_CNT 2 380#define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 381/* RX_SGE_CNT is promised to be a power of 2 */ 382#define RX_SGE_MASK (RX_SGE_CNT - 1) 383#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 384#define MAX_RX_SGE (NUM_RX_SGE - 1) 385#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 386 (MAX_RX_SGE_CNT - 1)) ? \ 387 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 388 (x) + 1) 389#define RX_SGE(x) ((x) & MAX_RX_SGE) 390 391/* 392 * Number of required SGEs is the sum of two: 393 * 1. Number of possible opened aggregations (next packet for 394 * these aggregations will probably consume SGE immediately) 395 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 396 * after placement on BD for new TPA aggregation) 397 * 398 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 399 */ 400#define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 401 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 402#define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 403 MAX_RX_SGE_CNT) 404#define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 405 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 406#define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 407 408/* Manipulate a bit vector defined as an array of u64 */ 409 410/* Number of bits in one sge_mask array element */ 411#define BIT_VEC64_ELEM_SZ 64 412#define BIT_VEC64_ELEM_SHIFT 6 413#define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 414 415#define __BIT_VEC64_SET_BIT(el, bit) \ 416 do { \ 417 el = ((el) | ((u64)0x1 << (bit))); \ 418 } while (0) 419 420#define __BIT_VEC64_CLEAR_BIT(el, bit) \ 421 do { \ 422 el = ((el) & (~((u64)0x1 << (bit)))); \ 423 } while (0) 424 425#define BIT_VEC64_SET_BIT(vec64, idx) \ 426 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 427 (idx) & BIT_VEC64_ELEM_MASK) 428 429#define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 430 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 431 (idx) & BIT_VEC64_ELEM_MASK) 432 433#define BIT_VEC64_TEST_BIT(vec64, idx) \ 434 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 435 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 436 437/* Creates a bitmask of all ones in less significant bits. 438 idx - index of the most significant bit in the created mask */ 439#define BIT_VEC64_ONES_MASK(idx) \ 440 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 441#define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 442 443/*******************************************************/ 444 445/* Number of u64 elements in SGE mask array */ 446#define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 447#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 448#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 449 450union host_hc_status_block { 451 /* pointer to fp status block e1x */ 452 struct host_hc_status_block_e1x *e1x_sb; 453 /* pointer to fp status block e2 */ 454 struct host_hc_status_block_e2 *e2_sb; 455}; 456 457struct bnx2x_agg_info { 458 /* 459 * First aggregation buffer is a data buffer, the following - are pages. 460 * We will preallocate the data buffer for each aggregation when 461 * we open the interface and will replace the BD at the consumer 462 * with this one when we receive the TPA_START CQE in order to 463 * keep the Rx BD ring consistent. 464 */ 465 struct sw_rx_bd first_buf; 466 u8 tpa_state; 467#define BNX2X_TPA_START 1 468#define BNX2X_TPA_STOP 2 469#define BNX2X_TPA_ERROR 3 470 u8 placement_offset; 471 u16 parsing_flags; 472 u16 vlan_tag; 473 u16 len_on_bd; 474 u32 rxhash; 475 bool l4_rxhash; 476 u16 gro_size; 477 u16 full_page; 478}; 479 480#define Q_STATS_OFFSET32(stat_name) \ 481 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 482 483struct bnx2x_fp_txdata { 484 485 struct sw_tx_bd *tx_buf_ring; 486 487 union eth_tx_bd_types *tx_desc_ring; 488 dma_addr_t tx_desc_mapping; 489 490 u32 cid; 491 492 union db_prod tx_db; 493 494 u16 tx_pkt_prod; 495 u16 tx_pkt_cons; 496 u16 tx_bd_prod; 497 u16 tx_bd_cons; 498 499 unsigned long tx_pkt; 500 501 __le16 *tx_cons_sb; 502 503 int txq_index; 504 struct bnx2x_fastpath *parent_fp; 505 int tx_ring_size; 506}; 507 508enum bnx2x_tpa_mode_t { 509 TPA_MODE_LRO, 510 TPA_MODE_GRO 511}; 512 513struct bnx2x_fastpath { 514 struct bnx2x *bp; /* parent */ 515 516 struct napi_struct napi; 517 518#ifdef CONFIG_NET_RX_BUSY_POLL 519 unsigned int state; 520#define BNX2X_FP_STATE_IDLE 0 521#define BNX2X_FP_STATE_NAPI (1 << 0) /* NAPI owns this FP */ 522#define BNX2X_FP_STATE_POLL (1 << 1) /* poll owns this FP */ 523#define BNX2X_FP_STATE_NAPI_YIELD (1 << 2) /* NAPI yielded this FP */ 524#define BNX2X_FP_STATE_POLL_YIELD (1 << 3) /* poll yielded this FP */ 525#define BNX2X_FP_YIELD (BNX2X_FP_STATE_NAPI_YIELD | BNX2X_FP_STATE_POLL_YIELD) 526#define BNX2X_FP_LOCKED (BNX2X_FP_STATE_NAPI | BNX2X_FP_STATE_POLL) 527#define BNX2X_FP_USER_PEND (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_POLL_YIELD) 528 /* protect state */ 529 spinlock_t lock; 530#endif /* CONFIG_NET_RX_BUSY_POLL */ 531 532 union host_hc_status_block status_blk; 533 /* chip independent shortcuts into sb structure */ 534 __le16 *sb_index_values; 535 __le16 *sb_running_index; 536 /* chip independent shortcut into rx_prods_offset memory */ 537 u32 ustorm_rx_prods_offset; 538 539 u32 rx_buf_size; 540 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 541 dma_addr_t status_blk_mapping; 542 543 enum bnx2x_tpa_mode_t mode; 544 545 u8 max_cos; /* actual number of active tx coses */ 546 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 547 548 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 549 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 550 551 struct eth_rx_bd *rx_desc_ring; 552 dma_addr_t rx_desc_mapping; 553 554 union eth_rx_cqe *rx_comp_ring; 555 dma_addr_t rx_comp_mapping; 556 557 /* SGE ring */ 558 struct eth_rx_sge *rx_sge_ring; 559 dma_addr_t rx_sge_mapping; 560 561 u64 sge_mask[RX_SGE_MASK_LEN]; 562 563 u32 cid; 564 565 __le16 fp_hc_idx; 566 567 u8 index; /* number in fp array */ 568 u8 rx_queue; /* index for skb_record */ 569 u8 cl_id; /* eth client id */ 570 u8 cl_qzone_id; 571 u8 fw_sb_id; /* status block number in FW */ 572 u8 igu_sb_id; /* status block number in HW */ 573 574 u16 rx_bd_prod; 575 u16 rx_bd_cons; 576 u16 rx_comp_prod; 577 u16 rx_comp_cons; 578 u16 rx_sge_prod; 579 /* The last maximal completed SGE */ 580 u16 last_max_sge; 581 __le16 *rx_cons_sb; 582 unsigned long rx_pkt, 583 rx_calls; 584 585 /* TPA related */ 586 struct bnx2x_agg_info *tpa_info; 587 u8 disable_tpa; 588#ifdef BNX2X_STOP_ON_ERROR 589 u64 tpa_queue_used; 590#endif 591 /* The size is calculated using the following: 592 sizeof name field from netdev structure + 593 4 ('-Xx-' string) + 594 4 (for the digits and to make it DWORD aligned) */ 595#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 596 char name[FP_NAME_SIZE]; 597}; 598 599#define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 600#define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 601#define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 602#define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 603 604#ifdef CONFIG_NET_RX_BUSY_POLL 605static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp) 606{ 607 spin_lock_init(&fp->lock); 608 fp->state = BNX2X_FP_STATE_IDLE; 609} 610 611/* called from the device poll routine to get ownership of a FP */ 612static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 613{ 614 bool rc = true; 615 616 spin_lock(&fp->lock); 617 if (fp->state & BNX2X_FP_LOCKED) { 618 WARN_ON(fp->state & BNX2X_FP_STATE_NAPI); 619 fp->state |= BNX2X_FP_STATE_NAPI_YIELD; 620 rc = false; 621 } else { 622 /* we don't care if someone yielded */ 623 fp->state = BNX2X_FP_STATE_NAPI; 624 } 625 spin_unlock(&fp->lock); 626 return rc; 627} 628 629/* returns true is someone tried to get the FP while napi had it */ 630static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 631{ 632 bool rc = false; 633 634 spin_lock(&fp->lock); 635 WARN_ON(fp->state & 636 (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_NAPI_YIELD)); 637 638 if (fp->state & BNX2X_FP_STATE_POLL_YIELD) 639 rc = true; 640 fp->state = BNX2X_FP_STATE_IDLE; 641 spin_unlock(&fp->lock); 642 return rc; 643} 644 645/* called from bnx2x_low_latency_poll() */ 646static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 647{ 648 bool rc = true; 649 650 spin_lock_bh(&fp->lock); 651 if ((fp->state & BNX2X_FP_LOCKED)) { 652 fp->state |= BNX2X_FP_STATE_POLL_YIELD; 653 rc = false; 654 } else { 655 /* preserve yield marks */ 656 fp->state |= BNX2X_FP_STATE_POLL; 657 } 658 spin_unlock_bh(&fp->lock); 659 return rc; 660} 661 662/* returns true if someone tried to get the FP while it was locked */ 663static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 664{ 665 bool rc = false; 666 667 spin_lock_bh(&fp->lock); 668 WARN_ON(fp->state & BNX2X_FP_STATE_NAPI); 669 670 if (fp->state & BNX2X_FP_STATE_POLL_YIELD) 671 rc = true; 672 fp->state = BNX2X_FP_STATE_IDLE; 673 spin_unlock_bh(&fp->lock); 674 return rc; 675} 676 677/* true if a socket is polling, even if it did not get the lock */ 678static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 679{ 680 WARN_ON(!(fp->state & BNX2X_FP_LOCKED)); 681 return fp->state & BNX2X_FP_USER_PEND; 682} 683#else 684static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp) 685{ 686} 687 688static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp) 689{ 690 return true; 691} 692 693static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp) 694{ 695 return false; 696} 697 698static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp) 699{ 700 return false; 701} 702 703static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp) 704{ 705 return false; 706} 707 708static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp) 709{ 710 return false; 711} 712#endif /* CONFIG_NET_RX_BUSY_POLL */ 713 714/* Use 2500 as a mini-jumbo MTU for FCoE */ 715#define BNX2X_FCOE_MINI_JUMBO_MTU 2500 716 717#define FCOE_IDX_OFFSET 0 718 719#define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 720 FCOE_IDX_OFFSET) 721#define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 722#define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 723#define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 724#define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 725#define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 726 txdata_ptr[FIRST_TX_COS_INDEX] \ 727 ->var) 728 729#define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 730#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 731#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 732 733/* MC hsi */ 734#define MAX_FETCH_BD 13 /* HW max BDs per packet */ 735#define RX_COPY_THRESH 92 736 737#define NUM_TX_RINGS 16 738#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 739#define NEXT_PAGE_TX_DESC_CNT 1 740#define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 741#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 742#define MAX_TX_BD (NUM_TX_BD - 1) 743#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 744#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 745 (MAX_TX_DESC_CNT - 1)) ? \ 746 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 747 (x) + 1) 748#define TX_BD(x) ((x) & MAX_TX_BD) 749#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 750 751/* number of NEXT_PAGE descriptors may be required during placement */ 752#define NEXT_CNT_PER_TX_PKT(bds) \ 753 (((bds) + MAX_TX_DESC_CNT - 1) / \ 754 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 755/* max BDs per tx packet w/o next_pages: 756 * START_BD - describes packed 757 * START_BD(splitted) - includes unpaged data segment for GSO 758 * PARSING_BD - for TSO and CSUM data 759 * PARSING_BD2 - for encapsulation data 760 * Frag BDs - describes pages for frags 761 */ 762#define BDS_PER_TX_PKT 4 763#define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 764/* max BDs per tx packet including next pages */ 765#define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 766 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 767 768/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 769#define NUM_RX_RINGS 8 770#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 771#define NEXT_PAGE_RX_DESC_CNT 2 772#define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 773#define RX_DESC_MASK (RX_DESC_CNT - 1) 774#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 775#define MAX_RX_BD (NUM_RX_BD - 1) 776#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 777 778/* dropless fc calculations for BDs 779 * 780 * Number of BDs should as number of buffers in BRB: 781 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 782 * "next" elements on each page 783 */ 784#define NUM_BD_REQ BRB_SIZE(bp) 785#define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 786 MAX_RX_DESC_CNT) 787#define BD_TH_LO(bp) (NUM_BD_REQ + \ 788 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 789 FW_DROP_LEVEL(bp)) 790#define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 791 792#define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 793 794#define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 795 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 796 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 797#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 798#define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 799#define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 800 MIN_RX_AVAIL)) 801 802#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 803 (MAX_RX_DESC_CNT - 1)) ? \ 804 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 805 (x) + 1) 806#define RX_BD(x) ((x) & MAX_RX_BD) 807 808/* 809 * As long as CQE is X times bigger than BD entry we have to allocate X times 810 * more pages for CQ ring in order to keep it balanced with BD ring 811 */ 812#define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 813#define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 814#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 815#define NEXT_PAGE_RCQ_DESC_CNT 1 816#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 817#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 818#define MAX_RCQ_BD (NUM_RCQ_BD - 1) 819#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 820#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 821 (MAX_RCQ_DESC_CNT - 1)) ? \ 822 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 823 (x) + 1) 824#define RCQ_BD(x) ((x) & MAX_RCQ_BD) 825 826/* dropless fc calculations for RCQs 827 * 828 * Number of RCQs should be as number of buffers in BRB: 829 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 830 * "next" elements on each page 831 */ 832#define NUM_RCQ_REQ BRB_SIZE(bp) 833#define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 834 MAX_RCQ_DESC_CNT) 835#define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 836 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 837 FW_DROP_LEVEL(bp)) 838#define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 839 840/* This is needed for determining of last_max */ 841#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 842#define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 843 844#define BNX2X_SWCID_SHIFT 17 845#define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 846 847/* used on a CID received from the HW */ 848#define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 849#define CQE_CMD(x) (le32_to_cpu(x) >> \ 850 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 851 852#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 853 le32_to_cpu((bd)->addr_lo)) 854#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 855 856#define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 857#define BNX2X_DB_SHIFT 3 /* 8 bytes*/ 858#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 859#error "Min DB doorbell stride is 8" 860#endif 861#define DOORBELL(bp, cid, val) \ 862 do { \ 863 writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \ 864 } while (0) 865 866/* TX CSUM helpers */ 867#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 868 skb->csum_offset) 869#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 870 skb->csum_offset)) 871 872#define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff) 873 874#define XMIT_PLAIN 0 875#define XMIT_CSUM_V4 (1 << 0) 876#define XMIT_CSUM_V6 (1 << 1) 877#define XMIT_CSUM_TCP (1 << 2) 878#define XMIT_GSO_V4 (1 << 3) 879#define XMIT_GSO_V6 (1 << 4) 880#define XMIT_CSUM_ENC_V4 (1 << 5) 881#define XMIT_CSUM_ENC_V6 (1 << 6) 882#define XMIT_GSO_ENC_V4 (1 << 7) 883#define XMIT_GSO_ENC_V6 (1 << 8) 884 885#define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6) 886#define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6) 887 888#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC) 889#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC) 890 891/* stuff added to make the code fit 80Col */ 892#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 893#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 894#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 895#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 896#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 897 898#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 899 900#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 901 (((le16_to_cpu(flags) & \ 902 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 903 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 904 == PRS_FLAG_OVERETH_IPV4) 905#define BNX2X_RX_SUM_FIX(cqe) \ 906 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 907 908#define FP_USB_FUNC_OFF \ 909 offsetof(struct cstorm_status_block_u, func) 910#define FP_CSB_FUNC_OFF \ 911 offsetof(struct cstorm_status_block_c, func) 912 913#define HC_INDEX_ETH_RX_CQ_CONS 1 914 915#define HC_INDEX_OOO_TX_CQ_CONS 4 916 917#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 918 919#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 920 921#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 922 923#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 924 925#define BNX2X_RX_SB_INDEX \ 926 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 927 928#define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 929 930#define BNX2X_TX_SB_INDEX_COS0 \ 931 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 932 933/* end of fast path */ 934 935/* common */ 936 937struct bnx2x_common { 938 939 u32 chip_id; 940/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 941#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 942 943#define CHIP_NUM(bp) (bp->common.chip_id >> 16) 944#define CHIP_NUM_57710 0x164e 945#define CHIP_NUM_57711 0x164f 946#define CHIP_NUM_57711E 0x1650 947#define CHIP_NUM_57712 0x1662 948#define CHIP_NUM_57712_MF 0x1663 949#define CHIP_NUM_57712_VF 0x166f 950#define CHIP_NUM_57713 0x1651 951#define CHIP_NUM_57713E 0x1652 952#define CHIP_NUM_57800 0x168a 953#define CHIP_NUM_57800_MF 0x16a5 954#define CHIP_NUM_57800_VF 0x16a9 955#define CHIP_NUM_57810 0x168e 956#define CHIP_NUM_57810_MF 0x16ae 957#define CHIP_NUM_57810_VF 0x16af 958#define CHIP_NUM_57811 0x163d 959#define CHIP_NUM_57811_MF 0x163e 960#define CHIP_NUM_57811_VF 0x163f 961#define CHIP_NUM_57840_OBSOLETE 0x168d 962#define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 963#define CHIP_NUM_57840_4_10 0x16a1 964#define CHIP_NUM_57840_2_20 0x16a2 965#define CHIP_NUM_57840_MF 0x16a4 966#define CHIP_NUM_57840_VF 0x16ad 967#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 968#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 969#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 970#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 971#define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF) 972#define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 973#define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 974#define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 975#define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF) 976#define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 977#define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 978#define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF) 979#define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 980#define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 981#define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF) 982#define CHIP_IS_57840(bp) \ 983 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 984 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 985 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 986#define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 987 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 988#define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF) 989#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 990 CHIP_IS_57711E(bp)) 991#define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \ 992 CHIP_IS_57811_MF(bp) || \ 993 CHIP_IS_57811_VF(bp)) 994#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 995 CHIP_IS_57712_MF(bp) || \ 996 CHIP_IS_57712_VF(bp)) 997#define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 998 CHIP_IS_57800_MF(bp) || \ 999 CHIP_IS_57800_VF(bp) || \ 1000 CHIP_IS_57810(bp) || \ 1001 CHIP_IS_57810_MF(bp) || \ 1002 CHIP_IS_57810_VF(bp) || \ 1003 CHIP_IS_57811xx(bp) || \ 1004 CHIP_IS_57840(bp) || \ 1005 CHIP_IS_57840_MF(bp) || \ 1006 CHIP_IS_57840_VF(bp)) 1007#define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 1008#define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 1009#define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 1010 1011#define CHIP_REV_SHIFT 12 1012#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1013#define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 1014#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1015#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1016/* assume maximum 5 revisions */ 1017#define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 1018/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 1019#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1020 !(CHIP_REV_VAL(bp) & 0x00001000)) 1021/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 1022#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 1023 (CHIP_REV_VAL(bp) & 0x00001000)) 1024 1025#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 1026 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 1027 1028#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 1029#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 1030#define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 1031 (CHIP_REV_SHIFT + 1)) \ 1032 << CHIP_REV_SHIFT) 1033#define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 1034 CHIP_REV_SIM(bp) :\ 1035 CHIP_REV_VAL(bp)) 1036#define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 1037 (CHIP_REV(bp) == CHIP_REV_Bx)) 1038#define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 1039 (CHIP_REV(bp) == CHIP_REV_Ax)) 1040/* This define is used in two main places: 1041 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher 1042 * to nic-only mode or to offload mode. Offload mode is configured if either the 1043 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 1044 * registered for this port (which means that the user wants storage services). 1045 * 2. During cnic-related load, to know if offload mode is already configured in 1046 * the HW or needs to be configured. 1047 * Since the transition from nic-mode to offload-mode in HW causes traffic 1048 * corruption, nic-mode is configured only in ports on which storage services 1049 * where never requested. 1050 */ 1051#define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 1052 1053 int flash_size; 1054#define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 1055#define BNX2X_NVRAM_TIMEOUT_COUNT 30000 1056#define BNX2X_NVRAM_PAGE_SIZE 256 1057 1058 u32 shmem_base; 1059 u32 shmem2_base; 1060 u32 mf_cfg_base; 1061 u32 mf2_cfg_base; 1062 1063 u32 hw_config; 1064 1065 u32 bc_ver; 1066 1067 u8 int_block; 1068#define INT_BLOCK_HC 0 1069#define INT_BLOCK_IGU 1 1070#define INT_BLOCK_MODE_NORMAL 0 1071#define INT_BLOCK_MODE_BW_COMP 2 1072#define CHIP_INT_MODE_IS_NBC(bp) \ 1073 (!CHIP_IS_E1x(bp) && \ 1074 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 1075#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 1076 1077 u8 chip_port_mode; 1078#define CHIP_4_PORT_MODE 0x0 1079#define CHIP_2_PORT_MODE 0x1 1080#define CHIP_PORT_MODE_NONE 0x2 1081#define CHIP_MODE(bp) (bp->common.chip_port_mode) 1082#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 1083 1084 u32 boot_mode; 1085}; 1086 1087/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 1088#define BNX2X_IGU_STAS_MSG_VF_CNT 64 1089#define BNX2X_IGU_STAS_MSG_PF_CNT 4 1090 1091#define MAX_IGU_ATTN_ACK_TO 100 1092/* end of common */ 1093 1094/* port */ 1095 1096struct bnx2x_port { 1097 u32 pmf; 1098 1099 u32 link_config[LINK_CONFIG_SIZE]; 1100 1101 u32 supported[LINK_CONFIG_SIZE]; 1102/* link settings - missing defines */ 1103#define SUPPORTED_2500baseX_Full (1 << 15) 1104 1105 u32 advertising[LINK_CONFIG_SIZE]; 1106/* link settings - missing defines */ 1107#define ADVERTISED_2500baseX_Full (1 << 15) 1108 1109 u32 phy_addr; 1110 1111 /* used to synchronize phy accesses */ 1112 struct mutex phy_mutex; 1113 1114 u32 port_stx; 1115 1116 struct nig_stats old_nig_stats; 1117}; 1118 1119/* end of port */ 1120 1121#define STATS_OFFSET32(stat_name) \ 1122 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 1123 1124/* slow path */ 1125 1126/* slow path work-queue */ 1127extern struct workqueue_struct *bnx2x_wq; 1128 1129#define BNX2X_MAX_NUM_OF_VFS 64 1130#define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */ 1131#define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 1132 1133/* We need to reserve doorbell addresses for all VF and queue combinations */ 1134#define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 1135 1136/* The doorbell is configured to have the same number of CIDs for PFs and for 1137 * VFs. For this reason the PF CID zone is as large as the VF zone. 1138 */ 1139#define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS 1140#define BNX2X_MAX_NUM_VF_QUEUES 64 1141#define BNX2X_VF_ID_INVALID 0xFF 1142 1143/* the number of VF CIDS multiplied by the amount of bytes reserved for each 1144 * cid must not exceed the size of the VF doorbell 1145 */ 1146#define BNX2X_VF_BAR_SIZE 512 1147#if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT)) 1148#error "VF doorbell bar size is 512" 1149#endif 1150 1151/* 1152 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 1153 * control by the number of fast-path status blocks supported by the 1154 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 1155 * status block represents an independent interrupts context that can 1156 * serve a regular L2 networking queue. However special L2 queues such 1157 * as the FCoE queue do not require a FP-SB and other components like 1158 * the CNIC may consume FP-SB reducing the number of possible L2 queues 1159 * 1160 * If the maximum number of FP-SB available is X then: 1161 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 1162 * regular L2 queues is Y=X-1 1163 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 1164 * c. If the FCoE L2 queue is supported the actual number of L2 queues 1165 * is Y+1 1166 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 1167 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 1168 * FP interrupt context for the CNIC). 1169 * e. The number of HW context (CID count) is always X or X+1 if FCoE 1170 * L2 queue is supported. The cid for the FCoE L2 queue is always X. 1171 */ 1172 1173/* fast-path interrupt contexts E1x */ 1174#define FP_SB_MAX_E1x 16 1175/* fast-path interrupt contexts E2 */ 1176#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 1177 1178union cdu_context { 1179 struct eth_context eth; 1180 char pad[1024]; 1181}; 1182 1183/* CDU host DB constants */ 1184#define CDU_ILT_PAGE_SZ_HW 2 1185#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1186#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1187 1188#define CNIC_ISCSI_CID_MAX 256 1189#define CNIC_FCOE_CID_MAX 2048 1190#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1191#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1192 1193#define QM_ILT_PAGE_SZ_HW 0 1194#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1195#define QM_CID_ROUND 1024 1196 1197/* TM (timers) host DB constants */ 1198#define TM_ILT_PAGE_SZ_HW 0 1199#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1200#define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \ 1201 BNX2X_VF_CIDS + \ 1202 CNIC_ISCSI_CID_MAX) 1203#define TM_ILT_SZ (8 * TM_CONN_NUM) 1204#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1205 1206/* SRC (Searcher) host DB constants */ 1207#define SRC_ILT_PAGE_SZ_HW 0 1208#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1209#define SRC_HASH_BITS 10 1210#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1211#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1212#define SRC_T2_SZ SRC_ILT_SZ 1213#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1214 1215#define MAX_DMAE_C 8 1216 1217/* DMA memory not used in fastpath */ 1218struct bnx2x_slowpath { 1219 union { 1220 struct mac_configuration_cmd e1x; 1221 struct eth_classify_rules_ramrod_data e2; 1222 } mac_rdata; 1223 1224 union { 1225 struct tstorm_eth_mac_filter_config e1x; 1226 struct eth_filter_rules_ramrod_data e2; 1227 } rx_mode_rdata; 1228 1229 union { 1230 struct mac_configuration_cmd e1; 1231 struct eth_multicast_rules_ramrod_data e2; 1232 } mcast_rdata; 1233 1234 struct eth_rss_update_ramrod_data rss_rdata; 1235 1236 /* Queue State related ramrods are always sent under rtnl_lock */ 1237 union { 1238 struct client_init_ramrod_data init_data; 1239 struct client_update_ramrod_data update_data; 1240 } q_rdata; 1241 1242 union { 1243 struct function_start_data func_start; 1244 /* pfc configuration for DCBX ramrod */ 1245 struct flow_control_configuration pfc_config; 1246 } func_rdata; 1247 1248 /* afex ramrod can not be a part of func_rdata union because these 1249 * events might arrive in parallel to other events from func_rdata. 1250 * Therefore, if they would have been defined in the same union, 1251 * data can get corrupted. 1252 */ 1253 union { 1254 struct afex_vif_list_ramrod_data viflist_data; 1255 struct function_update_data func_update; 1256 } func_afex_rdata; 1257 1258 /* used by dmae command executer */ 1259 struct dmae_command dmae[MAX_DMAE_C]; 1260 1261 u32 stats_comp; 1262 union mac_stats mac_stats; 1263 struct nig_stats nig_stats; 1264 struct host_port_stats port_stats; 1265 struct host_func_stats func_stats; 1266 1267 u32 wb_comp; 1268 u32 wb_data[4]; 1269 1270 union drv_info_to_mcp drv_info_to_mcp; 1271}; 1272 1273#define bnx2x_sp(bp, var) (&bp->slowpath->var) 1274#define bnx2x_sp_mapping(bp, var) \ 1275 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1276 1277/* attn group wiring */ 1278#define MAX_DYNAMIC_ATTN_GRPS 8 1279 1280struct attn_route { 1281 u32 sig[5]; 1282}; 1283 1284struct iro { 1285 u32 base; 1286 u16 m1; 1287 u16 m2; 1288 u16 m3; 1289 u16 size; 1290}; 1291 1292struct hw_context { 1293 union cdu_context *vcxt; 1294 dma_addr_t cxt_mapping; 1295 size_t size; 1296}; 1297 1298/* forward */ 1299struct bnx2x_ilt; 1300 1301struct bnx2x_vfdb; 1302 1303enum bnx2x_recovery_state { 1304 BNX2X_RECOVERY_DONE, 1305 BNX2X_RECOVERY_INIT, 1306 BNX2X_RECOVERY_WAIT, 1307 BNX2X_RECOVERY_FAILED, 1308 BNX2X_RECOVERY_NIC_LOADING 1309}; 1310 1311/* 1312 * Event queue (EQ or event ring) MC hsi 1313 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1314 */ 1315#define NUM_EQ_PAGES 1 1316#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1317#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1318#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1319#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1320#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1321 1322/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1323#define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1324 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1325 1326/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1327#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1328 1329#define BNX2X_EQ_INDEX \ 1330 (&bp->def_status_blk->sp_sb.\ 1331 index_values[HC_SP_INDEX_EQ_CONS]) 1332 1333/* This is a data that will be used to create a link report message. 1334 * We will keep the data used for the last link report in order 1335 * to prevent reporting the same link parameters twice. 1336 */ 1337struct bnx2x_link_report_data { 1338 u16 line_speed; /* Effective line speed */ 1339 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1340}; 1341 1342enum { 1343 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1344 BNX2X_LINK_REPORT_LINK_DOWN, 1345 BNX2X_LINK_REPORT_RX_FC_ON, 1346 BNX2X_LINK_REPORT_TX_FC_ON, 1347}; 1348 1349enum { 1350 BNX2X_PORT_QUERY_IDX, 1351 BNX2X_PF_QUERY_IDX, 1352 BNX2X_FCOE_QUERY_IDX, 1353 BNX2X_FIRST_QUEUE_QUERY_IDX, 1354}; 1355 1356struct bnx2x_fw_stats_req { 1357 struct stats_query_header hdr; 1358 struct stats_query_entry query[FP_SB_MAX_E1x+ 1359 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1360}; 1361 1362struct bnx2x_fw_stats_data { 1363 struct stats_counter storm_counters; 1364 struct per_port_stats port; 1365 struct per_pf_stats pf; 1366 struct fcoe_statistics_params fcoe; 1367 struct per_queue_stats queue_stats[1]; 1368}; 1369 1370/* Public slow path states */ 1371enum { 1372 BNX2X_SP_RTNL_SETUP_TC, 1373 BNX2X_SP_RTNL_TX_TIMEOUT, 1374 BNX2X_SP_RTNL_FAN_FAILURE, 1375 BNX2X_SP_RTNL_AFEX_F_UPDATE, 1376 BNX2X_SP_RTNL_ENABLE_SRIOV, 1377 BNX2X_SP_RTNL_VFPF_MCAST, 1378 BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN, 1379 BNX2X_SP_RTNL_RX_MODE, 1380 BNX2X_SP_RTNL_HYPERVISOR_VLAN, 1381 BNX2X_SP_RTNL_TX_STOP, 1382}; 1383 1384struct bnx2x_prev_path_list { 1385 struct list_head list; 1386 u8 bus; 1387 u8 slot; 1388 u8 path; 1389 u8 aer; 1390 u8 undi; 1391}; 1392 1393struct bnx2x_sp_objs { 1394 /* MACs object */ 1395 struct bnx2x_vlan_mac_obj mac_obj; 1396 1397 /* Queue State object */ 1398 struct bnx2x_queue_sp_obj q_obj; 1399}; 1400 1401struct bnx2x_fp_stats { 1402 struct tstorm_per_queue_stats old_tclient; 1403 struct ustorm_per_queue_stats old_uclient; 1404 struct xstorm_per_queue_stats old_xclient; 1405 struct bnx2x_eth_q_stats eth_q_stats; 1406 struct bnx2x_eth_q_stats_old eth_q_stats_old; 1407}; 1408 1409struct bnx2x { 1410 /* Fields used in the tx and intr/napi performance paths 1411 * are grouped together in the beginning of the structure 1412 */ 1413 struct bnx2x_fastpath *fp; 1414 struct bnx2x_sp_objs *sp_objs; 1415 struct bnx2x_fp_stats *fp_stats; 1416 struct bnx2x_fp_txdata *bnx2x_txq; 1417 void __iomem *regview; 1418 void __iomem *doorbells; 1419 u16 db_size; 1420 1421 u8 pf_num; /* absolute PF number */ 1422 u8 pfid; /* per-path PF number */ 1423 int base_fw_ndsb; /**/ 1424#define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1425#define BP_PORT(bp) (bp->pfid & 1) 1426#define BP_FUNC(bp) (bp->pfid) 1427#define BP_ABS_FUNC(bp) (bp->pf_num) 1428#define BP_VN(bp) ((bp)->pfid >> 1) 1429#define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1430#define BP_L_ID(bp) (BP_VN(bp) << 2) 1431#define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1432 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1433#define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1434 1435#ifdef CONFIG_BNX2X_SRIOV 1436 /* protects vf2pf mailbox from simultaneous access */ 1437 struct mutex vf2pf_mutex; 1438 /* vf pf channel mailbox contains request and response buffers */ 1439 struct bnx2x_vf_mbx_msg *vf2pf_mbox; 1440 dma_addr_t vf2pf_mbox_mapping; 1441 1442 /* we set aside a copy of the acquire response */ 1443 struct pfvf_acquire_resp_tlv acquire_resp; 1444 1445 /* bulletin board for messages from pf to vf */ 1446 union pf_vf_bulletin *pf2vf_bulletin; 1447 dma_addr_t pf2vf_bulletin_mapping; 1448 1449 struct pf_vf_bulletin_content old_bulletin; 1450 1451 u16 requested_nr_virtfn; 1452#endif /* CONFIG_BNX2X_SRIOV */ 1453 1454 struct net_device *dev; 1455 struct pci_dev *pdev; 1456 1457 const struct iro *iro_arr; 1458#define IRO (bp->iro_arr) 1459 1460 enum bnx2x_recovery_state recovery_state; 1461 int is_leader; 1462 struct msix_entry *msix_table; 1463 1464 int tx_ring_size; 1465 1466/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1467#define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1468#define ETH_MIN_PACKET_SIZE 60 1469#define ETH_MAX_PACKET_SIZE 1500 1470#define ETH_MAX_JUMBO_PACKET_SIZE 9600 1471/* TCP with Timestamp Option (32) + IPv6 (40) */ 1472#define ETH_MAX_TPA_HEADER_SIZE 72 1473 1474 /* Max supported alignment is 256 (8 shift) */ 1475#define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1476 1477 /* FW uses 2 Cache lines Alignment for start packet and size 1478 * 1479 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1480 * at the end of skb->data, to avoid wasting a full cache line. 1481 * This reduces memory use (skb->truesize). 1482 */ 1483#define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1484 1485#define BNX2X_FW_RX_ALIGN_END \ 1486 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1487 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1488 1489#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1490 1491 struct host_sp_status_block *def_status_blk; 1492#define DEF_SB_IGU_ID 16 1493#define DEF_SB_ID HC_SP_SB_ID 1494 __le16 def_idx; 1495 __le16 def_att_idx; 1496 u32 attn_state; 1497 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1498 1499 /* slow path ring */ 1500 struct eth_spe *spq; 1501 dma_addr_t spq_mapping; 1502 u16 spq_prod_idx; 1503 struct eth_spe *spq_prod_bd; 1504 struct eth_spe *spq_last_bd; 1505 __le16 *dsb_sp_prod; 1506 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1507 /* used to synchronize spq accesses */ 1508 spinlock_t spq_lock; 1509 1510 /* event queue */ 1511 union event_ring_elem *eq_ring; 1512 dma_addr_t eq_mapping; 1513 u16 eq_prod; 1514 u16 eq_cons; 1515 __le16 *eq_cons_sb; 1516 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1517 1518 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1519 u16 stats_pending; 1520 /* Counter for completed statistics ramrods */ 1521 u16 stats_comp; 1522 1523 /* End of fields used in the performance code paths */ 1524 1525 int panic; 1526 int msg_enable; 1527 1528 u32 flags; 1529#define PCIX_FLAG (1 << 0) 1530#define PCI_32BIT_FLAG (1 << 1) 1531#define ONE_PORT_FLAG (1 << 2) 1532#define NO_WOL_FLAG (1 << 3) 1533#define USING_MSIX_FLAG (1 << 5) 1534#define USING_MSI_FLAG (1 << 6) 1535#define DISABLE_MSI_FLAG (1 << 7) 1536#define TPA_ENABLE_FLAG (1 << 8) 1537#define NO_MCP_FLAG (1 << 9) 1538#define GRO_ENABLE_FLAG (1 << 10) 1539#define MF_FUNC_DIS (1 << 11) 1540#define OWN_CNIC_IRQ (1 << 12) 1541#define NO_ISCSI_OOO_FLAG (1 << 13) 1542#define NO_ISCSI_FLAG (1 << 14) 1543#define NO_FCOE_FLAG (1 << 15) 1544#define BC_SUPPORTS_PFC_STATS (1 << 17) 1545#define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 1546#define USING_SINGLE_MSIX_FLAG (1 << 20) 1547#define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 1548#define IS_VF_FLAG (1 << 22) 1549#define INTERRUPTS_ENABLED_FLAG (1 << 23) 1550#define BC_SUPPORTS_RMMOD_CMD (1 << 24) 1551#define HAS_PHYS_PORT_ID (1 << 25) 1552 1553#define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 1554 1555#ifdef CONFIG_BNX2X_SRIOV 1556#define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 1557#define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 1558#else 1559#define IS_VF(bp) false 1560#define IS_PF(bp) true 1561#endif 1562 1563#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1564#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1565#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1566 1567 u8 cnic_support; 1568 bool cnic_enabled; 1569 bool cnic_loaded; 1570 struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 1571 1572 /* Flag that indicates that we can start looking for FCoE L2 queue 1573 * completions in the default status block. 1574 */ 1575 bool fcoe_init; 1576 1577 int mrrs; 1578 1579 struct delayed_work sp_task; 1580 atomic_t interrupt_occurred; 1581 struct delayed_work sp_rtnl_task; 1582 1583 struct delayed_work period_task; 1584 struct timer_list timer; 1585 int current_interval; 1586 1587 u16 fw_seq; 1588 u16 fw_drv_pulse_wr_seq; 1589 u32 func_stx; 1590 1591 struct link_params link_params; 1592 struct link_vars link_vars; 1593 u32 link_cnt; 1594 struct bnx2x_link_report_data last_reported_link; 1595 1596 struct mdio_if_info mdio; 1597 1598 struct bnx2x_common common; 1599 struct bnx2x_port port; 1600 1601 struct cmng_init cmng; 1602 1603 u32 mf_config[E1HVN_MAX]; 1604 u32 mf_ext_config; 1605 u32 path_has_ovlan; /* E3 */ 1606 u16 mf_ov; 1607 u8 mf_mode; 1608#define IS_MF(bp) (bp->mf_mode != 0) 1609#define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1610#define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1611#define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1612 1613 u8 wol; 1614 1615 int rx_ring_size; 1616 1617 u16 tx_quick_cons_trip_int; 1618 u16 tx_quick_cons_trip; 1619 u16 tx_ticks_int; 1620 u16 tx_ticks; 1621 1622 u16 rx_quick_cons_trip_int; 1623 u16 rx_quick_cons_trip; 1624 u16 rx_ticks_int; 1625 u16 rx_ticks; 1626/* Maximal coalescing timeout in us */ 1627#define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR) 1628 1629 u32 lin_cnt; 1630 1631 u16 state; 1632#define BNX2X_STATE_CLOSED 0 1633#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1634#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1635#define BNX2X_STATE_OPEN 0x3000 1636#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1637#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1638 1639#define BNX2X_STATE_DIAG 0xe000 1640#define BNX2X_STATE_ERROR 0xf000 1641 1642#define BNX2X_MAX_PRIORITY 8 1643#define BNX2X_MAX_ENTRIES_PER_PRI 16 1644#define BNX2X_MAX_COS 3 1645#define BNX2X_MAX_TX_COS 2 1646 int num_queues; 1647 uint num_ethernet_queues; 1648 uint num_cnic_queues; 1649 int num_napi_queues; 1650 int disable_tpa; 1651 1652 u32 rx_mode; 1653#define BNX2X_RX_MODE_NONE 0 1654#define BNX2X_RX_MODE_NORMAL 1 1655#define BNX2X_RX_MODE_ALLMULTI 2 1656#define BNX2X_RX_MODE_PROMISC 3 1657#define BNX2X_MAX_MULTICAST 64 1658 1659 u8 igu_dsb_id; 1660 u8 igu_base_sb; 1661 u8 igu_sb_cnt; 1662 u8 min_msix_vec_cnt; 1663 1664 u32 igu_base_addr; 1665 dma_addr_t def_status_blk_mapping; 1666 1667 struct bnx2x_slowpath *slowpath; 1668 dma_addr_t slowpath_mapping; 1669 1670 /* Total number of FW statistics requests */ 1671 u8 fw_stats_num; 1672 1673 /* 1674 * This is a memory buffer that will contain both statistics 1675 * ramrod request and data. 1676 */ 1677 void *fw_stats; 1678 dma_addr_t fw_stats_mapping; 1679 1680 /* 1681 * FW statistics request shortcut (points at the 1682 * beginning of fw_stats buffer). 1683 */ 1684 struct bnx2x_fw_stats_req *fw_stats_req; 1685 dma_addr_t fw_stats_req_mapping; 1686 int fw_stats_req_sz; 1687 1688 /* 1689 * FW statistics data shortcut (points at the beginning of 1690 * fw_stats buffer + fw_stats_req_sz). 1691 */ 1692 struct bnx2x_fw_stats_data *fw_stats_data; 1693 dma_addr_t fw_stats_data_mapping; 1694 int fw_stats_data_sz; 1695 1696 /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB 1697 * context size we need 8 ILT entries. 1698 */ 1699#define ILT_MAX_L2_LINES 32 1700 struct hw_context context[ILT_MAX_L2_LINES]; 1701 1702 struct bnx2x_ilt *ilt; 1703#define BP_ILT(bp) ((bp)->ilt) 1704#define ILT_MAX_LINES 256 1705/* 1706 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1707 * to CNIC. 1708 */ 1709#define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1710 1711/* 1712 * Maximum CID count that might be required by the bnx2x: 1713 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1714 */ 1715 1716#define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1717 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1718#define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1719 + CNIC_SUPPORT(bp) * (2 + UIO_CID_PAD(bp))) 1720#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1721 ILT_PAGE_CIDS)) 1722 1723 int qm_cid_count; 1724 1725 bool dropless_fc; 1726 1727 void *t2; 1728 dma_addr_t t2_mapping; 1729 struct cnic_ops __rcu *cnic_ops; 1730 void *cnic_data; 1731 u32 cnic_tag; 1732 struct cnic_eth_dev cnic_eth_dev; 1733 union host_hc_status_block cnic_sb; 1734 dma_addr_t cnic_sb_mapping; 1735 struct eth_spe *cnic_kwq; 1736 struct eth_spe *cnic_kwq_prod; 1737 struct eth_spe *cnic_kwq_cons; 1738 struct eth_spe *cnic_kwq_last; 1739 u16 cnic_kwq_pending; 1740 u16 cnic_spq_pending; 1741 u8 fip_mac[ETH_ALEN]; 1742 struct mutex cnic_mutex; 1743 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1744 1745 /* Start index of the "special" (CNIC related) L2 clients */ 1746 u8 cnic_base_cl_id; 1747 1748 int dmae_ready; 1749 /* used to synchronize dmae accesses */ 1750 spinlock_t dmae_lock; 1751 1752 /* used to protect the FW mail box */ 1753 struct mutex fw_mb_mutex; 1754 1755 /* used to synchronize stats collecting */ 1756 int stats_state; 1757 1758 /* used for synchronization of concurrent threads statistics handling */ 1759 spinlock_t stats_lock; 1760 1761 /* used by dmae command loader */ 1762 struct dmae_command stats_dmae; 1763 int executer_idx; 1764 1765 u16 stats_counter; 1766 struct bnx2x_eth_stats eth_stats; 1767 struct host_func_stats func_stats; 1768 struct bnx2x_eth_stats_old eth_stats_old; 1769 struct bnx2x_net_stats_old net_stats_old; 1770 struct bnx2x_fw_port_stats_old fw_stats_old; 1771 bool stats_init; 1772 1773 struct z_stream_s *strm; 1774 void *gunzip_buf; 1775 dma_addr_t gunzip_mapping; 1776 int gunzip_outlen; 1777#define FW_BUF_SIZE 0x8000 1778#define GUNZIP_BUF(bp) (bp->gunzip_buf) 1779#define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1780#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1781 1782 struct raw_op *init_ops; 1783 /* Init blocks offsets inside init_ops */ 1784 u16 *init_ops_offsets; 1785 /* Data blob - has 32 bit granularity */ 1786 u32 *init_data; 1787 u32 init_mode_flags; 1788#define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1789 /* Zipped PRAM blobs - raw data */ 1790 const u8 *tsem_int_table_data; 1791 const u8 *tsem_pram_data; 1792 const u8 *usem_int_table_data; 1793 const u8 *usem_pram_data; 1794 const u8 *xsem_int_table_data; 1795 const u8 *xsem_pram_data; 1796 const u8 *csem_int_table_data; 1797 const u8 *csem_pram_data; 1798#define INIT_OPS(bp) (bp->init_ops) 1799#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1800#define INIT_DATA(bp) (bp->init_data) 1801#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1802#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1803#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1804#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1805#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1806#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1807#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1808#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1809 1810#define PHY_FW_VER_LEN 20 1811 char fw_ver[32]; 1812 const struct firmware *firmware; 1813 1814 struct bnx2x_vfdb *vfdb; 1815#define IS_SRIOV(bp) ((bp)->vfdb) 1816 1817 /* DCB support on/off */ 1818 u16 dcb_state; 1819#define BNX2X_DCB_STATE_OFF 0 1820#define BNX2X_DCB_STATE_ON 1 1821 1822 /* DCBX engine mode */ 1823 int dcbx_enabled; 1824#define BNX2X_DCBX_ENABLED_OFF 0 1825#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1826#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1827#define BNX2X_DCBX_ENABLED_INVALID (-1) 1828 1829 bool dcbx_mode_uset; 1830 1831 struct bnx2x_config_dcbx_params dcbx_config_params; 1832 struct bnx2x_dcbx_port_params dcbx_port_params; 1833 int dcb_version; 1834 1835 /* CAM credit pools */ 1836 1837 /* used only in sriov */ 1838 struct bnx2x_credit_pool_obj vlans_pool; 1839 1840 struct bnx2x_credit_pool_obj macs_pool; 1841 1842 /* RX_MODE object */ 1843 struct bnx2x_rx_mode_obj rx_mode_obj; 1844 1845 /* MCAST object */ 1846 struct bnx2x_mcast_obj mcast_obj; 1847 1848 /* RSS configuration object */ 1849 struct bnx2x_rss_config_obj rss_conf_obj; 1850 1851 /* Function State controlling object */ 1852 struct bnx2x_func_sp_obj func_obj; 1853 1854 unsigned long sp_state; 1855 1856 /* operation indication for the sp_rtnl task */ 1857 unsigned long sp_rtnl_state; 1858 1859 /* DCBX Negotiation results */ 1860 struct dcbx_features dcbx_local_feat; 1861 u32 dcbx_error; 1862 1863#ifdef BCM_DCBNL 1864 struct dcbx_features dcbx_remote_feat; 1865 u32 dcbx_remote_flags; 1866#endif 1867 /* AFEX: store default vlan used */ 1868 int afex_def_vlan_tag; 1869 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1870 u32 pending_max; 1871 1872 /* multiple tx classes of service */ 1873 u8 max_cos; 1874 1875 /* priority to cos mapping */ 1876 u8 prio_to_cos[8]; 1877 1878 int fp_array_size; 1879 u32 dump_preset_idx; 1880 bool stats_started; 1881 struct semaphore stats_sema; 1882 1883 u8 phys_port_id[ETH_ALEN]; 1884}; 1885 1886/* Tx queues may be less or equal to Rx queues */ 1887extern int num_queues; 1888#define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1889#define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 1890#define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 1891 (bp)->num_cnic_queues) 1892#define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1893 1894#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1895 1896#define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1897/* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1898 1899#define RSS_IPV4_CAP_MASK \ 1900 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1901 1902#define RSS_IPV4_TCP_CAP_MASK \ 1903 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1904 1905#define RSS_IPV6_CAP_MASK \ 1906 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1907 1908#define RSS_IPV6_TCP_CAP_MASK \ 1909 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1910 1911/* func init flags */ 1912#define FUNC_FLG_RSS 0x0001 1913#define FUNC_FLG_STATS 0x0002 1914/* removed FUNC_FLG_UNMATCHED 0x0004 */ 1915#define FUNC_FLG_TPA 0x0008 1916#define FUNC_FLG_SPQ 0x0010 1917#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1918#define FUNC_FLG_LEADING_STATS 0x0040 1919struct bnx2x_func_init_params { 1920 /* dma */ 1921 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1922 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1923 1924 u16 func_flgs; 1925 u16 func_id; /* abs fid */ 1926 u16 pf_id; 1927 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1928}; 1929 1930#define for_each_cnic_queue(bp, var) \ 1931 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1932 (var)++) \ 1933 if (skip_queue(bp, var)) \ 1934 continue; \ 1935 else 1936 1937#define for_each_eth_queue(bp, var) \ 1938 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1939 1940#define for_each_nondefault_eth_queue(bp, var) \ 1941 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1942 1943#define for_each_queue(bp, var) \ 1944 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1945 if (skip_queue(bp, var)) \ 1946 continue; \ 1947 else 1948 1949/* Skip forwarding FP */ 1950#define for_each_valid_rx_queue(bp, var) \ 1951 for ((var) = 0; \ 1952 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1953 BNX2X_NUM_ETH_QUEUES(bp)); \ 1954 (var)++) \ 1955 if (skip_rx_queue(bp, var)) \ 1956 continue; \ 1957 else 1958 1959#define for_each_rx_queue_cnic(bp, var) \ 1960 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1961 (var)++) \ 1962 if (skip_rx_queue(bp, var)) \ 1963 continue; \ 1964 else 1965 1966#define for_each_rx_queue(bp, var) \ 1967 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1968 if (skip_rx_queue(bp, var)) \ 1969 continue; \ 1970 else 1971 1972/* Skip OOO FP */ 1973#define for_each_valid_tx_queue(bp, var) \ 1974 for ((var) = 0; \ 1975 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1976 BNX2X_NUM_ETH_QUEUES(bp)); \ 1977 (var)++) \ 1978 if (skip_tx_queue(bp, var)) \ 1979 continue; \ 1980 else 1981 1982#define for_each_tx_queue_cnic(bp, var) \ 1983 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1984 (var)++) \ 1985 if (skip_tx_queue(bp, var)) \ 1986 continue; \ 1987 else 1988 1989#define for_each_tx_queue(bp, var) \ 1990 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1991 if (skip_tx_queue(bp, var)) \ 1992 continue; \ 1993 else 1994 1995#define for_each_nondefault_queue(bp, var) \ 1996 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1997 if (skip_queue(bp, var)) \ 1998 continue; \ 1999 else 2000 2001#define for_each_cos_in_tx_queue(fp, var) \ 2002 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 2003 2004/* skip rx queue 2005 * if FCOE l2 support is disabled and this is the fcoe L2 queue 2006 */ 2007#define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2008 2009/* skip tx queue 2010 * if FCOE l2 support is disabled and this is the fcoe L2 queue 2011 */ 2012#define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2013 2014#define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 2015 2016/** 2017 * bnx2x_set_mac_one - configure a single MAC address 2018 * 2019 * @bp: driver handle 2020 * @mac: MAC to configure 2021 * @obj: MAC object handle 2022 * @set: if 'true' add a new MAC, otherwise - delete 2023 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 2024 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 2025 * 2026 * Configures one MAC according to provided parameters or continues the 2027 * execution of previously scheduled commands if RAMROD_CONT is set in 2028 * ramrod_flags. 2029 * 2030 * Returns zero if operation has successfully completed, a positive value if the 2031 * operation has been successfully scheduled and a negative - if a requested 2032 * operations has failed. 2033 */ 2034int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 2035 struct bnx2x_vlan_mac_obj *obj, bool set, 2036 int mac_type, unsigned long *ramrod_flags); 2037/** 2038 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 2039 * 2040 * @bp: driver handle 2041 * @mac_obj: MAC object handle 2042 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 2043 * @wait_for_comp: if 'true' block until completion 2044 * 2045 * Deletes all MACs of the specific type (e.g. ETH, UC list). 2046 * 2047 * Returns zero if operation has successfully completed, a positive value if the 2048 * operation has been successfully scheduled and a negative - if a requested 2049 * operations has failed. 2050 */ 2051int bnx2x_del_all_macs(struct bnx2x *bp, 2052 struct bnx2x_vlan_mac_obj *mac_obj, 2053 int mac_type, bool wait_for_comp); 2054 2055/* Init Function API */ 2056void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 2057void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid, 2058 u8 vf_valid, int fw_sb_id, int igu_sb_id); 2059u32 bnx2x_get_pretend_reg(struct bnx2x *bp); 2060int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 2061int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2062int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 2063int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 2064void bnx2x_read_mf_cfg(struct bnx2x *bp); 2065 2066int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 2067 2068/* dmae */ 2069void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 2070void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 2071 u32 len32); 2072void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 2073u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 2074u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 2075u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 2076 bool with_comp, u8 comp_type); 2077 2078void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2079 u8 src_type, u8 dst_type); 2080int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae, 2081 u32 *comp); 2082 2083/* FLR related routines */ 2084u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp); 2085void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count); 2086int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt); 2087u8 bnx2x_is_pcie_pending(struct pci_dev *dev); 2088int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg, 2089 char *msg, u32 poll_cnt); 2090 2091void bnx2x_calc_fc_adv(struct bnx2x *bp); 2092int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 2093 u32 data_hi, u32 data_lo, int cmd_type); 2094void bnx2x_update_coalesce(struct bnx2x *bp); 2095int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 2096 2097bool bnx2x_port_after_undi(struct bnx2x *bp); 2098 2099static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 2100 int wait) 2101{ 2102 u32 val; 2103 2104 do { 2105 val = REG_RD(bp, reg); 2106 if (val == expected) 2107 break; 2108 ms -= wait; 2109 msleep(wait); 2110 2111 } while (ms > 0); 2112 2113 return val; 2114} 2115 2116void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, 2117 bool is_pf); 2118 2119#define BNX2X_ILT_ZALLOC(x, y, size) \ 2120 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL) 2121 2122#define BNX2X_ILT_FREE(x, y, size) \ 2123 do { \ 2124 if (x) { \ 2125 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 2126 x = NULL; \ 2127 y = 0; \ 2128 } \ 2129 } while (0) 2130 2131#define ILOG2(x) (ilog2((x))) 2132 2133#define ILT_NUM_PAGE_ENTRIES (3072) 2134/* In 57710/11 we use whole table since we have 8 func 2135 * In 57712 we have only 4 func, but use same size per func, then only half of 2136 * the table in use 2137 */ 2138#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 2139 2140#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 2141/* 2142 * the phys address is shifted right 12 bits and has an added 2143 * 1=valid bit added to the 53rd bit 2144 * then since this is a wide register(TM) 2145 * we split it into two 32 bit writes 2146 */ 2147#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 2148#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 2149 2150/* load/unload mode */ 2151#define LOAD_NORMAL 0 2152#define LOAD_OPEN 1 2153#define LOAD_DIAG 2 2154#define LOAD_LOOPBACK_EXT 3 2155#define UNLOAD_NORMAL 0 2156#define UNLOAD_CLOSE 1 2157#define UNLOAD_RECOVERY 2 2158 2159/* DMAE command defines */ 2160#define DMAE_TIMEOUT -1 2161#define DMAE_PCI_ERROR -2 /* E2 and onward */ 2162#define DMAE_NOT_RDY -3 2163#define DMAE_PCI_ERR_FLAG 0x80000000 2164 2165#define DMAE_SRC_PCI 0 2166#define DMAE_SRC_GRC 1 2167 2168#define DMAE_DST_NONE 0 2169#define DMAE_DST_PCI 1 2170#define DMAE_DST_GRC 2 2171 2172#define DMAE_COMP_PCI 0 2173#define DMAE_COMP_GRC 1 2174 2175/* E2 and onward - PCI error handling in the completion */ 2176 2177#define DMAE_COMP_REGULAR 0 2178#define DMAE_COM_SET_ERR 1 2179 2180#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 2181 DMAE_COMMAND_SRC_SHIFT) 2182#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 2183 DMAE_COMMAND_SRC_SHIFT) 2184 2185#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 2186 DMAE_COMMAND_DST_SHIFT) 2187#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 2188 DMAE_COMMAND_DST_SHIFT) 2189 2190#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 2191 DMAE_COMMAND_C_DST_SHIFT) 2192#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 2193 DMAE_COMMAND_C_DST_SHIFT) 2194 2195#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 2196 2197#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2198#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2199#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2200#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2201 2202#define DMAE_CMD_PORT_0 0 2203#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2204 2205#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 2206#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 2207#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 2208 2209#define DMAE_SRC_PF 0 2210#define DMAE_SRC_VF 1 2211 2212#define DMAE_DST_PF 0 2213#define DMAE_DST_VF 1 2214 2215#define DMAE_C_SRC 0 2216#define DMAE_C_DST 1 2217 2218#define DMAE_LEN32_RD_MAX 0x80 2219#define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 2220 2221#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 2222 * indicates error 2223 */ 2224 2225#define MAX_DMAE_C_PER_PORT 8 2226#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2227 BP_VN(bp)) 2228#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2229 E1HVN_MAX) 2230 2231/* PCIE link and speed */ 2232#define PCICFG_LINK_WIDTH 0x1f00000 2233#define PCICFG_LINK_WIDTH_SHIFT 20 2234#define PCICFG_LINK_SPEED 0xf0000 2235#define PCICFG_LINK_SPEED_SHIFT 16 2236 2237#define BNX2X_NUM_TESTS_SF 7 2238#define BNX2X_NUM_TESTS_MF 3 2239#define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 2240 IS_VF(bp) ? 0 : BNX2X_NUM_TESTS_SF) 2241 2242#define BNX2X_PHY_LOOPBACK 0 2243#define BNX2X_MAC_LOOPBACK 1 2244#define BNX2X_EXT_LOOPBACK 2 2245#define BNX2X_PHY_LOOPBACK_FAILED 1 2246#define BNX2X_MAC_LOOPBACK_FAILED 2 2247#define BNX2X_EXT_LOOPBACK_FAILED 3 2248#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2249 BNX2X_PHY_LOOPBACK_FAILED) 2250 2251#define STROM_ASSERT_ARRAY_SIZE 50 2252 2253/* must be used on a CID before placing it on a HW ring */ 2254#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 2255 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2256 (x)) 2257 2258#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2259#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2260 2261#define BNX2X_BTR 4 2262#define MAX_SPQ_PENDING 8 2263 2264/* CMNG constants, as derived from system spec calculations */ 2265/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2266#define DEF_MIN_RATE 100 2267/* resolution of the rate shaping timer - 400 usec */ 2268#define RS_PERIODIC_TIMEOUT_USEC 400 2269/* number of bytes in single QM arbitration cycle - 2270 * coefficient for calculating the fairness timer */ 2271#define QM_ARB_BYTES 160000 2272/* resolution of Min algorithm 1:100 */ 2273#define MIN_RES 100 2274/* how many bytes above threshold for the minimal credit of Min algorithm*/ 2275#define MIN_ABOVE_THRESH 32768 2276/* Fairness algorithm integration time coefficient - 2277 * for calculating the actual Tfair */ 2278#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2279/* Memory of fairness algorithm . 2 cycles */ 2280#define FAIR_MEM 2 2281 2282#define ATTN_NIG_FOR_FUNC (1L << 8) 2283#define ATTN_SW_TIMER_4_FUNC (1L << 9) 2284#define GPIO_2_FUNC (1L << 10) 2285#define GPIO_3_FUNC (1L << 11) 2286#define GPIO_4_FUNC (1L << 12) 2287#define ATTN_GENERAL_ATTN_1 (1L << 13) 2288#define ATTN_GENERAL_ATTN_2 (1L << 14) 2289#define ATTN_GENERAL_ATTN_3 (1L << 15) 2290#define ATTN_GENERAL_ATTN_4 (1L << 13) 2291#define ATTN_GENERAL_ATTN_5 (1L << 14) 2292#define ATTN_GENERAL_ATTN_6 (1L << 15) 2293 2294#define ATTN_HARD_WIRED_MASK 0xff00 2295#define ATTENTION_ID 4 2296 2297#define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_SD(bp) || \ 2298 IS_MF_FCOE_AFEX(bp)) 2299 2300/* stuff added to make the code fit 80Col */ 2301 2302#define BNX2X_PMF_LINK_ASSERT \ 2303 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2304 2305#define BNX2X_MC_ASSERT_BITS \ 2306 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2307 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2308 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2309 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2310 2311#define BNX2X_MCP_ASSERT \ 2312 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2313 2314#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2315#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2316 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2317 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2318 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2319 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2320 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2321 2322#define HW_INTERRUT_ASSERT_SET_0 \ 2323 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2324 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2325 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2326 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \ 2327 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2328#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2329 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2330 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2331 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2332 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2333 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2334 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2335#define HW_INTERRUT_ASSERT_SET_1 \ 2336 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2337 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2338 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2339 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2340 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2341 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2342 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2343 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2344 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2345 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2346 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2347#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2348 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2349 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2350 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2351 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2352 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2353 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2354 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2355 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2356 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2357 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2358 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2359 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2360 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2361 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2362 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2363#define HW_INTERRUT_ASSERT_SET_2 \ 2364 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2365 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2366 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2367 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2368 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2369#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2370 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2371 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2372 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2373 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2374 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2375 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2376 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2377 2378#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2379 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2380 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2381 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2382 2383#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2384 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2385 2386#define MULTI_MASK 0x7f 2387 2388#define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2389#define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2390#define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2391#define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2392 2393#define DEF_USB_IGU_INDEX_OFF \ 2394 offsetof(struct cstorm_def_status_block_u, igu_index) 2395#define DEF_CSB_IGU_INDEX_OFF \ 2396 offsetof(struct cstorm_def_status_block_c, igu_index) 2397#define DEF_XSB_IGU_INDEX_OFF \ 2398 offsetof(struct xstorm_def_status_block, igu_index) 2399#define DEF_TSB_IGU_INDEX_OFF \ 2400 offsetof(struct tstorm_def_status_block, igu_index) 2401 2402#define DEF_USB_SEGMENT_OFF \ 2403 offsetof(struct cstorm_def_status_block_u, segment) 2404#define DEF_CSB_SEGMENT_OFF \ 2405 offsetof(struct cstorm_def_status_block_c, segment) 2406#define DEF_XSB_SEGMENT_OFF \ 2407 offsetof(struct xstorm_def_status_block, segment) 2408#define DEF_TSB_SEGMENT_OFF \ 2409 offsetof(struct tstorm_def_status_block, segment) 2410 2411#define BNX2X_SP_DSB_INDEX \ 2412 (&bp->def_status_blk->sp_sb.\ 2413 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2414 2415#define CAM_IS_INVALID(x) \ 2416 (GET_FLAG(x.flags, \ 2417 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2418 (T_ETH_MAC_COMMAND_INVALIDATE)) 2419 2420/* Number of u32 elements in MC hash array */ 2421#define MC_HASH_SIZE 8 2422#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2423 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2424 2425#ifndef PXP2_REG_PXP2_INT_STS 2426#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2427#endif 2428 2429#ifndef ETH_MAX_RX_CLIENTS_E2 2430#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2431#endif 2432 2433#define BNX2X_VPD_LEN 128 2434#define VENDOR_ID_LEN 4 2435 2436#define VF_ACQUIRE_THRESH 3 2437#define VF_ACQUIRE_MAC_FILTERS 1 2438#define VF_ACQUIRE_MC_FILTERS 10 2439 2440#define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2441 (!((me_reg) & ME_REG_VF_ERR))) 2442int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code); 2443/* Congestion management fairness mode */ 2444#define CMNG_FNS_NONE 0 2445#define CMNG_FNS_MINMAX 1 2446 2447#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2448#define HC_SEG_ACCESS_ATTN 4 2449#define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2450 2451static const u32 dmae_reg_go_c[] = { 2452 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2453 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2454 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2455 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2456}; 2457 2458void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev); 2459void bnx2x_notify_link_changed(struct bnx2x *bp); 2460 2461#define BNX2X_MF_SD_PROTOCOL(bp) \ 2462 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2463 2464#define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 2465 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2466 2467#define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 2468 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 2469 2470#define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 2471#define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 2472 2473#define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \ 2474 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2475 2476#define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp)) 2477#define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \ 2478 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 2479 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2480 2481#define SET_FLAG(value, mask, flag) \ 2482 do {\ 2483 (value) &= ~(mask);\ 2484 (value) |= ((flag) << (mask##_SHIFT));\ 2485 } while (0) 2486 2487#define GET_FLAG(value, mask) \ 2488 (((value) & (mask)) >> (mask##_SHIFT)) 2489 2490#define GET_FIELD(value, fname) \ 2491 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2492 2493enum { 2494 SWITCH_UPDATE, 2495 AFEX_UPDATE, 2496}; 2497 2498#define NUM_MACS 8 2499 2500void bnx2x_set_local_cmng(struct bnx2x *bp); 2501 2502#define MCPR_SCRATCH_BASE(bp) \ 2503 (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH) 2504 2505#define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX)) 2506 2507#endif /* bnx2x.h */ 2508