bnx2x.h revision b56e9670ffa4de1a3cf0ca2f89ff5e2e0c31a1f7
1/* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14#ifndef BNX2X_H 15#define BNX2X_H 16 17#include <linux/pci.h> 18#include <linux/netdevice.h> 19#include <linux/dma-mapping.h> 20#include <linux/types.h> 21#include <linux/pci_regs.h> 22 23/* compilation time flags */ 24 25/* define this to make the driver freeze on error to allow getting debug info 26 * (you will need to reboot afterwards) */ 27/* #define BNX2X_STOP_ON_ERROR */ 28 29#define DRV_MODULE_VERSION "1.78.00-0" 30#define DRV_MODULE_RELDATE "2012/09/27" 31#define BNX2X_BC_VER 0x040200 32 33#if defined(CONFIG_DCB) 34#define BCM_DCBNL 35#endif 36 37 38#include "bnx2x_hsi.h" 39 40#include "../cnic_if.h" 41 42 43#define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt) 44 45#include <linux/mdio.h> 46 47#include "bnx2x_reg.h" 48#include "bnx2x_fw_defs.h" 49#include "bnx2x_mfw_req.h" 50#include "bnx2x_link.h" 51#include "bnx2x_sp.h" 52#include "bnx2x_dcb.h" 53#include "bnx2x_stats.h" 54#include "bnx2x_vfpf.h" 55 56enum bnx2x_int_mode { 57 BNX2X_INT_MODE_MSIX, 58 BNX2X_INT_MODE_INTX, 59 BNX2X_INT_MODE_MSI 60}; 61 62/* error/debug prints */ 63 64#define DRV_MODULE_NAME "bnx2x" 65 66/* for messages that are currently off */ 67#define BNX2X_MSG_OFF 0x0 68#define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 69#define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 70#define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 71#define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 72#define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 73#define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 74#define BNX2X_MSG_IOV 0x0800000 75#define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 76#define BNX2X_MSG_ETHTOOL 0x4000000 77#define BNX2X_MSG_DCB 0x8000000 78 79/* regular debug print */ 80#define DP(__mask, fmt, ...) \ 81do { \ 82 if (unlikely(bp->msg_enable & (__mask))) \ 83 pr_notice("[%s:%d(%s)]" fmt, \ 84 __func__, __LINE__, \ 85 bp->dev ? (bp->dev->name) : "?", \ 86 ##__VA_ARGS__); \ 87} while (0) 88 89#define DP_CONT(__mask, fmt, ...) \ 90do { \ 91 if (unlikely(bp->msg_enable & (__mask))) \ 92 pr_cont(fmt, ##__VA_ARGS__); \ 93} while (0) 94 95/* errors debug print */ 96#define BNX2X_DBG_ERR(fmt, ...) \ 97do { \ 98 if (unlikely(netif_msg_probe(bp))) \ 99 pr_err("[%s:%d(%s)]" fmt, \ 100 __func__, __LINE__, \ 101 bp->dev ? (bp->dev->name) : "?", \ 102 ##__VA_ARGS__); \ 103} while (0) 104 105/* for errors (never masked) */ 106#define BNX2X_ERR(fmt, ...) \ 107do { \ 108 pr_err("[%s:%d(%s)]" fmt, \ 109 __func__, __LINE__, \ 110 bp->dev ? (bp->dev->name) : "?", \ 111 ##__VA_ARGS__); \ 112} while (0) 113 114#define BNX2X_ERROR(fmt, ...) \ 115 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 116 117 118/* before we have a dev->name use dev_info() */ 119#define BNX2X_DEV_INFO(fmt, ...) \ 120do { \ 121 if (unlikely(netif_msg_probe(bp))) \ 122 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 123} while (0) 124 125#ifdef BNX2X_STOP_ON_ERROR 126void bnx2x_int_disable(struct bnx2x *bp); 127#define bnx2x_panic() \ 128do { \ 129 bp->panic = 1; \ 130 BNX2X_ERR("driver assert\n"); \ 131 bnx2x_int_disable(bp); \ 132 bnx2x_panic_dump(bp); \ 133} while (0) 134#else 135#define bnx2x_panic() \ 136do { \ 137 bp->panic = 1; \ 138 BNX2X_ERR("driver assert\n"); \ 139 bnx2x_panic_dump(bp); \ 140} while (0) 141#endif 142 143#define bnx2x_mc_addr(ha) ((ha)->addr) 144#define bnx2x_uc_addr(ha) ((ha)->addr) 145 146#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) 147#define U64_HI(x) (u32)(((u64)(x)) >> 32) 148#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 149 150 151#define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 152 153#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 154#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 155#define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 156 157#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 158#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 159#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 160 161#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 162#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 163 164#define REG_RD_DMAE(bp, offset, valp, len32) \ 165 do { \ 166 bnx2x_read_dmae(bp, offset, len32);\ 167 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 168 } while (0) 169 170#define REG_WR_DMAE(bp, offset, valp, len32) \ 171 do { \ 172 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 173 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 174 offset, len32); \ 175 } while (0) 176 177#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 178 REG_WR_DMAE(bp, offset, valp, len32) 179 180#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 181 do { \ 182 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 183 bnx2x_write_big_buf_wb(bp, addr, len32); \ 184 } while (0) 185 186#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 187 offsetof(struct shmem_region, field)) 188#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 189#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 190 191#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 192 offsetof(struct shmem2_region, field)) 193#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 194#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 195#define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 196 offsetof(struct mf_cfg, field)) 197#define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 198 offsetof(struct mf2_cfg, field)) 199 200#define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 201#define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 202 MF_CFG_ADDR(bp, field), (val)) 203#define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 204 205#define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 206 (SHMEM2_RD((bp), size) > \ 207 offsetof(struct shmem2_region, field))) 208 209#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 210#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 211 212/* SP SB indices */ 213 214/* General SP events - stats query, cfc delete, etc */ 215#define HC_SP_INDEX_ETH_DEF_CONS 3 216 217/* EQ completions */ 218#define HC_SP_INDEX_EQ_CONS 7 219 220/* FCoE L2 connection completions */ 221#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 222#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 223/* iSCSI L2 */ 224#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 225#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 226 227/* Special clients parameters */ 228 229/* SB indices */ 230/* FCoE L2 */ 231#define BNX2X_FCOE_L2_RX_INDEX \ 232 (&bp->def_status_blk->sp_sb.\ 233 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 234 235#define BNX2X_FCOE_L2_TX_INDEX \ 236 (&bp->def_status_blk->sp_sb.\ 237 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 238 239/** 240 * CIDs and CLIDs: 241 * CLIDs below is a CLID for func 0, then the CLID for other 242 * functions will be calculated by the formula: 243 * 244 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 245 * 246 */ 247enum { 248 BNX2X_ISCSI_ETH_CL_ID_IDX, 249 BNX2X_FCOE_ETH_CL_ID_IDX, 250 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 251}; 252 253#define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\ 254 (bp)->max_cos) 255 /* iSCSI L2 */ 256#define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp)) 257 /* FCoE L2 */ 258#define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1) 259 260#define CNIC_SUPPORT(bp) ((bp)->cnic_support) 261#define CNIC_ENABLED(bp) ((bp)->cnic_enabled) 262#define CNIC_LOADED(bp) ((bp)->cnic_loaded) 263#define FCOE_INIT(bp) ((bp)->fcoe_init) 264 265#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 266 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 267 268#define SM_RX_ID 0 269#define SM_TX_ID 1 270 271/* defines for multiple tx priority indices */ 272#define FIRST_TX_ONLY_COS_INDEX 1 273#define FIRST_TX_COS_INDEX 0 274 275/* rules for calculating the cids of tx-only connections */ 276#define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp)) 277#define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \ 278 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 279 280/* fp index inside class of service range */ 281#define FP_COS_TO_TXQ(fp, cos, bp) \ 282 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp)) 283 284/* Indexes for transmission queues array: 285 * txdata for RSS i CoS j is at location i + (j * num of RSS) 286 * txdata for FCoE (if exist) is at location max cos * num of RSS 287 * txdata for FWD (if exist) is one location after FCoE 288 * txdata for OOO (if exist) is one location after FWD 289 */ 290enum { 291 FCOE_TXQ_IDX_OFFSET, 292 FWD_TXQ_IDX_OFFSET, 293 OOO_TXQ_IDX_OFFSET, 294}; 295#define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos) 296#define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET) 297 298/* fast path */ 299/* 300 * This driver uses new build_skb() API : 301 * RX ring buffer contains pointer to kmalloc() data only, 302 * skb are built only after Hardware filled the frame. 303 */ 304struct sw_rx_bd { 305 u8 *data; 306 DEFINE_DMA_UNMAP_ADDR(mapping); 307}; 308 309struct sw_tx_bd { 310 struct sk_buff *skb; 311 u16 first_bd; 312 u8 flags; 313/* Set on the first BD descriptor when there is a split BD */ 314#define BNX2X_TSO_SPLIT_BD (1<<0) 315}; 316 317struct sw_rx_page { 318 struct page *page; 319 DEFINE_DMA_UNMAP_ADDR(mapping); 320}; 321 322union db_prod { 323 struct doorbell_set_prod data; 324 u32 raw; 325}; 326 327/* dropless fc FW/HW related params */ 328#define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 329#define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 330 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 331 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 332#define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 333#define FW_PREFETCH_CNT 16 334#define DROPLESS_FC_HEADROOM 100 335 336/* MC hsi */ 337#define BCM_PAGE_SHIFT 12 338#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 339#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 340#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 341 342#define PAGES_PER_SGE_SHIFT 0 343#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 344#define SGE_PAGE_SIZE PAGE_SIZE 345#define SGE_PAGE_SHIFT PAGE_SHIFT 346#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 347#define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 348#define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \ 349 SGE_PAGES), 0xffff) 350 351/* SGE ring related macros */ 352#define NUM_RX_SGE_PAGES 2 353#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 354#define NEXT_PAGE_SGE_DESC_CNT 2 355#define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 356/* RX_SGE_CNT is promised to be a power of 2 */ 357#define RX_SGE_MASK (RX_SGE_CNT - 1) 358#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 359#define MAX_RX_SGE (NUM_RX_SGE - 1) 360#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 361 (MAX_RX_SGE_CNT - 1)) ? \ 362 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 363 (x) + 1) 364#define RX_SGE(x) ((x) & MAX_RX_SGE) 365 366/* 367 * Number of required SGEs is the sum of two: 368 * 1. Number of possible opened aggregations (next packet for 369 * these aggregations will probably consume SGE immidiatelly) 370 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 371 * after placement on BD for new TPA aggregation) 372 * 373 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 374 */ 375#define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 376 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 377#define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 378 MAX_RX_SGE_CNT) 379#define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 380 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 381#define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 382 383/* Manipulate a bit vector defined as an array of u64 */ 384 385/* Number of bits in one sge_mask array element */ 386#define BIT_VEC64_ELEM_SZ 64 387#define BIT_VEC64_ELEM_SHIFT 6 388#define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 389 390 391#define __BIT_VEC64_SET_BIT(el, bit) \ 392 do { \ 393 el = ((el) | ((u64)0x1 << (bit))); \ 394 } while (0) 395 396#define __BIT_VEC64_CLEAR_BIT(el, bit) \ 397 do { \ 398 el = ((el) & (~((u64)0x1 << (bit)))); \ 399 } while (0) 400 401 402#define BIT_VEC64_SET_BIT(vec64, idx) \ 403 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 404 (idx) & BIT_VEC64_ELEM_MASK) 405 406#define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 407 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 408 (idx) & BIT_VEC64_ELEM_MASK) 409 410#define BIT_VEC64_TEST_BIT(vec64, idx) \ 411 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 412 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 413 414/* Creates a bitmask of all ones in less significant bits. 415 idx - index of the most significant bit in the created mask */ 416#define BIT_VEC64_ONES_MASK(idx) \ 417 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 418#define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 419 420/*******************************************************/ 421 422 423 424/* Number of u64 elements in SGE mask array */ 425#define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 426#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 427#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 428 429union host_hc_status_block { 430 /* pointer to fp status block e1x */ 431 struct host_hc_status_block_e1x *e1x_sb; 432 /* pointer to fp status block e2 */ 433 struct host_hc_status_block_e2 *e2_sb; 434}; 435 436struct bnx2x_agg_info { 437 /* 438 * First aggregation buffer is a data buffer, the following - are pages. 439 * We will preallocate the data buffer for each aggregation when 440 * we open the interface and will replace the BD at the consumer 441 * with this one when we receive the TPA_START CQE in order to 442 * keep the Rx BD ring consistent. 443 */ 444 struct sw_rx_bd first_buf; 445 u8 tpa_state; 446#define BNX2X_TPA_START 1 447#define BNX2X_TPA_STOP 2 448#define BNX2X_TPA_ERROR 3 449 u8 placement_offset; 450 u16 parsing_flags; 451 u16 vlan_tag; 452 u16 len_on_bd; 453 u32 rxhash; 454 bool l4_rxhash; 455 u16 gro_size; 456 u16 full_page; 457}; 458 459#define Q_STATS_OFFSET32(stat_name) \ 460 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 461 462struct bnx2x_fp_txdata { 463 464 struct sw_tx_bd *tx_buf_ring; 465 466 union eth_tx_bd_types *tx_desc_ring; 467 dma_addr_t tx_desc_mapping; 468 469 u32 cid; 470 471 union db_prod tx_db; 472 473 u16 tx_pkt_prod; 474 u16 tx_pkt_cons; 475 u16 tx_bd_prod; 476 u16 tx_bd_cons; 477 478 unsigned long tx_pkt; 479 480 __le16 *tx_cons_sb; 481 482 int txq_index; 483 struct bnx2x_fastpath *parent_fp; 484 int tx_ring_size; 485}; 486 487enum bnx2x_tpa_mode_t { 488 TPA_MODE_LRO, 489 TPA_MODE_GRO 490}; 491 492struct bnx2x_fastpath { 493 struct bnx2x *bp; /* parent */ 494 495#define BNX2X_NAPI_WEIGHT 128 496 struct napi_struct napi; 497 union host_hc_status_block status_blk; 498 /* chip independed shortcuts into sb structure */ 499 __le16 *sb_index_values; 500 __le16 *sb_running_index; 501 /* chip independed shortcut into rx_prods_offset memory */ 502 u32 ustorm_rx_prods_offset; 503 504 u32 rx_buf_size; 505 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */ 506 dma_addr_t status_blk_mapping; 507 508 enum bnx2x_tpa_mode_t mode; 509 510 u8 max_cos; /* actual number of active tx coses */ 511 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS]; 512 513 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 514 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 515 516 struct eth_rx_bd *rx_desc_ring; 517 dma_addr_t rx_desc_mapping; 518 519 union eth_rx_cqe *rx_comp_ring; 520 dma_addr_t rx_comp_mapping; 521 522 /* SGE ring */ 523 struct eth_rx_sge *rx_sge_ring; 524 dma_addr_t rx_sge_mapping; 525 526 u64 sge_mask[RX_SGE_MASK_LEN]; 527 528 u32 cid; 529 530 __le16 fp_hc_idx; 531 532 u8 index; /* number in fp array */ 533 u8 rx_queue; /* index for skb_record */ 534 u8 cl_id; /* eth client id */ 535 u8 cl_qzone_id; 536 u8 fw_sb_id; /* status block number in FW */ 537 u8 igu_sb_id; /* status block number in HW */ 538 539 u16 rx_bd_prod; 540 u16 rx_bd_cons; 541 u16 rx_comp_prod; 542 u16 rx_comp_cons; 543 u16 rx_sge_prod; 544 /* The last maximal completed SGE */ 545 u16 last_max_sge; 546 __le16 *rx_cons_sb; 547 unsigned long rx_pkt, 548 rx_calls; 549 550 /* TPA related */ 551 struct bnx2x_agg_info *tpa_info; 552 u8 disable_tpa; 553#ifdef BNX2X_STOP_ON_ERROR 554 u64 tpa_queue_used; 555#endif 556 /* The size is calculated using the following: 557 sizeof name field from netdev structure + 558 4 ('-Xx-' string) + 559 4 (for the digits and to make it DWORD aligned) */ 560#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 561 char name[FP_NAME_SIZE]; 562}; 563 564#define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var) 565#define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index]) 566#define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index])) 567#define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats)) 568 569/* Use 2500 as a mini-jumbo MTU for FCoE */ 570#define BNX2X_FCOE_MINI_JUMBO_MTU 2500 571 572#define FCOE_IDX_OFFSET 0 573 574#define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \ 575 FCOE_IDX_OFFSET) 576#define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)]) 577#define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 578#define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)]) 579#define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var) 580#define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 581 txdata_ptr[FIRST_TX_COS_INDEX] \ 582 ->var) 583 584 585#define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp)) 586#define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp)) 587#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp)) 588 589 590/* MC hsi */ 591#define MAX_FETCH_BD 13 /* HW max BDs per packet */ 592#define RX_COPY_THRESH 92 593 594#define NUM_TX_RINGS 16 595#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 596#define NEXT_PAGE_TX_DESC_CNT 1 597#define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 598#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 599#define MAX_TX_BD (NUM_TX_BD - 1) 600#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 601#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 602 (MAX_TX_DESC_CNT - 1)) ? \ 603 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 604 (x) + 1) 605#define TX_BD(x) ((x) & MAX_TX_BD) 606#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 607 608/* number of NEXT_PAGE descriptors may be required during placement */ 609#define NEXT_CNT_PER_TX_PKT(bds) \ 610 (((bds) + MAX_TX_DESC_CNT - 1) / \ 611 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT) 612/* max BDs per tx packet w/o next_pages: 613 * START_BD - describes packed 614 * START_BD(splitted) - includes unpaged data segment for GSO 615 * PARSING_BD - for TSO and CSUM data 616 * Frag BDs - decribes pages for frags 617 */ 618#define BDS_PER_TX_PKT 3 619#define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT) 620/* max BDs per tx packet including next pages */ 621#define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \ 622 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT)) 623 624/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 625#define NUM_RX_RINGS 8 626#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 627#define NEXT_PAGE_RX_DESC_CNT 2 628#define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 629#define RX_DESC_MASK (RX_DESC_CNT - 1) 630#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 631#define MAX_RX_BD (NUM_RX_BD - 1) 632#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 633 634/* dropless fc calculations for BDs 635 * 636 * Number of BDs should as number of buffers in BRB: 637 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 638 * "next" elements on each page 639 */ 640#define NUM_BD_REQ BRB_SIZE(bp) 641#define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 642 MAX_RX_DESC_CNT) 643#define BD_TH_LO(bp) (NUM_BD_REQ + \ 644 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 645 FW_DROP_LEVEL(bp)) 646#define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 647 648#define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 649 650#define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 651 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 652 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 653#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 654#define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 655#define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 656 MIN_RX_AVAIL)) 657 658#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 659 (MAX_RX_DESC_CNT - 1)) ? \ 660 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 661 (x) + 1) 662#define RX_BD(x) ((x) & MAX_RX_BD) 663 664/* 665 * As long as CQE is X times bigger than BD entry we have to allocate X times 666 * more pages for CQ ring in order to keep it balanced with BD ring 667 */ 668#define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 669#define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 670#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 671#define NEXT_PAGE_RCQ_DESC_CNT 1 672#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 673#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 674#define MAX_RCQ_BD (NUM_RCQ_BD - 1) 675#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 676#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 677 (MAX_RCQ_DESC_CNT - 1)) ? \ 678 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 679 (x) + 1) 680#define RCQ_BD(x) ((x) & MAX_RCQ_BD) 681 682/* dropless fc calculations for RCQs 683 * 684 * Number of RCQs should be as number of buffers in BRB: 685 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 686 * "next" elements on each page 687 */ 688#define NUM_RCQ_REQ BRB_SIZE(bp) 689#define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 690 MAX_RCQ_DESC_CNT) 691#define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 692 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 693 FW_DROP_LEVEL(bp)) 694#define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 695 696 697/* This is needed for determining of last_max */ 698#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 699#define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 700 701 702#define BNX2X_SWCID_SHIFT 17 703#define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 704 705/* used on a CID received from the HW */ 706#define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 707#define CQE_CMD(x) (le32_to_cpu(x) >> \ 708 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 709 710#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 711 le32_to_cpu((bd)->addr_lo)) 712#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 713 714#define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 715#define BNX2X_DB_SHIFT 7 /* 128 bytes*/ 716#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 717#error "Min DB doorbell stride is 8" 718#endif 719#define DPM_TRIGER_TYPE 0x40 720#define DOORBELL(bp, cid, val) \ 721 do { \ 722 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ 723 DPM_TRIGER_TYPE); \ 724 } while (0) 725 726 727/* TX CSUM helpers */ 728#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 729 skb->csum_offset) 730#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 731 skb->csum_offset)) 732 733#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) 734 735#define XMIT_PLAIN 0 736#define XMIT_CSUM_V4 0x1 737#define XMIT_CSUM_V6 0x2 738#define XMIT_CSUM_TCP 0x4 739#define XMIT_GSO_V4 0x8 740#define XMIT_GSO_V6 0x10 741 742#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) 743#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) 744 745 746/* stuff added to make the code fit 80Col */ 747#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 748#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 749#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 750#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 751#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 752 753#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 754 755#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 756 (((le16_to_cpu(flags) & \ 757 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 758 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 759 == PRS_FLAG_OVERETH_IPV4) 760#define BNX2X_RX_SUM_FIX(cqe) \ 761 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 762 763 764#define FP_USB_FUNC_OFF \ 765 offsetof(struct cstorm_status_block_u, func) 766#define FP_CSB_FUNC_OFF \ 767 offsetof(struct cstorm_status_block_c, func) 768 769#define HC_INDEX_ETH_RX_CQ_CONS 1 770 771#define HC_INDEX_OOO_TX_CQ_CONS 4 772 773#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 774 775#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 776 777#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 778 779#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 780 781#define BNX2X_RX_SB_INDEX \ 782 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 783 784#define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 785 786#define BNX2X_TX_SB_INDEX_COS0 \ 787 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 788 789/* end of fast path */ 790 791/* common */ 792 793struct bnx2x_common { 794 795 u32 chip_id; 796/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 797#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 798 799#define CHIP_NUM(bp) (bp->common.chip_id >> 16) 800#define CHIP_NUM_57710 0x164e 801#define CHIP_NUM_57711 0x164f 802#define CHIP_NUM_57711E 0x1650 803#define CHIP_NUM_57712 0x1662 804#define CHIP_NUM_57712_MF 0x1663 805#define CHIP_NUM_57713 0x1651 806#define CHIP_NUM_57713E 0x1652 807#define CHIP_NUM_57800 0x168a 808#define CHIP_NUM_57800_MF 0x16a5 809#define CHIP_NUM_57810 0x168e 810#define CHIP_NUM_57810_MF 0x16ae 811#define CHIP_NUM_57811 0x163d 812#define CHIP_NUM_57811_MF 0x163e 813#define CHIP_NUM_57840_OBSOLETE 0x168d 814#define CHIP_NUM_57840_MF_OBSOLETE 0x16ab 815#define CHIP_NUM_57840_4_10 0x16a1 816#define CHIP_NUM_57840_2_20 0x16a2 817#define CHIP_NUM_57840_MF 0x16a4 818#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 819#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 820#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 821#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 822#define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 823#define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 824#define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 825#define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 826#define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 827#define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 828#define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 829#define CHIP_IS_57840(bp) \ 830 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \ 831 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \ 832 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE)) 833#define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \ 834 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE)) 835#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 836 CHIP_IS_57711E(bp)) 837#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 838 CHIP_IS_57712_MF(bp)) 839#define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 840 CHIP_IS_57800_MF(bp) || \ 841 CHIP_IS_57810(bp) || \ 842 CHIP_IS_57810_MF(bp) || \ 843 CHIP_IS_57811(bp) || \ 844 CHIP_IS_57811_MF(bp) || \ 845 CHIP_IS_57840(bp) || \ 846 CHIP_IS_57840_MF(bp)) 847#define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 848#define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 849#define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 850 851#define CHIP_REV_SHIFT 12 852#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 853#define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 854#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 855#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 856/* assume maximum 5 revisions */ 857#define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 858/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 859#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 860 !(CHIP_REV_VAL(bp) & 0x00001000)) 861/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 862#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 863 (CHIP_REV_VAL(bp) & 0x00001000)) 864 865#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 866 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 867 868#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 869#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 870#define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 871 (CHIP_REV_SHIFT + 1)) \ 872 << CHIP_REV_SHIFT) 873#define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 874 CHIP_REV_SIM(bp) :\ 875 CHIP_REV_VAL(bp)) 876#define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 877 (CHIP_REV(bp) == CHIP_REV_Bx)) 878#define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 879 (CHIP_REV(bp) == CHIP_REV_Ax)) 880/* This define is used in two main places: 881 * 1. In the early stages of nic_load, to know if to configrue Parser / Searcher 882 * to nic-only mode or to offload mode. Offload mode is configured if either the 883 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already 884 * registered for this port (which means that the user wants storage services). 885 * 2. During cnic-related load, to know if offload mode is already configured in 886 * the HW or needs to be configrued. 887 * Since the transition from nic-mode to offload-mode in HW causes traffic 888 * coruption, nic-mode is configured only in ports on which storage services 889 * where never requested. 890 */ 891#define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp)) 892 893 int flash_size; 894#define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 895#define BNX2X_NVRAM_TIMEOUT_COUNT 30000 896#define BNX2X_NVRAM_PAGE_SIZE 256 897 898 u32 shmem_base; 899 u32 shmem2_base; 900 u32 mf_cfg_base; 901 u32 mf2_cfg_base; 902 903 u32 hw_config; 904 905 u32 bc_ver; 906 907 u8 int_block; 908#define INT_BLOCK_HC 0 909#define INT_BLOCK_IGU 1 910#define INT_BLOCK_MODE_NORMAL 0 911#define INT_BLOCK_MODE_BW_COMP 2 912#define CHIP_INT_MODE_IS_NBC(bp) \ 913 (!CHIP_IS_E1x(bp) && \ 914 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 915#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 916 917 u8 chip_port_mode; 918#define CHIP_4_PORT_MODE 0x0 919#define CHIP_2_PORT_MODE 0x1 920#define CHIP_PORT_MODE_NONE 0x2 921#define CHIP_MODE(bp) (bp->common.chip_port_mode) 922#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 923 924 u32 boot_mode; 925}; 926 927/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 928#define BNX2X_IGU_STAS_MSG_VF_CNT 64 929#define BNX2X_IGU_STAS_MSG_PF_CNT 4 930 931#define MAX_IGU_ATTN_ACK_TO 100 932/* end of common */ 933 934/* port */ 935 936struct bnx2x_port { 937 u32 pmf; 938 939 u32 link_config[LINK_CONFIG_SIZE]; 940 941 u32 supported[LINK_CONFIG_SIZE]; 942/* link settings - missing defines */ 943#define SUPPORTED_2500baseX_Full (1 << 15) 944 945 u32 advertising[LINK_CONFIG_SIZE]; 946/* link settings - missing defines */ 947#define ADVERTISED_2500baseX_Full (1 << 15) 948 949 u32 phy_addr; 950 951 /* used to synchronize phy accesses */ 952 struct mutex phy_mutex; 953 954 u32 port_stx; 955 956 struct nig_stats old_nig_stats; 957}; 958 959/* end of port */ 960 961#define STATS_OFFSET32(stat_name) \ 962 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 963 964/* slow path */ 965 966/* slow path work-queue */ 967extern struct workqueue_struct *bnx2x_wq; 968 969#define BNX2X_MAX_NUM_OF_VFS 64 970#define BNX2X_VF_CID_WND 0 971#define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND) 972#define BNX2X_FIRST_VF_CID 256 973#define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF) 974#define BNX2X_VF_ID_INVALID 0xFF 975 976/* 977 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 978 * control by the number of fast-path status blocks supported by the 979 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 980 * status block represents an independent interrupts context that can 981 * serve a regular L2 networking queue. However special L2 queues such 982 * as the FCoE queue do not require a FP-SB and other components like 983 * the CNIC may consume FP-SB reducing the number of possible L2 queues 984 * 985 * If the maximum number of FP-SB available is X then: 986 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 987 * regular L2 queues is Y=X-1 988 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 989 * c. If the FCoE L2 queue is supported the actual number of L2 queues 990 * is Y+1 991 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 992 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 993 * FP interrupt context for the CNIC). 994 * e. The number of HW context (CID count) is always X or X+1 if FCoE 995 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 996 */ 997 998/* fast-path interrupt contexts E1x */ 999#define FP_SB_MAX_E1x 16 1000/* fast-path interrupt contexts E2 */ 1001#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 1002 1003union cdu_context { 1004 struct eth_context eth; 1005 char pad[1024]; 1006}; 1007 1008/* CDU host DB constants */ 1009#define CDU_ILT_PAGE_SZ_HW 2 1010#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 1011#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 1012 1013#define CNIC_ISCSI_CID_MAX 256 1014#define CNIC_FCOE_CID_MAX 2048 1015#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1016#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1017 1018#define QM_ILT_PAGE_SZ_HW 0 1019#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1020#define QM_CID_ROUND 1024 1021 1022/* TM (timers) host DB constants */ 1023#define TM_ILT_PAGE_SZ_HW 0 1024#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1025/* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 1026#define TM_CONN_NUM 1024 1027#define TM_ILT_SZ (8 * TM_CONN_NUM) 1028#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1029 1030/* SRC (Searcher) host DB constants */ 1031#define SRC_ILT_PAGE_SZ_HW 0 1032#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1033#define SRC_HASH_BITS 10 1034#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1035#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1036#define SRC_T2_SZ SRC_ILT_SZ 1037#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1038 1039#define MAX_DMAE_C 8 1040 1041/* DMA memory not used in fastpath */ 1042struct bnx2x_slowpath { 1043 union { 1044 struct mac_configuration_cmd e1x; 1045 struct eth_classify_rules_ramrod_data e2; 1046 } mac_rdata; 1047 1048 1049 union { 1050 struct tstorm_eth_mac_filter_config e1x; 1051 struct eth_filter_rules_ramrod_data e2; 1052 } rx_mode_rdata; 1053 1054 union { 1055 struct mac_configuration_cmd e1; 1056 struct eth_multicast_rules_ramrod_data e2; 1057 } mcast_rdata; 1058 1059 struct eth_rss_update_ramrod_data rss_rdata; 1060 1061 /* Queue State related ramrods are always sent under rtnl_lock */ 1062 union { 1063 struct client_init_ramrod_data init_data; 1064 struct client_update_ramrod_data update_data; 1065 } q_rdata; 1066 1067 union { 1068 struct function_start_data func_start; 1069 /* pfc configuration for DCBX ramrod */ 1070 struct flow_control_configuration pfc_config; 1071 } func_rdata; 1072 1073 /* afex ramrod can not be a part of func_rdata union because these 1074 * events might arrive in parallel to other events from func_rdata. 1075 * Therefore, if they would have been defined in the same union, 1076 * data can get corrupted. 1077 */ 1078 struct afex_vif_list_ramrod_data func_afex_rdata; 1079 1080 /* used by dmae command executer */ 1081 struct dmae_command dmae[MAX_DMAE_C]; 1082 1083 u32 stats_comp; 1084 union mac_stats mac_stats; 1085 struct nig_stats nig_stats; 1086 struct host_port_stats port_stats; 1087 struct host_func_stats func_stats; 1088 1089 u32 wb_comp; 1090 u32 wb_data[4]; 1091 1092 union drv_info_to_mcp drv_info_to_mcp; 1093}; 1094 1095#define bnx2x_sp(bp, var) (&bp->slowpath->var) 1096#define bnx2x_sp_mapping(bp, var) \ 1097 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1098 1099 1100/* attn group wiring */ 1101#define MAX_DYNAMIC_ATTN_GRPS 8 1102 1103struct attn_route { 1104 u32 sig[5]; 1105}; 1106 1107struct iro { 1108 u32 base; 1109 u16 m1; 1110 u16 m2; 1111 u16 m3; 1112 u16 size; 1113}; 1114 1115struct hw_context { 1116 union cdu_context *vcxt; 1117 dma_addr_t cxt_mapping; 1118 size_t size; 1119}; 1120 1121/* forward */ 1122struct bnx2x_ilt; 1123 1124struct bnx2x_vfdb; 1125 1126enum bnx2x_recovery_state { 1127 BNX2X_RECOVERY_DONE, 1128 BNX2X_RECOVERY_INIT, 1129 BNX2X_RECOVERY_WAIT, 1130 BNX2X_RECOVERY_FAILED, 1131 BNX2X_RECOVERY_NIC_LOADING 1132}; 1133 1134/* 1135 * Event queue (EQ or event ring) MC hsi 1136 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1137 */ 1138#define NUM_EQ_PAGES 1 1139#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1140#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1141#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1142#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1143#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1144 1145/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1146#define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1147 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1148 1149/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1150#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1151 1152#define BNX2X_EQ_INDEX \ 1153 (&bp->def_status_blk->sp_sb.\ 1154 index_values[HC_SP_INDEX_EQ_CONS]) 1155 1156/* This is a data that will be used to create a link report message. 1157 * We will keep the data used for the last link report in order 1158 * to prevent reporting the same link parameters twice. 1159 */ 1160struct bnx2x_link_report_data { 1161 u16 line_speed; /* Effective line speed */ 1162 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1163}; 1164 1165enum { 1166 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1167 BNX2X_LINK_REPORT_LINK_DOWN, 1168 BNX2X_LINK_REPORT_RX_FC_ON, 1169 BNX2X_LINK_REPORT_TX_FC_ON, 1170}; 1171 1172enum { 1173 BNX2X_PORT_QUERY_IDX, 1174 BNX2X_PF_QUERY_IDX, 1175 BNX2X_FCOE_QUERY_IDX, 1176 BNX2X_FIRST_QUEUE_QUERY_IDX, 1177}; 1178 1179struct bnx2x_fw_stats_req { 1180 struct stats_query_header hdr; 1181 struct stats_query_entry query[FP_SB_MAX_E1x+ 1182 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1183}; 1184 1185struct bnx2x_fw_stats_data { 1186 struct stats_counter storm_counters; 1187 struct per_port_stats port; 1188 struct per_pf_stats pf; 1189 struct fcoe_statistics_params fcoe; 1190 struct per_queue_stats queue_stats[1]; 1191}; 1192 1193/* Public slow path states */ 1194enum { 1195 BNX2X_SP_RTNL_SETUP_TC, 1196 BNX2X_SP_RTNL_TX_TIMEOUT, 1197 BNX2X_SP_RTNL_AFEX_F_UPDATE, 1198 BNX2X_SP_RTNL_FAN_FAILURE, 1199 BNX2X_SP_RTNL_VFPF_MCAST, 1200 BNX2X_SP_RTNL_VFPF_STORM_RX_MODE, 1201}; 1202 1203 1204struct bnx2x_prev_path_list { 1205 u8 bus; 1206 u8 slot; 1207 u8 path; 1208 struct list_head list; 1209 u8 undi; 1210}; 1211 1212struct bnx2x_sp_objs { 1213 /* MACs object */ 1214 struct bnx2x_vlan_mac_obj mac_obj; 1215 1216 /* Queue State object */ 1217 struct bnx2x_queue_sp_obj q_obj; 1218}; 1219 1220struct bnx2x_fp_stats { 1221 struct tstorm_per_queue_stats old_tclient; 1222 struct ustorm_per_queue_stats old_uclient; 1223 struct xstorm_per_queue_stats old_xclient; 1224 struct bnx2x_eth_q_stats eth_q_stats; 1225 struct bnx2x_eth_q_stats_old eth_q_stats_old; 1226}; 1227 1228struct bnx2x { 1229 /* Fields used in the tx and intr/napi performance paths 1230 * are grouped together in the beginning of the structure 1231 */ 1232 struct bnx2x_fastpath *fp; 1233 struct bnx2x_sp_objs *sp_objs; 1234 struct bnx2x_fp_stats *fp_stats; 1235 struct bnx2x_fp_txdata *bnx2x_txq; 1236 void __iomem *regview; 1237 void __iomem *doorbells; 1238 u16 db_size; 1239 1240 u8 pf_num; /* absolute PF number */ 1241 u8 pfid; /* per-path PF number */ 1242 int base_fw_ndsb; /**/ 1243#define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1244#define BP_PORT(bp) (bp->pfid & 1) 1245#define BP_FUNC(bp) (bp->pfid) 1246#define BP_ABS_FUNC(bp) (bp->pf_num) 1247#define BP_VN(bp) ((bp)->pfid >> 1) 1248#define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1249#define BP_L_ID(bp) (BP_VN(bp) << 2) 1250#define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1251 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1252#define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1253 1254 /* vf pf channel mailbox contains request and response buffers */ 1255 struct bnx2x_vf_mbx_msg *vf2pf_mbox; 1256 dma_addr_t vf2pf_mbox_mapping; 1257 1258 /* we set aside a copy of the acquire response */ 1259 struct pfvf_acquire_resp_tlv acquire_resp; 1260 1261 struct net_device *dev; 1262 struct pci_dev *pdev; 1263 1264 const struct iro *iro_arr; 1265#define IRO (bp->iro_arr) 1266 1267 enum bnx2x_recovery_state recovery_state; 1268 int is_leader; 1269 struct msix_entry *msix_table; 1270 1271 int tx_ring_size; 1272 1273/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1274#define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1275#define ETH_MIN_PACKET_SIZE 60 1276#define ETH_MAX_PACKET_SIZE 1500 1277#define ETH_MAX_JUMBO_PACKET_SIZE 9600 1278/* TCP with Timestamp Option (32) + IPv6 (40) */ 1279#define ETH_MAX_TPA_HEADER_SIZE 72 1280 1281 /* Max supported alignment is 256 (8 shift) */ 1282#define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1283 1284 /* FW uses 2 Cache lines Alignment for start packet and size 1285 * 1286 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1287 * at the end of skb->data, to avoid wasting a full cache line. 1288 * This reduces memory use (skb->truesize). 1289 */ 1290#define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1291 1292#define BNX2X_FW_RX_ALIGN_END \ 1293 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \ 1294 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1295 1296#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1297 1298 struct host_sp_status_block *def_status_blk; 1299#define DEF_SB_IGU_ID 16 1300#define DEF_SB_ID HC_SP_SB_ID 1301 __le16 def_idx; 1302 __le16 def_att_idx; 1303 u32 attn_state; 1304 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1305 1306 /* slow path ring */ 1307 struct eth_spe *spq; 1308 dma_addr_t spq_mapping; 1309 u16 spq_prod_idx; 1310 struct eth_spe *spq_prod_bd; 1311 struct eth_spe *spq_last_bd; 1312 __le16 *dsb_sp_prod; 1313 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1314 /* used to synchronize spq accesses */ 1315 spinlock_t spq_lock; 1316 1317 /* event queue */ 1318 union event_ring_elem *eq_ring; 1319 dma_addr_t eq_mapping; 1320 u16 eq_prod; 1321 u16 eq_cons; 1322 __le16 *eq_cons_sb; 1323 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1324 1325 1326 1327 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1328 u16 stats_pending; 1329 /* Counter for completed statistics ramrods */ 1330 u16 stats_comp; 1331 1332 /* End of fields used in the performance code paths */ 1333 1334 int panic; 1335 int msg_enable; 1336 1337 u32 flags; 1338#define PCIX_FLAG (1 << 0) 1339#define PCI_32BIT_FLAG (1 << 1) 1340#define ONE_PORT_FLAG (1 << 2) 1341#define NO_WOL_FLAG (1 << 3) 1342#define USING_DAC_FLAG (1 << 4) 1343#define USING_MSIX_FLAG (1 << 5) 1344#define USING_MSI_FLAG (1 << 6) 1345#define DISABLE_MSI_FLAG (1 << 7) 1346#define TPA_ENABLE_FLAG (1 << 8) 1347#define NO_MCP_FLAG (1 << 9) 1348#define GRO_ENABLE_FLAG (1 << 10) 1349#define MF_FUNC_DIS (1 << 11) 1350#define OWN_CNIC_IRQ (1 << 12) 1351#define NO_ISCSI_OOO_FLAG (1 << 13) 1352#define NO_ISCSI_FLAG (1 << 14) 1353#define NO_FCOE_FLAG (1 << 15) 1354#define BC_SUPPORTS_PFC_STATS (1 << 17) 1355#define BC_SUPPORTS_FCOE_FEATURES (1 << 19) 1356#define USING_SINGLE_MSIX_FLAG (1 << 20) 1357#define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21) 1358#define IS_VF_FLAG (1 << 22) 1359 1360#define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG) 1361#define IS_VF(bp) ((bp)->flags & IS_VF_FLAG) 1362#define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG)) 1363 1364#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1365#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1366#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1367 1368 u8 cnic_support; 1369 bool cnic_enabled; 1370 bool cnic_loaded; 1371 struct cnic_eth_dev *(*cnic_probe)(struct net_device *); 1372 1373 /* Flag that indicates that we can start looking for FCoE L2 queue 1374 * completions in the default status block. 1375 */ 1376 bool fcoe_init; 1377 1378 int pm_cap; 1379 int mrrs; 1380 1381 struct delayed_work sp_task; 1382 struct delayed_work sp_rtnl_task; 1383 1384 struct delayed_work period_task; 1385 struct timer_list timer; 1386 int current_interval; 1387 1388 u16 fw_seq; 1389 u16 fw_drv_pulse_wr_seq; 1390 u32 func_stx; 1391 1392 struct link_params link_params; 1393 struct link_vars link_vars; 1394 u32 link_cnt; 1395 struct bnx2x_link_report_data last_reported_link; 1396 1397 struct mdio_if_info mdio; 1398 1399 struct bnx2x_common common; 1400 struct bnx2x_port port; 1401 1402 struct cmng_init cmng; 1403 1404 u32 mf_config[E1HVN_MAX]; 1405 u32 mf_ext_config; 1406 u32 path_has_ovlan; /* E3 */ 1407 u16 mf_ov; 1408 u8 mf_mode; 1409#define IS_MF(bp) (bp->mf_mode != 0) 1410#define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1411#define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1412#define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1413 1414 u8 wol; 1415 1416 int rx_ring_size; 1417 1418 u16 tx_quick_cons_trip_int; 1419 u16 tx_quick_cons_trip; 1420 u16 tx_ticks_int; 1421 u16 tx_ticks; 1422 1423 u16 rx_quick_cons_trip_int; 1424 u16 rx_quick_cons_trip; 1425 u16 rx_ticks_int; 1426 u16 rx_ticks; 1427/* Maximal coalescing timeout in us */ 1428#define BNX2X_MAX_COALESCE_TOUT (0xf0*12) 1429 1430 u32 lin_cnt; 1431 1432 u16 state; 1433#define BNX2X_STATE_CLOSED 0 1434#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1435#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1436#define BNX2X_STATE_OPEN 0x3000 1437#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1438#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1439 1440#define BNX2X_STATE_DIAG 0xe000 1441#define BNX2X_STATE_ERROR 0xf000 1442 1443#define BNX2X_MAX_PRIORITY 8 1444#define BNX2X_MAX_ENTRIES_PER_PRI 16 1445#define BNX2X_MAX_COS 3 1446#define BNX2X_MAX_TX_COS 2 1447 int num_queues; 1448 uint num_ethernet_queues; 1449 uint num_cnic_queues; 1450 int num_napi_queues; 1451 int disable_tpa; 1452 1453 u32 rx_mode; 1454#define BNX2X_RX_MODE_NONE 0 1455#define BNX2X_RX_MODE_NORMAL 1 1456#define BNX2X_RX_MODE_ALLMULTI 2 1457#define BNX2X_RX_MODE_PROMISC 3 1458#define BNX2X_MAX_MULTICAST 64 1459 1460 u8 igu_dsb_id; 1461 u8 igu_base_sb; 1462 u8 igu_sb_cnt; 1463 u8 min_msix_vec_cnt; 1464 1465 u32 igu_base_addr; 1466 dma_addr_t def_status_blk_mapping; 1467 1468 struct bnx2x_slowpath *slowpath; 1469 dma_addr_t slowpath_mapping; 1470 1471 /* Total number of FW statistics requests */ 1472 u8 fw_stats_num; 1473 1474 /* 1475 * This is a memory buffer that will contain both statistics 1476 * ramrod request and data. 1477 */ 1478 void *fw_stats; 1479 dma_addr_t fw_stats_mapping; 1480 1481 /* 1482 * FW statistics request shortcut (points at the 1483 * beginning of fw_stats buffer). 1484 */ 1485 struct bnx2x_fw_stats_req *fw_stats_req; 1486 dma_addr_t fw_stats_req_mapping; 1487 int fw_stats_req_sz; 1488 1489 /* 1490 * FW statistics data shortcut (points at the beginning of 1491 * fw_stats buffer + fw_stats_req_sz). 1492 */ 1493 struct bnx2x_fw_stats_data *fw_stats_data; 1494 dma_addr_t fw_stats_data_mapping; 1495 int fw_stats_data_sz; 1496 1497 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1498 * context size we need 8 ILT entries. 1499 */ 1500#define ILT_MAX_L2_LINES 8 1501 struct hw_context context[ILT_MAX_L2_LINES]; 1502 1503 struct bnx2x_ilt *ilt; 1504#define BP_ILT(bp) ((bp)->ilt) 1505#define ILT_MAX_LINES 256 1506/* 1507 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1508 * to CNIC. 1509 */ 1510#define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp)) 1511 1512/* 1513 * Maximum CID count that might be required by the bnx2x: 1514 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI 1515 */ 1516#define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \ 1517 + 2 * CNIC_SUPPORT(bp)) 1518#define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \ 1519 + 2 * CNIC_SUPPORT(bp)) 1520#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1521 ILT_PAGE_CIDS)) 1522 1523 int qm_cid_count; 1524 1525 bool dropless_fc; 1526 1527 void *t2; 1528 dma_addr_t t2_mapping; 1529 struct cnic_ops __rcu *cnic_ops; 1530 void *cnic_data; 1531 u32 cnic_tag; 1532 struct cnic_eth_dev cnic_eth_dev; 1533 union host_hc_status_block cnic_sb; 1534 dma_addr_t cnic_sb_mapping; 1535 struct eth_spe *cnic_kwq; 1536 struct eth_spe *cnic_kwq_prod; 1537 struct eth_spe *cnic_kwq_cons; 1538 struct eth_spe *cnic_kwq_last; 1539 u16 cnic_kwq_pending; 1540 u16 cnic_spq_pending; 1541 u8 fip_mac[ETH_ALEN]; 1542 struct mutex cnic_mutex; 1543 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1544 1545 /* Start index of the "special" (CNIC related) L2 cleints */ 1546 u8 cnic_base_cl_id; 1547 1548 int dmae_ready; 1549 /* used to synchronize dmae accesses */ 1550 spinlock_t dmae_lock; 1551 1552 /* used to protect the FW mail box */ 1553 struct mutex fw_mb_mutex; 1554 1555 /* used to synchronize stats collecting */ 1556 int stats_state; 1557 1558 /* used for synchronization of concurrent threads statistics handling */ 1559 spinlock_t stats_lock; 1560 1561 /* used by dmae command loader */ 1562 struct dmae_command stats_dmae; 1563 int executer_idx; 1564 1565 u16 stats_counter; 1566 struct bnx2x_eth_stats eth_stats; 1567 struct host_func_stats func_stats; 1568 struct bnx2x_eth_stats_old eth_stats_old; 1569 struct bnx2x_net_stats_old net_stats_old; 1570 struct bnx2x_fw_port_stats_old fw_stats_old; 1571 bool stats_init; 1572 1573 struct z_stream_s *strm; 1574 void *gunzip_buf; 1575 dma_addr_t gunzip_mapping; 1576 int gunzip_outlen; 1577#define FW_BUF_SIZE 0x8000 1578#define GUNZIP_BUF(bp) (bp->gunzip_buf) 1579#define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1580#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1581 1582 struct raw_op *init_ops; 1583 /* Init blocks offsets inside init_ops */ 1584 u16 *init_ops_offsets; 1585 /* Data blob - has 32 bit granularity */ 1586 u32 *init_data; 1587 u32 init_mode_flags; 1588#define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1589 /* Zipped PRAM blobs - raw data */ 1590 const u8 *tsem_int_table_data; 1591 const u8 *tsem_pram_data; 1592 const u8 *usem_int_table_data; 1593 const u8 *usem_pram_data; 1594 const u8 *xsem_int_table_data; 1595 const u8 *xsem_pram_data; 1596 const u8 *csem_int_table_data; 1597 const u8 *csem_pram_data; 1598#define INIT_OPS(bp) (bp->init_ops) 1599#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1600#define INIT_DATA(bp) (bp->init_data) 1601#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1602#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1603#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1604#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1605#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1606#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1607#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1608#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1609 1610#define PHY_FW_VER_LEN 20 1611 char fw_ver[32]; 1612 const struct firmware *firmware; 1613 1614 struct bnx2x_vfdb *vfdb; 1615#define IS_SRIOV(bp) ((bp)->vfdb) 1616 1617 /* DCB support on/off */ 1618 u16 dcb_state; 1619#define BNX2X_DCB_STATE_OFF 0 1620#define BNX2X_DCB_STATE_ON 1 1621 1622 /* DCBX engine mode */ 1623 int dcbx_enabled; 1624#define BNX2X_DCBX_ENABLED_OFF 0 1625#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1626#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1627#define BNX2X_DCBX_ENABLED_INVALID (-1) 1628 1629 bool dcbx_mode_uset; 1630 1631 struct bnx2x_config_dcbx_params dcbx_config_params; 1632 struct bnx2x_dcbx_port_params dcbx_port_params; 1633 int dcb_version; 1634 1635 /* CAM credit pools */ 1636 1637 /* used only in sriov */ 1638 struct bnx2x_credit_pool_obj vlans_pool; 1639 1640 struct bnx2x_credit_pool_obj macs_pool; 1641 1642 /* RX_MODE object */ 1643 struct bnx2x_rx_mode_obj rx_mode_obj; 1644 1645 /* MCAST object */ 1646 struct bnx2x_mcast_obj mcast_obj; 1647 1648 /* RSS configuration object */ 1649 struct bnx2x_rss_config_obj rss_conf_obj; 1650 1651 /* Function State controlling object */ 1652 struct bnx2x_func_sp_obj func_obj; 1653 1654 unsigned long sp_state; 1655 1656 /* operation indication for the sp_rtnl task */ 1657 unsigned long sp_rtnl_state; 1658 1659 /* DCBX Negotation results */ 1660 struct dcbx_features dcbx_local_feat; 1661 u32 dcbx_error; 1662 1663#ifdef BCM_DCBNL 1664 struct dcbx_features dcbx_remote_feat; 1665 u32 dcbx_remote_flags; 1666#endif 1667 /* AFEX: store default vlan used */ 1668 int afex_def_vlan_tag; 1669 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1670 u32 pending_max; 1671 1672 /* multiple tx classes of service */ 1673 u8 max_cos; 1674 1675 /* priority to cos mapping */ 1676 u8 prio_to_cos[8]; 1677}; 1678 1679/* Tx queues may be less or equal to Rx queues */ 1680extern int num_queues; 1681#define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1682#define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues) 1683#define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \ 1684 (bp)->num_cnic_queues) 1685#define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1686 1687#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1688 1689#define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1690/* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1691 1692#define RSS_IPV4_CAP_MASK \ 1693 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1694 1695#define RSS_IPV4_TCP_CAP_MASK \ 1696 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1697 1698#define RSS_IPV6_CAP_MASK \ 1699 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1700 1701#define RSS_IPV6_TCP_CAP_MASK \ 1702 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1703 1704/* func init flags */ 1705#define FUNC_FLG_RSS 0x0001 1706#define FUNC_FLG_STATS 0x0002 1707/* removed FUNC_FLG_UNMATCHED 0x0004 */ 1708#define FUNC_FLG_TPA 0x0008 1709#define FUNC_FLG_SPQ 0x0010 1710#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1711 1712 1713struct bnx2x_func_init_params { 1714 /* dma */ 1715 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1716 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1717 1718 u16 func_flgs; 1719 u16 func_id; /* abs fid */ 1720 u16 pf_id; 1721 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1722}; 1723 1724#define for_each_cnic_queue(bp, var) \ 1725 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1726 (var)++) \ 1727 if (skip_queue(bp, var)) \ 1728 continue; \ 1729 else 1730 1731#define for_each_eth_queue(bp, var) \ 1732 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1733 1734#define for_each_nondefault_eth_queue(bp, var) \ 1735 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1736 1737#define for_each_queue(bp, var) \ 1738 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1739 if (skip_queue(bp, var)) \ 1740 continue; \ 1741 else 1742 1743/* Skip forwarding FP */ 1744#define for_each_valid_rx_queue(bp, var) \ 1745 for ((var) = 0; \ 1746 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1747 BNX2X_NUM_ETH_QUEUES(bp)); \ 1748 (var)++) \ 1749 if (skip_rx_queue(bp, var)) \ 1750 continue; \ 1751 else 1752 1753#define for_each_rx_queue_cnic(bp, var) \ 1754 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1755 (var)++) \ 1756 if (skip_rx_queue(bp, var)) \ 1757 continue; \ 1758 else 1759 1760#define for_each_rx_queue(bp, var) \ 1761 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1762 if (skip_rx_queue(bp, var)) \ 1763 continue; \ 1764 else 1765 1766/* Skip OOO FP */ 1767#define for_each_valid_tx_queue(bp, var) \ 1768 for ((var) = 0; \ 1769 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \ 1770 BNX2X_NUM_ETH_QUEUES(bp)); \ 1771 (var)++) \ 1772 if (skip_tx_queue(bp, var)) \ 1773 continue; \ 1774 else 1775 1776#define for_each_tx_queue_cnic(bp, var) \ 1777 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \ 1778 (var)++) \ 1779 if (skip_tx_queue(bp, var)) \ 1780 continue; \ 1781 else 1782 1783#define for_each_tx_queue(bp, var) \ 1784 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1785 if (skip_tx_queue(bp, var)) \ 1786 continue; \ 1787 else 1788 1789#define for_each_nondefault_queue(bp, var) \ 1790 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1791 if (skip_queue(bp, var)) \ 1792 continue; \ 1793 else 1794 1795#define for_each_cos_in_tx_queue(fp, var) \ 1796 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1797 1798/* skip rx queue 1799 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1800 */ 1801#define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1802 1803/* skip tx queue 1804 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1805 */ 1806#define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1807 1808#define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1809 1810 1811 1812 1813/** 1814 * bnx2x_set_mac_one - configure a single MAC address 1815 * 1816 * @bp: driver handle 1817 * @mac: MAC to configure 1818 * @obj: MAC object handle 1819 * @set: if 'true' add a new MAC, otherwise - delete 1820 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 1821 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 1822 * 1823 * Configures one MAC according to provided parameters or continues the 1824 * execution of previously scheduled commands if RAMROD_CONT is set in 1825 * ramrod_flags. 1826 * 1827 * Returns zero if operation has successfully completed, a positive value if the 1828 * operation has been successfully scheduled and a negative - if a requested 1829 * operations has failed. 1830 */ 1831int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 1832 struct bnx2x_vlan_mac_obj *obj, bool set, 1833 int mac_type, unsigned long *ramrod_flags); 1834/** 1835 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 1836 * 1837 * @bp: driver handle 1838 * @mac_obj: MAC object handle 1839 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 1840 * @wait_for_comp: if 'true' block until completion 1841 * 1842 * Deletes all MACs of the specific type (e.g. ETH, UC list). 1843 * 1844 * Returns zero if operation has successfully completed, a positive value if the 1845 * operation has been successfully scheduled and a negative - if a requested 1846 * operations has failed. 1847 */ 1848int bnx2x_del_all_macs(struct bnx2x *bp, 1849 struct bnx2x_vlan_mac_obj *mac_obj, 1850 int mac_type, bool wait_for_comp); 1851 1852/* Init Function API */ 1853void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 1854u32 bnx2x_get_pretend_reg(struct bnx2x *bp); 1855int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 1856int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1857int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 1858int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1859void bnx2x_read_mf_cfg(struct bnx2x *bp); 1860 1861int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 1862 1863/* dmae */ 1864void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 1865void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 1866 u32 len32); 1867void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 1868u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 1869u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 1870u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 1871 bool with_comp, u8 comp_type); 1872 1873u8 bnx2x_is_pcie_pending(struct pci_dev *dev); 1874 1875void bnx2x_calc_fc_adv(struct bnx2x *bp); 1876int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 1877 u32 data_hi, u32 data_lo, int cmd_type); 1878void bnx2x_update_coalesce(struct bnx2x *bp); 1879int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 1880 1881static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 1882 int wait) 1883{ 1884 u32 val; 1885 1886 do { 1887 val = REG_RD(bp, reg); 1888 if (val == expected) 1889 break; 1890 ms -= wait; 1891 msleep(wait); 1892 1893 } while (ms > 0); 1894 1895 return val; 1896} 1897 1898void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, 1899 bool is_pf); 1900 1901#define BNX2X_ILT_ZALLOC(x, y, size) \ 1902 do { \ 1903 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 1904 if (x) \ 1905 memset(x, 0, size); \ 1906 } while (0) 1907 1908#define BNX2X_ILT_FREE(x, y, size) \ 1909 do { \ 1910 if (x) { \ 1911 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 1912 x = NULL; \ 1913 y = 0; \ 1914 } \ 1915 } while (0) 1916 1917#define ILOG2(x) (ilog2((x))) 1918 1919#define ILT_NUM_PAGE_ENTRIES (3072) 1920/* In 57710/11 we use whole table since we have 8 func 1921 * In 57712 we have only 4 func, but use same size per func, then only half of 1922 * the table in use 1923 */ 1924#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 1925 1926#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 1927/* 1928 * the phys address is shifted right 12 bits and has an added 1929 * 1=valid bit added to the 53rd bit 1930 * then since this is a wide register(TM) 1931 * we split it into two 32 bit writes 1932 */ 1933#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 1934#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 1935 1936/* load/unload mode */ 1937#define LOAD_NORMAL 0 1938#define LOAD_OPEN 1 1939#define LOAD_DIAG 2 1940#define LOAD_LOOPBACK_EXT 3 1941#define UNLOAD_NORMAL 0 1942#define UNLOAD_CLOSE 1 1943#define UNLOAD_RECOVERY 2 1944 1945 1946/* DMAE command defines */ 1947#define DMAE_TIMEOUT -1 1948#define DMAE_PCI_ERROR -2 /* E2 and onward */ 1949#define DMAE_NOT_RDY -3 1950#define DMAE_PCI_ERR_FLAG 0x80000000 1951 1952#define DMAE_SRC_PCI 0 1953#define DMAE_SRC_GRC 1 1954 1955#define DMAE_DST_NONE 0 1956#define DMAE_DST_PCI 1 1957#define DMAE_DST_GRC 2 1958 1959#define DMAE_COMP_PCI 0 1960#define DMAE_COMP_GRC 1 1961 1962/* E2 and onward - PCI error handling in the completion */ 1963 1964#define DMAE_COMP_REGULAR 0 1965#define DMAE_COM_SET_ERR 1 1966 1967#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 1968 DMAE_COMMAND_SRC_SHIFT) 1969#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 1970 DMAE_COMMAND_SRC_SHIFT) 1971 1972#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 1973 DMAE_COMMAND_DST_SHIFT) 1974#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 1975 DMAE_COMMAND_DST_SHIFT) 1976 1977#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 1978 DMAE_COMMAND_C_DST_SHIFT) 1979#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 1980 DMAE_COMMAND_C_DST_SHIFT) 1981 1982#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 1983 1984#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 1985#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 1986#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 1987#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 1988 1989#define DMAE_CMD_PORT_0 0 1990#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 1991 1992#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 1993#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 1994#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 1995 1996#define DMAE_SRC_PF 0 1997#define DMAE_SRC_VF 1 1998 1999#define DMAE_DST_PF 0 2000#define DMAE_DST_VF 1 2001 2002#define DMAE_C_SRC 0 2003#define DMAE_C_DST 1 2004 2005#define DMAE_LEN32_RD_MAX 0x80 2006#define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 2007 2008#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 2009 indicates eror */ 2010 2011#define MAX_DMAE_C_PER_PORT 8 2012#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2013 BP_VN(bp)) 2014#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 2015 E1HVN_MAX) 2016 2017/* PCIE link and speed */ 2018#define PCICFG_LINK_WIDTH 0x1f00000 2019#define PCICFG_LINK_WIDTH_SHIFT 20 2020#define PCICFG_LINK_SPEED 0xf0000 2021#define PCICFG_LINK_SPEED_SHIFT 16 2022 2023#define BNX2X_NUM_TESTS_SF 7 2024#define BNX2X_NUM_TESTS_MF 3 2025#define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \ 2026 BNX2X_NUM_TESTS_SF) 2027 2028#define BNX2X_PHY_LOOPBACK 0 2029#define BNX2X_MAC_LOOPBACK 1 2030#define BNX2X_EXT_LOOPBACK 2 2031#define BNX2X_PHY_LOOPBACK_FAILED 1 2032#define BNX2X_MAC_LOOPBACK_FAILED 2 2033#define BNX2X_EXT_LOOPBACK_FAILED 3 2034#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 2035 BNX2X_PHY_LOOPBACK_FAILED) 2036 2037 2038#define STROM_ASSERT_ARRAY_SIZE 50 2039 2040 2041/* must be used on a CID before placing it on a HW ring */ 2042#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 2043 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 2044 (x)) 2045 2046#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 2047#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 2048 2049 2050#define BNX2X_BTR 4 2051#define MAX_SPQ_PENDING 8 2052 2053/* CMNG constants, as derived from system spec calculations */ 2054/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 2055#define DEF_MIN_RATE 100 2056/* resolution of the rate shaping timer - 400 usec */ 2057#define RS_PERIODIC_TIMEOUT_USEC 400 2058/* number of bytes in single QM arbitration cycle - 2059 * coefficient for calculating the fairness timer */ 2060#define QM_ARB_BYTES 160000 2061/* resolution of Min algorithm 1:100 */ 2062#define MIN_RES 100 2063/* how many bytes above threshold for the minimal credit of Min algorithm*/ 2064#define MIN_ABOVE_THRESH 32768 2065/* Fairness algorithm integration time coefficient - 2066 * for calculating the actual Tfair */ 2067#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 2068/* Memory of fairness algorithm . 2 cycles */ 2069#define FAIR_MEM 2 2070 2071 2072#define ATTN_NIG_FOR_FUNC (1L << 8) 2073#define ATTN_SW_TIMER_4_FUNC (1L << 9) 2074#define GPIO_2_FUNC (1L << 10) 2075#define GPIO_3_FUNC (1L << 11) 2076#define GPIO_4_FUNC (1L << 12) 2077#define ATTN_GENERAL_ATTN_1 (1L << 13) 2078#define ATTN_GENERAL_ATTN_2 (1L << 14) 2079#define ATTN_GENERAL_ATTN_3 (1L << 15) 2080#define ATTN_GENERAL_ATTN_4 (1L << 13) 2081#define ATTN_GENERAL_ATTN_5 (1L << 14) 2082#define ATTN_GENERAL_ATTN_6 (1L << 15) 2083 2084#define ATTN_HARD_WIRED_MASK 0xff00 2085#define ATTENTION_ID 4 2086 2087 2088/* stuff added to make the code fit 80Col */ 2089 2090#define BNX2X_PMF_LINK_ASSERT \ 2091 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 2092 2093#define BNX2X_MC_ASSERT_BITS \ 2094 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2095 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2096 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2097 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2098 2099#define BNX2X_MCP_ASSERT \ 2100 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2101 2102#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2103#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2104 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2105 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2106 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2107 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2108 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2109 2110#define HW_INTERRUT_ASSERT_SET_0 \ 2111 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2112 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2113 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2114 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2115#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2116 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2117 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2118 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2119 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2120 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2121 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2122#define HW_INTERRUT_ASSERT_SET_1 \ 2123 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2124 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2125 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2126 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2127 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2128 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2129 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2130 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2131 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2132 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2133 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2134#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2135 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2136 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2137 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2138 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2139 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2140 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2141 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2142 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2143 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2144 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2145 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2146 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2147 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2148 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2149 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2150#define HW_INTERRUT_ASSERT_SET_2 \ 2151 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2152 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2153 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2154 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2155 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2156#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2157 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2158 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2159 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2160 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2161 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2162 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2163 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2164 2165#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2166 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2167 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2168 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2169 2170#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2171 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2172 2173#define MULTI_MASK 0x7f 2174 2175 2176#define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2177#define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2178#define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2179#define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2180 2181#define DEF_USB_IGU_INDEX_OFF \ 2182 offsetof(struct cstorm_def_status_block_u, igu_index) 2183#define DEF_CSB_IGU_INDEX_OFF \ 2184 offsetof(struct cstorm_def_status_block_c, igu_index) 2185#define DEF_XSB_IGU_INDEX_OFF \ 2186 offsetof(struct xstorm_def_status_block, igu_index) 2187#define DEF_TSB_IGU_INDEX_OFF \ 2188 offsetof(struct tstorm_def_status_block, igu_index) 2189 2190#define DEF_USB_SEGMENT_OFF \ 2191 offsetof(struct cstorm_def_status_block_u, segment) 2192#define DEF_CSB_SEGMENT_OFF \ 2193 offsetof(struct cstorm_def_status_block_c, segment) 2194#define DEF_XSB_SEGMENT_OFF \ 2195 offsetof(struct xstorm_def_status_block, segment) 2196#define DEF_TSB_SEGMENT_OFF \ 2197 offsetof(struct tstorm_def_status_block, segment) 2198 2199#define BNX2X_SP_DSB_INDEX \ 2200 (&bp->def_status_blk->sp_sb.\ 2201 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2202 2203#define SET_FLAG(value, mask, flag) \ 2204 do {\ 2205 (value) &= ~(mask);\ 2206 (value) |= ((flag) << (mask##_SHIFT));\ 2207 } while (0) 2208 2209#define GET_FLAG(value, mask) \ 2210 (((value) & (mask)) >> (mask##_SHIFT)) 2211 2212#define GET_FIELD(value, fname) \ 2213 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2214 2215#define CAM_IS_INVALID(x) \ 2216 (GET_FLAG(x.flags, \ 2217 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2218 (T_ETH_MAC_COMMAND_INVALIDATE)) 2219 2220/* Number of u32 elements in MC hash array */ 2221#define MC_HASH_SIZE 8 2222#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2223 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2224 2225 2226#ifndef PXP2_REG_PXP2_INT_STS 2227#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2228#endif 2229 2230#ifndef ETH_MAX_RX_CLIENTS_E2 2231#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2232#endif 2233 2234#define BNX2X_VPD_LEN 128 2235#define VENDOR_ID_LEN 4 2236 2237#define VF_ACQUIRE_THRESH 3 2238#define VF_ACQUIRE_MAC_FILTERS 1 2239#define VF_ACQUIRE_MC_FILTERS 10 2240 2241#define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \ 2242 (!((me_reg) & ME_REG_VF_ERR))) 2243int bnx2x_get_vf_id(struct bnx2x *bp, u32 *vf_id); 2244int bnx2x_send_msg2pf(struct bnx2x *bp, u8 *done, dma_addr_t msg_mapping); 2245int bnx2x_vfpf_acquire(struct bnx2x *bp, u8 tx_count, u8 rx_count); 2246int bnx2x_vfpf_release(struct bnx2x *bp); 2247int bnx2x_vfpf_init(struct bnx2x *bp); 2248void bnx2x_vfpf_close_vf(struct bnx2x *bp); 2249int bnx2x_vfpf_setup_q(struct bnx2x *bp, int fp_idx); 2250int bnx2x_vfpf_teardown_queue(struct bnx2x *bp, int qidx); 2251int bnx2x_vfpf_set_mac(struct bnx2x *bp); 2252int bnx2x_vfpf_set_mcast(struct net_device *dev); 2253int bnx2x_vfpf_storm_rx_mode(struct bnx2x *bp); 2254 2255int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code); 2256/* Congestion management fairness mode */ 2257#define CMNG_FNS_NONE 0 2258#define CMNG_FNS_MINMAX 1 2259 2260#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2261#define HC_SEG_ACCESS_ATTN 4 2262#define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2263 2264static const u32 dmae_reg_go_c[] = { 2265 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2266 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2267 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2268 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2269}; 2270 2271void bnx2x_set_ethtool_ops(struct net_device *netdev); 2272void bnx2x_notify_link_changed(struct bnx2x *bp); 2273 2274 2275#define BNX2X_MF_SD_PROTOCOL(bp) \ 2276 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2277 2278#define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 2279 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2280 2281#define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 2282 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 2283 2284#define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 2285#define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 2286 2287#define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \ 2288 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2289 2290#define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp)) 2291#define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \ 2292 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 2293 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2294 2295enum { 2296 SWITCH_UPDATE, 2297 AFEX_UPDATE, 2298}; 2299 2300#define NUM_MACS 8 2301 2302#endif /* bnx2x.h */ 2303