bnx2x.h revision e29ecd51de1683e6aeb88d76251f194b0311f749
1/* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14#ifndef BNX2X_H 15#define BNX2X_H 16#include <linux/netdevice.h> 17#include <linux/dma-mapping.h> 18#include <linux/types.h> 19 20/* compilation time flags */ 21 22/* define this to make the driver freeze on error to allow getting debug info 23 * (you will need to reboot afterwards) */ 24/* #define BNX2X_STOP_ON_ERROR */ 25 26#define DRV_MODULE_VERSION "1.72.50-0" 27#define DRV_MODULE_RELDATE "2012/04/23" 28#define BNX2X_BC_VER 0x040200 29 30#if defined(CONFIG_DCB) 31#define BCM_DCBNL 32#endif 33 34 35#include "bnx2x_hsi.h" 36 37#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) 38#define BCM_CNIC 1 39#include "../cnic_if.h" 40#endif 41 42#ifdef BCM_CNIC 43#define BNX2X_MIN_MSIX_VEC_CNT 3 44#define BNX2X_MSIX_VEC_FP_START 2 45#else 46#define BNX2X_MIN_MSIX_VEC_CNT 2 47#define BNX2X_MSIX_VEC_FP_START 1 48#endif 49 50#include <linux/mdio.h> 51 52#include "bnx2x_reg.h" 53#include "bnx2x_fw_defs.h" 54#include "bnx2x_hsi.h" 55#include "bnx2x_link.h" 56#include "bnx2x_sp.h" 57#include "bnx2x_dcb.h" 58#include "bnx2x_stats.h" 59 60/* error/debug prints */ 61 62#define DRV_MODULE_NAME "bnx2x" 63 64/* for messages that are currently off */ 65#define BNX2X_MSG_OFF 0x0 66#define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */ 67#define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */ 68#define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */ 69#define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */ 70#define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */ 71#define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */ 72#define BNX2X_MSG_IOV 0x0800000 73#define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/ 74#define BNX2X_MSG_ETHTOOL 0x4000000 75#define BNX2X_MSG_DCB 0x8000000 76 77/* regular debug print */ 78#define DP(__mask, fmt, ...) \ 79do { \ 80 if (unlikely(bp->msg_enable & (__mask))) \ 81 pr_notice("[%s:%d(%s)]" fmt, \ 82 __func__, __LINE__, \ 83 bp->dev ? (bp->dev->name) : "?", \ 84 ##__VA_ARGS__); \ 85} while (0) 86 87#define DP_CONT(__mask, fmt, ...) \ 88do { \ 89 if (unlikely(bp->msg_enable & (__mask))) \ 90 pr_cont(fmt, ##__VA_ARGS__); \ 91} while (0) 92 93/* errors debug print */ 94#define BNX2X_DBG_ERR(fmt, ...) \ 95do { \ 96 if (unlikely(netif_msg_probe(bp))) \ 97 pr_err("[%s:%d(%s)]" fmt, \ 98 __func__, __LINE__, \ 99 bp->dev ? (bp->dev->name) : "?", \ 100 ##__VA_ARGS__); \ 101} while (0) 102 103/* for errors (never masked) */ 104#define BNX2X_ERR(fmt, ...) \ 105do { \ 106 pr_err("[%s:%d(%s)]" fmt, \ 107 __func__, __LINE__, \ 108 bp->dev ? (bp->dev->name) : "?", \ 109 ##__VA_ARGS__); \ 110} while (0) 111 112#define BNX2X_ERROR(fmt, ...) \ 113 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 114 115 116/* before we have a dev->name use dev_info() */ 117#define BNX2X_DEV_INFO(fmt, ...) \ 118do { \ 119 if (unlikely(netif_msg_probe(bp))) \ 120 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 121} while (0) 122 123#ifdef BNX2X_STOP_ON_ERROR 124void bnx2x_int_disable(struct bnx2x *bp); 125#define bnx2x_panic() \ 126do { \ 127 bp->panic = 1; \ 128 BNX2X_ERR("driver assert\n"); \ 129 bnx2x_int_disable(bp); \ 130 bnx2x_panic_dump(bp); \ 131} while (0) 132#else 133#define bnx2x_panic() \ 134do { \ 135 bp->panic = 1; \ 136 BNX2X_ERR("driver assert\n"); \ 137 bnx2x_panic_dump(bp); \ 138} while (0) 139#endif 140 141#define bnx2x_mc_addr(ha) ((ha)->addr) 142#define bnx2x_uc_addr(ha) ((ha)->addr) 143 144#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) 145#define U64_HI(x) (u32)(((u64)(x)) >> 32) 146#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 147 148 149#define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 150 151#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 152#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 153#define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 154 155#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 156#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 157#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 158 159#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 160#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 161 162#define REG_RD_DMAE(bp, offset, valp, len32) \ 163 do { \ 164 bnx2x_read_dmae(bp, offset, len32);\ 165 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 166 } while (0) 167 168#define REG_WR_DMAE(bp, offset, valp, len32) \ 169 do { \ 170 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 171 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 172 offset, len32); \ 173 } while (0) 174 175#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 176 REG_WR_DMAE(bp, offset, valp, len32) 177 178#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 179 do { \ 180 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 181 bnx2x_write_big_buf_wb(bp, addr, len32); \ 182 } while (0) 183 184#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 185 offsetof(struct shmem_region, field)) 186#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 187#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 188 189#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 190 offsetof(struct shmem2_region, field)) 191#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 192#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 193#define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 194 offsetof(struct mf_cfg, field)) 195#define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 196 offsetof(struct mf2_cfg, field)) 197 198#define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 199#define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 200 MF_CFG_ADDR(bp, field), (val)) 201#define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 202 203#define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 204 (SHMEM2_RD((bp), size) > \ 205 offsetof(struct shmem2_region, field))) 206 207#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 208#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 209 210/* SP SB indices */ 211 212/* General SP events - stats query, cfc delete, etc */ 213#define HC_SP_INDEX_ETH_DEF_CONS 3 214 215/* EQ completions */ 216#define HC_SP_INDEX_EQ_CONS 7 217 218/* FCoE L2 connection completions */ 219#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 220#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 221/* iSCSI L2 */ 222#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 223#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 224 225/* Special clients parameters */ 226 227/* SB indices */ 228/* FCoE L2 */ 229#define BNX2X_FCOE_L2_RX_INDEX \ 230 (&bp->def_status_blk->sp_sb.\ 231 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 232 233#define BNX2X_FCOE_L2_TX_INDEX \ 234 (&bp->def_status_blk->sp_sb.\ 235 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 236 237/** 238 * CIDs and CLIDs: 239 * CLIDs below is a CLID for func 0, then the CLID for other 240 * functions will be calculated by the formula: 241 * 242 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 243 * 244 */ 245enum { 246 BNX2X_ISCSI_ETH_CL_ID_IDX, 247 BNX2X_FCOE_ETH_CL_ID_IDX, 248 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 249}; 250 251#define BNX2X_CNIC_START_ETH_CID 48 252enum { 253 /* iSCSI L2 */ 254 BNX2X_ISCSI_ETH_CID = BNX2X_CNIC_START_ETH_CID, 255 /* FCoE L2 */ 256 BNX2X_FCOE_ETH_CID, 257}; 258 259/** Additional rings budgeting */ 260#ifdef BCM_CNIC 261#define CNIC_PRESENT 1 262#define FCOE_PRESENT 1 263#else 264#define CNIC_PRESENT 0 265#define FCOE_PRESENT 0 266#endif /* BCM_CNIC */ 267#define NON_ETH_CONTEXT_USE (FCOE_PRESENT) 268 269#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 270 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 271 272#define SM_RX_ID 0 273#define SM_TX_ID 1 274 275/* defines for multiple tx priority indices */ 276#define FIRST_TX_ONLY_COS_INDEX 1 277#define FIRST_TX_COS_INDEX 0 278 279/* defines for decodeing the fastpath index and the cos index out of the 280 * transmission queue index 281 */ 282#define MAX_TXQS_PER_COS FP_SB_MAX_E1x 283 284#define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS) 285#define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS) 286 287/* rules for calculating the cids of tx-only connections */ 288#define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS) 289#define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS) 290 291/* fp index inside class of service range */ 292#define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS) 293 294/* 295 * 0..15 eth cos0 296 * 16..31 eth cos1 if applicable 297 * 32..47 eth cos2 If applicable 298 * fcoe queue follows eth queues (16, 32, 48 depending on cos) 299 */ 300#define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos) 301#define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp)) 302 303/* fast path */ 304/* 305 * This driver uses new build_skb() API : 306 * RX ring buffer contains pointer to kmalloc() data only, 307 * skb are built only after Hardware filled the frame. 308 */ 309struct sw_rx_bd { 310 u8 *data; 311 DEFINE_DMA_UNMAP_ADDR(mapping); 312}; 313 314struct sw_tx_bd { 315 struct sk_buff *skb; 316 u16 first_bd; 317 u8 flags; 318/* Set on the first BD descriptor when there is a split BD */ 319#define BNX2X_TSO_SPLIT_BD (1<<0) 320}; 321 322struct sw_rx_page { 323 struct page *page; 324 DEFINE_DMA_UNMAP_ADDR(mapping); 325}; 326 327union db_prod { 328 struct doorbell_set_prod data; 329 u32 raw; 330}; 331 332/* dropless fc FW/HW related params */ 333#define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 334#define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 335 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 336 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 337#define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 338#define FW_PREFETCH_CNT 16 339#define DROPLESS_FC_HEADROOM 100 340 341/* MC hsi */ 342#define BCM_PAGE_SHIFT 12 343#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 344#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 345#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 346 347#define PAGES_PER_SGE_SHIFT 0 348#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 349#define SGE_PAGE_SIZE PAGE_SIZE 350#define SGE_PAGE_SHIFT PAGE_SHIFT 351#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 352 353/* SGE ring related macros */ 354#define NUM_RX_SGE_PAGES 2 355#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 356#define NEXT_PAGE_SGE_DESC_CNT 2 357#define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 358/* RX_SGE_CNT is promised to be a power of 2 */ 359#define RX_SGE_MASK (RX_SGE_CNT - 1) 360#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 361#define MAX_RX_SGE (NUM_RX_SGE - 1) 362#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 363 (MAX_RX_SGE_CNT - 1)) ? \ 364 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 365 (x) + 1) 366#define RX_SGE(x) ((x) & MAX_RX_SGE) 367 368/* 369 * Number of required SGEs is the sum of two: 370 * 1. Number of possible opened aggregations (next packet for 371 * these aggregations will probably consume SGE immidiatelly) 372 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 373 * after placement on BD for new TPA aggregation) 374 * 375 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 376 */ 377#define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 378 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 379#define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 380 MAX_RX_SGE_CNT) 381#define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 382 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 383#define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 384 385/* Manipulate a bit vector defined as an array of u64 */ 386 387/* Number of bits in one sge_mask array element */ 388#define BIT_VEC64_ELEM_SZ 64 389#define BIT_VEC64_ELEM_SHIFT 6 390#define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 391 392 393#define __BIT_VEC64_SET_BIT(el, bit) \ 394 do { \ 395 el = ((el) | ((u64)0x1 << (bit))); \ 396 } while (0) 397 398#define __BIT_VEC64_CLEAR_BIT(el, bit) \ 399 do { \ 400 el = ((el) & (~((u64)0x1 << (bit)))); \ 401 } while (0) 402 403 404#define BIT_VEC64_SET_BIT(vec64, idx) \ 405 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 406 (idx) & BIT_VEC64_ELEM_MASK) 407 408#define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 409 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 410 (idx) & BIT_VEC64_ELEM_MASK) 411 412#define BIT_VEC64_TEST_BIT(vec64, idx) \ 413 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 414 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 415 416/* Creates a bitmask of all ones in less significant bits. 417 idx - index of the most significant bit in the created mask */ 418#define BIT_VEC64_ONES_MASK(idx) \ 419 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 420#define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 421 422/*******************************************************/ 423 424 425 426/* Number of u64 elements in SGE mask array */ 427#define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ) 428#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 429#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 430 431union host_hc_status_block { 432 /* pointer to fp status block e1x */ 433 struct host_hc_status_block_e1x *e1x_sb; 434 /* pointer to fp status block e2 */ 435 struct host_hc_status_block_e2 *e2_sb; 436}; 437 438struct bnx2x_agg_info { 439 /* 440 * First aggregation buffer is a data buffer, the following - are pages. 441 * We will preallocate the data buffer for each aggregation when 442 * we open the interface and will replace the BD at the consumer 443 * with this one when we receive the TPA_START CQE in order to 444 * keep the Rx BD ring consistent. 445 */ 446 struct sw_rx_bd first_buf; 447 u8 tpa_state; 448#define BNX2X_TPA_START 1 449#define BNX2X_TPA_STOP 2 450#define BNX2X_TPA_ERROR 3 451 u8 placement_offset; 452 u16 parsing_flags; 453 u16 vlan_tag; 454 u16 len_on_bd; 455 u32 rxhash; 456 u16 gro_size; 457 u16 full_page; 458}; 459 460#define Q_STATS_OFFSET32(stat_name) \ 461 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 462 463struct bnx2x_fp_txdata { 464 465 struct sw_tx_bd *tx_buf_ring; 466 467 union eth_tx_bd_types *tx_desc_ring; 468 dma_addr_t tx_desc_mapping; 469 470 u32 cid; 471 472 union db_prod tx_db; 473 474 u16 tx_pkt_prod; 475 u16 tx_pkt_cons; 476 u16 tx_bd_prod; 477 u16 tx_bd_cons; 478 479 unsigned long tx_pkt; 480 481 __le16 *tx_cons_sb; 482 483 int txq_index; 484}; 485 486enum bnx2x_tpa_mode_t { 487 TPA_MODE_LRO, 488 TPA_MODE_GRO 489}; 490 491struct bnx2x_fastpath { 492 struct bnx2x *bp; /* parent */ 493 494#define BNX2X_NAPI_WEIGHT 128 495 struct napi_struct napi; 496 union host_hc_status_block status_blk; 497 /* chip independed shortcuts into sb structure */ 498 __le16 *sb_index_values; 499 __le16 *sb_running_index; 500 /* chip independed shortcut into rx_prods_offset memory */ 501 u32 ustorm_rx_prods_offset; 502 503 u32 rx_buf_size; 504 505 dma_addr_t status_blk_mapping; 506 507 enum bnx2x_tpa_mode_t mode; 508 509 u8 max_cos; /* actual number of active tx coses */ 510 struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS]; 511 512 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 513 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 514 515 struct eth_rx_bd *rx_desc_ring; 516 dma_addr_t rx_desc_mapping; 517 518 union eth_rx_cqe *rx_comp_ring; 519 dma_addr_t rx_comp_mapping; 520 521 /* SGE ring */ 522 struct eth_rx_sge *rx_sge_ring; 523 dma_addr_t rx_sge_mapping; 524 525 u64 sge_mask[RX_SGE_MASK_LEN]; 526 527 u32 cid; 528 529 __le16 fp_hc_idx; 530 531 u8 index; /* number in fp array */ 532 u8 rx_queue; /* index for skb_record */ 533 u8 cl_id; /* eth client id */ 534 u8 cl_qzone_id; 535 u8 fw_sb_id; /* status block number in FW */ 536 u8 igu_sb_id; /* status block number in HW */ 537 538 u16 rx_bd_prod; 539 u16 rx_bd_cons; 540 u16 rx_comp_prod; 541 u16 rx_comp_cons; 542 u16 rx_sge_prod; 543 /* The last maximal completed SGE */ 544 u16 last_max_sge; 545 __le16 *rx_cons_sb; 546 unsigned long rx_pkt, 547 rx_calls; 548 549 /* TPA related */ 550 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 551 u8 disable_tpa; 552#ifdef BNX2X_STOP_ON_ERROR 553 u64 tpa_queue_used; 554#endif 555 556 struct tstorm_per_queue_stats old_tclient; 557 struct ustorm_per_queue_stats old_uclient; 558 struct xstorm_per_queue_stats old_xclient; 559 struct bnx2x_eth_q_stats eth_q_stats; 560 struct bnx2x_eth_q_stats_old eth_q_stats_old; 561 562 /* The size is calculated using the following: 563 sizeof name field from netdev structure + 564 4 ('-Xx-' string) + 565 4 (for the digits and to make it DWORD aligned) */ 566#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 567 char name[FP_NAME_SIZE]; 568 569 /* MACs object */ 570 struct bnx2x_vlan_mac_obj mac_obj; 571 572 /* Queue State object */ 573 struct bnx2x_queue_sp_obj q_obj; 574 575}; 576 577#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) 578 579/* Use 2500 as a mini-jumbo MTU for FCoE */ 580#define BNX2X_FCOE_MINI_JUMBO_MTU 2500 581 582/* FCoE L2 `fastpath' entry is right after the eth entries */ 583#define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp) 584#define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX]) 585#define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 586#define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 587 txdata[FIRST_TX_COS_INDEX].var) 588 589 590#define IS_ETH_FP(fp) (fp->index < \ 591 BNX2X_NUM_ETH_QUEUES(fp->bp)) 592#ifdef BCM_CNIC 593#define IS_FCOE_FP(fp) (fp->index == FCOE_IDX) 594#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX) 595#else 596#define IS_FCOE_FP(fp) false 597#define IS_FCOE_IDX(idx) false 598#endif 599 600 601/* MC hsi */ 602#define MAX_FETCH_BD 13 /* HW max BDs per packet */ 603#define RX_COPY_THRESH 92 604 605#define NUM_TX_RINGS 16 606#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 607#define NEXT_PAGE_TX_DESC_CNT 1 608#define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 609#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 610#define MAX_TX_BD (NUM_TX_BD - 1) 611#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 612#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 613 (MAX_TX_DESC_CNT - 1)) ? \ 614 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 615 (x) + 1) 616#define TX_BD(x) ((x) & MAX_TX_BD) 617#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 618 619/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 620#define NUM_RX_RINGS 8 621#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 622#define NEXT_PAGE_RX_DESC_CNT 2 623#define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 624#define RX_DESC_MASK (RX_DESC_CNT - 1) 625#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 626#define MAX_RX_BD (NUM_RX_BD - 1) 627#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 628 629/* dropless fc calculations for BDs 630 * 631 * Number of BDs should as number of buffers in BRB: 632 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 633 * "next" elements on each page 634 */ 635#define NUM_BD_REQ BRB_SIZE(bp) 636#define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 637 MAX_RX_DESC_CNT) 638#define BD_TH_LO(bp) (NUM_BD_REQ + \ 639 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 640 FW_DROP_LEVEL(bp)) 641#define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 642 643#define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 644 645#define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 646 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 647 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 648#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 649#define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 650#define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 651 MIN_RX_AVAIL)) 652 653#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 654 (MAX_RX_DESC_CNT - 1)) ? \ 655 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 656 (x) + 1) 657#define RX_BD(x) ((x) & MAX_RX_BD) 658 659/* 660 * As long as CQE is X times bigger than BD entry we have to allocate X times 661 * more pages for CQ ring in order to keep it balanced with BD ring 662 */ 663#define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 664#define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 665#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 666#define NEXT_PAGE_RCQ_DESC_CNT 1 667#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 668#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 669#define MAX_RCQ_BD (NUM_RCQ_BD - 1) 670#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 671#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 672 (MAX_RCQ_DESC_CNT - 1)) ? \ 673 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 674 (x) + 1) 675#define RCQ_BD(x) ((x) & MAX_RCQ_BD) 676 677/* dropless fc calculations for RCQs 678 * 679 * Number of RCQs should be as number of buffers in BRB: 680 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 681 * "next" elements on each page 682 */ 683#define NUM_RCQ_REQ BRB_SIZE(bp) 684#define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 685 MAX_RCQ_DESC_CNT) 686#define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 687 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 688 FW_DROP_LEVEL(bp)) 689#define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 690 691 692/* This is needed for determining of last_max */ 693#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 694#define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 695 696 697#define BNX2X_SWCID_SHIFT 17 698#define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 699 700/* used on a CID received from the HW */ 701#define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 702#define CQE_CMD(x) (le32_to_cpu(x) >> \ 703 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 704 705#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 706 le32_to_cpu((bd)->addr_lo)) 707#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 708 709#define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 710#define BNX2X_DB_SHIFT 7 /* 128 bytes*/ 711#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 712#error "Min DB doorbell stride is 8" 713#endif 714#define DPM_TRIGER_TYPE 0x40 715#define DOORBELL(bp, cid, val) \ 716 do { \ 717 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ 718 DPM_TRIGER_TYPE); \ 719 } while (0) 720 721 722/* TX CSUM helpers */ 723#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 724 skb->csum_offset) 725#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 726 skb->csum_offset)) 727 728#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) 729 730#define XMIT_PLAIN 0 731#define XMIT_CSUM_V4 0x1 732#define XMIT_CSUM_V6 0x2 733#define XMIT_CSUM_TCP 0x4 734#define XMIT_GSO_V4 0x8 735#define XMIT_GSO_V6 0x10 736 737#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) 738#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) 739 740 741/* stuff added to make the code fit 80Col */ 742#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 743#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 744#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 745#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 746#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 747 748#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 749 750#define BNX2X_IP_CSUM_ERR(cqe) \ 751 (!((cqe)->fast_path_cqe.status_flags & \ 752 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ 753 ((cqe)->fast_path_cqe.type_error_flags & \ 754 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) 755 756#define BNX2X_L4_CSUM_ERR(cqe) \ 757 (!((cqe)->fast_path_cqe.status_flags & \ 758 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ 759 ((cqe)->fast_path_cqe.type_error_flags & \ 760 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) 761 762#define BNX2X_RX_CSUM_OK(cqe) \ 763 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) 764 765#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 766 (((le16_to_cpu(flags) & \ 767 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 768 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 769 == PRS_FLAG_OVERETH_IPV4) 770#define BNX2X_RX_SUM_FIX(cqe) \ 771 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 772 773 774#define FP_USB_FUNC_OFF \ 775 offsetof(struct cstorm_status_block_u, func) 776#define FP_CSB_FUNC_OFF \ 777 offsetof(struct cstorm_status_block_c, func) 778 779#define HC_INDEX_ETH_RX_CQ_CONS 1 780 781#define HC_INDEX_OOO_TX_CQ_CONS 4 782 783#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 784 785#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 786 787#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 788 789#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 790 791#define BNX2X_RX_SB_INDEX \ 792 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 793 794#define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 795 796#define BNX2X_TX_SB_INDEX_COS0 \ 797 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 798 799/* end of fast path */ 800 801/* common */ 802 803struct bnx2x_common { 804 805 u32 chip_id; 806/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 807#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 808 809#define CHIP_NUM(bp) (bp->common.chip_id >> 16) 810#define CHIP_NUM_57710 0x164e 811#define CHIP_NUM_57711 0x164f 812#define CHIP_NUM_57711E 0x1650 813#define CHIP_NUM_57712 0x1662 814#define CHIP_NUM_57712_MF 0x1663 815#define CHIP_NUM_57713 0x1651 816#define CHIP_NUM_57713E 0x1652 817#define CHIP_NUM_57800 0x168a 818#define CHIP_NUM_57800_MF 0x16a5 819#define CHIP_NUM_57810 0x168e 820#define CHIP_NUM_57810_MF 0x16ae 821#define CHIP_NUM_57811 0x163d 822#define CHIP_NUM_57811_MF 0x163e 823#define CHIP_NUM_57840 0x168d 824#define CHIP_NUM_57840_MF 0x16ab 825#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 826#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 827#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 828#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 829#define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 830#define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 831#define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 832#define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 833#define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 834#define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811) 835#define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF) 836#define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840) 837#define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF) 838#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 839 CHIP_IS_57711E(bp)) 840#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 841 CHIP_IS_57712_MF(bp)) 842#define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 843 CHIP_IS_57800_MF(bp) || \ 844 CHIP_IS_57810(bp) || \ 845 CHIP_IS_57810_MF(bp) || \ 846 CHIP_IS_57811(bp) || \ 847 CHIP_IS_57811_MF(bp) || \ 848 CHIP_IS_57840(bp) || \ 849 CHIP_IS_57840_MF(bp)) 850#define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 851#define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 852#define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 853 854#define CHIP_REV_SHIFT 12 855#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 856#define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 857#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 858#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 859/* assume maximum 5 revisions */ 860#define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 861/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 862#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 863 !(CHIP_REV_VAL(bp) & 0x00001000)) 864/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 865#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 866 (CHIP_REV_VAL(bp) & 0x00001000)) 867 868#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 869 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 870 871#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 872#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 873#define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 874 (CHIP_REV_SHIFT + 1)) \ 875 << CHIP_REV_SHIFT) 876#define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 877 CHIP_REV_SIM(bp) :\ 878 CHIP_REV_VAL(bp)) 879#define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 880 (CHIP_REV(bp) == CHIP_REV_Bx)) 881#define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 882 (CHIP_REV(bp) == CHIP_REV_Ax)) 883 884 int flash_size; 885#define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 886#define BNX2X_NVRAM_TIMEOUT_COUNT 30000 887#define BNX2X_NVRAM_PAGE_SIZE 256 888 889 u32 shmem_base; 890 u32 shmem2_base; 891 u32 mf_cfg_base; 892 u32 mf2_cfg_base; 893 894 u32 hw_config; 895 896 u32 bc_ver; 897 898 u8 int_block; 899#define INT_BLOCK_HC 0 900#define INT_BLOCK_IGU 1 901#define INT_BLOCK_MODE_NORMAL 0 902#define INT_BLOCK_MODE_BW_COMP 2 903#define CHIP_INT_MODE_IS_NBC(bp) \ 904 (!CHIP_IS_E1x(bp) && \ 905 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 906#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 907 908 u8 chip_port_mode; 909#define CHIP_4_PORT_MODE 0x0 910#define CHIP_2_PORT_MODE 0x1 911#define CHIP_PORT_MODE_NONE 0x2 912#define CHIP_MODE(bp) (bp->common.chip_port_mode) 913#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 914 915 u32 boot_mode; 916}; 917 918/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 919#define BNX2X_IGU_STAS_MSG_VF_CNT 64 920#define BNX2X_IGU_STAS_MSG_PF_CNT 4 921 922/* end of common */ 923 924/* port */ 925 926struct bnx2x_port { 927 u32 pmf; 928 929 u32 link_config[LINK_CONFIG_SIZE]; 930 931 u32 supported[LINK_CONFIG_SIZE]; 932/* link settings - missing defines */ 933#define SUPPORTED_2500baseX_Full (1 << 15) 934 935 u32 advertising[LINK_CONFIG_SIZE]; 936/* link settings - missing defines */ 937#define ADVERTISED_2500baseX_Full (1 << 15) 938 939 u32 phy_addr; 940 941 /* used to synchronize phy accesses */ 942 struct mutex phy_mutex; 943 int need_hw_lock; 944 945 u32 port_stx; 946 947 struct nig_stats old_nig_stats; 948}; 949 950/* end of port */ 951 952#define STATS_OFFSET32(stat_name) \ 953 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 954 955/* slow path */ 956 957/* slow path work-queue */ 958extern struct workqueue_struct *bnx2x_wq; 959 960#define BNX2X_MAX_NUM_OF_VFS 64 961#define BNX2X_VF_ID_INVALID 0xFF 962 963/* 964 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 965 * control by the number of fast-path status blocks supported by the 966 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 967 * status block represents an independent interrupts context that can 968 * serve a regular L2 networking queue. However special L2 queues such 969 * as the FCoE queue do not require a FP-SB and other components like 970 * the CNIC may consume FP-SB reducing the number of possible L2 queues 971 * 972 * If the maximum number of FP-SB available is X then: 973 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 974 * regular L2 queues is Y=X-1 975 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 976 * c. If the FCoE L2 queue is supported the actual number of L2 queues 977 * is Y+1 978 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 979 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 980 * FP interrupt context for the CNIC). 981 * e. The number of HW context (CID count) is always X or X+1 if FCoE 982 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 983 */ 984 985/* fast-path interrupt contexts E1x */ 986#define FP_SB_MAX_E1x 16 987/* fast-path interrupt contexts E2 */ 988#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 989 990union cdu_context { 991 struct eth_context eth; 992 char pad[1024]; 993}; 994 995/* CDU host DB constants */ 996#define CDU_ILT_PAGE_SZ_HW 3 997#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */ 998#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 999 1000#ifdef BCM_CNIC 1001#define CNIC_ISCSI_CID_MAX 256 1002#define CNIC_FCOE_CID_MAX 2048 1003#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 1004#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 1005#endif 1006 1007#define QM_ILT_PAGE_SZ_HW 0 1008#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 1009#define QM_CID_ROUND 1024 1010 1011#ifdef BCM_CNIC 1012/* TM (timers) host DB constants */ 1013#define TM_ILT_PAGE_SZ_HW 0 1014#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 1015/* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 1016#define TM_CONN_NUM 1024 1017#define TM_ILT_SZ (8 * TM_CONN_NUM) 1018#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 1019 1020/* SRC (Searcher) host DB constants */ 1021#define SRC_ILT_PAGE_SZ_HW 0 1022#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 1023#define SRC_HASH_BITS 10 1024#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 1025#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 1026#define SRC_T2_SZ SRC_ILT_SZ 1027#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 1028 1029#endif 1030 1031#define MAX_DMAE_C 8 1032 1033/* DMA memory not used in fastpath */ 1034struct bnx2x_slowpath { 1035 union { 1036 struct mac_configuration_cmd e1x; 1037 struct eth_classify_rules_ramrod_data e2; 1038 } mac_rdata; 1039 1040 1041 union { 1042 struct tstorm_eth_mac_filter_config e1x; 1043 struct eth_filter_rules_ramrod_data e2; 1044 } rx_mode_rdata; 1045 1046 union { 1047 struct mac_configuration_cmd e1; 1048 struct eth_multicast_rules_ramrod_data e2; 1049 } mcast_rdata; 1050 1051 struct eth_rss_update_ramrod_data rss_rdata; 1052 1053 /* Queue State related ramrods are always sent under rtnl_lock */ 1054 union { 1055 struct client_init_ramrod_data init_data; 1056 struct client_update_ramrod_data update_data; 1057 } q_rdata; 1058 1059 union { 1060 struct function_start_data func_start; 1061 /* pfc configuration for DCBX ramrod */ 1062 struct flow_control_configuration pfc_config; 1063 } func_rdata; 1064 1065 /* afex ramrod can not be a part of func_rdata union because these 1066 * events might arrive in parallel to other events from func_rdata. 1067 * Therefore, if they would have been defined in the same union, 1068 * data can get corrupted. 1069 */ 1070 struct afex_vif_list_ramrod_data func_afex_rdata; 1071 1072 /* used by dmae command executer */ 1073 struct dmae_command dmae[MAX_DMAE_C]; 1074 1075 u32 stats_comp; 1076 union mac_stats mac_stats; 1077 struct nig_stats nig_stats; 1078 struct host_port_stats port_stats; 1079 struct host_func_stats func_stats; 1080 1081 u32 wb_comp; 1082 u32 wb_data[4]; 1083 1084 union drv_info_to_mcp drv_info_to_mcp; 1085}; 1086 1087#define bnx2x_sp(bp, var) (&bp->slowpath->var) 1088#define bnx2x_sp_mapping(bp, var) \ 1089 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1090 1091 1092/* attn group wiring */ 1093#define MAX_DYNAMIC_ATTN_GRPS 8 1094 1095struct attn_route { 1096 u32 sig[5]; 1097}; 1098 1099struct iro { 1100 u32 base; 1101 u16 m1; 1102 u16 m2; 1103 u16 m3; 1104 u16 size; 1105}; 1106 1107struct hw_context { 1108 union cdu_context *vcxt; 1109 dma_addr_t cxt_mapping; 1110 size_t size; 1111}; 1112 1113/* forward */ 1114struct bnx2x_ilt; 1115 1116 1117enum bnx2x_recovery_state { 1118 BNX2X_RECOVERY_DONE, 1119 BNX2X_RECOVERY_INIT, 1120 BNX2X_RECOVERY_WAIT, 1121 BNX2X_RECOVERY_FAILED, 1122 BNX2X_RECOVERY_NIC_LOADING 1123}; 1124 1125/* 1126 * Event queue (EQ or event ring) MC hsi 1127 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1128 */ 1129#define NUM_EQ_PAGES 1 1130#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1131#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1132#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1133#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1134#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1135 1136/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1137#define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1138 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1139 1140/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1141#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1142 1143#define BNX2X_EQ_INDEX \ 1144 (&bp->def_status_blk->sp_sb.\ 1145 index_values[HC_SP_INDEX_EQ_CONS]) 1146 1147/* This is a data that will be used to create a link report message. 1148 * We will keep the data used for the last link report in order 1149 * to prevent reporting the same link parameters twice. 1150 */ 1151struct bnx2x_link_report_data { 1152 u16 line_speed; /* Effective line speed */ 1153 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1154}; 1155 1156enum { 1157 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1158 BNX2X_LINK_REPORT_LINK_DOWN, 1159 BNX2X_LINK_REPORT_RX_FC_ON, 1160 BNX2X_LINK_REPORT_TX_FC_ON, 1161}; 1162 1163enum { 1164 BNX2X_PORT_QUERY_IDX, 1165 BNX2X_PF_QUERY_IDX, 1166 BNX2X_FCOE_QUERY_IDX, 1167 BNX2X_FIRST_QUEUE_QUERY_IDX, 1168}; 1169 1170struct bnx2x_fw_stats_req { 1171 struct stats_query_header hdr; 1172 struct stats_query_entry query[FP_SB_MAX_E1x+ 1173 BNX2X_FIRST_QUEUE_QUERY_IDX]; 1174}; 1175 1176struct bnx2x_fw_stats_data { 1177 struct stats_counter storm_counters; 1178 struct per_port_stats port; 1179 struct per_pf_stats pf; 1180 struct fcoe_statistics_params fcoe; 1181 struct per_queue_stats queue_stats[1]; 1182}; 1183 1184/* Public slow path states */ 1185enum { 1186 BNX2X_SP_RTNL_SETUP_TC, 1187 BNX2X_SP_RTNL_TX_TIMEOUT, 1188 BNX2X_SP_RTNL_AFEX_F_UPDATE, 1189 BNX2X_SP_RTNL_FAN_FAILURE, 1190}; 1191 1192 1193struct bnx2x_prev_path_list { 1194 u8 bus; 1195 u8 slot; 1196 u8 path; 1197 struct list_head list; 1198}; 1199 1200struct bnx2x { 1201 /* Fields used in the tx and intr/napi performance paths 1202 * are grouped together in the beginning of the structure 1203 */ 1204 struct bnx2x_fastpath *fp; 1205 void __iomem *regview; 1206 void __iomem *doorbells; 1207 u16 db_size; 1208 1209 u8 pf_num; /* absolute PF number */ 1210 u8 pfid; /* per-path PF number */ 1211 int base_fw_ndsb; /**/ 1212#define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1213#define BP_PORT(bp) (bp->pfid & 1) 1214#define BP_FUNC(bp) (bp->pfid) 1215#define BP_ABS_FUNC(bp) (bp->pf_num) 1216#define BP_VN(bp) ((bp)->pfid >> 1) 1217#define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1218#define BP_L_ID(bp) (BP_VN(bp) << 2) 1219#define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1220 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1221#define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1222 1223 struct net_device *dev; 1224 struct pci_dev *pdev; 1225 1226 const struct iro *iro_arr; 1227#define IRO (bp->iro_arr) 1228 1229 enum bnx2x_recovery_state recovery_state; 1230 int is_leader; 1231 struct msix_entry *msix_table; 1232 1233 int tx_ring_size; 1234 1235/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1236#define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1237#define ETH_MIN_PACKET_SIZE 60 1238#define ETH_MAX_PACKET_SIZE 1500 1239#define ETH_MAX_JUMBO_PACKET_SIZE 9600 1240/* TCP with Timestamp Option (32) + IPv6 (40) */ 1241#define ETH_MAX_TPA_HEADER_SIZE 72 1242 1243 /* Max supported alignment is 256 (8 shift) */ 1244#define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT) 1245 1246 /* FW uses 2 Cache lines Alignment for start packet and size 1247 * 1248 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes 1249 * at the end of skb->data, to avoid wasting a full cache line. 1250 * This reduces memory use (skb->truesize). 1251 */ 1252#define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT) 1253 1254#define BNX2X_FW_RX_ALIGN_END \ 1255 max(1UL << BNX2X_RX_ALIGN_SHIFT, \ 1256 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 1257 1258#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1259 1260 struct host_sp_status_block *def_status_blk; 1261#define DEF_SB_IGU_ID 16 1262#define DEF_SB_ID HC_SP_SB_ID 1263 __le16 def_idx; 1264 __le16 def_att_idx; 1265 u32 attn_state; 1266 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1267 1268 /* slow path ring */ 1269 struct eth_spe *spq; 1270 dma_addr_t spq_mapping; 1271 u16 spq_prod_idx; 1272 struct eth_spe *spq_prod_bd; 1273 struct eth_spe *spq_last_bd; 1274 __le16 *dsb_sp_prod; 1275 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1276 /* used to synchronize spq accesses */ 1277 spinlock_t spq_lock; 1278 1279 /* event queue */ 1280 union event_ring_elem *eq_ring; 1281 dma_addr_t eq_mapping; 1282 u16 eq_prod; 1283 u16 eq_cons; 1284 __le16 *eq_cons_sb; 1285 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1286 1287 1288 1289 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1290 u16 stats_pending; 1291 /* Counter for completed statistics ramrods */ 1292 u16 stats_comp; 1293 1294 /* End of fields used in the performance code paths */ 1295 1296 int panic; 1297 int msg_enable; 1298 1299 u32 flags; 1300#define PCIX_FLAG (1 << 0) 1301#define PCI_32BIT_FLAG (1 << 1) 1302#define ONE_PORT_FLAG (1 << 2) 1303#define NO_WOL_FLAG (1 << 3) 1304#define USING_DAC_FLAG (1 << 4) 1305#define USING_MSIX_FLAG (1 << 5) 1306#define USING_MSI_FLAG (1 << 6) 1307#define DISABLE_MSI_FLAG (1 << 7) 1308#define TPA_ENABLE_FLAG (1 << 8) 1309#define NO_MCP_FLAG (1 << 9) 1310 1311#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) 1312#define GRO_ENABLE_FLAG (1 << 10) 1313#define MF_FUNC_DIS (1 << 11) 1314#define OWN_CNIC_IRQ (1 << 12) 1315#define NO_ISCSI_OOO_FLAG (1 << 13) 1316#define NO_ISCSI_FLAG (1 << 14) 1317#define NO_FCOE_FLAG (1 << 15) 1318#define BC_SUPPORTS_PFC_STATS (1 << 17) 1319#define USING_SINGLE_MSIX_FLAG (1 << 20) 1320 1321#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1322#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1323#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1324 1325 int pm_cap; 1326 int mrrs; 1327 1328 struct delayed_work sp_task; 1329 struct delayed_work sp_rtnl_task; 1330 1331 struct delayed_work period_task; 1332 struct timer_list timer; 1333 int current_interval; 1334 1335 u16 fw_seq; 1336 u16 fw_drv_pulse_wr_seq; 1337 u32 func_stx; 1338 1339 struct link_params link_params; 1340 struct link_vars link_vars; 1341 u32 link_cnt; 1342 struct bnx2x_link_report_data last_reported_link; 1343 1344 struct mdio_if_info mdio; 1345 1346 struct bnx2x_common common; 1347 struct bnx2x_port port; 1348 1349 struct cmng_init cmng; 1350 1351 u32 mf_config[E1HVN_MAX]; 1352 u32 mf_ext_config; 1353 u32 path_has_ovlan; /* E3 */ 1354 u16 mf_ov; 1355 u8 mf_mode; 1356#define IS_MF(bp) (bp->mf_mode != 0) 1357#define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1358#define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1359#define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX) 1360 1361 u8 wol; 1362 1363 int rx_ring_size; 1364 1365 u16 tx_quick_cons_trip_int; 1366 u16 tx_quick_cons_trip; 1367 u16 tx_ticks_int; 1368 u16 tx_ticks; 1369 1370 u16 rx_quick_cons_trip_int; 1371 u16 rx_quick_cons_trip; 1372 u16 rx_ticks_int; 1373 u16 rx_ticks; 1374/* Maximal coalescing timeout in us */ 1375#define BNX2X_MAX_COALESCE_TOUT (0xf0*12) 1376 1377 u32 lin_cnt; 1378 1379 u16 state; 1380#define BNX2X_STATE_CLOSED 0 1381#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1382#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1383#define BNX2X_STATE_OPEN 0x3000 1384#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1385#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1386 1387#define BNX2X_STATE_DIAG 0xe000 1388#define BNX2X_STATE_ERROR 0xf000 1389 1390#define BNX2X_MAX_PRIORITY 8 1391#define BNX2X_MAX_ENTRIES_PER_PRI 16 1392#define BNX2X_MAX_COS 3 1393#define BNX2X_MAX_TX_COS 2 1394 int num_queues; 1395 int disable_tpa; 1396 1397 u32 rx_mode; 1398#define BNX2X_RX_MODE_NONE 0 1399#define BNX2X_RX_MODE_NORMAL 1 1400#define BNX2X_RX_MODE_ALLMULTI 2 1401#define BNX2X_RX_MODE_PROMISC 3 1402#define BNX2X_MAX_MULTICAST 64 1403 1404 u8 igu_dsb_id; 1405 u8 igu_base_sb; 1406 u8 igu_sb_cnt; 1407 dma_addr_t def_status_blk_mapping; 1408 1409 struct bnx2x_slowpath *slowpath; 1410 dma_addr_t slowpath_mapping; 1411 1412 /* Total number of FW statistics requests */ 1413 u8 fw_stats_num; 1414 1415 /* 1416 * This is a memory buffer that will contain both statistics 1417 * ramrod request and data. 1418 */ 1419 void *fw_stats; 1420 dma_addr_t fw_stats_mapping; 1421 1422 /* 1423 * FW statistics request shortcut (points at the 1424 * beginning of fw_stats buffer). 1425 */ 1426 struct bnx2x_fw_stats_req *fw_stats_req; 1427 dma_addr_t fw_stats_req_mapping; 1428 int fw_stats_req_sz; 1429 1430 /* 1431 * FW statistics data shortcut (points at the begining of 1432 * fw_stats buffer + fw_stats_req_sz). 1433 */ 1434 struct bnx2x_fw_stats_data *fw_stats_data; 1435 dma_addr_t fw_stats_data_mapping; 1436 int fw_stats_data_sz; 1437 1438 struct hw_context context; 1439 1440 struct bnx2x_ilt *ilt; 1441#define BP_ILT(bp) ((bp)->ilt) 1442#define ILT_MAX_LINES 256 1443/* 1444 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1445 * to CNIC. 1446 */ 1447#define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT) 1448 1449/* 1450 * Maximum CID count that might be required by the bnx2x: 1451 * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related) 1452 */ 1453#define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\ 1454 NON_ETH_CONTEXT_USE + CNIC_PRESENT) 1455#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1456 ILT_PAGE_CIDS)) 1457#define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT)) 1458 1459 int qm_cid_count; 1460 1461 int dropless_fc; 1462 1463#ifdef BCM_CNIC 1464 u32 cnic_flags; 1465#define BNX2X_CNIC_FLAG_MAC_SET 1 1466 void *t2; 1467 dma_addr_t t2_mapping; 1468 struct cnic_ops __rcu *cnic_ops; 1469 void *cnic_data; 1470 u32 cnic_tag; 1471 struct cnic_eth_dev cnic_eth_dev; 1472 union host_hc_status_block cnic_sb; 1473 dma_addr_t cnic_sb_mapping; 1474 struct eth_spe *cnic_kwq; 1475 struct eth_spe *cnic_kwq_prod; 1476 struct eth_spe *cnic_kwq_cons; 1477 struct eth_spe *cnic_kwq_last; 1478 u16 cnic_kwq_pending; 1479 u16 cnic_spq_pending; 1480 u8 fip_mac[ETH_ALEN]; 1481 struct mutex cnic_mutex; 1482 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1483 1484 /* Start index of the "special" (CNIC related) L2 cleints */ 1485 u8 cnic_base_cl_id; 1486#endif 1487 1488 int dmae_ready; 1489 /* used to synchronize dmae accesses */ 1490 spinlock_t dmae_lock; 1491 1492 /* used to protect the FW mail box */ 1493 struct mutex fw_mb_mutex; 1494 1495 /* used to synchronize stats collecting */ 1496 int stats_state; 1497 1498 /* used for synchronization of concurrent threads statistics handling */ 1499 spinlock_t stats_lock; 1500 1501 /* used by dmae command loader */ 1502 struct dmae_command stats_dmae; 1503 int executer_idx; 1504 1505 u16 stats_counter; 1506 struct bnx2x_eth_stats eth_stats; 1507 struct host_func_stats func_stats; 1508 struct bnx2x_eth_stats_old eth_stats_old; 1509 struct bnx2x_net_stats_old net_stats_old; 1510 struct bnx2x_fw_port_stats_old fw_stats_old; 1511 bool stats_init; 1512 1513 struct z_stream_s *strm; 1514 void *gunzip_buf; 1515 dma_addr_t gunzip_mapping; 1516 int gunzip_outlen; 1517#define FW_BUF_SIZE 0x8000 1518#define GUNZIP_BUF(bp) (bp->gunzip_buf) 1519#define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1520#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1521 1522 struct raw_op *init_ops; 1523 /* Init blocks offsets inside init_ops */ 1524 u16 *init_ops_offsets; 1525 /* Data blob - has 32 bit granularity */ 1526 u32 *init_data; 1527 u32 init_mode_flags; 1528#define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1529 /* Zipped PRAM blobs - raw data */ 1530 const u8 *tsem_int_table_data; 1531 const u8 *tsem_pram_data; 1532 const u8 *usem_int_table_data; 1533 const u8 *usem_pram_data; 1534 const u8 *xsem_int_table_data; 1535 const u8 *xsem_pram_data; 1536 const u8 *csem_int_table_data; 1537 const u8 *csem_pram_data; 1538#define INIT_OPS(bp) (bp->init_ops) 1539#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1540#define INIT_DATA(bp) (bp->init_data) 1541#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1542#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1543#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1544#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1545#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1546#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1547#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1548#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1549 1550#define PHY_FW_VER_LEN 20 1551 char fw_ver[32]; 1552 const struct firmware *firmware; 1553 1554 /* DCB support on/off */ 1555 u16 dcb_state; 1556#define BNX2X_DCB_STATE_OFF 0 1557#define BNX2X_DCB_STATE_ON 1 1558 1559 /* DCBX engine mode */ 1560 int dcbx_enabled; 1561#define BNX2X_DCBX_ENABLED_OFF 0 1562#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1563#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1564#define BNX2X_DCBX_ENABLED_INVALID (-1) 1565 1566 bool dcbx_mode_uset; 1567 1568 struct bnx2x_config_dcbx_params dcbx_config_params; 1569 struct bnx2x_dcbx_port_params dcbx_port_params; 1570 int dcb_version; 1571 1572 /* CAM credit pools */ 1573 struct bnx2x_credit_pool_obj macs_pool; 1574 1575 /* RX_MODE object */ 1576 struct bnx2x_rx_mode_obj rx_mode_obj; 1577 1578 /* MCAST object */ 1579 struct bnx2x_mcast_obj mcast_obj; 1580 1581 /* RSS configuration object */ 1582 struct bnx2x_rss_config_obj rss_conf_obj; 1583 1584 /* Function State controlling object */ 1585 struct bnx2x_func_sp_obj func_obj; 1586 1587 unsigned long sp_state; 1588 1589 /* operation indication for the sp_rtnl task */ 1590 unsigned long sp_rtnl_state; 1591 1592 /* DCBX Negotation results */ 1593 struct dcbx_features dcbx_local_feat; 1594 u32 dcbx_error; 1595 1596#ifdef BCM_DCBNL 1597 struct dcbx_features dcbx_remote_feat; 1598 u32 dcbx_remote_flags; 1599#endif 1600 /* AFEX: store default vlan used */ 1601 int afex_def_vlan_tag; 1602 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1603 u32 pending_max; 1604 1605 /* multiple tx classes of service */ 1606 u8 max_cos; 1607 1608 /* priority to cos mapping */ 1609 u8 prio_to_cos[8]; 1610}; 1611 1612/* Tx queues may be less or equal to Rx queues */ 1613extern int num_queues; 1614#define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1615#define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE) 1616#define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1617 1618#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1619 1620#define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1621/* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1622 1623#define RSS_IPV4_CAP_MASK \ 1624 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1625 1626#define RSS_IPV4_TCP_CAP_MASK \ 1627 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1628 1629#define RSS_IPV6_CAP_MASK \ 1630 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1631 1632#define RSS_IPV6_TCP_CAP_MASK \ 1633 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1634 1635/* func init flags */ 1636#define FUNC_FLG_RSS 0x0001 1637#define FUNC_FLG_STATS 0x0002 1638/* removed FUNC_FLG_UNMATCHED 0x0004 */ 1639#define FUNC_FLG_TPA 0x0008 1640#define FUNC_FLG_SPQ 0x0010 1641#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1642 1643 1644struct bnx2x_func_init_params { 1645 /* dma */ 1646 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1647 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1648 1649 u16 func_flgs; 1650 u16 func_id; /* abs fid */ 1651 u16 pf_id; 1652 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1653}; 1654 1655#define for_each_eth_queue(bp, var) \ 1656 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1657 1658#define for_each_nondefault_eth_queue(bp, var) \ 1659 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1660 1661#define for_each_queue(bp, var) \ 1662 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1663 if (skip_queue(bp, var)) \ 1664 continue; \ 1665 else 1666 1667/* Skip forwarding FP */ 1668#define for_each_rx_queue(bp, var) \ 1669 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1670 if (skip_rx_queue(bp, var)) \ 1671 continue; \ 1672 else 1673 1674/* Skip OOO FP */ 1675#define for_each_tx_queue(bp, var) \ 1676 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1677 if (skip_tx_queue(bp, var)) \ 1678 continue; \ 1679 else 1680 1681#define for_each_nondefault_queue(bp, var) \ 1682 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1683 if (skip_queue(bp, var)) \ 1684 continue; \ 1685 else 1686 1687#define for_each_cos_in_tx_queue(fp, var) \ 1688 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1689 1690/* skip rx queue 1691 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1692 */ 1693#define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1694 1695/* skip tx queue 1696 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1697 */ 1698#define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1699 1700#define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1701 1702 1703 1704 1705/** 1706 * bnx2x_set_mac_one - configure a single MAC address 1707 * 1708 * @bp: driver handle 1709 * @mac: MAC to configure 1710 * @obj: MAC object handle 1711 * @set: if 'true' add a new MAC, otherwise - delete 1712 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 1713 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 1714 * 1715 * Configures one MAC according to provided parameters or continues the 1716 * execution of previously scheduled commands if RAMROD_CONT is set in 1717 * ramrod_flags. 1718 * 1719 * Returns zero if operation has successfully completed, a positive value if the 1720 * operation has been successfully scheduled and a negative - if a requested 1721 * operations has failed. 1722 */ 1723int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 1724 struct bnx2x_vlan_mac_obj *obj, bool set, 1725 int mac_type, unsigned long *ramrod_flags); 1726/** 1727 * Deletes all MACs configured for the specific MAC object. 1728 * 1729 * @param bp Function driver instance 1730 * @param mac_obj MAC object to cleanup 1731 * 1732 * @return zero if all MACs were cleaned 1733 */ 1734 1735/** 1736 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 1737 * 1738 * @bp: driver handle 1739 * @mac_obj: MAC object handle 1740 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 1741 * @wait_for_comp: if 'true' block until completion 1742 * 1743 * Deletes all MACs of the specific type (e.g. ETH, UC list). 1744 * 1745 * Returns zero if operation has successfully completed, a positive value if the 1746 * operation has been successfully scheduled and a negative - if a requested 1747 * operations has failed. 1748 */ 1749int bnx2x_del_all_macs(struct bnx2x *bp, 1750 struct bnx2x_vlan_mac_obj *mac_obj, 1751 int mac_type, bool wait_for_comp); 1752 1753/* Init Function API */ 1754void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 1755int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 1756int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1757int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 1758int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1759void bnx2x_read_mf_cfg(struct bnx2x *bp); 1760 1761 1762/* dmae */ 1763void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 1764void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 1765 u32 len32); 1766void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 1767u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 1768u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 1769u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 1770 bool with_comp, u8 comp_type); 1771 1772 1773void bnx2x_calc_fc_adv(struct bnx2x *bp); 1774int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 1775 u32 data_hi, u32 data_lo, int cmd_type); 1776void bnx2x_update_coalesce(struct bnx2x *bp); 1777int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 1778 1779static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 1780 int wait) 1781{ 1782 u32 val; 1783 1784 do { 1785 val = REG_RD(bp, reg); 1786 if (val == expected) 1787 break; 1788 ms -= wait; 1789 msleep(wait); 1790 1791 } while (ms > 0); 1792 1793 return val; 1794} 1795 1796#define BNX2X_ILT_ZALLOC(x, y, size) \ 1797 do { \ 1798 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 1799 if (x) \ 1800 memset(x, 0, size); \ 1801 } while (0) 1802 1803#define BNX2X_ILT_FREE(x, y, size) \ 1804 do { \ 1805 if (x) { \ 1806 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 1807 x = NULL; \ 1808 y = 0; \ 1809 } \ 1810 } while (0) 1811 1812#define ILOG2(x) (ilog2((x))) 1813 1814#define ILT_NUM_PAGE_ENTRIES (3072) 1815/* In 57710/11 we use whole table since we have 8 func 1816 * In 57712 we have only 4 func, but use same size per func, then only half of 1817 * the table in use 1818 */ 1819#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 1820 1821#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 1822/* 1823 * the phys address is shifted right 12 bits and has an added 1824 * 1=valid bit added to the 53rd bit 1825 * then since this is a wide register(TM) 1826 * we split it into two 32 bit writes 1827 */ 1828#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 1829#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 1830 1831/* load/unload mode */ 1832#define LOAD_NORMAL 0 1833#define LOAD_OPEN 1 1834#define LOAD_DIAG 2 1835#define UNLOAD_NORMAL 0 1836#define UNLOAD_CLOSE 1 1837#define UNLOAD_RECOVERY 2 1838 1839 1840/* DMAE command defines */ 1841#define DMAE_TIMEOUT -1 1842#define DMAE_PCI_ERROR -2 /* E2 and onward */ 1843#define DMAE_NOT_RDY -3 1844#define DMAE_PCI_ERR_FLAG 0x80000000 1845 1846#define DMAE_SRC_PCI 0 1847#define DMAE_SRC_GRC 1 1848 1849#define DMAE_DST_NONE 0 1850#define DMAE_DST_PCI 1 1851#define DMAE_DST_GRC 2 1852 1853#define DMAE_COMP_PCI 0 1854#define DMAE_COMP_GRC 1 1855 1856/* E2 and onward - PCI error handling in the completion */ 1857 1858#define DMAE_COMP_REGULAR 0 1859#define DMAE_COM_SET_ERR 1 1860 1861#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 1862 DMAE_COMMAND_SRC_SHIFT) 1863#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 1864 DMAE_COMMAND_SRC_SHIFT) 1865 1866#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 1867 DMAE_COMMAND_DST_SHIFT) 1868#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 1869 DMAE_COMMAND_DST_SHIFT) 1870 1871#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 1872 DMAE_COMMAND_C_DST_SHIFT) 1873#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 1874 DMAE_COMMAND_C_DST_SHIFT) 1875 1876#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 1877 1878#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 1879#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 1880#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 1881#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 1882 1883#define DMAE_CMD_PORT_0 0 1884#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 1885 1886#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 1887#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 1888#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 1889 1890#define DMAE_SRC_PF 0 1891#define DMAE_SRC_VF 1 1892 1893#define DMAE_DST_PF 0 1894#define DMAE_DST_VF 1 1895 1896#define DMAE_C_SRC 0 1897#define DMAE_C_DST 1 1898 1899#define DMAE_LEN32_RD_MAX 0x80 1900#define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 1901 1902#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 1903 indicates eror */ 1904 1905#define MAX_DMAE_C_PER_PORT 8 1906#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1907 BP_VN(bp)) 1908#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1909 E1HVN_MAX) 1910 1911/* PCIE link and speed */ 1912#define PCICFG_LINK_WIDTH 0x1f00000 1913#define PCICFG_LINK_WIDTH_SHIFT 20 1914#define PCICFG_LINK_SPEED 0xf0000 1915#define PCICFG_LINK_SPEED_SHIFT 16 1916 1917 1918#define BNX2X_NUM_TESTS 7 1919 1920#define BNX2X_PHY_LOOPBACK 0 1921#define BNX2X_MAC_LOOPBACK 1 1922#define BNX2X_PHY_LOOPBACK_FAILED 1 1923#define BNX2X_MAC_LOOPBACK_FAILED 2 1924#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 1925 BNX2X_PHY_LOOPBACK_FAILED) 1926 1927 1928#define STROM_ASSERT_ARRAY_SIZE 50 1929 1930 1931/* must be used on a CID before placing it on a HW ring */ 1932#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 1933 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 1934 (x)) 1935 1936#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1937#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1938 1939 1940#define BNX2X_BTR 4 1941#define MAX_SPQ_PENDING 8 1942 1943/* CMNG constants, as derived from system spec calculations */ 1944/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 1945#define DEF_MIN_RATE 100 1946/* resolution of the rate shaping timer - 400 usec */ 1947#define RS_PERIODIC_TIMEOUT_USEC 400 1948/* number of bytes in single QM arbitration cycle - 1949 * coefficient for calculating the fairness timer */ 1950#define QM_ARB_BYTES 160000 1951/* resolution of Min algorithm 1:100 */ 1952#define MIN_RES 100 1953/* how many bytes above threshold for the minimal credit of Min algorithm*/ 1954#define MIN_ABOVE_THRESH 32768 1955/* Fairness algorithm integration time coefficient - 1956 * for calculating the actual Tfair */ 1957#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 1958/* Memory of fairness algorithm . 2 cycles */ 1959#define FAIR_MEM 2 1960 1961 1962#define ATTN_NIG_FOR_FUNC (1L << 8) 1963#define ATTN_SW_TIMER_4_FUNC (1L << 9) 1964#define GPIO_2_FUNC (1L << 10) 1965#define GPIO_3_FUNC (1L << 11) 1966#define GPIO_4_FUNC (1L << 12) 1967#define ATTN_GENERAL_ATTN_1 (1L << 13) 1968#define ATTN_GENERAL_ATTN_2 (1L << 14) 1969#define ATTN_GENERAL_ATTN_3 (1L << 15) 1970#define ATTN_GENERAL_ATTN_4 (1L << 13) 1971#define ATTN_GENERAL_ATTN_5 (1L << 14) 1972#define ATTN_GENERAL_ATTN_6 (1L << 15) 1973 1974#define ATTN_HARD_WIRED_MASK 0xff00 1975#define ATTENTION_ID 4 1976 1977 1978/* stuff added to make the code fit 80Col */ 1979 1980#define BNX2X_PMF_LINK_ASSERT \ 1981 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 1982 1983#define BNX2X_MC_ASSERT_BITS \ 1984 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1985 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1986 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1987 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 1988 1989#define BNX2X_MCP_ASSERT \ 1990 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 1991 1992#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 1993#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 1994 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 1995 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 1996 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 1997 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 1998 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 1999 2000#define HW_INTERRUT_ASSERT_SET_0 \ 2001 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 2002 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 2003 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 2004 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 2005#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 2006 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 2007 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 2008 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 2009 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 2010 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 2011 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 2012#define HW_INTERRUT_ASSERT_SET_1 \ 2013 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 2014 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 2015 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 2016 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 2017 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 2018 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 2019 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 2020 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 2021 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 2022 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 2023 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 2024#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 2025 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 2026 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 2027 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 2028 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 2029 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 2030 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 2031 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 2032 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 2033 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 2034 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 2035 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 2036 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 2037 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 2038 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 2039 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 2040#define HW_INTERRUT_ASSERT_SET_2 \ 2041 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 2042 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 2043 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 2044 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 2045 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 2046#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 2047 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 2048 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 2049 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 2050 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 2051 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 2052 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 2053 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 2054 2055#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 2056 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 2057 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 2058 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 2059 2060#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 2061 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 2062 2063#define MULTI_MASK 0x7f 2064 2065 2066#define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 2067#define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2068#define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2069#define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2070 2071#define DEF_USB_IGU_INDEX_OFF \ 2072 offsetof(struct cstorm_def_status_block_u, igu_index) 2073#define DEF_CSB_IGU_INDEX_OFF \ 2074 offsetof(struct cstorm_def_status_block_c, igu_index) 2075#define DEF_XSB_IGU_INDEX_OFF \ 2076 offsetof(struct xstorm_def_status_block, igu_index) 2077#define DEF_TSB_IGU_INDEX_OFF \ 2078 offsetof(struct tstorm_def_status_block, igu_index) 2079 2080#define DEF_USB_SEGMENT_OFF \ 2081 offsetof(struct cstorm_def_status_block_u, segment) 2082#define DEF_CSB_SEGMENT_OFF \ 2083 offsetof(struct cstorm_def_status_block_c, segment) 2084#define DEF_XSB_SEGMENT_OFF \ 2085 offsetof(struct xstorm_def_status_block, segment) 2086#define DEF_TSB_SEGMENT_OFF \ 2087 offsetof(struct tstorm_def_status_block, segment) 2088 2089#define BNX2X_SP_DSB_INDEX \ 2090 (&bp->def_status_blk->sp_sb.\ 2091 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2092 2093#define SET_FLAG(value, mask, flag) \ 2094 do {\ 2095 (value) &= ~(mask);\ 2096 (value) |= ((flag) << (mask##_SHIFT));\ 2097 } while (0) 2098 2099#define GET_FLAG(value, mask) \ 2100 (((value) & (mask)) >> (mask##_SHIFT)) 2101 2102#define GET_FIELD(value, fname) \ 2103 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2104 2105#define CAM_IS_INVALID(x) \ 2106 (GET_FLAG(x.flags, \ 2107 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2108 (T_ETH_MAC_COMMAND_INVALIDATE)) 2109 2110/* Number of u32 elements in MC hash array */ 2111#define MC_HASH_SIZE 8 2112#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2113 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2114 2115 2116#ifndef PXP2_REG_PXP2_INT_STS 2117#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2118#endif 2119 2120#ifndef ETH_MAX_RX_CLIENTS_E2 2121#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2122#endif 2123 2124#define BNX2X_VPD_LEN 128 2125#define VENDOR_ID_LEN 4 2126 2127/* Congestion management fairness mode */ 2128#define CMNG_FNS_NONE 0 2129#define CMNG_FNS_MINMAX 1 2130 2131#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2132#define HC_SEG_ACCESS_ATTN 4 2133#define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2134 2135static const u32 dmae_reg_go_c[] = { 2136 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2137 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2138 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2139 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2140}; 2141 2142void bnx2x_set_ethtool_ops(struct net_device *netdev); 2143void bnx2x_notify_link_changed(struct bnx2x *bp); 2144 2145 2146#define BNX2X_MF_SD_PROTOCOL(bp) \ 2147 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK) 2148 2149#ifdef BCM_CNIC 2150#define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \ 2151 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI) 2152 2153#define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \ 2154 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE) 2155 2156#define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) 2157#define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) 2158 2159#define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \ 2160 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) 2161 2162#define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp)) 2163#define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \ 2164 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \ 2165 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))) 2166#else 2167#define IS_MF_FCOE_AFEX(bp) false 2168#endif 2169 2170 2171#endif /* bnx2x.h */ 2172