bnx2x.h revision f233cafe1a9df8de75f446bc6f5dc715cc564325
1/* bnx2x.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 */ 13 14#ifndef BNX2X_H 15#define BNX2X_H 16#include <linux/netdevice.h> 17#include <linux/dma-mapping.h> 18#include <linux/types.h> 19 20/* compilation time flags */ 21 22/* define this to make the driver freeze on error to allow getting debug info 23 * (you will need to reboot afterwards) */ 24/* #define BNX2X_STOP_ON_ERROR */ 25 26#define DRV_MODULE_VERSION "1.70.30-0" 27#define DRV_MODULE_RELDATE "2011/10/25" 28#define BNX2X_BC_VER 0x040200 29 30#if defined(CONFIG_DCB) 31#define BCM_DCBNL 32#endif 33#if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE) 34#define BCM_CNIC 1 35#include "../cnic_if.h" 36#endif 37 38#ifdef BCM_CNIC 39#define BNX2X_MIN_MSIX_VEC_CNT 3 40#define BNX2X_MSIX_VEC_FP_START 2 41#else 42#define BNX2X_MIN_MSIX_VEC_CNT 2 43#define BNX2X_MSIX_VEC_FP_START 1 44#endif 45 46#include <linux/mdio.h> 47 48#include "bnx2x_reg.h" 49#include "bnx2x_fw_defs.h" 50#include "bnx2x_hsi.h" 51#include "bnx2x_link.h" 52#include "bnx2x_sp.h" 53#include "bnx2x_dcb.h" 54#include "bnx2x_stats.h" 55 56/* error/debug prints */ 57 58#define DRV_MODULE_NAME "bnx2x" 59 60/* for messages that are currently off */ 61#define BNX2X_MSG_OFF 0 62#define BNX2X_MSG_MCP 0x010000 /* was: NETIF_MSG_HW */ 63#define BNX2X_MSG_STATS 0x020000 /* was: NETIF_MSG_TIMER */ 64#define BNX2X_MSG_NVM 0x040000 /* was: NETIF_MSG_HW */ 65#define BNX2X_MSG_DMAE 0x080000 /* was: NETIF_MSG_HW */ 66#define BNX2X_MSG_SP 0x100000 /* was: NETIF_MSG_INTR */ 67#define BNX2X_MSG_FP 0x200000 /* was: NETIF_MSG_INTR */ 68 69/* regular debug print */ 70#define DP(__mask, fmt, ...) \ 71do { \ 72 if (bp->msg_enable & (__mask)) \ 73 pr_notice("[%s:%d(%s)]" fmt, \ 74 __func__, __LINE__, \ 75 bp->dev ? (bp->dev->name) : "?", \ 76 ##__VA_ARGS__); \ 77} while (0) 78 79#define DP_CONT(__mask, fmt, ...) \ 80do { \ 81 if (bp->msg_enable & (__mask)) \ 82 pr_cont(fmt, ##__VA_ARGS__); \ 83} while (0) 84 85/* errors debug print */ 86#define BNX2X_DBG_ERR(fmt, ...) \ 87do { \ 88 if (netif_msg_probe(bp)) \ 89 pr_err("[%s:%d(%s)]" fmt, \ 90 __func__, __LINE__, \ 91 bp->dev ? (bp->dev->name) : "?", \ 92 ##__VA_ARGS__); \ 93} while (0) 94 95/* for errors (never masked) */ 96#define BNX2X_ERR(fmt, ...) \ 97do { \ 98 pr_err("[%s:%d(%s)]" fmt, \ 99 __func__, __LINE__, \ 100 bp->dev ? (bp->dev->name) : "?", \ 101 ##__VA_ARGS__); \ 102} while (0) 103 104#define BNX2X_ERROR(fmt, ...) \ 105 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__) 106 107 108/* before we have a dev->name use dev_info() */ 109#define BNX2X_DEV_INFO(fmt, ...) \ 110do { \ 111 if (netif_msg_probe(bp)) \ 112 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \ 113} while (0) 114 115#ifdef BNX2X_STOP_ON_ERROR 116void bnx2x_int_disable(struct bnx2x *bp); 117#define bnx2x_panic() \ 118do { \ 119 bp->panic = 1; \ 120 BNX2X_ERR("driver assert\n"); \ 121 bnx2x_int_disable(bp); \ 122 bnx2x_panic_dump(bp); \ 123} while (0) 124#else 125#define bnx2x_panic() \ 126do { \ 127 bp->panic = 1; \ 128 BNX2X_ERR("driver assert\n"); \ 129 bnx2x_panic_dump(bp); \ 130} while (0) 131#endif 132 133#define bnx2x_mc_addr(ha) ((ha)->addr) 134#define bnx2x_uc_addr(ha) ((ha)->addr) 135 136#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff) 137#define U64_HI(x) (u32)(((u64)(x)) >> 32) 138#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo)) 139 140 141#define REG_ADDR(bp, offset) ((bp->regview) + (offset)) 142 143#define REG_RD(bp, offset) readl(REG_ADDR(bp, offset)) 144#define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset)) 145#define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset)) 146 147#define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset)) 148#define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset)) 149#define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset)) 150 151#define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset) 152#define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val) 153 154#define REG_RD_DMAE(bp, offset, valp, len32) \ 155 do { \ 156 bnx2x_read_dmae(bp, offset, len32);\ 157 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \ 158 } while (0) 159 160#define REG_WR_DMAE(bp, offset, valp, len32) \ 161 do { \ 162 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \ 163 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \ 164 offset, len32); \ 165 } while (0) 166 167#define REG_WR_DMAE_LEN(bp, offset, valp, len32) \ 168 REG_WR_DMAE(bp, offset, valp, len32) 169 170#define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \ 171 do { \ 172 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \ 173 bnx2x_write_big_buf_wb(bp, addr, len32); \ 174 } while (0) 175 176#define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \ 177 offsetof(struct shmem_region, field)) 178#define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field)) 179#define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val) 180 181#define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \ 182 offsetof(struct shmem2_region, field)) 183#define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field)) 184#define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val) 185#define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \ 186 offsetof(struct mf_cfg, field)) 187#define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \ 188 offsetof(struct mf2_cfg, field)) 189 190#define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field)) 191#define MF_CFG_WR(bp, field, val) REG_WR(bp,\ 192 MF_CFG_ADDR(bp, field), (val)) 193#define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field)) 194 195#define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \ 196 (SHMEM2_RD((bp), size) > \ 197 offsetof(struct shmem2_region, field))) 198 199#define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg) 200#define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val) 201 202/* SP SB indices */ 203 204/* General SP events - stats query, cfc delete, etc */ 205#define HC_SP_INDEX_ETH_DEF_CONS 3 206 207/* EQ completions */ 208#define HC_SP_INDEX_EQ_CONS 7 209 210/* FCoE L2 connection completions */ 211#define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 212#define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 213/* iSCSI L2 */ 214#define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 215#define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 216 217/* Special clients parameters */ 218 219/* SB indices */ 220/* FCoE L2 */ 221#define BNX2X_FCOE_L2_RX_INDEX \ 222 (&bp->def_status_blk->sp_sb.\ 223 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS]) 224 225#define BNX2X_FCOE_L2_TX_INDEX \ 226 (&bp->def_status_blk->sp_sb.\ 227 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS]) 228 229/** 230 * CIDs and CLIDs: 231 * CLIDs below is a CLID for func 0, then the CLID for other 232 * functions will be calculated by the formula: 233 * 234 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X 235 * 236 */ 237enum { 238 BNX2X_ISCSI_ETH_CL_ID_IDX, 239 BNX2X_FCOE_ETH_CL_ID_IDX, 240 BNX2X_MAX_CNIC_ETH_CL_ID_IDX, 241}; 242 243#define BNX2X_CNIC_START_ETH_CID 48 244enum { 245 /* iSCSI L2 */ 246 BNX2X_ISCSI_ETH_CID = BNX2X_CNIC_START_ETH_CID, 247 /* FCoE L2 */ 248 BNX2X_FCOE_ETH_CID, 249}; 250 251/** Additional rings budgeting */ 252#ifdef BCM_CNIC 253#define CNIC_PRESENT 1 254#define FCOE_PRESENT 1 255#else 256#define CNIC_PRESENT 0 257#define FCOE_PRESENT 0 258#endif /* BCM_CNIC */ 259#define NON_ETH_CONTEXT_USE (FCOE_PRESENT) 260 261#define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 262 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 263 264#define SM_RX_ID 0 265#define SM_TX_ID 1 266 267/* defines for multiple tx priority indices */ 268#define FIRST_TX_ONLY_COS_INDEX 1 269#define FIRST_TX_COS_INDEX 0 270 271/* defines for decodeing the fastpath index and the cos index out of the 272 * transmission queue index 273 */ 274#define MAX_TXQS_PER_COS FP_SB_MAX_E1x 275 276#define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS) 277#define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS) 278 279/* rules for calculating the cids of tx-only connections */ 280#define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS) 281#define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS) 282 283/* fp index inside class of service range */ 284#define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS) 285 286/* 287 * 0..15 eth cos0 288 * 16..31 eth cos1 if applicable 289 * 32..47 eth cos2 If applicable 290 * fcoe queue follows eth queues (16, 32, 48 depending on cos) 291 */ 292#define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos) 293#define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp)) 294 295/* fast path */ 296struct sw_rx_bd { 297 struct sk_buff *skb; 298 DEFINE_DMA_UNMAP_ADDR(mapping); 299}; 300 301struct sw_tx_bd { 302 struct sk_buff *skb; 303 u16 first_bd; 304 u8 flags; 305/* Set on the first BD descriptor when there is a split BD */ 306#define BNX2X_TSO_SPLIT_BD (1<<0) 307}; 308 309struct sw_rx_page { 310 struct page *page; 311 DEFINE_DMA_UNMAP_ADDR(mapping); 312}; 313 314union db_prod { 315 struct doorbell_set_prod data; 316 u32 raw; 317}; 318 319/* dropless fc FW/HW related params */ 320#define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512) 321#define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \ 322 ETH_MAX_AGGREGATION_QUEUES_E1 :\ 323 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 324#define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp)) 325#define FW_PREFETCH_CNT 16 326#define DROPLESS_FC_HEADROOM 100 327 328/* MC hsi */ 329#define BCM_PAGE_SHIFT 12 330#define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 331#define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 332#define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 333 334#define PAGES_PER_SGE_SHIFT 0 335#define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 336#define SGE_PAGE_SIZE PAGE_SIZE 337#define SGE_PAGE_SHIFT PAGE_SHIFT 338#define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr)) 339 340/* SGE ring related macros */ 341#define NUM_RX_SGE_PAGES 2 342#define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 343#define NEXT_PAGE_SGE_DESC_CNT 2 344#define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT) 345/* RX_SGE_CNT is promised to be a power of 2 */ 346#define RX_SGE_MASK (RX_SGE_CNT - 1) 347#define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES) 348#define MAX_RX_SGE (NUM_RX_SGE - 1) 349#define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \ 350 (MAX_RX_SGE_CNT - 1)) ? \ 351 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \ 352 (x) + 1) 353#define RX_SGE(x) ((x) & MAX_RX_SGE) 354 355/* 356 * Number of required SGEs is the sum of two: 357 * 1. Number of possible opened aggregations (next packet for 358 * these aggregations will probably consume SGE immidiatelly) 359 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 360 * after placement on BD for new TPA aggregation) 361 * 362 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page 363 */ 364#define NUM_SGE_REQ (MAX_AGG_QS(bp) + \ 365 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2) 366#define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \ 367 MAX_RX_SGE_CNT) 368#define SGE_TH_LO(bp) (NUM_SGE_REQ + \ 369 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT) 370#define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM) 371 372/* Manipulate a bit vector defined as an array of u64 */ 373 374/* Number of bits in one sge_mask array element */ 375#define BIT_VEC64_ELEM_SZ 64 376#define BIT_VEC64_ELEM_SHIFT 6 377#define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1) 378 379 380#define __BIT_VEC64_SET_BIT(el, bit) \ 381 do { \ 382 el = ((el) | ((u64)0x1 << (bit))); \ 383 } while (0) 384 385#define __BIT_VEC64_CLEAR_BIT(el, bit) \ 386 do { \ 387 el = ((el) & (~((u64)0x1 << (bit)))); \ 388 } while (0) 389 390 391#define BIT_VEC64_SET_BIT(vec64, idx) \ 392 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 393 (idx) & BIT_VEC64_ELEM_MASK) 394 395#define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 396 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 397 (idx) & BIT_VEC64_ELEM_MASK) 398 399#define BIT_VEC64_TEST_BIT(vec64, idx) \ 400 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 401 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 402 403/* Creates a bitmask of all ones in less significant bits. 404 idx - index of the most significant bit in the created mask */ 405#define BIT_VEC64_ONES_MASK(idx) \ 406 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 407#define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0)) 408 409/*******************************************************/ 410 411 412 413/* Number of u64 elements in SGE mask array */ 414#define RX_SGE_MASK_LEN ((NUM_RX_SGE_PAGES * RX_SGE_CNT) / \ 415 BIT_VEC64_ELEM_SZ) 416#define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 417#define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 418 419union host_hc_status_block { 420 /* pointer to fp status block e1x */ 421 struct host_hc_status_block_e1x *e1x_sb; 422 /* pointer to fp status block e2 */ 423 struct host_hc_status_block_e2 *e2_sb; 424}; 425 426struct bnx2x_agg_info { 427 /* 428 * First aggregation buffer is an skb, the following - are pages. 429 * We will preallocate the skbs for each aggregation when 430 * we open the interface and will replace the BD at the consumer 431 * with this one when we receive the TPA_START CQE in order to 432 * keep the Rx BD ring consistent. 433 */ 434 struct sw_rx_bd first_buf; 435 u8 tpa_state; 436#define BNX2X_TPA_START 1 437#define BNX2X_TPA_STOP 2 438#define BNX2X_TPA_ERROR 3 439 u8 placement_offset; 440 u16 parsing_flags; 441 u16 vlan_tag; 442 u16 len_on_bd; 443}; 444 445#define Q_STATS_OFFSET32(stat_name) \ 446 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4) 447 448struct bnx2x_fp_txdata { 449 450 struct sw_tx_bd *tx_buf_ring; 451 452 union eth_tx_bd_types *tx_desc_ring; 453 dma_addr_t tx_desc_mapping; 454 455 u32 cid; 456 457 union db_prod tx_db; 458 459 u16 tx_pkt_prod; 460 u16 tx_pkt_cons; 461 u16 tx_bd_prod; 462 u16 tx_bd_cons; 463 464 unsigned long tx_pkt; 465 466 __le16 *tx_cons_sb; 467 468 int txq_index; 469}; 470 471struct bnx2x_fastpath { 472 struct bnx2x *bp; /* parent */ 473 474#define BNX2X_NAPI_WEIGHT 128 475 struct napi_struct napi; 476 union host_hc_status_block status_blk; 477 /* chip independed shortcuts into sb structure */ 478 __le16 *sb_index_values; 479 __le16 *sb_running_index; 480 /* chip independed shortcut into rx_prods_offset memory */ 481 u32 ustorm_rx_prods_offset; 482 483 u32 rx_buf_size; 484 485 dma_addr_t status_blk_mapping; 486 487 u8 max_cos; /* actual number of active tx coses */ 488 struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS]; 489 490 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */ 491 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */ 492 493 struct eth_rx_bd *rx_desc_ring; 494 dma_addr_t rx_desc_mapping; 495 496 union eth_rx_cqe *rx_comp_ring; 497 dma_addr_t rx_comp_mapping; 498 499 /* SGE ring */ 500 struct eth_rx_sge *rx_sge_ring; 501 dma_addr_t rx_sge_mapping; 502 503 u64 sge_mask[RX_SGE_MASK_LEN]; 504 505 u32 cid; 506 507 __le16 fp_hc_idx; 508 509 u8 index; /* number in fp array */ 510 u8 rx_queue; /* index for skb_record */ 511 u8 cl_id; /* eth client id */ 512 u8 cl_qzone_id; 513 u8 fw_sb_id; /* status block number in FW */ 514 u8 igu_sb_id; /* status block number in HW */ 515 516 u16 rx_bd_prod; 517 u16 rx_bd_cons; 518 u16 rx_comp_prod; 519 u16 rx_comp_cons; 520 u16 rx_sge_prod; 521 /* The last maximal completed SGE */ 522 u16 last_max_sge; 523 __le16 *rx_cons_sb; 524 unsigned long rx_pkt, 525 rx_calls; 526 527 /* TPA related */ 528 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 529 u8 disable_tpa; 530#ifdef BNX2X_STOP_ON_ERROR 531 u64 tpa_queue_used; 532#endif 533 534 struct tstorm_per_queue_stats old_tclient; 535 struct ustorm_per_queue_stats old_uclient; 536 struct xstorm_per_queue_stats old_xclient; 537 struct bnx2x_eth_q_stats eth_q_stats; 538 539 /* The size is calculated using the following: 540 sizeof name field from netdev structure + 541 4 ('-Xx-' string) + 542 4 (for the digits and to make it DWORD aligned) */ 543#define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8) 544 char name[FP_NAME_SIZE]; 545 546 /* MACs object */ 547 struct bnx2x_vlan_mac_obj mac_obj; 548 549 /* Queue State object */ 550 struct bnx2x_queue_sp_obj q_obj; 551 552}; 553 554#define bnx2x_fp(bp, nr, var) (bp->fp[nr].var) 555 556/* Use 2500 as a mini-jumbo MTU for FCoE */ 557#define BNX2X_FCOE_MINI_JUMBO_MTU 2500 558 559/* FCoE L2 `fastpath' entry is right after the eth entries */ 560#define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp) 561#define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX]) 562#define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var) 563#define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \ 564 txdata[FIRST_TX_COS_INDEX].var) 565 566 567#define IS_ETH_FP(fp) (fp->index < \ 568 BNX2X_NUM_ETH_QUEUES(fp->bp)) 569#ifdef BCM_CNIC 570#define IS_FCOE_FP(fp) (fp->index == FCOE_IDX) 571#define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX) 572#else 573#define IS_FCOE_FP(fp) false 574#define IS_FCOE_IDX(idx) false 575#endif 576 577 578/* MC hsi */ 579#define MAX_FETCH_BD 13 /* HW max BDs per packet */ 580#define RX_COPY_THRESH 92 581 582#define NUM_TX_RINGS 16 583#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 584#define NEXT_PAGE_TX_DESC_CNT 1 585#define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT) 586#define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS) 587#define MAX_TX_BD (NUM_TX_BD - 1) 588#define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2) 589#define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \ 590 (MAX_TX_DESC_CNT - 1)) ? \ 591 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \ 592 (x) + 1) 593#define TX_BD(x) ((x) & MAX_TX_BD) 594#define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT) 595 596/* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */ 597#define NUM_RX_RINGS 8 598#define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 599#define NEXT_PAGE_RX_DESC_CNT 2 600#define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT) 601#define RX_DESC_MASK (RX_DESC_CNT - 1) 602#define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS) 603#define MAX_RX_BD (NUM_RX_BD - 1) 604#define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2) 605 606/* dropless fc calculations for BDs 607 * 608 * Number of BDs should as number of buffers in BRB: 609 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT 610 * "next" elements on each page 611 */ 612#define NUM_BD_REQ BRB_SIZE(bp) 613#define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \ 614 MAX_RX_DESC_CNT) 615#define BD_TH_LO(bp) (NUM_BD_REQ + \ 616 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \ 617 FW_DROP_LEVEL(bp)) 618#define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM) 619 620#define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128) 621 622#define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \ 623 ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 624 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 625#define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 626#define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL)) 627#define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\ 628 MIN_RX_AVAIL)) 629 630#define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \ 631 (MAX_RX_DESC_CNT - 1)) ? \ 632 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \ 633 (x) + 1) 634#define RX_BD(x) ((x) & MAX_RX_BD) 635 636/* 637 * As long as CQE is X times bigger than BD entry we have to allocate X times 638 * more pages for CQ ring in order to keep it balanced with BD ring 639 */ 640#define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd)) 641#define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL) 642#define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 643#define NEXT_PAGE_RCQ_DESC_CNT 1 644#define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT) 645#define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS) 646#define MAX_RCQ_BD (NUM_RCQ_BD - 1) 647#define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2) 648#define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \ 649 (MAX_RCQ_DESC_CNT - 1)) ? \ 650 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \ 651 (x) + 1) 652#define RCQ_BD(x) ((x) & MAX_RCQ_BD) 653 654/* dropless fc calculations for RCQs 655 * 656 * Number of RCQs should be as number of buffers in BRB: 657 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT 658 * "next" elements on each page 659 */ 660#define NUM_RCQ_REQ BRB_SIZE(bp) 661#define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \ 662 MAX_RCQ_DESC_CNT) 663#define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \ 664 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \ 665 FW_DROP_LEVEL(bp)) 666#define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM) 667 668 669/* This is needed for determining of last_max */ 670#define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b)) 671#define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b)) 672 673 674#define BNX2X_SWCID_SHIFT 17 675#define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1) 676 677/* used on a CID received from the HW */ 678#define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK) 679#define CQE_CMD(x) (le32_to_cpu(x) >> \ 680 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 681 682#define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \ 683 le32_to_cpu((bd)->addr_lo)) 684#define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes)) 685 686#define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */ 687#define BNX2X_DB_SHIFT 7 /* 128 bytes*/ 688#if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT) 689#error "Min DB doorbell stride is 8" 690#endif 691#define DPM_TRIGER_TYPE 0x40 692#define DOORBELL(bp, cid, val) \ 693 do { \ 694 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \ 695 DPM_TRIGER_TYPE); \ 696 } while (0) 697 698 699/* TX CSUM helpers */ 700#define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \ 701 skb->csum_offset) 702#define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \ 703 skb->csum_offset)) 704 705#define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff) 706 707#define XMIT_PLAIN 0 708#define XMIT_CSUM_V4 0x1 709#define XMIT_CSUM_V6 0x2 710#define XMIT_CSUM_TCP 0x4 711#define XMIT_GSO_V4 0x8 712#define XMIT_GSO_V6 0x10 713 714#define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6) 715#define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6) 716 717 718/* stuff added to make the code fit 80Col */ 719#define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 720#define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 721#define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 722#define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 723#define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 724 725#define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG 726 727#define BNX2X_IP_CSUM_ERR(cqe) \ 728 (!((cqe)->fast_path_cqe.status_flags & \ 729 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \ 730 ((cqe)->fast_path_cqe.type_error_flags & \ 731 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) 732 733#define BNX2X_L4_CSUM_ERR(cqe) \ 734 (!((cqe)->fast_path_cqe.status_flags & \ 735 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \ 736 ((cqe)->fast_path_cqe.type_error_flags & \ 737 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) 738 739#define BNX2X_RX_CSUM_OK(cqe) \ 740 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe))) 741 742#define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \ 743 (((le16_to_cpu(flags) & \ 744 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \ 745 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \ 746 == PRS_FLAG_OVERETH_IPV4) 747#define BNX2X_RX_SUM_FIX(cqe) \ 748 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags) 749 750 751#define FP_USB_FUNC_OFF \ 752 offsetof(struct cstorm_status_block_u, func) 753#define FP_CSB_FUNC_OFF \ 754 offsetof(struct cstorm_status_block_c, func) 755 756#define HC_INDEX_ETH_RX_CQ_CONS 1 757 758#define HC_INDEX_OOO_TX_CQ_CONS 4 759 760#define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 761 762#define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 763 764#define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 765 766#define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 767 768#define BNX2X_RX_SB_INDEX \ 769 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]) 770 771#define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0 772 773#define BNX2X_TX_SB_INDEX_COS0 \ 774 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]) 775 776/* end of fast path */ 777 778/* common */ 779 780struct bnx2x_common { 781 782 u32 chip_id; 783/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */ 784#define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0) 785 786#define CHIP_NUM(bp) (bp->common.chip_id >> 16) 787#define CHIP_NUM_57710 0x164e 788#define CHIP_NUM_57711 0x164f 789#define CHIP_NUM_57711E 0x1650 790#define CHIP_NUM_57712 0x1662 791#define CHIP_NUM_57712_MF 0x1663 792#define CHIP_NUM_57713 0x1651 793#define CHIP_NUM_57713E 0x1652 794#define CHIP_NUM_57800 0x168a 795#define CHIP_NUM_57800_MF 0x16a5 796#define CHIP_NUM_57810 0x168e 797#define CHIP_NUM_57810_MF 0x16ae 798#define CHIP_NUM_57840 0x168d 799#define CHIP_NUM_57840_MF 0x16ab 800#define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710) 801#define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711) 802#define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E) 803#define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712) 804#define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF) 805#define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800) 806#define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF) 807#define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810) 808#define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF) 809#define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840) 810#define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF) 811#define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \ 812 CHIP_IS_57711E(bp)) 813#define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \ 814 CHIP_IS_57712_MF(bp)) 815#define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \ 816 CHIP_IS_57800_MF(bp) || \ 817 CHIP_IS_57810(bp) || \ 818 CHIP_IS_57810_MF(bp) || \ 819 CHIP_IS_57840(bp) || \ 820 CHIP_IS_57840_MF(bp)) 821#define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp))) 822#define USES_WARPCORE(bp) (CHIP_IS_E3(bp)) 823#define IS_E1H_OFFSET (!CHIP_IS_E1(bp)) 824 825#define CHIP_REV_SHIFT 12 826#define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 827#define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK) 828#define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 829#define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 830/* assume maximum 5 revisions */ 831#define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000) 832/* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */ 833#define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 834 !(CHIP_REV_VAL(bp) & 0x00001000)) 835/* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */ 836#define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \ 837 (CHIP_REV_VAL(bp) & 0x00001000)) 838 839#define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \ 840 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1)) 841 842#define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0) 843#define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f) 844#define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\ 845 (CHIP_REV_SHIFT + 1)) \ 846 << CHIP_REV_SHIFT) 847#define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \ 848 CHIP_REV_SIM(bp) :\ 849 CHIP_REV_VAL(bp)) 850#define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \ 851 (CHIP_REV(bp) == CHIP_REV_Bx)) 852#define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \ 853 (CHIP_REV(bp) == CHIP_REV_Ax)) 854 855 int flash_size; 856#define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */ 857#define BNX2X_NVRAM_TIMEOUT_COUNT 30000 858#define BNX2X_NVRAM_PAGE_SIZE 256 859 860 u32 shmem_base; 861 u32 shmem2_base; 862 u32 mf_cfg_base; 863 u32 mf2_cfg_base; 864 865 u32 hw_config; 866 867 u32 bc_ver; 868 869 u8 int_block; 870#define INT_BLOCK_HC 0 871#define INT_BLOCK_IGU 1 872#define INT_BLOCK_MODE_NORMAL 0 873#define INT_BLOCK_MODE_BW_COMP 2 874#define CHIP_INT_MODE_IS_NBC(bp) \ 875 (!CHIP_IS_E1x(bp) && \ 876 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP)) 877#define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp)) 878 879 u8 chip_port_mode; 880#define CHIP_4_PORT_MODE 0x0 881#define CHIP_2_PORT_MODE 0x1 882#define CHIP_PORT_MODE_NONE 0x2 883#define CHIP_MODE(bp) (bp->common.chip_port_mode) 884#define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE) 885}; 886 887/* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 888#define BNX2X_IGU_STAS_MSG_VF_CNT 64 889#define BNX2X_IGU_STAS_MSG_PF_CNT 4 890 891/* end of common */ 892 893/* port */ 894 895struct bnx2x_port { 896 u32 pmf; 897 898 u32 link_config[LINK_CONFIG_SIZE]; 899 900 u32 supported[LINK_CONFIG_SIZE]; 901/* link settings - missing defines */ 902#define SUPPORTED_2500baseX_Full (1 << 15) 903 904 u32 advertising[LINK_CONFIG_SIZE]; 905/* link settings - missing defines */ 906#define ADVERTISED_2500baseX_Full (1 << 15) 907 908 u32 phy_addr; 909 910 /* used to synchronize phy accesses */ 911 struct mutex phy_mutex; 912 int need_hw_lock; 913 914 u32 port_stx; 915 916 struct nig_stats old_nig_stats; 917}; 918 919/* end of port */ 920 921#define STATS_OFFSET32(stat_name) \ 922 (offsetof(struct bnx2x_eth_stats, stat_name) / 4) 923 924/* slow path */ 925 926/* slow path work-queue */ 927extern struct workqueue_struct *bnx2x_wq; 928 929#define BNX2X_MAX_NUM_OF_VFS 64 930#define BNX2X_VF_ID_INVALID 0xFF 931 932/* 933 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 934 * control by the number of fast-path status blocks supported by the 935 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 936 * status block represents an independent interrupts context that can 937 * serve a regular L2 networking queue. However special L2 queues such 938 * as the FCoE queue do not require a FP-SB and other components like 939 * the CNIC may consume FP-SB reducing the number of possible L2 queues 940 * 941 * If the maximum number of FP-SB available is X then: 942 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 943 * regular L2 queues is Y=X-1 944 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 945 * c. If the FCoE L2 queue is supported the actual number of L2 queues 946 * is Y+1 947 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 948 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 949 * FP interrupt context for the CNIC). 950 * e. The number of HW context (CID count) is always X or X+1 if FCoE 951 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 952 */ 953 954/* fast-path interrupt contexts E1x */ 955#define FP_SB_MAX_E1x 16 956/* fast-path interrupt contexts E2 */ 957#define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 958 959union cdu_context { 960 struct eth_context eth; 961 char pad[1024]; 962}; 963 964/* CDU host DB constants */ 965#define CDU_ILT_PAGE_SZ_HW 3 966#define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */ 967#define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 968 969#ifdef BCM_CNIC 970#define CNIC_ISCSI_CID_MAX 256 971#define CNIC_FCOE_CID_MAX 2048 972#define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 973#define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 974#endif 975 976#define QM_ILT_PAGE_SZ_HW 0 977#define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 978#define QM_CID_ROUND 1024 979 980#ifdef BCM_CNIC 981/* TM (timers) host DB constants */ 982#define TM_ILT_PAGE_SZ_HW 0 983#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 984/* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 985#define TM_CONN_NUM 1024 986#define TM_ILT_SZ (8 * TM_CONN_NUM) 987#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 988 989/* SRC (Searcher) host DB constants */ 990#define SRC_ILT_PAGE_SZ_HW 0 991#define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 992#define SRC_HASH_BITS 10 993#define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 994#define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 995#define SRC_T2_SZ SRC_ILT_SZ 996#define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 997 998#endif 999 1000#define MAX_DMAE_C 8 1001 1002/* DMA memory not used in fastpath */ 1003struct bnx2x_slowpath { 1004 union { 1005 struct mac_configuration_cmd e1x; 1006 struct eth_classify_rules_ramrod_data e2; 1007 } mac_rdata; 1008 1009 1010 union { 1011 struct tstorm_eth_mac_filter_config e1x; 1012 struct eth_filter_rules_ramrod_data e2; 1013 } rx_mode_rdata; 1014 1015 union { 1016 struct mac_configuration_cmd e1; 1017 struct eth_multicast_rules_ramrod_data e2; 1018 } mcast_rdata; 1019 1020 struct eth_rss_update_ramrod_data rss_rdata; 1021 1022 /* Queue State related ramrods are always sent under rtnl_lock */ 1023 union { 1024 struct client_init_ramrod_data init_data; 1025 struct client_update_ramrod_data update_data; 1026 } q_rdata; 1027 1028 union { 1029 struct function_start_data func_start; 1030 /* pfc configuration for DCBX ramrod */ 1031 struct flow_control_configuration pfc_config; 1032 } func_rdata; 1033 1034 /* used by dmae command executer */ 1035 struct dmae_command dmae[MAX_DMAE_C]; 1036 1037 u32 stats_comp; 1038 union mac_stats mac_stats; 1039 struct nig_stats nig_stats; 1040 struct host_port_stats port_stats; 1041 struct host_func_stats func_stats; 1042 struct host_func_stats func_stats_base; 1043 1044 u32 wb_comp; 1045 u32 wb_data[4]; 1046}; 1047 1048#define bnx2x_sp(bp, var) (&bp->slowpath->var) 1049#define bnx2x_sp_mapping(bp, var) \ 1050 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var)) 1051 1052 1053/* attn group wiring */ 1054#define MAX_DYNAMIC_ATTN_GRPS 8 1055 1056struct attn_route { 1057 u32 sig[5]; 1058}; 1059 1060struct iro { 1061 u32 base; 1062 u16 m1; 1063 u16 m2; 1064 u16 m3; 1065 u16 size; 1066}; 1067 1068struct hw_context { 1069 union cdu_context *vcxt; 1070 dma_addr_t cxt_mapping; 1071 size_t size; 1072}; 1073 1074/* forward */ 1075struct bnx2x_ilt; 1076 1077 1078enum bnx2x_recovery_state { 1079 BNX2X_RECOVERY_DONE, 1080 BNX2X_RECOVERY_INIT, 1081 BNX2X_RECOVERY_WAIT, 1082 BNX2X_RECOVERY_FAILED 1083}; 1084 1085/* 1086 * Event queue (EQ or event ring) MC hsi 1087 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2 1088 */ 1089#define NUM_EQ_PAGES 1 1090#define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1091#define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1092#define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1093#define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1094#define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1095 1096/* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1097#define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \ 1098 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1) 1099 1100/* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1101#define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1102 1103#define BNX2X_EQ_INDEX \ 1104 (&bp->def_status_blk->sp_sb.\ 1105 index_values[HC_SP_INDEX_EQ_CONS]) 1106 1107/* This is a data that will be used to create a link report message. 1108 * We will keep the data used for the last link report in order 1109 * to prevent reporting the same link parameters twice. 1110 */ 1111struct bnx2x_link_report_data { 1112 u16 line_speed; /* Effective line speed */ 1113 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */ 1114}; 1115 1116enum { 1117 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */ 1118 BNX2X_LINK_REPORT_LINK_DOWN, 1119 BNX2X_LINK_REPORT_RX_FC_ON, 1120 BNX2X_LINK_REPORT_TX_FC_ON, 1121}; 1122 1123enum { 1124 BNX2X_PORT_QUERY_IDX, 1125 BNX2X_PF_QUERY_IDX, 1126 BNX2X_FIRST_QUEUE_QUERY_IDX, 1127}; 1128 1129struct bnx2x_fw_stats_req { 1130 struct stats_query_header hdr; 1131 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 1132}; 1133 1134struct bnx2x_fw_stats_data { 1135 struct stats_counter storm_counters; 1136 struct per_port_stats port; 1137 struct per_pf_stats pf; 1138 struct per_queue_stats queue_stats[1]; 1139}; 1140 1141/* Public slow path states */ 1142enum { 1143 BNX2X_SP_RTNL_SETUP_TC, 1144 BNX2X_SP_RTNL_TX_TIMEOUT, 1145}; 1146 1147 1148struct bnx2x { 1149 /* Fields used in the tx and intr/napi performance paths 1150 * are grouped together in the beginning of the structure 1151 */ 1152 struct bnx2x_fastpath *fp; 1153 void __iomem *regview; 1154 void __iomem *doorbells; 1155 u16 db_size; 1156 1157 u8 pf_num; /* absolute PF number */ 1158 u8 pfid; /* per-path PF number */ 1159 int base_fw_ndsb; /**/ 1160#define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1)) 1161#define BP_PORT(bp) (bp->pfid & 1) 1162#define BP_FUNC(bp) (bp->pfid) 1163#define BP_ABS_FUNC(bp) (bp->pf_num) 1164#define BP_VN(bp) ((bp)->pfid >> 1) 1165#define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4) 1166#define BP_L_ID(bp) (BP_VN(bp) << 2) 1167#define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\ 1168 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1169#define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp)) 1170 1171 struct net_device *dev; 1172 struct pci_dev *pdev; 1173 1174 const struct iro *iro_arr; 1175#define IRO (bp->iro_arr) 1176 1177 enum bnx2x_recovery_state recovery_state; 1178 int is_leader; 1179 struct msix_entry *msix_table; 1180 1181 int tx_ring_size; 1182 1183/* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 1184#define ETH_OVREHEAD (ETH_HLEN + 8 + 8) 1185#define ETH_MIN_PACKET_SIZE 60 1186#define ETH_MAX_PACKET_SIZE 1500 1187#define ETH_MAX_JUMBO_PACKET_SIZE 9600 1188 1189 /* Max supported alignment is 256 (8 shift) */ 1190#define BNX2X_RX_ALIGN_SHIFT ((L1_CACHE_SHIFT < 8) ? \ 1191 L1_CACHE_SHIFT : 8) 1192 /* FW use 2 Cache lines Alignment for start packet and size */ 1193#define BNX2X_FW_RX_ALIGN (2 << BNX2X_RX_ALIGN_SHIFT) 1194#define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5) 1195 1196 struct host_sp_status_block *def_status_blk; 1197#define DEF_SB_IGU_ID 16 1198#define DEF_SB_ID HC_SP_SB_ID 1199 __le16 def_idx; 1200 __le16 def_att_idx; 1201 u32 attn_state; 1202 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1203 1204 /* slow path ring */ 1205 struct eth_spe *spq; 1206 dma_addr_t spq_mapping; 1207 u16 spq_prod_idx; 1208 struct eth_spe *spq_prod_bd; 1209 struct eth_spe *spq_last_bd; 1210 __le16 *dsb_sp_prod; 1211 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */ 1212 /* used to synchronize spq accesses */ 1213 spinlock_t spq_lock; 1214 1215 /* event queue */ 1216 union event_ring_elem *eq_ring; 1217 dma_addr_t eq_mapping; 1218 u16 eq_prod; 1219 u16 eq_cons; 1220 __le16 *eq_cons_sb; 1221 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */ 1222 1223 1224 1225 /* Counter for marking that there is a STAT_QUERY ramrod pending */ 1226 u16 stats_pending; 1227 /* Counter for completed statistics ramrods */ 1228 u16 stats_comp; 1229 1230 /* End of fields used in the performance code paths */ 1231 1232 int panic; 1233 int msg_enable; 1234 1235 u32 flags; 1236#define PCIX_FLAG (1 << 0) 1237#define PCI_32BIT_FLAG (1 << 1) 1238#define ONE_PORT_FLAG (1 << 2) 1239#define NO_WOL_FLAG (1 << 3) 1240#define USING_DAC_FLAG (1 << 4) 1241#define USING_MSIX_FLAG (1 << 5) 1242#define USING_MSI_FLAG (1 << 6) 1243#define DISABLE_MSI_FLAG (1 << 7) 1244#define TPA_ENABLE_FLAG (1 << 8) 1245#define NO_MCP_FLAG (1 << 9) 1246 1247#define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG) 1248#define MF_FUNC_DIS (1 << 11) 1249#define OWN_CNIC_IRQ (1 << 12) 1250#define NO_ISCSI_OOO_FLAG (1 << 13) 1251#define NO_ISCSI_FLAG (1 << 14) 1252#define NO_FCOE_FLAG (1 << 15) 1253 1254#define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG) 1255#define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG) 1256#define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG) 1257 1258 int pm_cap; 1259 int mrrs; 1260 1261 struct delayed_work sp_task; 1262 struct delayed_work sp_rtnl_task; 1263 1264 struct delayed_work period_task; 1265 struct timer_list timer; 1266 int current_interval; 1267 1268 u16 fw_seq; 1269 u16 fw_drv_pulse_wr_seq; 1270 u32 func_stx; 1271 1272 struct link_params link_params; 1273 struct link_vars link_vars; 1274 u32 link_cnt; 1275 struct bnx2x_link_report_data last_reported_link; 1276 1277 struct mdio_if_info mdio; 1278 1279 struct bnx2x_common common; 1280 struct bnx2x_port port; 1281 1282 struct cmng_struct_per_port cmng; 1283 u32 vn_weight_sum; 1284 u32 mf_config[E1HVN_MAX]; 1285 u32 mf2_config[E2_FUNC_MAX]; 1286 u32 path_has_ovlan; /* E3 */ 1287 u16 mf_ov; 1288 u8 mf_mode; 1289#define IS_MF(bp) (bp->mf_mode != 0) 1290#define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI) 1291#define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD) 1292 1293 u8 wol; 1294 1295 int rx_ring_size; 1296 1297 u16 tx_quick_cons_trip_int; 1298 u16 tx_quick_cons_trip; 1299 u16 tx_ticks_int; 1300 u16 tx_ticks; 1301 1302 u16 rx_quick_cons_trip_int; 1303 u16 rx_quick_cons_trip; 1304 u16 rx_ticks_int; 1305 u16 rx_ticks; 1306/* Maximal coalescing timeout in us */ 1307#define BNX2X_MAX_COALESCE_TOUT (0xf0*12) 1308 1309 u32 lin_cnt; 1310 1311 u16 state; 1312#define BNX2X_STATE_CLOSED 0 1313#define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000 1314#define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000 1315#define BNX2X_STATE_OPEN 0x3000 1316#define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000 1317#define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000 1318 1319#define BNX2X_STATE_DIAG 0xe000 1320#define BNX2X_STATE_ERROR 0xf000 1321 1322 int multi_mode; 1323#define BNX2X_MAX_PRIORITY 8 1324#define BNX2X_MAX_ENTRIES_PER_PRI 16 1325#define BNX2X_MAX_COS 3 1326#define BNX2X_MAX_TX_COS 2 1327 int num_queues; 1328 int disable_tpa; 1329 1330 u32 rx_mode; 1331#define BNX2X_RX_MODE_NONE 0 1332#define BNX2X_RX_MODE_NORMAL 1 1333#define BNX2X_RX_MODE_ALLMULTI 2 1334#define BNX2X_RX_MODE_PROMISC 3 1335#define BNX2X_MAX_MULTICAST 64 1336 1337 u8 igu_dsb_id; 1338 u8 igu_base_sb; 1339 u8 igu_sb_cnt; 1340 dma_addr_t def_status_blk_mapping; 1341 1342 struct bnx2x_slowpath *slowpath; 1343 dma_addr_t slowpath_mapping; 1344 1345 /* Total number of FW statistics requests */ 1346 u8 fw_stats_num; 1347 1348 /* 1349 * This is a memory buffer that will contain both statistics 1350 * ramrod request and data. 1351 */ 1352 void *fw_stats; 1353 dma_addr_t fw_stats_mapping; 1354 1355 /* 1356 * FW statistics request shortcut (points at the 1357 * beginning of fw_stats buffer). 1358 */ 1359 struct bnx2x_fw_stats_req *fw_stats_req; 1360 dma_addr_t fw_stats_req_mapping; 1361 int fw_stats_req_sz; 1362 1363 /* 1364 * FW statistics data shortcut (points at the begining of 1365 * fw_stats buffer + fw_stats_req_sz). 1366 */ 1367 struct bnx2x_fw_stats_data *fw_stats_data; 1368 dma_addr_t fw_stats_data_mapping; 1369 int fw_stats_data_sz; 1370 1371 struct hw_context context; 1372 1373 struct bnx2x_ilt *ilt; 1374#define BP_ILT(bp) ((bp)->ilt) 1375#define ILT_MAX_LINES 256 1376/* 1377 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes 1378 * to CNIC. 1379 */ 1380#define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT) 1381 1382/* 1383 * Maximum CID count that might be required by the bnx2x: 1384 * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related) 1385 */ 1386#define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\ 1387 NON_ETH_CONTEXT_USE + CNIC_PRESENT) 1388#define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\ 1389 ILT_PAGE_CIDS)) 1390#define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT)) 1391 1392 int qm_cid_count; 1393 1394 int dropless_fc; 1395 1396#ifdef BCM_CNIC 1397 u32 cnic_flags; 1398#define BNX2X_CNIC_FLAG_MAC_SET 1 1399 void *t2; 1400 dma_addr_t t2_mapping; 1401 struct cnic_ops __rcu *cnic_ops; 1402 void *cnic_data; 1403 u32 cnic_tag; 1404 struct cnic_eth_dev cnic_eth_dev; 1405 union host_hc_status_block cnic_sb; 1406 dma_addr_t cnic_sb_mapping; 1407 struct eth_spe *cnic_kwq; 1408 struct eth_spe *cnic_kwq_prod; 1409 struct eth_spe *cnic_kwq_cons; 1410 struct eth_spe *cnic_kwq_last; 1411 u16 cnic_kwq_pending; 1412 u16 cnic_spq_pending; 1413 u8 fip_mac[ETH_ALEN]; 1414 struct mutex cnic_mutex; 1415 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj; 1416 1417 /* Start index of the "special" (CNIC related) L2 cleints */ 1418 u8 cnic_base_cl_id; 1419#endif 1420 1421 int dmae_ready; 1422 /* used to synchronize dmae accesses */ 1423 spinlock_t dmae_lock; 1424 1425 /* used to protect the FW mail box */ 1426 struct mutex fw_mb_mutex; 1427 1428 /* used to synchronize stats collecting */ 1429 int stats_state; 1430 1431 /* used for synchronization of concurrent threads statistics handling */ 1432 spinlock_t stats_lock; 1433 1434 /* used by dmae command loader */ 1435 struct dmae_command stats_dmae; 1436 int executer_idx; 1437 1438 u16 stats_counter; 1439 struct bnx2x_eth_stats eth_stats; 1440 1441 struct z_stream_s *strm; 1442 void *gunzip_buf; 1443 dma_addr_t gunzip_mapping; 1444 int gunzip_outlen; 1445#define FW_BUF_SIZE 0x8000 1446#define GUNZIP_BUF(bp) (bp->gunzip_buf) 1447#define GUNZIP_PHYS(bp) (bp->gunzip_mapping) 1448#define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen) 1449 1450 struct raw_op *init_ops; 1451 /* Init blocks offsets inside init_ops */ 1452 u16 *init_ops_offsets; 1453 /* Data blob - has 32 bit granularity */ 1454 u32 *init_data; 1455 u32 init_mode_flags; 1456#define INIT_MODE_FLAGS(bp) (bp->init_mode_flags) 1457 /* Zipped PRAM blobs - raw data */ 1458 const u8 *tsem_int_table_data; 1459 const u8 *tsem_pram_data; 1460 const u8 *usem_int_table_data; 1461 const u8 *usem_pram_data; 1462 const u8 *xsem_int_table_data; 1463 const u8 *xsem_pram_data; 1464 const u8 *csem_int_table_data; 1465 const u8 *csem_pram_data; 1466#define INIT_OPS(bp) (bp->init_ops) 1467#define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets) 1468#define INIT_DATA(bp) (bp->init_data) 1469#define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data) 1470#define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data) 1471#define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data) 1472#define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data) 1473#define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data) 1474#define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data) 1475#define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data) 1476#define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data) 1477 1478#define PHY_FW_VER_LEN 20 1479 char fw_ver[32]; 1480 const struct firmware *firmware; 1481 1482 /* DCB support on/off */ 1483 u16 dcb_state; 1484#define BNX2X_DCB_STATE_OFF 0 1485#define BNX2X_DCB_STATE_ON 1 1486 1487 /* DCBX engine mode */ 1488 int dcbx_enabled; 1489#define BNX2X_DCBX_ENABLED_OFF 0 1490#define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1 1491#define BNX2X_DCBX_ENABLED_ON_NEG_ON 2 1492#define BNX2X_DCBX_ENABLED_INVALID (-1) 1493 1494 bool dcbx_mode_uset; 1495 1496 struct bnx2x_config_dcbx_params dcbx_config_params; 1497 struct bnx2x_dcbx_port_params dcbx_port_params; 1498 int dcb_version; 1499 1500 /* CAM credit pools */ 1501 struct bnx2x_credit_pool_obj macs_pool; 1502 1503 /* RX_MODE object */ 1504 struct bnx2x_rx_mode_obj rx_mode_obj; 1505 1506 /* MCAST object */ 1507 struct bnx2x_mcast_obj mcast_obj; 1508 1509 /* RSS configuration object */ 1510 struct bnx2x_rss_config_obj rss_conf_obj; 1511 1512 /* Function State controlling object */ 1513 struct bnx2x_func_sp_obj func_obj; 1514 1515 unsigned long sp_state; 1516 1517 /* operation indication for the sp_rtnl task */ 1518 unsigned long sp_rtnl_state; 1519 1520 /* DCBX Negotation results */ 1521 struct dcbx_features dcbx_local_feat; 1522 u32 dcbx_error; 1523 1524#ifdef BCM_DCBNL 1525 struct dcbx_features dcbx_remote_feat; 1526 u32 dcbx_remote_flags; 1527#endif 1528 u32 pending_max; 1529 1530 /* multiple tx classes of service */ 1531 u8 max_cos; 1532 1533 /* priority to cos mapping */ 1534 u8 prio_to_cos[8]; 1535}; 1536 1537/* Tx queues may be less or equal to Rx queues */ 1538extern int num_queues; 1539#define BNX2X_NUM_QUEUES(bp) (bp->num_queues) 1540#define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE) 1541#define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp) 1542 1543#define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1) 1544 1545#define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp) 1546/* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */ 1547 1548#define RSS_IPV4_CAP_MASK \ 1549 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY 1550 1551#define RSS_IPV4_TCP_CAP_MASK \ 1552 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY 1553 1554#define RSS_IPV6_CAP_MASK \ 1555 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY 1556 1557#define RSS_IPV6_TCP_CAP_MASK \ 1558 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY 1559 1560/* func init flags */ 1561#define FUNC_FLG_RSS 0x0001 1562#define FUNC_FLG_STATS 0x0002 1563/* removed FUNC_FLG_UNMATCHED 0x0004 */ 1564#define FUNC_FLG_TPA 0x0008 1565#define FUNC_FLG_SPQ 0x0010 1566#define FUNC_FLG_LEADING 0x0020 /* PF only */ 1567 1568 1569struct bnx2x_func_init_params { 1570 /* dma */ 1571 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */ 1572 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */ 1573 1574 u16 func_flgs; 1575 u16 func_id; /* abs fid */ 1576 u16 pf_id; 1577 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */ 1578}; 1579 1580#define for_each_eth_queue(bp, var) \ 1581 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1582 1583#define for_each_nondefault_eth_queue(bp, var) \ 1584 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++) 1585 1586#define for_each_queue(bp, var) \ 1587 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1588 if (skip_queue(bp, var)) \ 1589 continue; \ 1590 else 1591 1592/* Skip forwarding FP */ 1593#define for_each_rx_queue(bp, var) \ 1594 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1595 if (skip_rx_queue(bp, var)) \ 1596 continue; \ 1597 else 1598 1599/* Skip OOO FP */ 1600#define for_each_tx_queue(bp, var) \ 1601 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1602 if (skip_tx_queue(bp, var)) \ 1603 continue; \ 1604 else 1605 1606#define for_each_nondefault_queue(bp, var) \ 1607 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \ 1608 if (skip_queue(bp, var)) \ 1609 continue; \ 1610 else 1611 1612#define for_each_cos_in_tx_queue(fp, var) \ 1613 for ((var) = 0; (var) < (fp)->max_cos; (var)++) 1614 1615/* skip rx queue 1616 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1617 */ 1618#define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1619 1620/* skip tx queue 1621 * if FCOE l2 support is disabled and this is the fcoe L2 queue 1622 */ 1623#define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1624 1625#define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx)) 1626 1627 1628 1629 1630/** 1631 * bnx2x_set_mac_one - configure a single MAC address 1632 * 1633 * @bp: driver handle 1634 * @mac: MAC to configure 1635 * @obj: MAC object handle 1636 * @set: if 'true' add a new MAC, otherwise - delete 1637 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list) 1638 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT) 1639 * 1640 * Configures one MAC according to provided parameters or continues the 1641 * execution of previously scheduled commands if RAMROD_CONT is set in 1642 * ramrod_flags. 1643 * 1644 * Returns zero if operation has successfully completed, a positive value if the 1645 * operation has been successfully scheduled and a negative - if a requested 1646 * operations has failed. 1647 */ 1648int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac, 1649 struct bnx2x_vlan_mac_obj *obj, bool set, 1650 int mac_type, unsigned long *ramrod_flags); 1651/** 1652 * Deletes all MACs configured for the specific MAC object. 1653 * 1654 * @param bp Function driver instance 1655 * @param mac_obj MAC object to cleanup 1656 * 1657 * @return zero if all MACs were cleaned 1658 */ 1659 1660/** 1661 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object 1662 * 1663 * @bp: driver handle 1664 * @mac_obj: MAC object handle 1665 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC) 1666 * @wait_for_comp: if 'true' block until completion 1667 * 1668 * Deletes all MACs of the specific type (e.g. ETH, UC list). 1669 * 1670 * Returns zero if operation has successfully completed, a positive value if the 1671 * operation has been successfully scheduled and a negative - if a requested 1672 * operations has failed. 1673 */ 1674int bnx2x_del_all_macs(struct bnx2x *bp, 1675 struct bnx2x_vlan_mac_obj *mac_obj, 1676 int mac_type, bool wait_for_comp); 1677 1678/* Init Function API */ 1679void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p); 1680int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port); 1681int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1682int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode); 1683int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port); 1684void bnx2x_read_mf_cfg(struct bnx2x *bp); 1685 1686 1687/* dmae */ 1688void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32); 1689void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr, 1690 u32 len32); 1691void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx); 1692u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type); 1693u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode); 1694u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type, 1695 bool with_comp, u8 comp_type); 1696 1697 1698void bnx2x_calc_fc_adv(struct bnx2x *bp); 1699int bnx2x_sp_post(struct bnx2x *bp, int command, int cid, 1700 u32 data_hi, u32 data_lo, int cmd_type); 1701void bnx2x_update_coalesce(struct bnx2x *bp); 1702int bnx2x_get_cur_phy_idx(struct bnx2x *bp); 1703 1704static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms, 1705 int wait) 1706{ 1707 u32 val; 1708 1709 do { 1710 val = REG_RD(bp, reg); 1711 if (val == expected) 1712 break; 1713 ms -= wait; 1714 msleep(wait); 1715 1716 } while (ms > 0); 1717 1718 return val; 1719} 1720 1721#define BNX2X_ILT_ZALLOC(x, y, size) \ 1722 do { \ 1723 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 1724 if (x) \ 1725 memset(x, 0, size); \ 1726 } while (0) 1727 1728#define BNX2X_ILT_FREE(x, y, size) \ 1729 do { \ 1730 if (x) { \ 1731 dma_free_coherent(&bp->pdev->dev, size, x, y); \ 1732 x = NULL; \ 1733 y = 0; \ 1734 } \ 1735 } while (0) 1736 1737#define ILOG2(x) (ilog2((x))) 1738 1739#define ILT_NUM_PAGE_ENTRIES (3072) 1740/* In 57710/11 we use whole table since we have 8 func 1741 * In 57712 we have only 4 func, but use same size per func, then only half of 1742 * the table in use 1743 */ 1744#define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8) 1745 1746#define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 1747/* 1748 * the phys address is shifted right 12 bits and has an added 1749 * 1=valid bit added to the 53rd bit 1750 * then since this is a wide register(TM) 1751 * we split it into two 32 bit writes 1752 */ 1753#define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF)) 1754#define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44))) 1755 1756/* load/unload mode */ 1757#define LOAD_NORMAL 0 1758#define LOAD_OPEN 1 1759#define LOAD_DIAG 2 1760#define UNLOAD_NORMAL 0 1761#define UNLOAD_CLOSE 1 1762#define UNLOAD_RECOVERY 2 1763 1764 1765/* DMAE command defines */ 1766#define DMAE_TIMEOUT -1 1767#define DMAE_PCI_ERROR -2 /* E2 and onward */ 1768#define DMAE_NOT_RDY -3 1769#define DMAE_PCI_ERR_FLAG 0x80000000 1770 1771#define DMAE_SRC_PCI 0 1772#define DMAE_SRC_GRC 1 1773 1774#define DMAE_DST_NONE 0 1775#define DMAE_DST_PCI 1 1776#define DMAE_DST_GRC 2 1777 1778#define DMAE_COMP_PCI 0 1779#define DMAE_COMP_GRC 1 1780 1781/* E2 and onward - PCI error handling in the completion */ 1782 1783#define DMAE_COMP_REGULAR 0 1784#define DMAE_COM_SET_ERR 1 1785 1786#define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \ 1787 DMAE_COMMAND_SRC_SHIFT) 1788#define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \ 1789 DMAE_COMMAND_SRC_SHIFT) 1790 1791#define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \ 1792 DMAE_COMMAND_DST_SHIFT) 1793#define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \ 1794 DMAE_COMMAND_DST_SHIFT) 1795 1796#define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \ 1797 DMAE_COMMAND_C_DST_SHIFT) 1798#define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \ 1799 DMAE_COMMAND_C_DST_SHIFT) 1800 1801#define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE 1802 1803#define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 1804#define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 1805#define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 1806#define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 1807 1808#define DMAE_CMD_PORT_0 0 1809#define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 1810 1811#define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET 1812#define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET 1813#define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT 1814 1815#define DMAE_SRC_PF 0 1816#define DMAE_SRC_VF 1 1817 1818#define DMAE_DST_PF 0 1819#define DMAE_DST_VF 1 1820 1821#define DMAE_C_SRC 0 1822#define DMAE_C_DST 1 1823 1824#define DMAE_LEN32_RD_MAX 0x80 1825#define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000) 1826 1827#define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit 1828 indicates eror */ 1829 1830#define MAX_DMAE_C_PER_PORT 8 1831#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1832 BP_VN(bp)) 1833#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1834 E1HVN_MAX) 1835 1836/* PCIE link and speed */ 1837#define PCICFG_LINK_WIDTH 0x1f00000 1838#define PCICFG_LINK_WIDTH_SHIFT 20 1839#define PCICFG_LINK_SPEED 0xf0000 1840#define PCICFG_LINK_SPEED_SHIFT 16 1841 1842 1843#define BNX2X_NUM_TESTS 7 1844 1845#define BNX2X_PHY_LOOPBACK 0 1846#define BNX2X_MAC_LOOPBACK 1 1847#define BNX2X_PHY_LOOPBACK_FAILED 1 1848#define BNX2X_MAC_LOOPBACK_FAILED 2 1849#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \ 1850 BNX2X_PHY_LOOPBACK_FAILED) 1851 1852 1853#define STROM_ASSERT_ARRAY_SIZE 50 1854 1855 1856/* must be used on a CID before placing it on a HW ring */ 1857#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 1858 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \ 1859 (x)) 1860 1861#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1862#define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1863 1864 1865#define BNX2X_BTR 4 1866#define MAX_SPQ_PENDING 8 1867 1868/* CMNG constants, as derived from system spec calculations */ 1869/* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 1870#define DEF_MIN_RATE 100 1871/* resolution of the rate shaping timer - 400 usec */ 1872#define RS_PERIODIC_TIMEOUT_USEC 400 1873/* number of bytes in single QM arbitration cycle - 1874 * coefficient for calculating the fairness timer */ 1875#define QM_ARB_BYTES 160000 1876/* resolution of Min algorithm 1:100 */ 1877#define MIN_RES 100 1878/* how many bytes above threshold for the minimal credit of Min algorithm*/ 1879#define MIN_ABOVE_THRESH 32768 1880/* Fairness algorithm integration time coefficient - 1881 * for calculating the actual Tfair */ 1882#define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 1883/* Memory of fairness algorithm . 2 cycles */ 1884#define FAIR_MEM 2 1885 1886 1887#define ATTN_NIG_FOR_FUNC (1L << 8) 1888#define ATTN_SW_TIMER_4_FUNC (1L << 9) 1889#define GPIO_2_FUNC (1L << 10) 1890#define GPIO_3_FUNC (1L << 11) 1891#define GPIO_4_FUNC (1L << 12) 1892#define ATTN_GENERAL_ATTN_1 (1L << 13) 1893#define ATTN_GENERAL_ATTN_2 (1L << 14) 1894#define ATTN_GENERAL_ATTN_3 (1L << 15) 1895#define ATTN_GENERAL_ATTN_4 (1L << 13) 1896#define ATTN_GENERAL_ATTN_5 (1L << 14) 1897#define ATTN_GENERAL_ATTN_6 (1L << 15) 1898 1899#define ATTN_HARD_WIRED_MASK 0xff00 1900#define ATTENTION_ID 4 1901 1902 1903/* stuff added to make the code fit 80Col */ 1904 1905#define BNX2X_PMF_LINK_ASSERT \ 1906 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp)) 1907 1908#define BNX2X_MC_ASSERT_BITS \ 1909 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1910 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1911 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 1912 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 1913 1914#define BNX2X_MCP_ASSERT \ 1915 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 1916 1917#define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 1918#define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 1919 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 1920 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 1921 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 1922 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 1923 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 1924 1925#define HW_INTERRUT_ASSERT_SET_0 \ 1926 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \ 1927 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \ 1928 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \ 1929 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT) 1930#define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \ 1931 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \ 1932 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \ 1933 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\ 1934 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\ 1935 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\ 1936 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR) 1937#define HW_INTERRUT_ASSERT_SET_1 \ 1938 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \ 1939 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \ 1940 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \ 1941 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \ 1942 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \ 1943 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \ 1944 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \ 1945 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \ 1946 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \ 1947 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \ 1948 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT) 1949#define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\ 1950 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \ 1951 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\ 1952 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \ 1953 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\ 1954 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \ 1955 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\ 1956 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\ 1957 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\ 1958 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \ 1959 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \ 1960 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\ 1961 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \ 1962 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \ 1963 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\ 1964 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR) 1965#define HW_INTERRUT_ASSERT_SET_2 \ 1966 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \ 1967 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \ 1968 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \ 1969 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\ 1970 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT) 1971#define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \ 1972 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \ 1973 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\ 1974 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \ 1975 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \ 1976 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\ 1977 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \ 1978 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR) 1979 1980#define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 1981 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 1982 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \ 1983 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 1984 1985#define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \ 1986 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR) 1987 1988#define RSS_FLAGS(bp) \ 1989 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \ 1990 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \ 1991 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \ 1992 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \ 1993 (bp->multi_mode << \ 1994 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT)) 1995#define MULTI_MASK 0x7f 1996 1997 1998#define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func) 1999#define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func) 2000#define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func) 2001#define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func) 2002 2003#define DEF_USB_IGU_INDEX_OFF \ 2004 offsetof(struct cstorm_def_status_block_u, igu_index) 2005#define DEF_CSB_IGU_INDEX_OFF \ 2006 offsetof(struct cstorm_def_status_block_c, igu_index) 2007#define DEF_XSB_IGU_INDEX_OFF \ 2008 offsetof(struct xstorm_def_status_block, igu_index) 2009#define DEF_TSB_IGU_INDEX_OFF \ 2010 offsetof(struct tstorm_def_status_block, igu_index) 2011 2012#define DEF_USB_SEGMENT_OFF \ 2013 offsetof(struct cstorm_def_status_block_u, segment) 2014#define DEF_CSB_SEGMENT_OFF \ 2015 offsetof(struct cstorm_def_status_block_c, segment) 2016#define DEF_XSB_SEGMENT_OFF \ 2017 offsetof(struct xstorm_def_status_block, segment) 2018#define DEF_TSB_SEGMENT_OFF \ 2019 offsetof(struct tstorm_def_status_block, segment) 2020 2021#define BNX2X_SP_DSB_INDEX \ 2022 (&bp->def_status_blk->sp_sb.\ 2023 index_values[HC_SP_INDEX_ETH_DEF_CONS]) 2024 2025#define SET_FLAG(value, mask, flag) \ 2026 do {\ 2027 (value) &= ~(mask);\ 2028 (value) |= ((flag) << (mask##_SHIFT));\ 2029 } while (0) 2030 2031#define GET_FLAG(value, mask) \ 2032 (((value) & (mask)) >> (mask##_SHIFT)) 2033 2034#define GET_FIELD(value, fname) \ 2035 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 2036 2037#define CAM_IS_INVALID(x) \ 2038 (GET_FLAG(x.flags, \ 2039 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \ 2040 (T_ETH_MAC_COMMAND_INVALIDATE)) 2041 2042/* Number of u32 elements in MC hash array */ 2043#define MC_HASH_SIZE 8 2044#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \ 2045 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4) 2046 2047 2048#ifndef PXP2_REG_PXP2_INT_STS 2049#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0 2050#endif 2051 2052#ifndef ETH_MAX_RX_CLIENTS_E2 2053#define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H 2054#endif 2055 2056#define BNX2X_VPD_LEN 128 2057#define VENDOR_ID_LEN 4 2058 2059/* Congestion management fairness mode */ 2060#define CMNG_FNS_NONE 0 2061#define CMNG_FNS_MINMAX 1 2062 2063#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/ 2064#define HC_SEG_ACCESS_ATTN 4 2065#define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/ 2066 2067static const u32 dmae_reg_go_c[] = { 2068 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2069 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2070 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2071 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2072}; 2073 2074void bnx2x_set_ethtool_ops(struct net_device *netdev); 2075void bnx2x_notify_link_changed(struct bnx2x *bp); 2076#endif /* bnx2x.h */ 2077