bnx2x_cmn.h revision 1ab4434c64f8d4786e4a26299e0ebb138a0a6415
1/* bnx2x_cmn.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17#ifndef BNX2X_CMN_H 18#define BNX2X_CMN_H 19 20#include <linux/types.h> 21#include <linux/pci.h> 22#include <linux/netdevice.h> 23#include <linux/etherdevice.h> 24 25 26#include "bnx2x.h" 27 28/* This is used as a replacement for an MCP if it's not present */ 29extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ 30 31extern int num_queues; 32extern int int_mode; 33 34/************************ Macros ********************************/ 35#define BNX2X_PCI_FREE(x, y, size) \ 36 do { \ 37 if (x) { \ 38 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ 39 x = NULL; \ 40 y = 0; \ 41 } \ 42 } while (0) 43 44#define BNX2X_FREE(x) \ 45 do { \ 46 if (x) { \ 47 kfree((void *)x); \ 48 x = NULL; \ 49 } \ 50 } while (0) 51 52#define BNX2X_PCI_ALLOC(x, y, size) \ 53 do { \ 54 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 55 if (x == NULL) \ 56 goto alloc_mem_err; \ 57 memset((void *)x, 0, size); \ 58 } while (0) 59 60#define BNX2X_ALLOC(x, size) \ 61 do { \ 62 x = kzalloc(size, GFP_KERNEL); \ 63 if (x == NULL) \ 64 goto alloc_mem_err; \ 65 } while (0) 66 67/*********************** Interfaces **************************** 68 * Functions that need to be implemented by each driver version 69 */ 70/* Init */ 71 72/** 73 * bnx2x_send_unload_req - request unload mode from the MCP. 74 * 75 * @bp: driver handle 76 * @unload_mode: requested function's unload mode 77 * 78 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 79 */ 80u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); 81 82/** 83 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 84 * 85 * @bp: driver handle 86 * @keep_link: true iff link should be kept up 87 */ 88void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link); 89 90/** 91 * bnx2x_config_rss_pf - configure RSS parameters in a PF. 92 * 93 * @bp: driver handle 94 * @rss_obj: RSS object to use 95 * @ind_table: indirection table to configure 96 * @config_hash: re-configure RSS hash keys configuration 97 */ 98int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, 99 bool config_hash); 100 101/** 102 * bnx2x__init_func_obj - init function object 103 * 104 * @bp: driver handle 105 * 106 * Initializes the Function Object with the appropriate 107 * parameters which include a function slow path driver 108 * interface. 109 */ 110void bnx2x__init_func_obj(struct bnx2x *bp); 111 112/** 113 * bnx2x_setup_queue - setup eth queue. 114 * 115 * @bp: driver handle 116 * @fp: pointer to the fastpath structure 117 * @leading: boolean 118 * 119 */ 120int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 121 bool leading); 122 123/** 124 * bnx2x_setup_leading - bring up a leading eth queue. 125 * 126 * @bp: driver handle 127 */ 128int bnx2x_setup_leading(struct bnx2x *bp); 129 130/** 131 * bnx2x_fw_command - send the MCP a request 132 * 133 * @bp: driver handle 134 * @command: request 135 * @param: request's parameter 136 * 137 * block until there is a reply 138 */ 139u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); 140 141/** 142 * bnx2x_initial_phy_init - initialize link parameters structure variables. 143 * 144 * @bp: driver handle 145 * @load_mode: current mode 146 */ 147int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); 148 149/** 150 * bnx2x_link_set - configure hw according to link parameters structure. 151 * 152 * @bp: driver handle 153 */ 154void bnx2x_link_set(struct bnx2x *bp); 155 156/** 157 * bnx2x_force_link_reset - Forces link reset, and put the PHY 158 * in reset as well. 159 * 160 * @bp: driver handle 161 */ 162void bnx2x_force_link_reset(struct bnx2x *bp); 163 164/** 165 * bnx2x_link_test - query link status. 166 * 167 * @bp: driver handle 168 * @is_serdes: bool 169 * 170 * Returns 0 if link is UP. 171 */ 172u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); 173 174/** 175 * bnx2x_drv_pulse - write driver pulse to shmem 176 * 177 * @bp: driver handle 178 * 179 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox 180 * in the shmem. 181 */ 182void bnx2x_drv_pulse(struct bnx2x *bp); 183 184/** 185 * bnx2x_igu_ack_sb - update IGU with current SB value 186 * 187 * @bp: driver handle 188 * @igu_sb_id: SB id 189 * @segment: SB segment 190 * @index: SB index 191 * @op: SB operation 192 * @update: is HW update required 193 */ 194void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 195 u16 index, u8 op, u8 update); 196 197/* Disable transactions from chip to host */ 198void bnx2x_pf_disable(struct bnx2x *bp); 199 200/** 201 * bnx2x__link_status_update - handles link status change. 202 * 203 * @bp: driver handle 204 */ 205void bnx2x__link_status_update(struct bnx2x *bp); 206 207/** 208 * bnx2x_link_report - report link status to upper layer. 209 * 210 * @bp: driver handle 211 */ 212void bnx2x_link_report(struct bnx2x *bp); 213 214/* None-atomic version of bnx2x_link_report() */ 215void __bnx2x_link_report(struct bnx2x *bp); 216 217/** 218 * bnx2x_get_mf_speed - calculate MF speed. 219 * 220 * @bp: driver handle 221 * 222 * Takes into account current linespeed and MF configuration. 223 */ 224u16 bnx2x_get_mf_speed(struct bnx2x *bp); 225 226/** 227 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler 228 * 229 * @irq: irq number 230 * @dev_instance: private instance 231 */ 232irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); 233 234/** 235 * bnx2x_interrupt - non MSI-X interrupt handler 236 * 237 * @irq: irq number 238 * @dev_instance: private instance 239 */ 240irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); 241 242/** 243 * bnx2x_cnic_notify - send command to cnic driver 244 * 245 * @bp: driver handle 246 * @cmd: command 247 */ 248int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); 249 250/** 251 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information 252 * 253 * @bp: driver handle 254 */ 255void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); 256 257/** 258 * bnx2x_setup_cnic_info - provides cnic with updated info 259 * 260 * @bp: driver handle 261 */ 262void bnx2x_setup_cnic_info(struct bnx2x *bp); 263 264/** 265 * bnx2x_int_enable - enable HW interrupts. 266 * 267 * @bp: driver handle 268 */ 269void bnx2x_int_enable(struct bnx2x *bp); 270 271/** 272 * bnx2x_int_disable_sync - disable interrupts. 273 * 274 * @bp: driver handle 275 * @disable_hw: true, disable HW interrupts. 276 * 277 * This function ensures that there are no 278 * ISRs or SP DPCs (sp_task) are running after it returns. 279 */ 280void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); 281 282/** 283 * bnx2x_nic_init_cnic - init driver internals for cnic. 284 * 285 * @bp: driver handle 286 * @load_code: COMMON, PORT or FUNCTION 287 * 288 * Initializes: 289 * - rings 290 * - status blocks 291 * - etc. 292 */ 293void bnx2x_nic_init_cnic(struct bnx2x *bp); 294 295/** 296 * bnx2x_nic_init - init driver internals. 297 * 298 * @bp: driver handle 299 * 300 * Initializes: 301 * - rings 302 * - status blocks 303 * - etc. 304 */ 305void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); 306/** 307 * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic. 308 * 309 * @bp: driver handle 310 */ 311int bnx2x_alloc_mem_cnic(struct bnx2x *bp); 312/** 313 * bnx2x_alloc_mem - allocate driver's memory. 314 * 315 * @bp: driver handle 316 */ 317int bnx2x_alloc_mem(struct bnx2x *bp); 318 319/** 320 * bnx2x_free_mem_cnic - release driver's memory for cnic. 321 * 322 * @bp: driver handle 323 */ 324void bnx2x_free_mem_cnic(struct bnx2x *bp); 325/** 326 * bnx2x_free_mem - release driver's memory. 327 * 328 * @bp: driver handle 329 */ 330void bnx2x_free_mem(struct bnx2x *bp); 331 332/** 333 * bnx2x_set_num_queues - set number of queues according to mode. 334 * 335 * @bp: driver handle 336 */ 337void bnx2x_set_num_queues(struct bnx2x *bp); 338 339/** 340 * bnx2x_chip_cleanup - cleanup chip internals. 341 * 342 * @bp: driver handle 343 * @unload_mode: COMMON, PORT, FUNCTION 344 * @keep_link: true iff link should be kept up. 345 * 346 * - Cleanup MAC configuration. 347 * - Closes clients. 348 * - etc. 349 */ 350void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link); 351 352/** 353 * bnx2x_acquire_hw_lock - acquire HW lock. 354 * 355 * @bp: driver handle 356 * @resource: resource bit which was locked 357 */ 358int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); 359 360/** 361 * bnx2x_release_hw_lock - release HW lock. 362 * 363 * @bp: driver handle 364 * @resource: resource bit which was locked 365 */ 366int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); 367 368/** 369 * bnx2x_release_leader_lock - release recovery leader lock 370 * 371 * @bp: driver handle 372 */ 373int bnx2x_release_leader_lock(struct bnx2x *bp); 374 375/** 376 * bnx2x_set_eth_mac - configure eth MAC address in the HW 377 * 378 * @bp: driver handle 379 * @set: set or clear 380 * 381 * Configures according to the value in netdev->dev_addr. 382 */ 383int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); 384 385/** 386 * bnx2x_set_rx_mode - set MAC filtering configurations. 387 * 388 * @dev: netdevice 389 * 390 * called with netif_tx_lock from dev_mcast.c 391 * If bp->state is OPEN, should be called with 392 * netif_addr_lock_bh() 393 */ 394void bnx2x_set_rx_mode(struct net_device *dev); 395 396/** 397 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. 398 * 399 * @bp: driver handle 400 * 401 * If bp->state is OPEN, should be called with 402 * netif_addr_lock_bh(). 403 */ 404void bnx2x_set_storm_rx_mode(struct bnx2x *bp); 405 406/** 407 * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. 408 * 409 * @bp: driver handle 410 * @cl_id: client id 411 * @rx_mode_flags: rx mode configuration 412 * @rx_accept_flags: rx accept configuration 413 * @tx_accept_flags: tx accept configuration (tx switch) 414 * @ramrod_flags: ramrod configuration 415 */ 416void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 417 unsigned long rx_mode_flags, 418 unsigned long rx_accept_flags, 419 unsigned long tx_accept_flags, 420 unsigned long ramrod_flags); 421 422/* Parity errors related */ 423void bnx2x_set_pf_load(struct bnx2x *bp); 424bool bnx2x_clear_pf_load(struct bnx2x *bp); 425bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); 426bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); 427void bnx2x_set_reset_in_progress(struct bnx2x *bp); 428void bnx2x_set_reset_global(struct bnx2x *bp); 429void bnx2x_disable_close_the_gate(struct bnx2x *bp); 430int bnx2x_init_hw_func_cnic(struct bnx2x *bp); 431 432/** 433 * bnx2x_sp_event - handle ramrods completion. 434 * 435 * @fp: fastpath handle for the event 436 * @rr_cqe: eth_rx_cqe 437 */ 438void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); 439 440/** 441 * bnx2x_ilt_set_info - prepare ILT configurations. 442 * 443 * @bp: driver handle 444 */ 445void bnx2x_ilt_set_info(struct bnx2x *bp); 446 447/** 448 * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC 449 * and TM. 450 * 451 * @bp: driver handle 452 */ 453void bnx2x_ilt_set_info_cnic(struct bnx2x *bp); 454 455/** 456 * bnx2x_dcbx_init - initialize dcbx protocol. 457 * 458 * @bp: driver handle 459 */ 460void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); 461 462/** 463 * bnx2x_set_power_state - set power state to the requested value. 464 * 465 * @bp: driver handle 466 * @state: required state D0 or D3hot 467 * 468 * Currently only D0 and D3hot are supported. 469 */ 470int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); 471 472/** 473 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. 474 * 475 * @bp: driver handle 476 * @value: new value 477 */ 478void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); 479/* Error handling */ 480void bnx2x_panic_dump(struct bnx2x *bp); 481 482void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); 483 484/* validate currect fw is loaded */ 485bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err); 486 487/* dev_close main block */ 488int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link); 489 490/* dev_open main block */ 491int bnx2x_nic_load(struct bnx2x *bp, int load_mode); 492 493/* hard_xmit callback */ 494netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); 495 496/* setup_tc callback */ 497int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); 498 499/* select_queue callback */ 500u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); 501 502/* reload helper */ 503int bnx2x_reload_if_running(struct net_device *dev); 504 505int bnx2x_change_mac_addr(struct net_device *dev, void *p); 506 507/* NAPI poll Rx part */ 508int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); 509 510void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 511 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod); 512 513/* NAPI poll Tx part */ 514int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); 515 516/* suspend/resume callbacks */ 517int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); 518int bnx2x_resume(struct pci_dev *pdev); 519 520/* Release IRQ vectors */ 521void bnx2x_free_irq(struct bnx2x *bp); 522 523void bnx2x_free_fp_mem_cnic(struct bnx2x *bp); 524void bnx2x_free_fp_mem(struct bnx2x *bp); 525int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp); 526int bnx2x_alloc_fp_mem(struct bnx2x *bp); 527void bnx2x_init_rx_rings(struct bnx2x *bp); 528void bnx2x_init_rx_rings_cnic(struct bnx2x *bp); 529void bnx2x_free_skbs_cnic(struct bnx2x *bp); 530void bnx2x_free_skbs(struct bnx2x *bp); 531void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); 532void bnx2x_netif_start(struct bnx2x *bp); 533int bnx2x_load_cnic(struct bnx2x *bp); 534 535/** 536 * bnx2x_enable_msix - set msix configuration. 537 * 538 * @bp: driver handle 539 * 540 * fills msix_table, requests vectors, updates num_queues 541 * according to number of available vectors. 542 */ 543int bnx2x_enable_msix(struct bnx2x *bp); 544 545/** 546 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly 547 * 548 * @bp: driver handle 549 */ 550int bnx2x_enable_msi(struct bnx2x *bp); 551 552/** 553 * bnx2x_poll - NAPI callback 554 * 555 * @napi: napi structure 556 * @budget: 557 * 558 */ 559int bnx2x_poll(struct napi_struct *napi, int budget); 560 561/** 562 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure 563 * 564 * @bp: driver handle 565 */ 566int bnx2x_alloc_mem_bp(struct bnx2x *bp); 567 568/** 569 * bnx2x_free_mem_bp - release memories outsize main driver structure 570 * 571 * @bp: driver handle 572 */ 573void bnx2x_free_mem_bp(struct bnx2x *bp); 574 575/** 576 * bnx2x_change_mtu - change mtu netdev callback 577 * 578 * @dev: net device 579 * @new_mtu: requested mtu 580 * 581 */ 582int bnx2x_change_mtu(struct net_device *dev, int new_mtu); 583 584#ifdef NETDEV_FCOE_WWNN 585/** 586 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port 587 * 588 * @dev: net_device 589 * @wwn: output buffer 590 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) 591 * 592 */ 593int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); 594#endif 595 596netdev_features_t bnx2x_fix_features(struct net_device *dev, 597 netdev_features_t features); 598int bnx2x_set_features(struct net_device *dev, netdev_features_t features); 599 600/** 601 * bnx2x_tx_timeout - tx timeout netdev callback 602 * 603 * @dev: net device 604 */ 605void bnx2x_tx_timeout(struct net_device *dev); 606 607/*********************** Inlines **********************************/ 608/*********************** Fast path ********************************/ 609static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 610{ 611 barrier(); /* status block is written to by the chip */ 612 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 613} 614 615static inline void bnx2x_update_rx_prod_gen(struct bnx2x *bp, 616 struct bnx2x_fastpath *fp, u16 bd_prod, 617 u16 rx_comp_prod, u16 rx_sge_prod, u32 start) 618{ 619 struct ustorm_eth_rx_producers rx_prods = {0}; 620 u32 i; 621 622 /* Update producers */ 623 rx_prods.bd_prod = bd_prod; 624 rx_prods.cqe_prod = rx_comp_prod; 625 rx_prods.sge_prod = rx_sge_prod; 626 627 /* 628 * Make sure that the BD and SGE data is updated before updating the 629 * producers since FW might read the BD/SGE right after the producer 630 * is updated. 631 * This is only applicable for weak-ordered memory model archs such 632 * as IA-64. The following barrier is also mandatory since FW will 633 * assumes BDs must have buffers. 634 */ 635 wmb(); 636 637 for (i = 0; i < sizeof(rx_prods)/4; i++) 638 REG_WR(bp, start + i*4, ((u32 *)&rx_prods)[i]); 639 640 mmiowb(); /* keep prod updates ordered */ 641 642 DP(NETIF_MSG_RX_STATUS, 643 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", 644 fp->index, bd_prod, rx_comp_prod, rx_sge_prod); 645} 646 647static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, 648 u8 segment, u16 index, u8 op, 649 u8 update, u32 igu_addr) 650{ 651 struct igu_regular cmd_data = {0}; 652 653 cmd_data.sb_id_and_flags = 654 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 655 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 656 (update << IGU_REGULAR_BUPDATE_SHIFT) | 657 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 658 659 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", 660 cmd_data.sb_id_and_flags, igu_addr); 661 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); 662 663 /* Make sure that ACK is written */ 664 mmiowb(); 665 barrier(); 666} 667 668static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, 669 u8 storm, u16 index, u8 op, u8 update) 670{ 671 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 672 COMMAND_REG_INT_ACK); 673 struct igu_ack_register igu_ack; 674 675 igu_ack.status_block_index = index; 676 igu_ack.sb_id_and_flags = 677 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 678 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 679 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 680 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 681 682 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); 683 684 /* Make sure that ACK is written */ 685 mmiowb(); 686 barrier(); 687} 688 689static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, 690 u16 index, u8 op, u8 update) 691{ 692 if (bp->common.int_block == INT_BLOCK_HC) 693 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); 694 else { 695 u8 segment; 696 697 if (CHIP_INT_MODE_IS_BC(bp)) 698 segment = storm; 699 else if (igu_sb_id != bp->igu_dsb_id) 700 segment = IGU_SEG_ACCESS_DEF; 701 else if (storm == ATTENTION_ID) 702 segment = IGU_SEG_ACCESS_ATTN; 703 else 704 segment = IGU_SEG_ACCESS_DEF; 705 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); 706 } 707} 708 709static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) 710{ 711 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 712 COMMAND_REG_SIMD_MASK); 713 u32 result = REG_RD(bp, hc_addr); 714 715 barrier(); 716 return result; 717} 718 719static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) 720{ 721 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 722 u32 result = REG_RD(bp, igu_addr); 723 724 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", 725 result, igu_addr); 726 727 barrier(); 728 return result; 729} 730 731static inline u16 bnx2x_ack_int(struct bnx2x *bp) 732{ 733 barrier(); 734 if (bp->common.int_block == INT_BLOCK_HC) 735 return bnx2x_hc_ack_int(bp); 736 else 737 return bnx2x_igu_ack_int(bp); 738} 739 740static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) 741{ 742 /* Tell compiler that consumer and producer can change */ 743 barrier(); 744 return txdata->tx_pkt_prod != txdata->tx_pkt_cons; 745} 746 747static inline u16 bnx2x_tx_avail(struct bnx2x *bp, 748 struct bnx2x_fp_txdata *txdata) 749{ 750 s16 used; 751 u16 prod; 752 u16 cons; 753 754 prod = txdata->tx_bd_prod; 755 cons = txdata->tx_bd_cons; 756 757 used = SUB_S16(prod, cons); 758 759#ifdef BNX2X_STOP_ON_ERROR 760 WARN_ON(used < 0); 761 WARN_ON(used > txdata->tx_ring_size); 762 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL); 763#endif 764 765 return (s16)(txdata->tx_ring_size) - used; 766} 767 768static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) 769{ 770 u16 hw_cons; 771 772 /* Tell compiler that status block fields can change */ 773 barrier(); 774 hw_cons = le16_to_cpu(*txdata->tx_cons_sb); 775 return hw_cons != txdata->tx_pkt_cons; 776} 777 778static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) 779{ 780 u8 cos; 781 for_each_cos_in_tx_queue(fp, cos) 782 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) 783 return true; 784 return false; 785} 786 787static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) 788{ 789 u16 rx_cons_sb; 790 791 /* Tell compiler that status block fields can change */ 792 barrier(); 793 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); 794 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) 795 rx_cons_sb++; 796 return (fp->rx_comp_cons != rx_cons_sb); 797} 798 799/** 800 * bnx2x_tx_disable - disables tx from stack point of view 801 * 802 * @bp: driver handle 803 */ 804static inline void bnx2x_tx_disable(struct bnx2x *bp) 805{ 806 netif_tx_disable(bp->dev); 807 netif_carrier_off(bp->dev); 808} 809 810static inline void bnx2x_free_rx_sge(struct bnx2x *bp, 811 struct bnx2x_fastpath *fp, u16 index) 812{ 813 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; 814 struct page *page = sw_buf->page; 815 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; 816 817 /* Skip "next page" elements */ 818 if (!page) 819 return; 820 821 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), 822 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); 823 __free_pages(page, PAGES_PER_SGE_SHIFT); 824 825 sw_buf->page = NULL; 826 sge->addr_hi = 0; 827 sge->addr_lo = 0; 828} 829 830static inline void bnx2x_add_all_napi_cnic(struct bnx2x *bp) 831{ 832 int i; 833 834 /* Add NAPI objects */ 835 for_each_rx_queue_cnic(bp, i) 836 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 837 bnx2x_poll, BNX2X_NAPI_WEIGHT); 838} 839 840static inline void bnx2x_add_all_napi(struct bnx2x *bp) 841{ 842 int i; 843 844 /* Add NAPI objects */ 845 for_each_eth_queue(bp, i) 846 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 847 bnx2x_poll, BNX2X_NAPI_WEIGHT); 848} 849 850static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp) 851{ 852 int i; 853 854 for_each_rx_queue_cnic(bp, i) 855 netif_napi_del(&bnx2x_fp(bp, i, napi)); 856} 857 858static inline void bnx2x_del_all_napi(struct bnx2x *bp) 859{ 860 int i; 861 862 for_each_eth_queue(bp, i) 863 netif_napi_del(&bnx2x_fp(bp, i, napi)); 864} 865 866int bnx2x_set_int_mode(struct bnx2x *bp); 867 868static inline void bnx2x_disable_msi(struct bnx2x *bp) 869{ 870 if (bp->flags & USING_MSIX_FLAG) { 871 pci_disable_msix(bp->pdev); 872 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); 873 } else if (bp->flags & USING_MSI_FLAG) { 874 pci_disable_msi(bp->pdev); 875 bp->flags &= ~USING_MSI_FLAG; 876 } 877} 878 879static inline int bnx2x_calc_num_queues(struct bnx2x *bp) 880{ 881 return num_queues ? 882 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : 883 min_t(int, netif_get_num_default_rss_queues(), 884 BNX2X_MAX_QUEUES(bp)); 885} 886 887static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) 888{ 889 int i, j; 890 891 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { 892 int idx = RX_SGE_CNT * i - 1; 893 894 for (j = 0; j < 2; j++) { 895 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); 896 idx--; 897 } 898 } 899} 900 901static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) 902{ 903 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ 904 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); 905 906 /* Clear the two last indices in the page to 1: 907 these are the indices that correspond to the "next" element, 908 hence will never be indicated and should be removed from 909 the calculations. */ 910 bnx2x_clear_sge_mask_next_elems(fp); 911} 912 913/* note that we are not allocating a new buffer, 914 * we are just moving one from cons to prod 915 * we are not creating a new mapping, 916 * so there is no need to check for dma_mapping_error(). 917 */ 918static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, 919 u16 cons, u16 prod) 920{ 921 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; 922 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; 923 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; 924 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; 925 926 dma_unmap_addr_set(prod_rx_buf, mapping, 927 dma_unmap_addr(cons_rx_buf, mapping)); 928 prod_rx_buf->data = cons_rx_buf->data; 929 *prod_bd = *cons_bd; 930} 931 932/************************* Init ******************************************/ 933 934/* returns func by VN for current port */ 935static inline int func_by_vn(struct bnx2x *bp, int vn) 936{ 937 return 2 * vn + BP_PORT(bp); 938} 939 940static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) 941{ 942 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash); 943} 944 945/** 946 * bnx2x_func_start - init function 947 * 948 * @bp: driver handle 949 * 950 * Must be called before sending CLIENT_SETUP for the first client. 951 */ 952static inline int bnx2x_func_start(struct bnx2x *bp) 953{ 954 struct bnx2x_func_state_params func_params = {NULL}; 955 struct bnx2x_func_start_params *start_params = 956 &func_params.params.start; 957 958 /* Prepare parameters for function state transitions */ 959 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 960 961 func_params.f_obj = &bp->func_obj; 962 func_params.cmd = BNX2X_F_CMD_START; 963 964 /* Function parameters */ 965 start_params->mf_mode = bp->mf_mode; 966 start_params->sd_vlan_tag = bp->mf_ov; 967 968 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) 969 start_params->network_cos_mode = STATIC_COS; 970 else /* CHIP_IS_E1X */ 971 start_params->network_cos_mode = FW_WRR; 972 973 return bnx2x_func_state_change(bp, &func_params); 974} 975 976 977/** 978 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format 979 * 980 * @fw_hi: pointer to upper part 981 * @fw_mid: pointer to middle part 982 * @fw_lo: pointer to lower part 983 * @mac: pointer to MAC address 984 */ 985static inline void bnx2x_set_fw_mac_addr(u16 *fw_hi, u16 *fw_mid, u16 *fw_lo, 986 u8 *mac) 987{ 988 ((u8 *)fw_hi)[0] = mac[1]; 989 ((u8 *)fw_hi)[1] = mac[0]; 990 ((u8 *)fw_mid)[0] = mac[3]; 991 ((u8 *)fw_mid)[1] = mac[2]; 992 ((u8 *)fw_lo)[0] = mac[5]; 993 ((u8 *)fw_lo)[1] = mac[4]; 994} 995 996static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, 997 struct bnx2x_fastpath *fp, int last) 998{ 999 int i; 1000 1001 if (fp->disable_tpa) 1002 return; 1003 1004 for (i = 0; i < last; i++) 1005 bnx2x_free_rx_sge(bp, fp, i); 1006} 1007 1008static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) 1009{ 1010 int i; 1011 1012 for (i = 1; i <= NUM_RX_RINGS; i++) { 1013 struct eth_rx_bd *rx_bd; 1014 1015 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; 1016 rx_bd->addr_hi = 1017 cpu_to_le32(U64_HI(fp->rx_desc_mapping + 1018 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 1019 rx_bd->addr_lo = 1020 cpu_to_le32(U64_LO(fp->rx_desc_mapping + 1021 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 1022 } 1023} 1024 1025/* Statistics ID are global per chip/path, while Client IDs for E1x are per 1026 * port. 1027 */ 1028static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) 1029{ 1030 struct bnx2x *bp = fp->bp; 1031 if (!CHIP_IS_E1x(bp)) { 1032 /* there are special statistics counters for FCoE 136..140 */ 1033 if (IS_FCOE_FP(fp)) 1034 return bp->cnic_base_cl_id + (bp->pf_num >> 1); 1035 return fp->cl_id; 1036 } 1037 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; 1038} 1039 1040static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, 1041 bnx2x_obj_type obj_type) 1042{ 1043 struct bnx2x *bp = fp->bp; 1044 1045 /* Configure classification DBs */ 1046 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, 1047 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), 1048 bnx2x_sp_mapping(bp, mac_rdata), 1049 BNX2X_FILTER_MAC_PENDING, 1050 &bp->sp_state, obj_type, 1051 &bp->macs_pool); 1052} 1053 1054/** 1055 * bnx2x_get_path_func_num - get number of active functions 1056 * 1057 * @bp: driver handle 1058 * 1059 * Calculates the number of active (not hidden) functions on the 1060 * current path. 1061 */ 1062static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) 1063{ 1064 u8 func_num = 0, i; 1065 1066 /* 57710 has only one function per-port */ 1067 if (CHIP_IS_E1(bp)) 1068 return 1; 1069 1070 /* Calculate a number of functions enabled on the current 1071 * PATH/PORT. 1072 */ 1073 if (CHIP_REV_IS_SLOW(bp)) { 1074 if (IS_MF(bp)) 1075 func_num = 4; 1076 else 1077 func_num = 2; 1078 } else { 1079 for (i = 0; i < E1H_FUNC_MAX / 2; i++) { 1080 u32 func_config = 1081 MF_CFG_RD(bp, 1082 func_mf_config[BP_PORT(bp) + 2 * i]. 1083 config); 1084 func_num += 1085 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); 1086 } 1087 } 1088 1089 WARN_ON(!func_num); 1090 1091 return func_num; 1092} 1093 1094static inline void bnx2x_init_bp_objs(struct bnx2x *bp) 1095{ 1096 /* RX_MODE controlling object */ 1097 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); 1098 1099 /* multicast configuration controlling object */ 1100 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, 1101 BP_FUNC(bp), BP_FUNC(bp), 1102 bnx2x_sp(bp, mcast_rdata), 1103 bnx2x_sp_mapping(bp, mcast_rdata), 1104 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, 1105 BNX2X_OBJ_TYPE_RX); 1106 1107 /* Setup CAM credit pools */ 1108 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), 1109 bnx2x_get_path_func_num(bp)); 1110 1111 /* RSS configuration object */ 1112 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, 1113 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), 1114 bnx2x_sp(bp, rss_rdata), 1115 bnx2x_sp_mapping(bp, rss_rdata), 1116 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, 1117 BNX2X_OBJ_TYPE_RX); 1118} 1119 1120static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) 1121{ 1122 if (CHIP_IS_E1x(fp->bp)) 1123 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; 1124 else 1125 return fp->cl_id; 1126} 1127 1128static inline u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) 1129{ 1130 struct bnx2x *bp = fp->bp; 1131 1132 if (!CHIP_IS_E1x(bp)) 1133 return USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); 1134 else 1135 return USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); 1136} 1137 1138static inline void bnx2x_init_txdata(struct bnx2x *bp, 1139 struct bnx2x_fp_txdata *txdata, u32 cid, 1140 int txq_index, __le16 *tx_cons_sb, 1141 struct bnx2x_fastpath *fp) 1142{ 1143 txdata->cid = cid; 1144 txdata->txq_index = txq_index; 1145 txdata->tx_cons_sb = tx_cons_sb; 1146 txdata->parent_fp = fp; 1147 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size; 1148 1149 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", 1150 txdata->cid, txdata->txq_index); 1151} 1152 1153static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) 1154{ 1155 return bp->cnic_base_cl_id + cl_idx + 1156 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; 1157} 1158 1159static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) 1160{ 1161 1162 /* the 'first' id is allocated for the cnic */ 1163 return bp->base_fw_ndsb; 1164} 1165 1166static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) 1167{ 1168 return bp->igu_base_sb; 1169} 1170 1171 1172static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) 1173{ 1174 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 1175 unsigned long q_type = 0; 1176 1177 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); 1178 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, 1179 BNX2X_FCOE_ETH_CL_ID_IDX); 1180 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); 1181 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; 1182 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; 1183 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; 1184 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), 1185 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, 1186 fp); 1187 1188 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); 1189 1190 /* qZone id equals to FW (per path) client id */ 1191 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); 1192 /* init shortcut */ 1193 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = 1194 bnx2x_rx_ustorm_prods_offset(fp); 1195 1196 /* Configure Queue State object */ 1197 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1198 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1199 1200 /* No multi-CoS for FCoE L2 client */ 1201 BUG_ON(fp->max_cos != 1); 1202 1203 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, 1204 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 1205 bnx2x_sp_mapping(bp, q_rdata), q_type); 1206 1207 DP(NETIF_MSG_IFUP, 1208 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 1209 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 1210 fp->igu_sb_id); 1211} 1212 1213static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, 1214 struct bnx2x_fp_txdata *txdata) 1215{ 1216 int cnt = 1000; 1217 1218 while (bnx2x_has_tx_work_unload(txdata)) { 1219 if (!cnt) { 1220 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", 1221 txdata->txq_index, txdata->tx_pkt_prod, 1222 txdata->tx_pkt_cons); 1223#ifdef BNX2X_STOP_ON_ERROR 1224 bnx2x_panic(); 1225 return -EBUSY; 1226#else 1227 break; 1228#endif 1229 } 1230 cnt--; 1231 usleep_range(1000, 1000); 1232 } 1233 1234 return 0; 1235} 1236 1237int bnx2x_get_link_cfg_idx(struct bnx2x *bp); 1238 1239static inline void __storm_memset_struct(struct bnx2x *bp, 1240 u32 addr, size_t size, u32 *data) 1241{ 1242 int i; 1243 for (i = 0; i < size/4; i++) 1244 REG_WR(bp, addr + (i * 4), data[i]); 1245} 1246 1247/** 1248 * bnx2x_wait_sp_comp - wait for the outstanding SP commands. 1249 * 1250 * @bp: driver handle 1251 * @mask: bits that need to be cleared 1252 */ 1253static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) 1254{ 1255 int tout = 5000; /* Wait for 5 secs tops */ 1256 1257 while (tout--) { 1258 smp_mb(); 1259 netif_addr_lock_bh(bp->dev); 1260 if (!(bp->sp_state & mask)) { 1261 netif_addr_unlock_bh(bp->dev); 1262 return true; 1263 } 1264 netif_addr_unlock_bh(bp->dev); 1265 1266 usleep_range(1000, 1000); 1267 } 1268 1269 smp_mb(); 1270 1271 netif_addr_lock_bh(bp->dev); 1272 if (bp->sp_state & mask) { 1273 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", 1274 bp->sp_state, mask); 1275 netif_addr_unlock_bh(bp->dev); 1276 return false; 1277 } 1278 netif_addr_unlock_bh(bp->dev); 1279 1280 return true; 1281} 1282 1283/** 1284 * bnx2x_set_ctx_validation - set CDU context validation values 1285 * 1286 * @bp: driver handle 1287 * @cxt: context of the connection on the host memory 1288 * @cid: SW CID of the connection to be configured 1289 */ 1290void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, 1291 u32 cid); 1292 1293void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, 1294 u8 sb_index, u8 disable, u16 usec); 1295void bnx2x_acquire_phy_lock(struct bnx2x *bp); 1296void bnx2x_release_phy_lock(struct bnx2x *bp); 1297 1298/** 1299 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. 1300 * 1301 * @bp: driver handle 1302 * @mf_cfg: MF configuration 1303 * 1304 */ 1305static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) 1306{ 1307 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 1308 FUNC_MF_CFG_MAX_BW_SHIFT; 1309 if (!max_cfg) { 1310 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, 1311 "Max BW configured to 0 - using 100 instead\n"); 1312 max_cfg = 100; 1313 } 1314 return max_cfg; 1315} 1316 1317/* checks if HW supports GRO for given MTU */ 1318static inline bool bnx2x_mtu_allows_gro(int mtu) 1319{ 1320 /* gro frags per page */ 1321 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); 1322 1323 /* 1324 * 1. number of frags should not grow above MAX_SKB_FRAGS 1325 * 2. frag must fit the page 1326 */ 1327 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; 1328} 1329 1330/** 1331 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. 1332 * 1333 * @bp: driver handle 1334 * 1335 */ 1336void bnx2x_get_iscsi_info(struct bnx2x *bp); 1337 1338/** 1339 * bnx2x_link_sync_notify - send notification to other functions. 1340 * 1341 * @bp: driver handle 1342 * 1343 */ 1344static inline void bnx2x_link_sync_notify(struct bnx2x *bp) 1345{ 1346 int func; 1347 int vn; 1348 1349 /* Set the attention towards other drivers on the same port */ 1350 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 1351 if (vn == BP_VN(bp)) 1352 continue; 1353 1354 func = func_by_vn(bp, vn); 1355 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + 1356 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); 1357 } 1358} 1359 1360/** 1361 * bnx2x_update_drv_flags - update flags in shmem 1362 * 1363 * @bp: driver handle 1364 * @flags: flags to update 1365 * @set: set or clear 1366 * 1367 */ 1368static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) 1369{ 1370 if (SHMEM2_HAS(bp, drv_flags)) { 1371 u32 drv_flags; 1372 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1373 drv_flags = SHMEM2_RD(bp, drv_flags); 1374 1375 if (set) 1376 SET_FLAGS(drv_flags, flags); 1377 else 1378 RESET_FLAGS(drv_flags, flags); 1379 1380 SHMEM2_WR(bp, drv_flags, drv_flags); 1381 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); 1382 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1383 } 1384} 1385 1386static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) 1387{ 1388 if (is_valid_ether_addr(addr) || 1389 (is_zero_ether_addr(addr) && 1390 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)))) 1391 return true; 1392 1393 return false; 1394} 1395 1396#endif /* BNX2X_CMN_H */ 1397