bnx2x_cmn.h revision 230bb0f33672b5fad1c485ca82789f427fc1b253
1/* bnx2x_cmn.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2013 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17#ifndef BNX2X_CMN_H 18#define BNX2X_CMN_H 19 20#include <linux/types.h> 21#include <linux/pci.h> 22#include <linux/netdevice.h> 23#include <linux/etherdevice.h> 24 25#include "bnx2x.h" 26#include "bnx2x_sriov.h" 27 28/* This is used as a replacement for an MCP if it's not present */ 29extern int bnx2x_load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ 30extern int bnx2x_num_queues; 31 32/************************ Macros ********************************/ 33#define BNX2X_PCI_FREE(x, y, size) \ 34 do { \ 35 if (x) { \ 36 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ 37 x = NULL; \ 38 y = 0; \ 39 } \ 40 } while (0) 41 42#define BNX2X_FREE(x) \ 43 do { \ 44 if (x) { \ 45 kfree((void *)x); \ 46 x = NULL; \ 47 } \ 48 } while (0) 49 50#define BNX2X_PCI_ALLOC(x, y, size) \ 51 do { \ 52 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 53 if (x == NULL) \ 54 goto alloc_mem_err; \ 55 DP(NETIF_MSG_HW, "BNX2X_PCI_ALLOC: Physical %Lx Virtual %p\n", \ 56 (unsigned long long)(*y), x); \ 57 } while (0) 58 59#define BNX2X_PCI_FALLOC(x, y, size) \ 60 do { \ 61 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 62 if (x == NULL) \ 63 goto alloc_mem_err; \ 64 memset((void *)x, 0xFFFFFFFF, size); \ 65 DP(NETIF_MSG_HW, "BNX2X_PCI_FALLOC: Physical %Lx Virtual %p\n",\ 66 (unsigned long long)(*y), x); \ 67 } while (0) 68 69#define BNX2X_ALLOC(x, size) \ 70 do { \ 71 x = kzalloc(size, GFP_KERNEL); \ 72 if (x == NULL) \ 73 goto alloc_mem_err; \ 74 } while (0) 75 76/*********************** Interfaces **************************** 77 * Functions that need to be implemented by each driver version 78 */ 79/* Init */ 80 81/** 82 * bnx2x_send_unload_req - request unload mode from the MCP. 83 * 84 * @bp: driver handle 85 * @unload_mode: requested function's unload mode 86 * 87 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 88 */ 89u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); 90 91/** 92 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 93 * 94 * @bp: driver handle 95 * @keep_link: true iff link should be kept up 96 */ 97void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link); 98 99/** 100 * bnx2x_config_rss_pf - configure RSS parameters in a PF. 101 * 102 * @bp: driver handle 103 * @rss_obj: RSS object to use 104 * @ind_table: indirection table to configure 105 * @config_hash: re-configure RSS hash keys configuration 106 * @enable: enabled or disabled configuration 107 */ 108int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, 109 bool config_hash, bool enable); 110 111/** 112 * bnx2x__init_func_obj - init function object 113 * 114 * @bp: driver handle 115 * 116 * Initializes the Function Object with the appropriate 117 * parameters which include a function slow path driver 118 * interface. 119 */ 120void bnx2x__init_func_obj(struct bnx2x *bp); 121 122/** 123 * bnx2x_setup_queue - setup eth queue. 124 * 125 * @bp: driver handle 126 * @fp: pointer to the fastpath structure 127 * @leading: boolean 128 * 129 */ 130int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 131 bool leading); 132 133/** 134 * bnx2x_setup_leading - bring up a leading eth queue. 135 * 136 * @bp: driver handle 137 */ 138int bnx2x_setup_leading(struct bnx2x *bp); 139 140/** 141 * bnx2x_fw_command - send the MCP a request 142 * 143 * @bp: driver handle 144 * @command: request 145 * @param: request's parameter 146 * 147 * block until there is a reply 148 */ 149u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); 150 151/** 152 * bnx2x_initial_phy_init - initialize link parameters structure variables. 153 * 154 * @bp: driver handle 155 * @load_mode: current mode 156 */ 157int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); 158 159/** 160 * bnx2x_link_set - configure hw according to link parameters structure. 161 * 162 * @bp: driver handle 163 */ 164void bnx2x_link_set(struct bnx2x *bp); 165 166/** 167 * bnx2x_force_link_reset - Forces link reset, and put the PHY 168 * in reset as well. 169 * 170 * @bp: driver handle 171 */ 172void bnx2x_force_link_reset(struct bnx2x *bp); 173 174/** 175 * bnx2x_link_test - query link status. 176 * 177 * @bp: driver handle 178 * @is_serdes: bool 179 * 180 * Returns 0 if link is UP. 181 */ 182u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); 183 184/** 185 * bnx2x_drv_pulse - write driver pulse to shmem 186 * 187 * @bp: driver handle 188 * 189 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox 190 * in the shmem. 191 */ 192void bnx2x_drv_pulse(struct bnx2x *bp); 193 194/** 195 * bnx2x_igu_ack_sb - update IGU with current SB value 196 * 197 * @bp: driver handle 198 * @igu_sb_id: SB id 199 * @segment: SB segment 200 * @index: SB index 201 * @op: SB operation 202 * @update: is HW update required 203 */ 204void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 205 u16 index, u8 op, u8 update); 206 207/* Disable transactions from chip to host */ 208void bnx2x_pf_disable(struct bnx2x *bp); 209int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val); 210 211/** 212 * bnx2x__link_status_update - handles link status change. 213 * 214 * @bp: driver handle 215 */ 216void bnx2x__link_status_update(struct bnx2x *bp); 217 218/** 219 * bnx2x_link_report - report link status to upper layer. 220 * 221 * @bp: driver handle 222 */ 223void bnx2x_link_report(struct bnx2x *bp); 224 225/* None-atomic version of bnx2x_link_report() */ 226void __bnx2x_link_report(struct bnx2x *bp); 227 228/** 229 * bnx2x_get_mf_speed - calculate MF speed. 230 * 231 * @bp: driver handle 232 * 233 * Takes into account current linespeed and MF configuration. 234 */ 235u16 bnx2x_get_mf_speed(struct bnx2x *bp); 236 237/** 238 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler 239 * 240 * @irq: irq number 241 * @dev_instance: private instance 242 */ 243irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); 244 245/** 246 * bnx2x_interrupt - non MSI-X interrupt handler 247 * 248 * @irq: irq number 249 * @dev_instance: private instance 250 */ 251irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); 252 253/** 254 * bnx2x_cnic_notify - send command to cnic driver 255 * 256 * @bp: driver handle 257 * @cmd: command 258 */ 259int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); 260 261/** 262 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information 263 * 264 * @bp: driver handle 265 */ 266void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); 267 268/** 269 * bnx2x_setup_cnic_info - provides cnic with updated info 270 * 271 * @bp: driver handle 272 */ 273void bnx2x_setup_cnic_info(struct bnx2x *bp); 274 275/** 276 * bnx2x_int_enable - enable HW interrupts. 277 * 278 * @bp: driver handle 279 */ 280void bnx2x_int_enable(struct bnx2x *bp); 281 282/** 283 * bnx2x_int_disable_sync - disable interrupts. 284 * 285 * @bp: driver handle 286 * @disable_hw: true, disable HW interrupts. 287 * 288 * This function ensures that there are no 289 * ISRs or SP DPCs (sp_task) are running after it returns. 290 */ 291void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); 292 293/** 294 * bnx2x_nic_init_cnic - init driver internals for cnic. 295 * 296 * @bp: driver handle 297 * @load_code: COMMON, PORT or FUNCTION 298 * 299 * Initializes: 300 * - rings 301 * - status blocks 302 * - etc. 303 */ 304void bnx2x_nic_init_cnic(struct bnx2x *bp); 305 306/** 307 * bnx2x_preirq_nic_init - init driver internals. 308 * 309 * @bp: driver handle 310 * 311 * Initializes: 312 * - fastpath object 313 * - fastpath rings 314 * etc. 315 */ 316void bnx2x_pre_irq_nic_init(struct bnx2x *bp); 317 318/** 319 * bnx2x_postirq_nic_init - init driver internals. 320 * 321 * @bp: driver handle 322 * @load_code: COMMON, PORT or FUNCTION 323 * 324 * Initializes: 325 * - status blocks 326 * - slowpath rings 327 * - etc. 328 */ 329void bnx2x_post_irq_nic_init(struct bnx2x *bp, u32 load_code); 330/** 331 * bnx2x_alloc_mem_cnic - allocate driver's memory for cnic. 332 * 333 * @bp: driver handle 334 */ 335int bnx2x_alloc_mem_cnic(struct bnx2x *bp); 336/** 337 * bnx2x_alloc_mem - allocate driver's memory. 338 * 339 * @bp: driver handle 340 */ 341int bnx2x_alloc_mem(struct bnx2x *bp); 342 343/** 344 * bnx2x_free_mem_cnic - release driver's memory for cnic. 345 * 346 * @bp: driver handle 347 */ 348void bnx2x_free_mem_cnic(struct bnx2x *bp); 349/** 350 * bnx2x_free_mem - release driver's memory. 351 * 352 * @bp: driver handle 353 */ 354void bnx2x_free_mem(struct bnx2x *bp); 355 356/** 357 * bnx2x_set_num_queues - set number of queues according to mode. 358 * 359 * @bp: driver handle 360 */ 361void bnx2x_set_num_queues(struct bnx2x *bp); 362 363/** 364 * bnx2x_chip_cleanup - cleanup chip internals. 365 * 366 * @bp: driver handle 367 * @unload_mode: COMMON, PORT, FUNCTION 368 * @keep_link: true iff link should be kept up. 369 * 370 * - Cleanup MAC configuration. 371 * - Closes clients. 372 * - etc. 373 */ 374void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link); 375 376/** 377 * bnx2x_acquire_hw_lock - acquire HW lock. 378 * 379 * @bp: driver handle 380 * @resource: resource bit which was locked 381 */ 382int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); 383 384/** 385 * bnx2x_release_hw_lock - release HW lock. 386 * 387 * @bp: driver handle 388 * @resource: resource bit which was locked 389 */ 390int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); 391 392/** 393 * bnx2x_release_leader_lock - release recovery leader lock 394 * 395 * @bp: driver handle 396 */ 397int bnx2x_release_leader_lock(struct bnx2x *bp); 398 399/** 400 * bnx2x_set_eth_mac - configure eth MAC address in the HW 401 * 402 * @bp: driver handle 403 * @set: set or clear 404 * 405 * Configures according to the value in netdev->dev_addr. 406 */ 407int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); 408 409/** 410 * bnx2x_set_rx_mode - set MAC filtering configurations. 411 * 412 * @dev: netdevice 413 * 414 * called with netif_tx_lock from dev_mcast.c 415 * If bp->state is OPEN, should be called with 416 * netif_addr_lock_bh() 417 */ 418void bnx2x_set_rx_mode_inner(struct bnx2x *bp); 419 420/* Parity errors related */ 421void bnx2x_set_pf_load(struct bnx2x *bp); 422bool bnx2x_clear_pf_load(struct bnx2x *bp); 423bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); 424bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); 425void bnx2x_set_reset_in_progress(struct bnx2x *bp); 426void bnx2x_set_reset_global(struct bnx2x *bp); 427void bnx2x_disable_close_the_gate(struct bnx2x *bp); 428int bnx2x_init_hw_func_cnic(struct bnx2x *bp); 429 430/** 431 * bnx2x_sp_event - handle ramrods completion. 432 * 433 * @fp: fastpath handle for the event 434 * @rr_cqe: eth_rx_cqe 435 */ 436void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); 437 438/** 439 * bnx2x_ilt_set_info - prepare ILT configurations. 440 * 441 * @bp: driver handle 442 */ 443void bnx2x_ilt_set_info(struct bnx2x *bp); 444 445/** 446 * bnx2x_ilt_set_cnic_info - prepare ILT configurations for SRC 447 * and TM. 448 * 449 * @bp: driver handle 450 */ 451void bnx2x_ilt_set_info_cnic(struct bnx2x *bp); 452 453/** 454 * bnx2x_dcbx_init - initialize dcbx protocol. 455 * 456 * @bp: driver handle 457 */ 458void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); 459 460/** 461 * bnx2x_set_power_state - set power state to the requested value. 462 * 463 * @bp: driver handle 464 * @state: required state D0 or D3hot 465 * 466 * Currently only D0 and D3hot are supported. 467 */ 468int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); 469 470/** 471 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. 472 * 473 * @bp: driver handle 474 * @value: new value 475 */ 476void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); 477/* Error handling */ 478void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); 479 480/* dev_close main block */ 481int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link); 482 483/* dev_open main block */ 484int bnx2x_nic_load(struct bnx2x *bp, int load_mode); 485 486/* hard_xmit callback */ 487netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); 488 489/* setup_tc callback */ 490int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); 491 492int bnx2x_get_vf_config(struct net_device *dev, int vf, 493 struct ifla_vf_info *ivi); 494int bnx2x_set_vf_mac(struct net_device *dev, int queue, u8 *mac); 495int bnx2x_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos); 496 497/* select_queue callback */ 498u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb, 499 void *accel_priv); 500 501static inline void bnx2x_update_rx_prod(struct bnx2x *bp, 502 struct bnx2x_fastpath *fp, 503 u16 bd_prod, u16 rx_comp_prod, 504 u16 rx_sge_prod) 505{ 506 struct ustorm_eth_rx_producers rx_prods = {0}; 507 u32 i; 508 509 /* Update producers */ 510 rx_prods.bd_prod = bd_prod; 511 rx_prods.cqe_prod = rx_comp_prod; 512 rx_prods.sge_prod = rx_sge_prod; 513 514 /* Make sure that the BD and SGE data is updated before updating the 515 * producers since FW might read the BD/SGE right after the producer 516 * is updated. 517 * This is only applicable for weak-ordered memory model archs such 518 * as IA-64. The following barrier is also mandatory since FW will 519 * assumes BDs must have buffers. 520 */ 521 wmb(); 522 523 for (i = 0; i < sizeof(rx_prods)/4; i++) 524 REG_WR(bp, fp->ustorm_rx_prods_offset + i*4, 525 ((u32 *)&rx_prods)[i]); 526 527 mmiowb(); /* keep prod updates ordered */ 528 529 DP(NETIF_MSG_RX_STATUS, 530 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", 531 fp->index, bd_prod, rx_comp_prod, rx_sge_prod); 532} 533 534/* reload helper */ 535int bnx2x_reload_if_running(struct net_device *dev); 536 537int bnx2x_change_mac_addr(struct net_device *dev, void *p); 538 539/* NAPI poll Tx part */ 540int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); 541 542/* suspend/resume callbacks */ 543int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); 544int bnx2x_resume(struct pci_dev *pdev); 545 546/* Release IRQ vectors */ 547void bnx2x_free_irq(struct bnx2x *bp); 548 549void bnx2x_free_fp_mem(struct bnx2x *bp); 550void bnx2x_init_rx_rings(struct bnx2x *bp); 551void bnx2x_init_rx_rings_cnic(struct bnx2x *bp); 552void bnx2x_free_skbs(struct bnx2x *bp); 553void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); 554void bnx2x_netif_start(struct bnx2x *bp); 555int bnx2x_load_cnic(struct bnx2x *bp); 556 557/** 558 * bnx2x_enable_msix - set msix configuration. 559 * 560 * @bp: driver handle 561 * 562 * fills msix_table, requests vectors, updates num_queues 563 * according to number of available vectors. 564 */ 565int bnx2x_enable_msix(struct bnx2x *bp); 566 567/** 568 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly 569 * 570 * @bp: driver handle 571 */ 572int bnx2x_enable_msi(struct bnx2x *bp); 573 574/** 575 * bnx2x_low_latency_recv - LL callback 576 * 577 * @napi: napi structure 578 */ 579int bnx2x_low_latency_recv(struct napi_struct *napi); 580 581/** 582 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure 583 * 584 * @bp: driver handle 585 */ 586int bnx2x_alloc_mem_bp(struct bnx2x *bp); 587 588/** 589 * bnx2x_free_mem_bp - release memories outsize main driver structure 590 * 591 * @bp: driver handle 592 */ 593void bnx2x_free_mem_bp(struct bnx2x *bp); 594 595/** 596 * bnx2x_change_mtu - change mtu netdev callback 597 * 598 * @dev: net device 599 * @new_mtu: requested mtu 600 * 601 */ 602int bnx2x_change_mtu(struct net_device *dev, int new_mtu); 603 604#ifdef NETDEV_FCOE_WWNN 605/** 606 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port 607 * 608 * @dev: net_device 609 * @wwn: output buffer 610 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) 611 * 612 */ 613int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); 614#endif 615 616netdev_features_t bnx2x_fix_features(struct net_device *dev, 617 netdev_features_t features); 618int bnx2x_set_features(struct net_device *dev, netdev_features_t features); 619 620/** 621 * bnx2x_tx_timeout - tx timeout netdev callback 622 * 623 * @dev: net device 624 */ 625void bnx2x_tx_timeout(struct net_device *dev); 626 627/*********************** Inlines **********************************/ 628/*********************** Fast path ********************************/ 629static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 630{ 631 barrier(); /* status block is written to by the chip */ 632 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 633} 634 635static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, 636 u8 segment, u16 index, u8 op, 637 u8 update, u32 igu_addr) 638{ 639 struct igu_regular cmd_data = {0}; 640 641 cmd_data.sb_id_and_flags = 642 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 643 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 644 (update << IGU_REGULAR_BUPDATE_SHIFT) | 645 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 646 647 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", 648 cmd_data.sb_id_and_flags, igu_addr); 649 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); 650 651 /* Make sure that ACK is written */ 652 mmiowb(); 653 barrier(); 654} 655 656static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, 657 u8 storm, u16 index, u8 op, u8 update) 658{ 659 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 660 COMMAND_REG_INT_ACK); 661 struct igu_ack_register igu_ack; 662 663 igu_ack.status_block_index = index; 664 igu_ack.sb_id_and_flags = 665 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 666 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 667 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 668 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 669 670 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); 671 672 /* Make sure that ACK is written */ 673 mmiowb(); 674 barrier(); 675} 676 677static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, 678 u16 index, u8 op, u8 update) 679{ 680 if (bp->common.int_block == INT_BLOCK_HC) 681 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); 682 else { 683 u8 segment; 684 685 if (CHIP_INT_MODE_IS_BC(bp)) 686 segment = storm; 687 else if (igu_sb_id != bp->igu_dsb_id) 688 segment = IGU_SEG_ACCESS_DEF; 689 else if (storm == ATTENTION_ID) 690 segment = IGU_SEG_ACCESS_ATTN; 691 else 692 segment = IGU_SEG_ACCESS_DEF; 693 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); 694 } 695} 696 697static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) 698{ 699 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 700 COMMAND_REG_SIMD_MASK); 701 u32 result = REG_RD(bp, hc_addr); 702 703 barrier(); 704 return result; 705} 706 707static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) 708{ 709 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 710 u32 result = REG_RD(bp, igu_addr); 711 712 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", 713 result, igu_addr); 714 715 barrier(); 716 return result; 717} 718 719static inline u16 bnx2x_ack_int(struct bnx2x *bp) 720{ 721 barrier(); 722 if (bp->common.int_block == INT_BLOCK_HC) 723 return bnx2x_hc_ack_int(bp); 724 else 725 return bnx2x_igu_ack_int(bp); 726} 727 728static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) 729{ 730 /* Tell compiler that consumer and producer can change */ 731 barrier(); 732 return txdata->tx_pkt_prod != txdata->tx_pkt_cons; 733} 734 735static inline u16 bnx2x_tx_avail(struct bnx2x *bp, 736 struct bnx2x_fp_txdata *txdata) 737{ 738 s16 used; 739 u16 prod; 740 u16 cons; 741 742 prod = txdata->tx_bd_prod; 743 cons = txdata->tx_bd_cons; 744 745 used = SUB_S16(prod, cons); 746 747#ifdef BNX2X_STOP_ON_ERROR 748 WARN_ON(used < 0); 749 WARN_ON(used > txdata->tx_ring_size); 750 WARN_ON((txdata->tx_ring_size - used) > MAX_TX_AVAIL); 751#endif 752 753 return (s16)(txdata->tx_ring_size) - used; 754} 755 756static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) 757{ 758 u16 hw_cons; 759 760 /* Tell compiler that status block fields can change */ 761 barrier(); 762 hw_cons = le16_to_cpu(*txdata->tx_cons_sb); 763 return hw_cons != txdata->tx_pkt_cons; 764} 765 766static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) 767{ 768 u8 cos; 769 for_each_cos_in_tx_queue(fp, cos) 770 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) 771 return true; 772 return false; 773} 774 775#define BNX2X_IS_CQE_COMPLETED(cqe_fp) (cqe_fp->marker == 0x0) 776#define BNX2X_SEED_CQE(cqe_fp) (cqe_fp->marker = 0xFFFFFFFF) 777static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) 778{ 779 u16 cons; 780 union eth_rx_cqe *cqe; 781 struct eth_fast_path_rx_cqe *cqe_fp; 782 783 cons = RCQ_BD(fp->rx_comp_cons); 784 cqe = &fp->rx_comp_ring[cons]; 785 cqe_fp = &cqe->fast_path_cqe; 786 return BNX2X_IS_CQE_COMPLETED(cqe_fp); 787} 788 789/** 790 * bnx2x_tx_disable - disables tx from stack point of view 791 * 792 * @bp: driver handle 793 */ 794static inline void bnx2x_tx_disable(struct bnx2x *bp) 795{ 796 netif_tx_disable(bp->dev); 797 netif_carrier_off(bp->dev); 798} 799 800static inline void bnx2x_free_rx_sge(struct bnx2x *bp, 801 struct bnx2x_fastpath *fp, u16 index) 802{ 803 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; 804 struct page *page = sw_buf->page; 805 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; 806 807 /* Skip "next page" elements */ 808 if (!page) 809 return; 810 811 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), 812 SGE_PAGES, DMA_FROM_DEVICE); 813 __free_pages(page, PAGES_PER_SGE_SHIFT); 814 815 sw_buf->page = NULL; 816 sge->addr_hi = 0; 817 sge->addr_lo = 0; 818} 819 820static inline void bnx2x_del_all_napi_cnic(struct bnx2x *bp) 821{ 822 int i; 823 824 for_each_rx_queue_cnic(bp, i) { 825 napi_hash_del(&bnx2x_fp(bp, i, napi)); 826 netif_napi_del(&bnx2x_fp(bp, i, napi)); 827 } 828} 829 830static inline void bnx2x_del_all_napi(struct bnx2x *bp) 831{ 832 int i; 833 834 for_each_eth_queue(bp, i) { 835 napi_hash_del(&bnx2x_fp(bp, i, napi)); 836 netif_napi_del(&bnx2x_fp(bp, i, napi)); 837 } 838} 839 840int bnx2x_set_int_mode(struct bnx2x *bp); 841 842static inline void bnx2x_disable_msi(struct bnx2x *bp) 843{ 844 if (bp->flags & USING_MSIX_FLAG) { 845 pci_disable_msix(bp->pdev); 846 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); 847 } else if (bp->flags & USING_MSI_FLAG) { 848 pci_disable_msi(bp->pdev); 849 bp->flags &= ~USING_MSI_FLAG; 850 } 851} 852 853static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) 854{ 855 int i, j; 856 857 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { 858 int idx = RX_SGE_CNT * i - 1; 859 860 for (j = 0; j < 2; j++) { 861 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); 862 idx--; 863 } 864 } 865} 866 867static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) 868{ 869 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ 870 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); 871 872 /* Clear the two last indices in the page to 1: 873 these are the indices that correspond to the "next" element, 874 hence will never be indicated and should be removed from 875 the calculations. */ 876 bnx2x_clear_sge_mask_next_elems(fp); 877} 878 879/* note that we are not allocating a new buffer, 880 * we are just moving one from cons to prod 881 * we are not creating a new mapping, 882 * so there is no need to check for dma_mapping_error(). 883 */ 884static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, 885 u16 cons, u16 prod) 886{ 887 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; 888 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; 889 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; 890 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; 891 892 dma_unmap_addr_set(prod_rx_buf, mapping, 893 dma_unmap_addr(cons_rx_buf, mapping)); 894 prod_rx_buf->data = cons_rx_buf->data; 895 *prod_bd = *cons_bd; 896} 897 898/************************* Init ******************************************/ 899 900/* returns func by VN for current port */ 901static inline int func_by_vn(struct bnx2x *bp, int vn) 902{ 903 return 2 * vn + BP_PORT(bp); 904} 905 906static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) 907{ 908 return bnx2x_rss(bp, &bp->rss_conf_obj, config_hash, true); 909} 910 911/** 912 * bnx2x_func_start - init function 913 * 914 * @bp: driver handle 915 * 916 * Must be called before sending CLIENT_SETUP for the first client. 917 */ 918static inline int bnx2x_func_start(struct bnx2x *bp) 919{ 920 struct bnx2x_func_state_params func_params = {NULL}; 921 struct bnx2x_func_start_params *start_params = 922 &func_params.params.start; 923 924 /* Prepare parameters for function state transitions */ 925 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 926 927 func_params.f_obj = &bp->func_obj; 928 func_params.cmd = BNX2X_F_CMD_START; 929 930 /* Function parameters */ 931 start_params->mf_mode = bp->mf_mode; 932 start_params->sd_vlan_tag = bp->mf_ov; 933 934 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) 935 start_params->network_cos_mode = STATIC_COS; 936 else /* CHIP_IS_E1X */ 937 start_params->network_cos_mode = FW_WRR; 938 939 start_params->gre_tunnel_mode = L2GRE_TUNNEL; 940 start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS; 941 942 return bnx2x_func_state_change(bp, &func_params); 943} 944 945/** 946 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format 947 * 948 * @fw_hi: pointer to upper part 949 * @fw_mid: pointer to middle part 950 * @fw_lo: pointer to lower part 951 * @mac: pointer to MAC address 952 */ 953static inline void bnx2x_set_fw_mac_addr(__le16 *fw_hi, __le16 *fw_mid, 954 __le16 *fw_lo, u8 *mac) 955{ 956 ((u8 *)fw_hi)[0] = mac[1]; 957 ((u8 *)fw_hi)[1] = mac[0]; 958 ((u8 *)fw_mid)[0] = mac[3]; 959 ((u8 *)fw_mid)[1] = mac[2]; 960 ((u8 *)fw_lo)[0] = mac[5]; 961 ((u8 *)fw_lo)[1] = mac[4]; 962} 963 964static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, 965 struct bnx2x_fastpath *fp, int last) 966{ 967 int i; 968 969 if (fp->disable_tpa) 970 return; 971 972 for (i = 0; i < last; i++) 973 bnx2x_free_rx_sge(bp, fp, i); 974} 975 976static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) 977{ 978 int i; 979 980 for (i = 1; i <= NUM_RX_RINGS; i++) { 981 struct eth_rx_bd *rx_bd; 982 983 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; 984 rx_bd->addr_hi = 985 cpu_to_le32(U64_HI(fp->rx_desc_mapping + 986 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 987 rx_bd->addr_lo = 988 cpu_to_le32(U64_LO(fp->rx_desc_mapping + 989 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 990 } 991} 992 993/* Statistics ID are global per chip/path, while Client IDs for E1x are per 994 * port. 995 */ 996static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) 997{ 998 struct bnx2x *bp = fp->bp; 999 if (!CHIP_IS_E1x(bp)) { 1000 /* there are special statistics counters for FCoE 136..140 */ 1001 if (IS_FCOE_FP(fp)) 1002 return bp->cnic_base_cl_id + (bp->pf_num >> 1); 1003 return fp->cl_id; 1004 } 1005 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; 1006} 1007 1008static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, 1009 bnx2x_obj_type obj_type) 1010{ 1011 struct bnx2x *bp = fp->bp; 1012 1013 /* Configure classification DBs */ 1014 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, 1015 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), 1016 bnx2x_sp_mapping(bp, mac_rdata), 1017 BNX2X_FILTER_MAC_PENDING, 1018 &bp->sp_state, obj_type, 1019 &bp->macs_pool); 1020} 1021 1022/** 1023 * bnx2x_get_path_func_num - get number of active functions 1024 * 1025 * @bp: driver handle 1026 * 1027 * Calculates the number of active (not hidden) functions on the 1028 * current path. 1029 */ 1030static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) 1031{ 1032 u8 func_num = 0, i; 1033 1034 /* 57710 has only one function per-port */ 1035 if (CHIP_IS_E1(bp)) 1036 return 1; 1037 1038 /* Calculate a number of functions enabled on the current 1039 * PATH/PORT. 1040 */ 1041 if (CHIP_REV_IS_SLOW(bp)) { 1042 if (IS_MF(bp)) 1043 func_num = 4; 1044 else 1045 func_num = 2; 1046 } else { 1047 for (i = 0; i < E1H_FUNC_MAX / 2; i++) { 1048 u32 func_config = 1049 MF_CFG_RD(bp, 1050 func_mf_config[BP_PORT(bp) + 2 * i]. 1051 config); 1052 func_num += 1053 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); 1054 } 1055 } 1056 1057 WARN_ON(!func_num); 1058 1059 return func_num; 1060} 1061 1062static inline void bnx2x_init_bp_objs(struct bnx2x *bp) 1063{ 1064 /* RX_MODE controlling object */ 1065 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); 1066 1067 /* multicast configuration controlling object */ 1068 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, 1069 BP_FUNC(bp), BP_FUNC(bp), 1070 bnx2x_sp(bp, mcast_rdata), 1071 bnx2x_sp_mapping(bp, mcast_rdata), 1072 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, 1073 BNX2X_OBJ_TYPE_RX); 1074 1075 /* Setup CAM credit pools */ 1076 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), 1077 bnx2x_get_path_func_num(bp)); 1078 1079 bnx2x_init_vlan_credit_pool(bp, &bp->vlans_pool, BP_ABS_FUNC(bp)>>1, 1080 bnx2x_get_path_func_num(bp)); 1081 1082 /* RSS configuration object */ 1083 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, 1084 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), 1085 bnx2x_sp(bp, rss_rdata), 1086 bnx2x_sp_mapping(bp, rss_rdata), 1087 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, 1088 BNX2X_OBJ_TYPE_RX); 1089} 1090 1091static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) 1092{ 1093 if (CHIP_IS_E1x(fp->bp)) 1094 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; 1095 else 1096 return fp->cl_id; 1097} 1098 1099static inline void bnx2x_init_txdata(struct bnx2x *bp, 1100 struct bnx2x_fp_txdata *txdata, u32 cid, 1101 int txq_index, __le16 *tx_cons_sb, 1102 struct bnx2x_fastpath *fp) 1103{ 1104 txdata->cid = cid; 1105 txdata->txq_index = txq_index; 1106 txdata->tx_cons_sb = tx_cons_sb; 1107 txdata->parent_fp = fp; 1108 txdata->tx_ring_size = IS_FCOE_FP(fp) ? MAX_TX_AVAIL : bp->tx_ring_size; 1109 1110 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", 1111 txdata->cid, txdata->txq_index); 1112} 1113 1114static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) 1115{ 1116 return bp->cnic_base_cl_id + cl_idx + 1117 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; 1118} 1119 1120static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) 1121{ 1122 /* the 'first' id is allocated for the cnic */ 1123 return bp->base_fw_ndsb; 1124} 1125 1126static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) 1127{ 1128 return bp->igu_base_sb; 1129} 1130 1131static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, 1132 struct bnx2x_fp_txdata *txdata) 1133{ 1134 int cnt = 1000; 1135 1136 while (bnx2x_has_tx_work_unload(txdata)) { 1137 if (!cnt) { 1138 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", 1139 txdata->txq_index, txdata->tx_pkt_prod, 1140 txdata->tx_pkt_cons); 1141#ifdef BNX2X_STOP_ON_ERROR 1142 bnx2x_panic(); 1143 return -EBUSY; 1144#else 1145 break; 1146#endif 1147 } 1148 cnt--; 1149 usleep_range(1000, 2000); 1150 } 1151 1152 return 0; 1153} 1154 1155int bnx2x_get_link_cfg_idx(struct bnx2x *bp); 1156 1157static inline void __storm_memset_struct(struct bnx2x *bp, 1158 u32 addr, size_t size, u32 *data) 1159{ 1160 int i; 1161 for (i = 0; i < size/4; i++) 1162 REG_WR(bp, addr + (i * 4), data[i]); 1163} 1164 1165/** 1166 * bnx2x_wait_sp_comp - wait for the outstanding SP commands. 1167 * 1168 * @bp: driver handle 1169 * @mask: bits that need to be cleared 1170 */ 1171static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) 1172{ 1173 int tout = 5000; /* Wait for 5 secs tops */ 1174 1175 while (tout--) { 1176 smp_mb(); 1177 netif_addr_lock_bh(bp->dev); 1178 if (!(bp->sp_state & mask)) { 1179 netif_addr_unlock_bh(bp->dev); 1180 return true; 1181 } 1182 netif_addr_unlock_bh(bp->dev); 1183 1184 usleep_range(1000, 2000); 1185 } 1186 1187 smp_mb(); 1188 1189 netif_addr_lock_bh(bp->dev); 1190 if (bp->sp_state & mask) { 1191 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", 1192 bp->sp_state, mask); 1193 netif_addr_unlock_bh(bp->dev); 1194 return false; 1195 } 1196 netif_addr_unlock_bh(bp->dev); 1197 1198 return true; 1199} 1200 1201/** 1202 * bnx2x_set_ctx_validation - set CDU context validation values 1203 * 1204 * @bp: driver handle 1205 * @cxt: context of the connection on the host memory 1206 * @cid: SW CID of the connection to be configured 1207 */ 1208void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, 1209 u32 cid); 1210 1211void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, 1212 u8 sb_index, u8 disable, u16 usec); 1213void bnx2x_acquire_phy_lock(struct bnx2x *bp); 1214void bnx2x_release_phy_lock(struct bnx2x *bp); 1215 1216/** 1217 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. 1218 * 1219 * @bp: driver handle 1220 * @mf_cfg: MF configuration 1221 * 1222 */ 1223static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) 1224{ 1225 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 1226 FUNC_MF_CFG_MAX_BW_SHIFT; 1227 if (!max_cfg) { 1228 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, 1229 "Max BW configured to 0 - using 100 instead\n"); 1230 max_cfg = 100; 1231 } 1232 return max_cfg; 1233} 1234 1235/* checks if HW supports GRO for given MTU */ 1236static inline bool bnx2x_mtu_allows_gro(int mtu) 1237{ 1238 /* gro frags per page */ 1239 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); 1240 1241 /* 1242 * 1. Number of frags should not grow above MAX_SKB_FRAGS 1243 * 2. Frag must fit the page 1244 */ 1245 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; 1246} 1247 1248/** 1249 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. 1250 * 1251 * @bp: driver handle 1252 * 1253 */ 1254void bnx2x_get_iscsi_info(struct bnx2x *bp); 1255 1256/** 1257 * bnx2x_link_sync_notify - send notification to other functions. 1258 * 1259 * @bp: driver handle 1260 * 1261 */ 1262static inline void bnx2x_link_sync_notify(struct bnx2x *bp) 1263{ 1264 int func; 1265 int vn; 1266 1267 /* Set the attention towards other drivers on the same port */ 1268 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 1269 if (vn == BP_VN(bp)) 1270 continue; 1271 1272 func = func_by_vn(bp, vn); 1273 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + 1274 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); 1275 } 1276} 1277 1278/** 1279 * bnx2x_update_drv_flags - update flags in shmem 1280 * 1281 * @bp: driver handle 1282 * @flags: flags to update 1283 * @set: set or clear 1284 * 1285 */ 1286static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) 1287{ 1288 if (SHMEM2_HAS(bp, drv_flags)) { 1289 u32 drv_flags; 1290 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1291 drv_flags = SHMEM2_RD(bp, drv_flags); 1292 1293 if (set) 1294 SET_FLAGS(drv_flags, flags); 1295 else 1296 RESET_FLAGS(drv_flags, flags); 1297 1298 SHMEM2_WR(bp, drv_flags, drv_flags); 1299 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); 1300 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1301 } 1302} 1303 1304static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) 1305{ 1306 if (is_valid_ether_addr(addr) || 1307 (is_zero_ether_addr(addr) && 1308 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)))) 1309 return true; 1310 1311 return false; 1312} 1313 1314/** 1315 * bnx2x_fill_fw_str - Fill buffer with FW version string 1316 * 1317 * @bp: driver handle 1318 * @buf: character buffer to fill with the fw name 1319 * @buf_len: length of the above buffer 1320 * 1321 */ 1322void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len); 1323 1324int bnx2x_drain_tx_queues(struct bnx2x *bp); 1325void bnx2x_squeeze_objects(struct bnx2x *bp); 1326 1327void bnx2x_schedule_sp_rtnl(struct bnx2x*, enum sp_rtnl_flag, 1328 u32 verbose); 1329 1330#endif /* BNX2X_CMN_H */ 1331