bnx2x_cmn.h revision 7d515413557907078e805ee7fd6f3920bc33762d
1/* bnx2x_cmn.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2012 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17#ifndef BNX2X_CMN_H 18#define BNX2X_CMN_H 19 20#include <linux/types.h> 21#include <linux/pci.h> 22#include <linux/netdevice.h> 23#include <linux/etherdevice.h> 24 25 26#include "bnx2x.h" 27 28/* This is used as a replacement for an MCP if it's not present */ 29extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ 30 31extern int num_queues; 32extern int int_mode; 33 34/************************ Macros ********************************/ 35#define BNX2X_PCI_FREE(x, y, size) \ 36 do { \ 37 if (x) { \ 38 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ 39 x = NULL; \ 40 y = 0; \ 41 } \ 42 } while (0) 43 44#define BNX2X_FREE(x) \ 45 do { \ 46 if (x) { \ 47 kfree((void *)x); \ 48 x = NULL; \ 49 } \ 50 } while (0) 51 52#define BNX2X_PCI_ALLOC(x, y, size) \ 53 do { \ 54 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 55 if (x == NULL) \ 56 goto alloc_mem_err; \ 57 memset((void *)x, 0, size); \ 58 } while (0) 59 60#define BNX2X_ALLOC(x, size) \ 61 do { \ 62 x = kzalloc(size, GFP_KERNEL); \ 63 if (x == NULL) \ 64 goto alloc_mem_err; \ 65 } while (0) 66 67/*********************** Interfaces **************************** 68 * Functions that need to be implemented by each driver version 69 */ 70/* Init */ 71 72/** 73 * bnx2x_send_unload_req - request unload mode from the MCP. 74 * 75 * @bp: driver handle 76 * @unload_mode: requested function's unload mode 77 * 78 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 79 */ 80u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); 81 82/** 83 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 84 * 85 * @bp: driver handle 86 */ 87void bnx2x_send_unload_done(struct bnx2x *bp); 88 89/** 90 * bnx2x_config_rss_pf - configure RSS parameters in a PF. 91 * 92 * @bp: driver handle 93 * @rss_obj RSS object to use 94 * @ind_table: indirection table to configure 95 * @config_hash: re-configure RSS hash keys configuration 96 */ 97int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj, 98 bool config_hash); 99 100/** 101 * bnx2x__init_func_obj - init function object 102 * 103 * @bp: driver handle 104 * 105 * Initializes the Function Object with the appropriate 106 * parameters which include a function slow path driver 107 * interface. 108 */ 109void bnx2x__init_func_obj(struct bnx2x *bp); 110 111/** 112 * bnx2x_setup_queue - setup eth queue. 113 * 114 * @bp: driver handle 115 * @fp: pointer to the fastpath structure 116 * @leading: boolean 117 * 118 */ 119int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 120 bool leading); 121 122/** 123 * bnx2x_setup_leading - bring up a leading eth queue. 124 * 125 * @bp: driver handle 126 */ 127int bnx2x_setup_leading(struct bnx2x *bp); 128 129/** 130 * bnx2x_fw_command - send the MCP a request 131 * 132 * @bp: driver handle 133 * @command: request 134 * @param: request's parameter 135 * 136 * block until there is a reply 137 */ 138u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); 139 140/** 141 * bnx2x_initial_phy_init - initialize link parameters structure variables. 142 * 143 * @bp: driver handle 144 * @load_mode: current mode 145 */ 146u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); 147 148/** 149 * bnx2x_link_set - configure hw according to link parameters structure. 150 * 151 * @bp: driver handle 152 */ 153void bnx2x_link_set(struct bnx2x *bp); 154 155/** 156 * bnx2x_link_test - query link status. 157 * 158 * @bp: driver handle 159 * @is_serdes: bool 160 * 161 * Returns 0 if link is UP. 162 */ 163u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); 164 165/** 166 * bnx2x_drv_pulse - write driver pulse to shmem 167 * 168 * @bp: driver handle 169 * 170 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox 171 * in the shmem. 172 */ 173void bnx2x_drv_pulse(struct bnx2x *bp); 174 175/** 176 * bnx2x_igu_ack_sb - update IGU with current SB value 177 * 178 * @bp: driver handle 179 * @igu_sb_id: SB id 180 * @segment: SB segment 181 * @index: SB index 182 * @op: SB operation 183 * @update: is HW update required 184 */ 185void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 186 u16 index, u8 op, u8 update); 187 188/* Disable transactions from chip to host */ 189void bnx2x_pf_disable(struct bnx2x *bp); 190 191/** 192 * bnx2x__link_status_update - handles link status change. 193 * 194 * @bp: driver handle 195 */ 196void bnx2x__link_status_update(struct bnx2x *bp); 197 198/** 199 * bnx2x_link_report - report link status to upper layer. 200 * 201 * @bp: driver handle 202 */ 203void bnx2x_link_report(struct bnx2x *bp); 204 205/* None-atomic version of bnx2x_link_report() */ 206void __bnx2x_link_report(struct bnx2x *bp); 207 208/** 209 * bnx2x_get_mf_speed - calculate MF speed. 210 * 211 * @bp: driver handle 212 * 213 * Takes into account current linespeed and MF configuration. 214 */ 215u16 bnx2x_get_mf_speed(struct bnx2x *bp); 216 217/** 218 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler 219 * 220 * @irq: irq number 221 * @dev_instance: private instance 222 */ 223irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); 224 225/** 226 * bnx2x_interrupt - non MSI-X interrupt handler 227 * 228 * @irq: irq number 229 * @dev_instance: private instance 230 */ 231irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); 232#ifdef BCM_CNIC 233 234/** 235 * bnx2x_cnic_notify - send command to cnic driver 236 * 237 * @bp: driver handle 238 * @cmd: command 239 */ 240int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); 241 242/** 243 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information 244 * 245 * @bp: driver handle 246 */ 247void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); 248 249/** 250 * bnx2x_setup_cnic_info - provides cnic with updated info 251 * 252 * @bp: driver handle 253 */ 254void bnx2x_setup_cnic_info(struct bnx2x *bp); 255 256#endif 257 258/** 259 * bnx2x_int_enable - enable HW interrupts. 260 * 261 * @bp: driver handle 262 */ 263void bnx2x_int_enable(struct bnx2x *bp); 264 265/** 266 * bnx2x_int_disable_sync - disable interrupts. 267 * 268 * @bp: driver handle 269 * @disable_hw: true, disable HW interrupts. 270 * 271 * This function ensures that there are no 272 * ISRs or SP DPCs (sp_task) are running after it returns. 273 */ 274void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); 275 276/** 277 * bnx2x_nic_init - init driver internals. 278 * 279 * @bp: driver handle 280 * @load_code: COMMON, PORT or FUNCTION 281 * 282 * Initializes: 283 * - rings 284 * - status blocks 285 * - etc. 286 */ 287void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); 288 289/** 290 * bnx2x_alloc_mem - allocate driver's memory. 291 * 292 * @bp: driver handle 293 */ 294int bnx2x_alloc_mem(struct bnx2x *bp); 295 296/** 297 * bnx2x_free_mem - release driver's memory. 298 * 299 * @bp: driver handle 300 */ 301void bnx2x_free_mem(struct bnx2x *bp); 302 303/** 304 * bnx2x_set_num_queues - set number of queues according to mode. 305 * 306 * @bp: driver handle 307 */ 308void bnx2x_set_num_queues(struct bnx2x *bp); 309 310/** 311 * bnx2x_chip_cleanup - cleanup chip internals. 312 * 313 * @bp: driver handle 314 * @unload_mode: COMMON, PORT, FUNCTION 315 * 316 * - Cleanup MAC configuration. 317 * - Closes clients. 318 * - etc. 319 */ 320void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode); 321 322/** 323 * bnx2x_acquire_hw_lock - acquire HW lock. 324 * 325 * @bp: driver handle 326 * @resource: resource bit which was locked 327 */ 328int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); 329 330/** 331 * bnx2x_release_hw_lock - release HW lock. 332 * 333 * @bp: driver handle 334 * @resource: resource bit which was locked 335 */ 336int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); 337 338/** 339 * bnx2x_release_leader_lock - release recovery leader lock 340 * 341 * @bp: driver handle 342 */ 343int bnx2x_release_leader_lock(struct bnx2x *bp); 344 345/** 346 * bnx2x_set_eth_mac - configure eth MAC address in the HW 347 * 348 * @bp: driver handle 349 * @set: set or clear 350 * 351 * Configures according to the value in netdev->dev_addr. 352 */ 353int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); 354 355/** 356 * bnx2x_set_rx_mode - set MAC filtering configurations. 357 * 358 * @dev: netdevice 359 * 360 * called with netif_tx_lock from dev_mcast.c 361 * If bp->state is OPEN, should be called with 362 * netif_addr_lock_bh() 363 */ 364void bnx2x_set_rx_mode(struct net_device *dev); 365 366/** 367 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. 368 * 369 * @bp: driver handle 370 * 371 * If bp->state is OPEN, should be called with 372 * netif_addr_lock_bh(). 373 */ 374void bnx2x_set_storm_rx_mode(struct bnx2x *bp); 375 376/** 377 * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. 378 * 379 * @bp: driver handle 380 * @cl_id: client id 381 * @rx_mode_flags: rx mode configuration 382 * @rx_accept_flags: rx accept configuration 383 * @tx_accept_flags: tx accept configuration (tx switch) 384 * @ramrod_flags: ramrod configuration 385 */ 386void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 387 unsigned long rx_mode_flags, 388 unsigned long rx_accept_flags, 389 unsigned long tx_accept_flags, 390 unsigned long ramrod_flags); 391 392/* Parity errors related */ 393void bnx2x_set_pf_load(struct bnx2x *bp); 394bool bnx2x_clear_pf_load(struct bnx2x *bp); 395bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); 396bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); 397void bnx2x_set_reset_in_progress(struct bnx2x *bp); 398void bnx2x_set_reset_global(struct bnx2x *bp); 399void bnx2x_disable_close_the_gate(struct bnx2x *bp); 400 401/** 402 * bnx2x_sp_event - handle ramrods completion. 403 * 404 * @fp: fastpath handle for the event 405 * @rr_cqe: eth_rx_cqe 406 */ 407void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); 408 409/** 410 * bnx2x_ilt_set_info - prepare ILT configurations. 411 * 412 * @bp: driver handle 413 */ 414void bnx2x_ilt_set_info(struct bnx2x *bp); 415 416/** 417 * bnx2x_dcbx_init - initialize dcbx protocol. 418 * 419 * @bp: driver handle 420 */ 421void bnx2x_dcbx_init(struct bnx2x *bp, bool update_shmem); 422 423/** 424 * bnx2x_set_power_state - set power state to the requested value. 425 * 426 * @bp: driver handle 427 * @state: required state D0 or D3hot 428 * 429 * Currently only D0 and D3hot are supported. 430 */ 431int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); 432 433/** 434 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. 435 * 436 * @bp: driver handle 437 * @value: new value 438 */ 439void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); 440/* Error handling */ 441void bnx2x_panic_dump(struct bnx2x *bp); 442 443void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); 444 445/* validate currect fw is loaded */ 446bool bnx2x_test_firmware_version(struct bnx2x *bp, bool is_err); 447 448/* dev_close main block */ 449int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode); 450 451/* dev_open main block */ 452int bnx2x_nic_load(struct bnx2x *bp, int load_mode); 453 454/* hard_xmit callback */ 455netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); 456 457/* setup_tc callback */ 458int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); 459 460/* select_queue callback */ 461u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); 462 463/* reload helper */ 464int bnx2x_reload_if_running(struct net_device *dev); 465 466int bnx2x_change_mac_addr(struct net_device *dev, void *p); 467 468/* NAPI poll Rx part */ 469int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); 470 471void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 472 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod); 473 474/* NAPI poll Tx part */ 475int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); 476 477/* suspend/resume callbacks */ 478int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); 479int bnx2x_resume(struct pci_dev *pdev); 480 481/* Release IRQ vectors */ 482void bnx2x_free_irq(struct bnx2x *bp); 483 484void bnx2x_free_fp_mem(struct bnx2x *bp); 485int bnx2x_alloc_fp_mem(struct bnx2x *bp); 486void bnx2x_init_rx_rings(struct bnx2x *bp); 487void bnx2x_free_skbs(struct bnx2x *bp); 488void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); 489void bnx2x_netif_start(struct bnx2x *bp); 490 491/** 492 * bnx2x_enable_msix - set msix configuration. 493 * 494 * @bp: driver handle 495 * 496 * fills msix_table, requests vectors, updates num_queues 497 * according to number of available vectors. 498 */ 499int bnx2x_enable_msix(struct bnx2x *bp); 500 501/** 502 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly 503 * 504 * @bp: driver handle 505 */ 506int bnx2x_enable_msi(struct bnx2x *bp); 507 508/** 509 * bnx2x_poll - NAPI callback 510 * 511 * @napi: napi structure 512 * @budget: 513 * 514 */ 515int bnx2x_poll(struct napi_struct *napi, int budget); 516 517/** 518 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure 519 * 520 * @bp: driver handle 521 */ 522int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp); 523 524/** 525 * bnx2x_free_mem_bp - release memories outsize main driver structure 526 * 527 * @bp: driver handle 528 */ 529void bnx2x_free_mem_bp(struct bnx2x *bp); 530 531/** 532 * bnx2x_change_mtu - change mtu netdev callback 533 * 534 * @dev: net device 535 * @new_mtu: requested mtu 536 * 537 */ 538int bnx2x_change_mtu(struct net_device *dev, int new_mtu); 539 540#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 541/** 542 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port 543 * 544 * @dev: net_device 545 * @wwn: output buffer 546 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) 547 * 548 */ 549int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); 550#endif 551 552netdev_features_t bnx2x_fix_features(struct net_device *dev, 553 netdev_features_t features); 554int bnx2x_set_features(struct net_device *dev, netdev_features_t features); 555 556/** 557 * bnx2x_tx_timeout - tx timeout netdev callback 558 * 559 * @dev: net device 560 */ 561void bnx2x_tx_timeout(struct net_device *dev); 562 563/*********************** Inlines **********************************/ 564/*********************** Fast path ********************************/ 565static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 566{ 567 barrier(); /* status block is written to by the chip */ 568 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 569} 570 571static inline void bnx2x_update_rx_prod_gen(struct bnx2x *bp, 572 struct bnx2x_fastpath *fp, u16 bd_prod, 573 u16 rx_comp_prod, u16 rx_sge_prod, u32 start) 574{ 575 struct ustorm_eth_rx_producers rx_prods = {0}; 576 u32 i; 577 578 /* Update producers */ 579 rx_prods.bd_prod = bd_prod; 580 rx_prods.cqe_prod = rx_comp_prod; 581 rx_prods.sge_prod = rx_sge_prod; 582 583 /* 584 * Make sure that the BD and SGE data is updated before updating the 585 * producers since FW might read the BD/SGE right after the producer 586 * is updated. 587 * This is only applicable for weak-ordered memory model archs such 588 * as IA-64. The following barrier is also mandatory since FW will 589 * assumes BDs must have buffers. 590 */ 591 wmb(); 592 593 for (i = 0; i < sizeof(rx_prods)/4; i++) 594 REG_WR(bp, start + i*4, ((u32 *)&rx_prods)[i]); 595 596 mmiowb(); /* keep prod updates ordered */ 597 598 DP(NETIF_MSG_RX_STATUS, 599 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", 600 fp->index, bd_prod, rx_comp_prod, rx_sge_prod); 601} 602 603static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, 604 u8 segment, u16 index, u8 op, 605 u8 update, u32 igu_addr) 606{ 607 struct igu_regular cmd_data = {0}; 608 609 cmd_data.sb_id_and_flags = 610 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 611 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 612 (update << IGU_REGULAR_BUPDATE_SHIFT) | 613 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 614 615 DP(NETIF_MSG_INTR, "write 0x%08x to IGU addr 0x%x\n", 616 cmd_data.sb_id_and_flags, igu_addr); 617 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); 618 619 /* Make sure that ACK is written */ 620 mmiowb(); 621 barrier(); 622} 623 624static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, 625 u8 storm, u16 index, u8 op, u8 update) 626{ 627 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 628 COMMAND_REG_INT_ACK); 629 struct igu_ack_register igu_ack; 630 631 igu_ack.status_block_index = index; 632 igu_ack.sb_id_and_flags = 633 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 634 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 635 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 636 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 637 638 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); 639 640 /* Make sure that ACK is written */ 641 mmiowb(); 642 barrier(); 643} 644 645static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, 646 u16 index, u8 op, u8 update) 647{ 648 if (bp->common.int_block == INT_BLOCK_HC) 649 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); 650 else { 651 u8 segment; 652 653 if (CHIP_INT_MODE_IS_BC(bp)) 654 segment = storm; 655 else if (igu_sb_id != bp->igu_dsb_id) 656 segment = IGU_SEG_ACCESS_DEF; 657 else if (storm == ATTENTION_ID) 658 segment = IGU_SEG_ACCESS_ATTN; 659 else 660 segment = IGU_SEG_ACCESS_DEF; 661 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); 662 } 663} 664 665static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) 666{ 667 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 668 COMMAND_REG_SIMD_MASK); 669 u32 result = REG_RD(bp, hc_addr); 670 671 barrier(); 672 return result; 673} 674 675static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) 676{ 677 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 678 u32 result = REG_RD(bp, igu_addr); 679 680 DP(NETIF_MSG_INTR, "read 0x%08x from IGU addr 0x%x\n", 681 result, igu_addr); 682 683 barrier(); 684 return result; 685} 686 687static inline u16 bnx2x_ack_int(struct bnx2x *bp) 688{ 689 barrier(); 690 if (bp->common.int_block == INT_BLOCK_HC) 691 return bnx2x_hc_ack_int(bp); 692 else 693 return bnx2x_igu_ack_int(bp); 694} 695 696static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) 697{ 698 /* Tell compiler that consumer and producer can change */ 699 barrier(); 700 return txdata->tx_pkt_prod != txdata->tx_pkt_cons; 701} 702 703static inline u16 bnx2x_tx_avail(struct bnx2x *bp, 704 struct bnx2x_fp_txdata *txdata) 705{ 706 s16 used; 707 u16 prod; 708 u16 cons; 709 710 prod = txdata->tx_bd_prod; 711 cons = txdata->tx_bd_cons; 712 713 /* NUM_TX_RINGS = number of "next-page" entries 714 It will be used as a threshold */ 715 used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS; 716 717#ifdef BNX2X_STOP_ON_ERROR 718 WARN_ON(used < 0); 719 WARN_ON(used > bp->tx_ring_size); 720 WARN_ON((bp->tx_ring_size - used) > MAX_TX_AVAIL); 721#endif 722 723 return (s16)(bp->tx_ring_size) - used; 724} 725 726static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) 727{ 728 u16 hw_cons; 729 730 /* Tell compiler that status block fields can change */ 731 barrier(); 732 hw_cons = le16_to_cpu(*txdata->tx_cons_sb); 733 return hw_cons != txdata->tx_pkt_cons; 734} 735 736static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) 737{ 738 u8 cos; 739 for_each_cos_in_tx_queue(fp, cos) 740 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos])) 741 return true; 742 return false; 743} 744 745static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) 746{ 747 u16 rx_cons_sb; 748 749 /* Tell compiler that status block fields can change */ 750 barrier(); 751 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); 752 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) 753 rx_cons_sb++; 754 return (fp->rx_comp_cons != rx_cons_sb); 755} 756 757/** 758 * bnx2x_tx_disable - disables tx from stack point of view 759 * 760 * @bp: driver handle 761 */ 762static inline void bnx2x_tx_disable(struct bnx2x *bp) 763{ 764 netif_tx_disable(bp->dev); 765 netif_carrier_off(bp->dev); 766} 767 768static inline void bnx2x_free_rx_sge(struct bnx2x *bp, 769 struct bnx2x_fastpath *fp, u16 index) 770{ 771 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; 772 struct page *page = sw_buf->page; 773 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; 774 775 /* Skip "next page" elements */ 776 if (!page) 777 return; 778 779 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), 780 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); 781 __free_pages(page, PAGES_PER_SGE_SHIFT); 782 783 sw_buf->page = NULL; 784 sge->addr_hi = 0; 785 sge->addr_lo = 0; 786} 787 788static inline void bnx2x_add_all_napi(struct bnx2x *bp) 789{ 790 int i; 791 792 bp->num_napi_queues = bp->num_queues; 793 794 /* Add NAPI objects */ 795 for_each_napi_rx_queue(bp, i) 796 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 797 bnx2x_poll, BNX2X_NAPI_WEIGHT); 798} 799 800static inline void bnx2x_del_all_napi(struct bnx2x *bp) 801{ 802 int i; 803 804 for_each_napi_rx_queue(bp, i) 805 netif_napi_del(&bnx2x_fp(bp, i, napi)); 806} 807 808void bnx2x_set_int_mode(struct bnx2x *bp); 809 810static inline void bnx2x_disable_msi(struct bnx2x *bp) 811{ 812 if (bp->flags & USING_MSIX_FLAG) { 813 pci_disable_msix(bp->pdev); 814 bp->flags &= ~(USING_MSIX_FLAG | USING_SINGLE_MSIX_FLAG); 815 } else if (bp->flags & USING_MSI_FLAG) { 816 pci_disable_msi(bp->pdev); 817 bp->flags &= ~USING_MSI_FLAG; 818 } 819} 820 821static inline int bnx2x_calc_num_queues(struct bnx2x *bp) 822{ 823 return num_queues ? 824 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : 825 min_t(int, netif_get_num_default_rss_queues(), 826 BNX2X_MAX_QUEUES(bp)); 827} 828 829static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) 830{ 831 int i, j; 832 833 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { 834 int idx = RX_SGE_CNT * i - 1; 835 836 for (j = 0; j < 2; j++) { 837 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); 838 idx--; 839 } 840 } 841} 842 843static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) 844{ 845 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ 846 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); 847 848 /* Clear the two last indices in the page to 1: 849 these are the indices that correspond to the "next" element, 850 hence will never be indicated and should be removed from 851 the calculations. */ 852 bnx2x_clear_sge_mask_next_elems(fp); 853} 854 855/* note that we are not allocating a new buffer, 856 * we are just moving one from cons to prod 857 * we are not creating a new mapping, 858 * so there is no need to check for dma_mapping_error(). 859 */ 860static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, 861 u16 cons, u16 prod) 862{ 863 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; 864 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; 865 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; 866 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; 867 868 dma_unmap_addr_set(prod_rx_buf, mapping, 869 dma_unmap_addr(cons_rx_buf, mapping)); 870 prod_rx_buf->data = cons_rx_buf->data; 871 *prod_bd = *cons_bd; 872} 873 874/************************* Init ******************************************/ 875 876/* returns func by VN for current port */ 877static inline int func_by_vn(struct bnx2x *bp, int vn) 878{ 879 return 2 * vn + BP_PORT(bp); 880} 881 882static inline int bnx2x_config_rss_eth(struct bnx2x *bp, bool config_hash) 883{ 884 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, config_hash); 885} 886 887/** 888 * bnx2x_func_start - init function 889 * 890 * @bp: driver handle 891 * 892 * Must be called before sending CLIENT_SETUP for the first client. 893 */ 894static inline int bnx2x_func_start(struct bnx2x *bp) 895{ 896 struct bnx2x_func_state_params func_params = {NULL}; 897 struct bnx2x_func_start_params *start_params = 898 &func_params.params.start; 899 900 /* Prepare parameters for function state transitions */ 901 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 902 903 func_params.f_obj = &bp->func_obj; 904 func_params.cmd = BNX2X_F_CMD_START; 905 906 /* Function parameters */ 907 start_params->mf_mode = bp->mf_mode; 908 start_params->sd_vlan_tag = bp->mf_ov; 909 910 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) 911 start_params->network_cos_mode = STATIC_COS; 912 else /* CHIP_IS_E1X */ 913 start_params->network_cos_mode = FW_WRR; 914 915 return bnx2x_func_state_change(bp, &func_params); 916} 917 918 919/** 920 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format 921 * 922 * @fw_hi: pointer to upper part 923 * @fw_mid: pointer to middle part 924 * @fw_lo: pointer to lower part 925 * @mac: pointer to MAC address 926 */ 927static inline void bnx2x_set_fw_mac_addr(u16 *fw_hi, u16 *fw_mid, u16 *fw_lo, 928 u8 *mac) 929{ 930 ((u8 *)fw_hi)[0] = mac[1]; 931 ((u8 *)fw_hi)[1] = mac[0]; 932 ((u8 *)fw_mid)[0] = mac[3]; 933 ((u8 *)fw_mid)[1] = mac[2]; 934 ((u8 *)fw_lo)[0] = mac[5]; 935 ((u8 *)fw_lo)[1] = mac[4]; 936} 937 938static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, 939 struct bnx2x_fastpath *fp, int last) 940{ 941 int i; 942 943 if (fp->disable_tpa) 944 return; 945 946 for (i = 0; i < last; i++) 947 bnx2x_free_rx_sge(bp, fp, i); 948} 949 950static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) 951{ 952 int i; 953 954 for (i = 1; i <= NUM_RX_RINGS; i++) { 955 struct eth_rx_bd *rx_bd; 956 957 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; 958 rx_bd->addr_hi = 959 cpu_to_le32(U64_HI(fp->rx_desc_mapping + 960 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 961 rx_bd->addr_lo = 962 cpu_to_le32(U64_LO(fp->rx_desc_mapping + 963 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 964 } 965} 966 967/* Statistics ID are global per chip/path, while Client IDs for E1x are per 968 * port. 969 */ 970static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) 971{ 972 struct bnx2x *bp = fp->bp; 973 if (!CHIP_IS_E1x(bp)) { 974#ifdef BCM_CNIC 975 /* there are special statistics counters for FCoE 136..140 */ 976 if (IS_FCOE_FP(fp)) 977 return bp->cnic_base_cl_id + (bp->pf_num >> 1); 978#endif 979 return fp->cl_id; 980 } 981 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; 982} 983 984static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, 985 bnx2x_obj_type obj_type) 986{ 987 struct bnx2x *bp = fp->bp; 988 989 /* Configure classification DBs */ 990 bnx2x_init_mac_obj(bp, &bnx2x_sp_obj(bp, fp).mac_obj, fp->cl_id, 991 fp->cid, BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), 992 bnx2x_sp_mapping(bp, mac_rdata), 993 BNX2X_FILTER_MAC_PENDING, 994 &bp->sp_state, obj_type, 995 &bp->macs_pool); 996} 997 998/** 999 * bnx2x_get_path_func_num - get number of active functions 1000 * 1001 * @bp: driver handle 1002 * 1003 * Calculates the number of active (not hidden) functions on the 1004 * current path. 1005 */ 1006static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) 1007{ 1008 u8 func_num = 0, i; 1009 1010 /* 57710 has only one function per-port */ 1011 if (CHIP_IS_E1(bp)) 1012 return 1; 1013 1014 /* Calculate a number of functions enabled on the current 1015 * PATH/PORT. 1016 */ 1017 if (CHIP_REV_IS_SLOW(bp)) { 1018 if (IS_MF(bp)) 1019 func_num = 4; 1020 else 1021 func_num = 2; 1022 } else { 1023 for (i = 0; i < E1H_FUNC_MAX / 2; i++) { 1024 u32 func_config = 1025 MF_CFG_RD(bp, 1026 func_mf_config[BP_PORT(bp) + 2 * i]. 1027 config); 1028 func_num += 1029 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); 1030 } 1031 } 1032 1033 WARN_ON(!func_num); 1034 1035 return func_num; 1036} 1037 1038static inline void bnx2x_init_bp_objs(struct bnx2x *bp) 1039{ 1040 /* RX_MODE controlling object */ 1041 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); 1042 1043 /* multicast configuration controlling object */ 1044 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, 1045 BP_FUNC(bp), BP_FUNC(bp), 1046 bnx2x_sp(bp, mcast_rdata), 1047 bnx2x_sp_mapping(bp, mcast_rdata), 1048 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, 1049 BNX2X_OBJ_TYPE_RX); 1050 1051 /* Setup CAM credit pools */ 1052 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), 1053 bnx2x_get_path_func_num(bp)); 1054 1055 /* RSS configuration object */ 1056 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, 1057 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), 1058 bnx2x_sp(bp, rss_rdata), 1059 bnx2x_sp_mapping(bp, rss_rdata), 1060 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, 1061 BNX2X_OBJ_TYPE_RX); 1062} 1063 1064static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) 1065{ 1066 if (CHIP_IS_E1x(fp->bp)) 1067 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; 1068 else 1069 return fp->cl_id; 1070} 1071 1072static inline u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) 1073{ 1074 struct bnx2x *bp = fp->bp; 1075 1076 if (!CHIP_IS_E1x(bp)) 1077 return USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); 1078 else 1079 return USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); 1080} 1081 1082static inline void bnx2x_init_txdata(struct bnx2x *bp, 1083 struct bnx2x_fp_txdata *txdata, u32 cid, 1084 int txq_index, __le16 *tx_cons_sb, 1085 struct bnx2x_fastpath *fp) 1086{ 1087 txdata->cid = cid; 1088 txdata->txq_index = txq_index; 1089 txdata->tx_cons_sb = tx_cons_sb; 1090 txdata->parent_fp = fp; 1091 1092 DP(NETIF_MSG_IFUP, "created tx data cid %d, txq %d\n", 1093 txdata->cid, txdata->txq_index); 1094} 1095 1096#ifdef BCM_CNIC 1097static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) 1098{ 1099 return bp->cnic_base_cl_id + cl_idx + 1100 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; 1101} 1102 1103static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) 1104{ 1105 1106 /* the 'first' id is allocated for the cnic */ 1107 return bp->base_fw_ndsb; 1108} 1109 1110static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) 1111{ 1112 return bp->igu_base_sb; 1113} 1114 1115 1116static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) 1117{ 1118 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 1119 unsigned long q_type = 0; 1120 1121 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); 1122 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, 1123 BNX2X_FCOE_ETH_CL_ID_IDX); 1124 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID(bp); 1125 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; 1126 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; 1127 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; 1128 bnx2x_init_txdata(bp, bnx2x_fcoe(bp, txdata_ptr[0]), 1129 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX, 1130 fp); 1131 1132 DP(NETIF_MSG_IFUP, "created fcoe tx data (fp index %d)\n", fp->index); 1133 1134 /* qZone id equals to FW (per path) client id */ 1135 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); 1136 /* init shortcut */ 1137 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = 1138 bnx2x_rx_ustorm_prods_offset(fp); 1139 1140 /* Configure Queue State object */ 1141 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1142 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1143 1144 /* No multi-CoS for FCoE L2 client */ 1145 BUG_ON(fp->max_cos != 1); 1146 1147 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, 1148 &fp->cid, 1, BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 1149 bnx2x_sp_mapping(bp, q_rdata), q_type); 1150 1151 DP(NETIF_MSG_IFUP, 1152 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n", 1153 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 1154 fp->igu_sb_id); 1155} 1156#endif 1157 1158static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, 1159 struct bnx2x_fp_txdata *txdata) 1160{ 1161 int cnt = 1000; 1162 1163 while (bnx2x_has_tx_work_unload(txdata)) { 1164 if (!cnt) { 1165 BNX2X_ERR("timeout waiting for queue[%d]: txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", 1166 txdata->txq_index, txdata->tx_pkt_prod, 1167 txdata->tx_pkt_cons); 1168#ifdef BNX2X_STOP_ON_ERROR 1169 bnx2x_panic(); 1170 return -EBUSY; 1171#else 1172 break; 1173#endif 1174 } 1175 cnt--; 1176 usleep_range(1000, 1000); 1177 } 1178 1179 return 0; 1180} 1181 1182int bnx2x_get_link_cfg_idx(struct bnx2x *bp); 1183 1184static inline void __storm_memset_struct(struct bnx2x *bp, 1185 u32 addr, size_t size, u32 *data) 1186{ 1187 int i; 1188 for (i = 0; i < size/4; i++) 1189 REG_WR(bp, addr + (i * 4), data[i]); 1190} 1191 1192/** 1193 * bnx2x_wait_sp_comp - wait for the outstanding SP commands. 1194 * 1195 * @bp: driver handle 1196 * @mask: bits that need to be cleared 1197 */ 1198static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) 1199{ 1200 int tout = 5000; /* Wait for 5 secs tops */ 1201 1202 while (tout--) { 1203 smp_mb(); 1204 netif_addr_lock_bh(bp->dev); 1205 if (!(bp->sp_state & mask)) { 1206 netif_addr_unlock_bh(bp->dev); 1207 return true; 1208 } 1209 netif_addr_unlock_bh(bp->dev); 1210 1211 usleep_range(1000, 1000); 1212 } 1213 1214 smp_mb(); 1215 1216 netif_addr_lock_bh(bp->dev); 1217 if (bp->sp_state & mask) { 1218 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, mask 0x%lx\n", 1219 bp->sp_state, mask); 1220 netif_addr_unlock_bh(bp->dev); 1221 return false; 1222 } 1223 netif_addr_unlock_bh(bp->dev); 1224 1225 return true; 1226} 1227 1228/** 1229 * bnx2x_set_ctx_validation - set CDU context validation values 1230 * 1231 * @bp: driver handle 1232 * @cxt: context of the connection on the host memory 1233 * @cid: SW CID of the connection to be configured 1234 */ 1235void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, 1236 u32 cid); 1237 1238void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, 1239 u8 sb_index, u8 disable, u16 usec); 1240void bnx2x_acquire_phy_lock(struct bnx2x *bp); 1241void bnx2x_release_phy_lock(struct bnx2x *bp); 1242 1243/** 1244 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. 1245 * 1246 * @bp: driver handle 1247 * @mf_cfg: MF configuration 1248 * 1249 */ 1250static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) 1251{ 1252 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 1253 FUNC_MF_CFG_MAX_BW_SHIFT; 1254 if (!max_cfg) { 1255 DP(NETIF_MSG_IFUP | BNX2X_MSG_ETHTOOL, 1256 "Max BW configured to 0 - using 100 instead\n"); 1257 max_cfg = 100; 1258 } 1259 return max_cfg; 1260} 1261 1262/* checks if HW supports GRO for given MTU */ 1263static inline bool bnx2x_mtu_allows_gro(int mtu) 1264{ 1265 /* gro frags per page */ 1266 int fpp = SGE_PAGE_SIZE / (mtu - ETH_MAX_TPA_HEADER_SIZE); 1267 1268 /* 1269 * 1. number of frags should not grow above MAX_SKB_FRAGS 1270 * 2. frag must fit the page 1271 */ 1272 return mtu <= SGE_PAGE_SIZE && (U_ETH_SGL_SIZE * fpp) <= MAX_SKB_FRAGS; 1273} 1274#ifdef BCM_CNIC 1275/** 1276 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. 1277 * 1278 * @bp: driver handle 1279 * 1280 */ 1281void bnx2x_get_iscsi_info(struct bnx2x *bp); 1282#endif 1283 1284/** 1285 * bnx2x_link_sync_notify - send notification to other functions. 1286 * 1287 * @bp: driver handle 1288 * 1289 */ 1290static inline void bnx2x_link_sync_notify(struct bnx2x *bp) 1291{ 1292 int func; 1293 int vn; 1294 1295 /* Set the attention towards other drivers on the same port */ 1296 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 1297 if (vn == BP_VN(bp)) 1298 continue; 1299 1300 func = func_by_vn(bp, vn); 1301 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + 1302 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); 1303 } 1304} 1305 1306/** 1307 * bnx2x_update_drv_flags - update flags in shmem 1308 * 1309 * @bp: driver handle 1310 * @flags: flags to update 1311 * @set: set or clear 1312 * 1313 */ 1314static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) 1315{ 1316 if (SHMEM2_HAS(bp, drv_flags)) { 1317 u32 drv_flags; 1318 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1319 drv_flags = SHMEM2_RD(bp, drv_flags); 1320 1321 if (set) 1322 SET_FLAGS(drv_flags, flags); 1323 else 1324 RESET_FLAGS(drv_flags, flags); 1325 1326 SHMEM2_WR(bp, drv_flags, drv_flags); 1327 DP(NETIF_MSG_IFUP, "drv_flags 0x%08x\n", drv_flags); 1328 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_DRV_FLAGS); 1329 } 1330} 1331 1332static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) 1333{ 1334 if (is_valid_ether_addr(addr)) 1335 return true; 1336#ifdef BCM_CNIC 1337 if (is_zero_ether_addr(addr) && 1338 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) 1339 return true; 1340#endif 1341 return false; 1342} 1343 1344#endif /* BNX2X_CMN_H */ 1345