bnx2x_cmn.h revision c8f44affb7244f2ac3e703cab13d55ede27621bb
1/* bnx2x_cmn.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17#ifndef BNX2X_CMN_H 18#define BNX2X_CMN_H 19 20#include <linux/types.h> 21#include <linux/pci.h> 22#include <linux/netdevice.h> 23 24 25#include "bnx2x.h" 26 27/* This is used as a replacement for an MCP if it's not present */ 28extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ 29 30extern int num_queues; 31 32/************************ Macros ********************************/ 33#define BNX2X_PCI_FREE(x, y, size) \ 34 do { \ 35 if (x) { \ 36 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ 37 x = NULL; \ 38 y = 0; \ 39 } \ 40 } while (0) 41 42#define BNX2X_FREE(x) \ 43 do { \ 44 if (x) { \ 45 kfree((void *)x); \ 46 x = NULL; \ 47 } \ 48 } while (0) 49 50#define BNX2X_PCI_ALLOC(x, y, size) \ 51 do { \ 52 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 53 if (x == NULL) \ 54 goto alloc_mem_err; \ 55 memset((void *)x, 0, size); \ 56 } while (0) 57 58#define BNX2X_ALLOC(x, size) \ 59 do { \ 60 x = kzalloc(size, GFP_KERNEL); \ 61 if (x == NULL) \ 62 goto alloc_mem_err; \ 63 } while (0) 64 65/*********************** Interfaces **************************** 66 * Functions that need to be implemented by each driver version 67 */ 68/* Init */ 69 70/** 71 * bnx2x_send_unload_req - request unload mode from the MCP. 72 * 73 * @bp: driver handle 74 * @unload_mode: requested function's unload mode 75 * 76 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 77 */ 78u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); 79 80/** 81 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 82 * 83 * @bp: driver handle 84 */ 85void bnx2x_send_unload_done(struct bnx2x *bp); 86 87/** 88 * bnx2x_config_rss_pf - configure RSS parameters. 89 * 90 * @bp: driver handle 91 * @ind_table: indirection table to configure 92 * @config_hash: re-configure RSS hash keys configuration 93 */ 94int bnx2x_config_rss_pf(struct bnx2x *bp, u8 *ind_table, bool config_hash); 95 96/** 97 * bnx2x__init_func_obj - init function object 98 * 99 * @bp: driver handle 100 * 101 * Initializes the Function Object with the appropriate 102 * parameters which include a function slow path driver 103 * interface. 104 */ 105void bnx2x__init_func_obj(struct bnx2x *bp); 106 107/** 108 * bnx2x_setup_queue - setup eth queue. 109 * 110 * @bp: driver handle 111 * @fp: pointer to the fastpath structure 112 * @leading: boolean 113 * 114 */ 115int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 116 bool leading); 117 118/** 119 * bnx2x_setup_leading - bring up a leading eth queue. 120 * 121 * @bp: driver handle 122 */ 123int bnx2x_setup_leading(struct bnx2x *bp); 124 125/** 126 * bnx2x_fw_command - send the MCP a request 127 * 128 * @bp: driver handle 129 * @command: request 130 * @param: request's parameter 131 * 132 * block until there is a reply 133 */ 134u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); 135 136/** 137 * bnx2x_initial_phy_init - initialize link parameters structure variables. 138 * 139 * @bp: driver handle 140 * @load_mode: current mode 141 */ 142u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); 143 144/** 145 * bnx2x_link_set - configure hw according to link parameters structure. 146 * 147 * @bp: driver handle 148 */ 149void bnx2x_link_set(struct bnx2x *bp); 150 151/** 152 * bnx2x_link_test - query link status. 153 * 154 * @bp: driver handle 155 * @is_serdes: bool 156 * 157 * Returns 0 if link is UP. 158 */ 159u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); 160 161/** 162 * bnx2x_drv_pulse - write driver pulse to shmem 163 * 164 * @bp: driver handle 165 * 166 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox 167 * in the shmem. 168 */ 169void bnx2x_drv_pulse(struct bnx2x *bp); 170 171/** 172 * bnx2x_igu_ack_sb - update IGU with current SB value 173 * 174 * @bp: driver handle 175 * @igu_sb_id: SB id 176 * @segment: SB segment 177 * @index: SB index 178 * @op: SB operation 179 * @update: is HW update required 180 */ 181void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 182 u16 index, u8 op, u8 update); 183 184/* Disable transactions from chip to host */ 185void bnx2x_pf_disable(struct bnx2x *bp); 186 187/** 188 * bnx2x__link_status_update - handles link status change. 189 * 190 * @bp: driver handle 191 */ 192void bnx2x__link_status_update(struct bnx2x *bp); 193 194/** 195 * bnx2x_link_report - report link status to upper layer. 196 * 197 * @bp: driver handle 198 */ 199void bnx2x_link_report(struct bnx2x *bp); 200 201/* None-atomic version of bnx2x_link_report() */ 202void __bnx2x_link_report(struct bnx2x *bp); 203 204/** 205 * bnx2x_get_mf_speed - calculate MF speed. 206 * 207 * @bp: driver handle 208 * 209 * Takes into account current linespeed and MF configuration. 210 */ 211u16 bnx2x_get_mf_speed(struct bnx2x *bp); 212 213/** 214 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler 215 * 216 * @irq: irq number 217 * @dev_instance: private instance 218 */ 219irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); 220 221/** 222 * bnx2x_interrupt - non MSI-X interrupt handler 223 * 224 * @irq: irq number 225 * @dev_instance: private instance 226 */ 227irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); 228#ifdef BCM_CNIC 229 230/** 231 * bnx2x_cnic_notify - send command to cnic driver 232 * 233 * @bp: driver handle 234 * @cmd: command 235 */ 236int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); 237 238/** 239 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information 240 * 241 * @bp: driver handle 242 */ 243void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); 244#endif 245 246/** 247 * bnx2x_int_enable - enable HW interrupts. 248 * 249 * @bp: driver handle 250 */ 251void bnx2x_int_enable(struct bnx2x *bp); 252 253/** 254 * bnx2x_int_disable_sync - disable interrupts. 255 * 256 * @bp: driver handle 257 * @disable_hw: true, disable HW interrupts. 258 * 259 * This function ensures that there are no 260 * ISRs or SP DPCs (sp_task) are running after it returns. 261 */ 262void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); 263 264/** 265 * bnx2x_nic_init - init driver internals. 266 * 267 * @bp: driver handle 268 * @load_code: COMMON, PORT or FUNCTION 269 * 270 * Initializes: 271 * - rings 272 * - status blocks 273 * - etc. 274 */ 275void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); 276 277/** 278 * bnx2x_alloc_mem - allocate driver's memory. 279 * 280 * @bp: driver handle 281 */ 282int bnx2x_alloc_mem(struct bnx2x *bp); 283 284/** 285 * bnx2x_free_mem - release driver's memory. 286 * 287 * @bp: driver handle 288 */ 289void bnx2x_free_mem(struct bnx2x *bp); 290 291/** 292 * bnx2x_set_num_queues - set number of queues according to mode. 293 * 294 * @bp: driver handle 295 */ 296void bnx2x_set_num_queues(struct bnx2x *bp); 297 298/** 299 * bnx2x_chip_cleanup - cleanup chip internals. 300 * 301 * @bp: driver handle 302 * @unload_mode: COMMON, PORT, FUNCTION 303 * 304 * - Cleanup MAC configuration. 305 * - Closes clients. 306 * - etc. 307 */ 308void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode); 309 310/** 311 * bnx2x_acquire_hw_lock - acquire HW lock. 312 * 313 * @bp: driver handle 314 * @resource: resource bit which was locked 315 */ 316int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); 317 318/** 319 * bnx2x_release_hw_lock - release HW lock. 320 * 321 * @bp: driver handle 322 * @resource: resource bit which was locked 323 */ 324int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); 325 326/** 327 * bnx2x_release_leader_lock - release recovery leader lock 328 * 329 * @bp: driver handle 330 */ 331int bnx2x_release_leader_lock(struct bnx2x *bp); 332 333/** 334 * bnx2x_set_eth_mac - configure eth MAC address in the HW 335 * 336 * @bp: driver handle 337 * @set: set or clear 338 * 339 * Configures according to the value in netdev->dev_addr. 340 */ 341int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); 342 343/** 344 * bnx2x_set_rx_mode - set MAC filtering configurations. 345 * 346 * @dev: netdevice 347 * 348 * called with netif_tx_lock from dev_mcast.c 349 * If bp->state is OPEN, should be called with 350 * netif_addr_lock_bh() 351 */ 352void bnx2x_set_rx_mode(struct net_device *dev); 353 354/** 355 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. 356 * 357 * @bp: driver handle 358 * 359 * If bp->state is OPEN, should be called with 360 * netif_addr_lock_bh(). 361 */ 362void bnx2x_set_storm_rx_mode(struct bnx2x *bp); 363 364/** 365 * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. 366 * 367 * @bp: driver handle 368 * @cl_id: client id 369 * @rx_mode_flags: rx mode configuration 370 * @rx_accept_flags: rx accept configuration 371 * @tx_accept_flags: tx accept configuration (tx switch) 372 * @ramrod_flags: ramrod configuration 373 */ 374void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 375 unsigned long rx_mode_flags, 376 unsigned long rx_accept_flags, 377 unsigned long tx_accept_flags, 378 unsigned long ramrod_flags); 379 380/* Parity errors related */ 381void bnx2x_inc_load_cnt(struct bnx2x *bp); 382u32 bnx2x_dec_load_cnt(struct bnx2x *bp); 383bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); 384bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); 385void bnx2x_set_reset_in_progress(struct bnx2x *bp); 386void bnx2x_set_reset_global(struct bnx2x *bp); 387void bnx2x_disable_close_the_gate(struct bnx2x *bp); 388 389/** 390 * bnx2x_sp_event - handle ramrods completion. 391 * 392 * @fp: fastpath handle for the event 393 * @rr_cqe: eth_rx_cqe 394 */ 395void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); 396 397/** 398 * bnx2x_ilt_set_info - prepare ILT configurations. 399 * 400 * @bp: driver handle 401 */ 402void bnx2x_ilt_set_info(struct bnx2x *bp); 403 404/** 405 * bnx2x_dcbx_init - initialize dcbx protocol. 406 * 407 * @bp: driver handle 408 */ 409void bnx2x_dcbx_init(struct bnx2x *bp); 410 411/** 412 * bnx2x_set_power_state - set power state to the requested value. 413 * 414 * @bp: driver handle 415 * @state: required state D0 or D3hot 416 * 417 * Currently only D0 and D3hot are supported. 418 */ 419int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); 420 421/** 422 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. 423 * 424 * @bp: driver handle 425 * @value: new value 426 */ 427void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); 428/* Error handling */ 429void bnx2x_panic_dump(struct bnx2x *bp); 430 431void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); 432 433/* dev_close main block */ 434int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode); 435 436/* dev_open main block */ 437int bnx2x_nic_load(struct bnx2x *bp, int load_mode); 438 439/* hard_xmit callback */ 440netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); 441 442/* setup_tc callback */ 443int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); 444 445/* select_queue callback */ 446u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); 447 448/* reload helper */ 449int bnx2x_reload_if_running(struct net_device *dev); 450 451int bnx2x_change_mac_addr(struct net_device *dev, void *p); 452 453/* NAPI poll Rx part */ 454int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); 455 456void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 457 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod); 458 459/* NAPI poll Tx part */ 460int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); 461 462/* suspend/resume callbacks */ 463int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); 464int bnx2x_resume(struct pci_dev *pdev); 465 466/* Release IRQ vectors */ 467void bnx2x_free_irq(struct bnx2x *bp); 468 469void bnx2x_free_fp_mem(struct bnx2x *bp); 470int bnx2x_alloc_fp_mem(struct bnx2x *bp); 471void bnx2x_init_rx_rings(struct bnx2x *bp); 472void bnx2x_free_skbs(struct bnx2x *bp); 473void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); 474void bnx2x_netif_start(struct bnx2x *bp); 475 476/** 477 * bnx2x_enable_msix - set msix configuration. 478 * 479 * @bp: driver handle 480 * 481 * fills msix_table, requests vectors, updates num_queues 482 * according to number of available vectors. 483 */ 484int bnx2x_enable_msix(struct bnx2x *bp); 485 486/** 487 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly 488 * 489 * @bp: driver handle 490 */ 491int bnx2x_enable_msi(struct bnx2x *bp); 492 493/** 494 * bnx2x_poll - NAPI callback 495 * 496 * @napi: napi structure 497 * @budget: 498 * 499 */ 500int bnx2x_poll(struct napi_struct *napi, int budget); 501 502/** 503 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure 504 * 505 * @bp: driver handle 506 */ 507int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp); 508 509/** 510 * bnx2x_free_mem_bp - release memories outsize main driver structure 511 * 512 * @bp: driver handle 513 */ 514void bnx2x_free_mem_bp(struct bnx2x *bp); 515 516/** 517 * bnx2x_change_mtu - change mtu netdev callback 518 * 519 * @dev: net device 520 * @new_mtu: requested mtu 521 * 522 */ 523int bnx2x_change_mtu(struct net_device *dev, int new_mtu); 524 525#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 526/** 527 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port 528 * 529 * @dev: net_device 530 * @wwn: output buffer 531 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) 532 * 533 */ 534int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); 535#endif 536netdev_features_t bnx2x_fix_features(struct net_device *dev, 537 netdev_features_t features); 538int bnx2x_set_features(struct net_device *dev, netdev_features_t features); 539 540/** 541 * bnx2x_tx_timeout - tx timeout netdev callback 542 * 543 * @dev: net device 544 */ 545void bnx2x_tx_timeout(struct net_device *dev); 546 547/*********************** Inlines **********************************/ 548/*********************** Fast path ********************************/ 549static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 550{ 551 barrier(); /* status block is written to by the chip */ 552 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 553} 554 555static inline void bnx2x_update_rx_prod_gen(struct bnx2x *bp, 556 struct bnx2x_fastpath *fp, u16 bd_prod, 557 u16 rx_comp_prod, u16 rx_sge_prod, u32 start) 558{ 559 struct ustorm_eth_rx_producers rx_prods = {0}; 560 u32 i; 561 562 /* Update producers */ 563 rx_prods.bd_prod = bd_prod; 564 rx_prods.cqe_prod = rx_comp_prod; 565 rx_prods.sge_prod = rx_sge_prod; 566 567 /* 568 * Make sure that the BD and SGE data is updated before updating the 569 * producers since FW might read the BD/SGE right after the producer 570 * is updated. 571 * This is only applicable for weak-ordered memory model archs such 572 * as IA-64. The following barrier is also mandatory since FW will 573 * assumes BDs must have buffers. 574 */ 575 wmb(); 576 577 for (i = 0; i < sizeof(rx_prods)/4; i++) 578 REG_WR(bp, start + i*4, ((u32 *)&rx_prods)[i]); 579 580 mmiowb(); /* keep prod updates ordered */ 581 582 DP(NETIF_MSG_RX_STATUS, 583 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", 584 fp->index, bd_prod, rx_comp_prod, rx_sge_prod); 585} 586 587static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, 588 u8 segment, u16 index, u8 op, 589 u8 update, u32 igu_addr) 590{ 591 struct igu_regular cmd_data = {0}; 592 593 cmd_data.sb_id_and_flags = 594 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 595 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 596 (update << IGU_REGULAR_BUPDATE_SHIFT) | 597 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 598 599 DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n", 600 cmd_data.sb_id_and_flags, igu_addr); 601 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); 602 603 /* Make sure that ACK is written */ 604 mmiowb(); 605 barrier(); 606} 607 608static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, 609 u8 idu_sb_id, bool is_Pf) 610{ 611 u32 data, ctl, cnt = 100; 612 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 613 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 614 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; 615 u32 sb_bit = 1 << (idu_sb_id%32); 616 u32 func_encode = func | 617 ((is_Pf == true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT); 618 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; 619 620 /* Not supported in BC mode */ 621 if (CHIP_INT_MODE_IS_BC(bp)) 622 return; 623 624 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 625 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | 626 IGU_REGULAR_CLEANUP_SET | 627 IGU_REGULAR_BCLEANUP; 628 629 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | 630 func_encode << IGU_CTRL_REG_FID_SHIFT | 631 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; 632 633 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 634 data, igu_addr_data); 635 REG_WR(bp, igu_addr_data, data); 636 mmiowb(); 637 barrier(); 638 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 639 ctl, igu_addr_ctl); 640 REG_WR(bp, igu_addr_ctl, ctl); 641 mmiowb(); 642 barrier(); 643 644 /* wait for clean up to finish */ 645 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) 646 msleep(20); 647 648 649 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { 650 DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: " 651 "idu_sb_id %d offset %d bit %d (cnt %d)\n", 652 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); 653 } 654} 655 656static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, 657 u8 storm, u16 index, u8 op, u8 update) 658{ 659 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 660 COMMAND_REG_INT_ACK); 661 struct igu_ack_register igu_ack; 662 663 igu_ack.status_block_index = index; 664 igu_ack.sb_id_and_flags = 665 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 666 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 667 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 668 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 669 670 DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n", 671 (*(u32 *)&igu_ack), hc_addr); 672 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); 673 674 /* Make sure that ACK is written */ 675 mmiowb(); 676 barrier(); 677} 678 679static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, 680 u16 index, u8 op, u8 update) 681{ 682 if (bp->common.int_block == INT_BLOCK_HC) 683 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); 684 else { 685 u8 segment; 686 687 if (CHIP_INT_MODE_IS_BC(bp)) 688 segment = storm; 689 else if (igu_sb_id != bp->igu_dsb_id) 690 segment = IGU_SEG_ACCESS_DEF; 691 else if (storm == ATTENTION_ID) 692 segment = IGU_SEG_ACCESS_ATTN; 693 else 694 segment = IGU_SEG_ACCESS_DEF; 695 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); 696 } 697} 698 699static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) 700{ 701 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 702 COMMAND_REG_SIMD_MASK); 703 u32 result = REG_RD(bp, hc_addr); 704 705 DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n", 706 result, hc_addr); 707 708 barrier(); 709 return result; 710} 711 712static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) 713{ 714 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 715 u32 result = REG_RD(bp, igu_addr); 716 717 DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n", 718 result, igu_addr); 719 720 barrier(); 721 return result; 722} 723 724static inline u16 bnx2x_ack_int(struct bnx2x *bp) 725{ 726 barrier(); 727 if (bp->common.int_block == INT_BLOCK_HC) 728 return bnx2x_hc_ack_int(bp); 729 else 730 return bnx2x_igu_ack_int(bp); 731} 732 733static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) 734{ 735 /* Tell compiler that consumer and producer can change */ 736 barrier(); 737 return txdata->tx_pkt_prod != txdata->tx_pkt_cons; 738} 739 740static inline u16 bnx2x_tx_avail(struct bnx2x *bp, 741 struct bnx2x_fp_txdata *txdata) 742{ 743 s16 used; 744 u16 prod; 745 u16 cons; 746 747 prod = txdata->tx_bd_prod; 748 cons = txdata->tx_bd_cons; 749 750 /* NUM_TX_RINGS = number of "next-page" entries 751 It will be used as a threshold */ 752 used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS; 753 754#ifdef BNX2X_STOP_ON_ERROR 755 WARN_ON(used < 0); 756 WARN_ON(used > bp->tx_ring_size); 757 WARN_ON((bp->tx_ring_size - used) > MAX_TX_AVAIL); 758#endif 759 760 return (s16)(bp->tx_ring_size) - used; 761} 762 763static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) 764{ 765 u16 hw_cons; 766 767 /* Tell compiler that status block fields can change */ 768 barrier(); 769 hw_cons = le16_to_cpu(*txdata->tx_cons_sb); 770 return hw_cons != txdata->tx_pkt_cons; 771} 772 773static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) 774{ 775 u8 cos; 776 for_each_cos_in_tx_queue(fp, cos) 777 if (bnx2x_tx_queue_has_work(&fp->txdata[cos])) 778 return true; 779 return false; 780} 781 782static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) 783{ 784 u16 rx_cons_sb; 785 786 /* Tell compiler that status block fields can change */ 787 barrier(); 788 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); 789 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) 790 rx_cons_sb++; 791 return (fp->rx_comp_cons != rx_cons_sb); 792} 793 794/** 795 * bnx2x_tx_disable - disables tx from stack point of view 796 * 797 * @bp: driver handle 798 */ 799static inline void bnx2x_tx_disable(struct bnx2x *bp) 800{ 801 netif_tx_disable(bp->dev); 802 netif_carrier_off(bp->dev); 803} 804 805static inline void bnx2x_free_rx_sge(struct bnx2x *bp, 806 struct bnx2x_fastpath *fp, u16 index) 807{ 808 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; 809 struct page *page = sw_buf->page; 810 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; 811 812 /* Skip "next page" elements */ 813 if (!page) 814 return; 815 816 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), 817 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); 818 __free_pages(page, PAGES_PER_SGE_SHIFT); 819 820 sw_buf->page = NULL; 821 sge->addr_hi = 0; 822 sge->addr_lo = 0; 823} 824 825static inline void bnx2x_add_all_napi(struct bnx2x *bp) 826{ 827 int i; 828 829 /* Add NAPI objects */ 830 for_each_rx_queue(bp, i) 831 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 832 bnx2x_poll, BNX2X_NAPI_WEIGHT); 833} 834 835static inline void bnx2x_del_all_napi(struct bnx2x *bp) 836{ 837 int i; 838 839 for_each_rx_queue(bp, i) 840 netif_napi_del(&bnx2x_fp(bp, i, napi)); 841} 842 843static inline void bnx2x_disable_msi(struct bnx2x *bp) 844{ 845 if (bp->flags & USING_MSIX_FLAG) { 846 pci_disable_msix(bp->pdev); 847 bp->flags &= ~USING_MSIX_FLAG; 848 } else if (bp->flags & USING_MSI_FLAG) { 849 pci_disable_msi(bp->pdev); 850 bp->flags &= ~USING_MSI_FLAG; 851 } 852} 853 854static inline int bnx2x_calc_num_queues(struct bnx2x *bp) 855{ 856 return num_queues ? 857 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : 858 min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp)); 859} 860 861static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) 862{ 863 int i, j; 864 865 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { 866 int idx = RX_SGE_CNT * i - 1; 867 868 for (j = 0; j < 2; j++) { 869 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); 870 idx--; 871 } 872 } 873} 874 875static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) 876{ 877 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ 878 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); 879 880 /* Clear the two last indices in the page to 1: 881 these are the indices that correspond to the "next" element, 882 hence will never be indicated and should be removed from 883 the calculations. */ 884 bnx2x_clear_sge_mask_next_elems(fp); 885} 886 887static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp, 888 struct bnx2x_fastpath *fp, u16 index) 889{ 890 struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT); 891 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; 892 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; 893 dma_addr_t mapping; 894 895 if (unlikely(page == NULL)) 896 return -ENOMEM; 897 898 mapping = dma_map_page(&bp->pdev->dev, page, 0, 899 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); 900 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 901 __free_pages(page, PAGES_PER_SGE_SHIFT); 902 return -ENOMEM; 903 } 904 905 sw_buf->page = page; 906 dma_unmap_addr_set(sw_buf, mapping, mapping); 907 908 sge->addr_hi = cpu_to_le32(U64_HI(mapping)); 909 sge->addr_lo = cpu_to_le32(U64_LO(mapping)); 910 911 return 0; 912} 913 914static inline int bnx2x_alloc_rx_data(struct bnx2x *bp, 915 struct bnx2x_fastpath *fp, u16 index) 916{ 917 u8 *data; 918 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index]; 919 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index]; 920 dma_addr_t mapping; 921 922 data = kmalloc(fp->rx_buf_size + NET_SKB_PAD, GFP_ATOMIC); 923 if (unlikely(data == NULL)) 924 return -ENOMEM; 925 926 mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD, 927 fp->rx_buf_size, 928 DMA_FROM_DEVICE); 929 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 930 kfree(data); 931 return -ENOMEM; 932 } 933 934 rx_buf->data = data; 935 dma_unmap_addr_set(rx_buf, mapping, mapping); 936 937 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 938 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 939 940 return 0; 941} 942 943/* note that we are not allocating a new buffer, 944 * we are just moving one from cons to prod 945 * we are not creating a new mapping, 946 * so there is no need to check for dma_mapping_error(). 947 */ 948static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, 949 u16 cons, u16 prod) 950{ 951 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; 952 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; 953 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; 954 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; 955 956 dma_unmap_addr_set(prod_rx_buf, mapping, 957 dma_unmap_addr(cons_rx_buf, mapping)); 958 prod_rx_buf->data = cons_rx_buf->data; 959 *prod_bd = *cons_bd; 960} 961 962/************************* Init ******************************************/ 963 964/** 965 * bnx2x_func_start - init function 966 * 967 * @bp: driver handle 968 * 969 * Must be called before sending CLIENT_SETUP for the first client. 970 */ 971static inline int bnx2x_func_start(struct bnx2x *bp) 972{ 973 struct bnx2x_func_state_params func_params = {0}; 974 struct bnx2x_func_start_params *start_params = 975 &func_params.params.start; 976 977 /* Prepare parameters for function state transitions */ 978 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 979 980 func_params.f_obj = &bp->func_obj; 981 func_params.cmd = BNX2X_F_CMD_START; 982 983 /* Function parameters */ 984 start_params->mf_mode = bp->mf_mode; 985 start_params->sd_vlan_tag = bp->mf_ov; 986 if (CHIP_IS_E1x(bp)) 987 start_params->network_cos_mode = OVERRIDE_COS; 988 else 989 start_params->network_cos_mode = STATIC_COS; 990 991 return bnx2x_func_state_change(bp, &func_params); 992} 993 994 995/** 996 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format 997 * 998 * @fw_hi: pointer to upper part 999 * @fw_mid: pointer to middle part 1000 * @fw_lo: pointer to lower part 1001 * @mac: pointer to MAC address 1002 */ 1003static inline void bnx2x_set_fw_mac_addr(u16 *fw_hi, u16 *fw_mid, u16 *fw_lo, 1004 u8 *mac) 1005{ 1006 ((u8 *)fw_hi)[0] = mac[1]; 1007 ((u8 *)fw_hi)[1] = mac[0]; 1008 ((u8 *)fw_mid)[0] = mac[3]; 1009 ((u8 *)fw_mid)[1] = mac[2]; 1010 ((u8 *)fw_lo)[0] = mac[5]; 1011 ((u8 *)fw_lo)[1] = mac[4]; 1012} 1013 1014static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, 1015 struct bnx2x_fastpath *fp, int last) 1016{ 1017 int i; 1018 1019 if (fp->disable_tpa) 1020 return; 1021 1022 for (i = 0; i < last; i++) 1023 bnx2x_free_rx_sge(bp, fp, i); 1024} 1025 1026static inline void bnx2x_free_tpa_pool(struct bnx2x *bp, 1027 struct bnx2x_fastpath *fp, int last) 1028{ 1029 int i; 1030 1031 for (i = 0; i < last; i++) { 1032 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i]; 1033 struct sw_rx_bd *first_buf = &tpa_info->first_buf; 1034 u8 *data = first_buf->data; 1035 1036 if (data == NULL) { 1037 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i); 1038 continue; 1039 } 1040 if (tpa_info->tpa_state == BNX2X_TPA_START) 1041 dma_unmap_single(&bp->pdev->dev, 1042 dma_unmap_addr(first_buf, mapping), 1043 fp->rx_buf_size, DMA_FROM_DEVICE); 1044 kfree(data); 1045 first_buf->data = NULL; 1046 } 1047} 1048 1049static inline void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) 1050{ 1051 int i; 1052 1053 for (i = 1; i <= NUM_TX_RINGS; i++) { 1054 struct eth_tx_next_bd *tx_next_bd = 1055 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; 1056 1057 tx_next_bd->addr_hi = 1058 cpu_to_le32(U64_HI(txdata->tx_desc_mapping + 1059 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 1060 tx_next_bd->addr_lo = 1061 cpu_to_le32(U64_LO(txdata->tx_desc_mapping + 1062 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 1063 } 1064 1065 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); 1066 txdata->tx_db.data.zero_fill1 = 0; 1067 txdata->tx_db.data.prod = 0; 1068 1069 txdata->tx_pkt_prod = 0; 1070 txdata->tx_pkt_cons = 0; 1071 txdata->tx_bd_prod = 0; 1072 txdata->tx_bd_cons = 0; 1073 txdata->tx_pkt = 0; 1074} 1075 1076static inline void bnx2x_init_tx_rings(struct bnx2x *bp) 1077{ 1078 int i; 1079 u8 cos; 1080 1081 for_each_tx_queue(bp, i) 1082 for_each_cos_in_tx_queue(&bp->fp[i], cos) 1083 bnx2x_init_tx_ring_one(&bp->fp[i].txdata[cos]); 1084} 1085 1086static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) 1087{ 1088 int i; 1089 1090 for (i = 1; i <= NUM_RX_RINGS; i++) { 1091 struct eth_rx_bd *rx_bd; 1092 1093 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; 1094 rx_bd->addr_hi = 1095 cpu_to_le32(U64_HI(fp->rx_desc_mapping + 1096 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 1097 rx_bd->addr_lo = 1098 cpu_to_le32(U64_LO(fp->rx_desc_mapping + 1099 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 1100 } 1101} 1102 1103static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp) 1104{ 1105 int i; 1106 1107 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { 1108 struct eth_rx_sge *sge; 1109 1110 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2]; 1111 sge->addr_hi = 1112 cpu_to_le32(U64_HI(fp->rx_sge_mapping + 1113 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES))); 1114 1115 sge->addr_lo = 1116 cpu_to_le32(U64_LO(fp->rx_sge_mapping + 1117 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES))); 1118 } 1119} 1120 1121static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp) 1122{ 1123 int i; 1124 for (i = 1; i <= NUM_RCQ_RINGS; i++) { 1125 struct eth_rx_cqe_next_page *nextpg; 1126 1127 nextpg = (struct eth_rx_cqe_next_page *) 1128 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1]; 1129 nextpg->addr_hi = 1130 cpu_to_le32(U64_HI(fp->rx_comp_mapping + 1131 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); 1132 nextpg->addr_lo = 1133 cpu_to_le32(U64_LO(fp->rx_comp_mapping + 1134 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); 1135 } 1136} 1137 1138/* Returns the number of actually allocated BDs */ 1139static inline int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp, 1140 int rx_ring_size) 1141{ 1142 struct bnx2x *bp = fp->bp; 1143 u16 ring_prod, cqe_ring_prod; 1144 int i; 1145 1146 fp->rx_comp_cons = 0; 1147 cqe_ring_prod = ring_prod = 0; 1148 1149 /* This routine is called only during fo init so 1150 * fp->eth_q_stats.rx_skb_alloc_failed = 0 1151 */ 1152 for (i = 0; i < rx_ring_size; i++) { 1153 if (bnx2x_alloc_rx_data(bp, fp, ring_prod) < 0) { 1154 fp->eth_q_stats.rx_skb_alloc_failed++; 1155 continue; 1156 } 1157 ring_prod = NEXT_RX_IDX(ring_prod); 1158 cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod); 1159 WARN_ON(ring_prod <= (i - fp->eth_q_stats.rx_skb_alloc_failed)); 1160 } 1161 1162 if (fp->eth_q_stats.rx_skb_alloc_failed) 1163 BNX2X_ERR("was only able to allocate " 1164 "%d rx skbs on queue[%d]\n", 1165 (i - fp->eth_q_stats.rx_skb_alloc_failed), fp->index); 1166 1167 fp->rx_bd_prod = ring_prod; 1168 /* Limit the CQE producer by the CQE ring size */ 1169 fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT, 1170 cqe_ring_prod); 1171 fp->rx_pkt = fp->rx_calls = 0; 1172 1173 return i - fp->eth_q_stats.rx_skb_alloc_failed; 1174} 1175 1176/* Statistics ID are global per chip/path, while Client IDs for E1x are per 1177 * port. 1178 */ 1179static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) 1180{ 1181 if (!CHIP_IS_E1x(fp->bp)) 1182 return fp->cl_id; 1183 else 1184 return fp->cl_id + BP_PORT(fp->bp) * FP_SB_MAX_E1x; 1185} 1186 1187static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, 1188 bnx2x_obj_type obj_type) 1189{ 1190 struct bnx2x *bp = fp->bp; 1191 1192 /* Configure classification DBs */ 1193 bnx2x_init_mac_obj(bp, &fp->mac_obj, fp->cl_id, fp->cid, 1194 BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), 1195 bnx2x_sp_mapping(bp, mac_rdata), 1196 BNX2X_FILTER_MAC_PENDING, 1197 &bp->sp_state, obj_type, 1198 &bp->macs_pool); 1199} 1200 1201/** 1202 * bnx2x_get_path_func_num - get number of active functions 1203 * 1204 * @bp: driver handle 1205 * 1206 * Calculates the number of active (not hidden) functions on the 1207 * current path. 1208 */ 1209static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) 1210{ 1211 u8 func_num = 0, i; 1212 1213 /* 57710 has only one function per-port */ 1214 if (CHIP_IS_E1(bp)) 1215 return 1; 1216 1217 /* Calculate a number of functions enabled on the current 1218 * PATH/PORT. 1219 */ 1220 if (CHIP_REV_IS_SLOW(bp)) { 1221 if (IS_MF(bp)) 1222 func_num = 4; 1223 else 1224 func_num = 2; 1225 } else { 1226 for (i = 0; i < E1H_FUNC_MAX / 2; i++) { 1227 u32 func_config = 1228 MF_CFG_RD(bp, 1229 func_mf_config[BP_PORT(bp) + 2 * i]. 1230 config); 1231 func_num += 1232 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); 1233 } 1234 } 1235 1236 WARN_ON(!func_num); 1237 1238 return func_num; 1239} 1240 1241static inline void bnx2x_init_bp_objs(struct bnx2x *bp) 1242{ 1243 /* RX_MODE controlling object */ 1244 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); 1245 1246 /* multicast configuration controlling object */ 1247 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, 1248 BP_FUNC(bp), BP_FUNC(bp), 1249 bnx2x_sp(bp, mcast_rdata), 1250 bnx2x_sp_mapping(bp, mcast_rdata), 1251 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, 1252 BNX2X_OBJ_TYPE_RX); 1253 1254 /* Setup CAM credit pools */ 1255 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), 1256 bnx2x_get_path_func_num(bp)); 1257 1258 /* RSS configuration object */ 1259 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, 1260 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), 1261 bnx2x_sp(bp, rss_rdata), 1262 bnx2x_sp_mapping(bp, rss_rdata), 1263 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, 1264 BNX2X_OBJ_TYPE_RX); 1265} 1266 1267static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) 1268{ 1269 if (CHIP_IS_E1x(fp->bp)) 1270 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; 1271 else 1272 return fp->cl_id; 1273} 1274 1275static inline u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) 1276{ 1277 struct bnx2x *bp = fp->bp; 1278 1279 if (!CHIP_IS_E1x(bp)) 1280 return USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); 1281 else 1282 return USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); 1283} 1284 1285static inline void bnx2x_init_txdata(struct bnx2x *bp, 1286 struct bnx2x_fp_txdata *txdata, u32 cid, int txq_index, 1287 __le16 *tx_cons_sb) 1288{ 1289 txdata->cid = cid; 1290 txdata->txq_index = txq_index; 1291 txdata->tx_cons_sb = tx_cons_sb; 1292 1293 DP(BNX2X_MSG_SP, "created tx data cid %d, txq %d\n", 1294 txdata->cid, txdata->txq_index); 1295} 1296 1297#ifdef BCM_CNIC 1298static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) 1299{ 1300 return bp->cnic_base_cl_id + cl_idx + 1301 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; 1302} 1303 1304static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) 1305{ 1306 1307 /* the 'first' id is allocated for the cnic */ 1308 return bp->base_fw_ndsb; 1309} 1310 1311static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) 1312{ 1313 return bp->igu_base_sb; 1314} 1315 1316 1317static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) 1318{ 1319 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 1320 unsigned long q_type = 0; 1321 1322 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); 1323 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, 1324 BNX2X_FCOE_ETH_CL_ID_IDX); 1325 /** Current BNX2X_FCOE_ETH_CID deffinition implies not more than 1326 * 16 ETH clients per function when CNIC is enabled! 1327 * 1328 * Fix it ASAP!!! 1329 */ 1330 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID; 1331 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; 1332 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; 1333 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; 1334 1335 bnx2x_init_txdata(bp, &bnx2x_fcoe(bp, txdata[0]), 1336 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX); 1337 1338 DP(BNX2X_MSG_SP, "created fcoe tx data (fp index %d)\n", fp->index); 1339 1340 /* qZone id equals to FW (per path) client id */ 1341 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); 1342 /* init shortcut */ 1343 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = 1344 bnx2x_rx_ustorm_prods_offset(fp); 1345 1346 /* Configure Queue State object */ 1347 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1348 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1349 1350 /* No multi-CoS for FCoE L2 client */ 1351 BUG_ON(fp->max_cos != 1); 1352 1353 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, &fp->cid, 1, 1354 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 1355 bnx2x_sp_mapping(bp, q_rdata), q_type); 1356 1357 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d " 1358 "igu_sb %d\n", 1359 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 1360 fp->igu_sb_id); 1361} 1362#endif 1363 1364static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, 1365 struct bnx2x_fp_txdata *txdata) 1366{ 1367 int cnt = 1000; 1368 1369 while (bnx2x_has_tx_work_unload(txdata)) { 1370 if (!cnt) { 1371 BNX2X_ERR("timeout waiting for queue[%d]: " 1372 "txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", 1373 txdata->txq_index, txdata->tx_pkt_prod, 1374 txdata->tx_pkt_cons); 1375#ifdef BNX2X_STOP_ON_ERROR 1376 bnx2x_panic(); 1377 return -EBUSY; 1378#else 1379 break; 1380#endif 1381 } 1382 cnt--; 1383 usleep_range(1000, 1000); 1384 } 1385 1386 return 0; 1387} 1388 1389int bnx2x_get_link_cfg_idx(struct bnx2x *bp); 1390 1391static inline void __storm_memset_struct(struct bnx2x *bp, 1392 u32 addr, size_t size, u32 *data) 1393{ 1394 int i; 1395 for (i = 0; i < size/4; i++) 1396 REG_WR(bp, addr + (i * 4), data[i]); 1397} 1398 1399static inline void storm_memset_func_cfg(struct bnx2x *bp, 1400 struct tstorm_eth_function_common_config *tcfg, 1401 u16 abs_fid) 1402{ 1403 size_t size = sizeof(struct tstorm_eth_function_common_config); 1404 1405 u32 addr = BAR_TSTRORM_INTMEM + 1406 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); 1407 1408 __storm_memset_struct(bp, addr, size, (u32 *)tcfg); 1409} 1410 1411static inline void storm_memset_cmng(struct bnx2x *bp, 1412 struct cmng_struct_per_port *cmng, 1413 u8 port) 1414{ 1415 size_t size = sizeof(struct cmng_struct_per_port); 1416 1417 u32 addr = BAR_XSTRORM_INTMEM + 1418 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); 1419 1420 __storm_memset_struct(bp, addr, size, (u32 *)cmng); 1421} 1422 1423/** 1424 * bnx2x_wait_sp_comp - wait for the outstanding SP commands. 1425 * 1426 * @bp: driver handle 1427 * @mask: bits that need to be cleared 1428 */ 1429static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) 1430{ 1431 int tout = 5000; /* Wait for 5 secs tops */ 1432 1433 while (tout--) { 1434 smp_mb(); 1435 netif_addr_lock_bh(bp->dev); 1436 if (!(bp->sp_state & mask)) { 1437 netif_addr_unlock_bh(bp->dev); 1438 return true; 1439 } 1440 netif_addr_unlock_bh(bp->dev); 1441 1442 usleep_range(1000, 1000); 1443 } 1444 1445 smp_mb(); 1446 1447 netif_addr_lock_bh(bp->dev); 1448 if (bp->sp_state & mask) { 1449 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, " 1450 "mask 0x%lx\n", bp->sp_state, mask); 1451 netif_addr_unlock_bh(bp->dev); 1452 return false; 1453 } 1454 netif_addr_unlock_bh(bp->dev); 1455 1456 return true; 1457} 1458 1459/** 1460 * bnx2x_set_ctx_validation - set CDU context validation values 1461 * 1462 * @bp: driver handle 1463 * @cxt: context of the connection on the host memory 1464 * @cid: SW CID of the connection to be configured 1465 */ 1466void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, 1467 u32 cid); 1468 1469void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, 1470 u8 sb_index, u8 disable, u16 usec); 1471void bnx2x_acquire_phy_lock(struct bnx2x *bp); 1472void bnx2x_release_phy_lock(struct bnx2x *bp); 1473 1474/** 1475 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. 1476 * 1477 * @bp: driver handle 1478 * @mf_cfg: MF configuration 1479 * 1480 */ 1481static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) 1482{ 1483 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 1484 FUNC_MF_CFG_MAX_BW_SHIFT; 1485 if (!max_cfg) { 1486 DP(NETIF_MSG_LINK, 1487 "Max BW configured to 0 - using 100 instead\n"); 1488 max_cfg = 100; 1489 } 1490 return max_cfg; 1491} 1492 1493#ifdef BCM_CNIC 1494/** 1495 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. 1496 * 1497 * @bp: driver handle 1498 * 1499 */ 1500void bnx2x_get_iscsi_info(struct bnx2x *bp); 1501#endif 1502 1503/* returns func by VN for current port */ 1504static inline int func_by_vn(struct bnx2x *bp, int vn) 1505{ 1506 return 2 * vn + BP_PORT(bp); 1507} 1508 1509/** 1510 * bnx2x_link_sync_notify - send notification to other functions. 1511 * 1512 * @bp: driver handle 1513 * 1514 */ 1515static inline void bnx2x_link_sync_notify(struct bnx2x *bp) 1516{ 1517 int func; 1518 int vn; 1519 1520 /* Set the attention towards other drivers on the same port */ 1521 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 1522 if (vn == BP_VN(bp)) 1523 continue; 1524 1525 func = func_by_vn(bp, vn); 1526 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + 1527 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); 1528 } 1529} 1530 1531/** 1532 * bnx2x_update_drv_flags - update flags in shmem 1533 * 1534 * @bp: driver handle 1535 * @flags: flags to update 1536 * @set: set or clear 1537 * 1538 */ 1539static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) 1540{ 1541 if (SHMEM2_HAS(bp, drv_flags)) { 1542 u32 drv_flags; 1543 bnx2x_acquire_hw_lock(bp, HW_LOCK_DRV_FLAGS); 1544 drv_flags = SHMEM2_RD(bp, drv_flags); 1545 1546 if (set) 1547 SET_FLAGS(drv_flags, flags); 1548 else 1549 RESET_FLAGS(drv_flags, flags); 1550 1551 SHMEM2_WR(bp, drv_flags, drv_flags); 1552 DP(NETIF_MSG_HW, "drv_flags 0x%08x\n", drv_flags); 1553 bnx2x_release_hw_lock(bp, HW_LOCK_DRV_FLAGS); 1554 } 1555} 1556 1557#endif /* BNX2X_CMN_H */ 1558