bnx2x_cmn.h revision de5c37414af10ac9305d4a3e9c1468347ca3ccaa
1/* bnx2x_cmn.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2007-2011 Broadcom Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation. 8 * 9 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 10 * Written by: Eliezer Tamir 11 * Based on code from Michael Chan's bnx2 driver 12 * UDP CSUM errata workaround by Arik Gendelman 13 * Slowpath and fastpath rework by Vladislav Zolotarov 14 * Statistics and Link management by Yitchak Gertner 15 * 16 */ 17#ifndef BNX2X_CMN_H 18#define BNX2X_CMN_H 19 20#include <linux/types.h> 21#include <linux/pci.h> 22#include <linux/netdevice.h> 23#include <linux/etherdevice.h> 24 25 26#include "bnx2x.h" 27 28/* This is used as a replacement for an MCP if it's not present */ 29extern int load_count[2][3]; /* per-path: 0-common, 1-port0, 2-port1 */ 30 31extern int num_queues; 32 33/************************ Macros ********************************/ 34#define BNX2X_PCI_FREE(x, y, size) \ 35 do { \ 36 if (x) { \ 37 dma_free_coherent(&bp->pdev->dev, size, (void *)x, y); \ 38 x = NULL; \ 39 y = 0; \ 40 } \ 41 } while (0) 42 43#define BNX2X_FREE(x) \ 44 do { \ 45 if (x) { \ 46 kfree((void *)x); \ 47 x = NULL; \ 48 } \ 49 } while (0) 50 51#define BNX2X_PCI_ALLOC(x, y, size) \ 52 do { \ 53 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \ 54 if (x == NULL) \ 55 goto alloc_mem_err; \ 56 memset((void *)x, 0, size); \ 57 } while (0) 58 59#define BNX2X_ALLOC(x, size) \ 60 do { \ 61 x = kzalloc(size, GFP_KERNEL); \ 62 if (x == NULL) \ 63 goto alloc_mem_err; \ 64 } while (0) 65 66/*********************** Interfaces **************************** 67 * Functions that need to be implemented by each driver version 68 */ 69/* Init */ 70 71/** 72 * bnx2x_send_unload_req - request unload mode from the MCP. 73 * 74 * @bp: driver handle 75 * @unload_mode: requested function's unload mode 76 * 77 * Return unload mode returned by the MCP: COMMON, PORT or FUNC. 78 */ 79u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode); 80 81/** 82 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP. 83 * 84 * @bp: driver handle 85 */ 86void bnx2x_send_unload_done(struct bnx2x *bp); 87 88/** 89 * bnx2x_config_rss_pf - configure RSS parameters. 90 * 91 * @bp: driver handle 92 * @ind_table: indirection table to configure 93 * @config_hash: re-configure RSS hash keys configuration 94 */ 95int bnx2x_config_rss_pf(struct bnx2x *bp, u8 *ind_table, bool config_hash); 96 97/** 98 * bnx2x__init_func_obj - init function object 99 * 100 * @bp: driver handle 101 * 102 * Initializes the Function Object with the appropriate 103 * parameters which include a function slow path driver 104 * interface. 105 */ 106void bnx2x__init_func_obj(struct bnx2x *bp); 107 108/** 109 * bnx2x_setup_queue - setup eth queue. 110 * 111 * @bp: driver handle 112 * @fp: pointer to the fastpath structure 113 * @leading: boolean 114 * 115 */ 116int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp, 117 bool leading); 118 119/** 120 * bnx2x_setup_leading - bring up a leading eth queue. 121 * 122 * @bp: driver handle 123 */ 124int bnx2x_setup_leading(struct bnx2x *bp); 125 126/** 127 * bnx2x_fw_command - send the MCP a request 128 * 129 * @bp: driver handle 130 * @command: request 131 * @param: request's parameter 132 * 133 * block until there is a reply 134 */ 135u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param); 136 137/** 138 * bnx2x_initial_phy_init - initialize link parameters structure variables. 139 * 140 * @bp: driver handle 141 * @load_mode: current mode 142 */ 143u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode); 144 145/** 146 * bnx2x_link_set - configure hw according to link parameters structure. 147 * 148 * @bp: driver handle 149 */ 150void bnx2x_link_set(struct bnx2x *bp); 151 152/** 153 * bnx2x_link_test - query link status. 154 * 155 * @bp: driver handle 156 * @is_serdes: bool 157 * 158 * Returns 0 if link is UP. 159 */ 160u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes); 161 162/** 163 * bnx2x_drv_pulse - write driver pulse to shmem 164 * 165 * @bp: driver handle 166 * 167 * writes the value in bp->fw_drv_pulse_wr_seq to drv_pulse mbox 168 * in the shmem. 169 */ 170void bnx2x_drv_pulse(struct bnx2x *bp); 171 172/** 173 * bnx2x_igu_ack_sb - update IGU with current SB value 174 * 175 * @bp: driver handle 176 * @igu_sb_id: SB id 177 * @segment: SB segment 178 * @index: SB index 179 * @op: SB operation 180 * @update: is HW update required 181 */ 182void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment, 183 u16 index, u8 op, u8 update); 184 185/* Disable transactions from chip to host */ 186void bnx2x_pf_disable(struct bnx2x *bp); 187 188/** 189 * bnx2x__link_status_update - handles link status change. 190 * 191 * @bp: driver handle 192 */ 193void bnx2x__link_status_update(struct bnx2x *bp); 194 195/** 196 * bnx2x_link_report - report link status to upper layer. 197 * 198 * @bp: driver handle 199 */ 200void bnx2x_link_report(struct bnx2x *bp); 201 202/* None-atomic version of bnx2x_link_report() */ 203void __bnx2x_link_report(struct bnx2x *bp); 204 205/** 206 * bnx2x_get_mf_speed - calculate MF speed. 207 * 208 * @bp: driver handle 209 * 210 * Takes into account current linespeed and MF configuration. 211 */ 212u16 bnx2x_get_mf_speed(struct bnx2x *bp); 213 214/** 215 * bnx2x_msix_sp_int - MSI-X slowpath interrupt handler 216 * 217 * @irq: irq number 218 * @dev_instance: private instance 219 */ 220irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance); 221 222/** 223 * bnx2x_interrupt - non MSI-X interrupt handler 224 * 225 * @irq: irq number 226 * @dev_instance: private instance 227 */ 228irqreturn_t bnx2x_interrupt(int irq, void *dev_instance); 229#ifdef BCM_CNIC 230 231/** 232 * bnx2x_cnic_notify - send command to cnic driver 233 * 234 * @bp: driver handle 235 * @cmd: command 236 */ 237int bnx2x_cnic_notify(struct bnx2x *bp, int cmd); 238 239/** 240 * bnx2x_setup_cnic_irq_info - provides cnic with IRQ information 241 * 242 * @bp: driver handle 243 */ 244void bnx2x_setup_cnic_irq_info(struct bnx2x *bp); 245#endif 246 247/** 248 * bnx2x_int_enable - enable HW interrupts. 249 * 250 * @bp: driver handle 251 */ 252void bnx2x_int_enable(struct bnx2x *bp); 253 254/** 255 * bnx2x_int_disable_sync - disable interrupts. 256 * 257 * @bp: driver handle 258 * @disable_hw: true, disable HW interrupts. 259 * 260 * This function ensures that there are no 261 * ISRs or SP DPCs (sp_task) are running after it returns. 262 */ 263void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw); 264 265/** 266 * bnx2x_nic_init - init driver internals. 267 * 268 * @bp: driver handle 269 * @load_code: COMMON, PORT or FUNCTION 270 * 271 * Initializes: 272 * - rings 273 * - status blocks 274 * - etc. 275 */ 276void bnx2x_nic_init(struct bnx2x *bp, u32 load_code); 277 278/** 279 * bnx2x_alloc_mem - allocate driver's memory. 280 * 281 * @bp: driver handle 282 */ 283int bnx2x_alloc_mem(struct bnx2x *bp); 284 285/** 286 * bnx2x_free_mem - release driver's memory. 287 * 288 * @bp: driver handle 289 */ 290void bnx2x_free_mem(struct bnx2x *bp); 291 292/** 293 * bnx2x_set_num_queues - set number of queues according to mode. 294 * 295 * @bp: driver handle 296 */ 297void bnx2x_set_num_queues(struct bnx2x *bp); 298 299/** 300 * bnx2x_chip_cleanup - cleanup chip internals. 301 * 302 * @bp: driver handle 303 * @unload_mode: COMMON, PORT, FUNCTION 304 * 305 * - Cleanup MAC configuration. 306 * - Closes clients. 307 * - etc. 308 */ 309void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode); 310 311/** 312 * bnx2x_acquire_hw_lock - acquire HW lock. 313 * 314 * @bp: driver handle 315 * @resource: resource bit which was locked 316 */ 317int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource); 318 319/** 320 * bnx2x_release_hw_lock - release HW lock. 321 * 322 * @bp: driver handle 323 * @resource: resource bit which was locked 324 */ 325int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource); 326 327/** 328 * bnx2x_release_leader_lock - release recovery leader lock 329 * 330 * @bp: driver handle 331 */ 332int bnx2x_release_leader_lock(struct bnx2x *bp); 333 334/** 335 * bnx2x_set_eth_mac - configure eth MAC address in the HW 336 * 337 * @bp: driver handle 338 * @set: set or clear 339 * 340 * Configures according to the value in netdev->dev_addr. 341 */ 342int bnx2x_set_eth_mac(struct bnx2x *bp, bool set); 343 344/** 345 * bnx2x_set_rx_mode - set MAC filtering configurations. 346 * 347 * @dev: netdevice 348 * 349 * called with netif_tx_lock from dev_mcast.c 350 * If bp->state is OPEN, should be called with 351 * netif_addr_lock_bh() 352 */ 353void bnx2x_set_rx_mode(struct net_device *dev); 354 355/** 356 * bnx2x_set_storm_rx_mode - configure MAC filtering rules in a FW. 357 * 358 * @bp: driver handle 359 * 360 * If bp->state is OPEN, should be called with 361 * netif_addr_lock_bh(). 362 */ 363void bnx2x_set_storm_rx_mode(struct bnx2x *bp); 364 365/** 366 * bnx2x_set_q_rx_mode - configures rx_mode for a single queue. 367 * 368 * @bp: driver handle 369 * @cl_id: client id 370 * @rx_mode_flags: rx mode configuration 371 * @rx_accept_flags: rx accept configuration 372 * @tx_accept_flags: tx accept configuration (tx switch) 373 * @ramrod_flags: ramrod configuration 374 */ 375void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id, 376 unsigned long rx_mode_flags, 377 unsigned long rx_accept_flags, 378 unsigned long tx_accept_flags, 379 unsigned long ramrod_flags); 380 381/* Parity errors related */ 382void bnx2x_inc_load_cnt(struct bnx2x *bp); 383u32 bnx2x_dec_load_cnt(struct bnx2x *bp); 384bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print); 385bool bnx2x_reset_is_done(struct bnx2x *bp, int engine); 386void bnx2x_set_reset_in_progress(struct bnx2x *bp); 387void bnx2x_set_reset_global(struct bnx2x *bp); 388void bnx2x_disable_close_the_gate(struct bnx2x *bp); 389 390/** 391 * bnx2x_sp_event - handle ramrods completion. 392 * 393 * @fp: fastpath handle for the event 394 * @rr_cqe: eth_rx_cqe 395 */ 396void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe); 397 398/** 399 * bnx2x_ilt_set_info - prepare ILT configurations. 400 * 401 * @bp: driver handle 402 */ 403void bnx2x_ilt_set_info(struct bnx2x *bp); 404 405/** 406 * bnx2x_dcbx_init - initialize dcbx protocol. 407 * 408 * @bp: driver handle 409 */ 410void bnx2x_dcbx_init(struct bnx2x *bp); 411 412/** 413 * bnx2x_set_power_state - set power state to the requested value. 414 * 415 * @bp: driver handle 416 * @state: required state D0 or D3hot 417 * 418 * Currently only D0 and D3hot are supported. 419 */ 420int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state); 421 422/** 423 * bnx2x_update_max_mf_config - update MAX part of MF configuration in HW. 424 * 425 * @bp: driver handle 426 * @value: new value 427 */ 428void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value); 429/* Error handling */ 430void bnx2x_panic_dump(struct bnx2x *bp); 431 432void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl); 433 434/* dev_close main block */ 435int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode); 436 437/* dev_open main block */ 438int bnx2x_nic_load(struct bnx2x *bp, int load_mode); 439 440/* hard_xmit callback */ 441netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev); 442 443/* setup_tc callback */ 444int bnx2x_setup_tc(struct net_device *dev, u8 num_tc); 445 446/* select_queue callback */ 447u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb); 448 449/* reload helper */ 450int bnx2x_reload_if_running(struct net_device *dev); 451 452int bnx2x_change_mac_addr(struct net_device *dev, void *p); 453 454/* NAPI poll Rx part */ 455int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget); 456 457void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp, 458 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod); 459 460/* NAPI poll Tx part */ 461int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata); 462 463/* suspend/resume callbacks */ 464int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state); 465int bnx2x_resume(struct pci_dev *pdev); 466 467/* Release IRQ vectors */ 468void bnx2x_free_irq(struct bnx2x *bp); 469 470void bnx2x_free_fp_mem(struct bnx2x *bp); 471int bnx2x_alloc_fp_mem(struct bnx2x *bp); 472void bnx2x_init_rx_rings(struct bnx2x *bp); 473void bnx2x_free_skbs(struct bnx2x *bp); 474void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw); 475void bnx2x_netif_start(struct bnx2x *bp); 476 477/** 478 * bnx2x_enable_msix - set msix configuration. 479 * 480 * @bp: driver handle 481 * 482 * fills msix_table, requests vectors, updates num_queues 483 * according to number of available vectors. 484 */ 485int bnx2x_enable_msix(struct bnx2x *bp); 486 487/** 488 * bnx2x_enable_msi - request msi mode from OS, updated internals accordingly 489 * 490 * @bp: driver handle 491 */ 492int bnx2x_enable_msi(struct bnx2x *bp); 493 494/** 495 * bnx2x_poll - NAPI callback 496 * 497 * @napi: napi structure 498 * @budget: 499 * 500 */ 501int bnx2x_poll(struct napi_struct *napi, int budget); 502 503/** 504 * bnx2x_alloc_mem_bp - allocate memories outsize main driver structure 505 * 506 * @bp: driver handle 507 */ 508int __devinit bnx2x_alloc_mem_bp(struct bnx2x *bp); 509 510/** 511 * bnx2x_free_mem_bp - release memories outsize main driver structure 512 * 513 * @bp: driver handle 514 */ 515void bnx2x_free_mem_bp(struct bnx2x *bp); 516 517/** 518 * bnx2x_change_mtu - change mtu netdev callback 519 * 520 * @dev: net device 521 * @new_mtu: requested mtu 522 * 523 */ 524int bnx2x_change_mtu(struct net_device *dev, int new_mtu); 525 526#if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC) 527/** 528 * bnx2x_fcoe_get_wwn - return the requested WWN value for this port 529 * 530 * @dev: net_device 531 * @wwn: output buffer 532 * @type: WWN type: NETDEV_FCOE_WWNN (node) or NETDEV_FCOE_WWPN (port) 533 * 534 */ 535int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type); 536#endif 537netdev_features_t bnx2x_fix_features(struct net_device *dev, 538 netdev_features_t features); 539int bnx2x_set_features(struct net_device *dev, netdev_features_t features); 540 541/** 542 * bnx2x_tx_timeout - tx timeout netdev callback 543 * 544 * @dev: net device 545 */ 546void bnx2x_tx_timeout(struct net_device *dev); 547 548/*********************** Inlines **********************************/ 549/*********************** Fast path ********************************/ 550static inline void bnx2x_update_fpsb_idx(struct bnx2x_fastpath *fp) 551{ 552 barrier(); /* status block is written to by the chip */ 553 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 554} 555 556static inline void bnx2x_update_rx_prod_gen(struct bnx2x *bp, 557 struct bnx2x_fastpath *fp, u16 bd_prod, 558 u16 rx_comp_prod, u16 rx_sge_prod, u32 start) 559{ 560 struct ustorm_eth_rx_producers rx_prods = {0}; 561 u32 i; 562 563 /* Update producers */ 564 rx_prods.bd_prod = bd_prod; 565 rx_prods.cqe_prod = rx_comp_prod; 566 rx_prods.sge_prod = rx_sge_prod; 567 568 /* 569 * Make sure that the BD and SGE data is updated before updating the 570 * producers since FW might read the BD/SGE right after the producer 571 * is updated. 572 * This is only applicable for weak-ordered memory model archs such 573 * as IA-64. The following barrier is also mandatory since FW will 574 * assumes BDs must have buffers. 575 */ 576 wmb(); 577 578 for (i = 0; i < sizeof(rx_prods)/4; i++) 579 REG_WR(bp, start + i*4, ((u32 *)&rx_prods)[i]); 580 581 mmiowb(); /* keep prod updates ordered */ 582 583 DP(NETIF_MSG_RX_STATUS, 584 "queue[%d]: wrote bd_prod %u cqe_prod %u sge_prod %u\n", 585 fp->index, bd_prod, rx_comp_prod, rx_sge_prod); 586} 587 588static inline void bnx2x_igu_ack_sb_gen(struct bnx2x *bp, u8 igu_sb_id, 589 u8 segment, u16 index, u8 op, 590 u8 update, u32 igu_addr) 591{ 592 struct igu_regular cmd_data = {0}; 593 594 cmd_data.sb_id_and_flags = 595 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 596 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 597 (update << IGU_REGULAR_BUPDATE_SHIFT) | 598 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 599 600 DP(NETIF_MSG_HW, "write 0x%08x to IGU addr 0x%x\n", 601 cmd_data.sb_id_and_flags, igu_addr); 602 REG_WR(bp, igu_addr, cmd_data.sb_id_and_flags); 603 604 /* Make sure that ACK is written */ 605 mmiowb(); 606 barrier(); 607} 608 609static inline void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, 610 u8 idu_sb_id, bool is_Pf) 611{ 612 u32 data, ctl, cnt = 100; 613 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 614 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 615 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; 616 u32 sb_bit = 1 << (idu_sb_id%32); 617 u32 func_encode = func | 618 ((is_Pf == true ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT); 619 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; 620 621 /* Not supported in BC mode */ 622 if (CHIP_INT_MODE_IS_BC(bp)) 623 return; 624 625 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup 626 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) | 627 IGU_REGULAR_CLEANUP_SET | 628 IGU_REGULAR_BCLEANUP; 629 630 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT | 631 func_encode << IGU_CTRL_REG_FID_SHIFT | 632 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT; 633 634 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 635 data, igu_addr_data); 636 REG_WR(bp, igu_addr_data, data); 637 mmiowb(); 638 barrier(); 639 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 640 ctl, igu_addr_ctl); 641 REG_WR(bp, igu_addr_ctl, ctl); 642 mmiowb(); 643 barrier(); 644 645 /* wait for clean up to finish */ 646 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt) 647 msleep(20); 648 649 650 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) { 651 DP(NETIF_MSG_HW, "Unable to finish IGU cleanup: " 652 "idu_sb_id %d offset %d bit %d (cnt %d)\n", 653 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); 654 } 655} 656 657static inline void bnx2x_hc_ack_sb(struct bnx2x *bp, u8 sb_id, 658 u8 storm, u16 index, u8 op, u8 update) 659{ 660 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 661 COMMAND_REG_INT_ACK); 662 struct igu_ack_register igu_ack; 663 664 igu_ack.status_block_index = index; 665 igu_ack.sb_id_and_flags = 666 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 667 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 668 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 669 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 670 671 DP(BNX2X_MSG_OFF, "write 0x%08x to HC addr 0x%x\n", 672 (*(u32 *)&igu_ack), hc_addr); 673 REG_WR(bp, hc_addr, (*(u32 *)&igu_ack)); 674 675 /* Make sure that ACK is written */ 676 mmiowb(); 677 barrier(); 678} 679 680static inline void bnx2x_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 storm, 681 u16 index, u8 op, u8 update) 682{ 683 if (bp->common.int_block == INT_BLOCK_HC) 684 bnx2x_hc_ack_sb(bp, igu_sb_id, storm, index, op, update); 685 else { 686 u8 segment; 687 688 if (CHIP_INT_MODE_IS_BC(bp)) 689 segment = storm; 690 else if (igu_sb_id != bp->igu_dsb_id) 691 segment = IGU_SEG_ACCESS_DEF; 692 else if (storm == ATTENTION_ID) 693 segment = IGU_SEG_ACCESS_ATTN; 694 else 695 segment = IGU_SEG_ACCESS_DEF; 696 bnx2x_igu_ack_sb(bp, igu_sb_id, segment, index, op, update); 697 } 698} 699 700static inline u16 bnx2x_hc_ack_int(struct bnx2x *bp) 701{ 702 u32 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(bp)*32 + 703 COMMAND_REG_SIMD_MASK); 704 u32 result = REG_RD(bp, hc_addr); 705 706 DP(BNX2X_MSG_OFF, "read 0x%08x from HC addr 0x%x\n", 707 result, hc_addr); 708 709 barrier(); 710 return result; 711} 712 713static inline u16 bnx2x_igu_ack_int(struct bnx2x *bp) 714{ 715 u32 igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 716 u32 result = REG_RD(bp, igu_addr); 717 718 DP(NETIF_MSG_HW, "read 0x%08x from IGU addr 0x%x\n", 719 result, igu_addr); 720 721 barrier(); 722 return result; 723} 724 725static inline u16 bnx2x_ack_int(struct bnx2x *bp) 726{ 727 barrier(); 728 if (bp->common.int_block == INT_BLOCK_HC) 729 return bnx2x_hc_ack_int(bp); 730 else 731 return bnx2x_igu_ack_int(bp); 732} 733 734static inline int bnx2x_has_tx_work_unload(struct bnx2x_fp_txdata *txdata) 735{ 736 /* Tell compiler that consumer and producer can change */ 737 barrier(); 738 return txdata->tx_pkt_prod != txdata->tx_pkt_cons; 739} 740 741static inline u16 bnx2x_tx_avail(struct bnx2x *bp, 742 struct bnx2x_fp_txdata *txdata) 743{ 744 s16 used; 745 u16 prod; 746 u16 cons; 747 748 prod = txdata->tx_bd_prod; 749 cons = txdata->tx_bd_cons; 750 751 /* NUM_TX_RINGS = number of "next-page" entries 752 It will be used as a threshold */ 753 used = SUB_S16(prod, cons) + (s16)NUM_TX_RINGS; 754 755#ifdef BNX2X_STOP_ON_ERROR 756 WARN_ON(used < 0); 757 WARN_ON(used > bp->tx_ring_size); 758 WARN_ON((bp->tx_ring_size - used) > MAX_TX_AVAIL); 759#endif 760 761 return (s16)(bp->tx_ring_size) - used; 762} 763 764static inline int bnx2x_tx_queue_has_work(struct bnx2x_fp_txdata *txdata) 765{ 766 u16 hw_cons; 767 768 /* Tell compiler that status block fields can change */ 769 barrier(); 770 hw_cons = le16_to_cpu(*txdata->tx_cons_sb); 771 return hw_cons != txdata->tx_pkt_cons; 772} 773 774static inline bool bnx2x_has_tx_work(struct bnx2x_fastpath *fp) 775{ 776 u8 cos; 777 for_each_cos_in_tx_queue(fp, cos) 778 if (bnx2x_tx_queue_has_work(&fp->txdata[cos])) 779 return true; 780 return false; 781} 782 783static inline int bnx2x_has_rx_work(struct bnx2x_fastpath *fp) 784{ 785 u16 rx_cons_sb; 786 787 /* Tell compiler that status block fields can change */ 788 barrier(); 789 rx_cons_sb = le16_to_cpu(*fp->rx_cons_sb); 790 if ((rx_cons_sb & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT) 791 rx_cons_sb++; 792 return (fp->rx_comp_cons != rx_cons_sb); 793} 794 795/** 796 * bnx2x_tx_disable - disables tx from stack point of view 797 * 798 * @bp: driver handle 799 */ 800static inline void bnx2x_tx_disable(struct bnx2x *bp) 801{ 802 netif_tx_disable(bp->dev); 803 netif_carrier_off(bp->dev); 804} 805 806static inline void bnx2x_free_rx_sge(struct bnx2x *bp, 807 struct bnx2x_fastpath *fp, u16 index) 808{ 809 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; 810 struct page *page = sw_buf->page; 811 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; 812 813 /* Skip "next page" elements */ 814 if (!page) 815 return; 816 817 dma_unmap_page(&bp->pdev->dev, dma_unmap_addr(sw_buf, mapping), 818 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); 819 __free_pages(page, PAGES_PER_SGE_SHIFT); 820 821 sw_buf->page = NULL; 822 sge->addr_hi = 0; 823 sge->addr_lo = 0; 824} 825 826static inline void bnx2x_add_all_napi(struct bnx2x *bp) 827{ 828 int i; 829 830 /* Add NAPI objects */ 831 for_each_rx_queue(bp, i) 832 netif_napi_add(bp->dev, &bnx2x_fp(bp, i, napi), 833 bnx2x_poll, BNX2X_NAPI_WEIGHT); 834} 835 836static inline void bnx2x_del_all_napi(struct bnx2x *bp) 837{ 838 int i; 839 840 for_each_rx_queue(bp, i) 841 netif_napi_del(&bnx2x_fp(bp, i, napi)); 842} 843 844static inline void bnx2x_disable_msi(struct bnx2x *bp) 845{ 846 if (bp->flags & USING_MSIX_FLAG) { 847 pci_disable_msix(bp->pdev); 848 bp->flags &= ~USING_MSIX_FLAG; 849 } else if (bp->flags & USING_MSI_FLAG) { 850 pci_disable_msi(bp->pdev); 851 bp->flags &= ~USING_MSI_FLAG; 852 } 853} 854 855static inline int bnx2x_calc_num_queues(struct bnx2x *bp) 856{ 857 return num_queues ? 858 min_t(int, num_queues, BNX2X_MAX_QUEUES(bp)) : 859 min_t(int, num_online_cpus(), BNX2X_MAX_QUEUES(bp)); 860} 861 862static inline void bnx2x_clear_sge_mask_next_elems(struct bnx2x_fastpath *fp) 863{ 864 int i, j; 865 866 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { 867 int idx = RX_SGE_CNT * i - 1; 868 869 for (j = 0; j < 2; j++) { 870 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); 871 idx--; 872 } 873 } 874} 875 876static inline void bnx2x_init_sge_ring_bit_mask(struct bnx2x_fastpath *fp) 877{ 878 /* Set the mask to all 1-s: it's faster to compare to 0 than to 0xf-s */ 879 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); 880 881 /* Clear the two last indices in the page to 1: 882 these are the indices that correspond to the "next" element, 883 hence will never be indicated and should be removed from 884 the calculations. */ 885 bnx2x_clear_sge_mask_next_elems(fp); 886} 887 888static inline int bnx2x_alloc_rx_sge(struct bnx2x *bp, 889 struct bnx2x_fastpath *fp, u16 index) 890{ 891 struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT); 892 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index]; 893 struct eth_rx_sge *sge = &fp->rx_sge_ring[index]; 894 dma_addr_t mapping; 895 896 if (unlikely(page == NULL)) 897 return -ENOMEM; 898 899 mapping = dma_map_page(&bp->pdev->dev, page, 0, 900 SGE_PAGE_SIZE*PAGES_PER_SGE, DMA_FROM_DEVICE); 901 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 902 __free_pages(page, PAGES_PER_SGE_SHIFT); 903 return -ENOMEM; 904 } 905 906 sw_buf->page = page; 907 dma_unmap_addr_set(sw_buf, mapping, mapping); 908 909 sge->addr_hi = cpu_to_le32(U64_HI(mapping)); 910 sge->addr_lo = cpu_to_le32(U64_LO(mapping)); 911 912 return 0; 913} 914 915static inline int bnx2x_alloc_rx_data(struct bnx2x *bp, 916 struct bnx2x_fastpath *fp, u16 index) 917{ 918 u8 *data; 919 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index]; 920 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index]; 921 dma_addr_t mapping; 922 923 data = kmalloc(fp->rx_buf_size + NET_SKB_PAD, GFP_ATOMIC); 924 if (unlikely(data == NULL)) 925 return -ENOMEM; 926 927 mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD, 928 fp->rx_buf_size, 929 DMA_FROM_DEVICE); 930 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) { 931 kfree(data); 932 return -ENOMEM; 933 } 934 935 rx_buf->data = data; 936 dma_unmap_addr_set(rx_buf, mapping, mapping); 937 938 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping)); 939 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping)); 940 941 return 0; 942} 943 944/* note that we are not allocating a new buffer, 945 * we are just moving one from cons to prod 946 * we are not creating a new mapping, 947 * so there is no need to check for dma_mapping_error(). 948 */ 949static inline void bnx2x_reuse_rx_data(struct bnx2x_fastpath *fp, 950 u16 cons, u16 prod) 951{ 952 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons]; 953 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod]; 954 struct eth_rx_bd *cons_bd = &fp->rx_desc_ring[cons]; 955 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod]; 956 957 dma_unmap_addr_set(prod_rx_buf, mapping, 958 dma_unmap_addr(cons_rx_buf, mapping)); 959 prod_rx_buf->data = cons_rx_buf->data; 960 *prod_bd = *cons_bd; 961} 962 963/************************* Init ******************************************/ 964 965/** 966 * bnx2x_func_start - init function 967 * 968 * @bp: driver handle 969 * 970 * Must be called before sending CLIENT_SETUP for the first client. 971 */ 972static inline int bnx2x_func_start(struct bnx2x *bp) 973{ 974 struct bnx2x_func_state_params func_params = {0}; 975 struct bnx2x_func_start_params *start_params = 976 &func_params.params.start; 977 978 /* Prepare parameters for function state transitions */ 979 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 980 981 func_params.f_obj = &bp->func_obj; 982 func_params.cmd = BNX2X_F_CMD_START; 983 984 /* Function parameters */ 985 start_params->mf_mode = bp->mf_mode; 986 start_params->sd_vlan_tag = bp->mf_ov; 987 if (CHIP_IS_E1x(bp)) 988 start_params->network_cos_mode = OVERRIDE_COS; 989 else 990 start_params->network_cos_mode = STATIC_COS; 991 992 return bnx2x_func_state_change(bp, &func_params); 993} 994 995 996/** 997 * bnx2x_set_fw_mac_addr - fill in a MAC address in FW format 998 * 999 * @fw_hi: pointer to upper part 1000 * @fw_mid: pointer to middle part 1001 * @fw_lo: pointer to lower part 1002 * @mac: pointer to MAC address 1003 */ 1004static inline void bnx2x_set_fw_mac_addr(u16 *fw_hi, u16 *fw_mid, u16 *fw_lo, 1005 u8 *mac) 1006{ 1007 ((u8 *)fw_hi)[0] = mac[1]; 1008 ((u8 *)fw_hi)[1] = mac[0]; 1009 ((u8 *)fw_mid)[0] = mac[3]; 1010 ((u8 *)fw_mid)[1] = mac[2]; 1011 ((u8 *)fw_lo)[0] = mac[5]; 1012 ((u8 *)fw_lo)[1] = mac[4]; 1013} 1014 1015static inline void bnx2x_free_rx_sge_range(struct bnx2x *bp, 1016 struct bnx2x_fastpath *fp, int last) 1017{ 1018 int i; 1019 1020 if (fp->disable_tpa) 1021 return; 1022 1023 for (i = 0; i < last; i++) 1024 bnx2x_free_rx_sge(bp, fp, i); 1025} 1026 1027static inline void bnx2x_free_tpa_pool(struct bnx2x *bp, 1028 struct bnx2x_fastpath *fp, int last) 1029{ 1030 int i; 1031 1032 for (i = 0; i < last; i++) { 1033 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i]; 1034 struct sw_rx_bd *first_buf = &tpa_info->first_buf; 1035 u8 *data = first_buf->data; 1036 1037 if (data == NULL) { 1038 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i); 1039 continue; 1040 } 1041 if (tpa_info->tpa_state == BNX2X_TPA_START) 1042 dma_unmap_single(&bp->pdev->dev, 1043 dma_unmap_addr(first_buf, mapping), 1044 fp->rx_buf_size, DMA_FROM_DEVICE); 1045 kfree(data); 1046 first_buf->data = NULL; 1047 } 1048} 1049 1050static inline void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata) 1051{ 1052 int i; 1053 1054 for (i = 1; i <= NUM_TX_RINGS; i++) { 1055 struct eth_tx_next_bd *tx_next_bd = 1056 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd; 1057 1058 tx_next_bd->addr_hi = 1059 cpu_to_le32(U64_HI(txdata->tx_desc_mapping + 1060 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 1061 tx_next_bd->addr_lo = 1062 cpu_to_le32(U64_LO(txdata->tx_desc_mapping + 1063 BCM_PAGE_SIZE*(i % NUM_TX_RINGS))); 1064 } 1065 1066 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); 1067 txdata->tx_db.data.zero_fill1 = 0; 1068 txdata->tx_db.data.prod = 0; 1069 1070 txdata->tx_pkt_prod = 0; 1071 txdata->tx_pkt_cons = 0; 1072 txdata->tx_bd_prod = 0; 1073 txdata->tx_bd_cons = 0; 1074 txdata->tx_pkt = 0; 1075} 1076 1077static inline void bnx2x_init_tx_rings(struct bnx2x *bp) 1078{ 1079 int i; 1080 u8 cos; 1081 1082 for_each_tx_queue(bp, i) 1083 for_each_cos_in_tx_queue(&bp->fp[i], cos) 1084 bnx2x_init_tx_ring_one(&bp->fp[i].txdata[cos]); 1085} 1086 1087static inline void bnx2x_set_next_page_rx_bd(struct bnx2x_fastpath *fp) 1088{ 1089 int i; 1090 1091 for (i = 1; i <= NUM_RX_RINGS; i++) { 1092 struct eth_rx_bd *rx_bd; 1093 1094 rx_bd = &fp->rx_desc_ring[RX_DESC_CNT * i - 2]; 1095 rx_bd->addr_hi = 1096 cpu_to_le32(U64_HI(fp->rx_desc_mapping + 1097 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 1098 rx_bd->addr_lo = 1099 cpu_to_le32(U64_LO(fp->rx_desc_mapping + 1100 BCM_PAGE_SIZE*(i % NUM_RX_RINGS))); 1101 } 1102} 1103 1104static inline void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp) 1105{ 1106 int i; 1107 1108 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) { 1109 struct eth_rx_sge *sge; 1110 1111 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2]; 1112 sge->addr_hi = 1113 cpu_to_le32(U64_HI(fp->rx_sge_mapping + 1114 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES))); 1115 1116 sge->addr_lo = 1117 cpu_to_le32(U64_LO(fp->rx_sge_mapping + 1118 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES))); 1119 } 1120} 1121 1122static inline void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp) 1123{ 1124 int i; 1125 for (i = 1; i <= NUM_RCQ_RINGS; i++) { 1126 struct eth_rx_cqe_next_page *nextpg; 1127 1128 nextpg = (struct eth_rx_cqe_next_page *) 1129 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1]; 1130 nextpg->addr_hi = 1131 cpu_to_le32(U64_HI(fp->rx_comp_mapping + 1132 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); 1133 nextpg->addr_lo = 1134 cpu_to_le32(U64_LO(fp->rx_comp_mapping + 1135 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS))); 1136 } 1137} 1138 1139/* Returns the number of actually allocated BDs */ 1140static inline int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp, 1141 int rx_ring_size) 1142{ 1143 struct bnx2x *bp = fp->bp; 1144 u16 ring_prod, cqe_ring_prod; 1145 int i; 1146 1147 fp->rx_comp_cons = 0; 1148 cqe_ring_prod = ring_prod = 0; 1149 1150 /* This routine is called only during fo init so 1151 * fp->eth_q_stats.rx_skb_alloc_failed = 0 1152 */ 1153 for (i = 0; i < rx_ring_size; i++) { 1154 if (bnx2x_alloc_rx_data(bp, fp, ring_prod) < 0) { 1155 fp->eth_q_stats.rx_skb_alloc_failed++; 1156 continue; 1157 } 1158 ring_prod = NEXT_RX_IDX(ring_prod); 1159 cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod); 1160 WARN_ON(ring_prod <= (i - fp->eth_q_stats.rx_skb_alloc_failed)); 1161 } 1162 1163 if (fp->eth_q_stats.rx_skb_alloc_failed) 1164 BNX2X_ERR("was only able to allocate " 1165 "%d rx skbs on queue[%d]\n", 1166 (i - fp->eth_q_stats.rx_skb_alloc_failed), fp->index); 1167 1168 fp->rx_bd_prod = ring_prod; 1169 /* Limit the CQE producer by the CQE ring size */ 1170 fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT, 1171 cqe_ring_prod); 1172 fp->rx_pkt = fp->rx_calls = 0; 1173 1174 return i - fp->eth_q_stats.rx_skb_alloc_failed; 1175} 1176 1177/* Statistics ID are global per chip/path, while Client IDs for E1x are per 1178 * port. 1179 */ 1180static inline u8 bnx2x_stats_id(struct bnx2x_fastpath *fp) 1181{ 1182 struct bnx2x *bp = fp->bp; 1183 if (!CHIP_IS_E1x(bp)) { 1184#ifdef BCM_CNIC 1185 /* there are special statistics counters for FCoE 136..140 */ 1186 if (IS_FCOE_FP(fp)) 1187 return bp->cnic_base_cl_id + (bp->pf_num >> 1); 1188#endif 1189 return fp->cl_id; 1190 } 1191 return fp->cl_id + BP_PORT(bp) * FP_SB_MAX_E1x; 1192} 1193 1194static inline void bnx2x_init_vlan_mac_fp_objs(struct bnx2x_fastpath *fp, 1195 bnx2x_obj_type obj_type) 1196{ 1197 struct bnx2x *bp = fp->bp; 1198 1199 /* Configure classification DBs */ 1200 bnx2x_init_mac_obj(bp, &fp->mac_obj, fp->cl_id, fp->cid, 1201 BP_FUNC(bp), bnx2x_sp(bp, mac_rdata), 1202 bnx2x_sp_mapping(bp, mac_rdata), 1203 BNX2X_FILTER_MAC_PENDING, 1204 &bp->sp_state, obj_type, 1205 &bp->macs_pool); 1206} 1207 1208/** 1209 * bnx2x_get_path_func_num - get number of active functions 1210 * 1211 * @bp: driver handle 1212 * 1213 * Calculates the number of active (not hidden) functions on the 1214 * current path. 1215 */ 1216static inline u8 bnx2x_get_path_func_num(struct bnx2x *bp) 1217{ 1218 u8 func_num = 0, i; 1219 1220 /* 57710 has only one function per-port */ 1221 if (CHIP_IS_E1(bp)) 1222 return 1; 1223 1224 /* Calculate a number of functions enabled on the current 1225 * PATH/PORT. 1226 */ 1227 if (CHIP_REV_IS_SLOW(bp)) { 1228 if (IS_MF(bp)) 1229 func_num = 4; 1230 else 1231 func_num = 2; 1232 } else { 1233 for (i = 0; i < E1H_FUNC_MAX / 2; i++) { 1234 u32 func_config = 1235 MF_CFG_RD(bp, 1236 func_mf_config[BP_PORT(bp) + 2 * i]. 1237 config); 1238 func_num += 1239 ((func_config & FUNC_MF_CFG_FUNC_HIDE) ? 0 : 1); 1240 } 1241 } 1242 1243 WARN_ON(!func_num); 1244 1245 return func_num; 1246} 1247 1248static inline void bnx2x_init_bp_objs(struct bnx2x *bp) 1249{ 1250 /* RX_MODE controlling object */ 1251 bnx2x_init_rx_mode_obj(bp, &bp->rx_mode_obj); 1252 1253 /* multicast configuration controlling object */ 1254 bnx2x_init_mcast_obj(bp, &bp->mcast_obj, bp->fp->cl_id, bp->fp->cid, 1255 BP_FUNC(bp), BP_FUNC(bp), 1256 bnx2x_sp(bp, mcast_rdata), 1257 bnx2x_sp_mapping(bp, mcast_rdata), 1258 BNX2X_FILTER_MCAST_PENDING, &bp->sp_state, 1259 BNX2X_OBJ_TYPE_RX); 1260 1261 /* Setup CAM credit pools */ 1262 bnx2x_init_mac_credit_pool(bp, &bp->macs_pool, BP_FUNC(bp), 1263 bnx2x_get_path_func_num(bp)); 1264 1265 /* RSS configuration object */ 1266 bnx2x_init_rss_config_obj(bp, &bp->rss_conf_obj, bp->fp->cl_id, 1267 bp->fp->cid, BP_FUNC(bp), BP_FUNC(bp), 1268 bnx2x_sp(bp, rss_rdata), 1269 bnx2x_sp_mapping(bp, rss_rdata), 1270 BNX2X_FILTER_RSS_CONF_PENDING, &bp->sp_state, 1271 BNX2X_OBJ_TYPE_RX); 1272} 1273 1274static inline u8 bnx2x_fp_qzone_id(struct bnx2x_fastpath *fp) 1275{ 1276 if (CHIP_IS_E1x(fp->bp)) 1277 return fp->cl_id + BP_PORT(fp->bp) * ETH_MAX_RX_CLIENTS_E1H; 1278 else 1279 return fp->cl_id; 1280} 1281 1282static inline u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp) 1283{ 1284 struct bnx2x *bp = fp->bp; 1285 1286 if (!CHIP_IS_E1x(bp)) 1287 return USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); 1288 else 1289 return USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id); 1290} 1291 1292static inline void bnx2x_init_txdata(struct bnx2x *bp, 1293 struct bnx2x_fp_txdata *txdata, u32 cid, int txq_index, 1294 __le16 *tx_cons_sb) 1295{ 1296 txdata->cid = cid; 1297 txdata->txq_index = txq_index; 1298 txdata->tx_cons_sb = tx_cons_sb; 1299 1300 DP(BNX2X_MSG_SP, "created tx data cid %d, txq %d\n", 1301 txdata->cid, txdata->txq_index); 1302} 1303 1304#ifdef BCM_CNIC 1305static inline u8 bnx2x_cnic_eth_cl_id(struct bnx2x *bp, u8 cl_idx) 1306{ 1307 return bp->cnic_base_cl_id + cl_idx + 1308 (bp->pf_num >> 1) * BNX2X_MAX_CNIC_ETH_CL_ID_IDX; 1309} 1310 1311static inline u8 bnx2x_cnic_fw_sb_id(struct bnx2x *bp) 1312{ 1313 1314 /* the 'first' id is allocated for the cnic */ 1315 return bp->base_fw_ndsb; 1316} 1317 1318static inline u8 bnx2x_cnic_igu_sb_id(struct bnx2x *bp) 1319{ 1320 return bp->igu_base_sb; 1321} 1322 1323 1324static inline void bnx2x_init_fcoe_fp(struct bnx2x *bp) 1325{ 1326 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp); 1327 unsigned long q_type = 0; 1328 1329 bnx2x_fcoe(bp, rx_queue) = BNX2X_NUM_ETH_QUEUES(bp); 1330 bnx2x_fcoe(bp, cl_id) = bnx2x_cnic_eth_cl_id(bp, 1331 BNX2X_FCOE_ETH_CL_ID_IDX); 1332 /** Current BNX2X_FCOE_ETH_CID deffinition implies not more than 1333 * 16 ETH clients per function when CNIC is enabled! 1334 * 1335 * Fix it ASAP!!! 1336 */ 1337 bnx2x_fcoe(bp, cid) = BNX2X_FCOE_ETH_CID; 1338 bnx2x_fcoe(bp, fw_sb_id) = DEF_SB_ID; 1339 bnx2x_fcoe(bp, igu_sb_id) = bp->igu_dsb_id; 1340 bnx2x_fcoe(bp, rx_cons_sb) = BNX2X_FCOE_L2_RX_INDEX; 1341 1342 bnx2x_init_txdata(bp, &bnx2x_fcoe(bp, txdata[0]), 1343 fp->cid, FCOE_TXQ_IDX(bp), BNX2X_FCOE_L2_TX_INDEX); 1344 1345 DP(BNX2X_MSG_SP, "created fcoe tx data (fp index %d)\n", fp->index); 1346 1347 /* qZone id equals to FW (per path) client id */ 1348 bnx2x_fcoe(bp, cl_qzone_id) = bnx2x_fp_qzone_id(fp); 1349 /* init shortcut */ 1350 bnx2x_fcoe(bp, ustorm_rx_prods_offset) = 1351 bnx2x_rx_ustorm_prods_offset(fp); 1352 1353 /* Configure Queue State object */ 1354 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type); 1355 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type); 1356 1357 /* No multi-CoS for FCoE L2 client */ 1358 BUG_ON(fp->max_cos != 1); 1359 1360 bnx2x_init_queue_obj(bp, &fp->q_obj, fp->cl_id, &fp->cid, 1, 1361 BP_FUNC(bp), bnx2x_sp(bp, q_rdata), 1362 bnx2x_sp_mapping(bp, q_rdata), q_type); 1363 1364 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d " 1365 "igu_sb %d\n", 1366 fp->index, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id, 1367 fp->igu_sb_id); 1368} 1369#endif 1370 1371static inline int bnx2x_clean_tx_queue(struct bnx2x *bp, 1372 struct bnx2x_fp_txdata *txdata) 1373{ 1374 int cnt = 1000; 1375 1376 while (bnx2x_has_tx_work_unload(txdata)) { 1377 if (!cnt) { 1378 BNX2X_ERR("timeout waiting for queue[%d]: " 1379 "txdata->tx_pkt_prod(%d) != txdata->tx_pkt_cons(%d)\n", 1380 txdata->txq_index, txdata->tx_pkt_prod, 1381 txdata->tx_pkt_cons); 1382#ifdef BNX2X_STOP_ON_ERROR 1383 bnx2x_panic(); 1384 return -EBUSY; 1385#else 1386 break; 1387#endif 1388 } 1389 cnt--; 1390 usleep_range(1000, 1000); 1391 } 1392 1393 return 0; 1394} 1395 1396int bnx2x_get_link_cfg_idx(struct bnx2x *bp); 1397 1398static inline void __storm_memset_struct(struct bnx2x *bp, 1399 u32 addr, size_t size, u32 *data) 1400{ 1401 int i; 1402 for (i = 0; i < size/4; i++) 1403 REG_WR(bp, addr + (i * 4), data[i]); 1404} 1405 1406static inline void storm_memset_func_cfg(struct bnx2x *bp, 1407 struct tstorm_eth_function_common_config *tcfg, 1408 u16 abs_fid) 1409{ 1410 size_t size = sizeof(struct tstorm_eth_function_common_config); 1411 1412 u32 addr = BAR_TSTRORM_INTMEM + 1413 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid); 1414 1415 __storm_memset_struct(bp, addr, size, (u32 *)tcfg); 1416} 1417 1418static inline void storm_memset_cmng(struct bnx2x *bp, 1419 struct cmng_struct_per_port *cmng, 1420 u8 port) 1421{ 1422 size_t size = sizeof(struct cmng_struct_per_port); 1423 1424 u32 addr = BAR_XSTRORM_INTMEM + 1425 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port); 1426 1427 __storm_memset_struct(bp, addr, size, (u32 *)cmng); 1428} 1429 1430/** 1431 * bnx2x_wait_sp_comp - wait for the outstanding SP commands. 1432 * 1433 * @bp: driver handle 1434 * @mask: bits that need to be cleared 1435 */ 1436static inline bool bnx2x_wait_sp_comp(struct bnx2x *bp, unsigned long mask) 1437{ 1438 int tout = 5000; /* Wait for 5 secs tops */ 1439 1440 while (tout--) { 1441 smp_mb(); 1442 netif_addr_lock_bh(bp->dev); 1443 if (!(bp->sp_state & mask)) { 1444 netif_addr_unlock_bh(bp->dev); 1445 return true; 1446 } 1447 netif_addr_unlock_bh(bp->dev); 1448 1449 usleep_range(1000, 1000); 1450 } 1451 1452 smp_mb(); 1453 1454 netif_addr_lock_bh(bp->dev); 1455 if (bp->sp_state & mask) { 1456 BNX2X_ERR("Filtering completion timed out. sp_state 0x%lx, " 1457 "mask 0x%lx\n", bp->sp_state, mask); 1458 netif_addr_unlock_bh(bp->dev); 1459 return false; 1460 } 1461 netif_addr_unlock_bh(bp->dev); 1462 1463 return true; 1464} 1465 1466/** 1467 * bnx2x_set_ctx_validation - set CDU context validation values 1468 * 1469 * @bp: driver handle 1470 * @cxt: context of the connection on the host memory 1471 * @cid: SW CID of the connection to be configured 1472 */ 1473void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt, 1474 u32 cid); 1475 1476void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id, 1477 u8 sb_index, u8 disable, u16 usec); 1478void bnx2x_acquire_phy_lock(struct bnx2x *bp); 1479void bnx2x_release_phy_lock(struct bnx2x *bp); 1480 1481/** 1482 * bnx2x_extract_max_cfg - extract MAX BW part from MF configuration. 1483 * 1484 * @bp: driver handle 1485 * @mf_cfg: MF configuration 1486 * 1487 */ 1488static inline u16 bnx2x_extract_max_cfg(struct bnx2x *bp, u32 mf_cfg) 1489{ 1490 u16 max_cfg = (mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 1491 FUNC_MF_CFG_MAX_BW_SHIFT; 1492 if (!max_cfg) { 1493 DP(NETIF_MSG_LINK, 1494 "Max BW configured to 0 - using 100 instead\n"); 1495 max_cfg = 100; 1496 } 1497 return max_cfg; 1498} 1499 1500/** 1501 * bnx2x_get_iscsi_info - update iSCSI params according to licensing info. 1502 * 1503 * @bp: driver handle 1504 * 1505 */ 1506void bnx2x_get_iscsi_info(struct bnx2x *bp); 1507 1508/* returns func by VN for current port */ 1509static inline int func_by_vn(struct bnx2x *bp, int vn) 1510{ 1511 return 2 * vn + BP_PORT(bp); 1512} 1513 1514/** 1515 * bnx2x_link_sync_notify - send notification to other functions. 1516 * 1517 * @bp: driver handle 1518 * 1519 */ 1520static inline void bnx2x_link_sync_notify(struct bnx2x *bp) 1521{ 1522 int func; 1523 int vn; 1524 1525 /* Set the attention towards other drivers on the same port */ 1526 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) { 1527 if (vn == BP_VN(bp)) 1528 continue; 1529 1530 func = func_by_vn(bp, vn); 1531 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + 1532 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); 1533 } 1534} 1535 1536/** 1537 * bnx2x_update_drv_flags - update flags in shmem 1538 * 1539 * @bp: driver handle 1540 * @flags: flags to update 1541 * @set: set or clear 1542 * 1543 */ 1544static inline void bnx2x_update_drv_flags(struct bnx2x *bp, u32 flags, u32 set) 1545{ 1546 if (SHMEM2_HAS(bp, drv_flags)) { 1547 u32 drv_flags; 1548 bnx2x_acquire_hw_lock(bp, HW_LOCK_DRV_FLAGS); 1549 drv_flags = SHMEM2_RD(bp, drv_flags); 1550 1551 if (set) 1552 SET_FLAGS(drv_flags, flags); 1553 else 1554 RESET_FLAGS(drv_flags, flags); 1555 1556 SHMEM2_WR(bp, drv_flags, drv_flags); 1557 DP(NETIF_MSG_HW, "drv_flags 0x%08x\n", drv_flags); 1558 bnx2x_release_hw_lock(bp, HW_LOCK_DRV_FLAGS); 1559 } 1560} 1561 1562static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr) 1563{ 1564 if (is_valid_ether_addr(addr)) 1565 return true; 1566#ifdef BCM_CNIC 1567 if (is_zero_ether_addr(addr) && IS_MF_ISCSI_SD(bp)) 1568 return true; 1569#endif 1570 return false; 1571} 1572 1573#endif /* BNX2X_CMN_H */ 1574