bnx2x_sp.h revision a334872224a67b614dc888460377862621f3dac7
1/* bnx2x_sp.h: Broadcom Everest network driver. 2 * 3 * Copyright (c) 2011-2012 Broadcom Corporation 4 * 5 * Unless you and Broadcom execute a separate written software license 6 * agreement governing use of this software, this software is licensed to you 7 * under the terms of the GNU General Public License version 2, available 8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL"). 9 * 10 * Notwithstanding the above, under no circumstances may you combine this 11 * software in any way with any other Broadcom software provided under a 12 * license other than the GPL, without Broadcom's express prior written 13 * consent. 14 * 15 * Maintained by: Eilon Greenstein <eilong@broadcom.com> 16 * Written by: Vladislav Zolotarov 17 * 18 */ 19#ifndef BNX2X_SP_VERBS 20#define BNX2X_SP_VERBS 21 22struct bnx2x; 23struct eth_context; 24 25/* Bits representing general command's configuration */ 26enum { 27 RAMROD_TX, 28 RAMROD_RX, 29 /* Wait until all pending commands complete */ 30 RAMROD_COMP_WAIT, 31 /* Don't send a ramrod, only update a registry */ 32 RAMROD_DRV_CLR_ONLY, 33 /* Configure HW according to the current object state */ 34 RAMROD_RESTORE, 35 /* Execute the next command now */ 36 RAMROD_EXEC, 37 /* 38 * Don't add a new command and continue execution of posponed 39 * commands. If not set a new command will be added to the 40 * pending commands list. 41 */ 42 RAMROD_CONT, 43}; 44 45typedef enum { 46 BNX2X_OBJ_TYPE_RX, 47 BNX2X_OBJ_TYPE_TX, 48 BNX2X_OBJ_TYPE_RX_TX, 49} bnx2x_obj_type; 50 51/* Filtering states */ 52enum { 53 BNX2X_FILTER_MAC_PENDING, 54 BNX2X_FILTER_VLAN_PENDING, 55 BNX2X_FILTER_VLAN_MAC_PENDING, 56 BNX2X_FILTER_RX_MODE_PENDING, 57 BNX2X_FILTER_RX_MODE_SCHED, 58 BNX2X_FILTER_ISCSI_ETH_START_SCHED, 59 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, 60 BNX2X_FILTER_FCOE_ETH_START_SCHED, 61 BNX2X_FILTER_FCOE_ETH_STOP_SCHED, 62 BNX2X_FILTER_MCAST_PENDING, 63 BNX2X_FILTER_MCAST_SCHED, 64 BNX2X_FILTER_RSS_CONF_PENDING, 65 BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, 66 BNX2X_AFEX_PENDING_VIFSET_MCP_ACK 67}; 68 69struct bnx2x_raw_obj { 70 u8 func_id; 71 72 /* Queue params */ 73 u8 cl_id; 74 u32 cid; 75 76 /* Ramrod data buffer params */ 77 void *rdata; 78 dma_addr_t rdata_mapping; 79 80 /* Ramrod state params */ 81 int state; /* "ramrod is pending" state bit */ 82 unsigned long *pstate; /* pointer to state buffer */ 83 84 bnx2x_obj_type obj_type; 85 86 int (*wait_comp)(struct bnx2x *bp, 87 struct bnx2x_raw_obj *o); 88 89 bool (*check_pending)(struct bnx2x_raw_obj *o); 90 void (*clear_pending)(struct bnx2x_raw_obj *o); 91 void (*set_pending)(struct bnx2x_raw_obj *o); 92}; 93 94/************************* VLAN-MAC commands related parameters ***************/ 95struct bnx2x_mac_ramrod_data { 96 u8 mac[ETH_ALEN]; 97}; 98 99struct bnx2x_vlan_ramrod_data { 100 u16 vlan; 101}; 102 103struct bnx2x_vlan_mac_ramrod_data { 104 u8 mac[ETH_ALEN]; 105 u16 vlan; 106}; 107 108union bnx2x_classification_ramrod_data { 109 struct bnx2x_mac_ramrod_data mac; 110 struct bnx2x_vlan_ramrod_data vlan; 111 struct bnx2x_vlan_mac_ramrod_data vlan_mac; 112}; 113 114/* VLAN_MAC commands */ 115enum bnx2x_vlan_mac_cmd { 116 BNX2X_VLAN_MAC_ADD, 117 BNX2X_VLAN_MAC_DEL, 118 BNX2X_VLAN_MAC_MOVE, 119}; 120 121struct bnx2x_vlan_mac_data { 122 /* Requested command: BNX2X_VLAN_MAC_XX */ 123 enum bnx2x_vlan_mac_cmd cmd; 124 /* 125 * used to contain the data related vlan_mac_flags bits from 126 * ramrod parameters. 127 */ 128 unsigned long vlan_mac_flags; 129 130 /* Needed for MOVE command */ 131 struct bnx2x_vlan_mac_obj *target_obj; 132 133 union bnx2x_classification_ramrod_data u; 134}; 135 136/*************************** Exe Queue obj ************************************/ 137union bnx2x_exe_queue_cmd_data { 138 struct bnx2x_vlan_mac_data vlan_mac; 139 140 struct { 141 /* TODO */ 142 } mcast; 143}; 144 145struct bnx2x_exeq_elem { 146 struct list_head link; 147 148 /* Length of this element in the exe_chunk. */ 149 int cmd_len; 150 151 union bnx2x_exe_queue_cmd_data cmd_data; 152}; 153 154union bnx2x_qable_obj; 155 156union bnx2x_exeq_comp_elem { 157 union event_ring_elem *elem; 158}; 159 160struct bnx2x_exe_queue_obj; 161 162typedef int (*exe_q_validate)(struct bnx2x *bp, 163 union bnx2x_qable_obj *o, 164 struct bnx2x_exeq_elem *elem); 165 166typedef int (*exe_q_remove)(struct bnx2x *bp, 167 union bnx2x_qable_obj *o, 168 struct bnx2x_exeq_elem *elem); 169 170/** 171 * @return positive is entry was optimized, 0 - if not, negative 172 * in case of an error. 173 */ 174typedef int (*exe_q_optimize)(struct bnx2x *bp, 175 union bnx2x_qable_obj *o, 176 struct bnx2x_exeq_elem *elem); 177typedef int (*exe_q_execute)(struct bnx2x *bp, 178 union bnx2x_qable_obj *o, 179 struct list_head *exe_chunk, 180 unsigned long *ramrod_flags); 181typedef struct bnx2x_exeq_elem * 182 (*exe_q_get)(struct bnx2x_exe_queue_obj *o, 183 struct bnx2x_exeq_elem *elem); 184 185struct bnx2x_exe_queue_obj { 186 /* 187 * Commands pending for an execution. 188 */ 189 struct list_head exe_queue; 190 191 /* 192 * Commands pending for an completion. 193 */ 194 struct list_head pending_comp; 195 196 spinlock_t lock; 197 198 /* Maximum length of commands' list for one execution */ 199 int exe_chunk_len; 200 201 union bnx2x_qable_obj *owner; 202 203 /****** Virtual functions ******/ 204 /** 205 * Called before commands execution for commands that are really 206 * going to be executed (after 'optimize'). 207 * 208 * Must run under exe_queue->lock 209 */ 210 exe_q_validate validate; 211 212 /** 213 * Called before removing pending commands, cleaning allocated 214 * resources (e.g., credits from validate) 215 */ 216 exe_q_remove remove; 217 218 /** 219 * This will try to cancel the current pending commands list 220 * considering the new command. 221 * 222 * Returns the number of optimized commands or a negative error code 223 * 224 * Must run under exe_queue->lock 225 */ 226 exe_q_optimize optimize; 227 228 /** 229 * Run the next commands chunk (owner specific). 230 */ 231 exe_q_execute execute; 232 233 /** 234 * Return the exe_queue element containing the specific command 235 * if any. Otherwise return NULL. 236 */ 237 exe_q_get get; 238}; 239/***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 240/* 241 * Element in the VLAN_MAC registry list having all currenty configured 242 * rules. 243 */ 244struct bnx2x_vlan_mac_registry_elem { 245 struct list_head link; 246 247 /* 248 * Used to store the cam offset used for the mac/vlan/vlan-mac. 249 * Relevant for 57710 and 57711 only. VLANs and MACs share the 250 * same CAM for these chips. 251 */ 252 int cam_offset; 253 254 /* Needed for DEL and RESTORE flows */ 255 unsigned long vlan_mac_flags; 256 257 union bnx2x_classification_ramrod_data u; 258}; 259 260/* Bits representing VLAN_MAC commands specific flags */ 261enum { 262 BNX2X_UC_LIST_MAC, 263 BNX2X_ETH_MAC, 264 BNX2X_ISCSI_ETH_MAC, 265 BNX2X_NETQ_ETH_MAC, 266 BNX2X_DONT_CONSUME_CAM_CREDIT, 267 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST, 268}; 269 270struct bnx2x_vlan_mac_ramrod_params { 271 /* Object to run the command from */ 272 struct bnx2x_vlan_mac_obj *vlan_mac_obj; 273 274 /* General command flags: COMP_WAIT, etc. */ 275 unsigned long ramrod_flags; 276 277 /* Command specific configuration request */ 278 struct bnx2x_vlan_mac_data user_req; 279}; 280 281struct bnx2x_vlan_mac_obj { 282 struct bnx2x_raw_obj raw; 283 284 /* Bookkeeping list: will prevent the addition of already existing 285 * entries. 286 */ 287 struct list_head head; 288 289 /* TODO: Add it's initialization in the init functions */ 290 struct bnx2x_exe_queue_obj exe_queue; 291 292 /* MACs credit pool */ 293 struct bnx2x_credit_pool_obj *macs_pool; 294 295 /* VLANs credit pool */ 296 struct bnx2x_credit_pool_obj *vlans_pool; 297 298 /* RAMROD command to be used */ 299 int ramrod_cmd; 300 301 /* copy first n elements onto preallocated buffer 302 * 303 * @param n number of elements to get 304 * @param buf buffer preallocated by caller into which elements 305 * will be copied. Note elements are 4-byte aligned 306 * so buffer size must be able to accomodate the 307 * aligned elements. 308 * 309 * @return number of copied bytes 310 */ 311 int (*get_n_elements)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 312 int n, u8 *buf); 313 314 /** 315 * Checks if ADD-ramrod with the given params may be performed. 316 * 317 * @return zero if the element may be added 318 */ 319 320 int (*check_add)(struct bnx2x *bp, 321 struct bnx2x_vlan_mac_obj *o, 322 union bnx2x_classification_ramrod_data *data); 323 324 /** 325 * Checks if DEL-ramrod with the given params may be performed. 326 * 327 * @return true if the element may be deleted 328 */ 329 struct bnx2x_vlan_mac_registry_elem * 330 (*check_del)(struct bnx2x *bp, 331 struct bnx2x_vlan_mac_obj *o, 332 union bnx2x_classification_ramrod_data *data); 333 334 /** 335 * Checks if DEL-ramrod with the given params may be performed. 336 * 337 * @return true if the element may be deleted 338 */ 339 bool (*check_move)(struct bnx2x *bp, 340 struct bnx2x_vlan_mac_obj *src_o, 341 struct bnx2x_vlan_mac_obj *dst_o, 342 union bnx2x_classification_ramrod_data *data); 343 344 /** 345 * Update the relevant credit object(s) (consume/return 346 * correspondingly). 347 */ 348 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o); 349 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o); 350 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset); 351 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset); 352 353 /** 354 * Configures one rule in the ramrod data buffer. 355 */ 356 void (*set_one_rule)(struct bnx2x *bp, 357 struct bnx2x_vlan_mac_obj *o, 358 struct bnx2x_exeq_elem *elem, int rule_idx, 359 int cam_offset); 360 361 /** 362 * Delete all configured elements having the given 363 * vlan_mac_flags specification. Assumes no pending for 364 * execution commands. Will schedule all all currently 365 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 366 * specification for deletion and will use the given 367 * ramrod_flags for the last DEL operation. 368 * 369 * @param bp 370 * @param o 371 * @param ramrod_flags RAMROD_XX flags 372 * 373 * @return 0 if the last operation has completed successfully 374 * and there are no more elements left, positive value 375 * if there are pending for completion commands, 376 * negative value in case of failure. 377 */ 378 int (*delete_all)(struct bnx2x *bp, 379 struct bnx2x_vlan_mac_obj *o, 380 unsigned long *vlan_mac_flags, 381 unsigned long *ramrod_flags); 382 383 /** 384 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 385 * configured elements list. 386 * 387 * @param bp 388 * @param p Command parameters (RAMROD_COMP_WAIT bit in 389 * ramrod_flags is only taken into an account) 390 * @param ppos a pointer to the cooky that should be given back in the 391 * next call to make function handle the next element. If 392 * *ppos is set to NULL it will restart the iterator. 393 * If returned *ppos == NULL this means that the last 394 * element has been handled. 395 * 396 * @return int 397 */ 398 int (*restore)(struct bnx2x *bp, 399 struct bnx2x_vlan_mac_ramrod_params *p, 400 struct bnx2x_vlan_mac_registry_elem **ppos); 401 402 /** 403 * Should be called on a completion arival. 404 * 405 * @param bp 406 * @param o 407 * @param cqe Completion element we are handling 408 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 409 * pending commands will be executed. 410 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 411 * may also be set if needed. 412 * 413 * @return 0 if there are neither pending nor waiting for 414 * completion commands. Positive value if there are 415 * pending for execution or for completion commands. 416 * Negative value in case of an error (including an 417 * error in the cqe). 418 */ 419 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o, 420 union event_ring_elem *cqe, 421 unsigned long *ramrod_flags); 422 423 /** 424 * Wait for completion of all commands. Don't schedule new ones, 425 * just wait. It assumes that the completion code will schedule 426 * for new commands. 427 */ 428 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o); 429}; 430 431enum { 432 BNX2X_LLH_CAM_ISCSI_ETH_LINE = 0, 433 BNX2X_LLH_CAM_ETH_LINE, 434 BNX2X_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 435}; 436 437void bnx2x_set_mac_in_nig(struct bnx2x *bp, 438 bool add, unsigned char *dev_addr, int index); 439 440/** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 441 442/* RX_MODE ramrod spesial flags: set in rx_mode_flags field in 443 * a bnx2x_rx_mode_ramrod_params. 444 */ 445enum { 446 BNX2X_RX_MODE_FCOE_ETH, 447 BNX2X_RX_MODE_ISCSI_ETH, 448}; 449 450enum { 451 BNX2X_ACCEPT_UNICAST, 452 BNX2X_ACCEPT_MULTICAST, 453 BNX2X_ACCEPT_ALL_UNICAST, 454 BNX2X_ACCEPT_ALL_MULTICAST, 455 BNX2X_ACCEPT_BROADCAST, 456 BNX2X_ACCEPT_UNMATCHED, 457 BNX2X_ACCEPT_ANY_VLAN 458}; 459 460struct bnx2x_rx_mode_ramrod_params { 461 struct bnx2x_rx_mode_obj *rx_mode_obj; 462 unsigned long *pstate; 463 int state; 464 u8 cl_id; 465 u32 cid; 466 u8 func_id; 467 unsigned long ramrod_flags; 468 unsigned long rx_mode_flags; 469 470 /* 471 * rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 472 * a tstorm_eth_mac_filter_config (e1x). 473 */ 474 void *rdata; 475 dma_addr_t rdata_mapping; 476 477 /* Rx mode settings */ 478 unsigned long rx_accept_flags; 479 480 /* internal switching settings */ 481 unsigned long tx_accept_flags; 482}; 483 484struct bnx2x_rx_mode_obj { 485 int (*config_rx_mode)(struct bnx2x *bp, 486 struct bnx2x_rx_mode_ramrod_params *p); 487 488 int (*wait_comp)(struct bnx2x *bp, 489 struct bnx2x_rx_mode_ramrod_params *p); 490}; 491 492/********************** Set multicast group ***********************************/ 493 494struct bnx2x_mcast_list_elem { 495 struct list_head link; 496 u8 *mac; 497}; 498 499union bnx2x_mcast_config_data { 500 u8 *mac; 501 u8 bin; /* used in a RESTORE flow */ 502}; 503 504struct bnx2x_mcast_ramrod_params { 505 struct bnx2x_mcast_obj *mcast_obj; 506 507 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 508 unsigned long ramrod_flags; 509 510 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */ 511 /** TODO: 512 * - rename it to macs_num. 513 * - Add a new command type for handling pending commands 514 * (remove "zero semantics"). 515 * 516 * Length of mcast_list. If zero and ADD_CONT command - post 517 * pending commands. 518 */ 519 int mcast_list_len; 520}; 521 522enum { 523 BNX2X_MCAST_CMD_ADD, 524 BNX2X_MCAST_CMD_CONT, 525 BNX2X_MCAST_CMD_DEL, 526 BNX2X_MCAST_CMD_RESTORE, 527}; 528 529struct bnx2x_mcast_obj { 530 struct bnx2x_raw_obj raw; 531 532 union { 533 struct { 534 #define BNX2X_MCAST_BINS_NUM 256 535 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64) 536 u64 vec[BNX2X_MCAST_VEC_SZ]; 537 538 /** Number of BINs to clear. Should be updated 539 * immediately when a command arrives in order to 540 * properly create DEL commands. 541 */ 542 int num_bins_set; 543 } aprox_match; 544 545 struct { 546 struct list_head macs; 547 int num_macs_set; 548 } exact_match; 549 } registry; 550 551 /* Pending commands */ 552 struct list_head pending_cmds_head; 553 554 /* A state that is set in raw.pstate, when there are pending commands */ 555 int sched_state; 556 557 /* Maximal number of mcast MACs configured in one command */ 558 int max_cmd_len; 559 560 /* Total number of currently pending MACs to configure: both 561 * in the pending commands list and in the current command. 562 */ 563 int total_pending_num; 564 565 u8 engine_id; 566 567 /** 568 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above) 569 */ 570 int (*config_mcast)(struct bnx2x *bp, 571 struct bnx2x_mcast_ramrod_params *p, int cmd); 572 573 /** 574 * Fills the ramrod data during the RESTORE flow. 575 * 576 * @param bp 577 * @param o 578 * @param start_idx Registry index to start from 579 * @param rdata_idx Index in the ramrod data to start from 580 * 581 * @return -1 if we handled the whole registry or index of the last 582 * handled registry element. 583 */ 584 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 585 int start_bin, int *rdata_idx); 586 587 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o, 588 struct bnx2x_mcast_ramrod_params *p, int cmd); 589 590 void (*set_one_rule)(struct bnx2x *bp, 591 struct bnx2x_mcast_obj *o, int idx, 592 union bnx2x_mcast_config_data *cfg_data, int cmd); 593 594 /** Checks if there are more mcast MACs to be set or a previous 595 * command is still pending. 596 */ 597 bool (*check_pending)(struct bnx2x_mcast_obj *o); 598 599 /** 600 * Set/Clear/Check SCHEDULED state of the object 601 */ 602 void (*set_sched)(struct bnx2x_mcast_obj *o); 603 void (*clear_sched)(struct bnx2x_mcast_obj *o); 604 bool (*check_sched)(struct bnx2x_mcast_obj *o); 605 606 /* Wait until all pending commands complete */ 607 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o); 608 609 /** 610 * Handle the internal object counters needed for proper 611 * commands handling. Checks that the provided parameters are 612 * feasible. 613 */ 614 int (*validate)(struct bnx2x *bp, 615 struct bnx2x_mcast_ramrod_params *p, int cmd); 616 617 /** 618 * Restore the values of internal counters in case of a failure. 619 */ 620 void (*revert)(struct bnx2x *bp, 621 struct bnx2x_mcast_ramrod_params *p, 622 int old_num_bins); 623 624 int (*get_registry_size)(struct bnx2x_mcast_obj *o); 625 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n); 626}; 627 628/*************************** Credit handling **********************************/ 629struct bnx2x_credit_pool_obj { 630 631 /* Current amount of credit in the pool */ 632 atomic_t credit; 633 634 /* Maximum allowed credit. put() will check against it. */ 635 int pool_sz; 636 637 /* 638 * Allocate a pool table statically. 639 * 640 * Currently the mamimum allowed size is MAX_MAC_CREDIT_E2(272) 641 * 642 * The set bit in the table will mean that the entry is available. 643 */ 644#define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 645 u64 pool_mirror[BNX2X_POOL_VEC_SIZE]; 646 647 /* Base pool offset (initialized differently */ 648 int base_pool_offset; 649 650 /** 651 * Get the next free pool entry. 652 * 653 * @return true if there was a free entry in the pool 654 */ 655 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry); 656 657 /** 658 * Return the entry back to the pool. 659 * 660 * @return true if entry is legal and has been successfully 661 * returned to the pool. 662 */ 663 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry); 664 665 /** 666 * Get the requested amount of credit from the pool. 667 * 668 * @param cnt Amount of requested credit 669 * @return true if the operation is successful 670 */ 671 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt); 672 673 /** 674 * Returns the credit to the pool. 675 * 676 * @param cnt Amount of credit to return 677 * @return true if the operation is successful 678 */ 679 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt); 680 681 /** 682 * Reads the current amount of credit. 683 */ 684 int (*check)(struct bnx2x_credit_pool_obj *o); 685}; 686 687/*************************** RSS configuration ********************************/ 688enum { 689 /* RSS_MODE bits are mutually exclusive */ 690 BNX2X_RSS_MODE_DISABLED, 691 BNX2X_RSS_MODE_REGULAR, 692 693 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 694 695 BNX2X_RSS_IPV4, 696 BNX2X_RSS_IPV4_TCP, 697 BNX2X_RSS_IPV6, 698 BNX2X_RSS_IPV6_TCP, 699}; 700 701struct bnx2x_config_rss_params { 702 struct bnx2x_rss_config_obj *rss_obj; 703 704 /* may have RAMROD_COMP_WAIT set only */ 705 unsigned long ramrod_flags; 706 707 /* BNX2X_RSS_X bits */ 708 unsigned long rss_flags; 709 710 /* Number hash bits to take into an account */ 711 u8 rss_result_mask; 712 713 /* Indirection table */ 714 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 715 716 /* RSS hash values */ 717 u32 rss_key[10]; 718 719 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */ 720 u16 toe_rss_bitmap; 721}; 722 723struct bnx2x_rss_config_obj { 724 struct bnx2x_raw_obj raw; 725 726 /* RSS engine to use */ 727 u8 engine_id; 728 729 /* Last configured indirection table */ 730 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 731 732 int (*config_rss)(struct bnx2x *bp, 733 struct bnx2x_config_rss_params *p); 734}; 735 736/*********************** Queue state update ***********************************/ 737 738/* UPDATE command options */ 739enum { 740 BNX2X_Q_UPDATE_IN_VLAN_REM, 741 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG, 742 BNX2X_Q_UPDATE_OUT_VLAN_REM, 743 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG, 744 BNX2X_Q_UPDATE_ANTI_SPOOF, 745 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG, 746 BNX2X_Q_UPDATE_ACTIVATE, 747 BNX2X_Q_UPDATE_ACTIVATE_CHNG, 748 BNX2X_Q_UPDATE_DEF_VLAN_EN, 749 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG, 750 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG, 751 BNX2X_Q_UPDATE_SILENT_VLAN_REM 752}; 753 754/* Allowed Queue states */ 755enum bnx2x_q_state { 756 BNX2X_Q_STATE_RESET, 757 BNX2X_Q_STATE_INITIALIZED, 758 BNX2X_Q_STATE_ACTIVE, 759 BNX2X_Q_STATE_MULTI_COS, 760 BNX2X_Q_STATE_MCOS_TERMINATED, 761 BNX2X_Q_STATE_INACTIVE, 762 BNX2X_Q_STATE_STOPPED, 763 BNX2X_Q_STATE_TERMINATED, 764 BNX2X_Q_STATE_FLRED, 765 BNX2X_Q_STATE_MAX, 766}; 767 768/* Allowed commands */ 769enum bnx2x_queue_cmd { 770 BNX2X_Q_CMD_INIT, 771 BNX2X_Q_CMD_SETUP, 772 BNX2X_Q_CMD_SETUP_TX_ONLY, 773 BNX2X_Q_CMD_DEACTIVATE, 774 BNX2X_Q_CMD_ACTIVATE, 775 BNX2X_Q_CMD_UPDATE, 776 BNX2X_Q_CMD_UPDATE_TPA, 777 BNX2X_Q_CMD_HALT, 778 BNX2X_Q_CMD_CFC_DEL, 779 BNX2X_Q_CMD_TERMINATE, 780 BNX2X_Q_CMD_EMPTY, 781 BNX2X_Q_CMD_MAX, 782}; 783 784/* queue SETUP + INIT flags */ 785enum { 786 BNX2X_Q_FLG_TPA, 787 BNX2X_Q_FLG_TPA_IPV6, 788 BNX2X_Q_FLG_TPA_GRO, 789 BNX2X_Q_FLG_STATS, 790 BNX2X_Q_FLG_ZERO_STATS, 791 BNX2X_Q_FLG_ACTIVE, 792 BNX2X_Q_FLG_OV, 793 BNX2X_Q_FLG_VLAN, 794 BNX2X_Q_FLG_COS, 795 BNX2X_Q_FLG_HC, 796 BNX2X_Q_FLG_HC_EN, 797 BNX2X_Q_FLG_DHC, 798 BNX2X_Q_FLG_FCOE, 799 BNX2X_Q_FLG_LEADING_RSS, 800 BNX2X_Q_FLG_MCAST, 801 BNX2X_Q_FLG_DEF_VLAN, 802 BNX2X_Q_FLG_TX_SWITCH, 803 BNX2X_Q_FLG_TX_SEC, 804 BNX2X_Q_FLG_ANTI_SPOOF, 805 BNX2X_Q_FLG_SILENT_VLAN_REM, 806 BNX2X_Q_FLG_FORCE_DEFAULT_PRI 807}; 808 809/* Queue type options: queue type may be a compination of below. */ 810enum bnx2x_q_type { 811 /** TODO: Consider moving both these flags into the init() 812 * ramrod params. 813 */ 814 BNX2X_Q_TYPE_HAS_RX, 815 BNX2X_Q_TYPE_HAS_TX, 816}; 817 818#define BNX2X_PRIMARY_CID_INDEX 0 819#define BNX2X_MULTI_TX_COS_E1X 3 /* QM only */ 820#define BNX2X_MULTI_TX_COS_E2_E3A0 2 821#define BNX2X_MULTI_TX_COS_E3B0 3 822#define BNX2X_MULTI_TX_COS 3 /* Maximum possible */ 823 824 825struct bnx2x_queue_init_params { 826 struct { 827 unsigned long flags; 828 u16 hc_rate; 829 u8 fw_sb_id; 830 u8 sb_cq_index; 831 } tx; 832 833 struct { 834 unsigned long flags; 835 u16 hc_rate; 836 u8 fw_sb_id; 837 u8 sb_cq_index; 838 } rx; 839 840 /* CID context in the host memory */ 841 struct eth_context *cxts[BNX2X_MULTI_TX_COS]; 842 843 /* maximum number of cos supported by hardware */ 844 u8 max_cos; 845}; 846 847struct bnx2x_queue_terminate_params { 848 /* index within the tx_only cids of this queue object */ 849 u8 cid_index; 850}; 851 852struct bnx2x_queue_cfc_del_params { 853 /* index within the tx_only cids of this queue object */ 854 u8 cid_index; 855}; 856 857struct bnx2x_queue_update_params { 858 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */ 859 u16 def_vlan; 860 u16 silent_removal_value; 861 u16 silent_removal_mask; 862/* index within the tx_only cids of this queue object */ 863 u8 cid_index; 864}; 865 866struct rxq_pause_params { 867 u16 bd_th_lo; 868 u16 bd_th_hi; 869 u16 rcq_th_lo; 870 u16 rcq_th_hi; 871 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */ 872 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */ 873 u16 pri_map; 874}; 875 876/* general */ 877struct bnx2x_general_setup_params { 878 /* valid iff BNX2X_Q_FLG_STATS */ 879 u8 stat_id; 880 881 u8 spcl_id; 882 u16 mtu; 883 u8 cos; 884}; 885 886struct bnx2x_rxq_setup_params { 887 /* dma */ 888 dma_addr_t dscr_map; 889 dma_addr_t sge_map; 890 dma_addr_t rcq_map; 891 dma_addr_t rcq_np_map; 892 893 u16 drop_flags; 894 u16 buf_sz; 895 u8 fw_sb_id; 896 u8 cl_qzone_id; 897 898 /* valid iff BNX2X_Q_FLG_TPA */ 899 u16 tpa_agg_sz; 900 u16 sge_buf_sz; 901 u8 max_sges_pkt; 902 u8 max_tpa_queues; 903 u8 rss_engine_id; 904 905 /* valid iff BNX2X_Q_FLG_MCAST */ 906 u8 mcast_engine_id; 907 908 u8 cache_line_log; 909 910 u8 sb_cq_index; 911 912 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 913 u16 silent_removal_value; 914 u16 silent_removal_mask; 915}; 916 917struct bnx2x_txq_setup_params { 918 /* dma */ 919 dma_addr_t dscr_map; 920 921 u8 fw_sb_id; 922 u8 sb_cq_index; 923 u8 cos; /* valid iff BNX2X_Q_FLG_COS */ 924 u16 traffic_type; 925 /* equals to the leading rss client id, used for TX classification*/ 926 u8 tss_leading_cl_id; 927 928 /* valid iff BNX2X_Q_FLG_DEF_VLAN */ 929 u16 default_vlan; 930}; 931 932struct bnx2x_queue_setup_params { 933 struct bnx2x_general_setup_params gen_params; 934 struct bnx2x_txq_setup_params txq_params; 935 struct bnx2x_rxq_setup_params rxq_params; 936 struct rxq_pause_params pause_params; 937 unsigned long flags; 938}; 939 940struct bnx2x_queue_setup_tx_only_params { 941 struct bnx2x_general_setup_params gen_params; 942 struct bnx2x_txq_setup_params txq_params; 943 unsigned long flags; 944 /* index within the tx_only cids of this queue object */ 945 u8 cid_index; 946}; 947 948struct bnx2x_queue_state_params { 949 struct bnx2x_queue_sp_obj *q_obj; 950 951 /* Current command */ 952 enum bnx2x_queue_cmd cmd; 953 954 /* may have RAMROD_COMP_WAIT set only */ 955 unsigned long ramrod_flags; 956 957 /* Params according to the current command */ 958 union { 959 struct bnx2x_queue_update_params update; 960 struct bnx2x_queue_setup_params setup; 961 struct bnx2x_queue_init_params init; 962 struct bnx2x_queue_setup_tx_only_params tx_only; 963 struct bnx2x_queue_terminate_params terminate; 964 struct bnx2x_queue_cfc_del_params cfc_del; 965 } params; 966}; 967 968struct bnx2x_viflist_params { 969 u8 echo_res; 970 u8 func_bit_map_res; 971}; 972 973struct bnx2x_queue_sp_obj { 974 u32 cids[BNX2X_MULTI_TX_COS]; 975 u8 cl_id; 976 u8 func_id; 977 978 /* 979 * number of traffic classes supported by queue. 980 * The primary connection of the queue suppotrs the first traffic 981 * class. Any further traffic class is suppoted by a tx-only 982 * connection. 983 * 984 * Therefore max_cos is also a number of valid entries in the cids 985 * array. 986 */ 987 u8 max_cos; 988 u8 num_tx_only, next_tx_only; 989 990 enum bnx2x_q_state state, next_state; 991 992 /* bits from enum bnx2x_q_type */ 993 unsigned long type; 994 995 /* BNX2X_Q_CMD_XX bits. This object implements "one 996 * pending" paradigm but for debug and tracing purposes it's 997 * more convinient to have different bits for different 998 * commands. 999 */ 1000 unsigned long pending; 1001 1002 /* Buffer to use as a ramrod data and its mapping */ 1003 void *rdata; 1004 dma_addr_t rdata_mapping; 1005 1006 /** 1007 * Performs one state change according to the given parameters. 1008 * 1009 * @return 0 in case of success and negative value otherwise. 1010 */ 1011 int (*send_cmd)(struct bnx2x *bp, 1012 struct bnx2x_queue_state_params *params); 1013 1014 /** 1015 * Sets the pending bit according to the requested transition. 1016 */ 1017 int (*set_pending)(struct bnx2x_queue_sp_obj *o, 1018 struct bnx2x_queue_state_params *params); 1019 1020 /** 1021 * Checks that the requested state transition is legal. 1022 */ 1023 int (*check_transition)(struct bnx2x *bp, 1024 struct bnx2x_queue_sp_obj *o, 1025 struct bnx2x_queue_state_params *params); 1026 1027 /** 1028 * Completes the pending command. 1029 */ 1030 int (*complete_cmd)(struct bnx2x *bp, 1031 struct bnx2x_queue_sp_obj *o, 1032 enum bnx2x_queue_cmd); 1033 1034 int (*wait_comp)(struct bnx2x *bp, 1035 struct bnx2x_queue_sp_obj *o, 1036 enum bnx2x_queue_cmd cmd); 1037}; 1038 1039/********************** Function state update *********************************/ 1040/* Allowed Function states */ 1041enum bnx2x_func_state { 1042 BNX2X_F_STATE_RESET, 1043 BNX2X_F_STATE_INITIALIZED, 1044 BNX2X_F_STATE_STARTED, 1045 BNX2X_F_STATE_TX_STOPPED, 1046 BNX2X_F_STATE_MAX, 1047}; 1048 1049/* Allowed Function commands */ 1050enum bnx2x_func_cmd { 1051 BNX2X_F_CMD_HW_INIT, 1052 BNX2X_F_CMD_START, 1053 BNX2X_F_CMD_STOP, 1054 BNX2X_F_CMD_HW_RESET, 1055 BNX2X_F_CMD_AFEX_UPDATE, 1056 BNX2X_F_CMD_AFEX_VIFLISTS, 1057 BNX2X_F_CMD_TX_STOP, 1058 BNX2X_F_CMD_TX_START, 1059 BNX2X_F_CMD_MAX, 1060}; 1061 1062struct bnx2x_func_hw_init_params { 1063 /* A load phase returned by MCP. 1064 * 1065 * May be: 1066 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1067 * FW_MSG_CODE_DRV_LOAD_COMMON 1068 * FW_MSG_CODE_DRV_LOAD_PORT 1069 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1070 */ 1071 u32 load_phase; 1072}; 1073 1074struct bnx2x_func_hw_reset_params { 1075 /* A load phase returned by MCP. 1076 * 1077 * May be: 1078 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1079 * FW_MSG_CODE_DRV_LOAD_COMMON 1080 * FW_MSG_CODE_DRV_LOAD_PORT 1081 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1082 */ 1083 u32 reset_phase; 1084}; 1085 1086struct bnx2x_func_start_params { 1087 /* Multi Function mode: 1088 * - Single Function 1089 * - Switch Dependent 1090 * - Switch Independent 1091 */ 1092 u16 mf_mode; 1093 1094 /* Switch Dependent mode outer VLAN tag */ 1095 u16 sd_vlan_tag; 1096 1097 /* Function cos mode */ 1098 u8 network_cos_mode; 1099}; 1100 1101struct bnx2x_func_afex_update_params { 1102 u16 vif_id; 1103 u16 afex_default_vlan; 1104 u8 allowed_priorities; 1105}; 1106 1107struct bnx2x_func_afex_viflists_params { 1108 u16 vif_list_index; 1109 u8 func_bit_map; 1110 u8 afex_vif_list_command; 1111 u8 func_to_clear; 1112}; 1113struct bnx2x_func_tx_start_params { 1114 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1115 u8 dcb_enabled; 1116 u8 dcb_version; 1117 u8 dont_add_pri_0_en; 1118}; 1119 1120struct bnx2x_func_state_params { 1121 struct bnx2x_func_sp_obj *f_obj; 1122 1123 /* Current command */ 1124 enum bnx2x_func_cmd cmd; 1125 1126 /* may have RAMROD_COMP_WAIT set only */ 1127 unsigned long ramrod_flags; 1128 1129 /* Params according to the current command */ 1130 union { 1131 struct bnx2x_func_hw_init_params hw_init; 1132 struct bnx2x_func_hw_reset_params hw_reset; 1133 struct bnx2x_func_start_params start; 1134 struct bnx2x_func_afex_update_params afex_update; 1135 struct bnx2x_func_afex_viflists_params afex_viflists; 1136 struct bnx2x_func_tx_start_params tx_start; 1137 } params; 1138}; 1139 1140struct bnx2x_func_sp_drv_ops { 1141 /* Init tool + runtime initialization: 1142 * - Common Chip 1143 * - Common (per Path) 1144 * - Port 1145 * - Function phases 1146 */ 1147 int (*init_hw_cmn_chip)(struct bnx2x *bp); 1148 int (*init_hw_cmn)(struct bnx2x *bp); 1149 int (*init_hw_port)(struct bnx2x *bp); 1150 int (*init_hw_func)(struct bnx2x *bp); 1151 1152 /* Reset Function HW: Common, Port, Function phases. */ 1153 void (*reset_hw_cmn)(struct bnx2x *bp); 1154 void (*reset_hw_port)(struct bnx2x *bp); 1155 void (*reset_hw_func)(struct bnx2x *bp); 1156 1157 /* Init/Free GUNZIP resources */ 1158 int (*gunzip_init)(struct bnx2x *bp); 1159 void (*gunzip_end)(struct bnx2x *bp); 1160 1161 /* Prepare/Release FW resources */ 1162 int (*init_fw)(struct bnx2x *bp); 1163 void (*release_fw)(struct bnx2x *bp); 1164}; 1165 1166struct bnx2x_func_sp_obj { 1167 enum bnx2x_func_state state, next_state; 1168 1169 /* BNX2X_FUNC_CMD_XX bits. This object implements "one 1170 * pending" paradigm but for debug and tracing purposes it's 1171 * more convinient to have different bits for different 1172 * commands. 1173 */ 1174 unsigned long pending; 1175 1176 /* Buffer to use as a ramrod data and its mapping */ 1177 void *rdata; 1178 dma_addr_t rdata_mapping; 1179 1180 /* Buffer to use as a afex ramrod data and its mapping. 1181 * This can't be same rdata as above because afex ramrod requests 1182 * can arrive to the object in parallel to other ramrod requests. 1183 */ 1184 void *afex_rdata; 1185 dma_addr_t afex_rdata_mapping; 1186 1187 /* this mutex validates that when pending flag is taken, the next 1188 * ramrod to be sent will be the one set the pending bit 1189 */ 1190 struct mutex one_pending_mutex; 1191 1192 /* Driver interface */ 1193 struct bnx2x_func_sp_drv_ops *drv; 1194 1195 /** 1196 * Performs one state change according to the given parameters. 1197 * 1198 * @return 0 in case of success and negative value otherwise. 1199 */ 1200 int (*send_cmd)(struct bnx2x *bp, 1201 struct bnx2x_func_state_params *params); 1202 1203 /** 1204 * Checks that the requested state transition is legal. 1205 */ 1206 int (*check_transition)(struct bnx2x *bp, 1207 struct bnx2x_func_sp_obj *o, 1208 struct bnx2x_func_state_params *params); 1209 1210 /** 1211 * Completes the pending command. 1212 */ 1213 int (*complete_cmd)(struct bnx2x *bp, 1214 struct bnx2x_func_sp_obj *o, 1215 enum bnx2x_func_cmd cmd); 1216 1217 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o, 1218 enum bnx2x_func_cmd cmd); 1219}; 1220 1221/********************** Interfaces ********************************************/ 1222/* Queueable objects set */ 1223union bnx2x_qable_obj { 1224 struct bnx2x_vlan_mac_obj vlan_mac; 1225}; 1226/************** Function state update *********/ 1227void bnx2x_init_func_obj(struct bnx2x *bp, 1228 struct bnx2x_func_sp_obj *obj, 1229 void *rdata, dma_addr_t rdata_mapping, 1230 void *afex_rdata, dma_addr_t afex_rdata_mapping, 1231 struct bnx2x_func_sp_drv_ops *drv_iface); 1232 1233int bnx2x_func_state_change(struct bnx2x *bp, 1234 struct bnx2x_func_state_params *params); 1235 1236enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp, 1237 struct bnx2x_func_sp_obj *o); 1238/******************* Queue State **************/ 1239void bnx2x_init_queue_obj(struct bnx2x *bp, 1240 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids, 1241 u8 cid_cnt, u8 func_id, void *rdata, 1242 dma_addr_t rdata_mapping, unsigned long type); 1243 1244int bnx2x_queue_state_change(struct bnx2x *bp, 1245 struct bnx2x_queue_state_params *params); 1246 1247/********************* VLAN-MAC ****************/ 1248void bnx2x_init_mac_obj(struct bnx2x *bp, 1249 struct bnx2x_vlan_mac_obj *mac_obj, 1250 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1251 dma_addr_t rdata_mapping, int state, 1252 unsigned long *pstate, bnx2x_obj_type type, 1253 struct bnx2x_credit_pool_obj *macs_pool); 1254 1255void bnx2x_init_vlan_obj(struct bnx2x *bp, 1256 struct bnx2x_vlan_mac_obj *vlan_obj, 1257 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1258 dma_addr_t rdata_mapping, int state, 1259 unsigned long *pstate, bnx2x_obj_type type, 1260 struct bnx2x_credit_pool_obj *vlans_pool); 1261 1262void bnx2x_init_vlan_mac_obj(struct bnx2x *bp, 1263 struct bnx2x_vlan_mac_obj *vlan_mac_obj, 1264 u8 cl_id, u32 cid, u8 func_id, void *rdata, 1265 dma_addr_t rdata_mapping, int state, 1266 unsigned long *pstate, bnx2x_obj_type type, 1267 struct bnx2x_credit_pool_obj *macs_pool, 1268 struct bnx2x_credit_pool_obj *vlans_pool); 1269 1270int bnx2x_config_vlan_mac(struct bnx2x *bp, 1271 struct bnx2x_vlan_mac_ramrod_params *p); 1272 1273int bnx2x_vlan_mac_move(struct bnx2x *bp, 1274 struct bnx2x_vlan_mac_ramrod_params *p, 1275 struct bnx2x_vlan_mac_obj *dest_o); 1276 1277/********************* RX MODE ****************/ 1278 1279void bnx2x_init_rx_mode_obj(struct bnx2x *bp, 1280 struct bnx2x_rx_mode_obj *o); 1281 1282/** 1283 * Send and RX_MODE ramrod according to the provided parameters. 1284 * 1285 * @param bp 1286 * @param p Command parameters 1287 * 1288 * @return 0 - if operation was successfull and there is no pending completions, 1289 * positive number - if there are pending completions, 1290 * negative - if there were errors 1291 */ 1292int bnx2x_config_rx_mode(struct bnx2x *bp, 1293 struct bnx2x_rx_mode_ramrod_params *p); 1294 1295/****************** MULTICASTS ****************/ 1296 1297void bnx2x_init_mcast_obj(struct bnx2x *bp, 1298 struct bnx2x_mcast_obj *mcast_obj, 1299 u8 mcast_cl_id, u32 mcast_cid, u8 func_id, 1300 u8 engine_id, void *rdata, dma_addr_t rdata_mapping, 1301 int state, unsigned long *pstate, 1302 bnx2x_obj_type type); 1303 1304/** 1305 * Configure multicast MACs list. May configure a new list 1306 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up 1307 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current 1308 * configuration, continue to execute the pending commands 1309 * (BNX2X_MCAST_CMD_CONT). 1310 * 1311 * If previous command is still pending or if number of MACs to 1312 * configure is more that maximum number of MACs in one command, 1313 * the current command will be enqueued to the tail of the 1314 * pending commands list. 1315 * 1316 * @param bp 1317 * @param p 1318 * @param command to execute: BNX2X_MCAST_CMD_X 1319 * 1320 * @return 0 is operation was sucessfull and there are no pending completions, 1321 * negative if there were errors, positive if there are pending 1322 * completions. 1323 */ 1324int bnx2x_config_mcast(struct bnx2x *bp, 1325 struct bnx2x_mcast_ramrod_params *p, int cmd); 1326 1327/****************** CREDIT POOL ****************/ 1328void bnx2x_init_mac_credit_pool(struct bnx2x *bp, 1329 struct bnx2x_credit_pool_obj *p, u8 func_id, 1330 u8 func_num); 1331void bnx2x_init_vlan_credit_pool(struct bnx2x *bp, 1332 struct bnx2x_credit_pool_obj *p, u8 func_id, 1333 u8 func_num); 1334 1335 1336/****************** RSS CONFIGURATION ****************/ 1337void bnx2x_init_rss_config_obj(struct bnx2x *bp, 1338 struct bnx2x_rss_config_obj *rss_obj, 1339 u8 cl_id, u32 cid, u8 func_id, u8 engine_id, 1340 void *rdata, dma_addr_t rdata_mapping, 1341 int state, unsigned long *pstate, 1342 bnx2x_obj_type type); 1343 1344/** 1345 * Updates RSS configuration according to provided parameters. 1346 * 1347 * @param bp 1348 * @param p 1349 * 1350 * @return 0 in case of success 1351 */ 1352int bnx2x_config_rss(struct bnx2x *bp, 1353 struct bnx2x_config_rss_params *p); 1354 1355/** 1356 * Return the current ind_table configuration. 1357 * 1358 * @param bp 1359 * @param ind_table buffer to fill with the current indirection 1360 * table content. Should be at least 1361 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1362 */ 1363void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj, 1364 u8 *ind_table); 1365 1366#endif /* BNX2X_SP_VERBS */ 1367