bcmgenet.c revision 98bb7399d29a53a58f497409f98acb3bc0434ded
1/* 2 * Broadcom GENET (Gigabit Ethernet) controller driver 3 * 4 * Copyright (c) 2014 Broadcom Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10 11#define pr_fmt(fmt) "bcmgenet: " fmt 12 13#include <linux/kernel.h> 14#include <linux/module.h> 15#include <linux/sched.h> 16#include <linux/types.h> 17#include <linux/fcntl.h> 18#include <linux/interrupt.h> 19#include <linux/string.h> 20#include <linux/if_ether.h> 21#include <linux/init.h> 22#include <linux/errno.h> 23#include <linux/delay.h> 24#include <linux/platform_device.h> 25#include <linux/dma-mapping.h> 26#include <linux/pm.h> 27#include <linux/clk.h> 28#include <linux/of.h> 29#include <linux/of_address.h> 30#include <linux/of_irq.h> 31#include <linux/of_net.h> 32#include <linux/of_platform.h> 33#include <net/arp.h> 34 35#include <linux/mii.h> 36#include <linux/ethtool.h> 37#include <linux/netdevice.h> 38#include <linux/inetdevice.h> 39#include <linux/etherdevice.h> 40#include <linux/skbuff.h> 41#include <linux/in.h> 42#include <linux/ip.h> 43#include <linux/ipv6.h> 44#include <linux/phy.h> 45 46#include <asm/unaligned.h> 47 48#include "bcmgenet.h" 49 50/* Maximum number of hardware queues, downsized if needed */ 51#define GENET_MAX_MQ_CNT 4 52 53/* Default highest priority queue for multi queue support */ 54#define GENET_Q0_PRIORITY 0 55 56#define GENET_DEFAULT_BD_CNT \ 57 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt) 58 59#define RX_BUF_LENGTH 2048 60#define SKB_ALIGNMENT 32 61 62/* Tx/Rx DMA register offset, skip 256 descriptors */ 63#define WORDS_PER_BD(p) (p->hw_params->words_per_bd) 64#define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32)) 65 66#define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \ 67 TOTAL_DESC * DMA_DESC_SIZE) 68 69#define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \ 70 TOTAL_DESC * DMA_DESC_SIZE) 71 72static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv, 73 void __iomem *d, u32 value) 74{ 75 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS); 76} 77 78static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv, 79 void __iomem *d) 80{ 81 return __raw_readl(d + DMA_DESC_LENGTH_STATUS); 82} 83 84static inline void dmadesc_set_addr(struct bcmgenet_priv *priv, 85 void __iomem *d, 86 dma_addr_t addr) 87{ 88 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO); 89 90 /* Register writes to GISB bus can take couple hundred nanoseconds 91 * and are done for each packet, save these expensive writes unless 92 * the platform is explicitly configured for 64-bits/LPAE. 93 */ 94#ifdef CONFIG_PHYS_ADDR_T_64BIT 95 if (priv->hw_params->flags & GENET_HAS_40BITS) 96 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI); 97#endif 98} 99 100/* Combined address + length/status setter */ 101static inline void dmadesc_set(struct bcmgenet_priv *priv, 102 void __iomem *d, dma_addr_t addr, u32 val) 103{ 104 dmadesc_set_length_status(priv, d, val); 105 dmadesc_set_addr(priv, d, addr); 106} 107 108static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv, 109 void __iomem *d) 110{ 111 dma_addr_t addr; 112 113 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO); 114 115 /* Register writes to GISB bus can take couple hundred nanoseconds 116 * and are done for each packet, save these expensive writes unless 117 * the platform is explicitly configured for 64-bits/LPAE. 118 */ 119#ifdef CONFIG_PHYS_ADDR_T_64BIT 120 if (priv->hw_params->flags & GENET_HAS_40BITS) 121 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32; 122#endif 123 return addr; 124} 125 126#define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x" 127 128#define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \ 129 NETIF_MSG_LINK) 130 131static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv) 132{ 133 if (GENET_IS_V1(priv)) 134 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1); 135 else 136 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL); 137} 138 139static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 140{ 141 if (GENET_IS_V1(priv)) 142 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1); 143 else 144 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL); 145} 146 147/* These macros are defined to deal with register map change 148 * between GENET1.1 and GENET2. Only those currently being used 149 * by driver are defined. 150 */ 151static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv) 152{ 153 if (GENET_IS_V1(priv)) 154 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1); 155 else 156 return __raw_readl(priv->base + 157 priv->hw_params->tbuf_offset + TBUF_CTRL); 158} 159 160static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val) 161{ 162 if (GENET_IS_V1(priv)) 163 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1); 164 else 165 __raw_writel(val, priv->base + 166 priv->hw_params->tbuf_offset + TBUF_CTRL); 167} 168 169static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv) 170{ 171 if (GENET_IS_V1(priv)) 172 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1); 173 else 174 return __raw_readl(priv->base + 175 priv->hw_params->tbuf_offset + TBUF_BP_MC); 176} 177 178static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val) 179{ 180 if (GENET_IS_V1(priv)) 181 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1); 182 else 183 __raw_writel(val, priv->base + 184 priv->hw_params->tbuf_offset + TBUF_BP_MC); 185} 186 187/* RX/TX DMA register accessors */ 188enum dma_reg { 189 DMA_RING_CFG = 0, 190 DMA_CTRL, 191 DMA_STATUS, 192 DMA_SCB_BURST_SIZE, 193 DMA_ARB_CTRL, 194 DMA_PRIORITY, 195 DMA_RING_PRIORITY, 196}; 197 198static const u8 bcmgenet_dma_regs_v3plus[] = { 199 [DMA_RING_CFG] = 0x00, 200 [DMA_CTRL] = 0x04, 201 [DMA_STATUS] = 0x08, 202 [DMA_SCB_BURST_SIZE] = 0x0C, 203 [DMA_ARB_CTRL] = 0x2C, 204 [DMA_PRIORITY] = 0x30, 205 [DMA_RING_PRIORITY] = 0x38, 206}; 207 208static const u8 bcmgenet_dma_regs_v2[] = { 209 [DMA_RING_CFG] = 0x00, 210 [DMA_CTRL] = 0x04, 211 [DMA_STATUS] = 0x08, 212 [DMA_SCB_BURST_SIZE] = 0x0C, 213 [DMA_ARB_CTRL] = 0x30, 214 [DMA_PRIORITY] = 0x34, 215 [DMA_RING_PRIORITY] = 0x3C, 216}; 217 218static const u8 bcmgenet_dma_regs_v1[] = { 219 [DMA_CTRL] = 0x00, 220 [DMA_STATUS] = 0x04, 221 [DMA_SCB_BURST_SIZE] = 0x0C, 222 [DMA_ARB_CTRL] = 0x30, 223 [DMA_PRIORITY] = 0x34, 224 [DMA_RING_PRIORITY] = 0x3C, 225}; 226 227/* Set at runtime once bcmgenet version is known */ 228static const u8 *bcmgenet_dma_regs; 229 230static inline struct bcmgenet_priv *dev_to_priv(struct device *dev) 231{ 232 return netdev_priv(dev_get_drvdata(dev)); 233} 234 235static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv, 236 enum dma_reg r) 237{ 238 return __raw_readl(priv->base + GENET_TDMA_REG_OFF + 239 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 240} 241 242static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv, 243 u32 val, enum dma_reg r) 244{ 245 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF + 246 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 247} 248 249static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv, 250 enum dma_reg r) 251{ 252 return __raw_readl(priv->base + GENET_RDMA_REG_OFF + 253 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 254} 255 256static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv, 257 u32 val, enum dma_reg r) 258{ 259 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF + 260 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]); 261} 262 263/* RDMA/TDMA ring registers and accessors 264 * we merge the common fields and just prefix with T/D the registers 265 * having different meaning depending on the direction 266 */ 267enum dma_ring_reg { 268 TDMA_READ_PTR = 0, 269 RDMA_WRITE_PTR = TDMA_READ_PTR, 270 TDMA_READ_PTR_HI, 271 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI, 272 TDMA_CONS_INDEX, 273 RDMA_PROD_INDEX = TDMA_CONS_INDEX, 274 TDMA_PROD_INDEX, 275 RDMA_CONS_INDEX = TDMA_PROD_INDEX, 276 DMA_RING_BUF_SIZE, 277 DMA_START_ADDR, 278 DMA_START_ADDR_HI, 279 DMA_END_ADDR, 280 DMA_END_ADDR_HI, 281 DMA_MBUF_DONE_THRESH, 282 TDMA_FLOW_PERIOD, 283 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD, 284 TDMA_WRITE_PTR, 285 RDMA_READ_PTR = TDMA_WRITE_PTR, 286 TDMA_WRITE_PTR_HI, 287 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI 288}; 289 290/* GENET v4 supports 40-bits pointer addressing 291 * for obvious reasons the LO and HI word parts 292 * are contiguous, but this offsets the other 293 * registers. 294 */ 295static const u8 genet_dma_ring_regs_v4[] = { 296 [TDMA_READ_PTR] = 0x00, 297 [TDMA_READ_PTR_HI] = 0x04, 298 [TDMA_CONS_INDEX] = 0x08, 299 [TDMA_PROD_INDEX] = 0x0C, 300 [DMA_RING_BUF_SIZE] = 0x10, 301 [DMA_START_ADDR] = 0x14, 302 [DMA_START_ADDR_HI] = 0x18, 303 [DMA_END_ADDR] = 0x1C, 304 [DMA_END_ADDR_HI] = 0x20, 305 [DMA_MBUF_DONE_THRESH] = 0x24, 306 [TDMA_FLOW_PERIOD] = 0x28, 307 [TDMA_WRITE_PTR] = 0x2C, 308 [TDMA_WRITE_PTR_HI] = 0x30, 309}; 310 311static const u8 genet_dma_ring_regs_v123[] = { 312 [TDMA_READ_PTR] = 0x00, 313 [TDMA_CONS_INDEX] = 0x04, 314 [TDMA_PROD_INDEX] = 0x08, 315 [DMA_RING_BUF_SIZE] = 0x0C, 316 [DMA_START_ADDR] = 0x10, 317 [DMA_END_ADDR] = 0x14, 318 [DMA_MBUF_DONE_THRESH] = 0x18, 319 [TDMA_FLOW_PERIOD] = 0x1C, 320 [TDMA_WRITE_PTR] = 0x20, 321}; 322 323/* Set at runtime once GENET version is known */ 324static const u8 *genet_dma_ring_regs; 325 326static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv, 327 unsigned int ring, 328 enum dma_ring_reg r) 329{ 330 return __raw_readl(priv->base + GENET_TDMA_REG_OFF + 331 (DMA_RING_SIZE * ring) + 332 genet_dma_ring_regs[r]); 333} 334 335static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv, 336 unsigned int ring, u32 val, 337 enum dma_ring_reg r) 338{ 339 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF + 340 (DMA_RING_SIZE * ring) + 341 genet_dma_ring_regs[r]); 342} 343 344static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv, 345 unsigned int ring, 346 enum dma_ring_reg r) 347{ 348 return __raw_readl(priv->base + GENET_RDMA_REG_OFF + 349 (DMA_RING_SIZE * ring) + 350 genet_dma_ring_regs[r]); 351} 352 353static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv, 354 unsigned int ring, u32 val, 355 enum dma_ring_reg r) 356{ 357 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF + 358 (DMA_RING_SIZE * ring) + 359 genet_dma_ring_regs[r]); 360} 361 362static int bcmgenet_get_settings(struct net_device *dev, 363 struct ethtool_cmd *cmd) 364{ 365 struct bcmgenet_priv *priv = netdev_priv(dev); 366 367 if (!netif_running(dev)) 368 return -EINVAL; 369 370 if (!priv->phydev) 371 return -ENODEV; 372 373 return phy_ethtool_gset(priv->phydev, cmd); 374} 375 376static int bcmgenet_set_settings(struct net_device *dev, 377 struct ethtool_cmd *cmd) 378{ 379 struct bcmgenet_priv *priv = netdev_priv(dev); 380 381 if (!netif_running(dev)) 382 return -EINVAL; 383 384 if (!priv->phydev) 385 return -ENODEV; 386 387 return phy_ethtool_sset(priv->phydev, cmd); 388} 389 390static int bcmgenet_set_rx_csum(struct net_device *dev, 391 netdev_features_t wanted) 392{ 393 struct bcmgenet_priv *priv = netdev_priv(dev); 394 u32 rbuf_chk_ctrl; 395 bool rx_csum_en; 396 397 rx_csum_en = !!(wanted & NETIF_F_RXCSUM); 398 399 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL); 400 401 /* enable rx checksumming */ 402 if (rx_csum_en) 403 rbuf_chk_ctrl |= RBUF_RXCHK_EN; 404 else 405 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN; 406 priv->desc_rxchk_en = rx_csum_en; 407 408 /* If UniMAC forwards CRC, we need to skip over it to get 409 * a valid CHK bit to be set in the per-packet status word 410 */ 411 if (rx_csum_en && priv->crc_fwd_en) 412 rbuf_chk_ctrl |= RBUF_SKIP_FCS; 413 else 414 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS; 415 416 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL); 417 418 return 0; 419} 420 421static int bcmgenet_set_tx_csum(struct net_device *dev, 422 netdev_features_t wanted) 423{ 424 struct bcmgenet_priv *priv = netdev_priv(dev); 425 bool desc_64b_en; 426 u32 tbuf_ctrl, rbuf_ctrl; 427 428 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv); 429 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 430 431 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)); 432 433 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */ 434 if (desc_64b_en) { 435 tbuf_ctrl |= RBUF_64B_EN; 436 rbuf_ctrl |= RBUF_64B_EN; 437 } else { 438 tbuf_ctrl &= ~RBUF_64B_EN; 439 rbuf_ctrl &= ~RBUF_64B_EN; 440 } 441 priv->desc_64b_en = desc_64b_en; 442 443 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl); 444 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL); 445 446 return 0; 447} 448 449static int bcmgenet_set_features(struct net_device *dev, 450 netdev_features_t features) 451{ 452 netdev_features_t changed = features ^ dev->features; 453 netdev_features_t wanted = dev->wanted_features; 454 int ret = 0; 455 456 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM)) 457 ret = bcmgenet_set_tx_csum(dev, wanted); 458 if (changed & (NETIF_F_RXCSUM)) 459 ret = bcmgenet_set_rx_csum(dev, wanted); 460 461 return ret; 462} 463 464static u32 bcmgenet_get_msglevel(struct net_device *dev) 465{ 466 struct bcmgenet_priv *priv = netdev_priv(dev); 467 468 return priv->msg_enable; 469} 470 471static void bcmgenet_set_msglevel(struct net_device *dev, u32 level) 472{ 473 struct bcmgenet_priv *priv = netdev_priv(dev); 474 475 priv->msg_enable = level; 476} 477 478/* standard ethtool support functions. */ 479enum bcmgenet_stat_type { 480 BCMGENET_STAT_NETDEV = -1, 481 BCMGENET_STAT_MIB_RX, 482 BCMGENET_STAT_MIB_TX, 483 BCMGENET_STAT_RUNT, 484 BCMGENET_STAT_MISC, 485}; 486 487struct bcmgenet_stats { 488 char stat_string[ETH_GSTRING_LEN]; 489 int stat_sizeof; 490 int stat_offset; 491 enum bcmgenet_stat_type type; 492 /* reg offset from UMAC base for misc counters */ 493 u16 reg_offset; 494}; 495 496#define STAT_NETDEV(m) { \ 497 .stat_string = __stringify(m), \ 498 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \ 499 .stat_offset = offsetof(struct net_device_stats, m), \ 500 .type = BCMGENET_STAT_NETDEV, \ 501} 502 503#define STAT_GENET_MIB(str, m, _type) { \ 504 .stat_string = str, \ 505 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 506 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 507 .type = _type, \ 508} 509 510#define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX) 511#define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX) 512#define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT) 513 514#define STAT_GENET_MISC(str, m, offset) { \ 515 .stat_string = str, \ 516 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \ 517 .stat_offset = offsetof(struct bcmgenet_priv, m), \ 518 .type = BCMGENET_STAT_MISC, \ 519 .reg_offset = offset, \ 520} 521 522 523/* There is a 0xC gap between the end of RX and beginning of TX stats and then 524 * between the end of TX stats and the beginning of the RX RUNT 525 */ 526#define BCMGENET_STAT_OFFSET 0xc 527 528/* Hardware counters must be kept in sync because the order/offset 529 * is important here (order in structure declaration = order in hardware) 530 */ 531static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = { 532 /* general stats */ 533 STAT_NETDEV(rx_packets), 534 STAT_NETDEV(tx_packets), 535 STAT_NETDEV(rx_bytes), 536 STAT_NETDEV(tx_bytes), 537 STAT_NETDEV(rx_errors), 538 STAT_NETDEV(tx_errors), 539 STAT_NETDEV(rx_dropped), 540 STAT_NETDEV(tx_dropped), 541 STAT_NETDEV(multicast), 542 /* UniMAC RSV counters */ 543 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64), 544 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127), 545 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255), 546 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511), 547 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023), 548 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518), 549 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv), 550 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047), 551 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095), 552 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216), 553 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt), 554 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes), 555 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca), 556 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca), 557 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs), 558 STAT_GENET_MIB_RX("rx_control", mib.rx.cf), 559 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf), 560 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo), 561 STAT_GENET_MIB_RX("rx_align", mib.rx.aln), 562 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr), 563 STAT_GENET_MIB_RX("rx_code", mib.rx.cde), 564 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr), 565 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr), 566 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr), 567 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue), 568 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok), 569 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc), 570 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp), 571 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc), 572 /* UniMAC TSV counters */ 573 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64), 574 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127), 575 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255), 576 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511), 577 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023), 578 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518), 579 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv), 580 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047), 581 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095), 582 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216), 583 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts), 584 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca), 585 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca), 586 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf), 587 STAT_GENET_MIB_TX("tx_control", mib.tx.cf), 588 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs), 589 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr), 590 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf), 591 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf), 592 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl), 593 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl), 594 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl), 595 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl), 596 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg), 597 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl), 598 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr), 599 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes), 600 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok), 601 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc), 602 /* UniMAC RUNT counters */ 603 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt), 604 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs), 605 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align), 606 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes), 607 /* Misc UniMAC counters */ 608 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt, 609 UMAC_RBUF_OVFL_CNT), 610 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT), 611 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT), 612}; 613 614#define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats) 615 616static void bcmgenet_get_drvinfo(struct net_device *dev, 617 struct ethtool_drvinfo *info) 618{ 619 strlcpy(info->driver, "bcmgenet", sizeof(info->driver)); 620 strlcpy(info->version, "v2.0", sizeof(info->version)); 621 info->n_stats = BCMGENET_STATS_LEN; 622} 623 624static int bcmgenet_get_sset_count(struct net_device *dev, int string_set) 625{ 626 switch (string_set) { 627 case ETH_SS_STATS: 628 return BCMGENET_STATS_LEN; 629 default: 630 return -EOPNOTSUPP; 631 } 632} 633 634static void bcmgenet_get_strings(struct net_device *dev, u32 stringset, 635 u8 *data) 636{ 637 int i; 638 639 switch (stringset) { 640 case ETH_SS_STATS: 641 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 642 memcpy(data + i * ETH_GSTRING_LEN, 643 bcmgenet_gstrings_stats[i].stat_string, 644 ETH_GSTRING_LEN); 645 } 646 break; 647 } 648} 649 650static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv) 651{ 652 int i, j = 0; 653 654 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 655 const struct bcmgenet_stats *s; 656 u8 offset = 0; 657 u32 val = 0; 658 char *p; 659 660 s = &bcmgenet_gstrings_stats[i]; 661 switch (s->type) { 662 case BCMGENET_STAT_NETDEV: 663 continue; 664 case BCMGENET_STAT_MIB_RX: 665 case BCMGENET_STAT_MIB_TX: 666 case BCMGENET_STAT_RUNT: 667 if (s->type != BCMGENET_STAT_MIB_RX) 668 offset = BCMGENET_STAT_OFFSET; 669 val = bcmgenet_umac_readl(priv, 670 UMAC_MIB_START + j + offset); 671 break; 672 case BCMGENET_STAT_MISC: 673 val = bcmgenet_umac_readl(priv, s->reg_offset); 674 /* clear if overflowed */ 675 if (val == ~0) 676 bcmgenet_umac_writel(priv, 0, s->reg_offset); 677 break; 678 } 679 680 j += s->stat_sizeof; 681 p = (char *)priv + s->stat_offset; 682 *(u32 *)p = val; 683 } 684} 685 686static void bcmgenet_get_ethtool_stats(struct net_device *dev, 687 struct ethtool_stats *stats, 688 u64 *data) 689{ 690 struct bcmgenet_priv *priv = netdev_priv(dev); 691 int i; 692 693 if (netif_running(dev)) 694 bcmgenet_update_mib_counters(priv); 695 696 for (i = 0; i < BCMGENET_STATS_LEN; i++) { 697 const struct bcmgenet_stats *s; 698 char *p; 699 700 s = &bcmgenet_gstrings_stats[i]; 701 if (s->type == BCMGENET_STAT_NETDEV) 702 p = (char *)&dev->stats; 703 else 704 p = (char *)priv; 705 p += s->stat_offset; 706 data[i] = *(u32 *)p; 707 } 708} 709 710/* standard ethtool support functions. */ 711static struct ethtool_ops bcmgenet_ethtool_ops = { 712 .get_strings = bcmgenet_get_strings, 713 .get_sset_count = bcmgenet_get_sset_count, 714 .get_ethtool_stats = bcmgenet_get_ethtool_stats, 715 .get_settings = bcmgenet_get_settings, 716 .set_settings = bcmgenet_set_settings, 717 .get_drvinfo = bcmgenet_get_drvinfo, 718 .get_link = ethtool_op_get_link, 719 .get_msglevel = bcmgenet_get_msglevel, 720 .set_msglevel = bcmgenet_set_msglevel, 721 .get_wol = bcmgenet_get_wol, 722 .set_wol = bcmgenet_set_wol, 723}; 724 725/* Power down the unimac, based on mode. */ 726static void bcmgenet_power_down(struct bcmgenet_priv *priv, 727 enum bcmgenet_power_mode mode) 728{ 729 u32 reg; 730 731 switch (mode) { 732 case GENET_POWER_CABLE_SENSE: 733 phy_detach(priv->phydev); 734 break; 735 736 case GENET_POWER_WOL_MAGIC: 737 bcmgenet_wol_power_down_cfg(priv, mode); 738 break; 739 740 case GENET_POWER_PASSIVE: 741 /* Power down LED */ 742 if (priv->hw_params->flags & GENET_HAS_EXT) { 743 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 744 reg |= (EXT_PWR_DOWN_PHY | 745 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS); 746 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 747 } 748 break; 749 default: 750 break; 751 } 752} 753 754static void bcmgenet_power_up(struct bcmgenet_priv *priv, 755 enum bcmgenet_power_mode mode) 756{ 757 u32 reg; 758 759 if (!(priv->hw_params->flags & GENET_HAS_EXT)) 760 return; 761 762 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 763 764 switch (mode) { 765 case GENET_POWER_PASSIVE: 766 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY | 767 EXT_PWR_DOWN_BIAS); 768 /* fallthrough */ 769 case GENET_POWER_CABLE_SENSE: 770 /* enable APD */ 771 reg |= EXT_PWR_DN_EN_LD; 772 break; 773 case GENET_POWER_WOL_MAGIC: 774 bcmgenet_wol_power_up_cfg(priv, mode); 775 return; 776 default: 777 break; 778 } 779 780 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 781 782 if (mode == GENET_POWER_PASSIVE) 783 bcmgenet_mii_reset(priv->dev); 784} 785 786/* ioctl handle special commands that are not present in ethtool. */ 787static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 788{ 789 struct bcmgenet_priv *priv = netdev_priv(dev); 790 int val = 0; 791 792 if (!netif_running(dev)) 793 return -EINVAL; 794 795 switch (cmd) { 796 case SIOCGMIIPHY: 797 case SIOCGMIIREG: 798 case SIOCSMIIREG: 799 if (!priv->phydev) 800 val = -ENODEV; 801 else 802 val = phy_mii_ioctl(priv->phydev, rq, cmd); 803 break; 804 805 default: 806 val = -EINVAL; 807 break; 808 } 809 810 return val; 811} 812 813static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv, 814 struct bcmgenet_tx_ring *ring) 815{ 816 struct enet_cb *tx_cb_ptr; 817 818 tx_cb_ptr = ring->cbs; 819 tx_cb_ptr += ring->write_ptr - ring->cb_ptr; 820 tx_cb_ptr->bd_addr = priv->tx_bds + ring->write_ptr * DMA_DESC_SIZE; 821 /* Advancing local write pointer */ 822 if (ring->write_ptr == ring->end_ptr) 823 ring->write_ptr = ring->cb_ptr; 824 else 825 ring->write_ptr++; 826 827 return tx_cb_ptr; 828} 829 830/* Simple helper to free a control block's resources */ 831static void bcmgenet_free_cb(struct enet_cb *cb) 832{ 833 dev_kfree_skb_any(cb->skb); 834 cb->skb = NULL; 835 dma_unmap_addr_set(cb, dma_addr, 0); 836} 837 838static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv *priv, 839 struct bcmgenet_tx_ring *ring) 840{ 841 bcmgenet_intrl2_0_writel(priv, 842 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE, 843 INTRL2_CPU_MASK_SET); 844} 845 846static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv *priv, 847 struct bcmgenet_tx_ring *ring) 848{ 849 bcmgenet_intrl2_0_writel(priv, 850 UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE, 851 INTRL2_CPU_MASK_CLEAR); 852} 853 854static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv *priv, 855 struct bcmgenet_tx_ring *ring) 856{ 857 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), 858 INTRL2_CPU_MASK_CLEAR); 859 priv->int1_mask &= ~(1 << ring->index); 860} 861 862static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv *priv, 863 struct bcmgenet_tx_ring *ring) 864{ 865 bcmgenet_intrl2_1_writel(priv, (1 << ring->index), 866 INTRL2_CPU_MASK_SET); 867 priv->int1_mask |= (1 << ring->index); 868} 869 870/* Unlocked version of the reclaim routine */ 871static void __bcmgenet_tx_reclaim(struct net_device *dev, 872 struct bcmgenet_tx_ring *ring) 873{ 874 struct bcmgenet_priv *priv = netdev_priv(dev); 875 int last_tx_cn, last_c_index, num_tx_bds; 876 struct enet_cb *tx_cb_ptr; 877 struct netdev_queue *txq; 878 unsigned int c_index; 879 880 /* Compute how many buffers are transmitted since last xmit call */ 881 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX); 882 txq = netdev_get_tx_queue(dev, ring->queue); 883 884 last_c_index = ring->c_index; 885 num_tx_bds = ring->size; 886 887 c_index &= (num_tx_bds - 1); 888 889 if (c_index >= last_c_index) 890 last_tx_cn = c_index - last_c_index; 891 else 892 last_tx_cn = num_tx_bds - last_c_index + c_index; 893 894 netif_dbg(priv, tx_done, dev, 895 "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n", 896 __func__, ring->index, 897 c_index, last_tx_cn, last_c_index); 898 899 /* Reclaim transmitted buffers */ 900 while (last_tx_cn-- > 0) { 901 tx_cb_ptr = ring->cbs + last_c_index; 902 if (tx_cb_ptr->skb) { 903 dev->stats.tx_bytes += tx_cb_ptr->skb->len; 904 dma_unmap_single(&dev->dev, 905 dma_unmap_addr(tx_cb_ptr, dma_addr), 906 tx_cb_ptr->skb->len, 907 DMA_TO_DEVICE); 908 bcmgenet_free_cb(tx_cb_ptr); 909 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) { 910 dev->stats.tx_bytes += 911 dma_unmap_len(tx_cb_ptr, dma_len); 912 dma_unmap_page(&dev->dev, 913 dma_unmap_addr(tx_cb_ptr, dma_addr), 914 dma_unmap_len(tx_cb_ptr, dma_len), 915 DMA_TO_DEVICE); 916 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0); 917 } 918 dev->stats.tx_packets++; 919 ring->free_bds += 1; 920 921 last_c_index++; 922 last_c_index &= (num_tx_bds - 1); 923 } 924 925 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) 926 ring->int_disable(priv, ring); 927 928 if (netif_tx_queue_stopped(txq)) 929 netif_tx_wake_queue(txq); 930 931 ring->c_index = c_index; 932} 933 934static void bcmgenet_tx_reclaim(struct net_device *dev, 935 struct bcmgenet_tx_ring *ring) 936{ 937 unsigned long flags; 938 939 spin_lock_irqsave(&ring->lock, flags); 940 __bcmgenet_tx_reclaim(dev, ring); 941 spin_unlock_irqrestore(&ring->lock, flags); 942} 943 944static void bcmgenet_tx_reclaim_all(struct net_device *dev) 945{ 946 struct bcmgenet_priv *priv = netdev_priv(dev); 947 int i; 948 949 if (netif_is_multiqueue(dev)) { 950 for (i = 0; i < priv->hw_params->tx_queues; i++) 951 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]); 952 } 953 954 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]); 955} 956 957/* Transmits a single SKB (either head of a fragment or a single SKB) 958 * caller must hold priv->lock 959 */ 960static int bcmgenet_xmit_single(struct net_device *dev, 961 struct sk_buff *skb, 962 u16 dma_desc_flags, 963 struct bcmgenet_tx_ring *ring) 964{ 965 struct bcmgenet_priv *priv = netdev_priv(dev); 966 struct device *kdev = &priv->pdev->dev; 967 struct enet_cb *tx_cb_ptr; 968 unsigned int skb_len; 969 dma_addr_t mapping; 970 u32 length_status; 971 int ret; 972 973 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 974 975 if (unlikely(!tx_cb_ptr)) 976 BUG(); 977 978 tx_cb_ptr->skb = skb; 979 980 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb); 981 982 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE); 983 ret = dma_mapping_error(kdev, mapping); 984 if (ret) { 985 netif_err(priv, tx_err, dev, "Tx DMA map failed\n"); 986 dev_kfree_skb(skb); 987 return ret; 988 } 989 990 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 991 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len); 992 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags | 993 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) | 994 DMA_TX_APPEND_CRC; 995 996 if (skb->ip_summed == CHECKSUM_PARTIAL) 997 length_status |= DMA_TX_DO_CSUM; 998 999 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status); 1000 1001 /* Decrement total BD count and advance our write pointer */ 1002 ring->free_bds -= 1; 1003 ring->prod_index += 1; 1004 ring->prod_index &= DMA_P_INDEX_MASK; 1005 1006 return 0; 1007} 1008 1009/* Transmit a SKB fragment */ 1010static int bcmgenet_xmit_frag(struct net_device *dev, 1011 skb_frag_t *frag, 1012 u16 dma_desc_flags, 1013 struct bcmgenet_tx_ring *ring) 1014{ 1015 struct bcmgenet_priv *priv = netdev_priv(dev); 1016 struct device *kdev = &priv->pdev->dev; 1017 struct enet_cb *tx_cb_ptr; 1018 dma_addr_t mapping; 1019 int ret; 1020 1021 tx_cb_ptr = bcmgenet_get_txcb(priv, ring); 1022 1023 if (unlikely(!tx_cb_ptr)) 1024 BUG(); 1025 tx_cb_ptr->skb = NULL; 1026 1027 mapping = skb_frag_dma_map(kdev, frag, 0, 1028 skb_frag_size(frag), DMA_TO_DEVICE); 1029 ret = dma_mapping_error(kdev, mapping); 1030 if (ret) { 1031 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n", 1032 __func__); 1033 return ret; 1034 } 1035 1036 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping); 1037 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size); 1038 1039 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, 1040 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags | 1041 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT)); 1042 1043 1044 ring->free_bds -= 1; 1045 ring->prod_index += 1; 1046 ring->prod_index &= DMA_P_INDEX_MASK; 1047 1048 return 0; 1049} 1050 1051/* Reallocate the SKB to put enough headroom in front of it and insert 1052 * the transmit checksum offsets in the descriptors 1053 */ 1054static int bcmgenet_put_tx_csum(struct net_device *dev, struct sk_buff *skb) 1055{ 1056 struct status_64 *status = NULL; 1057 struct sk_buff *new_skb; 1058 u16 offset; 1059 u8 ip_proto; 1060 u16 ip_ver; 1061 u32 tx_csum_info; 1062 1063 if (unlikely(skb_headroom(skb) < sizeof(*status))) { 1064 /* If 64 byte status block enabled, must make sure skb has 1065 * enough headroom for us to insert 64B status block. 1066 */ 1067 new_skb = skb_realloc_headroom(skb, sizeof(*status)); 1068 dev_kfree_skb(skb); 1069 if (!new_skb) { 1070 dev->stats.tx_errors++; 1071 dev->stats.tx_dropped++; 1072 return -ENOMEM; 1073 } 1074 skb = new_skb; 1075 } 1076 1077 skb_push(skb, sizeof(*status)); 1078 status = (struct status_64 *)skb->data; 1079 1080 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1081 ip_ver = htons(skb->protocol); 1082 switch (ip_ver) { 1083 case ETH_P_IP: 1084 ip_proto = ip_hdr(skb)->protocol; 1085 break; 1086 case ETH_P_IPV6: 1087 ip_proto = ipv6_hdr(skb)->nexthdr; 1088 break; 1089 default: 1090 return 0; 1091 } 1092 1093 offset = skb_checksum_start_offset(skb) - sizeof(*status); 1094 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) | 1095 (offset + skb->csum_offset); 1096 1097 /* Set the length valid bit for TCP and UDP and just set 1098 * the special UDP flag for IPv4, else just set to 0. 1099 */ 1100 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) { 1101 tx_csum_info |= STATUS_TX_CSUM_LV; 1102 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP) 1103 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP; 1104 } else { 1105 tx_csum_info = 0; 1106 } 1107 1108 status->tx_csum_info = tx_csum_info; 1109 } 1110 1111 return 0; 1112} 1113 1114static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev) 1115{ 1116 struct bcmgenet_priv *priv = netdev_priv(dev); 1117 struct bcmgenet_tx_ring *ring = NULL; 1118 struct netdev_queue *txq; 1119 unsigned long flags = 0; 1120 int nr_frags, index; 1121 u16 dma_desc_flags; 1122 int ret; 1123 int i; 1124 1125 index = skb_get_queue_mapping(skb); 1126 /* Mapping strategy: 1127 * queue_mapping = 0, unclassified, packet xmited through ring16 1128 * queue_mapping = 1, goes to ring 0. (highest priority queue 1129 * queue_mapping = 2, goes to ring 1. 1130 * queue_mapping = 3, goes to ring 2. 1131 * queue_mapping = 4, goes to ring 3. 1132 */ 1133 if (index == 0) 1134 index = DESC_INDEX; 1135 else 1136 index -= 1; 1137 1138 nr_frags = skb_shinfo(skb)->nr_frags; 1139 ring = &priv->tx_rings[index]; 1140 txq = netdev_get_tx_queue(dev, ring->queue); 1141 1142 spin_lock_irqsave(&ring->lock, flags); 1143 if (ring->free_bds <= nr_frags + 1) { 1144 netif_tx_stop_queue(txq); 1145 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n", 1146 __func__, index, ring->queue); 1147 ret = NETDEV_TX_BUSY; 1148 goto out; 1149 } 1150 1151 if (skb_padto(skb, ETH_ZLEN)) { 1152 ret = NETDEV_TX_OK; 1153 goto out; 1154 } 1155 1156 /* set the SKB transmit checksum */ 1157 if (priv->desc_64b_en) { 1158 ret = bcmgenet_put_tx_csum(dev, skb); 1159 if (ret) { 1160 ret = NETDEV_TX_OK; 1161 goto out; 1162 } 1163 } 1164 1165 dma_desc_flags = DMA_SOP; 1166 if (nr_frags == 0) 1167 dma_desc_flags |= DMA_EOP; 1168 1169 /* Transmit single SKB or head of fragment list */ 1170 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring); 1171 if (ret) { 1172 ret = NETDEV_TX_OK; 1173 goto out; 1174 } 1175 1176 /* xmit fragment */ 1177 for (i = 0; i < nr_frags; i++) { 1178 ret = bcmgenet_xmit_frag(dev, 1179 &skb_shinfo(skb)->frags[i], 1180 (i == nr_frags - 1) ? DMA_EOP : 0, 1181 ring); 1182 if (ret) { 1183 ret = NETDEV_TX_OK; 1184 goto out; 1185 } 1186 } 1187 1188 skb_tx_timestamp(skb); 1189 1190 /* we kept a software copy of how much we should advance the TDMA 1191 * producer index, now write it down to the hardware 1192 */ 1193 bcmgenet_tdma_ring_writel(priv, ring->index, 1194 ring->prod_index, TDMA_PROD_INDEX); 1195 1196 if (ring->free_bds <= (MAX_SKB_FRAGS + 1)) { 1197 netif_tx_stop_queue(txq); 1198 ring->int_enable(priv, ring); 1199 } 1200 1201out: 1202 spin_unlock_irqrestore(&ring->lock, flags); 1203 1204 return ret; 1205} 1206 1207 1208static int bcmgenet_rx_refill(struct bcmgenet_priv *priv, struct enet_cb *cb) 1209{ 1210 struct device *kdev = &priv->pdev->dev; 1211 struct sk_buff *skb; 1212 dma_addr_t mapping; 1213 int ret; 1214 1215 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT); 1216 if (!skb) 1217 return -ENOMEM; 1218 1219 /* a caller did not release this control block */ 1220 WARN_ON(cb->skb != NULL); 1221 cb->skb = skb; 1222 mapping = dma_map_single(kdev, skb->data, 1223 priv->rx_buf_len, DMA_FROM_DEVICE); 1224 ret = dma_mapping_error(kdev, mapping); 1225 if (ret) { 1226 bcmgenet_free_cb(cb); 1227 netif_err(priv, rx_err, priv->dev, 1228 "%s DMA map failed\n", __func__); 1229 return ret; 1230 } 1231 1232 dma_unmap_addr_set(cb, dma_addr, mapping); 1233 /* assign packet, prepare descriptor, and advance pointer */ 1234 1235 dmadesc_set_addr(priv, priv->rx_bd_assign_ptr, mapping); 1236 1237 /* turn on the newly assigned BD for DMA to use */ 1238 priv->rx_bd_assign_index++; 1239 priv->rx_bd_assign_index &= (priv->num_rx_bds - 1); 1240 1241 priv->rx_bd_assign_ptr = priv->rx_bds + 1242 (priv->rx_bd_assign_index * DMA_DESC_SIZE); 1243 1244 return 0; 1245} 1246 1247/* bcmgenet_desc_rx - descriptor based rx process. 1248 * this could be called from bottom half, or from NAPI polling method. 1249 */ 1250static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv *priv, 1251 unsigned int budget) 1252{ 1253 struct net_device *dev = priv->dev; 1254 struct enet_cb *cb; 1255 struct sk_buff *skb; 1256 u32 dma_length_status; 1257 unsigned long dma_flag; 1258 int len, err; 1259 unsigned int rxpktprocessed = 0, rxpkttoprocess; 1260 unsigned int p_index; 1261 unsigned int chksum_ok = 0; 1262 1263 p_index = bcmgenet_rdma_ring_readl(priv, DESC_INDEX, RDMA_PROD_INDEX); 1264 p_index &= DMA_P_INDEX_MASK; 1265 1266 if (p_index < priv->rx_c_index) 1267 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - 1268 priv->rx_c_index + p_index; 1269 else 1270 rxpkttoprocess = p_index - priv->rx_c_index; 1271 1272 netif_dbg(priv, rx_status, dev, 1273 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess); 1274 1275 while ((rxpktprocessed < rxpkttoprocess) && 1276 (rxpktprocessed < budget)) { 1277 /* Unmap the packet contents such that we can use the 1278 * RSV from the 64 bytes descriptor when enabled and save 1279 * a 32-bits register read 1280 */ 1281 cb = &priv->rx_cbs[priv->rx_read_ptr]; 1282 skb = cb->skb; 1283 dma_unmap_single(&dev->dev, dma_unmap_addr(cb, dma_addr), 1284 priv->rx_buf_len, DMA_FROM_DEVICE); 1285 1286 if (!priv->desc_64b_en) { 1287 dma_length_status = 1288 dmadesc_get_length_status(priv, 1289 priv->rx_bds + 1290 (priv->rx_read_ptr * 1291 DMA_DESC_SIZE)); 1292 } else { 1293 struct status_64 *status; 1294 1295 status = (struct status_64 *)skb->data; 1296 dma_length_status = status->length_status; 1297 } 1298 1299 /* DMA flags and length are still valid no matter how 1300 * we got the Receive Status Vector (64B RSB or register) 1301 */ 1302 dma_flag = dma_length_status & 0xffff; 1303 len = dma_length_status >> DMA_BUFLENGTH_SHIFT; 1304 1305 netif_dbg(priv, rx_status, dev, 1306 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n", 1307 __func__, p_index, priv->rx_c_index, 1308 priv->rx_read_ptr, dma_length_status); 1309 1310 rxpktprocessed++; 1311 1312 priv->rx_read_ptr++; 1313 priv->rx_read_ptr &= (priv->num_rx_bds - 1); 1314 1315 /* out of memory, just drop packets at the hardware level */ 1316 if (unlikely(!skb)) { 1317 dev->stats.rx_dropped++; 1318 dev->stats.rx_errors++; 1319 goto refill; 1320 } 1321 1322 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) { 1323 netif_err(priv, rx_status, dev, 1324 "dropping fragmented packet!\n"); 1325 dev->stats.rx_dropped++; 1326 dev->stats.rx_errors++; 1327 dev_kfree_skb_any(cb->skb); 1328 cb->skb = NULL; 1329 goto refill; 1330 } 1331 /* report errors */ 1332 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR | 1333 DMA_RX_OV | 1334 DMA_RX_NO | 1335 DMA_RX_LG | 1336 DMA_RX_RXER))) { 1337 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n", 1338 (unsigned int)dma_flag); 1339 if (dma_flag & DMA_RX_CRC_ERROR) 1340 dev->stats.rx_crc_errors++; 1341 if (dma_flag & DMA_RX_OV) 1342 dev->stats.rx_over_errors++; 1343 if (dma_flag & DMA_RX_NO) 1344 dev->stats.rx_frame_errors++; 1345 if (dma_flag & DMA_RX_LG) 1346 dev->stats.rx_length_errors++; 1347 dev->stats.rx_dropped++; 1348 dev->stats.rx_errors++; 1349 1350 /* discard the packet and advance consumer index.*/ 1351 dev_kfree_skb_any(cb->skb); 1352 cb->skb = NULL; 1353 goto refill; 1354 } /* error packet */ 1355 1356 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) && 1357 priv->desc_rxchk_en; 1358 1359 skb_put(skb, len); 1360 if (priv->desc_64b_en) { 1361 skb_pull(skb, 64); 1362 len -= 64; 1363 } 1364 1365 if (likely(chksum_ok)) 1366 skb->ip_summed = CHECKSUM_UNNECESSARY; 1367 1368 /* remove hardware 2bytes added for IP alignment */ 1369 skb_pull(skb, 2); 1370 len -= 2; 1371 1372 if (priv->crc_fwd_en) { 1373 skb_trim(skb, len - ETH_FCS_LEN); 1374 len -= ETH_FCS_LEN; 1375 } 1376 1377 /*Finish setting up the received SKB and send it to the kernel*/ 1378 skb->protocol = eth_type_trans(skb, priv->dev); 1379 dev->stats.rx_packets++; 1380 dev->stats.rx_bytes += len; 1381 if (dma_flag & DMA_RX_MULT) 1382 dev->stats.multicast++; 1383 1384 /* Notify kernel */ 1385 napi_gro_receive(&priv->napi, skb); 1386 cb->skb = NULL; 1387 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n"); 1388 1389 /* refill RX path on the current control block */ 1390refill: 1391 err = bcmgenet_rx_refill(priv, cb); 1392 if (err) 1393 netif_err(priv, rx_err, dev, "Rx refill failed\n"); 1394 } 1395 1396 return rxpktprocessed; 1397} 1398 1399/* Assign skb to RX DMA descriptor. */ 1400static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv) 1401{ 1402 struct enet_cb *cb; 1403 int ret = 0; 1404 int i; 1405 1406 netif_dbg(priv, hw, priv->dev, "%s:\n", __func__); 1407 1408 /* loop here for each buffer needing assign */ 1409 for (i = 0; i < priv->num_rx_bds; i++) { 1410 cb = &priv->rx_cbs[priv->rx_bd_assign_index]; 1411 if (cb->skb) 1412 continue; 1413 1414 ret = bcmgenet_rx_refill(priv, cb); 1415 if (ret) 1416 break; 1417 } 1418 1419 return ret; 1420} 1421 1422static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv) 1423{ 1424 struct enet_cb *cb; 1425 int i; 1426 1427 for (i = 0; i < priv->num_rx_bds; i++) { 1428 cb = &priv->rx_cbs[i]; 1429 1430 if (dma_unmap_addr(cb, dma_addr)) { 1431 dma_unmap_single(&priv->dev->dev, 1432 dma_unmap_addr(cb, dma_addr), 1433 priv->rx_buf_len, DMA_FROM_DEVICE); 1434 dma_unmap_addr_set(cb, dma_addr, 0); 1435 } 1436 1437 if (cb->skb) 1438 bcmgenet_free_cb(cb); 1439 } 1440} 1441 1442static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable) 1443{ 1444 u32 reg; 1445 1446 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 1447 if (enable) 1448 reg |= mask; 1449 else 1450 reg &= ~mask; 1451 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 1452 1453 /* UniMAC stops on a packet boundary, wait for a full-size packet 1454 * to be processed 1455 */ 1456 if (enable == 0) 1457 usleep_range(1000, 2000); 1458} 1459 1460static int reset_umac(struct bcmgenet_priv *priv) 1461{ 1462 struct device *kdev = &priv->pdev->dev; 1463 unsigned int timeout = 0; 1464 u32 reg; 1465 1466 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */ 1467 bcmgenet_rbuf_ctrl_set(priv, 0); 1468 udelay(10); 1469 1470 /* disable MAC while updating its registers */ 1471 bcmgenet_umac_writel(priv, 0, UMAC_CMD); 1472 1473 /* issue soft reset, wait for it to complete */ 1474 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD); 1475 while (timeout++ < 1000) { 1476 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 1477 if (!(reg & CMD_SW_RESET)) 1478 return 0; 1479 1480 udelay(1); 1481 } 1482 1483 if (timeout == 1000) { 1484 dev_err(kdev, 1485 "timeout waiting for MAC to come out of reset\n"); 1486 return -ETIMEDOUT; 1487 } 1488 1489 return 0; 1490} 1491 1492static void bcmgenet_intr_disable(struct bcmgenet_priv *priv) 1493{ 1494 /* Mask all interrupts.*/ 1495 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1496 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 1497 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); 1498 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET); 1499 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR); 1500 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR); 1501} 1502 1503static int init_umac(struct bcmgenet_priv *priv) 1504{ 1505 struct device *kdev = &priv->pdev->dev; 1506 int ret; 1507 u32 reg, cpu_mask_clear; 1508 1509 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n"); 1510 1511 ret = reset_umac(priv); 1512 if (ret) 1513 return ret; 1514 1515 bcmgenet_umac_writel(priv, 0, UMAC_CMD); 1516 /* clear tx/rx counter */ 1517 bcmgenet_umac_writel(priv, 1518 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT, 1519 UMAC_MIB_CTRL); 1520 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL); 1521 1522 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN); 1523 1524 /* init rx registers, enable ip header optimization */ 1525 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL); 1526 reg |= RBUF_ALIGN_2B; 1527 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL); 1528 1529 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv)) 1530 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL); 1531 1532 bcmgenet_intr_disable(priv); 1533 1534 cpu_mask_clear = UMAC_IRQ_RXDMA_BDONE; 1535 1536 dev_dbg(kdev, "%s:Enabling RXDMA_BDONE interrupt\n", __func__); 1537 1538 /* Monitor cable plug/unplugged event for internal PHY */ 1539 if (phy_is_internal(priv->phydev)) { 1540 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP); 1541 } else if (priv->ext_phy) { 1542 cpu_mask_clear |= (UMAC_IRQ_LINK_DOWN | UMAC_IRQ_LINK_UP); 1543 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) { 1544 reg = bcmgenet_bp_mc_get(priv); 1545 reg |= BIT(priv->hw_params->bp_in_en_shift); 1546 1547 /* bp_mask: back pressure mask */ 1548 if (netif_is_multiqueue(priv->dev)) 1549 reg |= priv->hw_params->bp_in_mask; 1550 else 1551 reg &= ~priv->hw_params->bp_in_mask; 1552 bcmgenet_bp_mc_set(priv, reg); 1553 } 1554 1555 /* Enable MDIO interrupts on GENET v3+ */ 1556 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR) 1557 cpu_mask_clear |= UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR; 1558 1559 bcmgenet_intrl2_0_writel(priv, cpu_mask_clear, INTRL2_CPU_MASK_CLEAR); 1560 1561 /* Enable rx/tx engine.*/ 1562 dev_dbg(kdev, "done init umac\n"); 1563 1564 return 0; 1565} 1566 1567/* Initialize all house-keeping variables for a TX ring, along 1568 * with corresponding hardware registers 1569 */ 1570static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv, 1571 unsigned int index, unsigned int size, 1572 unsigned int write_ptr, unsigned int end_ptr) 1573{ 1574 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index]; 1575 u32 words_per_bd = WORDS_PER_BD(priv); 1576 u32 flow_period_val = 0; 1577 unsigned int first_bd; 1578 1579 spin_lock_init(&ring->lock); 1580 ring->index = index; 1581 if (index == DESC_INDEX) { 1582 ring->queue = 0; 1583 ring->int_enable = bcmgenet_tx_ring16_int_enable; 1584 ring->int_disable = bcmgenet_tx_ring16_int_disable; 1585 } else { 1586 ring->queue = index + 1; 1587 ring->int_enable = bcmgenet_tx_ring_int_enable; 1588 ring->int_disable = bcmgenet_tx_ring_int_disable; 1589 } 1590 ring->cbs = priv->tx_cbs + write_ptr; 1591 ring->size = size; 1592 ring->c_index = 0; 1593 ring->free_bds = size; 1594 ring->write_ptr = write_ptr; 1595 ring->cb_ptr = write_ptr; 1596 ring->end_ptr = end_ptr - 1; 1597 ring->prod_index = 0; 1598 1599 /* Set flow period for ring != 16 */ 1600 if (index != DESC_INDEX) 1601 flow_period_val = ENET_MAX_MTU_SIZE << 16; 1602 1603 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX); 1604 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX); 1605 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH); 1606 /* Disable rate control for now */ 1607 bcmgenet_tdma_ring_writel(priv, index, flow_period_val, 1608 TDMA_FLOW_PERIOD); 1609 /* Unclassified traffic goes to ring 16 */ 1610 bcmgenet_tdma_ring_writel(priv, index, 1611 ((size << DMA_RING_SIZE_SHIFT) | 1612 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 1613 1614 first_bd = write_ptr; 1615 1616 /* Set start and end address, read and write pointers */ 1617 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd, 1618 DMA_START_ADDR); 1619 bcmgenet_tdma_ring_writel(priv, index, first_bd * words_per_bd, 1620 TDMA_READ_PTR); 1621 bcmgenet_tdma_ring_writel(priv, index, first_bd, 1622 TDMA_WRITE_PTR); 1623 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1, 1624 DMA_END_ADDR); 1625} 1626 1627/* Initialize a RDMA ring */ 1628static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv, 1629 unsigned int index, unsigned int size) 1630{ 1631 u32 words_per_bd = WORDS_PER_BD(priv); 1632 int ret; 1633 1634 priv->num_rx_bds = TOTAL_DESC; 1635 priv->rx_bds = priv->base + priv->hw_params->rdma_offset; 1636 priv->rx_bd_assign_ptr = priv->rx_bds; 1637 priv->rx_bd_assign_index = 0; 1638 priv->rx_c_index = 0; 1639 priv->rx_read_ptr = 0; 1640 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb), 1641 GFP_KERNEL); 1642 if (!priv->rx_cbs) 1643 return -ENOMEM; 1644 1645 ret = bcmgenet_alloc_rx_buffers(priv); 1646 if (ret) { 1647 kfree(priv->rx_cbs); 1648 return ret; 1649 } 1650 1651 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_WRITE_PTR); 1652 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX); 1653 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX); 1654 bcmgenet_rdma_ring_writel(priv, index, 1655 ((size << DMA_RING_SIZE_SHIFT) | 1656 RX_BUF_LENGTH), DMA_RING_BUF_SIZE); 1657 bcmgenet_rdma_ring_writel(priv, index, 0, DMA_START_ADDR); 1658 bcmgenet_rdma_ring_writel(priv, index, 1659 words_per_bd * size - 1, DMA_END_ADDR); 1660 bcmgenet_rdma_ring_writel(priv, index, 1661 (DMA_FC_THRESH_LO << 1662 DMA_XOFF_THRESHOLD_SHIFT) | 1663 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH); 1664 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_READ_PTR); 1665 1666 return ret; 1667} 1668 1669/* init multi xmit queues, only available for GENET2+ 1670 * the queue is partitioned as follows: 1671 * 1672 * queue 0 - 3 is priority based, each one has 32 descriptors, 1673 * with queue 0 being the highest priority queue. 1674 * 1675 * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT 1676 * descriptors: 256 - (number of tx queues * bds per queues) = 128 1677 * descriptors. 1678 * 1679 * The transmit control block pool is then partitioned as following: 1680 * - tx_cbs[0...127] are for queue 16 1681 * - tx_ring_cbs[0] points to tx_cbs[128..159] 1682 * - tx_ring_cbs[1] points to tx_cbs[160..191] 1683 * - tx_ring_cbs[2] points to tx_cbs[192..223] 1684 * - tx_ring_cbs[3] points to tx_cbs[224..255] 1685 */ 1686static void bcmgenet_init_multiq(struct net_device *dev) 1687{ 1688 struct bcmgenet_priv *priv = netdev_priv(dev); 1689 unsigned int i, dma_enable; 1690 u32 reg, dma_ctrl, ring_cfg = 0, dma_priority = 0; 1691 1692 if (!netif_is_multiqueue(dev)) { 1693 netdev_warn(dev, "called with non multi queue aware HW\n"); 1694 return; 1695 } 1696 1697 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL); 1698 dma_enable = dma_ctrl & DMA_EN; 1699 dma_ctrl &= ~DMA_EN; 1700 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL); 1701 1702 /* Enable strict priority arbiter mode */ 1703 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL); 1704 1705 for (i = 0; i < priv->hw_params->tx_queues; i++) { 1706 /* first 64 tx_cbs are reserved for default tx queue 1707 * (ring 16) 1708 */ 1709 bcmgenet_init_tx_ring(priv, i, priv->hw_params->bds_cnt, 1710 i * priv->hw_params->bds_cnt, 1711 (i + 1) * priv->hw_params->bds_cnt); 1712 1713 /* Configure ring as descriptor ring and setup priority */ 1714 ring_cfg |= 1 << i; 1715 dma_priority |= ((GENET_Q0_PRIORITY + i) << 1716 (GENET_MAX_MQ_CNT + 1) * i); 1717 dma_ctrl |= 1 << (i + DMA_RING_BUF_EN_SHIFT); 1718 } 1719 1720 /* Enable rings */ 1721 reg = bcmgenet_tdma_readl(priv, DMA_RING_CFG); 1722 reg |= ring_cfg; 1723 bcmgenet_tdma_writel(priv, reg, DMA_RING_CFG); 1724 1725 /* Use configured rings priority and set ring #16 priority */ 1726 reg = bcmgenet_tdma_readl(priv, DMA_RING_PRIORITY); 1727 reg |= ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) << 20); 1728 reg |= dma_priority; 1729 bcmgenet_tdma_writel(priv, reg, DMA_PRIORITY); 1730 1731 /* Configure ring as descriptor ring and re-enable DMA if enabled */ 1732 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 1733 reg |= dma_ctrl; 1734 if (dma_enable) 1735 reg |= DMA_EN; 1736 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 1737} 1738 1739static void bcmgenet_fini_dma(struct bcmgenet_priv *priv) 1740{ 1741 int i; 1742 1743 /* disable DMA */ 1744 bcmgenet_rdma_writel(priv, 0, DMA_CTRL); 1745 bcmgenet_tdma_writel(priv, 0, DMA_CTRL); 1746 1747 for (i = 0; i < priv->num_tx_bds; i++) { 1748 if (priv->tx_cbs[i].skb != NULL) { 1749 dev_kfree_skb(priv->tx_cbs[i].skb); 1750 priv->tx_cbs[i].skb = NULL; 1751 } 1752 } 1753 1754 bcmgenet_free_rx_buffers(priv); 1755 kfree(priv->rx_cbs); 1756 kfree(priv->tx_cbs); 1757} 1758 1759/* init_edma: Initialize DMA control register */ 1760static int bcmgenet_init_dma(struct bcmgenet_priv *priv) 1761{ 1762 int ret; 1763 1764 netif_dbg(priv, hw, priv->dev, "bcmgenet: init_edma\n"); 1765 1766 /* by default, enable ring 16 (descriptor based) */ 1767 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, TOTAL_DESC); 1768 if (ret) { 1769 netdev_err(priv->dev, "failed to initialize RX ring\n"); 1770 return ret; 1771 } 1772 1773 /* init rDma */ 1774 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE); 1775 1776 /* Init tDma */ 1777 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE); 1778 1779 /* Initialize common TX ring structures */ 1780 priv->tx_bds = priv->base + priv->hw_params->tdma_offset; 1781 priv->num_tx_bds = TOTAL_DESC; 1782 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb), 1783 GFP_KERNEL); 1784 if (!priv->tx_cbs) { 1785 bcmgenet_fini_dma(priv); 1786 return -ENOMEM; 1787 } 1788 1789 /* initialize multi xmit queue */ 1790 bcmgenet_init_multiq(priv->dev); 1791 1792 /* initialize special ring 16 */ 1793 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_DEFAULT_BD_CNT, 1794 priv->hw_params->tx_queues * 1795 priv->hw_params->bds_cnt, 1796 TOTAL_DESC); 1797 1798 return 0; 1799} 1800 1801/* NAPI polling method*/ 1802static int bcmgenet_poll(struct napi_struct *napi, int budget) 1803{ 1804 struct bcmgenet_priv *priv = container_of(napi, 1805 struct bcmgenet_priv, napi); 1806 unsigned int work_done; 1807 1808 /* tx reclaim */ 1809 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]); 1810 1811 work_done = bcmgenet_desc_rx(priv, budget); 1812 1813 /* Advancing our consumer index*/ 1814 priv->rx_c_index += work_done; 1815 priv->rx_c_index &= DMA_C_INDEX_MASK; 1816 bcmgenet_rdma_ring_writel(priv, DESC_INDEX, 1817 priv->rx_c_index, RDMA_CONS_INDEX); 1818 if (work_done < budget) { 1819 napi_complete(napi); 1820 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE, 1821 INTRL2_CPU_MASK_CLEAR); 1822 } 1823 1824 return work_done; 1825} 1826 1827/* Interrupt bottom half */ 1828static void bcmgenet_irq_task(struct work_struct *work) 1829{ 1830 struct bcmgenet_priv *priv = container_of( 1831 work, struct bcmgenet_priv, bcmgenet_irq_work); 1832 1833 netif_dbg(priv, intr, priv->dev, "%s\n", __func__); 1834 1835 if (priv->irq0_stat & UMAC_IRQ_MPD_R) { 1836 priv->irq0_stat &= ~UMAC_IRQ_MPD_R; 1837 netif_dbg(priv, wol, priv->dev, 1838 "magic packet detected, waking up\n"); 1839 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 1840 } 1841 1842 /* Link UP/DOWN event */ 1843 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 1844 (priv->irq0_stat & (UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN))) { 1845 phy_mac_interrupt(priv->phydev, 1846 priv->irq0_stat & UMAC_IRQ_LINK_UP); 1847 priv->irq0_stat &= ~(UMAC_IRQ_LINK_UP|UMAC_IRQ_LINK_DOWN); 1848 } 1849} 1850 1851/* bcmgenet_isr1: interrupt handler for ring buffer. */ 1852static irqreturn_t bcmgenet_isr1(int irq, void *dev_id) 1853{ 1854 struct bcmgenet_priv *priv = dev_id; 1855 unsigned int index; 1856 1857 /* Save irq status for bottom-half processing. */ 1858 priv->irq1_stat = 1859 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) & 1860 ~priv->int1_mask; 1861 /* clear interrupts */ 1862 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR); 1863 1864 netif_dbg(priv, intr, priv->dev, 1865 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat); 1866 /* Check the MBDONE interrupts. 1867 * packet is done, reclaim descriptors 1868 */ 1869 if (priv->irq1_stat & 0x0000ffff) { 1870 index = 0; 1871 for (index = 0; index < 16; index++) { 1872 if (priv->irq1_stat & (1 << index)) 1873 bcmgenet_tx_reclaim(priv->dev, 1874 &priv->tx_rings[index]); 1875 } 1876 } 1877 return IRQ_HANDLED; 1878} 1879 1880/* bcmgenet_isr0: Handle various interrupts. */ 1881static irqreturn_t bcmgenet_isr0(int irq, void *dev_id) 1882{ 1883 struct bcmgenet_priv *priv = dev_id; 1884 1885 /* Save irq status for bottom-half processing. */ 1886 priv->irq0_stat = 1887 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) & 1888 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS); 1889 /* clear interrupts */ 1890 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR); 1891 1892 netif_dbg(priv, intr, priv->dev, 1893 "IRQ=0x%x\n", priv->irq0_stat); 1894 1895 if (priv->irq0_stat & (UMAC_IRQ_RXDMA_BDONE | UMAC_IRQ_RXDMA_PDONE)) { 1896 /* We use NAPI(software interrupt throttling, if 1897 * Rx Descriptor throttling is not used. 1898 * Disable interrupt, will be enabled in the poll method. 1899 */ 1900 if (likely(napi_schedule_prep(&priv->napi))) { 1901 bcmgenet_intrl2_0_writel(priv, UMAC_IRQ_RXDMA_BDONE, 1902 INTRL2_CPU_MASK_SET); 1903 __napi_schedule(&priv->napi); 1904 } 1905 } 1906 if (priv->irq0_stat & 1907 (UMAC_IRQ_TXDMA_BDONE | UMAC_IRQ_TXDMA_PDONE)) { 1908 /* Tx reclaim */ 1909 bcmgenet_tx_reclaim(priv->dev, &priv->tx_rings[DESC_INDEX]); 1910 } 1911 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R | 1912 UMAC_IRQ_PHY_DET_F | 1913 UMAC_IRQ_LINK_UP | 1914 UMAC_IRQ_LINK_DOWN | 1915 UMAC_IRQ_HFB_SM | 1916 UMAC_IRQ_HFB_MM | 1917 UMAC_IRQ_MPD_R)) { 1918 /* all other interested interrupts handled in bottom half */ 1919 schedule_work(&priv->bcmgenet_irq_work); 1920 } 1921 1922 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) && 1923 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) { 1924 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR); 1925 wake_up(&priv->wq); 1926 } 1927 1928 return IRQ_HANDLED; 1929} 1930 1931static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id) 1932{ 1933 struct bcmgenet_priv *priv = dev_id; 1934 1935 pm_wakeup_event(&priv->pdev->dev, 0); 1936 1937 return IRQ_HANDLED; 1938} 1939 1940static void bcmgenet_umac_reset(struct bcmgenet_priv *priv) 1941{ 1942 u32 reg; 1943 1944 reg = bcmgenet_rbuf_ctrl_get(priv); 1945 reg |= BIT(1); 1946 bcmgenet_rbuf_ctrl_set(priv, reg); 1947 udelay(10); 1948 1949 reg &= ~BIT(1); 1950 bcmgenet_rbuf_ctrl_set(priv, reg); 1951 udelay(10); 1952} 1953 1954static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv, 1955 unsigned char *addr) 1956{ 1957 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) | 1958 (addr[2] << 8) | addr[3], UMAC_MAC0); 1959 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1); 1960} 1961 1962static int bcmgenet_wol_resume(struct bcmgenet_priv *priv) 1963{ 1964 /* From WOL-enabled suspend, switch to regular clock */ 1965 if (priv->wolopts) 1966 clk_disable_unprepare(priv->clk_wol); 1967 1968 phy_init_hw(priv->phydev); 1969 /* Speed settings must be restored */ 1970 bcmgenet_mii_config(priv->dev); 1971 1972 return 0; 1973} 1974 1975/* Returns a reusable dma control register value */ 1976static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv) 1977{ 1978 u32 reg; 1979 u32 dma_ctrl; 1980 1981 /* disable DMA */ 1982 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN; 1983 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 1984 reg &= ~dma_ctrl; 1985 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 1986 1987 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 1988 reg &= ~dma_ctrl; 1989 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 1990 1991 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH); 1992 udelay(10); 1993 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH); 1994 1995 return dma_ctrl; 1996} 1997 1998static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl) 1999{ 2000 u32 reg; 2001 2002 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2003 reg |= dma_ctrl; 2004 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2005 2006 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2007 reg |= dma_ctrl; 2008 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2009} 2010 2011static void bcmgenet_netif_start(struct net_device *dev) 2012{ 2013 struct bcmgenet_priv *priv = netdev_priv(dev); 2014 2015 /* Start the network engine */ 2016 napi_enable(&priv->napi); 2017 2018 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true); 2019 2020 if (phy_is_internal(priv->phydev)) 2021 bcmgenet_power_up(priv, GENET_POWER_PASSIVE); 2022 2023 netif_tx_start_all_queues(dev); 2024 2025 phy_start(priv->phydev); 2026} 2027 2028static int bcmgenet_open(struct net_device *dev) 2029{ 2030 struct bcmgenet_priv *priv = netdev_priv(dev); 2031 unsigned long dma_ctrl; 2032 u32 reg; 2033 int ret; 2034 2035 netif_dbg(priv, ifup, dev, "bcmgenet_open\n"); 2036 2037 /* Turn on the clock */ 2038 if (!IS_ERR(priv->clk)) 2039 clk_prepare_enable(priv->clk); 2040 2041 /* take MAC out of reset */ 2042 bcmgenet_umac_reset(priv); 2043 2044 ret = init_umac(priv); 2045 if (ret) 2046 goto err_clk_disable; 2047 2048 /* disable ethernet MAC while updating its registers */ 2049 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false); 2050 2051 /* Make sure we reflect the value of CRC_CMD_FWD */ 2052 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2053 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD); 2054 2055 bcmgenet_set_hw_addr(priv, dev->dev_addr); 2056 2057 if (phy_is_internal(priv->phydev)) { 2058 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 2059 reg |= EXT_ENERGY_DET_MASK; 2060 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 2061 } 2062 2063 /* Disable RX/TX DMA and flush TX queues */ 2064 dma_ctrl = bcmgenet_dma_disable(priv); 2065 2066 /* Reinitialize TDMA and RDMA and SW housekeeping */ 2067 ret = bcmgenet_init_dma(priv); 2068 if (ret) { 2069 netdev_err(dev, "failed to initialize DMA\n"); 2070 goto err_fini_dma; 2071 } 2072 2073 /* Always enable ring 16 - descriptor ring */ 2074 bcmgenet_enable_dma(priv, dma_ctrl); 2075 2076 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED, 2077 dev->name, priv); 2078 if (ret < 0) { 2079 netdev_err(dev, "can't request IRQ %d\n", priv->irq0); 2080 goto err_fini_dma; 2081 } 2082 2083 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED, 2084 dev->name, priv); 2085 if (ret < 0) { 2086 netdev_err(dev, "can't request IRQ %d\n", priv->irq1); 2087 goto err_irq0; 2088 } 2089 2090 bcmgenet_netif_start(dev); 2091 2092 return 0; 2093 2094err_irq0: 2095 free_irq(priv->irq0, dev); 2096err_fini_dma: 2097 bcmgenet_fini_dma(priv); 2098err_clk_disable: 2099 if (!IS_ERR(priv->clk)) 2100 clk_disable_unprepare(priv->clk); 2101 return ret; 2102} 2103 2104static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv) 2105{ 2106 int ret = 0; 2107 int timeout = 0; 2108 u32 reg; 2109 2110 /* Disable TDMA to stop add more frames in TX DMA */ 2111 reg = bcmgenet_tdma_readl(priv, DMA_CTRL); 2112 reg &= ~DMA_EN; 2113 bcmgenet_tdma_writel(priv, reg, DMA_CTRL); 2114 2115 /* Check TDMA status register to confirm TDMA is disabled */ 2116 while (timeout++ < DMA_TIMEOUT_VAL) { 2117 reg = bcmgenet_tdma_readl(priv, DMA_STATUS); 2118 if (reg & DMA_DISABLED) 2119 break; 2120 2121 udelay(1); 2122 } 2123 2124 if (timeout == DMA_TIMEOUT_VAL) { 2125 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n"); 2126 ret = -ETIMEDOUT; 2127 } 2128 2129 /* Wait 10ms for packet drain in both tx and rx dma */ 2130 usleep_range(10000, 20000); 2131 2132 /* Disable RDMA */ 2133 reg = bcmgenet_rdma_readl(priv, DMA_CTRL); 2134 reg &= ~DMA_EN; 2135 bcmgenet_rdma_writel(priv, reg, DMA_CTRL); 2136 2137 timeout = 0; 2138 /* Check RDMA status register to confirm RDMA is disabled */ 2139 while (timeout++ < DMA_TIMEOUT_VAL) { 2140 reg = bcmgenet_rdma_readl(priv, DMA_STATUS); 2141 if (reg & DMA_DISABLED) 2142 break; 2143 2144 udelay(1); 2145 } 2146 2147 if (timeout == DMA_TIMEOUT_VAL) { 2148 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n"); 2149 ret = -ETIMEDOUT; 2150 } 2151 2152 return ret; 2153} 2154 2155static void bcmgenet_netif_stop(struct net_device *dev) 2156{ 2157 struct bcmgenet_priv *priv = netdev_priv(dev); 2158 2159 netif_tx_stop_all_queues(dev); 2160 napi_disable(&priv->napi); 2161 phy_stop(priv->phydev); 2162 2163 bcmgenet_intr_disable(priv); 2164 2165 /* Wait for pending work items to complete. Since interrupts are 2166 * disabled no new work will be scheduled. 2167 */ 2168 cancel_work_sync(&priv->bcmgenet_irq_work); 2169 2170 priv->old_pause = -1; 2171 priv->old_link = -1; 2172 priv->old_duplex = -1; 2173} 2174 2175static int bcmgenet_close(struct net_device *dev) 2176{ 2177 struct bcmgenet_priv *priv = netdev_priv(dev); 2178 int ret; 2179 2180 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n"); 2181 2182 bcmgenet_netif_stop(dev); 2183 2184 /* Disable MAC receive */ 2185 umac_enable_set(priv, CMD_RX_EN, false); 2186 2187 ret = bcmgenet_dma_teardown(priv); 2188 if (ret) 2189 return ret; 2190 2191 /* Disable MAC transmit. TX DMA disabled have to done before this */ 2192 umac_enable_set(priv, CMD_TX_EN, false); 2193 2194 /* tx reclaim */ 2195 bcmgenet_tx_reclaim_all(dev); 2196 bcmgenet_fini_dma(priv); 2197 2198 free_irq(priv->irq0, priv); 2199 free_irq(priv->irq1, priv); 2200 2201 if (phy_is_internal(priv->phydev)) 2202 bcmgenet_power_down(priv, GENET_POWER_PASSIVE); 2203 2204 if (!IS_ERR(priv->clk)) 2205 clk_disable_unprepare(priv->clk); 2206 2207 return 0; 2208} 2209 2210static void bcmgenet_timeout(struct net_device *dev) 2211{ 2212 struct bcmgenet_priv *priv = netdev_priv(dev); 2213 2214 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n"); 2215 2216 dev->trans_start = jiffies; 2217 2218 dev->stats.tx_errors++; 2219 2220 netif_tx_wake_all_queues(dev); 2221} 2222 2223#define MAX_MC_COUNT 16 2224 2225static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv, 2226 unsigned char *addr, 2227 int *i, 2228 int *mc) 2229{ 2230 u32 reg; 2231 2232 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1], 2233 UMAC_MDF_ADDR + (*i * 4)); 2234 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 | 2235 addr[4] << 8 | addr[5], 2236 UMAC_MDF_ADDR + ((*i + 1) * 4)); 2237 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL); 2238 reg |= (1 << (MAX_MC_COUNT - *mc)); 2239 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL); 2240 *i += 2; 2241 (*mc)++; 2242} 2243 2244static void bcmgenet_set_rx_mode(struct net_device *dev) 2245{ 2246 struct bcmgenet_priv *priv = netdev_priv(dev); 2247 struct netdev_hw_addr *ha; 2248 int i, mc; 2249 u32 reg; 2250 2251 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags); 2252 2253 /* Promiscuous mode */ 2254 reg = bcmgenet_umac_readl(priv, UMAC_CMD); 2255 if (dev->flags & IFF_PROMISC) { 2256 reg |= CMD_PROMISC; 2257 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 2258 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL); 2259 return; 2260 } else { 2261 reg &= ~CMD_PROMISC; 2262 bcmgenet_umac_writel(priv, reg, UMAC_CMD); 2263 } 2264 2265 /* UniMac doesn't support ALLMULTI */ 2266 if (dev->flags & IFF_ALLMULTI) { 2267 netdev_warn(dev, "ALLMULTI is not supported\n"); 2268 return; 2269 } 2270 2271 /* update MDF filter */ 2272 i = 0; 2273 mc = 0; 2274 /* Broadcast */ 2275 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc); 2276 /* my own address.*/ 2277 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc); 2278 /* Unicast list*/ 2279 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc)) 2280 return; 2281 2282 if (!netdev_uc_empty(dev)) 2283 netdev_for_each_uc_addr(ha, dev) 2284 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc); 2285 /* Multicast */ 2286 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc)) 2287 return; 2288 2289 netdev_for_each_mc_addr(ha, dev) 2290 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc); 2291} 2292 2293/* Set the hardware MAC address. */ 2294static int bcmgenet_set_mac_addr(struct net_device *dev, void *p) 2295{ 2296 struct sockaddr *addr = p; 2297 2298 /* Setting the MAC address at the hardware level is not possible 2299 * without disabling the UniMAC RX/TX enable bits. 2300 */ 2301 if (netif_running(dev)) 2302 return -EBUSY; 2303 2304 ether_addr_copy(dev->dev_addr, addr->sa_data); 2305 2306 return 0; 2307} 2308 2309static const struct net_device_ops bcmgenet_netdev_ops = { 2310 .ndo_open = bcmgenet_open, 2311 .ndo_stop = bcmgenet_close, 2312 .ndo_start_xmit = bcmgenet_xmit, 2313 .ndo_tx_timeout = bcmgenet_timeout, 2314 .ndo_set_rx_mode = bcmgenet_set_rx_mode, 2315 .ndo_set_mac_address = bcmgenet_set_mac_addr, 2316 .ndo_do_ioctl = bcmgenet_ioctl, 2317 .ndo_set_features = bcmgenet_set_features, 2318}; 2319 2320/* Array of GENET hardware parameters/characteristics */ 2321static struct bcmgenet_hw_params bcmgenet_hw_params[] = { 2322 [GENET_V1] = { 2323 .tx_queues = 0, 2324 .rx_queues = 0, 2325 .bds_cnt = 0, 2326 .bp_in_en_shift = 16, 2327 .bp_in_mask = 0xffff, 2328 .hfb_filter_cnt = 16, 2329 .qtag_mask = 0x1F, 2330 .hfb_offset = 0x1000, 2331 .rdma_offset = 0x2000, 2332 .tdma_offset = 0x3000, 2333 .words_per_bd = 2, 2334 }, 2335 [GENET_V2] = { 2336 .tx_queues = 4, 2337 .rx_queues = 4, 2338 .bds_cnt = 32, 2339 .bp_in_en_shift = 16, 2340 .bp_in_mask = 0xffff, 2341 .hfb_filter_cnt = 16, 2342 .qtag_mask = 0x1F, 2343 .tbuf_offset = 0x0600, 2344 .hfb_offset = 0x1000, 2345 .hfb_reg_offset = 0x2000, 2346 .rdma_offset = 0x3000, 2347 .tdma_offset = 0x4000, 2348 .words_per_bd = 2, 2349 .flags = GENET_HAS_EXT, 2350 }, 2351 [GENET_V3] = { 2352 .tx_queues = 4, 2353 .rx_queues = 4, 2354 .bds_cnt = 32, 2355 .bp_in_en_shift = 17, 2356 .bp_in_mask = 0x1ffff, 2357 .hfb_filter_cnt = 48, 2358 .qtag_mask = 0x3F, 2359 .tbuf_offset = 0x0600, 2360 .hfb_offset = 0x8000, 2361 .hfb_reg_offset = 0xfc00, 2362 .rdma_offset = 0x10000, 2363 .tdma_offset = 0x11000, 2364 .words_per_bd = 2, 2365 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR, 2366 }, 2367 [GENET_V4] = { 2368 .tx_queues = 4, 2369 .rx_queues = 4, 2370 .bds_cnt = 32, 2371 .bp_in_en_shift = 17, 2372 .bp_in_mask = 0x1ffff, 2373 .hfb_filter_cnt = 48, 2374 .qtag_mask = 0x3F, 2375 .tbuf_offset = 0x0600, 2376 .hfb_offset = 0x8000, 2377 .hfb_reg_offset = 0xfc00, 2378 .rdma_offset = 0x2000, 2379 .tdma_offset = 0x4000, 2380 .words_per_bd = 3, 2381 .flags = GENET_HAS_40BITS | GENET_HAS_EXT | GENET_HAS_MDIO_INTR, 2382 }, 2383}; 2384 2385/* Infer hardware parameters from the detected GENET version */ 2386static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv) 2387{ 2388 struct bcmgenet_hw_params *params; 2389 u32 reg; 2390 u8 major; 2391 2392 if (GENET_IS_V4(priv)) { 2393 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 2394 genet_dma_ring_regs = genet_dma_ring_regs_v4; 2395 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; 2396 priv->version = GENET_V4; 2397 } else if (GENET_IS_V3(priv)) { 2398 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus; 2399 genet_dma_ring_regs = genet_dma_ring_regs_v123; 2400 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS; 2401 priv->version = GENET_V3; 2402 } else if (GENET_IS_V2(priv)) { 2403 bcmgenet_dma_regs = bcmgenet_dma_regs_v2; 2404 genet_dma_ring_regs = genet_dma_ring_regs_v123; 2405 priv->dma_rx_chk_bit = DMA_RX_CHK_V12; 2406 priv->version = GENET_V2; 2407 } else if (GENET_IS_V1(priv)) { 2408 bcmgenet_dma_regs = bcmgenet_dma_regs_v1; 2409 genet_dma_ring_regs = genet_dma_ring_regs_v123; 2410 priv->dma_rx_chk_bit = DMA_RX_CHK_V12; 2411 priv->version = GENET_V1; 2412 } 2413 2414 /* enum genet_version starts at 1 */ 2415 priv->hw_params = &bcmgenet_hw_params[priv->version]; 2416 params = priv->hw_params; 2417 2418 /* Read GENET HW version */ 2419 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL); 2420 major = (reg >> 24 & 0x0f); 2421 if (major == 5) 2422 major = 4; 2423 else if (major == 0) 2424 major = 1; 2425 if (major != priv->version) { 2426 dev_err(&priv->pdev->dev, 2427 "GENET version mismatch, got: %d, configured for: %d\n", 2428 major, priv->version); 2429 } 2430 2431 /* Print the GENET core version */ 2432 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT, 2433 major, (reg >> 16) & 0x0f, reg & 0xffff); 2434 2435#ifdef CONFIG_PHYS_ADDR_T_64BIT 2436 if (!(params->flags & GENET_HAS_40BITS)) 2437 pr_warn("GENET does not support 40-bits PA\n"); 2438#endif 2439 2440 pr_debug("Configuration for version: %d\n" 2441 "TXq: %1d, RXq: %1d, BDs: %1d\n" 2442 "BP << en: %2d, BP msk: 0x%05x\n" 2443 "HFB count: %2d, QTAQ msk: 0x%05x\n" 2444 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n" 2445 "RDMA: 0x%05x, TDMA: 0x%05x\n" 2446 "Words/BD: %d\n", 2447 priv->version, 2448 params->tx_queues, params->rx_queues, params->bds_cnt, 2449 params->bp_in_en_shift, params->bp_in_mask, 2450 params->hfb_filter_cnt, params->qtag_mask, 2451 params->tbuf_offset, params->hfb_offset, 2452 params->hfb_reg_offset, 2453 params->rdma_offset, params->tdma_offset, 2454 params->words_per_bd); 2455} 2456 2457static const struct of_device_id bcmgenet_match[] = { 2458 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 }, 2459 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 }, 2460 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 }, 2461 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 }, 2462 { }, 2463}; 2464 2465static int bcmgenet_probe(struct platform_device *pdev) 2466{ 2467 struct device_node *dn = pdev->dev.of_node; 2468 const struct of_device_id *of_id; 2469 struct bcmgenet_priv *priv; 2470 struct net_device *dev; 2471 const void *macaddr; 2472 struct resource *r; 2473 int err = -EIO; 2474 2475 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */ 2476 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1, 1); 2477 if (!dev) { 2478 dev_err(&pdev->dev, "can't allocate net device\n"); 2479 return -ENOMEM; 2480 } 2481 2482 of_id = of_match_node(bcmgenet_match, dn); 2483 if (!of_id) 2484 return -EINVAL; 2485 2486 priv = netdev_priv(dev); 2487 priv->irq0 = platform_get_irq(pdev, 0); 2488 priv->irq1 = platform_get_irq(pdev, 1); 2489 priv->wol_irq = platform_get_irq(pdev, 2); 2490 if (!priv->irq0 || !priv->irq1) { 2491 dev_err(&pdev->dev, "can't find IRQs\n"); 2492 err = -EINVAL; 2493 goto err; 2494 } 2495 2496 macaddr = of_get_mac_address(dn); 2497 if (!macaddr) { 2498 dev_err(&pdev->dev, "can't find MAC address\n"); 2499 err = -EINVAL; 2500 goto err; 2501 } 2502 2503 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2504 priv->base = devm_ioremap_resource(&pdev->dev, r); 2505 if (IS_ERR(priv->base)) { 2506 err = PTR_ERR(priv->base); 2507 goto err; 2508 } 2509 2510 SET_NETDEV_DEV(dev, &pdev->dev); 2511 dev_set_drvdata(&pdev->dev, dev); 2512 ether_addr_copy(dev->dev_addr, macaddr); 2513 dev->watchdog_timeo = 2 * HZ; 2514 dev->ethtool_ops = &bcmgenet_ethtool_ops; 2515 dev->netdev_ops = &bcmgenet_netdev_ops; 2516 netif_napi_add(dev, &priv->napi, bcmgenet_poll, 64); 2517 2518 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT); 2519 2520 /* Set hardware features */ 2521 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | 2522 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM; 2523 2524 /* Request the WOL interrupt and advertise suspend if available */ 2525 priv->wol_irq_disabled = true; 2526 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0, 2527 dev->name, priv); 2528 if (!err) 2529 device_set_wakeup_capable(&pdev->dev, 1); 2530 2531 /* Set the needed headroom to account for any possible 2532 * features enabling/disabling at runtime 2533 */ 2534 dev->needed_headroom += 64; 2535 2536 netdev_boot_setup_check(dev); 2537 2538 priv->dev = dev; 2539 priv->pdev = pdev; 2540 priv->version = (enum bcmgenet_version)of_id->data; 2541 2542 priv->clk = devm_clk_get(&priv->pdev->dev, "enet"); 2543 if (IS_ERR(priv->clk)) 2544 dev_warn(&priv->pdev->dev, "failed to get enet clock\n"); 2545 2546 if (!IS_ERR(priv->clk)) 2547 clk_prepare_enable(priv->clk); 2548 2549 bcmgenet_set_hw_params(priv); 2550 2551 /* Mii wait queue */ 2552 init_waitqueue_head(&priv->wq); 2553 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */ 2554 priv->rx_buf_len = RX_BUF_LENGTH; 2555 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task); 2556 2557 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol"); 2558 if (IS_ERR(priv->clk_wol)) 2559 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n"); 2560 2561 err = reset_umac(priv); 2562 if (err) 2563 goto err_clk_disable; 2564 2565 err = bcmgenet_mii_init(dev); 2566 if (err) 2567 goto err_clk_disable; 2568 2569 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues 2570 * just the ring 16 descriptor based TX 2571 */ 2572 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1); 2573 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1); 2574 2575 /* libphy will determine the link state */ 2576 netif_carrier_off(dev); 2577 2578 /* Turn off the main clock, WOL clock is handled separately */ 2579 if (!IS_ERR(priv->clk)) 2580 clk_disable_unprepare(priv->clk); 2581 2582 err = register_netdev(dev); 2583 if (err) 2584 goto err; 2585 2586 return err; 2587 2588err_clk_disable: 2589 if (!IS_ERR(priv->clk)) 2590 clk_disable_unprepare(priv->clk); 2591err: 2592 free_netdev(dev); 2593 return err; 2594} 2595 2596static int bcmgenet_remove(struct platform_device *pdev) 2597{ 2598 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev); 2599 2600 dev_set_drvdata(&pdev->dev, NULL); 2601 unregister_netdev(priv->dev); 2602 bcmgenet_mii_exit(priv->dev); 2603 free_netdev(priv->dev); 2604 2605 return 0; 2606} 2607 2608#ifdef CONFIG_PM_SLEEP 2609static int bcmgenet_suspend(struct device *d) 2610{ 2611 struct net_device *dev = dev_get_drvdata(d); 2612 struct bcmgenet_priv *priv = netdev_priv(dev); 2613 int ret; 2614 2615 if (!netif_running(dev)) 2616 return 0; 2617 2618 bcmgenet_netif_stop(dev); 2619 2620 phy_suspend(priv->phydev); 2621 2622 netif_device_detach(dev); 2623 2624 /* Disable MAC receive */ 2625 umac_enable_set(priv, CMD_RX_EN, false); 2626 2627 ret = bcmgenet_dma_teardown(priv); 2628 if (ret) 2629 return ret; 2630 2631 /* Disable MAC transmit. TX DMA disabled have to done before this */ 2632 umac_enable_set(priv, CMD_TX_EN, false); 2633 2634 /* tx reclaim */ 2635 bcmgenet_tx_reclaim_all(dev); 2636 bcmgenet_fini_dma(priv); 2637 2638 /* Prepare the device for Wake-on-LAN and switch to the slow clock */ 2639 if (device_may_wakeup(d) && priv->wolopts) { 2640 bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC); 2641 clk_prepare_enable(priv->clk_wol); 2642 } 2643 2644 /* Turn off the clocks */ 2645 clk_disable_unprepare(priv->clk); 2646 2647 return 0; 2648} 2649 2650static int bcmgenet_resume(struct device *d) 2651{ 2652 struct net_device *dev = dev_get_drvdata(d); 2653 struct bcmgenet_priv *priv = netdev_priv(dev); 2654 unsigned long dma_ctrl; 2655 int ret; 2656 u32 reg; 2657 2658 if (!netif_running(dev)) 2659 return 0; 2660 2661 /* Turn on the clock */ 2662 ret = clk_prepare_enable(priv->clk); 2663 if (ret) 2664 return ret; 2665 2666 bcmgenet_umac_reset(priv); 2667 2668 ret = init_umac(priv); 2669 if (ret) 2670 goto out_clk_disable; 2671 2672 ret = bcmgenet_wol_resume(priv); 2673 if (ret) 2674 goto out_clk_disable; 2675 2676 /* disable ethernet MAC while updating its registers */ 2677 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false); 2678 2679 bcmgenet_set_hw_addr(priv, dev->dev_addr); 2680 2681 if (phy_is_internal(priv->phydev)) { 2682 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT); 2683 reg |= EXT_ENERGY_DET_MASK; 2684 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT); 2685 } 2686 2687 if (priv->wolopts) 2688 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC); 2689 2690 /* Disable RX/TX DMA and flush TX queues */ 2691 dma_ctrl = bcmgenet_dma_disable(priv); 2692 2693 /* Reinitialize TDMA and RDMA and SW housekeeping */ 2694 ret = bcmgenet_init_dma(priv); 2695 if (ret) { 2696 netdev_err(dev, "failed to initialize DMA\n"); 2697 goto out_clk_disable; 2698 } 2699 2700 /* Always enable ring 16 - descriptor ring */ 2701 bcmgenet_enable_dma(priv, dma_ctrl); 2702 2703 netif_device_attach(dev); 2704 2705 phy_resume(priv->phydev); 2706 2707 bcmgenet_netif_start(dev); 2708 2709 return 0; 2710 2711out_clk_disable: 2712 clk_disable_unprepare(priv->clk); 2713 return ret; 2714} 2715#endif /* CONFIG_PM_SLEEP */ 2716 2717static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume); 2718 2719static struct platform_driver bcmgenet_driver = { 2720 .probe = bcmgenet_probe, 2721 .remove = bcmgenet_remove, 2722 .driver = { 2723 .name = "bcmgenet", 2724 .owner = THIS_MODULE, 2725 .of_match_table = bcmgenet_match, 2726 .pm = &bcmgenet_pm_ops, 2727 }, 2728}; 2729module_platform_driver(bcmgenet_driver); 2730 2731MODULE_AUTHOR("Broadcom Corporation"); 2732MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver"); 2733MODULE_ALIAS("platform:bcmgenet"); 2734MODULE_LICENSE("GPL"); 2735