sb1250-mac.c revision 446bbc4b5ee122c3a3a4954b144d031f0f9aa006
1/* 2 * Copyright (C) 2001,2002,2003,2004 Broadcom Corporation 3 * Copyright (c) 2006, 2007 Maciej W. Rozycki 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 18 * 19 * 20 * This driver is designed for the Broadcom SiByte SOC built-in 21 * Ethernet controllers. Written by Mitch Lichtenberg at Broadcom Corp. 22 * 23 * Updated to the driver model and the PHY abstraction layer 24 * by Maciej W. Rozycki. 25 */ 26 27#include <linux/bug.h> 28#include <linux/module.h> 29#include <linux/kernel.h> 30#include <linux/string.h> 31#include <linux/timer.h> 32#include <linux/errno.h> 33#include <linux/ioport.h> 34#include <linux/slab.h> 35#include <linux/interrupt.h> 36#include <linux/netdevice.h> 37#include <linux/etherdevice.h> 38#include <linux/skbuff.h> 39#include <linux/init.h> 40#include <linux/bitops.h> 41#include <linux/err.h> 42#include <linux/ethtool.h> 43#include <linux/mii.h> 44#include <linux/phy.h> 45#include <linux/platform_device.h> 46#include <linux/prefetch.h> 47 48#include <asm/cache.h> 49#include <asm/io.h> 50#include <asm/processor.h> /* Processor type for cache alignment. */ 51 52/* Operational parameters that usually are not changed. */ 53 54#define CONFIG_SBMAC_COALESCE 55 56/* Time in jiffies before concluding the transmitter is hung. */ 57#define TX_TIMEOUT (2*HZ) 58 59 60MODULE_AUTHOR("Mitch Lichtenberg (Broadcom Corp.)"); 61MODULE_DESCRIPTION("Broadcom SiByte SOC GB Ethernet driver"); 62 63/* A few user-configurable values which may be modified when a driver 64 module is loaded. */ 65 66/* 1 normal messages, 0 quiet .. 7 verbose. */ 67static int debug = 1; 68module_param(debug, int, S_IRUGO); 69MODULE_PARM_DESC(debug, "Debug messages"); 70 71#ifdef CONFIG_SBMAC_COALESCE 72static int int_pktcnt_tx = 255; 73module_param(int_pktcnt_tx, int, S_IRUGO); 74MODULE_PARM_DESC(int_pktcnt_tx, "TX packet count"); 75 76static int int_timeout_tx = 255; 77module_param(int_timeout_tx, int, S_IRUGO); 78MODULE_PARM_DESC(int_timeout_tx, "TX timeout value"); 79 80static int int_pktcnt_rx = 64; 81module_param(int_pktcnt_rx, int, S_IRUGO); 82MODULE_PARM_DESC(int_pktcnt_rx, "RX packet count"); 83 84static int int_timeout_rx = 64; 85module_param(int_timeout_rx, int, S_IRUGO); 86MODULE_PARM_DESC(int_timeout_rx, "RX timeout value"); 87#endif 88 89#include <asm/sibyte/board.h> 90#include <asm/sibyte/sb1250.h> 91#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 92#include <asm/sibyte/bcm1480_regs.h> 93#include <asm/sibyte/bcm1480_int.h> 94#define R_MAC_DMA_OODPKTLOST_RX R_MAC_DMA_OODPKTLOST 95#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 96#include <asm/sibyte/sb1250_regs.h> 97#include <asm/sibyte/sb1250_int.h> 98#else 99#error invalid SiByte MAC configuration 100#endif 101#include <asm/sibyte/sb1250_scd.h> 102#include <asm/sibyte/sb1250_mac.h> 103#include <asm/sibyte/sb1250_dma.h> 104 105#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 106#define UNIT_INT(n) (K_BCM1480_INT_MAC_0 + ((n) * 2)) 107#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 108#define UNIT_INT(n) (K_INT_MAC_0 + (n)) 109#else 110#error invalid SiByte MAC configuration 111#endif 112 113#ifdef K_INT_PHY 114#define SBMAC_PHY_INT K_INT_PHY 115#else 116#define SBMAC_PHY_INT PHY_POLL 117#endif 118 119/********************************************************************** 120 * Simple types 121 ********************************************************************* */ 122 123enum sbmac_speed { 124 sbmac_speed_none = 0, 125 sbmac_speed_10 = SPEED_10, 126 sbmac_speed_100 = SPEED_100, 127 sbmac_speed_1000 = SPEED_1000, 128}; 129 130enum sbmac_duplex { 131 sbmac_duplex_none = -1, 132 sbmac_duplex_half = DUPLEX_HALF, 133 sbmac_duplex_full = DUPLEX_FULL, 134}; 135 136enum sbmac_fc { 137 sbmac_fc_none, 138 sbmac_fc_disabled, 139 sbmac_fc_frame, 140 sbmac_fc_collision, 141 sbmac_fc_carrier, 142}; 143 144enum sbmac_state { 145 sbmac_state_uninit, 146 sbmac_state_off, 147 sbmac_state_on, 148 sbmac_state_broken, 149}; 150 151 152/********************************************************************** 153 * Macros 154 ********************************************************************* */ 155 156 157#define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \ 158 (d)->sbdma_dscrtable : (d)->f+1) 159 160 161#define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES) 162 163#define SBMAC_MAX_TXDESCR 256 164#define SBMAC_MAX_RXDESCR 256 165 166#define ENET_PACKET_SIZE 1518 167/*#define ENET_PACKET_SIZE 9216 */ 168 169/********************************************************************** 170 * DMA Descriptor structure 171 ********************************************************************* */ 172 173struct sbdmadscr { 174 uint64_t dscr_a; 175 uint64_t dscr_b; 176}; 177 178/********************************************************************** 179 * DMA Controller structure 180 ********************************************************************* */ 181 182struct sbmacdma { 183 184 /* 185 * This stuff is used to identify the channel and the registers 186 * associated with it. 187 */ 188 struct sbmac_softc *sbdma_eth; /* back pointer to associated 189 MAC */ 190 int sbdma_channel; /* channel number */ 191 int sbdma_txdir; /* direction (1=transmit) */ 192 int sbdma_maxdescr; /* total # of descriptors 193 in ring */ 194#ifdef CONFIG_SBMAC_COALESCE 195 int sbdma_int_pktcnt; 196 /* # descriptors rx/tx 197 before interrupt */ 198 int sbdma_int_timeout; 199 /* # usec rx/tx interrupt */ 200#endif 201 void __iomem *sbdma_config0; /* DMA config register 0 */ 202 void __iomem *sbdma_config1; /* DMA config register 1 */ 203 void __iomem *sbdma_dscrbase; 204 /* descriptor base address */ 205 void __iomem *sbdma_dscrcnt; /* descriptor count register */ 206 void __iomem *sbdma_curdscr; /* current descriptor 207 address */ 208 void __iomem *sbdma_oodpktlost; 209 /* pkt drop (rx only) */ 210 211 /* 212 * This stuff is for maintenance of the ring 213 */ 214 void *sbdma_dscrtable_unaligned; 215 struct sbdmadscr *sbdma_dscrtable; 216 /* base of descriptor table */ 217 struct sbdmadscr *sbdma_dscrtable_end; 218 /* end of descriptor table */ 219 struct sk_buff **sbdma_ctxtable; 220 /* context table, one 221 per descr */ 222 dma_addr_t sbdma_dscrtable_phys; 223 /* and also the phys addr */ 224 struct sbdmadscr *sbdma_addptr; /* next dscr for sw to add */ 225 struct sbdmadscr *sbdma_remptr; /* next dscr for sw 226 to remove */ 227}; 228 229 230/********************************************************************** 231 * Ethernet softc structure 232 ********************************************************************* */ 233 234struct sbmac_softc { 235 236 /* 237 * Linux-specific things 238 */ 239 struct net_device *sbm_dev; /* pointer to linux device */ 240 struct napi_struct napi; 241 struct phy_device *phy_dev; /* the associated PHY device */ 242 struct mii_bus *mii_bus; /* the MII bus */ 243 int phy_irq[PHY_MAX_ADDR]; 244 spinlock_t sbm_lock; /* spin lock */ 245 int sbm_devflags; /* current device flags */ 246 247 /* 248 * Controller-specific things 249 */ 250 void __iomem *sbm_base; /* MAC's base address */ 251 enum sbmac_state sbm_state; /* current state */ 252 253 void __iomem *sbm_macenable; /* MAC Enable Register */ 254 void __iomem *sbm_maccfg; /* MAC Config Register */ 255 void __iomem *sbm_fifocfg; /* FIFO Config Register */ 256 void __iomem *sbm_framecfg; /* Frame Config Register */ 257 void __iomem *sbm_rxfilter; /* Receive Filter Register */ 258 void __iomem *sbm_isr; /* Interrupt Status Register */ 259 void __iomem *sbm_imr; /* Interrupt Mask Register */ 260 void __iomem *sbm_mdio; /* MDIO Register */ 261 262 enum sbmac_speed sbm_speed; /* current speed */ 263 enum sbmac_duplex sbm_duplex; /* current duplex */ 264 enum sbmac_fc sbm_fc; /* cur. flow control setting */ 265 int sbm_pause; /* current pause setting */ 266 int sbm_link; /* current link state */ 267 268 unsigned char sbm_hwaddr[ETH_ALEN]; 269 270 struct sbmacdma sbm_txdma; /* only channel 0 for now */ 271 struct sbmacdma sbm_rxdma; 272 int rx_hw_checksum; 273 int sbe_idx; 274}; 275 276 277/********************************************************************** 278 * Externs 279 ********************************************************************* */ 280 281/********************************************************************** 282 * Prototypes 283 ********************************************************************* */ 284 285static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan, 286 int txrx, int maxdescr); 287static void sbdma_channel_start(struct sbmacdma *d, int rxtx); 288static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d, 289 struct sk_buff *m); 290static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *m); 291static void sbdma_emptyring(struct sbmacdma *d); 292static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d); 293static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d, 294 int work_to_do, int poll); 295static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d, 296 int poll); 297static int sbmac_initctx(struct sbmac_softc *s); 298static void sbmac_channel_start(struct sbmac_softc *s); 299static void sbmac_channel_stop(struct sbmac_softc *s); 300static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *, 301 enum sbmac_state); 302static void sbmac_promiscuous_mode(struct sbmac_softc *sc, int onoff); 303static uint64_t sbmac_addr2reg(unsigned char *ptr); 304static irqreturn_t sbmac_intr(int irq, void *dev_instance); 305static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev); 306static void sbmac_setmulti(struct sbmac_softc *sc); 307static int sbmac_init(struct platform_device *pldev, long long base); 308static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed); 309static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex, 310 enum sbmac_fc fc); 311 312static int sbmac_open(struct net_device *dev); 313static void sbmac_tx_timeout (struct net_device *dev); 314static void sbmac_set_rx_mode(struct net_device *dev); 315static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 316static int sbmac_close(struct net_device *dev); 317static int sbmac_poll(struct napi_struct *napi, int budget); 318 319static void sbmac_mii_poll(struct net_device *dev); 320static int sbmac_mii_probe(struct net_device *dev); 321 322static void sbmac_mii_sync(void __iomem *sbm_mdio); 323static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data, 324 int bitcnt); 325static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx); 326static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, 327 u16 val); 328 329 330/********************************************************************** 331 * Globals 332 ********************************************************************* */ 333 334static char sbmac_string[] = "sb1250-mac"; 335 336static char sbmac_mdio_string[] = "sb1250-mac-mdio"; 337 338 339/********************************************************************** 340 * MDIO constants 341 ********************************************************************* */ 342 343#define MII_COMMAND_START 0x01 344#define MII_COMMAND_READ 0x02 345#define MII_COMMAND_WRITE 0x01 346#define MII_COMMAND_ACK 0x02 347 348#define M_MAC_MDIO_DIR_OUTPUT 0 /* for clarity */ 349 350#define ENABLE 1 351#define DISABLE 0 352 353/********************************************************************** 354 * SBMAC_MII_SYNC(sbm_mdio) 355 * 356 * Synchronize with the MII - send a pattern of bits to the MII 357 * that will guarantee that it is ready to accept a command. 358 * 359 * Input parameters: 360 * sbm_mdio - address of the MAC's MDIO register 361 * 362 * Return value: 363 * nothing 364 ********************************************************************* */ 365 366static void sbmac_mii_sync(void __iomem *sbm_mdio) 367{ 368 int cnt; 369 uint64_t bits; 370 int mac_mdio_genc; 371 372 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; 373 374 bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT; 375 376 __raw_writeq(bits | mac_mdio_genc, sbm_mdio); 377 378 for (cnt = 0; cnt < 32; cnt++) { 379 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio); 380 __raw_writeq(bits | mac_mdio_genc, sbm_mdio); 381 } 382} 383 384/********************************************************************** 385 * SBMAC_MII_SENDDATA(sbm_mdio, data, bitcnt) 386 * 387 * Send some bits to the MII. The bits to be sent are right- 388 * justified in the 'data' parameter. 389 * 390 * Input parameters: 391 * sbm_mdio - address of the MAC's MDIO register 392 * data - data to send 393 * bitcnt - number of bits to send 394 ********************************************************************* */ 395 396static void sbmac_mii_senddata(void __iomem *sbm_mdio, unsigned int data, 397 int bitcnt) 398{ 399 int i; 400 uint64_t bits; 401 unsigned int curmask; 402 int mac_mdio_genc; 403 404 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; 405 406 bits = M_MAC_MDIO_DIR_OUTPUT; 407 __raw_writeq(bits | mac_mdio_genc, sbm_mdio); 408 409 curmask = 1 << (bitcnt - 1); 410 411 for (i = 0; i < bitcnt; i++) { 412 if (data & curmask) 413 bits |= M_MAC_MDIO_OUT; 414 else bits &= ~M_MAC_MDIO_OUT; 415 __raw_writeq(bits | mac_mdio_genc, sbm_mdio); 416 __raw_writeq(bits | M_MAC_MDC | mac_mdio_genc, sbm_mdio); 417 __raw_writeq(bits | mac_mdio_genc, sbm_mdio); 418 curmask >>= 1; 419 } 420} 421 422 423 424/********************************************************************** 425 * SBMAC_MII_READ(bus, phyaddr, regidx) 426 * Read a PHY register. 427 * 428 * Input parameters: 429 * bus - MDIO bus handle 430 * phyaddr - PHY's address 431 * regnum - index of register to read 432 * 433 * Return value: 434 * value read, or 0xffff if an error occurred. 435 ********************************************************************* */ 436 437static int sbmac_mii_read(struct mii_bus *bus, int phyaddr, int regidx) 438{ 439 struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv; 440 void __iomem *sbm_mdio = sc->sbm_mdio; 441 int idx; 442 int error; 443 int regval; 444 int mac_mdio_genc; 445 446 /* 447 * Synchronize ourselves so that the PHY knows the next 448 * thing coming down is a command 449 */ 450 sbmac_mii_sync(sbm_mdio); 451 452 /* 453 * Send the data to the PHY. The sequence is 454 * a "start" command (2 bits) 455 * a "read" command (2 bits) 456 * the PHY addr (5 bits) 457 * the register index (5 bits) 458 */ 459 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2); 460 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_READ, 2); 461 sbmac_mii_senddata(sbm_mdio, phyaddr, 5); 462 sbmac_mii_senddata(sbm_mdio, regidx, 5); 463 464 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; 465 466 /* 467 * Switch the port around without a clock transition. 468 */ 469 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); 470 471 /* 472 * Send out a clock pulse to signal we want the status 473 */ 474 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, 475 sbm_mdio); 476 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); 477 478 /* 479 * If an error occurred, the PHY will signal '1' back 480 */ 481 error = __raw_readq(sbm_mdio) & M_MAC_MDIO_IN; 482 483 /* 484 * Issue an 'idle' clock pulse, but keep the direction 485 * the same. 486 */ 487 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, 488 sbm_mdio); 489 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); 490 491 regval = 0; 492 493 for (idx = 0; idx < 16; idx++) { 494 regval <<= 1; 495 496 if (error == 0) { 497 if (__raw_readq(sbm_mdio) & M_MAC_MDIO_IN) 498 regval |= 1; 499 } 500 501 __raw_writeq(M_MAC_MDIO_DIR_INPUT | M_MAC_MDC | mac_mdio_genc, 502 sbm_mdio); 503 __raw_writeq(M_MAC_MDIO_DIR_INPUT | mac_mdio_genc, sbm_mdio); 504 } 505 506 /* Switch back to output */ 507 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio); 508 509 if (error == 0) 510 return regval; 511 return 0xffff; 512} 513 514 515/********************************************************************** 516 * SBMAC_MII_WRITE(bus, phyaddr, regidx, regval) 517 * 518 * Write a value to a PHY register. 519 * 520 * Input parameters: 521 * bus - MDIO bus handle 522 * phyaddr - PHY to use 523 * regidx - register within the PHY 524 * regval - data to write to register 525 * 526 * Return value: 527 * 0 for success 528 ********************************************************************* */ 529 530static int sbmac_mii_write(struct mii_bus *bus, int phyaddr, int regidx, 531 u16 regval) 532{ 533 struct sbmac_softc *sc = (struct sbmac_softc *)bus->priv; 534 void __iomem *sbm_mdio = sc->sbm_mdio; 535 int mac_mdio_genc; 536 537 sbmac_mii_sync(sbm_mdio); 538 539 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_START, 2); 540 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_WRITE, 2); 541 sbmac_mii_senddata(sbm_mdio, phyaddr, 5); 542 sbmac_mii_senddata(sbm_mdio, regidx, 5); 543 sbmac_mii_senddata(sbm_mdio, MII_COMMAND_ACK, 2); 544 sbmac_mii_senddata(sbm_mdio, regval, 16); 545 546 mac_mdio_genc = __raw_readq(sbm_mdio) & M_MAC_GENC; 547 548 __raw_writeq(M_MAC_MDIO_DIR_OUTPUT | mac_mdio_genc, sbm_mdio); 549 550 return 0; 551} 552 553 554 555/********************************************************************** 556 * SBDMA_INITCTX(d,s,chan,txrx,maxdescr) 557 * 558 * Initialize a DMA channel context. Since there are potentially 559 * eight DMA channels per MAC, it's nice to do this in a standard 560 * way. 561 * 562 * Input parameters: 563 * d - struct sbmacdma (DMA channel context) 564 * s - struct sbmac_softc (pointer to a MAC) 565 * chan - channel number (0..1 right now) 566 * txrx - Identifies DMA_TX or DMA_RX for channel direction 567 * maxdescr - number of descriptors 568 * 569 * Return value: 570 * nothing 571 ********************************************************************* */ 572 573static void sbdma_initctx(struct sbmacdma *d, struct sbmac_softc *s, int chan, 574 int txrx, int maxdescr) 575{ 576#ifdef CONFIG_SBMAC_COALESCE 577 int int_pktcnt, int_timeout; 578#endif 579 580 /* 581 * Save away interesting stuff in the structure 582 */ 583 584 d->sbdma_eth = s; 585 d->sbdma_channel = chan; 586 d->sbdma_txdir = txrx; 587 588#if 0 589 /* RMON clearing */ 590 s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING; 591#endif 592 593 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BYTES); 594 __raw_writeq(0, s->sbm_base + R_MAC_RMON_COLLISIONS); 595 __raw_writeq(0, s->sbm_base + R_MAC_RMON_LATE_COL); 596 __raw_writeq(0, s->sbm_base + R_MAC_RMON_EX_COL); 597 __raw_writeq(0, s->sbm_base + R_MAC_RMON_FCS_ERROR); 598 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_ABORT); 599 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_BAD); 600 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_GOOD); 601 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_RUNT); 602 __raw_writeq(0, s->sbm_base + R_MAC_RMON_TX_OVERSIZE); 603 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BYTES); 604 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_MCAST); 605 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BCAST); 606 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_BAD); 607 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_GOOD); 608 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_RUNT); 609 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_OVERSIZE); 610 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_FCS_ERROR); 611 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_LENGTH_ERROR); 612 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_CODE_ERROR); 613 __raw_writeq(0, s->sbm_base + R_MAC_RMON_RX_ALIGN_ERROR); 614 615 /* 616 * initialize register pointers 617 */ 618 619 d->sbdma_config0 = 620 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0); 621 d->sbdma_config1 = 622 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1); 623 d->sbdma_dscrbase = 624 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE); 625 d->sbdma_dscrcnt = 626 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT); 627 d->sbdma_curdscr = 628 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR); 629 if (d->sbdma_txdir) 630 d->sbdma_oodpktlost = NULL; 631 else 632 d->sbdma_oodpktlost = 633 s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_OODPKTLOST_RX); 634 635 /* 636 * Allocate memory for the ring 637 */ 638 639 d->sbdma_maxdescr = maxdescr; 640 641 d->sbdma_dscrtable_unaligned = kcalloc(d->sbdma_maxdescr + 1, 642 sizeof(*d->sbdma_dscrtable), 643 GFP_KERNEL); 644 645 /* 646 * The descriptor table must be aligned to at least 16 bytes or the 647 * MAC will corrupt it. 648 */ 649 d->sbdma_dscrtable = (struct sbdmadscr *) 650 ALIGN((unsigned long)d->sbdma_dscrtable_unaligned, 651 sizeof(*d->sbdma_dscrtable)); 652 653 d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr; 654 655 d->sbdma_dscrtable_phys = virt_to_phys(d->sbdma_dscrtable); 656 657 /* 658 * And context table 659 */ 660 661 d->sbdma_ctxtable = kcalloc(d->sbdma_maxdescr, 662 sizeof(*d->sbdma_ctxtable), GFP_KERNEL); 663 664#ifdef CONFIG_SBMAC_COALESCE 665 /* 666 * Setup Rx/Tx DMA coalescing defaults 667 */ 668 669 int_pktcnt = (txrx == DMA_TX) ? int_pktcnt_tx : int_pktcnt_rx; 670 if ( int_pktcnt ) { 671 d->sbdma_int_pktcnt = int_pktcnt; 672 } else { 673 d->sbdma_int_pktcnt = 1; 674 } 675 676 int_timeout = (txrx == DMA_TX) ? int_timeout_tx : int_timeout_rx; 677 if ( int_timeout ) { 678 d->sbdma_int_timeout = int_timeout; 679 } else { 680 d->sbdma_int_timeout = 0; 681 } 682#endif 683 684} 685 686/********************************************************************** 687 * SBDMA_CHANNEL_START(d) 688 * 689 * Initialize the hardware registers for a DMA channel. 690 * 691 * Input parameters: 692 * d - DMA channel to init (context must be previously init'd 693 * rxtx - DMA_RX or DMA_TX depending on what type of channel 694 * 695 * Return value: 696 * nothing 697 ********************************************************************* */ 698 699static void sbdma_channel_start(struct sbmacdma *d, int rxtx) 700{ 701 /* 702 * Turn on the DMA channel 703 */ 704 705#ifdef CONFIG_SBMAC_COALESCE 706 __raw_writeq(V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) | 707 0, d->sbdma_config1); 708 __raw_writeq(M_DMA_EOP_INT_EN | 709 V_DMA_RINGSZ(d->sbdma_maxdescr) | 710 V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) | 711 0, d->sbdma_config0); 712#else 713 __raw_writeq(0, d->sbdma_config1); 714 __raw_writeq(V_DMA_RINGSZ(d->sbdma_maxdescr) | 715 0, d->sbdma_config0); 716#endif 717 718 __raw_writeq(d->sbdma_dscrtable_phys, d->sbdma_dscrbase); 719 720 /* 721 * Initialize ring pointers 722 */ 723 724 d->sbdma_addptr = d->sbdma_dscrtable; 725 d->sbdma_remptr = d->sbdma_dscrtable; 726} 727 728/********************************************************************** 729 * SBDMA_CHANNEL_STOP(d) 730 * 731 * Initialize the hardware registers for a DMA channel. 732 * 733 * Input parameters: 734 * d - DMA channel to init (context must be previously init'd 735 * 736 * Return value: 737 * nothing 738 ********************************************************************* */ 739 740static void sbdma_channel_stop(struct sbmacdma *d) 741{ 742 /* 743 * Turn off the DMA channel 744 */ 745 746 __raw_writeq(0, d->sbdma_config1); 747 748 __raw_writeq(0, d->sbdma_dscrbase); 749 750 __raw_writeq(0, d->sbdma_config0); 751 752 /* 753 * Zero ring pointers 754 */ 755 756 d->sbdma_addptr = NULL; 757 d->sbdma_remptr = NULL; 758} 759 760static inline void sbdma_align_skb(struct sk_buff *skb, 761 unsigned int power2, unsigned int offset) 762{ 763 unsigned char *addr = skb->data; 764 unsigned char *newaddr = PTR_ALIGN(addr, power2); 765 766 skb_reserve(skb, newaddr - addr + offset); 767} 768 769 770/********************************************************************** 771 * SBDMA_ADD_RCVBUFFER(d,sb) 772 * 773 * Add a buffer to the specified DMA channel. For receive channels, 774 * this queues a buffer for inbound packets. 775 * 776 * Input parameters: 777 * sc - softc structure 778 * d - DMA channel descriptor 779 * sb - sk_buff to add, or NULL if we should allocate one 780 * 781 * Return value: 782 * 0 if buffer could not be added (ring is full) 783 * 1 if buffer added successfully 784 ********************************************************************* */ 785 786 787static int sbdma_add_rcvbuffer(struct sbmac_softc *sc, struct sbmacdma *d, 788 struct sk_buff *sb) 789{ 790 struct net_device *dev = sc->sbm_dev; 791 struct sbdmadscr *dsc; 792 struct sbdmadscr *nextdsc; 793 struct sk_buff *sb_new = NULL; 794 int pktsize = ENET_PACKET_SIZE; 795 796 /* get pointer to our current place in the ring */ 797 798 dsc = d->sbdma_addptr; 799 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); 800 801 /* 802 * figure out if the ring is full - if the next descriptor 803 * is the same as the one that we're going to remove from 804 * the ring, the ring is full 805 */ 806 807 if (nextdsc == d->sbdma_remptr) { 808 return -ENOSPC; 809 } 810 811 /* 812 * Allocate a sk_buff if we don't already have one. 813 * If we do have an sk_buff, reset it so that it's empty. 814 * 815 * Note: sk_buffs don't seem to be guaranteed to have any sort 816 * of alignment when they are allocated. Therefore, allocate enough 817 * extra space to make sure that: 818 * 819 * 1. the data does not start in the middle of a cache line. 820 * 2. The data does not end in the middle of a cache line 821 * 3. The buffer can be aligned such that the IP addresses are 822 * naturally aligned. 823 * 824 * Remember, the SOCs MAC writes whole cache lines at a time, 825 * without reading the old contents first. So, if the sk_buff's 826 * data portion starts in the middle of a cache line, the SOC 827 * DMA will trash the beginning (and ending) portions. 828 */ 829 830 if (sb == NULL) { 831 sb_new = netdev_alloc_skb(dev, ENET_PACKET_SIZE + 832 SMP_CACHE_BYTES * 2 + 833 NET_IP_ALIGN); 834 if (sb_new == NULL) { 835 pr_info("%s: sk_buff allocation failed\n", 836 d->sbdma_eth->sbm_dev->name); 837 return -ENOBUFS; 838 } 839 840 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, NET_IP_ALIGN); 841 } 842 else { 843 sb_new = sb; 844 /* 845 * nothing special to reinit buffer, it's already aligned 846 * and sb->data already points to a good place. 847 */ 848 } 849 850 /* 851 * fill in the descriptor 852 */ 853 854#ifdef CONFIG_SBMAC_COALESCE 855 /* 856 * Do not interrupt per DMA transfer. 857 */ 858 dsc->dscr_a = virt_to_phys(sb_new->data) | 859 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | 0; 860#else 861 dsc->dscr_a = virt_to_phys(sb_new->data) | 862 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize + NET_IP_ALIGN)) | 863 M_DMA_DSCRA_INTERRUPT; 864#endif 865 866 /* receiving: no options */ 867 dsc->dscr_b = 0; 868 869 /* 870 * fill in the context 871 */ 872 873 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new; 874 875 /* 876 * point at next packet 877 */ 878 879 d->sbdma_addptr = nextdsc; 880 881 /* 882 * Give the buffer to the DMA engine. 883 */ 884 885 __raw_writeq(1, d->sbdma_dscrcnt); 886 887 return 0; /* we did it */ 888} 889 890/********************************************************************** 891 * SBDMA_ADD_TXBUFFER(d,sb) 892 * 893 * Add a transmit buffer to the specified DMA channel, causing a 894 * transmit to start. 895 * 896 * Input parameters: 897 * d - DMA channel descriptor 898 * sb - sk_buff to add 899 * 900 * Return value: 901 * 0 transmit queued successfully 902 * otherwise error code 903 ********************************************************************* */ 904 905 906static int sbdma_add_txbuffer(struct sbmacdma *d, struct sk_buff *sb) 907{ 908 struct sbdmadscr *dsc; 909 struct sbdmadscr *nextdsc; 910 uint64_t phys; 911 uint64_t ncb; 912 int length; 913 914 /* get pointer to our current place in the ring */ 915 916 dsc = d->sbdma_addptr; 917 nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr); 918 919 /* 920 * figure out if the ring is full - if the next descriptor 921 * is the same as the one that we're going to remove from 922 * the ring, the ring is full 923 */ 924 925 if (nextdsc == d->sbdma_remptr) { 926 return -ENOSPC; 927 } 928 929 /* 930 * Under Linux, it's not necessary to copy/coalesce buffers 931 * like it is on NetBSD. We think they're all contiguous, 932 * but that may not be true for GBE. 933 */ 934 935 length = sb->len; 936 937 /* 938 * fill in the descriptor. Note that the number of cache 939 * blocks in the descriptor is the number of blocks 940 * *spanned*, so we need to add in the offset (if any) 941 * while doing the calculation. 942 */ 943 944 phys = virt_to_phys(sb->data); 945 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1))); 946 947 dsc->dscr_a = phys | 948 V_DMA_DSCRA_A_SIZE(ncb) | 949#ifndef CONFIG_SBMAC_COALESCE 950 M_DMA_DSCRA_INTERRUPT | 951#endif 952 M_DMA_ETHTX_SOP; 953 954 /* transmitting: set outbound options and length */ 955 956 dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) | 957 V_DMA_DSCRB_PKT_SIZE(length); 958 959 /* 960 * fill in the context 961 */ 962 963 d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb; 964 965 /* 966 * point at next packet 967 */ 968 969 d->sbdma_addptr = nextdsc; 970 971 /* 972 * Give the buffer to the DMA engine. 973 */ 974 975 __raw_writeq(1, d->sbdma_dscrcnt); 976 977 return 0; /* we did it */ 978} 979 980 981 982 983/********************************************************************** 984 * SBDMA_EMPTYRING(d) 985 * 986 * Free all allocated sk_buffs on the specified DMA channel; 987 * 988 * Input parameters: 989 * d - DMA channel 990 * 991 * Return value: 992 * nothing 993 ********************************************************************* */ 994 995static void sbdma_emptyring(struct sbmacdma *d) 996{ 997 int idx; 998 struct sk_buff *sb; 999 1000 for (idx = 0; idx < d->sbdma_maxdescr; idx++) { 1001 sb = d->sbdma_ctxtable[idx]; 1002 if (sb) { 1003 dev_kfree_skb(sb); 1004 d->sbdma_ctxtable[idx] = NULL; 1005 } 1006 } 1007} 1008 1009 1010/********************************************************************** 1011 * SBDMA_FILLRING(d) 1012 * 1013 * Fill the specified DMA channel (must be receive channel) 1014 * with sk_buffs 1015 * 1016 * Input parameters: 1017 * sc - softc structure 1018 * d - DMA channel 1019 * 1020 * Return value: 1021 * nothing 1022 ********************************************************************* */ 1023 1024static void sbdma_fillring(struct sbmac_softc *sc, struct sbmacdma *d) 1025{ 1026 int idx; 1027 1028 for (idx = 0; idx < SBMAC_MAX_RXDESCR - 1; idx++) { 1029 if (sbdma_add_rcvbuffer(sc, d, NULL) != 0) 1030 break; 1031 } 1032} 1033 1034#ifdef CONFIG_NET_POLL_CONTROLLER 1035static void sbmac_netpoll(struct net_device *netdev) 1036{ 1037 struct sbmac_softc *sc = netdev_priv(netdev); 1038 int irq = sc->sbm_dev->irq; 1039 1040 __raw_writeq(0, sc->sbm_imr); 1041 1042 sbmac_intr(irq, netdev); 1043 1044#ifdef CONFIG_SBMAC_COALESCE 1045 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | 1046 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), 1047 sc->sbm_imr); 1048#else 1049 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 1050 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr); 1051#endif 1052} 1053#endif 1054 1055/********************************************************************** 1056 * SBDMA_RX_PROCESS(sc,d,work_to_do,poll) 1057 * 1058 * Process "completed" receive buffers on the specified DMA channel. 1059 * 1060 * Input parameters: 1061 * sc - softc structure 1062 * d - DMA channel context 1063 * work_to_do - no. of packets to process before enabling interrupt 1064 * again (for NAPI) 1065 * poll - 1: using polling (for NAPI) 1066 * 1067 * Return value: 1068 * nothing 1069 ********************************************************************* */ 1070 1071static int sbdma_rx_process(struct sbmac_softc *sc, struct sbmacdma *d, 1072 int work_to_do, int poll) 1073{ 1074 struct net_device *dev = sc->sbm_dev; 1075 int curidx; 1076 int hwidx; 1077 struct sbdmadscr *dsc; 1078 struct sk_buff *sb; 1079 int len; 1080 int work_done = 0; 1081 int dropped = 0; 1082 1083 prefetch(d); 1084 1085again: 1086 /* Check if the HW dropped any frames */ 1087 dev->stats.rx_fifo_errors 1088 += __raw_readq(sc->sbm_rxdma.sbdma_oodpktlost) & 0xffff; 1089 __raw_writeq(0, sc->sbm_rxdma.sbdma_oodpktlost); 1090 1091 while (work_to_do-- > 0) { 1092 /* 1093 * figure out where we are (as an index) and where 1094 * the hardware is (also as an index) 1095 * 1096 * This could be done faster if (for example) the 1097 * descriptor table was page-aligned and contiguous in 1098 * both virtual and physical memory -- you could then 1099 * just compare the low-order bits of the virtual address 1100 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 1101 */ 1102 1103 dsc = d->sbdma_remptr; 1104 curidx = dsc - d->sbdma_dscrtable; 1105 1106 prefetch(dsc); 1107 prefetch(&d->sbdma_ctxtable[curidx]); 1108 1109 hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 1110 d->sbdma_dscrtable_phys) / 1111 sizeof(*d->sbdma_dscrtable); 1112 1113 /* 1114 * If they're the same, that means we've processed all 1115 * of the descriptors up to (but not including) the one that 1116 * the hardware is working on right now. 1117 */ 1118 1119 if (curidx == hwidx) 1120 goto done; 1121 1122 /* 1123 * Otherwise, get the packet's sk_buff ptr back 1124 */ 1125 1126 sb = d->sbdma_ctxtable[curidx]; 1127 d->sbdma_ctxtable[curidx] = NULL; 1128 1129 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4; 1130 1131 /* 1132 * Check packet status. If good, process it. 1133 * If not, silently drop it and put it back on the 1134 * receive ring. 1135 */ 1136 1137 if (likely (!(dsc->dscr_a & M_DMA_ETHRX_BAD))) { 1138 1139 /* 1140 * Add a new buffer to replace the old one. If we fail 1141 * to allocate a buffer, we're going to drop this 1142 * packet and put it right back on the receive ring. 1143 */ 1144 1145 if (unlikely(sbdma_add_rcvbuffer(sc, d, NULL) == 1146 -ENOBUFS)) { 1147 dev->stats.rx_dropped++; 1148 /* Re-add old buffer */ 1149 sbdma_add_rcvbuffer(sc, d, sb); 1150 /* No point in continuing at the moment */ 1151 printk(KERN_ERR "dropped packet (1)\n"); 1152 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); 1153 goto done; 1154 } else { 1155 /* 1156 * Set length into the packet 1157 */ 1158 skb_put(sb,len); 1159 1160 /* 1161 * Buffer has been replaced on the 1162 * receive ring. Pass the buffer to 1163 * the kernel 1164 */ 1165 sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev); 1166 /* Check hw IPv4/TCP checksum if supported */ 1167 if (sc->rx_hw_checksum == ENABLE) { 1168 if (!((dsc->dscr_a) & M_DMA_ETHRX_BADIP4CS) && 1169 !((dsc->dscr_a) & M_DMA_ETHRX_BADTCPCS)) { 1170 sb->ip_summed = CHECKSUM_UNNECESSARY; 1171 /* don't need to set sb->csum */ 1172 } else { 1173 skb_checksum_none_assert(sb); 1174 } 1175 } 1176 prefetch(sb->data); 1177 prefetch((const void *)(((char *)sb->data)+32)); 1178 if (poll) 1179 dropped = netif_receive_skb(sb); 1180 else 1181 dropped = netif_rx(sb); 1182 1183 if (dropped == NET_RX_DROP) { 1184 dev->stats.rx_dropped++; 1185 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); 1186 goto done; 1187 } 1188 else { 1189 dev->stats.rx_bytes += len; 1190 dev->stats.rx_packets++; 1191 } 1192 } 1193 } else { 1194 /* 1195 * Packet was mangled somehow. Just drop it and 1196 * put it back on the receive ring. 1197 */ 1198 dev->stats.rx_errors++; 1199 sbdma_add_rcvbuffer(sc, d, sb); 1200 } 1201 1202 1203 /* 1204 * .. and advance to the next buffer. 1205 */ 1206 1207 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); 1208 work_done++; 1209 } 1210 if (!poll) { 1211 work_to_do = 32; 1212 goto again; /* collect fifo drop statistics again */ 1213 } 1214done: 1215 return work_done; 1216} 1217 1218/********************************************************************** 1219 * SBDMA_TX_PROCESS(sc,d) 1220 * 1221 * Process "completed" transmit buffers on the specified DMA channel. 1222 * This is normally called within the interrupt service routine. 1223 * Note that this isn't really ideal for priority channels, since 1224 * it processes all of the packets on a given channel before 1225 * returning. 1226 * 1227 * Input parameters: 1228 * sc - softc structure 1229 * d - DMA channel context 1230 * poll - 1: using polling (for NAPI) 1231 * 1232 * Return value: 1233 * nothing 1234 ********************************************************************* */ 1235 1236static void sbdma_tx_process(struct sbmac_softc *sc, struct sbmacdma *d, 1237 int poll) 1238{ 1239 struct net_device *dev = sc->sbm_dev; 1240 int curidx; 1241 int hwidx; 1242 struct sbdmadscr *dsc; 1243 struct sk_buff *sb; 1244 unsigned long flags; 1245 int packets_handled = 0; 1246 1247 spin_lock_irqsave(&(sc->sbm_lock), flags); 1248 1249 if (d->sbdma_remptr == d->sbdma_addptr) 1250 goto end_unlock; 1251 1252 hwidx = ((__raw_readq(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) - 1253 d->sbdma_dscrtable_phys) / sizeof(*d->sbdma_dscrtable); 1254 1255 for (;;) { 1256 /* 1257 * figure out where we are (as an index) and where 1258 * the hardware is (also as an index) 1259 * 1260 * This could be done faster if (for example) the 1261 * descriptor table was page-aligned and contiguous in 1262 * both virtual and physical memory -- you could then 1263 * just compare the low-order bits of the virtual address 1264 * (sbdma_remptr) and the physical address (sbdma_curdscr CSR) 1265 */ 1266 1267 curidx = d->sbdma_remptr - d->sbdma_dscrtable; 1268 1269 /* 1270 * If they're the same, that means we've processed all 1271 * of the descriptors up to (but not including) the one that 1272 * the hardware is working on right now. 1273 */ 1274 1275 if (curidx == hwidx) 1276 break; 1277 1278 /* 1279 * Otherwise, get the packet's sk_buff ptr back 1280 */ 1281 1282 dsc = &(d->sbdma_dscrtable[curidx]); 1283 sb = d->sbdma_ctxtable[curidx]; 1284 d->sbdma_ctxtable[curidx] = NULL; 1285 1286 /* 1287 * Stats 1288 */ 1289 1290 dev->stats.tx_bytes += sb->len; 1291 dev->stats.tx_packets++; 1292 1293 /* 1294 * for transmits, we just free buffers. 1295 */ 1296 1297 dev_kfree_skb_irq(sb); 1298 1299 /* 1300 * .. and advance to the next buffer. 1301 */ 1302 1303 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr); 1304 1305 packets_handled++; 1306 1307 } 1308 1309 /* 1310 * Decide if we should wake up the protocol or not. 1311 * Other drivers seem to do this when we reach a low 1312 * watermark on the transmit queue. 1313 */ 1314 1315 if (packets_handled) 1316 netif_wake_queue(d->sbdma_eth->sbm_dev); 1317 1318end_unlock: 1319 spin_unlock_irqrestore(&(sc->sbm_lock), flags); 1320 1321} 1322 1323 1324 1325/********************************************************************** 1326 * SBMAC_INITCTX(s) 1327 * 1328 * Initialize an Ethernet context structure - this is called 1329 * once per MAC on the 1250. Memory is allocated here, so don't 1330 * call it again from inside the ioctl routines that bring the 1331 * interface up/down 1332 * 1333 * Input parameters: 1334 * s - sbmac context structure 1335 * 1336 * Return value: 1337 * 0 1338 ********************************************************************* */ 1339 1340static int sbmac_initctx(struct sbmac_softc *s) 1341{ 1342 1343 /* 1344 * figure out the addresses of some ports 1345 */ 1346 1347 s->sbm_macenable = s->sbm_base + R_MAC_ENABLE; 1348 s->sbm_maccfg = s->sbm_base + R_MAC_CFG; 1349 s->sbm_fifocfg = s->sbm_base + R_MAC_THRSH_CFG; 1350 s->sbm_framecfg = s->sbm_base + R_MAC_FRAMECFG; 1351 s->sbm_rxfilter = s->sbm_base + R_MAC_ADFILTER_CFG; 1352 s->sbm_isr = s->sbm_base + R_MAC_STATUS; 1353 s->sbm_imr = s->sbm_base + R_MAC_INT_MASK; 1354 s->sbm_mdio = s->sbm_base + R_MAC_MDIO; 1355 1356 /* 1357 * Initialize the DMA channels. Right now, only one per MAC is used 1358 * Note: Only do this _once_, as it allocates memory from the kernel! 1359 */ 1360 1361 sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR); 1362 sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR); 1363 1364 /* 1365 * initial state is OFF 1366 */ 1367 1368 s->sbm_state = sbmac_state_off; 1369 1370 return 0; 1371} 1372 1373 1374static void sbdma_uninitctx(struct sbmacdma *d) 1375{ 1376 if (d->sbdma_dscrtable_unaligned) { 1377 kfree(d->sbdma_dscrtable_unaligned); 1378 d->sbdma_dscrtable_unaligned = d->sbdma_dscrtable = NULL; 1379 } 1380 1381 if (d->sbdma_ctxtable) { 1382 kfree(d->sbdma_ctxtable); 1383 d->sbdma_ctxtable = NULL; 1384 } 1385} 1386 1387 1388static void sbmac_uninitctx(struct sbmac_softc *sc) 1389{ 1390 sbdma_uninitctx(&(sc->sbm_txdma)); 1391 sbdma_uninitctx(&(sc->sbm_rxdma)); 1392} 1393 1394 1395/********************************************************************** 1396 * SBMAC_CHANNEL_START(s) 1397 * 1398 * Start packet processing on this MAC. 1399 * 1400 * Input parameters: 1401 * s - sbmac structure 1402 * 1403 * Return value: 1404 * nothing 1405 ********************************************************************* */ 1406 1407static void sbmac_channel_start(struct sbmac_softc *s) 1408{ 1409 uint64_t reg; 1410 void __iomem *port; 1411 uint64_t cfg,fifo,framecfg; 1412 int idx, th_value; 1413 1414 /* 1415 * Don't do this if running 1416 */ 1417 1418 if (s->sbm_state == sbmac_state_on) 1419 return; 1420 1421 /* 1422 * Bring the controller out of reset, but leave it off. 1423 */ 1424 1425 __raw_writeq(0, s->sbm_macenable); 1426 1427 /* 1428 * Ignore all received packets 1429 */ 1430 1431 __raw_writeq(0, s->sbm_rxfilter); 1432 1433 /* 1434 * Calculate values for various control registers. 1435 */ 1436 1437 cfg = M_MAC_RETRY_EN | 1438 M_MAC_TX_HOLD_SOP_EN | 1439 V_MAC_TX_PAUSE_CNT_16K | 1440 M_MAC_AP_STAT_EN | 1441 M_MAC_FAST_SYNC | 1442 M_MAC_SS_EN | 1443 0; 1444 1445 /* 1446 * Be sure that RD_THRSH+WR_THRSH <= 32 for pass1 pars 1447 * and make sure that RD_THRSH + WR_THRSH <=128 for pass2 and above 1448 * Use a larger RD_THRSH for gigabit 1449 */ 1450 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) 1451 th_value = 28; 1452 else 1453 th_value = 64; 1454 1455 fifo = V_MAC_TX_WR_THRSH(4) | /* Must be '4' or '8' */ 1456 ((s->sbm_speed == sbmac_speed_1000) 1457 ? V_MAC_TX_RD_THRSH(th_value) : V_MAC_TX_RD_THRSH(4)) | 1458 V_MAC_TX_RL_THRSH(4) | 1459 V_MAC_RX_PL_THRSH(4) | 1460 V_MAC_RX_RD_THRSH(4) | /* Must be '4' */ 1461 V_MAC_RX_RL_THRSH(8) | 1462 0; 1463 1464 framecfg = V_MAC_MIN_FRAMESZ_DEFAULT | 1465 V_MAC_MAX_FRAMESZ_DEFAULT | 1466 V_MAC_BACKOFF_SEL(1); 1467 1468 /* 1469 * Clear out the hash address map 1470 */ 1471 1472 port = s->sbm_base + R_MAC_HASH_BASE; 1473 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 1474 __raw_writeq(0, port); 1475 port += sizeof(uint64_t); 1476 } 1477 1478 /* 1479 * Clear out the exact-match table 1480 */ 1481 1482 port = s->sbm_base + R_MAC_ADDR_BASE; 1483 for (idx = 0; idx < MAC_ADDR_COUNT; idx++) { 1484 __raw_writeq(0, port); 1485 port += sizeof(uint64_t); 1486 } 1487 1488 /* 1489 * Clear out the DMA Channel mapping table registers 1490 */ 1491 1492 port = s->sbm_base + R_MAC_CHUP0_BASE; 1493 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1494 __raw_writeq(0, port); 1495 port += sizeof(uint64_t); 1496 } 1497 1498 1499 port = s->sbm_base + R_MAC_CHLO0_BASE; 1500 for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) { 1501 __raw_writeq(0, port); 1502 port += sizeof(uint64_t); 1503 } 1504 1505 /* 1506 * Program the hardware address. It goes into the hardware-address 1507 * register as well as the first filter register. 1508 */ 1509 1510 reg = sbmac_addr2reg(s->sbm_hwaddr); 1511 1512 port = s->sbm_base + R_MAC_ADDR_BASE; 1513 __raw_writeq(reg, port); 1514 port = s->sbm_base + R_MAC_ETHERNET_ADDR; 1515 1516#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS 1517 /* 1518 * Pass1 SOCs do not receive packets addressed to the 1519 * destination address in the R_MAC_ETHERNET_ADDR register. 1520 * Set the value to zero. 1521 */ 1522 __raw_writeq(0, port); 1523#else 1524 __raw_writeq(reg, port); 1525#endif 1526 1527 /* 1528 * Set the receive filter for no packets, and write values 1529 * to the various config registers 1530 */ 1531 1532 __raw_writeq(0, s->sbm_rxfilter); 1533 __raw_writeq(0, s->sbm_imr); 1534 __raw_writeq(framecfg, s->sbm_framecfg); 1535 __raw_writeq(fifo, s->sbm_fifocfg); 1536 __raw_writeq(cfg, s->sbm_maccfg); 1537 1538 /* 1539 * Initialize DMA channels (rings should be ok now) 1540 */ 1541 1542 sbdma_channel_start(&(s->sbm_rxdma), DMA_RX); 1543 sbdma_channel_start(&(s->sbm_txdma), DMA_TX); 1544 1545 /* 1546 * Configure the speed, duplex, and flow control 1547 */ 1548 1549 sbmac_set_speed(s,s->sbm_speed); 1550 sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc); 1551 1552 /* 1553 * Fill the receive ring 1554 */ 1555 1556 sbdma_fillring(s, &(s->sbm_rxdma)); 1557 1558 /* 1559 * Turn on the rest of the bits in the enable register 1560 */ 1561 1562#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) 1563 __raw_writeq(M_MAC_RXDMA_EN0 | 1564 M_MAC_TXDMA_EN0, s->sbm_macenable); 1565#elif defined(CONFIG_SIBYTE_SB1250) || defined(CONFIG_SIBYTE_BCM112X) 1566 __raw_writeq(M_MAC_RXDMA_EN0 | 1567 M_MAC_TXDMA_EN0 | 1568 M_MAC_RX_ENABLE | 1569 M_MAC_TX_ENABLE, s->sbm_macenable); 1570#else 1571#error invalid SiByte MAC configuration 1572#endif 1573 1574#ifdef CONFIG_SBMAC_COALESCE 1575 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | 1576 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), s->sbm_imr); 1577#else 1578 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 1579 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), s->sbm_imr); 1580#endif 1581 1582 /* 1583 * Enable receiving unicasts and broadcasts 1584 */ 1585 1586 __raw_writeq(M_MAC_UCAST_EN | M_MAC_BCAST_EN, s->sbm_rxfilter); 1587 1588 /* 1589 * we're running now. 1590 */ 1591 1592 s->sbm_state = sbmac_state_on; 1593 1594 /* 1595 * Program multicast addresses 1596 */ 1597 1598 sbmac_setmulti(s); 1599 1600 /* 1601 * If channel was in promiscuous mode before, turn that on 1602 */ 1603 1604 if (s->sbm_devflags & IFF_PROMISC) { 1605 sbmac_promiscuous_mode(s,1); 1606 } 1607 1608} 1609 1610 1611/********************************************************************** 1612 * SBMAC_CHANNEL_STOP(s) 1613 * 1614 * Stop packet processing on this MAC. 1615 * 1616 * Input parameters: 1617 * s - sbmac structure 1618 * 1619 * Return value: 1620 * nothing 1621 ********************************************************************* */ 1622 1623static void sbmac_channel_stop(struct sbmac_softc *s) 1624{ 1625 /* don't do this if already stopped */ 1626 1627 if (s->sbm_state == sbmac_state_off) 1628 return; 1629 1630 /* don't accept any packets, disable all interrupts */ 1631 1632 __raw_writeq(0, s->sbm_rxfilter); 1633 __raw_writeq(0, s->sbm_imr); 1634 1635 /* Turn off ticker */ 1636 1637 /* XXX */ 1638 1639 /* turn off receiver and transmitter */ 1640 1641 __raw_writeq(0, s->sbm_macenable); 1642 1643 /* We're stopped now. */ 1644 1645 s->sbm_state = sbmac_state_off; 1646 1647 /* 1648 * Stop DMA channels (rings should be ok now) 1649 */ 1650 1651 sbdma_channel_stop(&(s->sbm_rxdma)); 1652 sbdma_channel_stop(&(s->sbm_txdma)); 1653 1654 /* Empty the receive and transmit rings */ 1655 1656 sbdma_emptyring(&(s->sbm_rxdma)); 1657 sbdma_emptyring(&(s->sbm_txdma)); 1658 1659} 1660 1661/********************************************************************** 1662 * SBMAC_SET_CHANNEL_STATE(state) 1663 * 1664 * Set the channel's state ON or OFF 1665 * 1666 * Input parameters: 1667 * state - new state 1668 * 1669 * Return value: 1670 * old state 1671 ********************************************************************* */ 1672static enum sbmac_state sbmac_set_channel_state(struct sbmac_softc *sc, 1673 enum sbmac_state state) 1674{ 1675 enum sbmac_state oldstate = sc->sbm_state; 1676 1677 /* 1678 * If same as previous state, return 1679 */ 1680 1681 if (state == oldstate) { 1682 return oldstate; 1683 } 1684 1685 /* 1686 * If new state is ON, turn channel on 1687 */ 1688 1689 if (state == sbmac_state_on) { 1690 sbmac_channel_start(sc); 1691 } 1692 else { 1693 sbmac_channel_stop(sc); 1694 } 1695 1696 /* 1697 * Return previous state 1698 */ 1699 1700 return oldstate; 1701} 1702 1703 1704/********************************************************************** 1705 * SBMAC_PROMISCUOUS_MODE(sc,onoff) 1706 * 1707 * Turn on or off promiscuous mode 1708 * 1709 * Input parameters: 1710 * sc - softc 1711 * onoff - 1 to turn on, 0 to turn off 1712 * 1713 * Return value: 1714 * nothing 1715 ********************************************************************* */ 1716 1717static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff) 1718{ 1719 uint64_t reg; 1720 1721 if (sc->sbm_state != sbmac_state_on) 1722 return; 1723 1724 if (onoff) { 1725 reg = __raw_readq(sc->sbm_rxfilter); 1726 reg |= M_MAC_ALLPKT_EN; 1727 __raw_writeq(reg, sc->sbm_rxfilter); 1728 } 1729 else { 1730 reg = __raw_readq(sc->sbm_rxfilter); 1731 reg &= ~M_MAC_ALLPKT_EN; 1732 __raw_writeq(reg, sc->sbm_rxfilter); 1733 } 1734} 1735 1736/********************************************************************** 1737 * SBMAC_SETIPHDR_OFFSET(sc,onoff) 1738 * 1739 * Set the iphdr offset as 15 assuming ethernet encapsulation 1740 * 1741 * Input parameters: 1742 * sc - softc 1743 * 1744 * Return value: 1745 * nothing 1746 ********************************************************************* */ 1747 1748static void sbmac_set_iphdr_offset(struct sbmac_softc *sc) 1749{ 1750 uint64_t reg; 1751 1752 /* Hard code the off set to 15 for now */ 1753 reg = __raw_readq(sc->sbm_rxfilter); 1754 reg &= ~M_MAC_IPHDR_OFFSET | V_MAC_IPHDR_OFFSET(15); 1755 __raw_writeq(reg, sc->sbm_rxfilter); 1756 1757 /* BCM1250 pass1 didn't have hardware checksum. Everything 1758 later does. */ 1759 if (soc_type == K_SYS_SOC_TYPE_BCM1250 && periph_rev < 2) { 1760 sc->rx_hw_checksum = DISABLE; 1761 } else { 1762 sc->rx_hw_checksum = ENABLE; 1763 } 1764} 1765 1766 1767/********************************************************************** 1768 * SBMAC_ADDR2REG(ptr) 1769 * 1770 * Convert six bytes into the 64-bit register value that 1771 * we typically write into the SBMAC's address/mcast registers 1772 * 1773 * Input parameters: 1774 * ptr - pointer to 6 bytes 1775 * 1776 * Return value: 1777 * register value 1778 ********************************************************************* */ 1779 1780static uint64_t sbmac_addr2reg(unsigned char *ptr) 1781{ 1782 uint64_t reg = 0; 1783 1784 ptr += 6; 1785 1786 reg |= (uint64_t) *(--ptr); 1787 reg <<= 8; 1788 reg |= (uint64_t) *(--ptr); 1789 reg <<= 8; 1790 reg |= (uint64_t) *(--ptr); 1791 reg <<= 8; 1792 reg |= (uint64_t) *(--ptr); 1793 reg <<= 8; 1794 reg |= (uint64_t) *(--ptr); 1795 reg <<= 8; 1796 reg |= (uint64_t) *(--ptr); 1797 1798 return reg; 1799} 1800 1801 1802/********************************************************************** 1803 * SBMAC_SET_SPEED(s,speed) 1804 * 1805 * Configure LAN speed for the specified MAC. 1806 * Warning: must be called when MAC is off! 1807 * 1808 * Input parameters: 1809 * s - sbmac structure 1810 * speed - speed to set MAC to (see enum sbmac_speed) 1811 * 1812 * Return value: 1813 * 1 if successful 1814 * 0 indicates invalid parameters 1815 ********************************************************************* */ 1816 1817static int sbmac_set_speed(struct sbmac_softc *s, enum sbmac_speed speed) 1818{ 1819 uint64_t cfg; 1820 uint64_t framecfg; 1821 1822 /* 1823 * Save new current values 1824 */ 1825 1826 s->sbm_speed = speed; 1827 1828 if (s->sbm_state == sbmac_state_on) 1829 return 0; /* save for next restart */ 1830 1831 /* 1832 * Read current register values 1833 */ 1834 1835 cfg = __raw_readq(s->sbm_maccfg); 1836 framecfg = __raw_readq(s->sbm_framecfg); 1837 1838 /* 1839 * Mask out the stuff we want to change 1840 */ 1841 1842 cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL); 1843 framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH | 1844 M_MAC_SLOT_SIZE); 1845 1846 /* 1847 * Now add in the new bits 1848 */ 1849 1850 switch (speed) { 1851 case sbmac_speed_10: 1852 framecfg |= V_MAC_IFG_RX_10 | 1853 V_MAC_IFG_TX_10 | 1854 K_MAC_IFG_THRSH_10 | 1855 V_MAC_SLOT_SIZE_10; 1856 cfg |= V_MAC_SPEED_SEL_10MBPS; 1857 break; 1858 1859 case sbmac_speed_100: 1860 framecfg |= V_MAC_IFG_RX_100 | 1861 V_MAC_IFG_TX_100 | 1862 V_MAC_IFG_THRSH_100 | 1863 V_MAC_SLOT_SIZE_100; 1864 cfg |= V_MAC_SPEED_SEL_100MBPS ; 1865 break; 1866 1867 case sbmac_speed_1000: 1868 framecfg |= V_MAC_IFG_RX_1000 | 1869 V_MAC_IFG_TX_1000 | 1870 V_MAC_IFG_THRSH_1000 | 1871 V_MAC_SLOT_SIZE_1000; 1872 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN; 1873 break; 1874 1875 default: 1876 return 0; 1877 } 1878 1879 /* 1880 * Send the bits back to the hardware 1881 */ 1882 1883 __raw_writeq(framecfg, s->sbm_framecfg); 1884 __raw_writeq(cfg, s->sbm_maccfg); 1885 1886 return 1; 1887} 1888 1889/********************************************************************** 1890 * SBMAC_SET_DUPLEX(s,duplex,fc) 1891 * 1892 * Set Ethernet duplex and flow control options for this MAC 1893 * Warning: must be called when MAC is off! 1894 * 1895 * Input parameters: 1896 * s - sbmac structure 1897 * duplex - duplex setting (see enum sbmac_duplex) 1898 * fc - flow control setting (see enum sbmac_fc) 1899 * 1900 * Return value: 1901 * 1 if ok 1902 * 0 if an invalid parameter combination was specified 1903 ********************************************************************* */ 1904 1905static int sbmac_set_duplex(struct sbmac_softc *s, enum sbmac_duplex duplex, 1906 enum sbmac_fc fc) 1907{ 1908 uint64_t cfg; 1909 1910 /* 1911 * Save new current values 1912 */ 1913 1914 s->sbm_duplex = duplex; 1915 s->sbm_fc = fc; 1916 1917 if (s->sbm_state == sbmac_state_on) 1918 return 0; /* save for next restart */ 1919 1920 /* 1921 * Read current register values 1922 */ 1923 1924 cfg = __raw_readq(s->sbm_maccfg); 1925 1926 /* 1927 * Mask off the stuff we're about to change 1928 */ 1929 1930 cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN); 1931 1932 1933 switch (duplex) { 1934 case sbmac_duplex_half: 1935 switch (fc) { 1936 case sbmac_fc_disabled: 1937 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED; 1938 break; 1939 1940 case sbmac_fc_collision: 1941 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED; 1942 break; 1943 1944 case sbmac_fc_carrier: 1945 cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR; 1946 break; 1947 1948 case sbmac_fc_frame: /* not valid in half duplex */ 1949 default: /* invalid selection */ 1950 return 0; 1951 } 1952 break; 1953 1954 case sbmac_duplex_full: 1955 switch (fc) { 1956 case sbmac_fc_disabled: 1957 cfg |= V_MAC_FC_CMD_DISABLED; 1958 break; 1959 1960 case sbmac_fc_frame: 1961 cfg |= V_MAC_FC_CMD_ENABLED; 1962 break; 1963 1964 case sbmac_fc_collision: /* not valid in full duplex */ 1965 case sbmac_fc_carrier: /* not valid in full duplex */ 1966 default: 1967 return 0; 1968 } 1969 break; 1970 default: 1971 return 0; 1972 } 1973 1974 /* 1975 * Send the bits back to the hardware 1976 */ 1977 1978 __raw_writeq(cfg, s->sbm_maccfg); 1979 1980 return 1; 1981} 1982 1983 1984 1985 1986/********************************************************************** 1987 * SBMAC_INTR() 1988 * 1989 * Interrupt handler for MAC interrupts 1990 * 1991 * Input parameters: 1992 * MAC structure 1993 * 1994 * Return value: 1995 * nothing 1996 ********************************************************************* */ 1997static irqreturn_t sbmac_intr(int irq,void *dev_instance) 1998{ 1999 struct net_device *dev = (struct net_device *) dev_instance; 2000 struct sbmac_softc *sc = netdev_priv(dev); 2001 uint64_t isr; 2002 int handled = 0; 2003 2004 /* 2005 * Read the ISR (this clears the bits in the real 2006 * register, except for counter addr) 2007 */ 2008 2009 isr = __raw_readq(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR; 2010 2011 if (isr == 0) 2012 return IRQ_RETVAL(0); 2013 handled = 1; 2014 2015 /* 2016 * Transmits on channel 0 2017 */ 2018 2019 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) 2020 sbdma_tx_process(sc,&(sc->sbm_txdma), 0); 2021 2022 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) { 2023 if (napi_schedule_prep(&sc->napi)) { 2024 __raw_writeq(0, sc->sbm_imr); 2025 __napi_schedule(&sc->napi); 2026 /* Depend on the exit from poll to reenable intr */ 2027 } 2028 else { 2029 /* may leave some packets behind */ 2030 sbdma_rx_process(sc,&(sc->sbm_rxdma), 2031 SBMAC_MAX_RXDESCR * 2, 0); 2032 } 2033 } 2034 return IRQ_RETVAL(handled); 2035} 2036 2037/********************************************************************** 2038 * SBMAC_START_TX(skb,dev) 2039 * 2040 * Start output on the specified interface. Basically, we 2041 * queue as many buffers as we can until the ring fills up, or 2042 * we run off the end of the queue, whichever comes first. 2043 * 2044 * Input parameters: 2045 * 2046 * 2047 * Return value: 2048 * nothing 2049 ********************************************************************* */ 2050static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev) 2051{ 2052 struct sbmac_softc *sc = netdev_priv(dev); 2053 unsigned long flags; 2054 2055 /* lock eth irq */ 2056 spin_lock_irqsave(&sc->sbm_lock, flags); 2057 2058 /* 2059 * Put the buffer on the transmit ring. If we 2060 * don't have room, stop the queue. 2061 */ 2062 2063 if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) { 2064 /* XXX save skb that we could not send */ 2065 netif_stop_queue(dev); 2066 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2067 2068 return NETDEV_TX_BUSY; 2069 } 2070 2071 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2072 2073 return NETDEV_TX_OK; 2074} 2075 2076/********************************************************************** 2077 * SBMAC_SETMULTI(sc) 2078 * 2079 * Reprogram the multicast table into the hardware, given 2080 * the list of multicasts associated with the interface 2081 * structure. 2082 * 2083 * Input parameters: 2084 * sc - softc 2085 * 2086 * Return value: 2087 * nothing 2088 ********************************************************************* */ 2089 2090static void sbmac_setmulti(struct sbmac_softc *sc) 2091{ 2092 uint64_t reg; 2093 void __iomem *port; 2094 int idx; 2095 struct netdev_hw_addr *ha; 2096 struct net_device *dev = sc->sbm_dev; 2097 2098 /* 2099 * Clear out entire multicast table. We do this by nuking 2100 * the entire hash table and all the direct matches except 2101 * the first one, which is used for our station address 2102 */ 2103 2104 for (idx = 1; idx < MAC_ADDR_COUNT; idx++) { 2105 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t)); 2106 __raw_writeq(0, port); 2107 } 2108 2109 for (idx = 0; idx < MAC_HASH_COUNT; idx++) { 2110 port = sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t)); 2111 __raw_writeq(0, port); 2112 } 2113 2114 /* 2115 * Clear the filter to say we don't want any multicasts. 2116 */ 2117 2118 reg = __raw_readq(sc->sbm_rxfilter); 2119 reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN); 2120 __raw_writeq(reg, sc->sbm_rxfilter); 2121 2122 if (dev->flags & IFF_ALLMULTI) { 2123 /* 2124 * Enable ALL multicasts. Do this by inverting the 2125 * multicast enable bit. 2126 */ 2127 reg = __raw_readq(sc->sbm_rxfilter); 2128 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN); 2129 __raw_writeq(reg, sc->sbm_rxfilter); 2130 return; 2131 } 2132 2133 2134 /* 2135 * Progam new multicast entries. For now, only use the 2136 * perfect filter. In the future we'll need to use the 2137 * hash filter if the perfect filter overflows 2138 */ 2139 2140 /* XXX only using perfect filter for now, need to use hash 2141 * XXX if the table overflows */ 2142 2143 idx = 1; /* skip station address */ 2144 netdev_for_each_mc_addr(ha, dev) { 2145 if (idx == MAC_ADDR_COUNT) 2146 break; 2147 reg = sbmac_addr2reg(ha->addr); 2148 port = sc->sbm_base + R_MAC_ADDR_BASE+(idx * sizeof(uint64_t)); 2149 __raw_writeq(reg, port); 2150 idx++; 2151 } 2152 2153 /* 2154 * Enable the "accept multicast bits" if we programmed at least one 2155 * multicast. 2156 */ 2157 2158 if (idx > 1) { 2159 reg = __raw_readq(sc->sbm_rxfilter); 2160 reg |= M_MAC_MCAST_EN; 2161 __raw_writeq(reg, sc->sbm_rxfilter); 2162 } 2163} 2164 2165static int sb1250_change_mtu(struct net_device *_dev, int new_mtu) 2166{ 2167 if (new_mtu > ENET_PACKET_SIZE) 2168 return -EINVAL; 2169 _dev->mtu = new_mtu; 2170 pr_info("changing the mtu to %d\n", new_mtu); 2171 return 0; 2172} 2173 2174static const struct net_device_ops sbmac_netdev_ops = { 2175 .ndo_open = sbmac_open, 2176 .ndo_stop = sbmac_close, 2177 .ndo_start_xmit = sbmac_start_tx, 2178 .ndo_set_rx_mode = sbmac_set_rx_mode, 2179 .ndo_tx_timeout = sbmac_tx_timeout, 2180 .ndo_do_ioctl = sbmac_mii_ioctl, 2181 .ndo_change_mtu = sb1250_change_mtu, 2182 .ndo_validate_addr = eth_validate_addr, 2183 .ndo_set_mac_address = eth_mac_addr, 2184#ifdef CONFIG_NET_POLL_CONTROLLER 2185 .ndo_poll_controller = sbmac_netpoll, 2186#endif 2187}; 2188 2189/********************************************************************** 2190 * SBMAC_INIT(dev) 2191 * 2192 * Attach routine - init hardware and hook ourselves into linux 2193 * 2194 * Input parameters: 2195 * dev - net_device structure 2196 * 2197 * Return value: 2198 * status 2199 ********************************************************************* */ 2200 2201static int sbmac_init(struct platform_device *pldev, long long base) 2202{ 2203 struct net_device *dev = dev_get_drvdata(&pldev->dev); 2204 int idx = pldev->id; 2205 struct sbmac_softc *sc = netdev_priv(dev); 2206 unsigned char *eaddr; 2207 uint64_t ea_reg; 2208 int i; 2209 int err; 2210 2211 sc->sbm_dev = dev; 2212 sc->sbe_idx = idx; 2213 2214 eaddr = sc->sbm_hwaddr; 2215 2216 /* 2217 * Read the ethernet address. The firmware left this programmed 2218 * for us in the ethernet address register for each mac. 2219 */ 2220 2221 ea_reg = __raw_readq(sc->sbm_base + R_MAC_ETHERNET_ADDR); 2222 __raw_writeq(0, sc->sbm_base + R_MAC_ETHERNET_ADDR); 2223 for (i = 0; i < 6; i++) { 2224 eaddr[i] = (uint8_t) (ea_reg & 0xFF); 2225 ea_reg >>= 8; 2226 } 2227 2228 for (i = 0; i < 6; i++) { 2229 dev->dev_addr[i] = eaddr[i]; 2230 } 2231 2232 /* 2233 * Initialize context (get pointers to registers and stuff), then 2234 * allocate the memory for the descriptor tables. 2235 */ 2236 2237 sbmac_initctx(sc); 2238 2239 /* 2240 * Set up Linux device callins 2241 */ 2242 2243 spin_lock_init(&(sc->sbm_lock)); 2244 2245 dev->netdev_ops = &sbmac_netdev_ops; 2246 dev->watchdog_timeo = TX_TIMEOUT; 2247 2248 netif_napi_add(dev, &sc->napi, sbmac_poll, 16); 2249 2250 dev->irq = UNIT_INT(idx); 2251 2252 /* This is needed for PASS2 for Rx H/W checksum feature */ 2253 sbmac_set_iphdr_offset(sc); 2254 2255 sc->mii_bus = mdiobus_alloc(); 2256 if (sc->mii_bus == NULL) { 2257 err = -ENOMEM; 2258 goto uninit_ctx; 2259 } 2260 2261 sc->mii_bus->name = sbmac_mdio_string; 2262 snprintf(sc->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2263 pldev->name, idx); 2264 sc->mii_bus->priv = sc; 2265 sc->mii_bus->read = sbmac_mii_read; 2266 sc->mii_bus->write = sbmac_mii_write; 2267 sc->mii_bus->irq = sc->phy_irq; 2268 for (i = 0; i < PHY_MAX_ADDR; ++i) 2269 sc->mii_bus->irq[i] = SBMAC_PHY_INT; 2270 2271 sc->mii_bus->parent = &pldev->dev; 2272 /* 2273 * Probe PHY address 2274 */ 2275 err = mdiobus_register(sc->mii_bus); 2276 if (err) { 2277 printk(KERN_ERR "%s: unable to register MDIO bus\n", 2278 dev->name); 2279 goto free_mdio; 2280 } 2281 dev_set_drvdata(&pldev->dev, sc->mii_bus); 2282 2283 err = register_netdev(dev); 2284 if (err) { 2285 printk(KERN_ERR "%s.%d: unable to register netdev\n", 2286 sbmac_string, idx); 2287 goto unreg_mdio; 2288 } 2289 2290 pr_info("%s.%d: registered as %s\n", sbmac_string, idx, dev->name); 2291 2292 if (sc->rx_hw_checksum == ENABLE) 2293 pr_info("%s: enabling TCP rcv checksum\n", dev->name); 2294 2295 /* 2296 * Display Ethernet address (this is called during the config 2297 * process so we need to finish off the config message that 2298 * was being displayed) 2299 */ 2300 pr_info("%s: SiByte Ethernet at 0x%08Lx, address: %pM\n", 2301 dev->name, base, eaddr); 2302 2303 return 0; 2304unreg_mdio: 2305 mdiobus_unregister(sc->mii_bus); 2306 dev_set_drvdata(&pldev->dev, NULL); 2307free_mdio: 2308 mdiobus_free(sc->mii_bus); 2309uninit_ctx: 2310 sbmac_uninitctx(sc); 2311 return err; 2312} 2313 2314 2315static int sbmac_open(struct net_device *dev) 2316{ 2317 struct sbmac_softc *sc = netdev_priv(dev); 2318 int err; 2319 2320 if (debug > 1) 2321 pr_debug("%s: sbmac_open() irq %d.\n", dev->name, dev->irq); 2322 2323 /* 2324 * map/route interrupt (clear status first, in case something 2325 * weird is pending; we haven't initialized the mac registers 2326 * yet) 2327 */ 2328 2329 __raw_readq(sc->sbm_isr); 2330 err = request_irq(dev->irq, sbmac_intr, IRQF_SHARED, dev->name, dev); 2331 if (err) { 2332 printk(KERN_ERR "%s: unable to get IRQ %d\n", dev->name, 2333 dev->irq); 2334 goto out_err; 2335 } 2336 2337 sc->sbm_speed = sbmac_speed_none; 2338 sc->sbm_duplex = sbmac_duplex_none; 2339 sc->sbm_fc = sbmac_fc_none; 2340 sc->sbm_pause = -1; 2341 sc->sbm_link = 0; 2342 2343 /* 2344 * Attach to the PHY 2345 */ 2346 err = sbmac_mii_probe(dev); 2347 if (err) 2348 goto out_unregister; 2349 2350 /* 2351 * Turn on the channel 2352 */ 2353 2354 sbmac_set_channel_state(sc,sbmac_state_on); 2355 2356 netif_start_queue(dev); 2357 2358 sbmac_set_rx_mode(dev); 2359 2360 phy_start(sc->phy_dev); 2361 2362 napi_enable(&sc->napi); 2363 2364 return 0; 2365 2366out_unregister: 2367 free_irq(dev->irq, dev); 2368out_err: 2369 return err; 2370} 2371 2372static int sbmac_mii_probe(struct net_device *dev) 2373{ 2374 struct sbmac_softc *sc = netdev_priv(dev); 2375 struct phy_device *phy_dev; 2376 int i; 2377 2378 for (i = 0; i < PHY_MAX_ADDR; i++) { 2379 phy_dev = sc->mii_bus->phy_map[i]; 2380 if (phy_dev) 2381 break; 2382 } 2383 if (!phy_dev) { 2384 printk(KERN_ERR "%s: no PHY found\n", dev->name); 2385 return -ENXIO; 2386 } 2387 2388 phy_dev = phy_connect(dev, dev_name(&phy_dev->dev), &sbmac_mii_poll, 0, 2389 PHY_INTERFACE_MODE_GMII); 2390 if (IS_ERR(phy_dev)) { 2391 printk(KERN_ERR "%s: could not attach to PHY\n", dev->name); 2392 return PTR_ERR(phy_dev); 2393 } 2394 2395 /* Remove any features not supported by the controller */ 2396 phy_dev->supported &= SUPPORTED_10baseT_Half | 2397 SUPPORTED_10baseT_Full | 2398 SUPPORTED_100baseT_Half | 2399 SUPPORTED_100baseT_Full | 2400 SUPPORTED_1000baseT_Half | 2401 SUPPORTED_1000baseT_Full | 2402 SUPPORTED_Autoneg | 2403 SUPPORTED_MII | 2404 SUPPORTED_Pause | 2405 SUPPORTED_Asym_Pause; 2406 phy_dev->advertising = phy_dev->supported; 2407 2408 pr_info("%s: attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", 2409 dev->name, phy_dev->drv->name, 2410 dev_name(&phy_dev->dev), phy_dev->irq); 2411 2412 sc->phy_dev = phy_dev; 2413 2414 return 0; 2415} 2416 2417 2418static void sbmac_mii_poll(struct net_device *dev) 2419{ 2420 struct sbmac_softc *sc = netdev_priv(dev); 2421 struct phy_device *phy_dev = sc->phy_dev; 2422 unsigned long flags; 2423 enum sbmac_fc fc; 2424 int link_chg, speed_chg, duplex_chg, pause_chg, fc_chg; 2425 2426 link_chg = (sc->sbm_link != phy_dev->link); 2427 speed_chg = (sc->sbm_speed != phy_dev->speed); 2428 duplex_chg = (sc->sbm_duplex != phy_dev->duplex); 2429 pause_chg = (sc->sbm_pause != phy_dev->pause); 2430 2431 if (!link_chg && !speed_chg && !duplex_chg && !pause_chg) 2432 return; /* Hmmm... */ 2433 2434 if (!phy_dev->link) { 2435 if (link_chg) { 2436 sc->sbm_link = phy_dev->link; 2437 sc->sbm_speed = sbmac_speed_none; 2438 sc->sbm_duplex = sbmac_duplex_none; 2439 sc->sbm_fc = sbmac_fc_disabled; 2440 sc->sbm_pause = -1; 2441 pr_info("%s: link unavailable\n", dev->name); 2442 } 2443 return; 2444 } 2445 2446 if (phy_dev->duplex == DUPLEX_FULL) { 2447 if (phy_dev->pause) 2448 fc = sbmac_fc_frame; 2449 else 2450 fc = sbmac_fc_disabled; 2451 } else 2452 fc = sbmac_fc_collision; 2453 fc_chg = (sc->sbm_fc != fc); 2454 2455 pr_info("%s: link available: %dbase-%cD\n", dev->name, phy_dev->speed, 2456 phy_dev->duplex == DUPLEX_FULL ? 'F' : 'H'); 2457 2458 spin_lock_irqsave(&sc->sbm_lock, flags); 2459 2460 sc->sbm_speed = phy_dev->speed; 2461 sc->sbm_duplex = phy_dev->duplex; 2462 sc->sbm_fc = fc; 2463 sc->sbm_pause = phy_dev->pause; 2464 sc->sbm_link = phy_dev->link; 2465 2466 if ((speed_chg || duplex_chg || fc_chg) && 2467 sc->sbm_state != sbmac_state_off) { 2468 /* 2469 * something changed, restart the channel 2470 */ 2471 if (debug > 1) 2472 pr_debug("%s: restarting channel " 2473 "because PHY state changed\n", dev->name); 2474 sbmac_channel_stop(sc); 2475 sbmac_channel_start(sc); 2476 } 2477 2478 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2479} 2480 2481 2482static void sbmac_tx_timeout (struct net_device *dev) 2483{ 2484 struct sbmac_softc *sc = netdev_priv(dev); 2485 unsigned long flags; 2486 2487 spin_lock_irqsave(&sc->sbm_lock, flags); 2488 2489 2490 dev->trans_start = jiffies; /* prevent tx timeout */ 2491 dev->stats.tx_errors++; 2492 2493 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2494 2495 printk (KERN_WARNING "%s: Transmit timed out\n",dev->name); 2496} 2497 2498 2499 2500 2501static void sbmac_set_rx_mode(struct net_device *dev) 2502{ 2503 unsigned long flags; 2504 struct sbmac_softc *sc = netdev_priv(dev); 2505 2506 spin_lock_irqsave(&sc->sbm_lock, flags); 2507 if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) { 2508 /* 2509 * Promiscuous changed. 2510 */ 2511 2512 if (dev->flags & IFF_PROMISC) { 2513 sbmac_promiscuous_mode(sc,1); 2514 } 2515 else { 2516 sbmac_promiscuous_mode(sc,0); 2517 } 2518 } 2519 spin_unlock_irqrestore(&sc->sbm_lock, flags); 2520 2521 /* 2522 * Program the multicasts. Do this every time. 2523 */ 2524 2525 sbmac_setmulti(sc); 2526 2527} 2528 2529static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2530{ 2531 struct sbmac_softc *sc = netdev_priv(dev); 2532 2533 if (!netif_running(dev) || !sc->phy_dev) 2534 return -EINVAL; 2535 2536 return phy_mii_ioctl(sc->phy_dev, rq, cmd); 2537} 2538 2539static int sbmac_close(struct net_device *dev) 2540{ 2541 struct sbmac_softc *sc = netdev_priv(dev); 2542 2543 napi_disable(&sc->napi); 2544 2545 phy_stop(sc->phy_dev); 2546 2547 sbmac_set_channel_state(sc, sbmac_state_off); 2548 2549 netif_stop_queue(dev); 2550 2551 if (debug > 1) 2552 pr_debug("%s: Shutting down ethercard\n", dev->name); 2553 2554 phy_disconnect(sc->phy_dev); 2555 sc->phy_dev = NULL; 2556 free_irq(dev->irq, dev); 2557 2558 sbdma_emptyring(&(sc->sbm_txdma)); 2559 sbdma_emptyring(&(sc->sbm_rxdma)); 2560 2561 return 0; 2562} 2563 2564static int sbmac_poll(struct napi_struct *napi, int budget) 2565{ 2566 struct sbmac_softc *sc = container_of(napi, struct sbmac_softc, napi); 2567 int work_done; 2568 2569 work_done = sbdma_rx_process(sc, &(sc->sbm_rxdma), budget, 1); 2570 sbdma_tx_process(sc, &(sc->sbm_txdma), 1); 2571 2572 if (work_done < budget) { 2573 napi_complete(napi); 2574 2575#ifdef CONFIG_SBMAC_COALESCE 2576 __raw_writeq(((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_TX_CH0) | 2577 ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0), 2578 sc->sbm_imr); 2579#else 2580 __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 2581 (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr); 2582#endif 2583 } 2584 2585 return work_done; 2586} 2587 2588 2589static int __devinit sbmac_probe(struct platform_device *pldev) 2590{ 2591 struct net_device *dev; 2592 struct sbmac_softc *sc; 2593 void __iomem *sbm_base; 2594 struct resource *res; 2595 u64 sbmac_orig_hwaddr; 2596 int err; 2597 2598 res = platform_get_resource(pldev, IORESOURCE_MEM, 0); 2599 BUG_ON(!res); 2600 sbm_base = ioremap_nocache(res->start, resource_size(res)); 2601 if (!sbm_base) { 2602 printk(KERN_ERR "%s: unable to map device registers\n", 2603 dev_name(&pldev->dev)); 2604 err = -ENOMEM; 2605 goto out_out; 2606 } 2607 2608 /* 2609 * The R_MAC_ETHERNET_ADDR register will be set to some nonzero 2610 * value for us by the firmware if we're going to use this MAC. 2611 * If we find a zero, skip this MAC. 2612 */ 2613 sbmac_orig_hwaddr = __raw_readq(sbm_base + R_MAC_ETHERNET_ADDR); 2614 pr_debug("%s: %sconfiguring MAC at 0x%08Lx\n", dev_name(&pldev->dev), 2615 sbmac_orig_hwaddr ? "" : "not ", (long long)res->start); 2616 if (sbmac_orig_hwaddr == 0) { 2617 err = 0; 2618 goto out_unmap; 2619 } 2620 2621 /* 2622 * Okay, cool. Initialize this MAC. 2623 */ 2624 dev = alloc_etherdev(sizeof(struct sbmac_softc)); 2625 if (!dev) { 2626 printk(KERN_ERR "%s: unable to allocate etherdev\n", 2627 dev_name(&pldev->dev)); 2628 err = -ENOMEM; 2629 goto out_unmap; 2630 } 2631 2632 dev_set_drvdata(&pldev->dev, dev); 2633 SET_NETDEV_DEV(dev, &pldev->dev); 2634 2635 sc = netdev_priv(dev); 2636 sc->sbm_base = sbm_base; 2637 2638 err = sbmac_init(pldev, res->start); 2639 if (err) 2640 goto out_kfree; 2641 2642 return 0; 2643 2644out_kfree: 2645 free_netdev(dev); 2646 __raw_writeq(sbmac_orig_hwaddr, sbm_base + R_MAC_ETHERNET_ADDR); 2647 2648out_unmap: 2649 iounmap(sbm_base); 2650 2651out_out: 2652 return err; 2653} 2654 2655static int __exit sbmac_remove(struct platform_device *pldev) 2656{ 2657 struct net_device *dev = dev_get_drvdata(&pldev->dev); 2658 struct sbmac_softc *sc = netdev_priv(dev); 2659 2660 unregister_netdev(dev); 2661 sbmac_uninitctx(sc); 2662 mdiobus_unregister(sc->mii_bus); 2663 mdiobus_free(sc->mii_bus); 2664 iounmap(sc->sbm_base); 2665 free_netdev(dev); 2666 2667 return 0; 2668} 2669 2670static struct platform_driver sbmac_driver = { 2671 .probe = sbmac_probe, 2672 .remove = __exit_p(sbmac_remove), 2673 .driver = { 2674 .name = sbmac_string, 2675 .owner = THIS_MODULE, 2676 }, 2677}; 2678 2679module_platform_driver(sbmac_driver); 2680