common.h revision 34336ec032878d1a32e7df881f16ce2145e53f83
1/* 2 * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32#ifndef __CHELSIO_COMMON_H 33#define __CHELSIO_COMMON_H 34 35#include <linux/kernel.h> 36#include <linux/types.h> 37#include <linux/ctype.h> 38#include <linux/delay.h> 39#include <linux/init.h> 40#include <linux/netdevice.h> 41#include <linux/ethtool.h> 42#include <linux/mdio.h> 43#include "version.h" 44 45#define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__) 46#define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ## __VA_ARGS__) 47#define CH_ALERT(adap, fmt, ...) \ 48 dev_printk(KERN_ALERT, &adap->pdev->dev, fmt, ## __VA_ARGS__) 49 50/* 51 * More powerful macro that selectively prints messages based on msg_enable. 52 * For info and debugging messages. 53 */ 54#define CH_MSG(adapter, level, category, fmt, ...) do { \ 55 if ((adapter)->msg_enable & NETIF_MSG_##category) \ 56 dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \ 57 ## __VA_ARGS__); \ 58} while (0) 59 60#ifdef DEBUG 61# define CH_DBG(adapter, category, fmt, ...) \ 62 CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__) 63#else 64# define CH_DBG(adapter, category, fmt, ...) 65#endif 66 67/* Additional NETIF_MSG_* categories */ 68#define NETIF_MSG_MMIO 0x8000000 69 70struct t3_rx_mode { 71 struct net_device *dev; 72 struct dev_mc_list *mclist; 73 unsigned int idx; 74}; 75 76static inline void init_rx_mode(struct t3_rx_mode *p, struct net_device *dev, 77 struct dev_mc_list *mclist) 78{ 79 p->dev = dev; 80 p->mclist = mclist; 81 p->idx = 0; 82} 83 84static inline u8 *t3_get_next_mcaddr(struct t3_rx_mode *rm) 85{ 86 u8 *addr = NULL; 87 88 if (rm->mclist && rm->idx < rm->dev->mc_count) { 89 addr = rm->mclist->dmi_addr; 90 rm->mclist = rm->mclist->next; 91 rm->idx++; 92 } 93 return addr; 94} 95 96enum { 97 MAX_NPORTS = 2, /* max # of ports */ 98 MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */ 99 EEPROMSIZE = 8192, /* Serial EEPROM size */ 100 SERNUM_LEN = 16, /* Serial # length */ 101 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ 102 TCB_SIZE = 128, /* TCB size */ 103 NMTUS = 16, /* size of MTU table */ 104 NCCTRL_WIN = 32, /* # of congestion control windows */ 105 PROTO_SRAM_LINES = 128, /* size of TP sram */ 106}; 107 108#define MAX_RX_COALESCING_LEN 12288U 109 110enum { 111 PAUSE_RX = 1 << 0, 112 PAUSE_TX = 1 << 1, 113 PAUSE_AUTONEG = 1 << 2 114}; 115 116enum { 117 SUPPORTED_IRQ = 1 << 24 118}; 119 120enum { /* adapter interrupt-maintained statistics */ 121 STAT_ULP_CH0_PBL_OOB, 122 STAT_ULP_CH1_PBL_OOB, 123 STAT_PCI_CORR_ECC, 124 125 IRQ_NUM_STATS /* keep last */ 126}; 127 128#define TP_VERSION_MAJOR 1 129#define TP_VERSION_MINOR 1 130#define TP_VERSION_MICRO 0 131 132#define S_TP_VERSION_MAJOR 16 133#define M_TP_VERSION_MAJOR 0xFF 134#define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR) 135#define G_TP_VERSION_MAJOR(x) \ 136 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR) 137 138#define S_TP_VERSION_MINOR 8 139#define M_TP_VERSION_MINOR 0xFF 140#define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR) 141#define G_TP_VERSION_MINOR(x) \ 142 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR) 143 144#define S_TP_VERSION_MICRO 0 145#define M_TP_VERSION_MICRO 0xFF 146#define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO) 147#define G_TP_VERSION_MICRO(x) \ 148 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) 149 150enum { 151 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ 152 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ 153 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ 154}; 155 156enum sge_context_type { /* SGE egress context types */ 157 SGE_CNTXT_RDMA = 0, 158 SGE_CNTXT_ETH = 2, 159 SGE_CNTXT_OFLD = 4, 160 SGE_CNTXT_CTRL = 5 161}; 162 163enum { 164 AN_PKT_SIZE = 32, /* async notification packet size */ 165 IMMED_PKT_SIZE = 48 /* packet size for immediate data */ 166}; 167 168struct sg_ent { /* SGE scatter/gather entry */ 169 __be32 len[2]; 170 __be64 addr[2]; 171}; 172 173#ifndef SGE_NUM_GENBITS 174/* Must be 1 or 2 */ 175# define SGE_NUM_GENBITS 2 176#endif 177 178#define TX_DESC_FLITS 16U 179#define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) 180 181struct cphy; 182struct adapter; 183 184struct mdio_ops { 185 int (*read)(struct net_device *dev, int phy_addr, int mmd_addr, 186 u16 reg_addr); 187 int (*write)(struct net_device *dev, int phy_addr, int mmd_addr, 188 u16 reg_addr, u16 val); 189 unsigned mode_support; 190}; 191 192struct adapter_info { 193 unsigned char nports0; /* # of ports on channel 0 */ 194 unsigned char nports1; /* # of ports on channel 1 */ 195 unsigned char phy_base_addr; /* MDIO PHY base address */ 196 unsigned int gpio_out; /* GPIO output settings */ 197 unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */ 198 unsigned long caps; /* adapter capabilities */ 199 const struct mdio_ops *mdio_ops; /* MDIO operations */ 200 const char *desc; /* product description */ 201}; 202 203struct mc5_stats { 204 unsigned long parity_err; 205 unsigned long active_rgn_full; 206 unsigned long nfa_srch_err; 207 unsigned long unknown_cmd; 208 unsigned long reqq_parity_err; 209 unsigned long dispq_parity_err; 210 unsigned long del_act_empty; 211}; 212 213struct mc7_stats { 214 unsigned long corr_err; 215 unsigned long uncorr_err; 216 unsigned long parity_err; 217 unsigned long addr_err; 218}; 219 220struct mac_stats { 221 u64 tx_octets; /* total # of octets in good frames */ 222 u64 tx_octets_bad; /* total # of octets in error frames */ 223 u64 tx_frames; /* all good frames */ 224 u64 tx_mcast_frames; /* good multicast frames */ 225 u64 tx_bcast_frames; /* good broadcast frames */ 226 u64 tx_pause; /* # of transmitted pause frames */ 227 u64 tx_deferred; /* frames with deferred transmissions */ 228 u64 tx_late_collisions; /* # of late collisions */ 229 u64 tx_total_collisions; /* # of total collisions */ 230 u64 tx_excess_collisions; /* frame errors from excessive collissions */ 231 u64 tx_underrun; /* # of Tx FIFO underruns */ 232 u64 tx_len_errs; /* # of Tx length errors */ 233 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ 234 u64 tx_excess_deferral; /* # of frames with excessive deferral */ 235 u64 tx_fcs_errs; /* # of frames with bad FCS */ 236 237 u64 tx_frames_64; /* # of Tx frames in a particular range */ 238 u64 tx_frames_65_127; 239 u64 tx_frames_128_255; 240 u64 tx_frames_256_511; 241 u64 tx_frames_512_1023; 242 u64 tx_frames_1024_1518; 243 u64 tx_frames_1519_max; 244 245 u64 rx_octets; /* total # of octets in good frames */ 246 u64 rx_octets_bad; /* total # of octets in error frames */ 247 u64 rx_frames; /* all good frames */ 248 u64 rx_mcast_frames; /* good multicast frames */ 249 u64 rx_bcast_frames; /* good broadcast frames */ 250 u64 rx_pause; /* # of received pause frames */ 251 u64 rx_fcs_errs; /* # of received frames with bad FCS */ 252 u64 rx_align_errs; /* alignment errors */ 253 u64 rx_symbol_errs; /* symbol errors */ 254 u64 rx_data_errs; /* data errors */ 255 u64 rx_sequence_errs; /* sequence errors */ 256 u64 rx_runt; /* # of runt frames */ 257 u64 rx_jabber; /* # of jabber frames */ 258 u64 rx_short; /* # of short frames */ 259 u64 rx_too_long; /* # of oversized frames */ 260 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ 261 262 u64 rx_frames_64; /* # of Rx frames in a particular range */ 263 u64 rx_frames_65_127; 264 u64 rx_frames_128_255; 265 u64 rx_frames_256_511; 266 u64 rx_frames_512_1023; 267 u64 rx_frames_1024_1518; 268 u64 rx_frames_1519_max; 269 270 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ 271 272 unsigned long tx_fifo_parity_err; 273 unsigned long rx_fifo_parity_err; 274 unsigned long tx_fifo_urun; 275 unsigned long rx_fifo_ovfl; 276 unsigned long serdes_signal_loss; 277 unsigned long xaui_pcs_ctc_err; 278 unsigned long xaui_pcs_align_change; 279 280 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ 281 unsigned long num_resets; /* # times reset due to stuck TX */ 282 283 unsigned long link_faults; /* # detected link faults */ 284}; 285 286struct tp_mib_stats { 287 u32 ipInReceive_hi; 288 u32 ipInReceive_lo; 289 u32 ipInHdrErrors_hi; 290 u32 ipInHdrErrors_lo; 291 u32 ipInAddrErrors_hi; 292 u32 ipInAddrErrors_lo; 293 u32 ipInUnknownProtos_hi; 294 u32 ipInUnknownProtos_lo; 295 u32 ipInDiscards_hi; 296 u32 ipInDiscards_lo; 297 u32 ipInDelivers_hi; 298 u32 ipInDelivers_lo; 299 u32 ipOutRequests_hi; 300 u32 ipOutRequests_lo; 301 u32 ipOutDiscards_hi; 302 u32 ipOutDiscards_lo; 303 u32 ipOutNoRoutes_hi; 304 u32 ipOutNoRoutes_lo; 305 u32 ipReasmTimeout; 306 u32 ipReasmReqds; 307 u32 ipReasmOKs; 308 u32 ipReasmFails; 309 310 u32 reserved[8]; 311 312 u32 tcpActiveOpens; 313 u32 tcpPassiveOpens; 314 u32 tcpAttemptFails; 315 u32 tcpEstabResets; 316 u32 tcpOutRsts; 317 u32 tcpCurrEstab; 318 u32 tcpInSegs_hi; 319 u32 tcpInSegs_lo; 320 u32 tcpOutSegs_hi; 321 u32 tcpOutSegs_lo; 322 u32 tcpRetransSeg_hi; 323 u32 tcpRetransSeg_lo; 324 u32 tcpInErrs_hi; 325 u32 tcpInErrs_lo; 326 u32 tcpRtoMin; 327 u32 tcpRtoMax; 328}; 329 330struct tp_params { 331 unsigned int nchan; /* # of channels */ 332 unsigned int pmrx_size; /* total PMRX capacity */ 333 unsigned int pmtx_size; /* total PMTX capacity */ 334 unsigned int cm_size; /* total CM capacity */ 335 unsigned int chan_rx_size; /* per channel Rx size */ 336 unsigned int chan_tx_size; /* per channel Tx size */ 337 unsigned int rx_pg_size; /* Rx page size */ 338 unsigned int tx_pg_size; /* Tx page size */ 339 unsigned int rx_num_pgs; /* # of Rx pages */ 340 unsigned int tx_num_pgs; /* # of Tx pages */ 341 unsigned int ntimer_qs; /* # of timer queues */ 342}; 343 344struct qset_params { /* SGE queue set parameters */ 345 unsigned int polling; /* polling/interrupt service for rspq */ 346 unsigned int lro; /* large receive offload */ 347 unsigned int coalesce_usecs; /* irq coalescing timer */ 348 unsigned int rspq_size; /* # of entries in response queue */ 349 unsigned int fl_size; /* # of entries in regular free list */ 350 unsigned int jumbo_size; /* # of entries in jumbo free list */ 351 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ 352 unsigned int cong_thres; /* FL congestion threshold */ 353 unsigned int vector; /* Interrupt (line or vector) number */ 354}; 355 356struct sge_params { 357 unsigned int max_pkt_size; /* max offload pkt size */ 358 struct qset_params qset[SGE_QSETS]; 359}; 360 361struct mc5_params { 362 unsigned int mode; /* selects MC5 width */ 363 unsigned int nservers; /* size of server region */ 364 unsigned int nfilters; /* size of filter region */ 365 unsigned int nroutes; /* size of routing region */ 366}; 367 368/* Default MC5 region sizes */ 369enum { 370 DEFAULT_NSERVERS = 512, 371 DEFAULT_NFILTERS = 128 372}; 373 374/* MC5 modes, these must be non-0 */ 375enum { 376 MC5_MODE_144_BIT = 1, 377 MC5_MODE_72_BIT = 2 378}; 379 380/* MC5 min active region size */ 381enum { MC5_MIN_TIDS = 16 }; 382 383struct vpd_params { 384 unsigned int cclk; 385 unsigned int mclk; 386 unsigned int uclk; 387 unsigned int mdc; 388 unsigned int mem_timing; 389 u8 sn[SERNUM_LEN + 1]; 390 u8 eth_base[6]; 391 u8 port_type[MAX_NPORTS]; 392 unsigned short xauicfg[2]; 393}; 394 395struct pci_params { 396 unsigned int vpd_cap_addr; 397 unsigned int pcie_cap_addr; 398 unsigned short speed; 399 unsigned char width; 400 unsigned char variant; 401}; 402 403enum { 404 PCI_VARIANT_PCI, 405 PCI_VARIANT_PCIX_MODE1_PARITY, 406 PCI_VARIANT_PCIX_MODE1_ECC, 407 PCI_VARIANT_PCIX_266_MODE2, 408 PCI_VARIANT_PCIE 409}; 410 411struct adapter_params { 412 struct sge_params sge; 413 struct mc5_params mc5; 414 struct tp_params tp; 415 struct vpd_params vpd; 416 struct pci_params pci; 417 418 const struct adapter_info *info; 419 420 unsigned short mtus[NMTUS]; 421 unsigned short a_wnd[NCCTRL_WIN]; 422 unsigned short b_wnd[NCCTRL_WIN]; 423 424 unsigned int nports; /* # of ethernet ports */ 425 unsigned int chan_map; /* bitmap of in-use Tx channels */ 426 unsigned int stats_update_period; /* MAC stats accumulation period */ 427 unsigned int linkpoll_period; /* link poll period in 0.1s */ 428 unsigned int rev; /* chip revision */ 429 unsigned int offload; 430}; 431 432enum { /* chip revisions */ 433 T3_REV_A = 0, 434 T3_REV_B = 2, 435 T3_REV_B2 = 3, 436 T3_REV_C = 4, 437}; 438 439struct trace_params { 440 u32 sip; 441 u32 sip_mask; 442 u32 dip; 443 u32 dip_mask; 444 u16 sport; 445 u16 sport_mask; 446 u16 dport; 447 u16 dport_mask; 448 u32 vlan:12; 449 u32 vlan_mask:12; 450 u32 intf:4; 451 u32 intf_mask:4; 452 u8 proto; 453 u8 proto_mask; 454}; 455 456struct link_config { 457 unsigned int supported; /* link capabilities */ 458 unsigned int advertising; /* advertised capabilities */ 459 unsigned short requested_speed; /* speed user has requested */ 460 unsigned short speed; /* actual link speed */ 461 unsigned char requested_duplex; /* duplex user has requested */ 462 unsigned char duplex; /* actual link duplex */ 463 unsigned char requested_fc; /* flow control user has requested */ 464 unsigned char fc; /* actual link flow control */ 465 unsigned char autoneg; /* autonegotiating? */ 466 unsigned int link_ok; /* link up? */ 467}; 468 469#define SPEED_INVALID 0xffff 470#define DUPLEX_INVALID 0xff 471 472struct mc5 { 473 struct adapter *adapter; 474 unsigned int tcam_size; 475 unsigned char part_type; 476 unsigned char parity_enabled; 477 unsigned char mode; 478 struct mc5_stats stats; 479}; 480 481static inline unsigned int t3_mc5_size(const struct mc5 *p) 482{ 483 return p->tcam_size; 484} 485 486struct mc7 { 487 struct adapter *adapter; /* backpointer to adapter */ 488 unsigned int size; /* memory size in bytes */ 489 unsigned int width; /* MC7 interface width */ 490 unsigned int offset; /* register address offset for MC7 instance */ 491 const char *name; /* name of MC7 instance */ 492 struct mc7_stats stats; /* MC7 statistics */ 493}; 494 495static inline unsigned int t3_mc7_size(const struct mc7 *p) 496{ 497 return p->size; 498} 499 500struct cmac { 501 struct adapter *adapter; 502 unsigned int offset; 503 unsigned int nucast; /* # of address filters for unicast MACs */ 504 unsigned int tx_tcnt; 505 unsigned int tx_xcnt; 506 u64 tx_mcnt; 507 unsigned int rx_xcnt; 508 unsigned int rx_ocnt; 509 u64 rx_mcnt; 510 unsigned int toggle_cnt; 511 unsigned int txen; 512 u64 rx_pause; 513 struct mac_stats stats; 514}; 515 516enum { 517 MAC_DIRECTION_RX = 1, 518 MAC_DIRECTION_TX = 2, 519 MAC_RXFIFO_SIZE = 32768 520}; 521 522/* PHY loopback direction */ 523enum { 524 PHY_LOOPBACK_TX = 1, 525 PHY_LOOPBACK_RX = 2 526}; 527 528/* PHY interrupt types */ 529enum { 530 cphy_cause_link_change = 1, 531 cphy_cause_fifo_error = 2, 532 cphy_cause_module_change = 4, 533}; 534 535/* PHY module types */ 536enum { 537 phy_modtype_none, 538 phy_modtype_sr, 539 phy_modtype_lr, 540 phy_modtype_lrm, 541 phy_modtype_twinax, 542 phy_modtype_twinax_long, 543 phy_modtype_unknown 544}; 545 546/* PHY operations */ 547struct cphy_ops { 548 int (*reset)(struct cphy *phy, int wait); 549 550 int (*intr_enable)(struct cphy *phy); 551 int (*intr_disable)(struct cphy *phy); 552 int (*intr_clear)(struct cphy *phy); 553 int (*intr_handler)(struct cphy *phy); 554 555 int (*autoneg_enable)(struct cphy *phy); 556 int (*autoneg_restart)(struct cphy *phy); 557 558 int (*advertise)(struct cphy *phy, unsigned int advertise_map); 559 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); 560 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); 561 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed, 562 int *duplex, int *fc); 563 int (*power_down)(struct cphy *phy, int enable); 564 565 u32 mmds; 566}; 567enum { 568 EDC_OPT_AEL2005 = 0, 569 EDC_OPT_AEL2005_SIZE = 1084, 570 EDC_TWX_AEL2005 = 1, 571 EDC_TWX_AEL2005_SIZE = 1464, 572 EDC_TWX_AEL2020 = 2, 573 EDC_TWX_AEL2020_SIZE = 1628, 574 EDC_MAX_SIZE = EDC_TWX_AEL2020_SIZE, /* Max cache size */ 575}; 576 577/* A PHY instance */ 578struct cphy { 579 u8 modtype; /* PHY module type */ 580 short priv; /* scratch pad */ 581 unsigned int caps; /* PHY capabilities */ 582 struct adapter *adapter; /* associated adapter */ 583 const char *desc; /* PHY description */ 584 unsigned long fifo_errors; /* FIFO over/under-flows */ 585 const struct cphy_ops *ops; /* PHY operations */ 586 struct mdio_if_info mdio; 587 u16 phy_cache[EDC_MAX_SIZE]; /* EDC cache */ 588}; 589 590/* Convenience MDIO read/write wrappers */ 591static inline int t3_mdio_read(struct cphy *phy, int mmd, int reg, 592 unsigned int *valp) 593{ 594 int rc = phy->mdio.mdio_read(phy->mdio.dev, phy->mdio.prtad, mmd, reg); 595 *valp = (rc >= 0) ? rc : -1; 596 return (rc >= 0) ? 0 : rc; 597} 598 599static inline int t3_mdio_write(struct cphy *phy, int mmd, int reg, 600 unsigned int val) 601{ 602 return phy->mdio.mdio_write(phy->mdio.dev, phy->mdio.prtad, mmd, 603 reg, val); 604} 605 606/* Convenience initializer */ 607static inline void cphy_init(struct cphy *phy, struct adapter *adapter, 608 int phy_addr, struct cphy_ops *phy_ops, 609 const struct mdio_ops *mdio_ops, 610 unsigned int caps, const char *desc) 611{ 612 phy->caps = caps; 613 phy->adapter = adapter; 614 phy->desc = desc; 615 phy->ops = phy_ops; 616 if (mdio_ops) { 617 phy->mdio.prtad = phy_addr; 618 phy->mdio.mmds = phy_ops->mmds; 619 phy->mdio.mode_support = mdio_ops->mode_support; 620 phy->mdio.mdio_read = mdio_ops->read; 621 phy->mdio.mdio_write = mdio_ops->write; 622 } 623} 624 625/* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ 626#define MAC_STATS_ACCUM_SECS 180 627 628#define XGM_REG(reg_addr, idx) \ 629 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) 630 631struct addr_val_pair { 632 unsigned int reg_addr; 633 unsigned int val; 634}; 635 636#include "adapter.h" 637 638#ifndef PCI_VENDOR_ID_CHELSIO 639# define PCI_VENDOR_ID_CHELSIO 0x1425 640#endif 641 642#define for_each_port(adapter, iter) \ 643 for (iter = 0; iter < (adapter)->params.nports; ++iter) 644 645#define adapter_info(adap) ((adap)->params.info) 646 647static inline int uses_xaui(const struct adapter *adap) 648{ 649 return adapter_info(adap)->caps & SUPPORTED_AUI; 650} 651 652static inline int is_10G(const struct adapter *adap) 653{ 654 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; 655} 656 657static inline int is_offload(const struct adapter *adap) 658{ 659 return adap->params.offload; 660} 661 662static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 663{ 664 return adap->params.vpd.cclk / 1000; 665} 666 667static inline unsigned int is_pcie(const struct adapter *adap) 668{ 669 return adap->params.pci.variant == PCI_VARIANT_PCIE; 670} 671 672void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 673 u32 val); 674void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p, 675 int n, unsigned int offset); 676int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 677 int polarity, int attempts, int delay, u32 *valp); 678static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask, 679 int polarity, int attempts, int delay) 680{ 681 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, 682 delay, NULL); 683} 684int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, 685 unsigned int set); 686int t3_phy_reset(struct cphy *phy, int mmd, int wait); 687int t3_phy_advertise(struct cphy *phy, unsigned int advert); 688int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert); 689int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); 690int t3_phy_lasi_intr_enable(struct cphy *phy); 691int t3_phy_lasi_intr_disable(struct cphy *phy); 692int t3_phy_lasi_intr_clear(struct cphy *phy); 693int t3_phy_lasi_intr_handler(struct cphy *phy); 694 695void t3_intr_enable(struct adapter *adapter); 696void t3_intr_disable(struct adapter *adapter); 697void t3_intr_clear(struct adapter *adapter); 698void t3_xgm_intr_enable(struct adapter *adapter, int idx); 699void t3_xgm_intr_disable(struct adapter *adapter, int idx); 700void t3_port_intr_enable(struct adapter *adapter, int idx); 701void t3_port_intr_disable(struct adapter *adapter, int idx); 702void t3_port_intr_clear(struct adapter *adapter, int idx); 703int t3_slow_intr_handler(struct adapter *adapter); 704int t3_phy_intr_handler(struct adapter *adapter); 705 706void t3_link_changed(struct adapter *adapter, int port_id); 707void t3_link_fault(struct adapter *adapter, int port_id); 708int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 709const struct adapter_info *t3_get_adapter_info(unsigned int board_id); 710int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data); 711int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data); 712int t3_seeprom_wp(struct adapter *adapter, int enable); 713int t3_get_tp_version(struct adapter *adapter, u32 *vers); 714int t3_check_tpsram_version(struct adapter *adapter); 715int t3_check_tpsram(struct adapter *adapter, const u8 *tp_ram, 716 unsigned int size); 717int t3_set_proto_sram(struct adapter *adap, const u8 *data); 718int t3_read_flash(struct adapter *adapter, unsigned int addr, 719 unsigned int nwords, u32 *data, int byte_oriented); 720int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size); 721int t3_get_fw_version(struct adapter *adapter, u32 *vers); 722int t3_check_fw_version(struct adapter *adapter); 723int t3_init_hw(struct adapter *adapter, u32 fw_params); 724void mac_prep(struct cmac *mac, struct adapter *adapter, int index); 725void early_hw_init(struct adapter *adapter, const struct adapter_info *ai); 726int t3_reset_adapter(struct adapter *adapter); 727int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai, 728 int reset); 729int t3_replay_prep_adapter(struct adapter *adapter); 730void t3_led_ready(struct adapter *adapter); 731void t3_fatal_err(struct adapter *adapter); 732void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on); 733void t3_config_rss(struct adapter *adapter, unsigned int rss_config, 734 const u8 * cpus, const u16 *rspq); 735int t3_read_rss(struct adapter *adapter, u8 * lkup, u16 *map); 736int t3_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 737int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr, 738 unsigned int n, unsigned int *valp); 739int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, 740 u64 *buf); 741 742int t3_mac_reset(struct cmac *mac); 743void t3b_pcs_reset(struct cmac *mac); 744void t3_mac_disable_exact_filters(struct cmac *mac); 745void t3_mac_enable_exact_filters(struct cmac *mac); 746int t3_mac_enable(struct cmac *mac, int which); 747int t3_mac_disable(struct cmac *mac, int which); 748int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); 749int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); 750int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); 751int t3_mac_set_num_ucast(struct cmac *mac, int n); 752const struct mac_stats *t3_mac_update_stats(struct cmac *mac); 753int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc); 754int t3b2_mac_watchdog_task(struct cmac *mac); 755 756void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode); 757int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 758 unsigned int nroutes); 759void t3_mc5_intr_handler(struct mc5 *mc5); 760int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, 761 u32 *buf); 762 763int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh); 764void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size); 765void t3_tp_set_offload_mode(struct adapter *adap, int enable); 766void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps); 767void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS], 768 unsigned short alpha[NCCTRL_WIN], 769 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); 770void t3_read_hw_mtus(struct adapter *adap, unsigned short mtus[NMTUS]); 771void t3_get_cong_cntl_tab(struct adapter *adap, 772 unsigned short incr[NMTUS][NCCTRL_WIN]); 773void t3_config_trace_filter(struct adapter *adapter, 774 const struct trace_params *tp, int filter_index, 775 int invert, int enable); 776int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched); 777 778void t3_sge_prep(struct adapter *adap, struct sge_params *p); 779void t3_sge_init(struct adapter *adap, struct sge_params *p); 780int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable, 781 enum sge_context_type type, int respq, u64 base_addr, 782 unsigned int size, unsigned int token, int gen, 783 unsigned int cidx); 784int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id, 785 int gts_enable, u64 base_addr, unsigned int size, 786 unsigned int esize, unsigned int cong_thres, int gen, 787 unsigned int cidx); 788int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id, 789 int irq_vec_idx, u64 base_addr, unsigned int size, 790 unsigned int fl_thres, int gen, unsigned int cidx); 791int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr, 792 unsigned int size, int rspq, int ovfl_mode, 793 unsigned int credits, unsigned int credit_thres); 794int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable); 795int t3_sge_disable_fl(struct adapter *adapter, unsigned int id); 796int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id); 797int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id); 798int t3_sge_read_ecntxt(struct adapter *adapter, unsigned int id, u32 data[4]); 799int t3_sge_read_fl(struct adapter *adapter, unsigned int id, u32 data[4]); 800int t3_sge_read_cq(struct adapter *adapter, unsigned int id, u32 data[4]); 801int t3_sge_read_rspq(struct adapter *adapter, unsigned int id, u32 data[4]); 802int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op, 803 unsigned int credits); 804 805int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter, 806 int phy_addr, const struct mdio_ops *mdio_ops); 807int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter, 808 int phy_addr, const struct mdio_ops *mdio_ops); 809int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter, 810 int phy_addr, const struct mdio_ops *mdio_ops); 811int t3_ael2005_phy_prep(struct cphy *phy, struct adapter *adapter, 812 int phy_addr, const struct mdio_ops *mdio_ops); 813int t3_ael2020_phy_prep(struct cphy *phy, struct adapter *adapter, 814 int phy_addr, const struct mdio_ops *mdio_ops); 815int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr, 816 const struct mdio_ops *mdio_ops); 817int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter, 818 int phy_addr, const struct mdio_ops *mdio_ops); 819int t3_aq100x_phy_prep(struct cphy *phy, struct adapter *adapter, 820 int phy_addr, const struct mdio_ops *mdio_ops); 821#endif /* __CHELSIO_COMMON_H */ 822