common.h revision f231e0a5a2d01da40515c24f1daa689fe8cfd8d7
1/* 2 * Copyright (c) 2005-2007 Chelsio, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32#ifndef __CHELSIO_COMMON_H 33#define __CHELSIO_COMMON_H 34 35#include <linux/kernel.h> 36#include <linux/types.h> 37#include <linux/ctype.h> 38#include <linux/delay.h> 39#include <linux/init.h> 40#include <linux/netdevice.h> 41#include <linux/ethtool.h> 42#include <linux/mii.h> 43#include "version.h" 44 45#define CH_ERR(adap, fmt, ...) dev_err(&adap->pdev->dev, fmt, ## __VA_ARGS__) 46#define CH_WARN(adap, fmt, ...) dev_warn(&adap->pdev->dev, fmt, ## __VA_ARGS__) 47#define CH_ALERT(adap, fmt, ...) \ 48 dev_printk(KERN_ALERT, &adap->pdev->dev, fmt, ## __VA_ARGS__) 49 50/* 51 * More powerful macro that selectively prints messages based on msg_enable. 52 * For info and debugging messages. 53 */ 54#define CH_MSG(adapter, level, category, fmt, ...) do { \ 55 if ((adapter)->msg_enable & NETIF_MSG_##category) \ 56 dev_printk(KERN_##level, &adapter->pdev->dev, fmt, \ 57 ## __VA_ARGS__); \ 58} while (0) 59 60#ifdef DEBUG 61# define CH_DBG(adapter, category, fmt, ...) \ 62 CH_MSG(adapter, DEBUG, category, fmt, ## __VA_ARGS__) 63#else 64# define CH_DBG(adapter, category, fmt, ...) 65#endif 66 67/* Additional NETIF_MSG_* categories */ 68#define NETIF_MSG_MMIO 0x8000000 69 70struct t3_rx_mode { 71 struct net_device *dev; 72 struct dev_mc_list *mclist; 73 unsigned int idx; 74}; 75 76static inline void init_rx_mode(struct t3_rx_mode *p, struct net_device *dev, 77 struct dev_mc_list *mclist) 78{ 79 p->dev = dev; 80 p->mclist = mclist; 81 p->idx = 0; 82} 83 84static inline u8 *t3_get_next_mcaddr(struct t3_rx_mode *rm) 85{ 86 u8 *addr = NULL; 87 88 if (rm->mclist && rm->idx < rm->dev->mc_count) { 89 addr = rm->mclist->dmi_addr; 90 rm->mclist = rm->mclist->next; 91 rm->idx++; 92 } 93 return addr; 94} 95 96enum { 97 MAX_NPORTS = 2, /* max # of ports */ 98 MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */ 99 EEPROMSIZE = 8192, /* Serial EEPROM size */ 100 SERNUM_LEN = 16, /* Serial # length */ 101 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ 102 TCB_SIZE = 128, /* TCB size */ 103 NMTUS = 16, /* size of MTU table */ 104 NCCTRL_WIN = 32, /* # of congestion control windows */ 105 PROTO_SRAM_LINES = 128, /* size of TP sram */ 106}; 107 108#define MAX_RX_COALESCING_LEN 12288U 109 110enum { 111 PAUSE_RX = 1 << 0, 112 PAUSE_TX = 1 << 1, 113 PAUSE_AUTONEG = 1 << 2 114}; 115 116enum { 117 SUPPORTED_IRQ = 1 << 24 118}; 119 120enum { /* adapter interrupt-maintained statistics */ 121 STAT_ULP_CH0_PBL_OOB, 122 STAT_ULP_CH1_PBL_OOB, 123 STAT_PCI_CORR_ECC, 124 125 IRQ_NUM_STATS /* keep last */ 126}; 127 128enum { 129 TP_VERSION_MAJOR = 1, 130 TP_VERSION_MINOR = 1, 131 TP_VERSION_MICRO = 0 132}; 133 134#define S_TP_VERSION_MAJOR 16 135#define M_TP_VERSION_MAJOR 0xFF 136#define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR) 137#define G_TP_VERSION_MAJOR(x) \ 138 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR) 139 140#define S_TP_VERSION_MINOR 8 141#define M_TP_VERSION_MINOR 0xFF 142#define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR) 143#define G_TP_VERSION_MINOR(x) \ 144 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR) 145 146#define S_TP_VERSION_MICRO 0 147#define M_TP_VERSION_MICRO 0xFF 148#define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO) 149#define G_TP_VERSION_MICRO(x) \ 150 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) 151 152enum { 153 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ 154 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ 155 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ 156}; 157 158enum sge_context_type { /* SGE egress context types */ 159 SGE_CNTXT_RDMA = 0, 160 SGE_CNTXT_ETH = 2, 161 SGE_CNTXT_OFLD = 4, 162 SGE_CNTXT_CTRL = 5 163}; 164 165enum { 166 AN_PKT_SIZE = 32, /* async notification packet size */ 167 IMMED_PKT_SIZE = 48 /* packet size for immediate data */ 168}; 169 170struct sg_ent { /* SGE scatter/gather entry */ 171 __be32 len[2]; 172 __be64 addr[2]; 173}; 174 175#ifndef SGE_NUM_GENBITS 176/* Must be 1 or 2 */ 177# define SGE_NUM_GENBITS 2 178#endif 179 180#define TX_DESC_FLITS 16U 181#define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) 182 183struct cphy; 184struct adapter; 185 186struct mdio_ops { 187 int (*read)(struct adapter *adapter, int phy_addr, int mmd_addr, 188 int reg_addr, unsigned int *val); 189 int (*write)(struct adapter *adapter, int phy_addr, int mmd_addr, 190 int reg_addr, unsigned int val); 191}; 192 193struct adapter_info { 194 unsigned char nports; /* # of ports */ 195 unsigned char phy_base_addr; /* MDIO PHY base address */ 196 unsigned int gpio_out; /* GPIO output settings */ 197 unsigned char gpio_intr[MAX_NPORTS]; /* GPIO PHY IRQ pins */ 198 unsigned long caps; /* adapter capabilities */ 199 const struct mdio_ops *mdio_ops; /* MDIO operations */ 200 const char *desc; /* product description */ 201}; 202 203struct mc5_stats { 204 unsigned long parity_err; 205 unsigned long active_rgn_full; 206 unsigned long nfa_srch_err; 207 unsigned long unknown_cmd; 208 unsigned long reqq_parity_err; 209 unsigned long dispq_parity_err; 210 unsigned long del_act_empty; 211}; 212 213struct mc7_stats { 214 unsigned long corr_err; 215 unsigned long uncorr_err; 216 unsigned long parity_err; 217 unsigned long addr_err; 218}; 219 220struct mac_stats { 221 u64 tx_octets; /* total # of octets in good frames */ 222 u64 tx_octets_bad; /* total # of octets in error frames */ 223 u64 tx_frames; /* all good frames */ 224 u64 tx_mcast_frames; /* good multicast frames */ 225 u64 tx_bcast_frames; /* good broadcast frames */ 226 u64 tx_pause; /* # of transmitted pause frames */ 227 u64 tx_deferred; /* frames with deferred transmissions */ 228 u64 tx_late_collisions; /* # of late collisions */ 229 u64 tx_total_collisions; /* # of total collisions */ 230 u64 tx_excess_collisions; /* frame errors from excessive collissions */ 231 u64 tx_underrun; /* # of Tx FIFO underruns */ 232 u64 tx_len_errs; /* # of Tx length errors */ 233 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ 234 u64 tx_excess_deferral; /* # of frames with excessive deferral */ 235 u64 tx_fcs_errs; /* # of frames with bad FCS */ 236 237 u64 tx_frames_64; /* # of Tx frames in a particular range */ 238 u64 tx_frames_65_127; 239 u64 tx_frames_128_255; 240 u64 tx_frames_256_511; 241 u64 tx_frames_512_1023; 242 u64 tx_frames_1024_1518; 243 u64 tx_frames_1519_max; 244 245 u64 rx_octets; /* total # of octets in good frames */ 246 u64 rx_octets_bad; /* total # of octets in error frames */ 247 u64 rx_frames; /* all good frames */ 248 u64 rx_mcast_frames; /* good multicast frames */ 249 u64 rx_bcast_frames; /* good broadcast frames */ 250 u64 rx_pause; /* # of received pause frames */ 251 u64 rx_fcs_errs; /* # of received frames with bad FCS */ 252 u64 rx_align_errs; /* alignment errors */ 253 u64 rx_symbol_errs; /* symbol errors */ 254 u64 rx_data_errs; /* data errors */ 255 u64 rx_sequence_errs; /* sequence errors */ 256 u64 rx_runt; /* # of runt frames */ 257 u64 rx_jabber; /* # of jabber frames */ 258 u64 rx_short; /* # of short frames */ 259 u64 rx_too_long; /* # of oversized frames */ 260 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ 261 262 u64 rx_frames_64; /* # of Rx frames in a particular range */ 263 u64 rx_frames_65_127; 264 u64 rx_frames_128_255; 265 u64 rx_frames_256_511; 266 u64 rx_frames_512_1023; 267 u64 rx_frames_1024_1518; 268 u64 rx_frames_1519_max; 269 270 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ 271 272 unsigned long tx_fifo_parity_err; 273 unsigned long rx_fifo_parity_err; 274 unsigned long tx_fifo_urun; 275 unsigned long rx_fifo_ovfl; 276 unsigned long serdes_signal_loss; 277 unsigned long xaui_pcs_ctc_err; 278 unsigned long xaui_pcs_align_change; 279 280 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ 281 unsigned long num_resets; /* # times reset due to stuck TX */ 282 283}; 284 285struct tp_mib_stats { 286 u32 ipInReceive_hi; 287 u32 ipInReceive_lo; 288 u32 ipInHdrErrors_hi; 289 u32 ipInHdrErrors_lo; 290 u32 ipInAddrErrors_hi; 291 u32 ipInAddrErrors_lo; 292 u32 ipInUnknownProtos_hi; 293 u32 ipInUnknownProtos_lo; 294 u32 ipInDiscards_hi; 295 u32 ipInDiscards_lo; 296 u32 ipInDelivers_hi; 297 u32 ipInDelivers_lo; 298 u32 ipOutRequests_hi; 299 u32 ipOutRequests_lo; 300 u32 ipOutDiscards_hi; 301 u32 ipOutDiscards_lo; 302 u32 ipOutNoRoutes_hi; 303 u32 ipOutNoRoutes_lo; 304 u32 ipReasmTimeout; 305 u32 ipReasmReqds; 306 u32 ipReasmOKs; 307 u32 ipReasmFails; 308 309 u32 reserved[8]; 310 311 u32 tcpActiveOpens; 312 u32 tcpPassiveOpens; 313 u32 tcpAttemptFails; 314 u32 tcpEstabResets; 315 u32 tcpOutRsts; 316 u32 tcpCurrEstab; 317 u32 tcpInSegs_hi; 318 u32 tcpInSegs_lo; 319 u32 tcpOutSegs_hi; 320 u32 tcpOutSegs_lo; 321 u32 tcpRetransSeg_hi; 322 u32 tcpRetransSeg_lo; 323 u32 tcpInErrs_hi; 324 u32 tcpInErrs_lo; 325 u32 tcpRtoMin; 326 u32 tcpRtoMax; 327}; 328 329struct tp_params { 330 unsigned int nchan; /* # of channels */ 331 unsigned int pmrx_size; /* total PMRX capacity */ 332 unsigned int pmtx_size; /* total PMTX capacity */ 333 unsigned int cm_size; /* total CM capacity */ 334 unsigned int chan_rx_size; /* per channel Rx size */ 335 unsigned int chan_tx_size; /* per channel Tx size */ 336 unsigned int rx_pg_size; /* Rx page size */ 337 unsigned int tx_pg_size; /* Tx page size */ 338 unsigned int rx_num_pgs; /* # of Rx pages */ 339 unsigned int tx_num_pgs; /* # of Tx pages */ 340 unsigned int ntimer_qs; /* # of timer queues */ 341}; 342 343struct qset_params { /* SGE queue set parameters */ 344 unsigned int polling; /* polling/interrupt service for rspq */ 345 unsigned int lro; /* large receive offload */ 346 unsigned int coalesce_usecs; /* irq coalescing timer */ 347 unsigned int rspq_size; /* # of entries in response queue */ 348 unsigned int fl_size; /* # of entries in regular free list */ 349 unsigned int jumbo_size; /* # of entries in jumbo free list */ 350 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ 351 unsigned int cong_thres; /* FL congestion threshold */ 352 unsigned int vector; /* Interrupt (line or vector) number */ 353}; 354 355struct sge_params { 356 unsigned int max_pkt_size; /* max offload pkt size */ 357 struct qset_params qset[SGE_QSETS]; 358}; 359 360struct mc5_params { 361 unsigned int mode; /* selects MC5 width */ 362 unsigned int nservers; /* size of server region */ 363 unsigned int nfilters; /* size of filter region */ 364 unsigned int nroutes; /* size of routing region */ 365}; 366 367/* Default MC5 region sizes */ 368enum { 369 DEFAULT_NSERVERS = 512, 370 DEFAULT_NFILTERS = 128 371}; 372 373/* MC5 modes, these must be non-0 */ 374enum { 375 MC5_MODE_144_BIT = 1, 376 MC5_MODE_72_BIT = 2 377}; 378 379/* MC5 min active region size */ 380enum { MC5_MIN_TIDS = 16 }; 381 382struct vpd_params { 383 unsigned int cclk; 384 unsigned int mclk; 385 unsigned int uclk; 386 unsigned int mdc; 387 unsigned int mem_timing; 388 u8 sn[SERNUM_LEN + 1]; 389 u8 eth_base[6]; 390 u8 port_type[MAX_NPORTS]; 391 unsigned short xauicfg[2]; 392}; 393 394struct pci_params { 395 unsigned int vpd_cap_addr; 396 unsigned int pcie_cap_addr; 397 unsigned short speed; 398 unsigned char width; 399 unsigned char variant; 400}; 401 402enum { 403 PCI_VARIANT_PCI, 404 PCI_VARIANT_PCIX_MODE1_PARITY, 405 PCI_VARIANT_PCIX_MODE1_ECC, 406 PCI_VARIANT_PCIX_266_MODE2, 407 PCI_VARIANT_PCIE 408}; 409 410struct adapter_params { 411 struct sge_params sge; 412 struct mc5_params mc5; 413 struct tp_params tp; 414 struct vpd_params vpd; 415 struct pci_params pci; 416 417 const struct adapter_info *info; 418 419 unsigned short mtus[NMTUS]; 420 unsigned short a_wnd[NCCTRL_WIN]; 421 unsigned short b_wnd[NCCTRL_WIN]; 422 423 unsigned int nports; /* # of ethernet ports */ 424 unsigned int stats_update_period; /* MAC stats accumulation period */ 425 unsigned int linkpoll_period; /* link poll period in 0.1s */ 426 unsigned int rev; /* chip revision */ 427 unsigned int offload; 428}; 429 430enum { /* chip revisions */ 431 T3_REV_A = 0, 432 T3_REV_B = 2, 433 T3_REV_B2 = 3, 434 T3_REV_C = 4, 435}; 436 437struct trace_params { 438 u32 sip; 439 u32 sip_mask; 440 u32 dip; 441 u32 dip_mask; 442 u16 sport; 443 u16 sport_mask; 444 u16 dport; 445 u16 dport_mask; 446 u32 vlan:12; 447 u32 vlan_mask:12; 448 u32 intf:4; 449 u32 intf_mask:4; 450 u8 proto; 451 u8 proto_mask; 452}; 453 454struct link_config { 455 unsigned int supported; /* link capabilities */ 456 unsigned int advertising; /* advertised capabilities */ 457 unsigned short requested_speed; /* speed user has requested */ 458 unsigned short speed; /* actual link speed */ 459 unsigned char requested_duplex; /* duplex user has requested */ 460 unsigned char duplex; /* actual link duplex */ 461 unsigned char requested_fc; /* flow control user has requested */ 462 unsigned char fc; /* actual link flow control */ 463 unsigned char autoneg; /* autonegotiating? */ 464 unsigned int link_ok; /* link up? */ 465}; 466 467#define SPEED_INVALID 0xffff 468#define DUPLEX_INVALID 0xff 469 470struct mc5 { 471 struct adapter *adapter; 472 unsigned int tcam_size; 473 unsigned char part_type; 474 unsigned char parity_enabled; 475 unsigned char mode; 476 struct mc5_stats stats; 477}; 478 479static inline unsigned int t3_mc5_size(const struct mc5 *p) 480{ 481 return p->tcam_size; 482} 483 484struct mc7 { 485 struct adapter *adapter; /* backpointer to adapter */ 486 unsigned int size; /* memory size in bytes */ 487 unsigned int width; /* MC7 interface width */ 488 unsigned int offset; /* register address offset for MC7 instance */ 489 const char *name; /* name of MC7 instance */ 490 struct mc7_stats stats; /* MC7 statistics */ 491}; 492 493static inline unsigned int t3_mc7_size(const struct mc7 *p) 494{ 495 return p->size; 496} 497 498struct cmac { 499 struct adapter *adapter; 500 unsigned int offset; 501 unsigned int nucast; /* # of address filters for unicast MACs */ 502 unsigned int tx_tcnt; 503 unsigned int tx_xcnt; 504 u64 tx_mcnt; 505 unsigned int rx_xcnt; 506 unsigned int rx_ocnt; 507 u64 rx_mcnt; 508 unsigned int toggle_cnt; 509 unsigned int txen; 510 u64 rx_pause; 511 struct mac_stats stats; 512}; 513 514enum { 515 MAC_DIRECTION_RX = 1, 516 MAC_DIRECTION_TX = 2, 517 MAC_RXFIFO_SIZE = 32768 518}; 519 520/* IEEE 802.3 specified MDIO devices */ 521enum { 522 MDIO_DEV_PMA_PMD = 1, 523 MDIO_DEV_WIS = 2, 524 MDIO_DEV_PCS = 3, 525 MDIO_DEV_XGXS = 4 526}; 527 528/* PHY loopback direction */ 529enum { 530 PHY_LOOPBACK_TX = 1, 531 PHY_LOOPBACK_RX = 2 532}; 533 534/* PHY interrupt types */ 535enum { 536 cphy_cause_link_change = 1, 537 cphy_cause_fifo_error = 2 538}; 539 540/* PHY operations */ 541struct cphy_ops { 542 int (*reset)(struct cphy *phy, int wait); 543 544 int (*intr_enable)(struct cphy *phy); 545 int (*intr_disable)(struct cphy *phy); 546 int (*intr_clear)(struct cphy *phy); 547 int (*intr_handler)(struct cphy *phy); 548 549 int (*autoneg_enable)(struct cphy *phy); 550 int (*autoneg_restart)(struct cphy *phy); 551 552 int (*advertise)(struct cphy *phy, unsigned int advertise_map); 553 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); 554 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); 555 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed, 556 int *duplex, int *fc); 557 int (*power_down)(struct cphy *phy, int enable); 558}; 559 560/* A PHY instance */ 561struct cphy { 562 int addr; /* PHY address */ 563 unsigned int caps; /* PHY capabilities */ 564 struct adapter *adapter; /* associated adapter */ 565 const char *desc; /* PHY description */ 566 unsigned long fifo_errors; /* FIFO over/under-flows */ 567 const struct cphy_ops *ops; /* PHY operations */ 568 int (*mdio_read)(struct adapter *adapter, int phy_addr, int mmd_addr, 569 int reg_addr, unsigned int *val); 570 int (*mdio_write)(struct adapter *adapter, int phy_addr, int mmd_addr, 571 int reg_addr, unsigned int val); 572}; 573 574/* Convenience MDIO read/write wrappers */ 575static inline int mdio_read(struct cphy *phy, int mmd, int reg, 576 unsigned int *valp) 577{ 578 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp); 579} 580 581static inline int mdio_write(struct cphy *phy, int mmd, int reg, 582 unsigned int val) 583{ 584 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val); 585} 586 587/* Convenience initializer */ 588static inline void cphy_init(struct cphy *phy, struct adapter *adapter, 589 int phy_addr, struct cphy_ops *phy_ops, 590 const struct mdio_ops *mdio_ops, 591 unsigned int caps, const char *desc) 592{ 593 phy->addr = phy_addr; 594 phy->caps = caps; 595 phy->adapter = adapter; 596 phy->desc = desc; 597 phy->ops = phy_ops; 598 if (mdio_ops) { 599 phy->mdio_read = mdio_ops->read; 600 phy->mdio_write = mdio_ops->write; 601 } 602} 603 604/* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ 605#define MAC_STATS_ACCUM_SECS 180 606 607#define XGM_REG(reg_addr, idx) \ 608 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) 609 610struct addr_val_pair { 611 unsigned int reg_addr; 612 unsigned int val; 613}; 614 615#include "adapter.h" 616 617#ifndef PCI_VENDOR_ID_CHELSIO 618# define PCI_VENDOR_ID_CHELSIO 0x1425 619#endif 620 621#define for_each_port(adapter, iter) \ 622 for (iter = 0; iter < (adapter)->params.nports; ++iter) 623 624#define adapter_info(adap) ((adap)->params.info) 625 626static inline int uses_xaui(const struct adapter *adap) 627{ 628 return adapter_info(adap)->caps & SUPPORTED_AUI; 629} 630 631static inline int is_10G(const struct adapter *adap) 632{ 633 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; 634} 635 636static inline int is_offload(const struct adapter *adap) 637{ 638 return adap->params.offload; 639} 640 641static inline unsigned int core_ticks_per_usec(const struct adapter *adap) 642{ 643 return adap->params.vpd.cclk / 1000; 644} 645 646static inline unsigned int is_pcie(const struct adapter *adap) 647{ 648 return adap->params.pci.variant == PCI_VARIANT_PCIE; 649} 650 651void t3_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, 652 u32 val); 653void t3_write_regs(struct adapter *adapter, const struct addr_val_pair *p, 654 int n, unsigned int offset); 655int t3_wait_op_done_val(struct adapter *adapter, int reg, u32 mask, 656 int polarity, int attempts, int delay, u32 *valp); 657static inline int t3_wait_op_done(struct adapter *adapter, int reg, u32 mask, 658 int polarity, int attempts, int delay) 659{ 660 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, 661 delay, NULL); 662} 663int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, 664 unsigned int set); 665int t3_phy_reset(struct cphy *phy, int mmd, int wait); 666int t3_phy_advertise(struct cphy *phy, unsigned int advert); 667int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); 668 669void t3_intr_enable(struct adapter *adapter); 670void t3_intr_disable(struct adapter *adapter); 671void t3_intr_clear(struct adapter *adapter); 672void t3_port_intr_enable(struct adapter *adapter, int idx); 673void t3_port_intr_disable(struct adapter *adapter, int idx); 674void t3_port_intr_clear(struct adapter *adapter, int idx); 675int t3_slow_intr_handler(struct adapter *adapter); 676int t3_phy_intr_handler(struct adapter *adapter); 677 678void t3_link_changed(struct adapter *adapter, int port_id); 679int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 680const struct adapter_info *t3_get_adapter_info(unsigned int board_id); 681int t3_seeprom_read(struct adapter *adapter, u32 addr, __le32 *data); 682int t3_seeprom_write(struct adapter *adapter, u32 addr, __le32 data); 683int t3_seeprom_wp(struct adapter *adapter, int enable); 684int t3_get_tp_version(struct adapter *adapter, u32 *vers); 685int t3_check_tpsram_version(struct adapter *adapter, int *must_load); 686int t3_check_tpsram(struct adapter *adapter, const u8 *tp_ram, 687 unsigned int size); 688int t3_set_proto_sram(struct adapter *adap, const u8 *data); 689int t3_read_flash(struct adapter *adapter, unsigned int addr, 690 unsigned int nwords, u32 *data, int byte_oriented); 691int t3_load_fw(struct adapter *adapter, const u8 * fw_data, unsigned int size); 692int t3_get_fw_version(struct adapter *adapter, u32 *vers); 693int t3_check_fw_version(struct adapter *adapter, int *must_load); 694int t3_init_hw(struct adapter *adapter, u32 fw_params); 695void mac_prep(struct cmac *mac, struct adapter *adapter, int index); 696void early_hw_init(struct adapter *adapter, const struct adapter_info *ai); 697int t3_reset_adapter(struct adapter *adapter); 698int t3_prep_adapter(struct adapter *adapter, const struct adapter_info *ai, 699 int reset); 700int t3_replay_prep_adapter(struct adapter *adapter); 701void t3_led_ready(struct adapter *adapter); 702void t3_fatal_err(struct adapter *adapter); 703void t3_set_vlan_accel(struct adapter *adapter, unsigned int ports, int on); 704void t3_config_rss(struct adapter *adapter, unsigned int rss_config, 705 const u8 * cpus, const u16 *rspq); 706int t3_read_rss(struct adapter *adapter, u8 * lkup, u16 *map); 707int t3_mps_set_active_ports(struct adapter *adap, unsigned int port_mask); 708int t3_cim_ctl_blk_read(struct adapter *adap, unsigned int addr, 709 unsigned int n, unsigned int *valp); 710int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, 711 u64 *buf); 712 713int t3_mac_reset(struct cmac *mac); 714void t3b_pcs_reset(struct cmac *mac); 715int t3_mac_enable(struct cmac *mac, int which); 716int t3_mac_disable(struct cmac *mac, int which); 717int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); 718int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); 719int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); 720int t3_mac_set_num_ucast(struct cmac *mac, int n); 721const struct mac_stats *t3_mac_update_stats(struct cmac *mac); 722int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc); 723int t3b2_mac_watchdog_task(struct cmac *mac); 724 725void t3_mc5_prep(struct adapter *adapter, struct mc5 *mc5, int mode); 726int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 727 unsigned int nroutes); 728void t3_mc5_intr_handler(struct mc5 *mc5); 729int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, 730 u32 *buf); 731 732int t3_tp_set_coalescing_size(struct adapter *adap, unsigned int size, int psh); 733void t3_tp_set_max_rxsize(struct adapter *adap, unsigned int size); 734void t3_tp_set_offload_mode(struct adapter *adap, int enable); 735void t3_tp_get_mib_stats(struct adapter *adap, struct tp_mib_stats *tps); 736void t3_load_mtus(struct adapter *adap, unsigned short mtus[NMTUS], 737 unsigned short alpha[NCCTRL_WIN], 738 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); 739void t3_read_hw_mtus(struct adapter *adap, unsigned short mtus[NMTUS]); 740void t3_get_cong_cntl_tab(struct adapter *adap, 741 unsigned short incr[NMTUS][NCCTRL_WIN]); 742void t3_config_trace_filter(struct adapter *adapter, 743 const struct trace_params *tp, int filter_index, 744 int invert, int enable); 745int t3_config_sched(struct adapter *adap, unsigned int kbps, int sched); 746 747void t3_sge_prep(struct adapter *adap, struct sge_params *p); 748void t3_sge_init(struct adapter *adap, struct sge_params *p); 749int t3_sge_init_ecntxt(struct adapter *adapter, unsigned int id, int gts_enable, 750 enum sge_context_type type, int respq, u64 base_addr, 751 unsigned int size, unsigned int token, int gen, 752 unsigned int cidx); 753int t3_sge_init_flcntxt(struct adapter *adapter, unsigned int id, 754 int gts_enable, u64 base_addr, unsigned int size, 755 unsigned int esize, unsigned int cong_thres, int gen, 756 unsigned int cidx); 757int t3_sge_init_rspcntxt(struct adapter *adapter, unsigned int id, 758 int irq_vec_idx, u64 base_addr, unsigned int size, 759 unsigned int fl_thres, int gen, unsigned int cidx); 760int t3_sge_init_cqcntxt(struct adapter *adapter, unsigned int id, u64 base_addr, 761 unsigned int size, int rspq, int ovfl_mode, 762 unsigned int credits, unsigned int credit_thres); 763int t3_sge_enable_ecntxt(struct adapter *adapter, unsigned int id, int enable); 764int t3_sge_disable_fl(struct adapter *adapter, unsigned int id); 765int t3_sge_disable_rspcntxt(struct adapter *adapter, unsigned int id); 766int t3_sge_disable_cqcntxt(struct adapter *adapter, unsigned int id); 767int t3_sge_read_ecntxt(struct adapter *adapter, unsigned int id, u32 data[4]); 768int t3_sge_read_fl(struct adapter *adapter, unsigned int id, u32 data[4]); 769int t3_sge_read_cq(struct adapter *adapter, unsigned int id, u32 data[4]); 770int t3_sge_read_rspq(struct adapter *adapter, unsigned int id, u32 data[4]); 771int t3_sge_cqcntxt_op(struct adapter *adapter, unsigned int id, unsigned int op, 772 unsigned int credits); 773 774int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter, 775 int phy_addr, const struct mdio_ops *mdio_ops); 776int t3_ael1002_phy_prep(struct cphy *phy, struct adapter *adapter, 777 int phy_addr, const struct mdio_ops *mdio_ops); 778int t3_ael1006_phy_prep(struct cphy *phy, struct adapter *adapter, 779 int phy_addr, const struct mdio_ops *mdio_ops); 780int t3_qt2045_phy_prep(struct cphy *phy, struct adapter *adapter, int phy_addr, 781 const struct mdio_ops *mdio_ops); 782int t3_xaui_direct_phy_prep(struct cphy *phy, struct adapter *adapter, 783 int phy_addr, const struct mdio_ops *mdio_ops); 784#endif /* __CHELSIO_COMMON_H */ 785