defines.h revision 1241f29fa3c6fa95f20e3e77452f8d6d60deae7a
1/******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27*******************************************************************************/ 28 29#ifndef _E1000_DEFINES_H_ 30#define _E1000_DEFINES_H_ 31 32#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 33#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 34#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 35#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 36#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 37#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 38#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 39#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 40#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 41#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 42#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 43#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 44#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 45#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 46#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 47#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 48#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 49#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 50 51/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 52#define REQ_TX_DESCRIPTOR_MULTIPLE 8 53#define REQ_RX_DESCRIPTOR_MULTIPLE 8 54 55/* Definitions for power management and wakeup registers */ 56/* Wake Up Control */ 57#define E1000_WUC_APME 0x00000001 /* APM Enable */ 58#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 59#define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 60 61/* Wake Up Filter Control */ 62#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 63#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 64#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 65#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 66#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 67#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 68 69/* Wake Up Status */ 70#define E1000_WUS_LNKC E1000_WUFC_LNKC 71#define E1000_WUS_MAG E1000_WUFC_MAG 72#define E1000_WUS_EX E1000_WUFC_EX 73#define E1000_WUS_MC E1000_WUFC_MC 74#define E1000_WUS_BC E1000_WUFC_BC 75 76/* Extended Device Control */ 77#define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 78#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ 79#define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 80#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 81#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 82#define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 83#define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ 84#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 85#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 86#define E1000_CTRL_EXT_EIAME 0x01000000 87#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 88#define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 89#define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 90#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 91#define E1000_CTRL_EXT_LSECCK 0x00001000 92#define E1000_CTRL_EXT_PHYPDEN 0x00100000 93 94/* Receive Descriptor bit definitions */ 95#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 96#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 97#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 98#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 99#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 100#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 101#define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 102#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 103#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 104#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 105#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 106#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 107#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 108#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 109 110#define E1000_RXDEXT_STATERR_CE 0x01000000 111#define E1000_RXDEXT_STATERR_SE 0x02000000 112#define E1000_RXDEXT_STATERR_SEQ 0x04000000 113#define E1000_RXDEXT_STATERR_CXE 0x10000000 114#define E1000_RXDEXT_STATERR_RXE 0x80000000 115 116/* mask to determine if packets should be dropped due to frame errors */ 117#define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 118 E1000_RXD_ERR_CE | \ 119 E1000_RXD_ERR_SE | \ 120 E1000_RXD_ERR_SEQ | \ 121 E1000_RXD_ERR_CXE | \ 122 E1000_RXD_ERR_RXE) 123 124/* Same mask, but for extended and packet split descriptors */ 125#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 126 E1000_RXDEXT_STATERR_CE | \ 127 E1000_RXDEXT_STATERR_SE | \ 128 E1000_RXDEXT_STATERR_SEQ | \ 129 E1000_RXDEXT_STATERR_CXE | \ 130 E1000_RXDEXT_STATERR_RXE) 131 132#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 133#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 134#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 135#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 136#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 137#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 138 139#define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 140 141/* Management Control */ 142#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 143#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 144#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 145#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 146#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 147/* Enable MAC address filtering */ 148#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 149/* Enable MNG packets to host memory */ 150#define E1000_MANC_EN_MNG2HOST 0x00200000 151 152#define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 153#define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 154#define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 155#define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 156 157/* Receive Control */ 158#define E1000_RCTL_EN 0x00000002 /* enable */ 159#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 160#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 161#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 162#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 163#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 164#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 165#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 166#define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 167#define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */ 168#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 169#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 170#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 171/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 172#define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 173#define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 174#define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 175#define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 176/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 177#define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 178#define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 179#define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 180#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 181#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 182#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 183#define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ 184#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 185#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 186#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 187 188/* Use byte values for the following shift parameters 189 * Usage: 190 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 191 * E1000_PSRCTL_BSIZE0_MASK) | 192 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 193 * E1000_PSRCTL_BSIZE1_MASK) | 194 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 195 * E1000_PSRCTL_BSIZE2_MASK) | 196 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 197 * E1000_PSRCTL_BSIZE3_MASK)) 198 * where value0 = [128..16256], default=256 199 * value1 = [1024..64512], default=4096 200 * value2 = [0..64512], default=4096 201 * value3 = [0..64512], default=0 202 */ 203 204#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 205#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 206#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 207#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 208 209#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 210#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 211#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 212#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 213 214/* SWFW_SYNC Definitions */ 215#define E1000_SWFW_EEP_SM 0x1 216#define E1000_SWFW_PHY0_SM 0x2 217#define E1000_SWFW_PHY1_SM 0x4 218#define E1000_SWFW_CSR_SM 0x8 219 220/* Device Control */ 221#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 222#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 223#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 224#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 225#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 226#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 227#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 228#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 229#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 230#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 231#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 232#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 233#define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 234#define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 235#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 236#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 237#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 238#define E1000_CTRL_RST 0x04000000 /* Global reset */ 239#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 240#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 241#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 242#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 243 244#define E1000_PCS_LCTL_FORCE_FCTRL 0x80 245 246#define E1000_PCS_LSTS_AN_COMPLETE 0x10000 247 248/* Device Status */ 249#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 250#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 251#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 252#define E1000_STATUS_FUNC_SHIFT 2 253#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 254#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 255#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 256#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 257#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 258#define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ 259#define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 260#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 261 262/* Constants used to interpret the masked PCI-X bus speed. */ 263 264#define HALF_DUPLEX 1 265#define FULL_DUPLEX 2 266 267 268#define ADVERTISE_10_HALF 0x0001 269#define ADVERTISE_10_FULL 0x0002 270#define ADVERTISE_100_HALF 0x0004 271#define ADVERTISE_100_FULL 0x0008 272#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 273#define ADVERTISE_1000_FULL 0x0020 274 275/* 1000/H is not supported, nor spec-compliant. */ 276#define E1000_ALL_SPEED_DUPLEX ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 277 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 278 ADVERTISE_1000_FULL) 279#define E1000_ALL_NOT_GIG ( ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 280 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 281#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 282#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 283#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 284 285#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 286 287/* LED Control */ 288#define E1000_PHY_LED0_MODE_MASK 0x00000007 289#define E1000_PHY_LED0_IVRT 0x00000008 290#define E1000_PHY_LED0_MASK 0x0000001F 291 292#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 293#define E1000_LEDCTL_LED0_MODE_SHIFT 0 294#define E1000_LEDCTL_LED0_IVRT 0x00000040 295#define E1000_LEDCTL_LED0_BLINK 0x00000080 296 297#define E1000_LEDCTL_MODE_LINK_UP 0x2 298#define E1000_LEDCTL_MODE_LED_ON 0xE 299#define E1000_LEDCTL_MODE_LED_OFF 0xF 300 301/* Transmit Descriptor bit definitions */ 302#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 303#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 304#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 305#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 306#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 307#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 308#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 309#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 310#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 311#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 312#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 313#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 314#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 315#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 316#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 317#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 318#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 319#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 320#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 321 322/* Transmit Control */ 323#define E1000_TCTL_EN 0x00000002 /* enable Tx */ 324#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 325#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 326#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 327#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 328#define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 329 330/* Transmit Arbitration Count */ 331 332/* SerDes Control */ 333#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 334 335/* Receive Checksum Control */ 336#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 337#define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 338#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 339 340/* Header split receive */ 341#define E1000_RFCTL_NFSW_DIS 0x00000040 342#define E1000_RFCTL_NFSR_DIS 0x00000080 343#define E1000_RFCTL_ACK_DIS 0x00001000 344#define E1000_RFCTL_EXTEN 0x00008000 345#define E1000_RFCTL_IPV6_EX_DIS 0x00010000 346#define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 347 348/* Collision related configuration parameters */ 349#define E1000_COLLISION_THRESHOLD 15 350#define E1000_CT_SHIFT 4 351#define E1000_COLLISION_DISTANCE 63 352#define E1000_COLD_SHIFT 12 353 354/* Default values for the transmit IPG register */ 355#define DEFAULT_82543_TIPG_IPGT_COPPER 8 356 357#define E1000_TIPG_IPGT_MASK 0x000003FF 358 359#define DEFAULT_82543_TIPG_IPGR1 8 360#define E1000_TIPG_IPGR1_SHIFT 10 361 362#define DEFAULT_82543_TIPG_IPGR2 6 363#define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 364#define E1000_TIPG_IPGR2_SHIFT 20 365 366#define MAX_JUMBO_FRAME_SIZE 0x3F00 367 368/* Extended Configuration Control and Size */ 369#define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 370#define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 371#define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 372#define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 373#define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 374#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 375#define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 376#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 377#define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 378 379#define E1000_PHY_CTRL_D0A_LPLU 0x00000002 380#define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 381#define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 382#define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 383 384#define E1000_KABGTXD_BGSQLBIAS 0x00050000 385 386/* PBA constants */ 387#define E1000_PBA_8K 0x0008 /* 8KB */ 388#define E1000_PBA_16K 0x0010 /* 16KB */ 389 390#define E1000_PBS_16K E1000_PBA_16K 391 392#define IFS_MAX 80 393#define IFS_MIN 40 394#define IFS_RATIO 4 395#define IFS_STEP 10 396#define MIN_NUM_XMITS 1000 397 398/* SW Semaphore Register */ 399#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 400#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 401#define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 402 403#define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 404 405/* Interrupt Cause Read */ 406#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 407#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 408#define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 409#define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 410#define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 411#define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 412#define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 413#define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 414#define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 415#define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 416#define E1000_ICR_OTHER 0x01000000 /* Other Interrupts */ 417 418/* PBA ECC Register */ 419#define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 420#define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 421#define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */ 422#define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 423#define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */ 424 425/* This defines the bits that are set in the Interrupt Mask 426 * Set/Read Register. Each bit is documented below: 427 * o RXT0 = Receiver Timer Interrupt (ring 0) 428 * o TXDW = Transmit Descriptor Written Back 429 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 430 * o RXSEQ = Receive Sequence Error 431 * o LSC = Link Status Change 432 */ 433#define IMS_ENABLE_MASK ( \ 434 E1000_IMS_RXT0 | \ 435 E1000_IMS_TXDW | \ 436 E1000_IMS_RXDMT0 | \ 437 E1000_IMS_RXSEQ | \ 438 E1000_IMS_LSC) 439 440/* Interrupt Mask Set */ 441#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 442#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 443#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 444#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 445#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 446#define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 447#define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 448#define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 449#define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 450#define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupts */ 451 452/* Interrupt Cause Set */ 453#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 454#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 455#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 456 457/* Transmit Descriptor Control */ 458#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 459#define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 460#define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 461#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 462#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 463#define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 464/* Enable the counting of desc. still to be processed. */ 465#define E1000_TXDCTL_COUNT_DESC 0x00400000 466 467/* Flow Control Constants */ 468#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 469#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 470#define FLOW_CONTROL_TYPE 0x8808 471 472/* 802.1q VLAN Packet Size */ 473#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 474 475/* Receive Address 476 * Number of high/low register pairs in the RAR. The RAR (Receive Address 477 * Registers) holds the directed and multicast addresses that we monitor. 478 * Technically, we have 16 spots. However, we reserve one of these spots 479 * (RAR[15]) for our directed address used by controllers with 480 * manageability enabled, allowing us room for 15 multicast addresses. 481 */ 482#define E1000_RAR_ENTRIES 15 483#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 484#define E1000_RAL_MAC_ADDR_LEN 4 485#define E1000_RAH_MAC_ADDR_LEN 2 486 487/* Error Codes */ 488#define E1000_ERR_NVM 1 489#define E1000_ERR_PHY 2 490#define E1000_ERR_CONFIG 3 491#define E1000_ERR_PARAM 4 492#define E1000_ERR_MAC_INIT 5 493#define E1000_ERR_PHY_TYPE 6 494#define E1000_ERR_RESET 9 495#define E1000_ERR_MASTER_REQUESTS_PENDING 10 496#define E1000_ERR_HOST_INTERFACE_COMMAND 11 497#define E1000_BLK_PHY_RESET 12 498#define E1000_ERR_SWFW_SYNC 13 499#define E1000_NOT_IMPLEMENTED 14 500#define E1000_ERR_INVALID_ARGUMENT 16 501#define E1000_ERR_NO_SPACE 17 502#define E1000_ERR_NVM_PBA_SECTION 18 503 504/* Loop limit on how long we wait for auto-negotiation to complete */ 505#define FIBER_LINK_UP_LIMIT 50 506#define COPPER_LINK_UP_LIMIT 10 507#define PHY_AUTO_NEG_LIMIT 45 508#define PHY_FORCE_LIMIT 20 509/* Number of 100 microseconds we wait for PCI Express master disable */ 510#define MASTER_DISABLE_TIMEOUT 800 511/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 512#define PHY_CFG_TIMEOUT 100 513/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 514#define MDIO_OWNERSHIP_TIMEOUT 10 515/* Number of milliseconds for NVM auto read done after MAC reset. */ 516#define AUTO_READ_DONE_TIMEOUT 10 517 518/* Flow Control */ 519#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 520#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 521#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 522 523/* Transmit Configuration Word */ 524#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 525#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 526#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 527#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 528#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 529 530/* Receive Configuration Word */ 531#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 532#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 533#define E1000_RXCW_C 0x20000000 /* Receive config */ 534#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 535 536/* PCI Express Control */ 537#define E1000_GCR_RXD_NO_SNOOP 0x00000001 538#define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 539#define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 540#define E1000_GCR_TXD_NO_SNOOP 0x00000008 541#define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 542#define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 543 544#define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 545 E1000_GCR_RXDSCW_NO_SNOOP | \ 546 E1000_GCR_RXDSCR_NO_SNOOP | \ 547 E1000_GCR_TXD_NO_SNOOP | \ 548 E1000_GCR_TXDSCW_NO_SNOOP | \ 549 E1000_GCR_TXDSCR_NO_SNOOP) 550 551/* PHY Control Register */ 552#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 553#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 554#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 555#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 556#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 557#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 558#define MII_CR_SPEED_1000 0x0040 559#define MII_CR_SPEED_100 0x2000 560#define MII_CR_SPEED_10 0x0000 561 562/* PHY Status Register */ 563#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 564#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 565 566/* Autoneg Advertisement Register */ 567#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 568#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 569#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 570#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 571#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 572#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 573 574/* Link Partner Ability Register (Base Page) */ 575#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP 100TX Full Dplx Capable */ 576#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 577#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 578 579/* Autoneg Expansion Register */ 580#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 581 582/* 1000BASE-T Control Register */ 583#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 584#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 585 /* 0=DTE device */ 586#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 587 /* 0=Configure PHY as Slave */ 588#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 589 /* 0=Automatic Master/Slave config */ 590 591/* 1000BASE-T Status Register */ 592#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 593#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 594 595 596/* PHY 1000 MII Register/Bit Definitions */ 597/* PHY Registers defined by IEEE */ 598#define PHY_CONTROL 0x00 /* Control Register */ 599#define PHY_STATUS 0x01 /* Status Register */ 600#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 601#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 602#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 603#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 604#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 605#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 606#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 607#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 608 609#define PHY_CONTROL_LB 0x4000 /* PHY Loopback bit */ 610 611/* NVM Control */ 612#define E1000_EECD_SK 0x00000001 /* NVM Clock */ 613#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 614#define E1000_EECD_DI 0x00000004 /* NVM Data In */ 615#define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 616#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 617#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 618#define E1000_EECD_PRES 0x00000100 /* NVM Present */ 619#define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 620/* NVM Addressing bits based on type (0-small, 1-large) */ 621#define E1000_EECD_ADDR_BITS 0x00000400 622#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 623#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 624#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 625#define E1000_EECD_SIZE_EX_SHIFT 11 626#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 627#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 628#define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 629#define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 630 631#define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM read/write registers */ 632#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 633#define E1000_NVM_RW_REG_START 1 /* Start operation */ 634#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 635#define E1000_NVM_POLL_WRITE 1 /* Flag for polling for write complete */ 636#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 637#define E1000_FLASH_UPDATES 2000 638 639/* NVM Word Offsets */ 640#define NVM_COMPAT 0x0003 641#define NVM_ID_LED_SETTINGS 0x0004 642#define NVM_INIT_CONTROL2_REG 0x000F 643#define NVM_INIT_CONTROL3_PORT_B 0x0014 644#define NVM_INIT_3GIO_3 0x001A 645#define NVM_INIT_CONTROL3_PORT_A 0x0024 646#define NVM_CFG 0x0012 647#define NVM_ALT_MAC_ADDR_PTR 0x0037 648#define NVM_CHECKSUM_REG 0x003F 649 650#define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */ 651 652#define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ 653#define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ 654 655/* Mask bits for fields in Word 0x0f of the NVM */ 656#define NVM_WORD0F_PAUSE_MASK 0x3000 657#define NVM_WORD0F_PAUSE 0x1000 658#define NVM_WORD0F_ASM_DIR 0x2000 659 660/* Mask bits for fields in Word 0x1a of the NVM */ 661#define NVM_WORD1A_ASPM_MASK 0x000C 662 663/* Mask bits for fields in Word 0x03 of the EEPROM */ 664#define NVM_COMPAT_LOM 0x0800 665 666/* length of string needed to store PBA number */ 667#define E1000_PBANUM_LENGTH 11 668 669/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 670#define NVM_SUM 0xBABA 671 672/* PBA (printed board assembly) number words */ 673#define NVM_PBA_OFFSET_0 8 674#define NVM_PBA_OFFSET_1 9 675#define NVM_PBA_PTR_GUARD 0xFAFA 676#define NVM_WORD_SIZE_BASE_SHIFT 6 677 678/* NVM Commands - SPI */ 679#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 680#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 681#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 682#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 683#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 684#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 685 686/* SPI NVM Status Register */ 687#define NVM_STATUS_RDY_SPI 0x01 688 689/* Word definitions for ID LED Settings */ 690#define ID_LED_RESERVED_0000 0x0000 691#define ID_LED_RESERVED_FFFF 0xFFFF 692#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 693 (ID_LED_OFF1_OFF2 << 8) | \ 694 (ID_LED_DEF1_DEF2 << 4) | \ 695 (ID_LED_DEF1_DEF2)) 696#define ID_LED_DEF1_DEF2 0x1 697#define ID_LED_DEF1_ON2 0x2 698#define ID_LED_DEF1_OFF2 0x3 699#define ID_LED_ON1_DEF2 0x4 700#define ID_LED_ON1_ON2 0x5 701#define ID_LED_ON1_OFF2 0x6 702#define ID_LED_OFF1_DEF2 0x7 703#define ID_LED_OFF1_ON2 0x8 704#define ID_LED_OFF1_OFF2 0x9 705 706#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 707#define IGP_ACTIVITY_LED_ENABLE 0x0300 708#define IGP_LED3_MODE 0x07000000 709 710/* PCI/PCI-X/PCI-EX Config space */ 711#define PCI_HEADER_TYPE_REGISTER 0x0E 712#define PCIE_LINK_STATUS 0x12 713 714#define PCI_HEADER_TYPE_MULTIFUNC 0x80 715#define PCIE_LINK_WIDTH_MASK 0x3F0 716#define PCIE_LINK_WIDTH_SHIFT 4 717 718#define PHY_REVISION_MASK 0xFFFFFFF0 719#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 720#define MAX_PHY_MULTI_PAGE_REG 0xF 721 722/* Bit definitions for valid PHY IDs. 723 * I = Integrated 724 * E = External 725 */ 726#define M88E1000_E_PHY_ID 0x01410C50 727#define M88E1000_I_PHY_ID 0x01410C30 728#define M88E1011_I_PHY_ID 0x01410C20 729#define IGP01E1000_I_PHY_ID 0x02A80380 730#define M88E1111_I_PHY_ID 0x01410CC0 731#define GG82563_E_PHY_ID 0x01410CA0 732#define IGP03E1000_E_PHY_ID 0x02A80390 733#define IFE_E_PHY_ID 0x02A80330 734#define IFE_PLUS_E_PHY_ID 0x02A80320 735#define IFE_C_E_PHY_ID 0x02A80310 736#define BME1000_E_PHY_ID 0x01410CB0 737#define BME1000_E_PHY_ID_R2 0x01410CB1 738#define I82577_E_PHY_ID 0x01540050 739#define I82578_E_PHY_ID 0x004DD040 740#define I82579_E_PHY_ID 0x01540090 741#define I217_E_PHY_ID 0x015400A0 742 743/* M88E1000 Specific Registers */ 744#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 745#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 746#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 747 748#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 749#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 750 751/* M88E1000 PHY Specific Control Register */ 752#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 753#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 754 /* Manual MDI configuration */ 755#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 756/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 757#define M88E1000_PSCR_AUTO_X_1000T 0x0040 758/* Auto crossover enabled all speeds */ 759#define M88E1000_PSCR_AUTO_X_MODE 0x0060 760/* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold) 761 * 0=Normal 10BASE-T Rx Threshold 762 */ 763#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 764 765/* M88E1000 PHY Specific Status Register */ 766#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 767#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 768#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 769/* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */ 770#define M88E1000_PSSR_CABLE_LENGTH 0x0380 771#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 772#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 773 774#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 775 776/* Number of times we will attempt to autonegotiate before downshifting if we 777 * are the master 778 */ 779#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 780#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 781/* Number of times we will attempt to autonegotiate before downshifting if we 782 * are the slave 783 */ 784#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 785#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 786#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 787 788/* M88EC018 Rev 2 specific DownShift settings */ 789#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 790#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 791 792#define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 793#define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 794 795/* BME1000 PHY Specific Control Register */ 796#define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 797 798 799#define PHY_PAGE_SHIFT 5 800#define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ 801 ((reg) & MAX_PHY_REG_ADDRESS)) 802 803/* Bits... 804 * 15-5: page 805 * 4-0: register offset 806 */ 807#define GG82563_PAGE_SHIFT 5 808#define GG82563_REG(page, reg) \ 809 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 810#define GG82563_MIN_ALT_REG 30 811 812/* GG82563 Specific Registers */ 813#define GG82563_PHY_SPEC_CTRL \ 814 GG82563_REG(0, 16) /* PHY Specific Control */ 815#define GG82563_PHY_PAGE_SELECT \ 816 GG82563_REG(0, 22) /* Page Select */ 817#define GG82563_PHY_SPEC_CTRL_2 \ 818 GG82563_REG(0, 26) /* PHY Specific Control 2 */ 819#define GG82563_PHY_PAGE_SELECT_ALT \ 820 GG82563_REG(0, 29) /* Alternate Page Select */ 821 822#define GG82563_PHY_MAC_SPEC_CTRL \ 823 GG82563_REG(2, 21) /* MAC Specific Control Register */ 824 825#define GG82563_PHY_DSP_DISTANCE \ 826 GG82563_REG(5, 26) /* DSP Distance */ 827 828/* Page 193 - Port Control Registers */ 829#define GG82563_PHY_KMRN_MODE_CTRL \ 830 GG82563_REG(193, 16) /* Kumeran Mode Control */ 831#define GG82563_PHY_PWR_MGMT_CTRL \ 832 GG82563_REG(193, 20) /* Power Management Control */ 833 834/* Page 194 - KMRN Registers */ 835#define GG82563_PHY_INBAND_CTRL \ 836 GG82563_REG(194, 18) /* Inband Control */ 837 838/* MDI Control */ 839#define E1000_MDIC_REG_SHIFT 16 840#define E1000_MDIC_PHY_SHIFT 21 841#define E1000_MDIC_OP_WRITE 0x04000000 842#define E1000_MDIC_OP_READ 0x08000000 843#define E1000_MDIC_READY 0x10000000 844#define E1000_MDIC_ERROR 0x40000000 845 846/* SerDes Control */ 847#define E1000_GEN_POLL_TIMEOUT 640 848 849/* FW Semaphore */ 850#define E1000_FWSM_WLOCK_MAC_MASK 0x0380 851#define E1000_FWSM_WLOCK_MAC_SHIFT 7 852 853#endif /* _E1000_DEFINES_H_ */ 854