mac.c revision 57cde7630c1911ea7e8e1561cccfde8096e8bcc7
1/******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27*******************************************************************************/ 28 29#include "e1000.h" 30 31/** 32 * e1000e_get_bus_info_pcie - Get PCIe bus information 33 * @hw: pointer to the HW structure 34 * 35 * Determines and stores the system bus information for a particular 36 * network interface. The following bus information is determined and stored: 37 * bus speed, bus width, type (PCIe), and PCIe function. 38 **/ 39s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw) 40{ 41 struct e1000_mac_info *mac = &hw->mac; 42 struct e1000_bus_info *bus = &hw->bus; 43 struct e1000_adapter *adapter = hw->adapter; 44 u16 pcie_link_status, cap_offset; 45 46 cap_offset = adapter->pdev->pcie_cap; 47 if (!cap_offset) { 48 bus->width = e1000_bus_width_unknown; 49 } else { 50 pci_read_config_word(adapter->pdev, 51 cap_offset + PCIE_LINK_STATUS, 52 &pcie_link_status); 53 bus->width = (enum e1000_bus_width)((pcie_link_status & 54 PCIE_LINK_WIDTH_MASK) >> 55 PCIE_LINK_WIDTH_SHIFT); 56 } 57 58 mac->ops.set_lan_id(hw); 59 60 return 0; 61} 62 63/** 64 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 65 * 66 * @hw: pointer to the HW structure 67 * 68 * Determines the LAN function id by reading memory-mapped registers 69 * and swaps the port value if requested. 70 **/ 71void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 72{ 73 struct e1000_bus_info *bus = &hw->bus; 74 u32 reg; 75 76 /* 77 * The status register reports the correct function number 78 * for the device regardless of function swap state. 79 */ 80 reg = er32(STATUS); 81 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 82} 83 84/** 85 * e1000_set_lan_id_single_port - Set LAN id for a single port device 86 * @hw: pointer to the HW structure 87 * 88 * Sets the LAN function id to zero for a single port device. 89 **/ 90void e1000_set_lan_id_single_port(struct e1000_hw *hw) 91{ 92 struct e1000_bus_info *bus = &hw->bus; 93 94 bus->func = 0; 95} 96 97/** 98 * e1000_clear_vfta_generic - Clear VLAN filter table 99 * @hw: pointer to the HW structure 100 * 101 * Clears the register array which contains the VLAN filter table by 102 * setting all the values to 0. 103 **/ 104void e1000_clear_vfta_generic(struct e1000_hw *hw) 105{ 106 u32 offset; 107 108 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 109 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 110 e1e_flush(); 111 } 112} 113 114/** 115 * e1000_write_vfta_generic - Write value to VLAN filter table 116 * @hw: pointer to the HW structure 117 * @offset: register offset in VLAN filter table 118 * @value: register value written to VLAN filter table 119 * 120 * Writes value at the given offset in the register array which stores 121 * the VLAN filter table. 122 **/ 123void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 124{ 125 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 126 e1e_flush(); 127} 128 129/** 130 * e1000e_init_rx_addrs - Initialize receive address's 131 * @hw: pointer to the HW structure 132 * @rar_count: receive address registers 133 * 134 * Setup the receive address registers by setting the base receive address 135 * register to the devices MAC address and clearing all the other receive 136 * address registers to 0. 137 **/ 138void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) 139{ 140 u32 i; 141 u8 mac_addr[ETH_ALEN] = { 0 }; 142 143 /* Setup the receive address */ 144 e_dbg("Programming MAC Address into RAR[0]\n"); 145 146 e1000e_rar_set(hw, hw->mac.addr, 0); 147 148 /* Zero out the other (rar_entry_count - 1) receive addresses */ 149 e_dbg("Clearing RAR[1-%u]\n", rar_count - 1); 150 for (i = 1; i < rar_count; i++) 151 e1000e_rar_set(hw, mac_addr, i); 152} 153 154/** 155 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 156 * @hw: pointer to the HW structure 157 * 158 * Checks the nvm for an alternate MAC address. An alternate MAC address 159 * can be setup by pre-boot software and must be treated like a permanent 160 * address and must override the actual permanent MAC address. If an 161 * alternate MAC address is found it is programmed into RAR0, replacing 162 * the permanent address that was installed into RAR0 by the Si on reset. 163 * This function will return SUCCESS unless it encounters an error while 164 * reading the EEPROM. 165 **/ 166s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 167{ 168 u32 i; 169 s32 ret_val = 0; 170 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 171 u8 alt_mac_addr[ETH_ALEN]; 172 173 ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data); 174 if (ret_val) 175 return ret_val; 176 177 /* not supported on 82573 */ 178 if (hw->mac.type == e1000_82573) 179 return 0; 180 181 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, 182 &nvm_alt_mac_addr_offset); 183 if (ret_val) { 184 e_dbg("NVM Read Error\n"); 185 return ret_val; 186 } 187 188 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 189 (nvm_alt_mac_addr_offset == 0x0000)) 190 /* There is no Alternate MAC Address */ 191 return 0; 192 193 if (hw->bus.func == E1000_FUNC_1) 194 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 195 for (i = 0; i < ETH_ALEN; i += 2) { 196 offset = nvm_alt_mac_addr_offset + (i >> 1); 197 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); 198 if (ret_val) { 199 e_dbg("NVM Read Error\n"); 200 return ret_val; 201 } 202 203 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 204 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 205 } 206 207 /* if multicast bit is set, the alternate address will not be used */ 208 if (is_multicast_ether_addr(alt_mac_addr)) { 209 e_dbg("Ignoring Alternate Mac Address with MC bit set\n"); 210 return 0; 211 } 212 213 /* 214 * We have a valid alternate MAC address, and we want to treat it the 215 * same as the normal permanent MAC address stored by the HW into the 216 * RAR. Do this by mapping this address into RAR0. 217 */ 218 e1000e_rar_set(hw, alt_mac_addr, 0); 219 220 return 0; 221} 222 223/** 224 * e1000e_rar_set - Set receive address register 225 * @hw: pointer to the HW structure 226 * @addr: pointer to the receive address 227 * @index: receive address array register 228 * 229 * Sets the receive address array register at index to the address passed 230 * in by addr. 231 **/ 232void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) 233{ 234 u32 rar_low, rar_high; 235 236 /* 237 * HW expects these in little endian so we reverse the byte order 238 * from network order (big endian) to little endian 239 */ 240 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 241 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 242 243 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 244 245 /* If MAC address zero, no need to set the AV bit */ 246 if (rar_low || rar_high) 247 rar_high |= E1000_RAH_AV; 248 249 /* 250 * Some bridges will combine consecutive 32-bit writes into 251 * a single burst write, which will malfunction on some parts. 252 * The flushes avoid this. 253 */ 254 ew32(RAL(index), rar_low); 255 e1e_flush(); 256 ew32(RAH(index), rar_high); 257 e1e_flush(); 258} 259 260/** 261 * e1000_hash_mc_addr - Generate a multicast hash value 262 * @hw: pointer to the HW structure 263 * @mc_addr: pointer to a multicast address 264 * 265 * Generates a multicast address hash value which is used to determine 266 * the multicast filter table array address and new table value. See 267 * e1000_mta_set_generic() 268 **/ 269static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 270{ 271 u32 hash_value, hash_mask; 272 u8 bit_shift = 0; 273 274 /* Register count multiplied by bits per register */ 275 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 276 277 /* 278 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 279 * where 0xFF would still fall within the hash mask. 280 */ 281 while (hash_mask >> bit_shift != 0xFF) 282 bit_shift++; 283 284 /* 285 * The portion of the address that is used for the hash table 286 * is determined by the mc_filter_type setting. 287 * The algorithm is such that there is a total of 8 bits of shifting. 288 * The bit_shift for a mc_filter_type of 0 represents the number of 289 * left-shifts where the MSB of mc_addr[5] would still fall within 290 * the hash_mask. Case 0 does this exactly. Since there are a total 291 * of 8 bits of shifting, then mc_addr[4] will shift right the 292 * remaining number of bits. Thus 8 - bit_shift. The rest of the 293 * cases are a variation of this algorithm...essentially raising the 294 * number of bits to shift mc_addr[5] left, while still keeping the 295 * 8-bit shifting total. 296 * 297 * For example, given the following Destination MAC Address and an 298 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 299 * we can see that the bit_shift for case 0 is 4. These are the hash 300 * values resulting from each mc_filter_type... 301 * [0] [1] [2] [3] [4] [5] 302 * 01 AA 00 12 34 56 303 * LSB MSB 304 * 305 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 306 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 307 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 308 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 309 */ 310 switch (hw->mac.mc_filter_type) { 311 default: 312 case 0: 313 break; 314 case 1: 315 bit_shift += 1; 316 break; 317 case 2: 318 bit_shift += 2; 319 break; 320 case 3: 321 bit_shift += 4; 322 break; 323 } 324 325 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 326 (((u16)mc_addr[5]) << bit_shift))); 327 328 return hash_value; 329} 330 331/** 332 * e1000e_update_mc_addr_list_generic - Update Multicast addresses 333 * @hw: pointer to the HW structure 334 * @mc_addr_list: array of multicast addresses to program 335 * @mc_addr_count: number of multicast addresses to program 336 * 337 * Updates entire Multicast Table Array. 338 * The caller must have a packed mc_addr_list of multicast addresses. 339 **/ 340void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, 341 u8 *mc_addr_list, u32 mc_addr_count) 342{ 343 u32 hash_value, hash_bit, hash_reg; 344 int i; 345 346 /* clear mta_shadow */ 347 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 348 349 /* update mta_shadow from mc_addr_list */ 350 for (i = 0; (u32)i < mc_addr_count; i++) { 351 hash_value = e1000_hash_mc_addr(hw, mc_addr_list); 352 353 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 354 hash_bit = hash_value & 0x1F; 355 356 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 357 mc_addr_list += (ETH_ALEN); 358 } 359 360 /* replace the entire MTA table */ 361 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 362 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 363 e1e_flush(); 364} 365 366/** 367 * e1000e_clear_hw_cntrs_base - Clear base hardware counters 368 * @hw: pointer to the HW structure 369 * 370 * Clears the base hardware counters by reading the counter registers. 371 **/ 372void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw) 373{ 374 er32(CRCERRS); 375 er32(SYMERRS); 376 er32(MPC); 377 er32(SCC); 378 er32(ECOL); 379 er32(MCC); 380 er32(LATECOL); 381 er32(COLC); 382 er32(DC); 383 er32(SEC); 384 er32(RLEC); 385 er32(XONRXC); 386 er32(XONTXC); 387 er32(XOFFRXC); 388 er32(XOFFTXC); 389 er32(FCRUC); 390 er32(GPRC); 391 er32(BPRC); 392 er32(MPRC); 393 er32(GPTC); 394 er32(GORCL); 395 er32(GORCH); 396 er32(GOTCL); 397 er32(GOTCH); 398 er32(RNBC); 399 er32(RUC); 400 er32(RFC); 401 er32(ROC); 402 er32(RJC); 403 er32(TORL); 404 er32(TORH); 405 er32(TOTL); 406 er32(TOTH); 407 er32(TPR); 408 er32(TPT); 409 er32(MPTC); 410 er32(BPTC); 411} 412 413/** 414 * e1000e_check_for_copper_link - Check for link (Copper) 415 * @hw: pointer to the HW structure 416 * 417 * Checks to see of the link status of the hardware has changed. If a 418 * change in link status has been detected, then we read the PHY registers 419 * to get the current speed/duplex if link exists. 420 **/ 421s32 e1000e_check_for_copper_link(struct e1000_hw *hw) 422{ 423 struct e1000_mac_info *mac = &hw->mac; 424 s32 ret_val; 425 bool link; 426 427 /* 428 * We only want to go out to the PHY registers to see if Auto-Neg 429 * has completed and/or if our link status has changed. The 430 * get_link_status flag is set upon receiving a Link Status 431 * Change or Rx Sequence Error interrupt. 432 */ 433 if (!mac->get_link_status) 434 return 0; 435 436 /* 437 * First we want to see if the MII Status Register reports 438 * link. If so, then we want to get the current speed/duplex 439 * of the PHY. 440 */ 441 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 442 if (ret_val) 443 return ret_val; 444 445 if (!link) 446 return 0; /* No link detected */ 447 448 mac->get_link_status = false; 449 450 /* 451 * Check if there was DownShift, must be checked 452 * immediately after link-up 453 */ 454 e1000e_check_downshift(hw); 455 456 /* 457 * If we are forcing speed/duplex, then we simply return since 458 * we have already determined whether we have link or not. 459 */ 460 if (!mac->autoneg) 461 return -E1000_ERR_CONFIG; 462 463 /* 464 * Auto-Neg is enabled. Auto Speed Detection takes care 465 * of MAC speed/duplex configuration. So we only need to 466 * configure Collision Distance in the MAC. 467 */ 468 mac->ops.config_collision_dist(hw); 469 470 /* 471 * Configure Flow Control now that Auto-Neg has completed. 472 * First, we need to restore the desired flow control 473 * settings because we may have had to re-autoneg with a 474 * different link partner. 475 */ 476 ret_val = e1000e_config_fc_after_link_up(hw); 477 if (ret_val) 478 e_dbg("Error configuring flow control\n"); 479 480 return ret_val; 481} 482 483/** 484 * e1000e_check_for_fiber_link - Check for link (Fiber) 485 * @hw: pointer to the HW structure 486 * 487 * Checks for link up on the hardware. If link is not up and we have 488 * a signal, then we need to force link up. 489 **/ 490s32 e1000e_check_for_fiber_link(struct e1000_hw *hw) 491{ 492 struct e1000_mac_info *mac = &hw->mac; 493 u32 rxcw; 494 u32 ctrl; 495 u32 status; 496 s32 ret_val; 497 498 ctrl = er32(CTRL); 499 status = er32(STATUS); 500 rxcw = er32(RXCW); 501 502 /* 503 * If we don't have link (auto-negotiation failed or link partner 504 * cannot auto-negotiate), the cable is plugged in (we have signal), 505 * and our link partner is not trying to auto-negotiate with us (we 506 * are receiving idles or data), we need to force link up. We also 507 * need to give auto-negotiation time to complete, in case the cable 508 * was just plugged in. The autoneg_failed flag does this. 509 */ 510 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 511 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 512 !(rxcw & E1000_RXCW_C)) { 513 if (!mac->autoneg_failed) { 514 mac->autoneg_failed = true; 515 return 0; 516 } 517 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 518 519 /* Disable auto-negotiation in the TXCW register */ 520 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 521 522 /* Force link-up and also force full-duplex. */ 523 ctrl = er32(CTRL); 524 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 525 ew32(CTRL, ctrl); 526 527 /* Configure Flow Control after forcing link up. */ 528 ret_val = e1000e_config_fc_after_link_up(hw); 529 if (ret_val) { 530 e_dbg("Error configuring flow control\n"); 531 return ret_val; 532 } 533 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 534 /* 535 * If we are forcing link and we are receiving /C/ ordered 536 * sets, re-enable auto-negotiation in the TXCW register 537 * and disable forced link in the Device Control register 538 * in an attempt to auto-negotiate with our link partner. 539 */ 540 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 541 ew32(TXCW, mac->txcw); 542 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 543 544 mac->serdes_has_link = true; 545 } 546 547 return 0; 548} 549 550/** 551 * e1000e_check_for_serdes_link - Check for link (Serdes) 552 * @hw: pointer to the HW structure 553 * 554 * Checks for link up on the hardware. If link is not up and we have 555 * a signal, then we need to force link up. 556 **/ 557s32 e1000e_check_for_serdes_link(struct e1000_hw *hw) 558{ 559 struct e1000_mac_info *mac = &hw->mac; 560 u32 rxcw; 561 u32 ctrl; 562 u32 status; 563 s32 ret_val; 564 565 ctrl = er32(CTRL); 566 status = er32(STATUS); 567 rxcw = er32(RXCW); 568 569 /* 570 * If we don't have link (auto-negotiation failed or link partner 571 * cannot auto-negotiate), and our link partner is not trying to 572 * auto-negotiate with us (we are receiving idles or data), 573 * we need to force link up. We also need to give auto-negotiation 574 * time to complete. 575 */ 576 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 577 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 578 if (!mac->autoneg_failed) { 579 mac->autoneg_failed = true; 580 return 0; 581 } 582 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 583 584 /* Disable auto-negotiation in the TXCW register */ 585 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 586 587 /* Force link-up and also force full-duplex. */ 588 ctrl = er32(CTRL); 589 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 590 ew32(CTRL, ctrl); 591 592 /* Configure Flow Control after forcing link up. */ 593 ret_val = e1000e_config_fc_after_link_up(hw); 594 if (ret_val) { 595 e_dbg("Error configuring flow control\n"); 596 return ret_val; 597 } 598 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 599 /* 600 * If we are forcing link and we are receiving /C/ ordered 601 * sets, re-enable auto-negotiation in the TXCW register 602 * and disable forced link in the Device Control register 603 * in an attempt to auto-negotiate with our link partner. 604 */ 605 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 606 ew32(TXCW, mac->txcw); 607 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 608 609 mac->serdes_has_link = true; 610 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { 611 /* 612 * If we force link for non-auto-negotiation switch, check 613 * link status based on MAC synchronization for internal 614 * serdes media type. 615 */ 616 /* SYNCH bit and IV bit are sticky. */ 617 udelay(10); 618 rxcw = er32(RXCW); 619 if (rxcw & E1000_RXCW_SYNCH) { 620 if (!(rxcw & E1000_RXCW_IV)) { 621 mac->serdes_has_link = true; 622 e_dbg("SERDES: Link up - forced.\n"); 623 } 624 } else { 625 mac->serdes_has_link = false; 626 e_dbg("SERDES: Link down - force failed.\n"); 627 } 628 } 629 630 if (E1000_TXCW_ANE & er32(TXCW)) { 631 status = er32(STATUS); 632 if (status & E1000_STATUS_LU) { 633 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 634 udelay(10); 635 rxcw = er32(RXCW); 636 if (rxcw & E1000_RXCW_SYNCH) { 637 if (!(rxcw & E1000_RXCW_IV)) { 638 mac->serdes_has_link = true; 639 e_dbg("SERDES: Link up - autoneg completed successfully.\n"); 640 } else { 641 mac->serdes_has_link = false; 642 e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n"); 643 } 644 } else { 645 mac->serdes_has_link = false; 646 e_dbg("SERDES: Link down - no sync.\n"); 647 } 648 } else { 649 mac->serdes_has_link = false; 650 e_dbg("SERDES: Link down - autoneg failed\n"); 651 } 652 } 653 654 return 0; 655} 656 657/** 658 * e1000_set_default_fc_generic - Set flow control default values 659 * @hw: pointer to the HW structure 660 * 661 * Read the EEPROM for the default values for flow control and store the 662 * values. 663 **/ 664static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 665{ 666 s32 ret_val; 667 u16 nvm_data; 668 669 /* 670 * Read and store word 0x0F of the EEPROM. This word contains bits 671 * that determine the hardware's default PAUSE (flow control) mode, 672 * a bit that determines whether the HW defaults to enabling or 673 * disabling auto-negotiation, and the direction of the 674 * SW defined pins. If there is no SW over-ride of the flow 675 * control setting, then the variable hw->fc will 676 * be initialized based on a value in the EEPROM. 677 */ 678 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 679 680 if (ret_val) { 681 e_dbg("NVM Read Error\n"); 682 return ret_val; 683 } 684 685 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 686 hw->fc.requested_mode = e1000_fc_none; 687 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR) 688 hw->fc.requested_mode = e1000_fc_tx_pause; 689 else 690 hw->fc.requested_mode = e1000_fc_full; 691 692 return 0; 693} 694 695/** 696 * e1000e_setup_link_generic - Setup flow control and link settings 697 * @hw: pointer to the HW structure 698 * 699 * Determines which flow control settings to use, then configures flow 700 * control. Calls the appropriate media-specific link configuration 701 * function. Assuming the adapter has a valid link partner, a valid link 702 * should be established. Assumes the hardware has previously been reset 703 * and the transmitter and receiver are not enabled. 704 **/ 705s32 e1000e_setup_link_generic(struct e1000_hw *hw) 706{ 707 struct e1000_mac_info *mac = &hw->mac; 708 s32 ret_val; 709 710 /* 711 * In the case of the phy reset being blocked, we already have a link. 712 * We do not need to set it up again. 713 */ 714 if (hw->phy.ops.check_reset_block(hw)) 715 return 0; 716 717 /* 718 * If requested flow control is set to default, set flow control 719 * based on the EEPROM flow control settings. 720 */ 721 if (hw->fc.requested_mode == e1000_fc_default) { 722 ret_val = e1000_set_default_fc_generic(hw); 723 if (ret_val) 724 return ret_val; 725 } 726 727 /* 728 * Save off the requested flow control mode for use later. Depending 729 * on the link partner's capabilities, we may or may not use this mode. 730 */ 731 hw->fc.current_mode = hw->fc.requested_mode; 732 733 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 734 735 /* Call the necessary media_type subroutine to configure the link. */ 736 ret_val = mac->ops.setup_physical_interface(hw); 737 if (ret_val) 738 return ret_val; 739 740 /* 741 * Initialize the flow control address, type, and PAUSE timer 742 * registers to their default values. This is done even if flow 743 * control is disabled, because it does not hurt anything to 744 * initialize these registers. 745 */ 746 e_dbg("Initializing the Flow Control address, type and timer regs\n"); 747 ew32(FCT, FLOW_CONTROL_TYPE); 748 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 749 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); 750 751 ew32(FCTTV, hw->fc.pause_time); 752 753 return e1000e_set_fc_watermarks(hw); 754} 755 756/** 757 * e1000_commit_fc_settings_generic - Configure flow control 758 * @hw: pointer to the HW structure 759 * 760 * Write the flow control settings to the Transmit Config Word Register (TXCW) 761 * base on the flow control settings in e1000_mac_info. 762 **/ 763static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 764{ 765 struct e1000_mac_info *mac = &hw->mac; 766 u32 txcw; 767 768 /* 769 * Check for a software override of the flow control settings, and 770 * setup the device accordingly. If auto-negotiation is enabled, then 771 * software will have to set the "PAUSE" bits to the correct value in 772 * the Transmit Config Word Register (TXCW) and re-start auto- 773 * negotiation. However, if auto-negotiation is disabled, then 774 * software will have to manually configure the two flow control enable 775 * bits in the CTRL register. 776 * 777 * The possible values of the "fc" parameter are: 778 * 0: Flow control is completely disabled 779 * 1: Rx flow control is enabled (we can receive pause frames, 780 * but not send pause frames). 781 * 2: Tx flow control is enabled (we can send pause frames but we 782 * do not support receiving pause frames). 783 * 3: Both Rx and Tx flow control (symmetric) are enabled. 784 */ 785 switch (hw->fc.current_mode) { 786 case e1000_fc_none: 787 /* Flow control completely disabled by a software over-ride. */ 788 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 789 break; 790 case e1000_fc_rx_pause: 791 /* 792 * Rx Flow control is enabled and Tx Flow control is disabled 793 * by a software over-ride. Since there really isn't a way to 794 * advertise that we are capable of Rx Pause ONLY, we will 795 * advertise that we support both symmetric and asymmetric Rx 796 * PAUSE. Later, we will disable the adapter's ability to send 797 * PAUSE frames. 798 */ 799 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 800 break; 801 case e1000_fc_tx_pause: 802 /* 803 * Tx Flow control is enabled, and Rx Flow control is disabled, 804 * by a software over-ride. 805 */ 806 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 807 break; 808 case e1000_fc_full: 809 /* 810 * Flow control (both Rx and Tx) is enabled by a software 811 * over-ride. 812 */ 813 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 814 break; 815 default: 816 e_dbg("Flow control param set incorrectly\n"); 817 return -E1000_ERR_CONFIG; 818 break; 819 } 820 821 ew32(TXCW, txcw); 822 mac->txcw = txcw; 823 824 return 0; 825} 826 827/** 828 * e1000_poll_fiber_serdes_link_generic - Poll for link up 829 * @hw: pointer to the HW structure 830 * 831 * Polls for link up by reading the status register, if link fails to come 832 * up with auto-negotiation, then the link is forced if a signal is detected. 833 **/ 834static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 835{ 836 struct e1000_mac_info *mac = &hw->mac; 837 u32 i, status; 838 s32 ret_val; 839 840 /* 841 * If we have a signal (the cable is plugged in, or assumed true for 842 * serdes media) then poll for a "Link-Up" indication in the Device 843 * Status Register. Time-out if a link isn't seen in 500 milliseconds 844 * seconds (Auto-negotiation should complete in less than 500 845 * milliseconds even if the other end is doing it in SW). 846 */ 847 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 848 usleep_range(10000, 20000); 849 status = er32(STATUS); 850 if (status & E1000_STATUS_LU) 851 break; 852 } 853 if (i == FIBER_LINK_UP_LIMIT) { 854 e_dbg("Never got a valid link from auto-neg!!!\n"); 855 mac->autoneg_failed = true; 856 /* 857 * AutoNeg failed to achieve a link, so we'll call 858 * mac->check_for_link. This routine will force the 859 * link up if we detect a signal. This will allow us to 860 * communicate with non-autonegotiating link partners. 861 */ 862 ret_val = mac->ops.check_for_link(hw); 863 if (ret_val) { 864 e_dbg("Error while checking for link\n"); 865 return ret_val; 866 } 867 mac->autoneg_failed = false; 868 } else { 869 mac->autoneg_failed = false; 870 e_dbg("Valid Link Found\n"); 871 } 872 873 return 0; 874} 875 876/** 877 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes 878 * @hw: pointer to the HW structure 879 * 880 * Configures collision distance and flow control for fiber and serdes 881 * links. Upon successful setup, poll for link. 882 **/ 883s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw) 884{ 885 u32 ctrl; 886 s32 ret_val; 887 888 ctrl = er32(CTRL); 889 890 /* Take the link out of reset */ 891 ctrl &= ~E1000_CTRL_LRST; 892 893 hw->mac.ops.config_collision_dist(hw); 894 895 ret_val = e1000_commit_fc_settings_generic(hw); 896 if (ret_val) 897 return ret_val; 898 899 /* 900 * Since auto-negotiation is enabled, take the link out of reset (the 901 * link will be in reset, because we previously reset the chip). This 902 * will restart auto-negotiation. If auto-negotiation is successful 903 * then the link-up status bit will be set and the flow control enable 904 * bits (RFCE and TFCE) will be set according to their negotiated value. 905 */ 906 e_dbg("Auto-negotiation enabled\n"); 907 908 ew32(CTRL, ctrl); 909 e1e_flush(); 910 usleep_range(1000, 2000); 911 912 /* 913 * For these adapters, the SW definable pin 1 is set when the optics 914 * detect a signal. If we have a signal, then poll for a "Link-Up" 915 * indication. 916 */ 917 if (hw->phy.media_type == e1000_media_type_internal_serdes || 918 (er32(CTRL) & E1000_CTRL_SWDPIN1)) { 919 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 920 } else { 921 e_dbg("No signal detected\n"); 922 } 923 924 return ret_val; 925} 926 927/** 928 * e1000e_config_collision_dist_generic - Configure collision distance 929 * @hw: pointer to the HW structure 930 * 931 * Configures the collision distance to the default value and is used 932 * during link setup. 933 **/ 934void e1000e_config_collision_dist_generic(struct e1000_hw *hw) 935{ 936 u32 tctl; 937 938 tctl = er32(TCTL); 939 940 tctl &= ~E1000_TCTL_COLD; 941 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 942 943 ew32(TCTL, tctl); 944 e1e_flush(); 945} 946 947/** 948 * e1000e_set_fc_watermarks - Set flow control high/low watermarks 949 * @hw: pointer to the HW structure 950 * 951 * Sets the flow control high/low threshold (watermark) registers. If 952 * flow control XON frame transmission is enabled, then set XON frame 953 * transmission as well. 954 **/ 955s32 e1000e_set_fc_watermarks(struct e1000_hw *hw) 956{ 957 u32 fcrtl = 0, fcrth = 0; 958 959 /* 960 * Set the flow control receive threshold registers. Normally, 961 * these registers will be set to a default threshold that may be 962 * adjusted later by the driver's runtime code. However, if the 963 * ability to transmit pause frames is not enabled, then these 964 * registers will be set to 0. 965 */ 966 if (hw->fc.current_mode & e1000_fc_tx_pause) { 967 /* 968 * We need to set up the Receive Threshold high and low water 969 * marks as well as (optionally) enabling the transmission of 970 * XON frames. 971 */ 972 fcrtl = hw->fc.low_water; 973 fcrtl |= E1000_FCRTL_XONE; 974 fcrth = hw->fc.high_water; 975 } 976 ew32(FCRTL, fcrtl); 977 ew32(FCRTH, fcrth); 978 979 return 0; 980} 981 982/** 983 * e1000e_force_mac_fc - Force the MAC's flow control settings 984 * @hw: pointer to the HW structure 985 * 986 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 987 * device control register to reflect the adapter settings. TFCE and RFCE 988 * need to be explicitly set by software when a copper PHY is used because 989 * autonegotiation is managed by the PHY rather than the MAC. Software must 990 * also configure these bits when link is forced on a fiber connection. 991 **/ 992s32 e1000e_force_mac_fc(struct e1000_hw *hw) 993{ 994 u32 ctrl; 995 996 ctrl = er32(CTRL); 997 998 /* 999 * Because we didn't get link via the internal auto-negotiation 1000 * mechanism (we either forced link or we got link via PHY 1001 * auto-neg), we have to manually enable/disable transmit an 1002 * receive flow control. 1003 * 1004 * The "Case" statement below enables/disable flow control 1005 * according to the "hw->fc.current_mode" parameter. 1006 * 1007 * The possible values of the "fc" parameter are: 1008 * 0: Flow control is completely disabled 1009 * 1: Rx flow control is enabled (we can receive pause 1010 * frames but not send pause frames). 1011 * 2: Tx flow control is enabled (we can send pause frames 1012 * frames but we do not receive pause frames). 1013 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1014 * other: No other values should be possible at this point. 1015 */ 1016 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1017 1018 switch (hw->fc.current_mode) { 1019 case e1000_fc_none: 1020 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1021 break; 1022 case e1000_fc_rx_pause: 1023 ctrl &= (~E1000_CTRL_TFCE); 1024 ctrl |= E1000_CTRL_RFCE; 1025 break; 1026 case e1000_fc_tx_pause: 1027 ctrl &= (~E1000_CTRL_RFCE); 1028 ctrl |= E1000_CTRL_TFCE; 1029 break; 1030 case e1000_fc_full: 1031 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1032 break; 1033 default: 1034 e_dbg("Flow control param set incorrectly\n"); 1035 return -E1000_ERR_CONFIG; 1036 } 1037 1038 ew32(CTRL, ctrl); 1039 1040 return 0; 1041} 1042 1043/** 1044 * e1000e_config_fc_after_link_up - Configures flow control after link 1045 * @hw: pointer to the HW structure 1046 * 1047 * Checks the status of auto-negotiation after link up to ensure that the 1048 * speed and duplex were not forced. If the link needed to be forced, then 1049 * flow control needs to be forced also. If auto-negotiation is enabled 1050 * and did not fail, then we configure flow control based on our link 1051 * partner. 1052 **/ 1053s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw) 1054{ 1055 struct e1000_mac_info *mac = &hw->mac; 1056 s32 ret_val = 0; 1057 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1058 u16 speed, duplex; 1059 1060 /* 1061 * Check for the case where we have fiber media and auto-neg failed 1062 * so we had to force link. In this case, we need to force the 1063 * configuration of the MAC to match the "fc" parameter. 1064 */ 1065 if (mac->autoneg_failed) { 1066 if (hw->phy.media_type == e1000_media_type_fiber || 1067 hw->phy.media_type == e1000_media_type_internal_serdes) 1068 ret_val = e1000e_force_mac_fc(hw); 1069 } else { 1070 if (hw->phy.media_type == e1000_media_type_copper) 1071 ret_val = e1000e_force_mac_fc(hw); 1072 } 1073 1074 if (ret_val) { 1075 e_dbg("Error forcing flow control settings\n"); 1076 return ret_val; 1077 } 1078 1079 /* 1080 * Check for the case where we have copper media and auto-neg is 1081 * enabled. In this case, we need to check and see if Auto-Neg 1082 * has completed, and if so, how the PHY and link partner has 1083 * flow control configured. 1084 */ 1085 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1086 /* 1087 * Read the MII Status Register and check to see if AutoNeg 1088 * has completed. We read this twice because this reg has 1089 * some "sticky" (latched) bits. 1090 */ 1091 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); 1092 if (ret_val) 1093 return ret_val; 1094 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); 1095 if (ret_val) 1096 return ret_val; 1097 1098 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1099 e_dbg("Copper PHY and Auto Neg has not completed.\n"); 1100 return ret_val; 1101 } 1102 1103 /* 1104 * The AutoNeg process has completed, so we now need to 1105 * read both the Auto Negotiation Advertisement 1106 * Register (Address 4) and the Auto_Negotiation Base 1107 * Page Ability Register (Address 5) to determine how 1108 * flow control was negotiated. 1109 */ 1110 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg); 1111 if (ret_val) 1112 return ret_val; 1113 ret_val = 1114 e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg); 1115 if (ret_val) 1116 return ret_val; 1117 1118 /* 1119 * Two bits in the Auto Negotiation Advertisement Register 1120 * (Address 4) and two bits in the Auto Negotiation Base 1121 * Page Ability Register (Address 5) determine flow control 1122 * for both the PHY and the link partner. The following 1123 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1124 * 1999, describes these PAUSE resolution bits and how flow 1125 * control is determined based upon these settings. 1126 * NOTE: DC = Don't Care 1127 * 1128 * LOCAL DEVICE | LINK PARTNER 1129 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1130 *-------|---------|-------|---------|-------------------- 1131 * 0 | 0 | DC | DC | e1000_fc_none 1132 * 0 | 1 | 0 | DC | e1000_fc_none 1133 * 0 | 1 | 1 | 0 | e1000_fc_none 1134 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1135 * 1 | 0 | 0 | DC | e1000_fc_none 1136 * 1 | DC | 1 | DC | e1000_fc_full 1137 * 1 | 1 | 0 | 0 | e1000_fc_none 1138 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1139 * 1140 * Are both PAUSE bits set to 1? If so, this implies 1141 * Symmetric Flow Control is enabled at both ends. The 1142 * ASM_DIR bits are irrelevant per the spec. 1143 * 1144 * For Symmetric Flow Control: 1145 * 1146 * LOCAL DEVICE | LINK PARTNER 1147 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1148 *-------|---------|-------|---------|-------------------- 1149 * 1 | DC | 1 | DC | E1000_fc_full 1150 * 1151 */ 1152 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1153 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1154 /* 1155 * Now we need to check if the user selected Rx ONLY 1156 * of pause frames. In this case, we had to advertise 1157 * FULL flow control because we could not advertise Rx 1158 * ONLY. Hence, we must now check to see if we need to 1159 * turn OFF the TRANSMISSION of PAUSE frames. 1160 */ 1161 if (hw->fc.requested_mode == e1000_fc_full) { 1162 hw->fc.current_mode = e1000_fc_full; 1163 e_dbg("Flow Control = FULL.\n"); 1164 } else { 1165 hw->fc.current_mode = e1000_fc_rx_pause; 1166 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1167 } 1168 } 1169 /* 1170 * For receiving PAUSE frames ONLY. 1171 * 1172 * LOCAL DEVICE | LINK PARTNER 1173 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1174 *-------|---------|-------|---------|-------------------- 1175 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1176 */ 1177 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1178 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1179 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1180 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1181 hw->fc.current_mode = e1000_fc_tx_pause; 1182 e_dbg("Flow Control = Tx PAUSE frames only.\n"); 1183 } 1184 /* 1185 * For transmitting PAUSE frames ONLY. 1186 * 1187 * LOCAL DEVICE | LINK PARTNER 1188 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1189 *-------|---------|-------|---------|-------------------- 1190 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1191 */ 1192 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1193 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1194 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1195 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1196 hw->fc.current_mode = e1000_fc_rx_pause; 1197 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1198 } else { 1199 /* 1200 * Per the IEEE spec, at this point flow control 1201 * should be disabled. 1202 */ 1203 hw->fc.current_mode = e1000_fc_none; 1204 e_dbg("Flow Control = NONE.\n"); 1205 } 1206 1207 /* 1208 * Now we need to do one last check... If we auto- 1209 * negotiated to HALF DUPLEX, flow control should not be 1210 * enabled per IEEE 802.3 spec. 1211 */ 1212 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1213 if (ret_val) { 1214 e_dbg("Error getting link speed and duplex\n"); 1215 return ret_val; 1216 } 1217 1218 if (duplex == HALF_DUPLEX) 1219 hw->fc.current_mode = e1000_fc_none; 1220 1221 /* 1222 * Now we call a subroutine to actually force the MAC 1223 * controller to use the correct flow control settings. 1224 */ 1225 ret_val = e1000e_force_mac_fc(hw); 1226 if (ret_val) { 1227 e_dbg("Error forcing flow control settings\n"); 1228 return ret_val; 1229 } 1230 } 1231 1232 return 0; 1233} 1234 1235/** 1236 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex 1237 * @hw: pointer to the HW structure 1238 * @speed: stores the current speed 1239 * @duplex: stores the current duplex 1240 * 1241 * Read the status register for the current speed/duplex and store the current 1242 * speed and duplex for copper connections. 1243 **/ 1244s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, 1245 u16 *duplex) 1246{ 1247 u32 status; 1248 1249 status = er32(STATUS); 1250 if (status & E1000_STATUS_SPEED_1000) 1251 *speed = SPEED_1000; 1252 else if (status & E1000_STATUS_SPEED_100) 1253 *speed = SPEED_100; 1254 else 1255 *speed = SPEED_10; 1256 1257 if (status & E1000_STATUS_FD) 1258 *duplex = FULL_DUPLEX; 1259 else 1260 *duplex = HALF_DUPLEX; 1261 1262 e_dbg("%u Mbps, %s Duplex\n", 1263 *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10, 1264 *duplex == FULL_DUPLEX ? "Full" : "Half"); 1265 1266 return 0; 1267} 1268 1269/** 1270 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex 1271 * @hw: pointer to the HW structure 1272 * @speed: stores the current speed 1273 * @duplex: stores the current duplex 1274 * 1275 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1276 * for fiber/serdes links. 1277 **/ 1278s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, 1279 u16 *duplex) 1280{ 1281 *speed = SPEED_1000; 1282 *duplex = FULL_DUPLEX; 1283 1284 return 0; 1285} 1286 1287/** 1288 * e1000e_get_hw_semaphore - Acquire hardware semaphore 1289 * @hw: pointer to the HW structure 1290 * 1291 * Acquire the HW semaphore to access the PHY or NVM 1292 **/ 1293s32 e1000e_get_hw_semaphore(struct e1000_hw *hw) 1294{ 1295 u32 swsm; 1296 s32 timeout = hw->nvm.word_size + 1; 1297 s32 i = 0; 1298 1299 /* Get the SW semaphore */ 1300 while (i < timeout) { 1301 swsm = er32(SWSM); 1302 if (!(swsm & E1000_SWSM_SMBI)) 1303 break; 1304 1305 udelay(50); 1306 i++; 1307 } 1308 1309 if (i == timeout) { 1310 e_dbg("Driver can't access device - SMBI bit is set.\n"); 1311 return -E1000_ERR_NVM; 1312 } 1313 1314 /* Get the FW semaphore. */ 1315 for (i = 0; i < timeout; i++) { 1316 swsm = er32(SWSM); 1317 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); 1318 1319 /* Semaphore acquired if bit latched */ 1320 if (er32(SWSM) & E1000_SWSM_SWESMBI) 1321 break; 1322 1323 udelay(50); 1324 } 1325 1326 if (i == timeout) { 1327 /* Release semaphores */ 1328 e1000e_put_hw_semaphore(hw); 1329 e_dbg("Driver can't access the NVM\n"); 1330 return -E1000_ERR_NVM; 1331 } 1332 1333 return 0; 1334} 1335 1336/** 1337 * e1000e_put_hw_semaphore - Release hardware semaphore 1338 * @hw: pointer to the HW structure 1339 * 1340 * Release hardware semaphore used to access the PHY or NVM 1341 **/ 1342void e1000e_put_hw_semaphore(struct e1000_hw *hw) 1343{ 1344 u32 swsm; 1345 1346 swsm = er32(SWSM); 1347 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1348 ew32(SWSM, swsm); 1349} 1350 1351/** 1352 * e1000e_get_auto_rd_done - Check for auto read completion 1353 * @hw: pointer to the HW structure 1354 * 1355 * Check EEPROM for Auto Read done bit. 1356 **/ 1357s32 e1000e_get_auto_rd_done(struct e1000_hw *hw) 1358{ 1359 s32 i = 0; 1360 1361 while (i < AUTO_READ_DONE_TIMEOUT) { 1362 if (er32(EECD) & E1000_EECD_AUTO_RD) 1363 break; 1364 usleep_range(1000, 2000); 1365 i++; 1366 } 1367 1368 if (i == AUTO_READ_DONE_TIMEOUT) { 1369 e_dbg("Auto read by HW from NVM has not completed.\n"); 1370 return -E1000_ERR_RESET; 1371 } 1372 1373 return 0; 1374} 1375 1376/** 1377 * e1000e_valid_led_default - Verify a valid default LED config 1378 * @hw: pointer to the HW structure 1379 * @data: pointer to the NVM (EEPROM) 1380 * 1381 * Read the EEPROM for the current default LED configuration. If the 1382 * LED configuration is not valid, set to a valid LED configuration. 1383 **/ 1384s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data) 1385{ 1386 s32 ret_val; 1387 1388 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1389 if (ret_val) { 1390 e_dbg("NVM Read Error\n"); 1391 return ret_val; 1392 } 1393 1394 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1395 *data = ID_LED_DEFAULT; 1396 1397 return 0; 1398} 1399 1400/** 1401 * e1000e_id_led_init_generic - 1402 * @hw: pointer to the HW structure 1403 * 1404 **/ 1405s32 e1000e_id_led_init_generic(struct e1000_hw *hw) 1406{ 1407 struct e1000_mac_info *mac = &hw->mac; 1408 s32 ret_val; 1409 const u32 ledctl_mask = 0x000000FF; 1410 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1411 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1412 u16 data, i, temp; 1413 const u16 led_mask = 0x0F; 1414 1415 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1416 if (ret_val) 1417 return ret_val; 1418 1419 mac->ledctl_default = er32(LEDCTL); 1420 mac->ledctl_mode1 = mac->ledctl_default; 1421 mac->ledctl_mode2 = mac->ledctl_default; 1422 1423 for (i = 0; i < 4; i++) { 1424 temp = (data >> (i << 2)) & led_mask; 1425 switch (temp) { 1426 case ID_LED_ON1_DEF2: 1427 case ID_LED_ON1_ON2: 1428 case ID_LED_ON1_OFF2: 1429 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1430 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1431 break; 1432 case ID_LED_OFF1_DEF2: 1433 case ID_LED_OFF1_ON2: 1434 case ID_LED_OFF1_OFF2: 1435 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1436 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1437 break; 1438 default: 1439 /* Do nothing */ 1440 break; 1441 } 1442 switch (temp) { 1443 case ID_LED_DEF1_ON2: 1444 case ID_LED_ON1_ON2: 1445 case ID_LED_OFF1_ON2: 1446 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1447 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1448 break; 1449 case ID_LED_DEF1_OFF2: 1450 case ID_LED_ON1_OFF2: 1451 case ID_LED_OFF1_OFF2: 1452 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1453 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1454 break; 1455 default: 1456 /* Do nothing */ 1457 break; 1458 } 1459 } 1460 1461 return 0; 1462} 1463 1464/** 1465 * e1000e_setup_led_generic - Configures SW controllable LED 1466 * @hw: pointer to the HW structure 1467 * 1468 * This prepares the SW controllable LED for use and saves the current state 1469 * of the LED so it can be later restored. 1470 **/ 1471s32 e1000e_setup_led_generic(struct e1000_hw *hw) 1472{ 1473 u32 ledctl; 1474 1475 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) 1476 return -E1000_ERR_CONFIG; 1477 1478 if (hw->phy.media_type == e1000_media_type_fiber) { 1479 ledctl = er32(LEDCTL); 1480 hw->mac.ledctl_default = ledctl; 1481 /* Turn off LED0 */ 1482 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1483 E1000_LEDCTL_LED0_MODE_MASK); 1484 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1485 E1000_LEDCTL_LED0_MODE_SHIFT); 1486 ew32(LEDCTL, ledctl); 1487 } else if (hw->phy.media_type == e1000_media_type_copper) { 1488 ew32(LEDCTL, hw->mac.ledctl_mode1); 1489 } 1490 1491 return 0; 1492} 1493 1494/** 1495 * e1000e_cleanup_led_generic - Set LED config to default operation 1496 * @hw: pointer to the HW structure 1497 * 1498 * Remove the current LED configuration and set the LED configuration 1499 * to the default value, saved from the EEPROM. 1500 **/ 1501s32 e1000e_cleanup_led_generic(struct e1000_hw *hw) 1502{ 1503 ew32(LEDCTL, hw->mac.ledctl_default); 1504 return 0; 1505} 1506 1507/** 1508 * e1000e_blink_led_generic - Blink LED 1509 * @hw: pointer to the HW structure 1510 * 1511 * Blink the LEDs which are set to be on. 1512 **/ 1513s32 e1000e_blink_led_generic(struct e1000_hw *hw) 1514{ 1515 u32 ledctl_blink = 0; 1516 u32 i; 1517 1518 if (hw->phy.media_type == e1000_media_type_fiber) { 1519 /* always blink LED0 for PCI-E fiber */ 1520 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1521 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1522 } else { 1523 /* 1524 * set the blink bit for each LED that's "on" (0x0E) 1525 * in ledctl_mode2 1526 */ 1527 ledctl_blink = hw->mac.ledctl_mode2; 1528 for (i = 0; i < 4; i++) 1529 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1530 E1000_LEDCTL_MODE_LED_ON) 1531 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1532 (i * 8)); 1533 } 1534 1535 ew32(LEDCTL, ledctl_blink); 1536 1537 return 0; 1538} 1539 1540/** 1541 * e1000e_led_on_generic - Turn LED on 1542 * @hw: pointer to the HW structure 1543 * 1544 * Turn LED on. 1545 **/ 1546s32 e1000e_led_on_generic(struct e1000_hw *hw) 1547{ 1548 u32 ctrl; 1549 1550 switch (hw->phy.media_type) { 1551 case e1000_media_type_fiber: 1552 ctrl = er32(CTRL); 1553 ctrl &= ~E1000_CTRL_SWDPIN0; 1554 ctrl |= E1000_CTRL_SWDPIO0; 1555 ew32(CTRL, ctrl); 1556 break; 1557 case e1000_media_type_copper: 1558 ew32(LEDCTL, hw->mac.ledctl_mode2); 1559 break; 1560 default: 1561 break; 1562 } 1563 1564 return 0; 1565} 1566 1567/** 1568 * e1000e_led_off_generic - Turn LED off 1569 * @hw: pointer to the HW structure 1570 * 1571 * Turn LED off. 1572 **/ 1573s32 e1000e_led_off_generic(struct e1000_hw *hw) 1574{ 1575 u32 ctrl; 1576 1577 switch (hw->phy.media_type) { 1578 case e1000_media_type_fiber: 1579 ctrl = er32(CTRL); 1580 ctrl |= E1000_CTRL_SWDPIN0; 1581 ctrl |= E1000_CTRL_SWDPIO0; 1582 ew32(CTRL, ctrl); 1583 break; 1584 case e1000_media_type_copper: 1585 ew32(LEDCTL, hw->mac.ledctl_mode1); 1586 break; 1587 default: 1588 break; 1589 } 1590 1591 return 0; 1592} 1593 1594/** 1595 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities 1596 * @hw: pointer to the HW structure 1597 * @no_snoop: bitmap of snoop events 1598 * 1599 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1600 **/ 1601void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) 1602{ 1603 u32 gcr; 1604 1605 if (no_snoop) { 1606 gcr = er32(GCR); 1607 gcr &= ~(PCIE_NO_SNOOP_ALL); 1608 gcr |= no_snoop; 1609 ew32(GCR, gcr); 1610 } 1611} 1612 1613/** 1614 * e1000e_disable_pcie_master - Disables PCI-express master access 1615 * @hw: pointer to the HW structure 1616 * 1617 * Returns 0 if successful, else returns -10 1618 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1619 * the master requests to be disabled. 1620 * 1621 * Disables PCI-Express master access and verifies there are no pending 1622 * requests. 1623 **/ 1624s32 e1000e_disable_pcie_master(struct e1000_hw *hw) 1625{ 1626 u32 ctrl; 1627 s32 timeout = MASTER_DISABLE_TIMEOUT; 1628 1629 ctrl = er32(CTRL); 1630 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1631 ew32(CTRL, ctrl); 1632 1633 while (timeout) { 1634 if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) 1635 break; 1636 udelay(100); 1637 timeout--; 1638 } 1639 1640 if (!timeout) { 1641 e_dbg("Master requests are pending.\n"); 1642 return -E1000_ERR_MASTER_REQUESTS_PENDING; 1643 } 1644 1645 return 0; 1646} 1647 1648/** 1649 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing 1650 * @hw: pointer to the HW structure 1651 * 1652 * Reset the Adaptive Interframe Spacing throttle to default values. 1653 **/ 1654void e1000e_reset_adaptive(struct e1000_hw *hw) 1655{ 1656 struct e1000_mac_info *mac = &hw->mac; 1657 1658 if (!mac->adaptive_ifs) { 1659 e_dbg("Not in Adaptive IFS mode!\n"); 1660 return; 1661 } 1662 1663 mac->current_ifs_val = 0; 1664 mac->ifs_min_val = IFS_MIN; 1665 mac->ifs_max_val = IFS_MAX; 1666 mac->ifs_step_size = IFS_STEP; 1667 mac->ifs_ratio = IFS_RATIO; 1668 1669 mac->in_ifs_mode = false; 1670 ew32(AIT, 0); 1671} 1672 1673/** 1674 * e1000e_update_adaptive - Update Adaptive Interframe Spacing 1675 * @hw: pointer to the HW structure 1676 * 1677 * Update the Adaptive Interframe Spacing Throttle value based on the 1678 * time between transmitted packets and time between collisions. 1679 **/ 1680void e1000e_update_adaptive(struct e1000_hw *hw) 1681{ 1682 struct e1000_mac_info *mac = &hw->mac; 1683 1684 if (!mac->adaptive_ifs) { 1685 e_dbg("Not in Adaptive IFS mode!\n"); 1686 return; 1687 } 1688 1689 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 1690 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 1691 mac->in_ifs_mode = true; 1692 if (mac->current_ifs_val < mac->ifs_max_val) { 1693 if (!mac->current_ifs_val) 1694 mac->current_ifs_val = mac->ifs_min_val; 1695 else 1696 mac->current_ifs_val += 1697 mac->ifs_step_size; 1698 ew32(AIT, mac->current_ifs_val); 1699 } 1700 } 1701 } else { 1702 if (mac->in_ifs_mode && 1703 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 1704 mac->current_ifs_val = 0; 1705 mac->in_ifs_mode = false; 1706 ew32(AIT, 0); 1707 } 1708 } 1709} 1710