mac.c revision 7eb61d81946ccb61726600c6e8ceefcce9844f02
1/******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27*******************************************************************************/ 28 29#include "e1000.h" 30 31/** 32 * e1000e_get_bus_info_pcie - Get PCIe bus information 33 * @hw: pointer to the HW structure 34 * 35 * Determines and stores the system bus information for a particular 36 * network interface. The following bus information is determined and stored: 37 * bus speed, bus width, type (PCIe), and PCIe function. 38 **/ 39s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw) 40{ 41 struct e1000_mac_info *mac = &hw->mac; 42 struct e1000_bus_info *bus = &hw->bus; 43 struct e1000_adapter *adapter = hw->adapter; 44 u16 pcie_link_status, cap_offset; 45 46 cap_offset = adapter->pdev->pcie_cap; 47 if (!cap_offset) { 48 bus->width = e1000_bus_width_unknown; 49 } else { 50 pci_read_config_word(adapter->pdev, 51 cap_offset + PCIE_LINK_STATUS, 52 &pcie_link_status); 53 bus->width = (enum e1000_bus_width)((pcie_link_status & 54 PCIE_LINK_WIDTH_MASK) >> 55 PCIE_LINK_WIDTH_SHIFT); 56 } 57 58 mac->ops.set_lan_id(hw); 59 60 return 0; 61} 62 63/** 64 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 65 * 66 * @hw: pointer to the HW structure 67 * 68 * Determines the LAN function id by reading memory-mapped registers 69 * and swaps the port value if requested. 70 **/ 71void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 72{ 73 struct e1000_bus_info *bus = &hw->bus; 74 u32 reg; 75 76 /* 77 * The status register reports the correct function number 78 * for the device regardless of function swap state. 79 */ 80 reg = er32(STATUS); 81 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 82} 83 84/** 85 * e1000_set_lan_id_single_port - Set LAN id for a single port device 86 * @hw: pointer to the HW structure 87 * 88 * Sets the LAN function id to zero for a single port device. 89 **/ 90void e1000_set_lan_id_single_port(struct e1000_hw *hw) 91{ 92 struct e1000_bus_info *bus = &hw->bus; 93 94 bus->func = 0; 95} 96 97/** 98 * e1000_clear_vfta_generic - Clear VLAN filter table 99 * @hw: pointer to the HW structure 100 * 101 * Clears the register array which contains the VLAN filter table by 102 * setting all the values to 0. 103 **/ 104void e1000_clear_vfta_generic(struct e1000_hw *hw) 105{ 106 u32 offset; 107 108 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 109 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 110 e1e_flush(); 111 } 112} 113 114/** 115 * e1000_write_vfta_generic - Write value to VLAN filter table 116 * @hw: pointer to the HW structure 117 * @offset: register offset in VLAN filter table 118 * @value: register value written to VLAN filter table 119 * 120 * Writes value at the given offset in the register array which stores 121 * the VLAN filter table. 122 **/ 123void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 124{ 125 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 126 e1e_flush(); 127} 128 129/** 130 * e1000e_init_rx_addrs - Initialize receive address's 131 * @hw: pointer to the HW structure 132 * @rar_count: receive address registers 133 * 134 * Setup the receive address registers by setting the base receive address 135 * register to the devices MAC address and clearing all the other receive 136 * address registers to 0. 137 **/ 138void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) 139{ 140 u32 i; 141 u8 mac_addr[ETH_ALEN] = { 0 }; 142 143 /* Setup the receive address */ 144 e_dbg("Programming MAC Address into RAR[0]\n"); 145 146 e1000e_rar_set(hw, hw->mac.addr, 0); 147 148 /* Zero out the other (rar_entry_count - 1) receive addresses */ 149 e_dbg("Clearing RAR[1-%u]\n", rar_count - 1); 150 for (i = 1; i < rar_count; i++) 151 e1000e_rar_set(hw, mac_addr, i); 152} 153 154/** 155 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 156 * @hw: pointer to the HW structure 157 * 158 * Checks the nvm for an alternate MAC address. An alternate MAC address 159 * can be setup by pre-boot software and must be treated like a permanent 160 * address and must override the actual permanent MAC address. If an 161 * alternate MAC address is found it is programmed into RAR0, replacing 162 * the permanent address that was installed into RAR0 by the Si on reset. 163 * This function will return SUCCESS unless it encounters an error while 164 * reading the EEPROM. 165 **/ 166s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 167{ 168 u32 i; 169 s32 ret_val = 0; 170 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 171 u8 alt_mac_addr[ETH_ALEN]; 172 173 ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data); 174 if (ret_val) 175 goto out; 176 177 /* not supported on 82573 */ 178 if (hw->mac.type == e1000_82573) 179 goto out; 180 181 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, 182 &nvm_alt_mac_addr_offset); 183 if (ret_val) { 184 e_dbg("NVM Read Error\n"); 185 goto out; 186 } 187 188 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 189 (nvm_alt_mac_addr_offset == 0x0000)) 190 /* There is no Alternate MAC Address */ 191 goto out; 192 193 if (hw->bus.func == E1000_FUNC_1) 194 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 195 for (i = 0; i < ETH_ALEN; i += 2) { 196 offset = nvm_alt_mac_addr_offset + (i >> 1); 197 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); 198 if (ret_val) { 199 e_dbg("NVM Read Error\n"); 200 goto out; 201 } 202 203 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 204 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 205 } 206 207 /* if multicast bit is set, the alternate address will not be used */ 208 if (is_multicast_ether_addr(alt_mac_addr)) { 209 e_dbg("Ignoring Alternate Mac Address with MC bit set\n"); 210 goto out; 211 } 212 213 /* 214 * We have a valid alternate MAC address, and we want to treat it the 215 * same as the normal permanent MAC address stored by the HW into the 216 * RAR. Do this by mapping this address into RAR0. 217 */ 218 e1000e_rar_set(hw, alt_mac_addr, 0); 219 220out: 221 return ret_val; 222} 223 224/** 225 * e1000e_rar_set - Set receive address register 226 * @hw: pointer to the HW structure 227 * @addr: pointer to the receive address 228 * @index: receive address array register 229 * 230 * Sets the receive address array register at index to the address passed 231 * in by addr. 232 **/ 233void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) 234{ 235 u32 rar_low, rar_high; 236 237 /* 238 * HW expects these in little endian so we reverse the byte order 239 * from network order (big endian) to little endian 240 */ 241 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 242 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 243 244 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 245 246 /* If MAC address zero, no need to set the AV bit */ 247 if (rar_low || rar_high) 248 rar_high |= E1000_RAH_AV; 249 250 /* 251 * Some bridges will combine consecutive 32-bit writes into 252 * a single burst write, which will malfunction on some parts. 253 * The flushes avoid this. 254 */ 255 ew32(RAL(index), rar_low); 256 e1e_flush(); 257 ew32(RAH(index), rar_high); 258 e1e_flush(); 259} 260 261/** 262 * e1000_hash_mc_addr - Generate a multicast hash value 263 * @hw: pointer to the HW structure 264 * @mc_addr: pointer to a multicast address 265 * 266 * Generates a multicast address hash value which is used to determine 267 * the multicast filter table array address and new table value. See 268 * e1000_mta_set_generic() 269 **/ 270static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 271{ 272 u32 hash_value, hash_mask; 273 u8 bit_shift = 0; 274 275 /* Register count multiplied by bits per register */ 276 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 277 278 /* 279 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 280 * where 0xFF would still fall within the hash mask. 281 */ 282 while (hash_mask >> bit_shift != 0xFF) 283 bit_shift++; 284 285 /* 286 * The portion of the address that is used for the hash table 287 * is determined by the mc_filter_type setting. 288 * The algorithm is such that there is a total of 8 bits of shifting. 289 * The bit_shift for a mc_filter_type of 0 represents the number of 290 * left-shifts where the MSB of mc_addr[5] would still fall within 291 * the hash_mask. Case 0 does this exactly. Since there are a total 292 * of 8 bits of shifting, then mc_addr[4] will shift right the 293 * remaining number of bits. Thus 8 - bit_shift. The rest of the 294 * cases are a variation of this algorithm...essentially raising the 295 * number of bits to shift mc_addr[5] left, while still keeping the 296 * 8-bit shifting total. 297 * 298 * For example, given the following Destination MAC Address and an 299 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 300 * we can see that the bit_shift for case 0 is 4. These are the hash 301 * values resulting from each mc_filter_type... 302 * [0] [1] [2] [3] [4] [5] 303 * 01 AA 00 12 34 56 304 * LSB MSB 305 * 306 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 307 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 308 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 309 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 310 */ 311 switch (hw->mac.mc_filter_type) { 312 default: 313 case 0: 314 break; 315 case 1: 316 bit_shift += 1; 317 break; 318 case 2: 319 bit_shift += 2; 320 break; 321 case 3: 322 bit_shift += 4; 323 break; 324 } 325 326 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 327 (((u16)mc_addr[5]) << bit_shift))); 328 329 return hash_value; 330} 331 332/** 333 * e1000e_update_mc_addr_list_generic - Update Multicast addresses 334 * @hw: pointer to the HW structure 335 * @mc_addr_list: array of multicast addresses to program 336 * @mc_addr_count: number of multicast addresses to program 337 * 338 * Updates entire Multicast Table Array. 339 * The caller must have a packed mc_addr_list of multicast addresses. 340 **/ 341void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, 342 u8 *mc_addr_list, u32 mc_addr_count) 343{ 344 u32 hash_value, hash_bit, hash_reg; 345 int i; 346 347 /* clear mta_shadow */ 348 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 349 350 /* update mta_shadow from mc_addr_list */ 351 for (i = 0; (u32)i < mc_addr_count; i++) { 352 hash_value = e1000_hash_mc_addr(hw, mc_addr_list); 353 354 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 355 hash_bit = hash_value & 0x1F; 356 357 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 358 mc_addr_list += (ETH_ALEN); 359 } 360 361 /* replace the entire MTA table */ 362 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 363 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 364 e1e_flush(); 365} 366 367/** 368 * e1000e_clear_hw_cntrs_base - Clear base hardware counters 369 * @hw: pointer to the HW structure 370 * 371 * Clears the base hardware counters by reading the counter registers. 372 **/ 373void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw) 374{ 375 er32(CRCERRS); 376 er32(SYMERRS); 377 er32(MPC); 378 er32(SCC); 379 er32(ECOL); 380 er32(MCC); 381 er32(LATECOL); 382 er32(COLC); 383 er32(DC); 384 er32(SEC); 385 er32(RLEC); 386 er32(XONRXC); 387 er32(XONTXC); 388 er32(XOFFRXC); 389 er32(XOFFTXC); 390 er32(FCRUC); 391 er32(GPRC); 392 er32(BPRC); 393 er32(MPRC); 394 er32(GPTC); 395 er32(GORCL); 396 er32(GORCH); 397 er32(GOTCL); 398 er32(GOTCH); 399 er32(RNBC); 400 er32(RUC); 401 er32(RFC); 402 er32(ROC); 403 er32(RJC); 404 er32(TORL); 405 er32(TORH); 406 er32(TOTL); 407 er32(TOTH); 408 er32(TPR); 409 er32(TPT); 410 er32(MPTC); 411 er32(BPTC); 412} 413 414/** 415 * e1000e_check_for_copper_link - Check for link (Copper) 416 * @hw: pointer to the HW structure 417 * 418 * Checks to see of the link status of the hardware has changed. If a 419 * change in link status has been detected, then we read the PHY registers 420 * to get the current speed/duplex if link exists. 421 **/ 422s32 e1000e_check_for_copper_link(struct e1000_hw *hw) 423{ 424 struct e1000_mac_info *mac = &hw->mac; 425 s32 ret_val; 426 bool link; 427 428 /* 429 * We only want to go out to the PHY registers to see if Auto-Neg 430 * has completed and/or if our link status has changed. The 431 * get_link_status flag is set upon receiving a Link Status 432 * Change or Rx Sequence Error interrupt. 433 */ 434 if (!mac->get_link_status) 435 return 0; 436 437 /* 438 * First we want to see if the MII Status Register reports 439 * link. If so, then we want to get the current speed/duplex 440 * of the PHY. 441 */ 442 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 443 if (ret_val) 444 return ret_val; 445 446 if (!link) 447 return ret_val; /* No link detected */ 448 449 mac->get_link_status = false; 450 451 /* 452 * Check if there was DownShift, must be checked 453 * immediately after link-up 454 */ 455 e1000e_check_downshift(hw); 456 457 /* 458 * If we are forcing speed/duplex, then we simply return since 459 * we have already determined whether we have link or not. 460 */ 461 if (!mac->autoneg) 462 return -E1000_ERR_CONFIG; 463 464 /* 465 * Auto-Neg is enabled. Auto Speed Detection takes care 466 * of MAC speed/duplex configuration. So we only need to 467 * configure Collision Distance in the MAC. 468 */ 469 e1000e_config_collision_dist(hw); 470 471 /* 472 * Configure Flow Control now that Auto-Neg has completed. 473 * First, we need to restore the desired flow control 474 * settings because we may have had to re-autoneg with a 475 * different link partner. 476 */ 477 ret_val = e1000e_config_fc_after_link_up(hw); 478 if (ret_val) 479 e_dbg("Error configuring flow control\n"); 480 481 return ret_val; 482} 483 484/** 485 * e1000e_check_for_fiber_link - Check for link (Fiber) 486 * @hw: pointer to the HW structure 487 * 488 * Checks for link up on the hardware. If link is not up and we have 489 * a signal, then we need to force link up. 490 **/ 491s32 e1000e_check_for_fiber_link(struct e1000_hw *hw) 492{ 493 struct e1000_mac_info *mac = &hw->mac; 494 u32 rxcw; 495 u32 ctrl; 496 u32 status; 497 s32 ret_val; 498 499 ctrl = er32(CTRL); 500 status = er32(STATUS); 501 rxcw = er32(RXCW); 502 503 /* 504 * If we don't have link (auto-negotiation failed or link partner 505 * cannot auto-negotiate), the cable is plugged in (we have signal), 506 * and our link partner is not trying to auto-negotiate with us (we 507 * are receiving idles or data), we need to force link up. We also 508 * need to give auto-negotiation time to complete, in case the cable 509 * was just plugged in. The autoneg_failed flag does this. 510 */ 511 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 512 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 513 !(rxcw & E1000_RXCW_C)) { 514 if (!mac->autoneg_failed) { 515 mac->autoneg_failed = true; 516 return 0; 517 } 518 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 519 520 /* Disable auto-negotiation in the TXCW register */ 521 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 522 523 /* Force link-up and also force full-duplex. */ 524 ctrl = er32(CTRL); 525 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 526 ew32(CTRL, ctrl); 527 528 /* Configure Flow Control after forcing link up. */ 529 ret_val = e1000e_config_fc_after_link_up(hw); 530 if (ret_val) { 531 e_dbg("Error configuring flow control\n"); 532 return ret_val; 533 } 534 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 535 /* 536 * If we are forcing link and we are receiving /C/ ordered 537 * sets, re-enable auto-negotiation in the TXCW register 538 * and disable forced link in the Device Control register 539 * in an attempt to auto-negotiate with our link partner. 540 */ 541 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 542 ew32(TXCW, mac->txcw); 543 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 544 545 mac->serdes_has_link = true; 546 } 547 548 return 0; 549} 550 551/** 552 * e1000e_check_for_serdes_link - Check for link (Serdes) 553 * @hw: pointer to the HW structure 554 * 555 * Checks for link up on the hardware. If link is not up and we have 556 * a signal, then we need to force link up. 557 **/ 558s32 e1000e_check_for_serdes_link(struct e1000_hw *hw) 559{ 560 struct e1000_mac_info *mac = &hw->mac; 561 u32 rxcw; 562 u32 ctrl; 563 u32 status; 564 s32 ret_val; 565 566 ctrl = er32(CTRL); 567 status = er32(STATUS); 568 rxcw = er32(RXCW); 569 570 /* 571 * If we don't have link (auto-negotiation failed or link partner 572 * cannot auto-negotiate), and our link partner is not trying to 573 * auto-negotiate with us (we are receiving idles or data), 574 * we need to force link up. We also need to give auto-negotiation 575 * time to complete. 576 */ 577 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 578 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 579 if (!mac->autoneg_failed) { 580 mac->autoneg_failed = true; 581 return 0; 582 } 583 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 584 585 /* Disable auto-negotiation in the TXCW register */ 586 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 587 588 /* Force link-up and also force full-duplex. */ 589 ctrl = er32(CTRL); 590 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 591 ew32(CTRL, ctrl); 592 593 /* Configure Flow Control after forcing link up. */ 594 ret_val = e1000e_config_fc_after_link_up(hw); 595 if (ret_val) { 596 e_dbg("Error configuring flow control\n"); 597 return ret_val; 598 } 599 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 600 /* 601 * If we are forcing link and we are receiving /C/ ordered 602 * sets, re-enable auto-negotiation in the TXCW register 603 * and disable forced link in the Device Control register 604 * in an attempt to auto-negotiate with our link partner. 605 */ 606 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 607 ew32(TXCW, mac->txcw); 608 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 609 610 mac->serdes_has_link = true; 611 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { 612 /* 613 * If we force link for non-auto-negotiation switch, check 614 * link status based on MAC synchronization for internal 615 * serdes media type. 616 */ 617 /* SYNCH bit and IV bit are sticky. */ 618 udelay(10); 619 rxcw = er32(RXCW); 620 if (rxcw & E1000_RXCW_SYNCH) { 621 if (!(rxcw & E1000_RXCW_IV)) { 622 mac->serdes_has_link = true; 623 e_dbg("SERDES: Link up - forced.\n"); 624 } 625 } else { 626 mac->serdes_has_link = false; 627 e_dbg("SERDES: Link down - force failed.\n"); 628 } 629 } 630 631 if (E1000_TXCW_ANE & er32(TXCW)) { 632 status = er32(STATUS); 633 if (status & E1000_STATUS_LU) { 634 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 635 udelay(10); 636 rxcw = er32(RXCW); 637 if (rxcw & E1000_RXCW_SYNCH) { 638 if (!(rxcw & E1000_RXCW_IV)) { 639 mac->serdes_has_link = true; 640 e_dbg("SERDES: Link up - autoneg completed successfully.\n"); 641 } else { 642 mac->serdes_has_link = false; 643 e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n"); 644 } 645 } else { 646 mac->serdes_has_link = false; 647 e_dbg("SERDES: Link down - no sync.\n"); 648 } 649 } else { 650 mac->serdes_has_link = false; 651 e_dbg("SERDES: Link down - autoneg failed\n"); 652 } 653 } 654 655 return 0; 656} 657 658/** 659 * e1000_set_default_fc_generic - Set flow control default values 660 * @hw: pointer to the HW structure 661 * 662 * Read the EEPROM for the default values for flow control and store the 663 * values. 664 **/ 665static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 666{ 667 s32 ret_val; 668 u16 nvm_data; 669 670 /* 671 * Read and store word 0x0F of the EEPROM. This word contains bits 672 * that determine the hardware's default PAUSE (flow control) mode, 673 * a bit that determines whether the HW defaults to enabling or 674 * disabling auto-negotiation, and the direction of the 675 * SW defined pins. If there is no SW over-ride of the flow 676 * control setting, then the variable hw->fc will 677 * be initialized based on a value in the EEPROM. 678 */ 679 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 680 681 if (ret_val) { 682 e_dbg("NVM Read Error\n"); 683 return ret_val; 684 } 685 686 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 687 hw->fc.requested_mode = e1000_fc_none; 688 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR) 689 hw->fc.requested_mode = e1000_fc_tx_pause; 690 else 691 hw->fc.requested_mode = e1000_fc_full; 692 693 return 0; 694} 695 696/** 697 * e1000e_setup_link - Setup flow control and link settings 698 * @hw: pointer to the HW structure 699 * 700 * Determines which flow control settings to use, then configures flow 701 * control. Calls the appropriate media-specific link configuration 702 * function. Assuming the adapter has a valid link partner, a valid link 703 * should be established. Assumes the hardware has previously been reset 704 * and the transmitter and receiver are not enabled. 705 **/ 706s32 e1000e_setup_link(struct e1000_hw *hw) 707{ 708 struct e1000_mac_info *mac = &hw->mac; 709 s32 ret_val; 710 711 /* 712 * In the case of the phy reset being blocked, we already have a link. 713 * We do not need to set it up again. 714 */ 715 if (e1000_check_reset_block(hw)) 716 return 0; 717 718 /* 719 * If requested flow control is set to default, set flow control 720 * based on the EEPROM flow control settings. 721 */ 722 if (hw->fc.requested_mode == e1000_fc_default) { 723 ret_val = e1000_set_default_fc_generic(hw); 724 if (ret_val) 725 return ret_val; 726 } 727 728 /* 729 * Save off the requested flow control mode for use later. Depending 730 * on the link partner's capabilities, we may or may not use this mode. 731 */ 732 hw->fc.current_mode = hw->fc.requested_mode; 733 734 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 735 736 /* Call the necessary media_type subroutine to configure the link. */ 737 ret_val = mac->ops.setup_physical_interface(hw); 738 if (ret_val) 739 return ret_val; 740 741 /* 742 * Initialize the flow control address, type, and PAUSE timer 743 * registers to their default values. This is done even if flow 744 * control is disabled, because it does not hurt anything to 745 * initialize these registers. 746 */ 747 e_dbg("Initializing the Flow Control address, type and timer regs\n"); 748 ew32(FCT, FLOW_CONTROL_TYPE); 749 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 750 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); 751 752 ew32(FCTTV, hw->fc.pause_time); 753 754 return e1000e_set_fc_watermarks(hw); 755} 756 757/** 758 * e1000_commit_fc_settings_generic - Configure flow control 759 * @hw: pointer to the HW structure 760 * 761 * Write the flow control settings to the Transmit Config Word Register (TXCW) 762 * base on the flow control settings in e1000_mac_info. 763 **/ 764static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 765{ 766 struct e1000_mac_info *mac = &hw->mac; 767 u32 txcw; 768 769 /* 770 * Check for a software override of the flow control settings, and 771 * setup the device accordingly. If auto-negotiation is enabled, then 772 * software will have to set the "PAUSE" bits to the correct value in 773 * the Transmit Config Word Register (TXCW) and re-start auto- 774 * negotiation. However, if auto-negotiation is disabled, then 775 * software will have to manually configure the two flow control enable 776 * bits in the CTRL register. 777 * 778 * The possible values of the "fc" parameter are: 779 * 0: Flow control is completely disabled 780 * 1: Rx flow control is enabled (we can receive pause frames, 781 * but not send pause frames). 782 * 2: Tx flow control is enabled (we can send pause frames but we 783 * do not support receiving pause frames). 784 * 3: Both Rx and Tx flow control (symmetric) are enabled. 785 */ 786 switch (hw->fc.current_mode) { 787 case e1000_fc_none: 788 /* Flow control completely disabled by a software over-ride. */ 789 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 790 break; 791 case e1000_fc_rx_pause: 792 /* 793 * Rx Flow control is enabled and Tx Flow control is disabled 794 * by a software over-ride. Since there really isn't a way to 795 * advertise that we are capable of Rx Pause ONLY, we will 796 * advertise that we support both symmetric and asymmetric Rx 797 * PAUSE. Later, we will disable the adapter's ability to send 798 * PAUSE frames. 799 */ 800 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 801 break; 802 case e1000_fc_tx_pause: 803 /* 804 * Tx Flow control is enabled, and Rx Flow control is disabled, 805 * by a software over-ride. 806 */ 807 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 808 break; 809 case e1000_fc_full: 810 /* 811 * Flow control (both Rx and Tx) is enabled by a software 812 * over-ride. 813 */ 814 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 815 break; 816 default: 817 e_dbg("Flow control param set incorrectly\n"); 818 return -E1000_ERR_CONFIG; 819 break; 820 } 821 822 ew32(TXCW, txcw); 823 mac->txcw = txcw; 824 825 return 0; 826} 827 828/** 829 * e1000_poll_fiber_serdes_link_generic - Poll for link up 830 * @hw: pointer to the HW structure 831 * 832 * Polls for link up by reading the status register, if link fails to come 833 * up with auto-negotiation, then the link is forced if a signal is detected. 834 **/ 835static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 836{ 837 struct e1000_mac_info *mac = &hw->mac; 838 u32 i, status; 839 s32 ret_val; 840 841 /* 842 * If we have a signal (the cable is plugged in, or assumed true for 843 * serdes media) then poll for a "Link-Up" indication in the Device 844 * Status Register. Time-out if a link isn't seen in 500 milliseconds 845 * seconds (Auto-negotiation should complete in less than 500 846 * milliseconds even if the other end is doing it in SW). 847 */ 848 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 849 usleep_range(10000, 20000); 850 status = er32(STATUS); 851 if (status & E1000_STATUS_LU) 852 break; 853 } 854 if (i == FIBER_LINK_UP_LIMIT) { 855 e_dbg("Never got a valid link from auto-neg!!!\n"); 856 mac->autoneg_failed = true; 857 /* 858 * AutoNeg failed to achieve a link, so we'll call 859 * mac->check_for_link. This routine will force the 860 * link up if we detect a signal. This will allow us to 861 * communicate with non-autonegotiating link partners. 862 */ 863 ret_val = mac->ops.check_for_link(hw); 864 if (ret_val) { 865 e_dbg("Error while checking for link\n"); 866 return ret_val; 867 } 868 mac->autoneg_failed = false; 869 } else { 870 mac->autoneg_failed = false; 871 e_dbg("Valid Link Found\n"); 872 } 873 874 return 0; 875} 876 877/** 878 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes 879 * @hw: pointer to the HW structure 880 * 881 * Configures collision distance and flow control for fiber and serdes 882 * links. Upon successful setup, poll for link. 883 **/ 884s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw) 885{ 886 u32 ctrl; 887 s32 ret_val; 888 889 ctrl = er32(CTRL); 890 891 /* Take the link out of reset */ 892 ctrl &= ~E1000_CTRL_LRST; 893 894 e1000e_config_collision_dist(hw); 895 896 ret_val = e1000_commit_fc_settings_generic(hw); 897 if (ret_val) 898 return ret_val; 899 900 /* 901 * Since auto-negotiation is enabled, take the link out of reset (the 902 * link will be in reset, because we previously reset the chip). This 903 * will restart auto-negotiation. If auto-negotiation is successful 904 * then the link-up status bit will be set and the flow control enable 905 * bits (RFCE and TFCE) will be set according to their negotiated value. 906 */ 907 e_dbg("Auto-negotiation enabled\n"); 908 909 ew32(CTRL, ctrl); 910 e1e_flush(); 911 usleep_range(1000, 2000); 912 913 /* 914 * For these adapters, the SW definable pin 1 is set when the optics 915 * detect a signal. If we have a signal, then poll for a "Link-Up" 916 * indication. 917 */ 918 if (hw->phy.media_type == e1000_media_type_internal_serdes || 919 (er32(CTRL) & E1000_CTRL_SWDPIN1)) { 920 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 921 } else { 922 e_dbg("No signal detected\n"); 923 } 924 925 return 0; 926} 927 928/** 929 * e1000e_config_collision_dist - Configure collision distance 930 * @hw: pointer to the HW structure 931 * 932 * Configures the collision distance to the default value and is used 933 * during link setup. Currently no func pointer exists and all 934 * implementations are handled in the generic version of this function. 935 **/ 936void e1000e_config_collision_dist(struct e1000_hw *hw) 937{ 938 u32 tctl; 939 940 tctl = er32(TCTL); 941 942 tctl &= ~E1000_TCTL_COLD; 943 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 944 945 ew32(TCTL, tctl); 946 e1e_flush(); 947} 948 949/** 950 * e1000e_set_fc_watermarks - Set flow control high/low watermarks 951 * @hw: pointer to the HW structure 952 * 953 * Sets the flow control high/low threshold (watermark) registers. If 954 * flow control XON frame transmission is enabled, then set XON frame 955 * transmission as well. 956 **/ 957s32 e1000e_set_fc_watermarks(struct e1000_hw *hw) 958{ 959 u32 fcrtl = 0, fcrth = 0; 960 961 /* 962 * Set the flow control receive threshold registers. Normally, 963 * these registers will be set to a default threshold that may be 964 * adjusted later by the driver's runtime code. However, if the 965 * ability to transmit pause frames is not enabled, then these 966 * registers will be set to 0. 967 */ 968 if (hw->fc.current_mode & e1000_fc_tx_pause) { 969 /* 970 * We need to set up the Receive Threshold high and low water 971 * marks as well as (optionally) enabling the transmission of 972 * XON frames. 973 */ 974 fcrtl = hw->fc.low_water; 975 fcrtl |= E1000_FCRTL_XONE; 976 fcrth = hw->fc.high_water; 977 } 978 ew32(FCRTL, fcrtl); 979 ew32(FCRTH, fcrth); 980 981 return 0; 982} 983 984/** 985 * e1000e_force_mac_fc - Force the MAC's flow control settings 986 * @hw: pointer to the HW structure 987 * 988 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 989 * device control register to reflect the adapter settings. TFCE and RFCE 990 * need to be explicitly set by software when a copper PHY is used because 991 * autonegotiation is managed by the PHY rather than the MAC. Software must 992 * also configure these bits when link is forced on a fiber connection. 993 **/ 994s32 e1000e_force_mac_fc(struct e1000_hw *hw) 995{ 996 u32 ctrl; 997 998 ctrl = er32(CTRL); 999 1000 /* 1001 * Because we didn't get link via the internal auto-negotiation 1002 * mechanism (we either forced link or we got link via PHY 1003 * auto-neg), we have to manually enable/disable transmit an 1004 * receive flow control. 1005 * 1006 * The "Case" statement below enables/disable flow control 1007 * according to the "hw->fc.current_mode" parameter. 1008 * 1009 * The possible values of the "fc" parameter are: 1010 * 0: Flow control is completely disabled 1011 * 1: Rx flow control is enabled (we can receive pause 1012 * frames but not send pause frames). 1013 * 2: Tx flow control is enabled (we can send pause frames 1014 * frames but we do not receive pause frames). 1015 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1016 * other: No other values should be possible at this point. 1017 */ 1018 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1019 1020 switch (hw->fc.current_mode) { 1021 case e1000_fc_none: 1022 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1023 break; 1024 case e1000_fc_rx_pause: 1025 ctrl &= (~E1000_CTRL_TFCE); 1026 ctrl |= E1000_CTRL_RFCE; 1027 break; 1028 case e1000_fc_tx_pause: 1029 ctrl &= (~E1000_CTRL_RFCE); 1030 ctrl |= E1000_CTRL_TFCE; 1031 break; 1032 case e1000_fc_full: 1033 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1034 break; 1035 default: 1036 e_dbg("Flow control param set incorrectly\n"); 1037 return -E1000_ERR_CONFIG; 1038 } 1039 1040 ew32(CTRL, ctrl); 1041 1042 return 0; 1043} 1044 1045/** 1046 * e1000e_config_fc_after_link_up - Configures flow control after link 1047 * @hw: pointer to the HW structure 1048 * 1049 * Checks the status of auto-negotiation after link up to ensure that the 1050 * speed and duplex were not forced. If the link needed to be forced, then 1051 * flow control needs to be forced also. If auto-negotiation is enabled 1052 * and did not fail, then we configure flow control based on our link 1053 * partner. 1054 **/ 1055s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw) 1056{ 1057 struct e1000_mac_info *mac = &hw->mac; 1058 s32 ret_val = 0; 1059 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1060 u16 speed, duplex; 1061 1062 /* 1063 * Check for the case where we have fiber media and auto-neg failed 1064 * so we had to force link. In this case, we need to force the 1065 * configuration of the MAC to match the "fc" parameter. 1066 */ 1067 if (mac->autoneg_failed) { 1068 if (hw->phy.media_type == e1000_media_type_fiber || 1069 hw->phy.media_type == e1000_media_type_internal_serdes) 1070 ret_val = e1000e_force_mac_fc(hw); 1071 } else { 1072 if (hw->phy.media_type == e1000_media_type_copper) 1073 ret_val = e1000e_force_mac_fc(hw); 1074 } 1075 1076 if (ret_val) { 1077 e_dbg("Error forcing flow control settings\n"); 1078 return ret_val; 1079 } 1080 1081 /* 1082 * Check for the case where we have copper media and auto-neg is 1083 * enabled. In this case, we need to check and see if Auto-Neg 1084 * has completed, and if so, how the PHY and link partner has 1085 * flow control configured. 1086 */ 1087 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1088 /* 1089 * Read the MII Status Register and check to see if AutoNeg 1090 * has completed. We read this twice because this reg has 1091 * some "sticky" (latched) bits. 1092 */ 1093 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); 1094 if (ret_val) 1095 return ret_val; 1096 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); 1097 if (ret_val) 1098 return ret_val; 1099 1100 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1101 e_dbg("Copper PHY and Auto Neg has not completed.\n"); 1102 return ret_val; 1103 } 1104 1105 /* 1106 * The AutoNeg process has completed, so we now need to 1107 * read both the Auto Negotiation Advertisement 1108 * Register (Address 4) and the Auto_Negotiation Base 1109 * Page Ability Register (Address 5) to determine how 1110 * flow control was negotiated. 1111 */ 1112 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg); 1113 if (ret_val) 1114 return ret_val; 1115 ret_val = 1116 e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg); 1117 if (ret_val) 1118 return ret_val; 1119 1120 /* 1121 * Two bits in the Auto Negotiation Advertisement Register 1122 * (Address 4) and two bits in the Auto Negotiation Base 1123 * Page Ability Register (Address 5) determine flow control 1124 * for both the PHY and the link partner. The following 1125 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1126 * 1999, describes these PAUSE resolution bits and how flow 1127 * control is determined based upon these settings. 1128 * NOTE: DC = Don't Care 1129 * 1130 * LOCAL DEVICE | LINK PARTNER 1131 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1132 *-------|---------|-------|---------|-------------------- 1133 * 0 | 0 | DC | DC | e1000_fc_none 1134 * 0 | 1 | 0 | DC | e1000_fc_none 1135 * 0 | 1 | 1 | 0 | e1000_fc_none 1136 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1137 * 1 | 0 | 0 | DC | e1000_fc_none 1138 * 1 | DC | 1 | DC | e1000_fc_full 1139 * 1 | 1 | 0 | 0 | e1000_fc_none 1140 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1141 * 1142 * Are both PAUSE bits set to 1? If so, this implies 1143 * Symmetric Flow Control is enabled at both ends. The 1144 * ASM_DIR bits are irrelevant per the spec. 1145 * 1146 * For Symmetric Flow Control: 1147 * 1148 * LOCAL DEVICE | LINK PARTNER 1149 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1150 *-------|---------|-------|---------|-------------------- 1151 * 1 | DC | 1 | DC | E1000_fc_full 1152 * 1153 */ 1154 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1155 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1156 /* 1157 * Now we need to check if the user selected Rx ONLY 1158 * of pause frames. In this case, we had to advertise 1159 * FULL flow control because we could not advertise Rx 1160 * ONLY. Hence, we must now check to see if we need to 1161 * turn OFF the TRANSMISSION of PAUSE frames. 1162 */ 1163 if (hw->fc.requested_mode == e1000_fc_full) { 1164 hw->fc.current_mode = e1000_fc_full; 1165 e_dbg("Flow Control = FULL.\n"); 1166 } else { 1167 hw->fc.current_mode = e1000_fc_rx_pause; 1168 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1169 } 1170 } 1171 /* 1172 * For receiving PAUSE frames ONLY. 1173 * 1174 * LOCAL DEVICE | LINK PARTNER 1175 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1176 *-------|---------|-------|---------|-------------------- 1177 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1178 */ 1179 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1180 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1181 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1182 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1183 hw->fc.current_mode = e1000_fc_tx_pause; 1184 e_dbg("Flow Control = Tx PAUSE frames only.\n"); 1185 } 1186 /* 1187 * For transmitting PAUSE frames ONLY. 1188 * 1189 * LOCAL DEVICE | LINK PARTNER 1190 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1191 *-------|---------|-------|---------|-------------------- 1192 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1193 */ 1194 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1195 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1196 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1197 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1198 hw->fc.current_mode = e1000_fc_rx_pause; 1199 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1200 } else { 1201 /* 1202 * Per the IEEE spec, at this point flow control 1203 * should be disabled. 1204 */ 1205 hw->fc.current_mode = e1000_fc_none; 1206 e_dbg("Flow Control = NONE.\n"); 1207 } 1208 1209 /* 1210 * Now we need to do one last check... If we auto- 1211 * negotiated to HALF DUPLEX, flow control should not be 1212 * enabled per IEEE 802.3 spec. 1213 */ 1214 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1215 if (ret_val) { 1216 e_dbg("Error getting link speed and duplex\n"); 1217 return ret_val; 1218 } 1219 1220 if (duplex == HALF_DUPLEX) 1221 hw->fc.current_mode = e1000_fc_none; 1222 1223 /* 1224 * Now we call a subroutine to actually force the MAC 1225 * controller to use the correct flow control settings. 1226 */ 1227 ret_val = e1000e_force_mac_fc(hw); 1228 if (ret_val) { 1229 e_dbg("Error forcing flow control settings\n"); 1230 return ret_val; 1231 } 1232 } 1233 1234 return 0; 1235} 1236 1237/** 1238 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex 1239 * @hw: pointer to the HW structure 1240 * @speed: stores the current speed 1241 * @duplex: stores the current duplex 1242 * 1243 * Read the status register for the current speed/duplex and store the current 1244 * speed and duplex for copper connections. 1245 **/ 1246s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, 1247 u16 *duplex) 1248{ 1249 u32 status; 1250 1251 status = er32(STATUS); 1252 if (status & E1000_STATUS_SPEED_1000) 1253 *speed = SPEED_1000; 1254 else if (status & E1000_STATUS_SPEED_100) 1255 *speed = SPEED_100; 1256 else 1257 *speed = SPEED_10; 1258 1259 if (status & E1000_STATUS_FD) 1260 *duplex = FULL_DUPLEX; 1261 else 1262 *duplex = HALF_DUPLEX; 1263 1264 e_dbg("%u Mbps, %s Duplex\n", 1265 *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10, 1266 *duplex == FULL_DUPLEX ? "Full" : "Half"); 1267 1268 return 0; 1269} 1270 1271/** 1272 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex 1273 * @hw: pointer to the HW structure 1274 * @speed: stores the current speed 1275 * @duplex: stores the current duplex 1276 * 1277 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1278 * for fiber/serdes links. 1279 **/ 1280s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, 1281 u16 *duplex) 1282{ 1283 *speed = SPEED_1000; 1284 *duplex = FULL_DUPLEX; 1285 1286 return 0; 1287} 1288 1289/** 1290 * e1000e_get_hw_semaphore - Acquire hardware semaphore 1291 * @hw: pointer to the HW structure 1292 * 1293 * Acquire the HW semaphore to access the PHY or NVM 1294 **/ 1295s32 e1000e_get_hw_semaphore(struct e1000_hw *hw) 1296{ 1297 u32 swsm; 1298 s32 timeout = hw->nvm.word_size + 1; 1299 s32 i = 0; 1300 1301 /* Get the SW semaphore */ 1302 while (i < timeout) { 1303 swsm = er32(SWSM); 1304 if (!(swsm & E1000_SWSM_SMBI)) 1305 break; 1306 1307 udelay(50); 1308 i++; 1309 } 1310 1311 if (i == timeout) { 1312 e_dbg("Driver can't access device - SMBI bit is set.\n"); 1313 return -E1000_ERR_NVM; 1314 } 1315 1316 /* Get the FW semaphore. */ 1317 for (i = 0; i < timeout; i++) { 1318 swsm = er32(SWSM); 1319 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); 1320 1321 /* Semaphore acquired if bit latched */ 1322 if (er32(SWSM) & E1000_SWSM_SWESMBI) 1323 break; 1324 1325 udelay(50); 1326 } 1327 1328 if (i == timeout) { 1329 /* Release semaphores */ 1330 e1000e_put_hw_semaphore(hw); 1331 e_dbg("Driver can't access the NVM\n"); 1332 return -E1000_ERR_NVM; 1333 } 1334 1335 return 0; 1336} 1337 1338/** 1339 * e1000e_put_hw_semaphore - Release hardware semaphore 1340 * @hw: pointer to the HW structure 1341 * 1342 * Release hardware semaphore used to access the PHY or NVM 1343 **/ 1344void e1000e_put_hw_semaphore(struct e1000_hw *hw) 1345{ 1346 u32 swsm; 1347 1348 swsm = er32(SWSM); 1349 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1350 ew32(SWSM, swsm); 1351} 1352 1353/** 1354 * e1000e_get_auto_rd_done - Check for auto read completion 1355 * @hw: pointer to the HW structure 1356 * 1357 * Check EEPROM for Auto Read done bit. 1358 **/ 1359s32 e1000e_get_auto_rd_done(struct e1000_hw *hw) 1360{ 1361 s32 i = 0; 1362 1363 while (i < AUTO_READ_DONE_TIMEOUT) { 1364 if (er32(EECD) & E1000_EECD_AUTO_RD) 1365 break; 1366 usleep_range(1000, 2000); 1367 i++; 1368 } 1369 1370 if (i == AUTO_READ_DONE_TIMEOUT) { 1371 e_dbg("Auto read by HW from NVM has not completed.\n"); 1372 return -E1000_ERR_RESET; 1373 } 1374 1375 return 0; 1376} 1377 1378/** 1379 * e1000e_valid_led_default - Verify a valid default LED config 1380 * @hw: pointer to the HW structure 1381 * @data: pointer to the NVM (EEPROM) 1382 * 1383 * Read the EEPROM for the current default LED configuration. If the 1384 * LED configuration is not valid, set to a valid LED configuration. 1385 **/ 1386s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data) 1387{ 1388 s32 ret_val; 1389 1390 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1391 if (ret_val) { 1392 e_dbg("NVM Read Error\n"); 1393 return ret_val; 1394 } 1395 1396 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1397 *data = ID_LED_DEFAULT; 1398 1399 return 0; 1400} 1401 1402/** 1403 * e1000e_id_led_init - 1404 * @hw: pointer to the HW structure 1405 * 1406 **/ 1407s32 e1000e_id_led_init(struct e1000_hw *hw) 1408{ 1409 struct e1000_mac_info *mac = &hw->mac; 1410 s32 ret_val; 1411 const u32 ledctl_mask = 0x000000FF; 1412 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1413 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1414 u16 data, i, temp; 1415 const u16 led_mask = 0x0F; 1416 1417 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1418 if (ret_val) 1419 return ret_val; 1420 1421 mac->ledctl_default = er32(LEDCTL); 1422 mac->ledctl_mode1 = mac->ledctl_default; 1423 mac->ledctl_mode2 = mac->ledctl_default; 1424 1425 for (i = 0; i < 4; i++) { 1426 temp = (data >> (i << 2)) & led_mask; 1427 switch (temp) { 1428 case ID_LED_ON1_DEF2: 1429 case ID_LED_ON1_ON2: 1430 case ID_LED_ON1_OFF2: 1431 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1432 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1433 break; 1434 case ID_LED_OFF1_DEF2: 1435 case ID_LED_OFF1_ON2: 1436 case ID_LED_OFF1_OFF2: 1437 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1438 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1439 break; 1440 default: 1441 /* Do nothing */ 1442 break; 1443 } 1444 switch (temp) { 1445 case ID_LED_DEF1_ON2: 1446 case ID_LED_ON1_ON2: 1447 case ID_LED_OFF1_ON2: 1448 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1449 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1450 break; 1451 case ID_LED_DEF1_OFF2: 1452 case ID_LED_ON1_OFF2: 1453 case ID_LED_OFF1_OFF2: 1454 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1455 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1456 break; 1457 default: 1458 /* Do nothing */ 1459 break; 1460 } 1461 } 1462 1463 return 0; 1464} 1465 1466/** 1467 * e1000e_setup_led_generic - Configures SW controllable LED 1468 * @hw: pointer to the HW structure 1469 * 1470 * This prepares the SW controllable LED for use and saves the current state 1471 * of the LED so it can be later restored. 1472 **/ 1473s32 e1000e_setup_led_generic(struct e1000_hw *hw) 1474{ 1475 u32 ledctl; 1476 1477 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) 1478 return -E1000_ERR_CONFIG; 1479 1480 if (hw->phy.media_type == e1000_media_type_fiber) { 1481 ledctl = er32(LEDCTL); 1482 hw->mac.ledctl_default = ledctl; 1483 /* Turn off LED0 */ 1484 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1485 E1000_LEDCTL_LED0_MODE_MASK); 1486 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1487 E1000_LEDCTL_LED0_MODE_SHIFT); 1488 ew32(LEDCTL, ledctl); 1489 } else if (hw->phy.media_type == e1000_media_type_copper) { 1490 ew32(LEDCTL, hw->mac.ledctl_mode1); 1491 } 1492 1493 return 0; 1494} 1495 1496/** 1497 * e1000e_cleanup_led_generic - Set LED config to default operation 1498 * @hw: pointer to the HW structure 1499 * 1500 * Remove the current LED configuration and set the LED configuration 1501 * to the default value, saved from the EEPROM. 1502 **/ 1503s32 e1000e_cleanup_led_generic(struct e1000_hw *hw) 1504{ 1505 ew32(LEDCTL, hw->mac.ledctl_default); 1506 return 0; 1507} 1508 1509/** 1510 * e1000e_blink_led_generic - Blink LED 1511 * @hw: pointer to the HW structure 1512 * 1513 * Blink the LEDs which are set to be on. 1514 **/ 1515s32 e1000e_blink_led_generic(struct e1000_hw *hw) 1516{ 1517 u32 ledctl_blink = 0; 1518 u32 i; 1519 1520 if (hw->phy.media_type == e1000_media_type_fiber) { 1521 /* always blink LED0 for PCI-E fiber */ 1522 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1523 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1524 } else { 1525 /* 1526 * set the blink bit for each LED that's "on" (0x0E) 1527 * in ledctl_mode2 1528 */ 1529 ledctl_blink = hw->mac.ledctl_mode2; 1530 for (i = 0; i < 4; i++) 1531 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1532 E1000_LEDCTL_MODE_LED_ON) 1533 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1534 (i * 8)); 1535 } 1536 1537 ew32(LEDCTL, ledctl_blink); 1538 1539 return 0; 1540} 1541 1542/** 1543 * e1000e_led_on_generic - Turn LED on 1544 * @hw: pointer to the HW structure 1545 * 1546 * Turn LED on. 1547 **/ 1548s32 e1000e_led_on_generic(struct e1000_hw *hw) 1549{ 1550 u32 ctrl; 1551 1552 switch (hw->phy.media_type) { 1553 case e1000_media_type_fiber: 1554 ctrl = er32(CTRL); 1555 ctrl &= ~E1000_CTRL_SWDPIN0; 1556 ctrl |= E1000_CTRL_SWDPIO0; 1557 ew32(CTRL, ctrl); 1558 break; 1559 case e1000_media_type_copper: 1560 ew32(LEDCTL, hw->mac.ledctl_mode2); 1561 break; 1562 default: 1563 break; 1564 } 1565 1566 return 0; 1567} 1568 1569/** 1570 * e1000e_led_off_generic - Turn LED off 1571 * @hw: pointer to the HW structure 1572 * 1573 * Turn LED off. 1574 **/ 1575s32 e1000e_led_off_generic(struct e1000_hw *hw) 1576{ 1577 u32 ctrl; 1578 1579 switch (hw->phy.media_type) { 1580 case e1000_media_type_fiber: 1581 ctrl = er32(CTRL); 1582 ctrl |= E1000_CTRL_SWDPIN0; 1583 ctrl |= E1000_CTRL_SWDPIO0; 1584 ew32(CTRL, ctrl); 1585 break; 1586 case e1000_media_type_copper: 1587 ew32(LEDCTL, hw->mac.ledctl_mode1); 1588 break; 1589 default: 1590 break; 1591 } 1592 1593 return 0; 1594} 1595 1596/** 1597 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities 1598 * @hw: pointer to the HW structure 1599 * @no_snoop: bitmap of snoop events 1600 * 1601 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1602 **/ 1603void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) 1604{ 1605 u32 gcr; 1606 1607 if (no_snoop) { 1608 gcr = er32(GCR); 1609 gcr &= ~(PCIE_NO_SNOOP_ALL); 1610 gcr |= no_snoop; 1611 ew32(GCR, gcr); 1612 } 1613} 1614 1615/** 1616 * e1000e_disable_pcie_master - Disables PCI-express master access 1617 * @hw: pointer to the HW structure 1618 * 1619 * Returns 0 if successful, else returns -10 1620 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1621 * the master requests to be disabled. 1622 * 1623 * Disables PCI-Express master access and verifies there are no pending 1624 * requests. 1625 **/ 1626s32 e1000e_disable_pcie_master(struct e1000_hw *hw) 1627{ 1628 u32 ctrl; 1629 s32 timeout = MASTER_DISABLE_TIMEOUT; 1630 1631 ctrl = er32(CTRL); 1632 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1633 ew32(CTRL, ctrl); 1634 1635 while (timeout) { 1636 if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) 1637 break; 1638 udelay(100); 1639 timeout--; 1640 } 1641 1642 if (!timeout) { 1643 e_dbg("Master requests are pending.\n"); 1644 return -E1000_ERR_MASTER_REQUESTS_PENDING; 1645 } 1646 1647 return 0; 1648} 1649 1650/** 1651 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing 1652 * @hw: pointer to the HW structure 1653 * 1654 * Reset the Adaptive Interframe Spacing throttle to default values. 1655 **/ 1656void e1000e_reset_adaptive(struct e1000_hw *hw) 1657{ 1658 struct e1000_mac_info *mac = &hw->mac; 1659 1660 if (!mac->adaptive_ifs) { 1661 e_dbg("Not in Adaptive IFS mode!\n"); 1662 return; 1663 } 1664 1665 mac->current_ifs_val = 0; 1666 mac->ifs_min_val = IFS_MIN; 1667 mac->ifs_max_val = IFS_MAX; 1668 mac->ifs_step_size = IFS_STEP; 1669 mac->ifs_ratio = IFS_RATIO; 1670 1671 mac->in_ifs_mode = false; 1672 ew32(AIT, 0); 1673} 1674 1675/** 1676 * e1000e_update_adaptive - Update Adaptive Interframe Spacing 1677 * @hw: pointer to the HW structure 1678 * 1679 * Update the Adaptive Interframe Spacing Throttle value based on the 1680 * time between transmitted packets and time between collisions. 1681 **/ 1682void e1000e_update_adaptive(struct e1000_hw *hw) 1683{ 1684 struct e1000_mac_info *mac = &hw->mac; 1685 1686 if (!mac->adaptive_ifs) { 1687 e_dbg("Not in Adaptive IFS mode!\n"); 1688 return; 1689 } 1690 1691 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 1692 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 1693 mac->in_ifs_mode = true; 1694 if (mac->current_ifs_val < mac->ifs_max_val) { 1695 if (!mac->current_ifs_val) 1696 mac->current_ifs_val = mac->ifs_min_val; 1697 else 1698 mac->current_ifs_val += 1699 mac->ifs_step_size; 1700 ew32(AIT, mac->current_ifs_val); 1701 } 1702 } 1703 } else { 1704 if (mac->in_ifs_mode && 1705 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 1706 mac->current_ifs_val = 0; 1707 mac->in_ifs_mode = false; 1708 ew32(AIT, 0); 1709 } 1710 } 1711} 1712