mac.c revision b20caa80e8c9b0180defb42678209dc0d6c229d2
1/******************************************************************************* 2 3 Intel PRO/1000 Linux driver 4 Copyright(c) 1999 - 2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 Linux NICS <linux.nics@intel.com> 24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 26 27*******************************************************************************/ 28 29#include "e1000.h" 30 31/** 32 * e1000e_get_bus_info_pcie - Get PCIe bus information 33 * @hw: pointer to the HW structure 34 * 35 * Determines and stores the system bus information for a particular 36 * network interface. The following bus information is determined and stored: 37 * bus speed, bus width, type (PCIe), and PCIe function. 38 **/ 39s32 e1000e_get_bus_info_pcie(struct e1000_hw *hw) 40{ 41 struct e1000_mac_info *mac = &hw->mac; 42 struct e1000_bus_info *bus = &hw->bus; 43 struct e1000_adapter *adapter = hw->adapter; 44 u16 pcie_link_status, cap_offset; 45 46 cap_offset = adapter->pdev->pcie_cap; 47 if (!cap_offset) { 48 bus->width = e1000_bus_width_unknown; 49 } else { 50 pci_read_config_word(adapter->pdev, 51 cap_offset + PCIE_LINK_STATUS, 52 &pcie_link_status); 53 bus->width = (enum e1000_bus_width)((pcie_link_status & 54 PCIE_LINK_WIDTH_MASK) >> 55 PCIE_LINK_WIDTH_SHIFT); 56 } 57 58 mac->ops.set_lan_id(hw); 59 60 return 0; 61} 62 63/** 64 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices 65 * 66 * @hw: pointer to the HW structure 67 * 68 * Determines the LAN function id by reading memory-mapped registers 69 * and swaps the port value if requested. 70 **/ 71void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw) 72{ 73 struct e1000_bus_info *bus = &hw->bus; 74 u32 reg; 75 76 /* 77 * The status register reports the correct function number 78 * for the device regardless of function swap state. 79 */ 80 reg = er32(STATUS); 81 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT; 82} 83 84/** 85 * e1000_set_lan_id_single_port - Set LAN id for a single port device 86 * @hw: pointer to the HW structure 87 * 88 * Sets the LAN function id to zero for a single port device. 89 **/ 90void e1000_set_lan_id_single_port(struct e1000_hw *hw) 91{ 92 struct e1000_bus_info *bus = &hw->bus; 93 94 bus->func = 0; 95} 96 97/** 98 * e1000_clear_vfta_generic - Clear VLAN filter table 99 * @hw: pointer to the HW structure 100 * 101 * Clears the register array which contains the VLAN filter table by 102 * setting all the values to 0. 103 **/ 104void e1000_clear_vfta_generic(struct e1000_hw *hw) 105{ 106 u32 offset; 107 108 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) { 109 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0); 110 e1e_flush(); 111 } 112} 113 114/** 115 * e1000_write_vfta_generic - Write value to VLAN filter table 116 * @hw: pointer to the HW structure 117 * @offset: register offset in VLAN filter table 118 * @value: register value written to VLAN filter table 119 * 120 * Writes value at the given offset in the register array which stores 121 * the VLAN filter table. 122 **/ 123void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value) 124{ 125 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value); 126 e1e_flush(); 127} 128 129/** 130 * e1000e_init_rx_addrs - Initialize receive address's 131 * @hw: pointer to the HW structure 132 * @rar_count: receive address registers 133 * 134 * Setup the receive address registers by setting the base receive address 135 * register to the devices MAC address and clearing all the other receive 136 * address registers to 0. 137 **/ 138void e1000e_init_rx_addrs(struct e1000_hw *hw, u16 rar_count) 139{ 140 u32 i; 141 u8 mac_addr[ETH_ALEN] = { 0 }; 142 143 /* Setup the receive address */ 144 e_dbg("Programming MAC Address into RAR[0]\n"); 145 146 e1000e_rar_set(hw, hw->mac.addr, 0); 147 148 /* Zero out the other (rar_entry_count - 1) receive addresses */ 149 e_dbg("Clearing RAR[1-%u]\n", rar_count - 1); 150 for (i = 1; i < rar_count; i++) 151 e1000e_rar_set(hw, mac_addr, i); 152} 153 154/** 155 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr 156 * @hw: pointer to the HW structure 157 * 158 * Checks the nvm for an alternate MAC address. An alternate MAC address 159 * can be setup by pre-boot software and must be treated like a permanent 160 * address and must override the actual permanent MAC address. If an 161 * alternate MAC address is found it is programmed into RAR0, replacing 162 * the permanent address that was installed into RAR0 by the Si on reset. 163 * This function will return SUCCESS unless it encounters an error while 164 * reading the EEPROM. 165 **/ 166s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw) 167{ 168 u32 i; 169 s32 ret_val = 0; 170 u16 offset, nvm_alt_mac_addr_offset, nvm_data; 171 u8 alt_mac_addr[ETH_ALEN]; 172 173 ret_val = e1000_read_nvm(hw, NVM_COMPAT, 1, &nvm_data); 174 if (ret_val) 175 return ret_val; 176 177 /* not supported on 82573 */ 178 if (hw->mac.type == e1000_82573) 179 return 0; 180 181 ret_val = e1000_read_nvm(hw, NVM_ALT_MAC_ADDR_PTR, 1, 182 &nvm_alt_mac_addr_offset); 183 if (ret_val) { 184 e_dbg("NVM Read Error\n"); 185 return ret_val; 186 } 187 188 if ((nvm_alt_mac_addr_offset == 0xFFFF) || 189 (nvm_alt_mac_addr_offset == 0x0000)) 190 /* There is no Alternate MAC Address */ 191 return 0; 192 193 if (hw->bus.func == E1000_FUNC_1) 194 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1; 195 for (i = 0; i < ETH_ALEN; i += 2) { 196 offset = nvm_alt_mac_addr_offset + (i >> 1); 197 ret_val = e1000_read_nvm(hw, offset, 1, &nvm_data); 198 if (ret_val) { 199 e_dbg("NVM Read Error\n"); 200 return ret_val; 201 } 202 203 alt_mac_addr[i] = (u8)(nvm_data & 0xFF); 204 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8); 205 } 206 207 /* if multicast bit is set, the alternate address will not be used */ 208 if (is_multicast_ether_addr(alt_mac_addr)) { 209 e_dbg("Ignoring Alternate Mac Address with MC bit set\n"); 210 return 0; 211 } 212 213 /* 214 * We have a valid alternate MAC address, and we want to treat it the 215 * same as the normal permanent MAC address stored by the HW into the 216 * RAR. Do this by mapping this address into RAR0. 217 */ 218 e1000e_rar_set(hw, alt_mac_addr, 0); 219 220 return 0; 221} 222 223/** 224 * e1000e_rar_set - Set receive address register 225 * @hw: pointer to the HW structure 226 * @addr: pointer to the receive address 227 * @index: receive address array register 228 * 229 * Sets the receive address array register at index to the address passed 230 * in by addr. 231 **/ 232void e1000e_rar_set(struct e1000_hw *hw, u8 *addr, u32 index) 233{ 234 u32 rar_low, rar_high; 235 236 /* 237 * HW expects these in little endian so we reverse the byte order 238 * from network order (big endian) to little endian 239 */ 240 rar_low = ((u32)addr[0] | ((u32)addr[1] << 8) | 241 ((u32)addr[2] << 16) | ((u32)addr[3] << 24)); 242 243 rar_high = ((u32)addr[4] | ((u32)addr[5] << 8)); 244 245 /* If MAC address zero, no need to set the AV bit */ 246 if (rar_low || rar_high) 247 rar_high |= E1000_RAH_AV; 248 249 /* 250 * Some bridges will combine consecutive 32-bit writes into 251 * a single burst write, which will malfunction on some parts. 252 * The flushes avoid this. 253 */ 254 ew32(RAL(index), rar_low); 255 e1e_flush(); 256 ew32(RAH(index), rar_high); 257 e1e_flush(); 258} 259 260/** 261 * e1000_hash_mc_addr - Generate a multicast hash value 262 * @hw: pointer to the HW structure 263 * @mc_addr: pointer to a multicast address 264 * 265 * Generates a multicast address hash value which is used to determine 266 * the multicast filter table array address and new table value. 267 **/ 268static u32 e1000_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr) 269{ 270 u32 hash_value, hash_mask; 271 u8 bit_shift = 0; 272 273 /* Register count multiplied by bits per register */ 274 hash_mask = (hw->mac.mta_reg_count * 32) - 1; 275 276 /* 277 * For a mc_filter_type of 0, bit_shift is the number of left-shifts 278 * where 0xFF would still fall within the hash mask. 279 */ 280 while (hash_mask >> bit_shift != 0xFF) 281 bit_shift++; 282 283 /* 284 * The portion of the address that is used for the hash table 285 * is determined by the mc_filter_type setting. 286 * The algorithm is such that there is a total of 8 bits of shifting. 287 * The bit_shift for a mc_filter_type of 0 represents the number of 288 * left-shifts where the MSB of mc_addr[5] would still fall within 289 * the hash_mask. Case 0 does this exactly. Since there are a total 290 * of 8 bits of shifting, then mc_addr[4] will shift right the 291 * remaining number of bits. Thus 8 - bit_shift. The rest of the 292 * cases are a variation of this algorithm...essentially raising the 293 * number of bits to shift mc_addr[5] left, while still keeping the 294 * 8-bit shifting total. 295 * 296 * For example, given the following Destination MAC Address and an 297 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask), 298 * we can see that the bit_shift for case 0 is 4. These are the hash 299 * values resulting from each mc_filter_type... 300 * [0] [1] [2] [3] [4] [5] 301 * 01 AA 00 12 34 56 302 * LSB MSB 303 * 304 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563 305 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6 306 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163 307 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634 308 */ 309 switch (hw->mac.mc_filter_type) { 310 default: 311 case 0: 312 break; 313 case 1: 314 bit_shift += 1; 315 break; 316 case 2: 317 bit_shift += 2; 318 break; 319 case 3: 320 bit_shift += 4; 321 break; 322 } 323 324 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) | 325 (((u16)mc_addr[5]) << bit_shift))); 326 327 return hash_value; 328} 329 330/** 331 * e1000e_update_mc_addr_list_generic - Update Multicast addresses 332 * @hw: pointer to the HW structure 333 * @mc_addr_list: array of multicast addresses to program 334 * @mc_addr_count: number of multicast addresses to program 335 * 336 * Updates entire Multicast Table Array. 337 * The caller must have a packed mc_addr_list of multicast addresses. 338 **/ 339void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw, 340 u8 *mc_addr_list, u32 mc_addr_count) 341{ 342 u32 hash_value, hash_bit, hash_reg; 343 int i; 344 345 /* clear mta_shadow */ 346 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow)); 347 348 /* update mta_shadow from mc_addr_list */ 349 for (i = 0; (u32)i < mc_addr_count; i++) { 350 hash_value = e1000_hash_mc_addr(hw, mc_addr_list); 351 352 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1); 353 hash_bit = hash_value & 0x1F; 354 355 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit); 356 mc_addr_list += (ETH_ALEN); 357 } 358 359 /* replace the entire MTA table */ 360 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) 361 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]); 362 e1e_flush(); 363} 364 365/** 366 * e1000e_clear_hw_cntrs_base - Clear base hardware counters 367 * @hw: pointer to the HW structure 368 * 369 * Clears the base hardware counters by reading the counter registers. 370 **/ 371void e1000e_clear_hw_cntrs_base(struct e1000_hw *hw) 372{ 373 er32(CRCERRS); 374 er32(SYMERRS); 375 er32(MPC); 376 er32(SCC); 377 er32(ECOL); 378 er32(MCC); 379 er32(LATECOL); 380 er32(COLC); 381 er32(DC); 382 er32(SEC); 383 er32(RLEC); 384 er32(XONRXC); 385 er32(XONTXC); 386 er32(XOFFRXC); 387 er32(XOFFTXC); 388 er32(FCRUC); 389 er32(GPRC); 390 er32(BPRC); 391 er32(MPRC); 392 er32(GPTC); 393 er32(GORCL); 394 er32(GORCH); 395 er32(GOTCL); 396 er32(GOTCH); 397 er32(RNBC); 398 er32(RUC); 399 er32(RFC); 400 er32(ROC); 401 er32(RJC); 402 er32(TORL); 403 er32(TORH); 404 er32(TOTL); 405 er32(TOTH); 406 er32(TPR); 407 er32(TPT); 408 er32(MPTC); 409 er32(BPTC); 410} 411 412/** 413 * e1000e_check_for_copper_link - Check for link (Copper) 414 * @hw: pointer to the HW structure 415 * 416 * Checks to see of the link status of the hardware has changed. If a 417 * change in link status has been detected, then we read the PHY registers 418 * to get the current speed/duplex if link exists. 419 **/ 420s32 e1000e_check_for_copper_link(struct e1000_hw *hw) 421{ 422 struct e1000_mac_info *mac = &hw->mac; 423 s32 ret_val; 424 bool link; 425 426 /* 427 * We only want to go out to the PHY registers to see if Auto-Neg 428 * has completed and/or if our link status has changed. The 429 * get_link_status flag is set upon receiving a Link Status 430 * Change or Rx Sequence Error interrupt. 431 */ 432 if (!mac->get_link_status) 433 return 0; 434 435 /* 436 * First we want to see if the MII Status Register reports 437 * link. If so, then we want to get the current speed/duplex 438 * of the PHY. 439 */ 440 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link); 441 if (ret_val) 442 return ret_val; 443 444 if (!link) 445 return 0; /* No link detected */ 446 447 mac->get_link_status = false; 448 449 /* 450 * Check if there was DownShift, must be checked 451 * immediately after link-up 452 */ 453 e1000e_check_downshift(hw); 454 455 /* 456 * If we are forcing speed/duplex, then we simply return since 457 * we have already determined whether we have link or not. 458 */ 459 if (!mac->autoneg) 460 return -E1000_ERR_CONFIG; 461 462 /* 463 * Auto-Neg is enabled. Auto Speed Detection takes care 464 * of MAC speed/duplex configuration. So we only need to 465 * configure Collision Distance in the MAC. 466 */ 467 mac->ops.config_collision_dist(hw); 468 469 /* 470 * Configure Flow Control now that Auto-Neg has completed. 471 * First, we need to restore the desired flow control 472 * settings because we may have had to re-autoneg with a 473 * different link partner. 474 */ 475 ret_val = e1000e_config_fc_after_link_up(hw); 476 if (ret_val) 477 e_dbg("Error configuring flow control\n"); 478 479 return ret_val; 480} 481 482/** 483 * e1000e_check_for_fiber_link - Check for link (Fiber) 484 * @hw: pointer to the HW structure 485 * 486 * Checks for link up on the hardware. If link is not up and we have 487 * a signal, then we need to force link up. 488 **/ 489s32 e1000e_check_for_fiber_link(struct e1000_hw *hw) 490{ 491 struct e1000_mac_info *mac = &hw->mac; 492 u32 rxcw; 493 u32 ctrl; 494 u32 status; 495 s32 ret_val; 496 497 ctrl = er32(CTRL); 498 status = er32(STATUS); 499 rxcw = er32(RXCW); 500 501 /* 502 * If we don't have link (auto-negotiation failed or link partner 503 * cannot auto-negotiate), the cable is plugged in (we have signal), 504 * and our link partner is not trying to auto-negotiate with us (we 505 * are receiving idles or data), we need to force link up. We also 506 * need to give auto-negotiation time to complete, in case the cable 507 * was just plugged in. The autoneg_failed flag does this. 508 */ 509 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 510 if ((ctrl & E1000_CTRL_SWDPIN1) && !(status & E1000_STATUS_LU) && 511 !(rxcw & E1000_RXCW_C)) { 512 if (!mac->autoneg_failed) { 513 mac->autoneg_failed = true; 514 return 0; 515 } 516 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 517 518 /* Disable auto-negotiation in the TXCW register */ 519 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 520 521 /* Force link-up and also force full-duplex. */ 522 ctrl = er32(CTRL); 523 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 524 ew32(CTRL, ctrl); 525 526 /* Configure Flow Control after forcing link up. */ 527 ret_val = e1000e_config_fc_after_link_up(hw); 528 if (ret_val) { 529 e_dbg("Error configuring flow control\n"); 530 return ret_val; 531 } 532 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 533 /* 534 * If we are forcing link and we are receiving /C/ ordered 535 * sets, re-enable auto-negotiation in the TXCW register 536 * and disable forced link in the Device Control register 537 * in an attempt to auto-negotiate with our link partner. 538 */ 539 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 540 ew32(TXCW, mac->txcw); 541 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 542 543 mac->serdes_has_link = true; 544 } 545 546 return 0; 547} 548 549/** 550 * e1000e_check_for_serdes_link - Check for link (Serdes) 551 * @hw: pointer to the HW structure 552 * 553 * Checks for link up on the hardware. If link is not up and we have 554 * a signal, then we need to force link up. 555 **/ 556s32 e1000e_check_for_serdes_link(struct e1000_hw *hw) 557{ 558 struct e1000_mac_info *mac = &hw->mac; 559 u32 rxcw; 560 u32 ctrl; 561 u32 status; 562 s32 ret_val; 563 564 ctrl = er32(CTRL); 565 status = er32(STATUS); 566 rxcw = er32(RXCW); 567 568 /* 569 * If we don't have link (auto-negotiation failed or link partner 570 * cannot auto-negotiate), and our link partner is not trying to 571 * auto-negotiate with us (we are receiving idles or data), 572 * we need to force link up. We also need to give auto-negotiation 573 * time to complete. 574 */ 575 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */ 576 if (!(status & E1000_STATUS_LU) && !(rxcw & E1000_RXCW_C)) { 577 if (!mac->autoneg_failed) { 578 mac->autoneg_failed = true; 579 return 0; 580 } 581 e_dbg("NOT Rx'ing /C/, disable AutoNeg and force link.\n"); 582 583 /* Disable auto-negotiation in the TXCW register */ 584 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE)); 585 586 /* Force link-up and also force full-duplex. */ 587 ctrl = er32(CTRL); 588 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); 589 ew32(CTRL, ctrl); 590 591 /* Configure Flow Control after forcing link up. */ 592 ret_val = e1000e_config_fc_after_link_up(hw); 593 if (ret_val) { 594 e_dbg("Error configuring flow control\n"); 595 return ret_val; 596 } 597 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { 598 /* 599 * If we are forcing link and we are receiving /C/ ordered 600 * sets, re-enable auto-negotiation in the TXCW register 601 * and disable forced link in the Device Control register 602 * in an attempt to auto-negotiate with our link partner. 603 */ 604 e_dbg("Rx'ing /C/, enable AutoNeg and stop forcing link.\n"); 605 ew32(TXCW, mac->txcw); 606 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU)); 607 608 mac->serdes_has_link = true; 609 } else if (!(E1000_TXCW_ANE & er32(TXCW))) { 610 /* 611 * If we force link for non-auto-negotiation switch, check 612 * link status based on MAC synchronization for internal 613 * serdes media type. 614 */ 615 /* SYNCH bit and IV bit are sticky. */ 616 udelay(10); 617 rxcw = er32(RXCW); 618 if (rxcw & E1000_RXCW_SYNCH) { 619 if (!(rxcw & E1000_RXCW_IV)) { 620 mac->serdes_has_link = true; 621 e_dbg("SERDES: Link up - forced.\n"); 622 } 623 } else { 624 mac->serdes_has_link = false; 625 e_dbg("SERDES: Link down - force failed.\n"); 626 } 627 } 628 629 if (E1000_TXCW_ANE & er32(TXCW)) { 630 status = er32(STATUS); 631 if (status & E1000_STATUS_LU) { 632 /* SYNCH bit and IV bit are sticky, so reread rxcw. */ 633 udelay(10); 634 rxcw = er32(RXCW); 635 if (rxcw & E1000_RXCW_SYNCH) { 636 if (!(rxcw & E1000_RXCW_IV)) { 637 mac->serdes_has_link = true; 638 e_dbg("SERDES: Link up - autoneg completed successfully.\n"); 639 } else { 640 mac->serdes_has_link = false; 641 e_dbg("SERDES: Link down - invalid codewords detected in autoneg.\n"); 642 } 643 } else { 644 mac->serdes_has_link = false; 645 e_dbg("SERDES: Link down - no sync.\n"); 646 } 647 } else { 648 mac->serdes_has_link = false; 649 e_dbg("SERDES: Link down - autoneg failed\n"); 650 } 651 } 652 653 return 0; 654} 655 656/** 657 * e1000_set_default_fc_generic - Set flow control default values 658 * @hw: pointer to the HW structure 659 * 660 * Read the EEPROM for the default values for flow control and store the 661 * values. 662 **/ 663static s32 e1000_set_default_fc_generic(struct e1000_hw *hw) 664{ 665 s32 ret_val; 666 u16 nvm_data; 667 668 /* 669 * Read and store word 0x0F of the EEPROM. This word contains bits 670 * that determine the hardware's default PAUSE (flow control) mode, 671 * a bit that determines whether the HW defaults to enabling or 672 * disabling auto-negotiation, and the direction of the 673 * SW defined pins. If there is no SW over-ride of the flow 674 * control setting, then the variable hw->fc will 675 * be initialized based on a value in the EEPROM. 676 */ 677 ret_val = e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data); 678 679 if (ret_val) { 680 e_dbg("NVM Read Error\n"); 681 return ret_val; 682 } 683 684 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0) 685 hw->fc.requested_mode = e1000_fc_none; 686 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR) 687 hw->fc.requested_mode = e1000_fc_tx_pause; 688 else 689 hw->fc.requested_mode = e1000_fc_full; 690 691 return 0; 692} 693 694/** 695 * e1000e_setup_link_generic - Setup flow control and link settings 696 * @hw: pointer to the HW structure 697 * 698 * Determines which flow control settings to use, then configures flow 699 * control. Calls the appropriate media-specific link configuration 700 * function. Assuming the adapter has a valid link partner, a valid link 701 * should be established. Assumes the hardware has previously been reset 702 * and the transmitter and receiver are not enabled. 703 **/ 704s32 e1000e_setup_link_generic(struct e1000_hw *hw) 705{ 706 struct e1000_mac_info *mac = &hw->mac; 707 s32 ret_val; 708 709 /* 710 * In the case of the phy reset being blocked, we already have a link. 711 * We do not need to set it up again. 712 */ 713 if (hw->phy.ops.check_reset_block(hw)) 714 return 0; 715 716 /* 717 * If requested flow control is set to default, set flow control 718 * based on the EEPROM flow control settings. 719 */ 720 if (hw->fc.requested_mode == e1000_fc_default) { 721 ret_val = e1000_set_default_fc_generic(hw); 722 if (ret_val) 723 return ret_val; 724 } 725 726 /* 727 * Save off the requested flow control mode for use later. Depending 728 * on the link partner's capabilities, we may or may not use this mode. 729 */ 730 hw->fc.current_mode = hw->fc.requested_mode; 731 732 e_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode); 733 734 /* Call the necessary media_type subroutine to configure the link. */ 735 ret_val = mac->ops.setup_physical_interface(hw); 736 if (ret_val) 737 return ret_val; 738 739 /* 740 * Initialize the flow control address, type, and PAUSE timer 741 * registers to their default values. This is done even if flow 742 * control is disabled, because it does not hurt anything to 743 * initialize these registers. 744 */ 745 e_dbg("Initializing the Flow Control address, type and timer regs\n"); 746 ew32(FCT, FLOW_CONTROL_TYPE); 747 ew32(FCAH, FLOW_CONTROL_ADDRESS_HIGH); 748 ew32(FCAL, FLOW_CONTROL_ADDRESS_LOW); 749 750 ew32(FCTTV, hw->fc.pause_time); 751 752 return e1000e_set_fc_watermarks(hw); 753} 754 755/** 756 * e1000_commit_fc_settings_generic - Configure flow control 757 * @hw: pointer to the HW structure 758 * 759 * Write the flow control settings to the Transmit Config Word Register (TXCW) 760 * base on the flow control settings in e1000_mac_info. 761 **/ 762static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw) 763{ 764 struct e1000_mac_info *mac = &hw->mac; 765 u32 txcw; 766 767 /* 768 * Check for a software override of the flow control settings, and 769 * setup the device accordingly. If auto-negotiation is enabled, then 770 * software will have to set the "PAUSE" bits to the correct value in 771 * the Transmit Config Word Register (TXCW) and re-start auto- 772 * negotiation. However, if auto-negotiation is disabled, then 773 * software will have to manually configure the two flow control enable 774 * bits in the CTRL register. 775 * 776 * The possible values of the "fc" parameter are: 777 * 0: Flow control is completely disabled 778 * 1: Rx flow control is enabled (we can receive pause frames, 779 * but not send pause frames). 780 * 2: Tx flow control is enabled (we can send pause frames but we 781 * do not support receiving pause frames). 782 * 3: Both Rx and Tx flow control (symmetric) are enabled. 783 */ 784 switch (hw->fc.current_mode) { 785 case e1000_fc_none: 786 /* Flow control completely disabled by a software over-ride. */ 787 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD); 788 break; 789 case e1000_fc_rx_pause: 790 /* 791 * Rx Flow control is enabled and Tx Flow control is disabled 792 * by a software over-ride. Since there really isn't a way to 793 * advertise that we are capable of Rx Pause ONLY, we will 794 * advertise that we support both symmetric and asymmetric Rx 795 * PAUSE. Later, we will disable the adapter's ability to send 796 * PAUSE frames. 797 */ 798 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 799 break; 800 case e1000_fc_tx_pause: 801 /* 802 * Tx Flow control is enabled, and Rx Flow control is disabled, 803 * by a software over-ride. 804 */ 805 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR); 806 break; 807 case e1000_fc_full: 808 /* 809 * Flow control (both Rx and Tx) is enabled by a software 810 * over-ride. 811 */ 812 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK); 813 break; 814 default: 815 e_dbg("Flow control param set incorrectly\n"); 816 return -E1000_ERR_CONFIG; 817 break; 818 } 819 820 ew32(TXCW, txcw); 821 mac->txcw = txcw; 822 823 return 0; 824} 825 826/** 827 * e1000_poll_fiber_serdes_link_generic - Poll for link up 828 * @hw: pointer to the HW structure 829 * 830 * Polls for link up by reading the status register, if link fails to come 831 * up with auto-negotiation, then the link is forced if a signal is detected. 832 **/ 833static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw) 834{ 835 struct e1000_mac_info *mac = &hw->mac; 836 u32 i, status; 837 s32 ret_val; 838 839 /* 840 * If we have a signal (the cable is plugged in, or assumed true for 841 * serdes media) then poll for a "Link-Up" indication in the Device 842 * Status Register. Time-out if a link isn't seen in 500 milliseconds 843 * seconds (Auto-negotiation should complete in less than 500 844 * milliseconds even if the other end is doing it in SW). 845 */ 846 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) { 847 usleep_range(10000, 20000); 848 status = er32(STATUS); 849 if (status & E1000_STATUS_LU) 850 break; 851 } 852 if (i == FIBER_LINK_UP_LIMIT) { 853 e_dbg("Never got a valid link from auto-neg!!!\n"); 854 mac->autoneg_failed = true; 855 /* 856 * AutoNeg failed to achieve a link, so we'll call 857 * mac->check_for_link. This routine will force the 858 * link up if we detect a signal. This will allow us to 859 * communicate with non-autonegotiating link partners. 860 */ 861 ret_val = mac->ops.check_for_link(hw); 862 if (ret_val) { 863 e_dbg("Error while checking for link\n"); 864 return ret_val; 865 } 866 mac->autoneg_failed = false; 867 } else { 868 mac->autoneg_failed = false; 869 e_dbg("Valid Link Found\n"); 870 } 871 872 return 0; 873} 874 875/** 876 * e1000e_setup_fiber_serdes_link - Setup link for fiber/serdes 877 * @hw: pointer to the HW structure 878 * 879 * Configures collision distance and flow control for fiber and serdes 880 * links. Upon successful setup, poll for link. 881 **/ 882s32 e1000e_setup_fiber_serdes_link(struct e1000_hw *hw) 883{ 884 u32 ctrl; 885 s32 ret_val; 886 887 ctrl = er32(CTRL); 888 889 /* Take the link out of reset */ 890 ctrl &= ~E1000_CTRL_LRST; 891 892 hw->mac.ops.config_collision_dist(hw); 893 894 ret_val = e1000_commit_fc_settings_generic(hw); 895 if (ret_val) 896 return ret_val; 897 898 /* 899 * Since auto-negotiation is enabled, take the link out of reset (the 900 * link will be in reset, because we previously reset the chip). This 901 * will restart auto-negotiation. If auto-negotiation is successful 902 * then the link-up status bit will be set and the flow control enable 903 * bits (RFCE and TFCE) will be set according to their negotiated value. 904 */ 905 e_dbg("Auto-negotiation enabled\n"); 906 907 ew32(CTRL, ctrl); 908 e1e_flush(); 909 usleep_range(1000, 2000); 910 911 /* 912 * For these adapters, the SW definable pin 1 is set when the optics 913 * detect a signal. If we have a signal, then poll for a "Link-Up" 914 * indication. 915 */ 916 if (hw->phy.media_type == e1000_media_type_internal_serdes || 917 (er32(CTRL) & E1000_CTRL_SWDPIN1)) { 918 ret_val = e1000_poll_fiber_serdes_link_generic(hw); 919 } else { 920 e_dbg("No signal detected\n"); 921 } 922 923 return ret_val; 924} 925 926/** 927 * e1000e_config_collision_dist_generic - Configure collision distance 928 * @hw: pointer to the HW structure 929 * 930 * Configures the collision distance to the default value and is used 931 * during link setup. 932 **/ 933void e1000e_config_collision_dist_generic(struct e1000_hw *hw) 934{ 935 u32 tctl; 936 937 tctl = er32(TCTL); 938 939 tctl &= ~E1000_TCTL_COLD; 940 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT; 941 942 ew32(TCTL, tctl); 943 e1e_flush(); 944} 945 946/** 947 * e1000e_set_fc_watermarks - Set flow control high/low watermarks 948 * @hw: pointer to the HW structure 949 * 950 * Sets the flow control high/low threshold (watermark) registers. If 951 * flow control XON frame transmission is enabled, then set XON frame 952 * transmission as well. 953 **/ 954s32 e1000e_set_fc_watermarks(struct e1000_hw *hw) 955{ 956 u32 fcrtl = 0, fcrth = 0; 957 958 /* 959 * Set the flow control receive threshold registers. Normally, 960 * these registers will be set to a default threshold that may be 961 * adjusted later by the driver's runtime code. However, if the 962 * ability to transmit pause frames is not enabled, then these 963 * registers will be set to 0. 964 */ 965 if (hw->fc.current_mode & e1000_fc_tx_pause) { 966 /* 967 * We need to set up the Receive Threshold high and low water 968 * marks as well as (optionally) enabling the transmission of 969 * XON frames. 970 */ 971 fcrtl = hw->fc.low_water; 972 if (hw->fc.send_xon) 973 fcrtl |= E1000_FCRTL_XONE; 974 975 fcrth = hw->fc.high_water; 976 } 977 ew32(FCRTL, fcrtl); 978 ew32(FCRTH, fcrth); 979 980 return 0; 981} 982 983/** 984 * e1000e_force_mac_fc - Force the MAC's flow control settings 985 * @hw: pointer to the HW structure 986 * 987 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the 988 * device control register to reflect the adapter settings. TFCE and RFCE 989 * need to be explicitly set by software when a copper PHY is used because 990 * autonegotiation is managed by the PHY rather than the MAC. Software must 991 * also configure these bits when link is forced on a fiber connection. 992 **/ 993s32 e1000e_force_mac_fc(struct e1000_hw *hw) 994{ 995 u32 ctrl; 996 997 ctrl = er32(CTRL); 998 999 /* 1000 * Because we didn't get link via the internal auto-negotiation 1001 * mechanism (we either forced link or we got link via PHY 1002 * auto-neg), we have to manually enable/disable transmit an 1003 * receive flow control. 1004 * 1005 * The "Case" statement below enables/disable flow control 1006 * according to the "hw->fc.current_mode" parameter. 1007 * 1008 * The possible values of the "fc" parameter are: 1009 * 0: Flow control is completely disabled 1010 * 1: Rx flow control is enabled (we can receive pause 1011 * frames but not send pause frames). 1012 * 2: Tx flow control is enabled (we can send pause frames 1013 * frames but we do not receive pause frames). 1014 * 3: Both Rx and Tx flow control (symmetric) is enabled. 1015 * other: No other values should be possible at this point. 1016 */ 1017 e_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode); 1018 1019 switch (hw->fc.current_mode) { 1020 case e1000_fc_none: 1021 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); 1022 break; 1023 case e1000_fc_rx_pause: 1024 ctrl &= (~E1000_CTRL_TFCE); 1025 ctrl |= E1000_CTRL_RFCE; 1026 break; 1027 case e1000_fc_tx_pause: 1028 ctrl &= (~E1000_CTRL_RFCE); 1029 ctrl |= E1000_CTRL_TFCE; 1030 break; 1031 case e1000_fc_full: 1032 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); 1033 break; 1034 default: 1035 e_dbg("Flow control param set incorrectly\n"); 1036 return -E1000_ERR_CONFIG; 1037 } 1038 1039 ew32(CTRL, ctrl); 1040 1041 return 0; 1042} 1043 1044/** 1045 * e1000e_config_fc_after_link_up - Configures flow control after link 1046 * @hw: pointer to the HW structure 1047 * 1048 * Checks the status of auto-negotiation after link up to ensure that the 1049 * speed and duplex were not forced. If the link needed to be forced, then 1050 * flow control needs to be forced also. If auto-negotiation is enabled 1051 * and did not fail, then we configure flow control based on our link 1052 * partner. 1053 **/ 1054s32 e1000e_config_fc_after_link_up(struct e1000_hw *hw) 1055{ 1056 struct e1000_mac_info *mac = &hw->mac; 1057 s32 ret_val = 0; 1058 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg; 1059 u16 speed, duplex; 1060 1061 /* 1062 * Check for the case where we have fiber media and auto-neg failed 1063 * so we had to force link. In this case, we need to force the 1064 * configuration of the MAC to match the "fc" parameter. 1065 */ 1066 if (mac->autoneg_failed) { 1067 if (hw->phy.media_type == e1000_media_type_fiber || 1068 hw->phy.media_type == e1000_media_type_internal_serdes) 1069 ret_val = e1000e_force_mac_fc(hw); 1070 } else { 1071 if (hw->phy.media_type == e1000_media_type_copper) 1072 ret_val = e1000e_force_mac_fc(hw); 1073 } 1074 1075 if (ret_val) { 1076 e_dbg("Error forcing flow control settings\n"); 1077 return ret_val; 1078 } 1079 1080 /* 1081 * Check for the case where we have copper media and auto-neg is 1082 * enabled. In this case, we need to check and see if Auto-Neg 1083 * has completed, and if so, how the PHY and link partner has 1084 * flow control configured. 1085 */ 1086 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) { 1087 /* 1088 * Read the MII Status Register and check to see if AutoNeg 1089 * has completed. We read this twice because this reg has 1090 * some "sticky" (latched) bits. 1091 */ 1092 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); 1093 if (ret_val) 1094 return ret_val; 1095 ret_val = e1e_rphy(hw, PHY_STATUS, &mii_status_reg); 1096 if (ret_val) 1097 return ret_val; 1098 1099 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) { 1100 e_dbg("Copper PHY and Auto Neg has not completed.\n"); 1101 return ret_val; 1102 } 1103 1104 /* 1105 * The AutoNeg process has completed, so we now need to 1106 * read both the Auto Negotiation Advertisement 1107 * Register (Address 4) and the Auto_Negotiation Base 1108 * Page Ability Register (Address 5) to determine how 1109 * flow control was negotiated. 1110 */ 1111 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_nway_adv_reg); 1112 if (ret_val) 1113 return ret_val; 1114 ret_val = 1115 e1e_rphy(hw, PHY_LP_ABILITY, &mii_nway_lp_ability_reg); 1116 if (ret_val) 1117 return ret_val; 1118 1119 /* 1120 * Two bits in the Auto Negotiation Advertisement Register 1121 * (Address 4) and two bits in the Auto Negotiation Base 1122 * Page Ability Register (Address 5) determine flow control 1123 * for both the PHY and the link partner. The following 1124 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25, 1125 * 1999, describes these PAUSE resolution bits and how flow 1126 * control is determined based upon these settings. 1127 * NOTE: DC = Don't Care 1128 * 1129 * LOCAL DEVICE | LINK PARTNER 1130 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution 1131 *-------|---------|-------|---------|-------------------- 1132 * 0 | 0 | DC | DC | e1000_fc_none 1133 * 0 | 1 | 0 | DC | e1000_fc_none 1134 * 0 | 1 | 1 | 0 | e1000_fc_none 1135 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1136 * 1 | 0 | 0 | DC | e1000_fc_none 1137 * 1 | DC | 1 | DC | e1000_fc_full 1138 * 1 | 1 | 0 | 0 | e1000_fc_none 1139 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1140 * 1141 * Are both PAUSE bits set to 1? If so, this implies 1142 * Symmetric Flow Control is enabled at both ends. The 1143 * ASM_DIR bits are irrelevant per the spec. 1144 * 1145 * For Symmetric Flow Control: 1146 * 1147 * LOCAL DEVICE | LINK PARTNER 1148 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1149 *-------|---------|-------|---------|-------------------- 1150 * 1 | DC | 1 | DC | E1000_fc_full 1151 * 1152 */ 1153 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1154 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) { 1155 /* 1156 * Now we need to check if the user selected Rx ONLY 1157 * of pause frames. In this case, we had to advertise 1158 * FULL flow control because we could not advertise Rx 1159 * ONLY. Hence, we must now check to see if we need to 1160 * turn OFF the TRANSMISSION of PAUSE frames. 1161 */ 1162 if (hw->fc.requested_mode == e1000_fc_full) { 1163 hw->fc.current_mode = e1000_fc_full; 1164 e_dbg("Flow Control = FULL.\n"); 1165 } else { 1166 hw->fc.current_mode = e1000_fc_rx_pause; 1167 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1168 } 1169 } 1170 /* 1171 * For receiving PAUSE frames ONLY. 1172 * 1173 * LOCAL DEVICE | LINK PARTNER 1174 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1175 *-------|---------|-------|---------|-------------------- 1176 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause 1177 */ 1178 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) && 1179 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1180 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1181 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1182 hw->fc.current_mode = e1000_fc_tx_pause; 1183 e_dbg("Flow Control = Tx PAUSE frames only.\n"); 1184 } 1185 /* 1186 * For transmitting PAUSE frames ONLY. 1187 * 1188 * LOCAL DEVICE | LINK PARTNER 1189 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result 1190 *-------|---------|-------|---------|-------------------- 1191 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause 1192 */ 1193 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) && 1194 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) && 1195 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) && 1196 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) { 1197 hw->fc.current_mode = e1000_fc_rx_pause; 1198 e_dbg("Flow Control = Rx PAUSE frames only.\n"); 1199 } else { 1200 /* 1201 * Per the IEEE spec, at this point flow control 1202 * should be disabled. 1203 */ 1204 hw->fc.current_mode = e1000_fc_none; 1205 e_dbg("Flow Control = NONE.\n"); 1206 } 1207 1208 /* 1209 * Now we need to do one last check... If we auto- 1210 * negotiated to HALF DUPLEX, flow control should not be 1211 * enabled per IEEE 802.3 spec. 1212 */ 1213 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex); 1214 if (ret_val) { 1215 e_dbg("Error getting link speed and duplex\n"); 1216 return ret_val; 1217 } 1218 1219 if (duplex == HALF_DUPLEX) 1220 hw->fc.current_mode = e1000_fc_none; 1221 1222 /* 1223 * Now we call a subroutine to actually force the MAC 1224 * controller to use the correct flow control settings. 1225 */ 1226 ret_val = e1000e_force_mac_fc(hw); 1227 if (ret_val) { 1228 e_dbg("Error forcing flow control settings\n"); 1229 return ret_val; 1230 } 1231 } 1232 1233 return 0; 1234} 1235 1236/** 1237 * e1000e_get_speed_and_duplex_copper - Retrieve current speed/duplex 1238 * @hw: pointer to the HW structure 1239 * @speed: stores the current speed 1240 * @duplex: stores the current duplex 1241 * 1242 * Read the status register for the current speed/duplex and store the current 1243 * speed and duplex for copper connections. 1244 **/ 1245s32 e1000e_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed, 1246 u16 *duplex) 1247{ 1248 u32 status; 1249 1250 status = er32(STATUS); 1251 if (status & E1000_STATUS_SPEED_1000) 1252 *speed = SPEED_1000; 1253 else if (status & E1000_STATUS_SPEED_100) 1254 *speed = SPEED_100; 1255 else 1256 *speed = SPEED_10; 1257 1258 if (status & E1000_STATUS_FD) 1259 *duplex = FULL_DUPLEX; 1260 else 1261 *duplex = HALF_DUPLEX; 1262 1263 e_dbg("%u Mbps, %s Duplex\n", 1264 *speed == SPEED_1000 ? 1000 : *speed == SPEED_100 ? 100 : 10, 1265 *duplex == FULL_DUPLEX ? "Full" : "Half"); 1266 1267 return 0; 1268} 1269 1270/** 1271 * e1000e_get_speed_and_duplex_fiber_serdes - Retrieve current speed/duplex 1272 * @hw: pointer to the HW structure 1273 * @speed: stores the current speed 1274 * @duplex: stores the current duplex 1275 * 1276 * Sets the speed and duplex to gigabit full duplex (the only possible option) 1277 * for fiber/serdes links. 1278 **/ 1279s32 e1000e_get_speed_and_duplex_fiber_serdes(struct e1000_hw *hw, u16 *speed, 1280 u16 *duplex) 1281{ 1282 *speed = SPEED_1000; 1283 *duplex = FULL_DUPLEX; 1284 1285 return 0; 1286} 1287 1288/** 1289 * e1000e_get_hw_semaphore - Acquire hardware semaphore 1290 * @hw: pointer to the HW structure 1291 * 1292 * Acquire the HW semaphore to access the PHY or NVM 1293 **/ 1294s32 e1000e_get_hw_semaphore(struct e1000_hw *hw) 1295{ 1296 u32 swsm; 1297 s32 timeout = hw->nvm.word_size + 1; 1298 s32 i = 0; 1299 1300 /* Get the SW semaphore */ 1301 while (i < timeout) { 1302 swsm = er32(SWSM); 1303 if (!(swsm & E1000_SWSM_SMBI)) 1304 break; 1305 1306 udelay(50); 1307 i++; 1308 } 1309 1310 if (i == timeout) { 1311 e_dbg("Driver can't access device - SMBI bit is set.\n"); 1312 return -E1000_ERR_NVM; 1313 } 1314 1315 /* Get the FW semaphore. */ 1316 for (i = 0; i < timeout; i++) { 1317 swsm = er32(SWSM); 1318 ew32(SWSM, swsm | E1000_SWSM_SWESMBI); 1319 1320 /* Semaphore acquired if bit latched */ 1321 if (er32(SWSM) & E1000_SWSM_SWESMBI) 1322 break; 1323 1324 udelay(50); 1325 } 1326 1327 if (i == timeout) { 1328 /* Release semaphores */ 1329 e1000e_put_hw_semaphore(hw); 1330 e_dbg("Driver can't access the NVM\n"); 1331 return -E1000_ERR_NVM; 1332 } 1333 1334 return 0; 1335} 1336 1337/** 1338 * e1000e_put_hw_semaphore - Release hardware semaphore 1339 * @hw: pointer to the HW structure 1340 * 1341 * Release hardware semaphore used to access the PHY or NVM 1342 **/ 1343void e1000e_put_hw_semaphore(struct e1000_hw *hw) 1344{ 1345 u32 swsm; 1346 1347 swsm = er32(SWSM); 1348 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI); 1349 ew32(SWSM, swsm); 1350} 1351 1352/** 1353 * e1000e_get_auto_rd_done - Check for auto read completion 1354 * @hw: pointer to the HW structure 1355 * 1356 * Check EEPROM for Auto Read done bit. 1357 **/ 1358s32 e1000e_get_auto_rd_done(struct e1000_hw *hw) 1359{ 1360 s32 i = 0; 1361 1362 while (i < AUTO_READ_DONE_TIMEOUT) { 1363 if (er32(EECD) & E1000_EECD_AUTO_RD) 1364 break; 1365 usleep_range(1000, 2000); 1366 i++; 1367 } 1368 1369 if (i == AUTO_READ_DONE_TIMEOUT) { 1370 e_dbg("Auto read by HW from NVM has not completed.\n"); 1371 return -E1000_ERR_RESET; 1372 } 1373 1374 return 0; 1375} 1376 1377/** 1378 * e1000e_valid_led_default - Verify a valid default LED config 1379 * @hw: pointer to the HW structure 1380 * @data: pointer to the NVM (EEPROM) 1381 * 1382 * Read the EEPROM for the current default LED configuration. If the 1383 * LED configuration is not valid, set to a valid LED configuration. 1384 **/ 1385s32 e1000e_valid_led_default(struct e1000_hw *hw, u16 *data) 1386{ 1387 s32 ret_val; 1388 1389 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data); 1390 if (ret_val) { 1391 e_dbg("NVM Read Error\n"); 1392 return ret_val; 1393 } 1394 1395 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) 1396 *data = ID_LED_DEFAULT; 1397 1398 return 0; 1399} 1400 1401/** 1402 * e1000e_id_led_init_generic - 1403 * @hw: pointer to the HW structure 1404 * 1405 **/ 1406s32 e1000e_id_led_init_generic(struct e1000_hw *hw) 1407{ 1408 struct e1000_mac_info *mac = &hw->mac; 1409 s32 ret_val; 1410 const u32 ledctl_mask = 0x000000FF; 1411 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON; 1412 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF; 1413 u16 data, i, temp; 1414 const u16 led_mask = 0x0F; 1415 1416 ret_val = hw->nvm.ops.valid_led_default(hw, &data); 1417 if (ret_val) 1418 return ret_val; 1419 1420 mac->ledctl_default = er32(LEDCTL); 1421 mac->ledctl_mode1 = mac->ledctl_default; 1422 mac->ledctl_mode2 = mac->ledctl_default; 1423 1424 for (i = 0; i < 4; i++) { 1425 temp = (data >> (i << 2)) & led_mask; 1426 switch (temp) { 1427 case ID_LED_ON1_DEF2: 1428 case ID_LED_ON1_ON2: 1429 case ID_LED_ON1_OFF2: 1430 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1431 mac->ledctl_mode1 |= ledctl_on << (i << 3); 1432 break; 1433 case ID_LED_OFF1_DEF2: 1434 case ID_LED_OFF1_ON2: 1435 case ID_LED_OFF1_OFF2: 1436 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3)); 1437 mac->ledctl_mode1 |= ledctl_off << (i << 3); 1438 break; 1439 default: 1440 /* Do nothing */ 1441 break; 1442 } 1443 switch (temp) { 1444 case ID_LED_DEF1_ON2: 1445 case ID_LED_ON1_ON2: 1446 case ID_LED_OFF1_ON2: 1447 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1448 mac->ledctl_mode2 |= ledctl_on << (i << 3); 1449 break; 1450 case ID_LED_DEF1_OFF2: 1451 case ID_LED_ON1_OFF2: 1452 case ID_LED_OFF1_OFF2: 1453 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3)); 1454 mac->ledctl_mode2 |= ledctl_off << (i << 3); 1455 break; 1456 default: 1457 /* Do nothing */ 1458 break; 1459 } 1460 } 1461 1462 return 0; 1463} 1464 1465/** 1466 * e1000e_setup_led_generic - Configures SW controllable LED 1467 * @hw: pointer to the HW structure 1468 * 1469 * This prepares the SW controllable LED for use and saves the current state 1470 * of the LED so it can be later restored. 1471 **/ 1472s32 e1000e_setup_led_generic(struct e1000_hw *hw) 1473{ 1474 u32 ledctl; 1475 1476 if (hw->mac.ops.setup_led != e1000e_setup_led_generic) 1477 return -E1000_ERR_CONFIG; 1478 1479 if (hw->phy.media_type == e1000_media_type_fiber) { 1480 ledctl = er32(LEDCTL); 1481 hw->mac.ledctl_default = ledctl; 1482 /* Turn off LED0 */ 1483 ledctl &= ~(E1000_LEDCTL_LED0_IVRT | E1000_LEDCTL_LED0_BLINK | 1484 E1000_LEDCTL_LED0_MODE_MASK); 1485 ledctl |= (E1000_LEDCTL_MODE_LED_OFF << 1486 E1000_LEDCTL_LED0_MODE_SHIFT); 1487 ew32(LEDCTL, ledctl); 1488 } else if (hw->phy.media_type == e1000_media_type_copper) { 1489 ew32(LEDCTL, hw->mac.ledctl_mode1); 1490 } 1491 1492 return 0; 1493} 1494 1495/** 1496 * e1000e_cleanup_led_generic - Set LED config to default operation 1497 * @hw: pointer to the HW structure 1498 * 1499 * Remove the current LED configuration and set the LED configuration 1500 * to the default value, saved from the EEPROM. 1501 **/ 1502s32 e1000e_cleanup_led_generic(struct e1000_hw *hw) 1503{ 1504 ew32(LEDCTL, hw->mac.ledctl_default); 1505 return 0; 1506} 1507 1508/** 1509 * e1000e_blink_led_generic - Blink LED 1510 * @hw: pointer to the HW structure 1511 * 1512 * Blink the LEDs which are set to be on. 1513 **/ 1514s32 e1000e_blink_led_generic(struct e1000_hw *hw) 1515{ 1516 u32 ledctl_blink = 0; 1517 u32 i; 1518 1519 if (hw->phy.media_type == e1000_media_type_fiber) { 1520 /* always blink LED0 for PCI-E fiber */ 1521 ledctl_blink = E1000_LEDCTL_LED0_BLINK | 1522 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT); 1523 } else { 1524 /* 1525 * set the blink bit for each LED that's "on" (0x0E) 1526 * in ledctl_mode2 1527 */ 1528 ledctl_blink = hw->mac.ledctl_mode2; 1529 for (i = 0; i < 4; i++) 1530 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) == 1531 E1000_LEDCTL_MODE_LED_ON) 1532 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK << 1533 (i * 8)); 1534 } 1535 1536 ew32(LEDCTL, ledctl_blink); 1537 1538 return 0; 1539} 1540 1541/** 1542 * e1000e_led_on_generic - Turn LED on 1543 * @hw: pointer to the HW structure 1544 * 1545 * Turn LED on. 1546 **/ 1547s32 e1000e_led_on_generic(struct e1000_hw *hw) 1548{ 1549 u32 ctrl; 1550 1551 switch (hw->phy.media_type) { 1552 case e1000_media_type_fiber: 1553 ctrl = er32(CTRL); 1554 ctrl &= ~E1000_CTRL_SWDPIN0; 1555 ctrl |= E1000_CTRL_SWDPIO0; 1556 ew32(CTRL, ctrl); 1557 break; 1558 case e1000_media_type_copper: 1559 ew32(LEDCTL, hw->mac.ledctl_mode2); 1560 break; 1561 default: 1562 break; 1563 } 1564 1565 return 0; 1566} 1567 1568/** 1569 * e1000e_led_off_generic - Turn LED off 1570 * @hw: pointer to the HW structure 1571 * 1572 * Turn LED off. 1573 **/ 1574s32 e1000e_led_off_generic(struct e1000_hw *hw) 1575{ 1576 u32 ctrl; 1577 1578 switch (hw->phy.media_type) { 1579 case e1000_media_type_fiber: 1580 ctrl = er32(CTRL); 1581 ctrl |= E1000_CTRL_SWDPIN0; 1582 ctrl |= E1000_CTRL_SWDPIO0; 1583 ew32(CTRL, ctrl); 1584 break; 1585 case e1000_media_type_copper: 1586 ew32(LEDCTL, hw->mac.ledctl_mode1); 1587 break; 1588 default: 1589 break; 1590 } 1591 1592 return 0; 1593} 1594 1595/** 1596 * e1000e_set_pcie_no_snoop - Set PCI-express capabilities 1597 * @hw: pointer to the HW structure 1598 * @no_snoop: bitmap of snoop events 1599 * 1600 * Set the PCI-express register to snoop for events enabled in 'no_snoop'. 1601 **/ 1602void e1000e_set_pcie_no_snoop(struct e1000_hw *hw, u32 no_snoop) 1603{ 1604 u32 gcr; 1605 1606 if (no_snoop) { 1607 gcr = er32(GCR); 1608 gcr &= ~(PCIE_NO_SNOOP_ALL); 1609 gcr |= no_snoop; 1610 ew32(GCR, gcr); 1611 } 1612} 1613 1614/** 1615 * e1000e_disable_pcie_master - Disables PCI-express master access 1616 * @hw: pointer to the HW structure 1617 * 1618 * Returns 0 if successful, else returns -10 1619 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused 1620 * the master requests to be disabled. 1621 * 1622 * Disables PCI-Express master access and verifies there are no pending 1623 * requests. 1624 **/ 1625s32 e1000e_disable_pcie_master(struct e1000_hw *hw) 1626{ 1627 u32 ctrl; 1628 s32 timeout = MASTER_DISABLE_TIMEOUT; 1629 1630 ctrl = er32(CTRL); 1631 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE; 1632 ew32(CTRL, ctrl); 1633 1634 while (timeout) { 1635 if (!(er32(STATUS) & E1000_STATUS_GIO_MASTER_ENABLE)) 1636 break; 1637 udelay(100); 1638 timeout--; 1639 } 1640 1641 if (!timeout) { 1642 e_dbg("Master requests are pending.\n"); 1643 return -E1000_ERR_MASTER_REQUESTS_PENDING; 1644 } 1645 1646 return 0; 1647} 1648 1649/** 1650 * e1000e_reset_adaptive - Reset Adaptive Interframe Spacing 1651 * @hw: pointer to the HW structure 1652 * 1653 * Reset the Adaptive Interframe Spacing throttle to default values. 1654 **/ 1655void e1000e_reset_adaptive(struct e1000_hw *hw) 1656{ 1657 struct e1000_mac_info *mac = &hw->mac; 1658 1659 if (!mac->adaptive_ifs) { 1660 e_dbg("Not in Adaptive IFS mode!\n"); 1661 return; 1662 } 1663 1664 mac->current_ifs_val = 0; 1665 mac->ifs_min_val = IFS_MIN; 1666 mac->ifs_max_val = IFS_MAX; 1667 mac->ifs_step_size = IFS_STEP; 1668 mac->ifs_ratio = IFS_RATIO; 1669 1670 mac->in_ifs_mode = false; 1671 ew32(AIT, 0); 1672} 1673 1674/** 1675 * e1000e_update_adaptive - Update Adaptive Interframe Spacing 1676 * @hw: pointer to the HW structure 1677 * 1678 * Update the Adaptive Interframe Spacing Throttle value based on the 1679 * time between transmitted packets and time between collisions. 1680 **/ 1681void e1000e_update_adaptive(struct e1000_hw *hw) 1682{ 1683 struct e1000_mac_info *mac = &hw->mac; 1684 1685 if (!mac->adaptive_ifs) { 1686 e_dbg("Not in Adaptive IFS mode!\n"); 1687 return; 1688 } 1689 1690 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) { 1691 if (mac->tx_packet_delta > MIN_NUM_XMITS) { 1692 mac->in_ifs_mode = true; 1693 if (mac->current_ifs_val < mac->ifs_max_val) { 1694 if (!mac->current_ifs_val) 1695 mac->current_ifs_val = mac->ifs_min_val; 1696 else 1697 mac->current_ifs_val += 1698 mac->ifs_step_size; 1699 ew32(AIT, mac->current_ifs_val); 1700 } 1701 } 1702 } else { 1703 if (mac->in_ifs_mode && 1704 (mac->tx_packet_delta <= MIN_NUM_XMITS)) { 1705 mac->current_ifs_val = 0; 1706 mac->in_ifs_mode = false; 1707 ew32(AIT, 0); 1708 } 1709 } 1710} 1711