1e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman/* Intel PRO/1000 Linux driver 2e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * Copyright(c) 1999 - 2014 Intel Corporation. 3e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * 4e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * This program is free software; you can redistribute it and/or modify it 5e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * under the terms and conditions of the GNU General Public License, 6e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * version 2, as published by the Free Software Foundation. 7e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * 8e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * This program is distributed in the hope it will be useful, but WITHOUT 9e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * more details. 12e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * 13e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * The full GNU General Public License is included in this distribution in 14e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * the file called "COPYING". 15e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * 16e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * Contact Information: 17e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * Linux NICS <linux.nics@intel.com> 18e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 19e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 20e78b80b1079e1269ca57c28abda790555b546a5fDavid Ertman */ 2193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 2293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#ifndef _E1000E_PHY_H_ 2393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define _E1000E_PHY_H_ 2493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 2593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_check_downshift(struct e1000_hw *hw); 2693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_check_polarity_m88(struct e1000_hw *hw); 2793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_check_polarity_igp(struct e1000_hw *hw); 2893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_check_polarity_ife(struct e1000_hw *hw); 2993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_check_reset_block_generic(struct e1000_hw *hw); 3093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_copper_link_setup_igp(struct e1000_hw *hw); 3193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_copper_link_setup_m88(struct e1000_hw *hw); 3293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw); 3393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw); 3493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw); 3593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_get_cable_length_m88(struct e1000_hw *hw); 3693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw); 3793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_get_cfg_done_generic(struct e1000_hw *hw); 3893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_get_phy_id(struct e1000_hw *hw); 3993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_get_phy_info_igp(struct e1000_hw *hw); 4093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_get_phy_info_m88(struct e1000_hw *hw); 4193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_get_phy_info_ife(struct e1000_hw *hw); 4293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_phy_sw_reset(struct e1000_hw *hw); 4393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allanvoid e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl); 4493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw); 4593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_phy_reset_dsp(struct e1000_hw *hw); 4693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data); 4793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data); 4893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_set_page_igp(struct e1000_hw *hw, u16 page); 4993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data); 5093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data); 5193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data); 5293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active); 5393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_setup_copper_link(struct e1000_hw *hw); 5493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data); 5593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data); 5693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data); 5793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data); 5893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data); 5993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations, 6093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan u32 usec_interval, bool *success); 6193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_phy_init_script_igp3(struct e1000_hw *hw); 6293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allanenum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id); 6393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_determine_phy_address(struct e1000_hw *hw); 6493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_write_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 data); 6593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_read_phy_reg_bm(struct e1000_hw *hw, u32 offset, u16 *data); 6693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); 6793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg); 6893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_read_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 *data); 6993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_write_phy_reg_bm2(struct e1000_hw *hw, u32 offset, u16 data); 7093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allanvoid e1000_power_up_phy_copper(struct e1000_hw *hw); 7193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allanvoid e1000_power_down_phy_copper(struct e1000_hw *hw); 7293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); 7393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000e_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); 7493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_read_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 *data); 7593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_read_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 *data); 7693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_read_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 *data); 7793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_write_phy_reg_hv(struct e1000_hw *hw, u32 offset, u16 data); 7893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_write_phy_reg_hv_locked(struct e1000_hw *hw, u32 offset, u16 data); 7993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_write_phy_reg_page_hv(struct e1000_hw *hw, u32 offset, u16 data); 8093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_link_stall_workaround_hv(struct e1000_hw *hw); 8193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_copper_link_setup_82577(struct e1000_hw *hw); 8293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_check_polarity_82577(struct e1000_hw *hw); 8393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_get_phy_info_82577(struct e1000_hw *hw); 8493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw); 8593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allans32 e1000_get_cable_length_82577(struct e1000_hw *hw); 8693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 8793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define E1000_MAX_PHY_ADDR 8 8893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 8993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan/* IGP01E1000 Specific Registers */ 9093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* Port Config */ 9193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PHY_PORT_STATUS 0x11 /* Status */ 9293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PHY_PORT_CTRL 0x12 /* Control */ 9393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health */ 9493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP02E1000_PHY_POWER_MGMT 0x19 /* Power Management */ 9593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* Page Select */ 9693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 9793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP_PAGE_SHIFT 5 9893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define PHY_REG_MASK 0x1F 9993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 10093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan/* BM/HV Specific Registers */ 10193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_PORT_CTRL_PAGE 769 10293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_WUC_PAGE 800 10393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_WUC_ADDRESS_OPCODE 0x11 10493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_WUC_DATA_OPCODE 0x12 10593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE 10693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_WUC_ENABLE_REG 17 10793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_WUC_ENABLE_BIT (1 << 2) 10893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_WUC_HOST_WU_BIT (1 << 4) 10993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_WUC_ME_WU_BIT (1 << 5) 11093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 11193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define PHY_UPPER_SHIFT 21 11293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_PHY_REG(page, reg) \ 11393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan (((reg) & MAX_PHY_REG_ADDRESS) |\ 11493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ 11593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) 11693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_PHY_REG_PAGE(offset) \ 11793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan ((u16)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) 11893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_PHY_REG_NUM(offset) \ 11993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan ((u16)(((offset) & MAX_PHY_REG_ADDRESS) |\ 12093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ 12193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan ~MAX_PHY_REG_ADDRESS))) 12293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 12393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define HV_INTC_FC_PAGE_START 768 12493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82578_ADDR_REG 29 12593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_ADDR_REG 16 12693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_CFG_REG 22 12793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_CFG_ASSERT_CRS_ON_TX (1 << 15) 12893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift */ 12993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_CTRL_REG 23 13093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 13193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan/* 82577 specific PHY registers */ 13293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_PHY_CTRL_2 18 13393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_PHY_LBK_CTRL 19 13493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_PHY_STATUS_2 26 13593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_PHY_DIAG_STATUS 31 13693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 13793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan/* I82577 PHY Status 2 */ 13893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_PHY_STATUS2_REV_POLARITY 0x0400 13993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_PHY_STATUS2_MDIX 0x0800 14093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_PHY_STATUS2_SPEED_MASK 0x0300 14193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_PHY_STATUS2_SPEED_1000MBPS 0x0200 14293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 14393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan/* I82577 PHY Control 2 */ 14493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_PHY_CTRL2_MANUAL_MDIX 0x0200 14593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_PHY_CTRL2_AUTO_MDI_MDIX 0x0400 14693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_PHY_CTRL2_MDIX_CFG_MASK 0x0600 14793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 14893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan/* I82577 PHY Diagnostics Status */ 14993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_DSTATUS_CABLE_LENGTH 0x03FC 15093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define I82577_DSTATUS_CABLE_LENGTH_SHIFT 2 15193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 15293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan/* BM PHY Copper Specific Control 1 */ 15393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_CS_CTRL1 16 15493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 15593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan/* BM PHY Copper Specific Status */ 15693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_CS_STATUS 17 15793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_CS_STATUS_LINK_UP 0x0400 15893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_CS_STATUS_RESOLVED 0x0800 15993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_CS_STATUS_SPEED_MASK 0xC000 16093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define BM_CS_STATUS_SPEED_1000 0x8000 16193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 16293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan/* 82577 Mobile Phy Status Register */ 16393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define HV_M_STATUS 26 16493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 16593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define HV_M_STATUS_SPEED_MASK 0x0300 16693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define HV_M_STATUS_SPEED_1000 0x0200 16777e61146c67765deae45faa7db088c64a9fbca00David Ertman#define HV_M_STATUS_SPEED_100 0x0100 16893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define HV_M_STATUS_LINK_UP 0x0040 16993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 17093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 17193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PHY_POLARITY_MASK 0x0078 17293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 17393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PSCR_AUTO_MDIX 0x1000 17493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0=MDI, 1=MDIX */ 17593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 17693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PSCFR_SMART_SPEED 0x0080 17793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 17893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 17993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP02E1000_PM_D0_LPLU 0x0002 /* For D0a states */ 18093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP02E1000_PM_D3_LPLU 0x0004 /* For all other states */ 18193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 18293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 18393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 18493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 18593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PSSR_MDIX 0x0800 18693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PSSR_SPEED_MASK 0xC000 18793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 18893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 18993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP02E1000_PHY_CHANNEL_NUM 4 19093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP02E1000_PHY_AGC_A 0x11B1 19193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP02E1000_PHY_AGC_B 0x12B1 19293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP02E1000_PHY_AGC_C 0x14B1 19393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP02E1000_PHY_AGC_D 0x18B1 19493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 19593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Course=15:13, Fine=12:9 */ 19693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP02E1000_AGC_LENGTH_MASK 0x7F 19793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IGP02E1000_AGC_RANGE 15 19893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 19993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define E1000_CABLE_LENGTH_UNDEFINED 0xFF 20093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 20193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 20293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 20393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define E1000_KMRNCTRLSTA_REN 0x00200000 20493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define E1000_KMRNCTRLSTA_CTRL_OFFSET 0x1 /* Kumeran Control */ 20593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Kumeran Diagnostic */ 20693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Kumeran Timeouts */ 20793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* Kumeran InBand Parameters */ 20893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */ 20993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Nearend Loopback mode */ 21093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 21193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 /* enable K1 */ 21293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define E1000_KMRNCTRLSTA_HD_CTRL 0x10 /* Kumeran HD Control */ 21393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 21493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 21593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY Special Ctrl */ 21693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY Special and LED Ctrl */ 21793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control */ 21893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 21993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan/* IFE PHY Extended Status Control */ 22093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IFE_PESC_POLARITY_REVERSED 0x0100 22193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 22293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan/* IFE PHY Special Control */ 22393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 22493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IFE_PSC_FORCE_POLARITY 0x0020 22593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 22693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan/* IFE PHY Special Control and LED Control */ 22793b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IFE_PSCL_PROBE_MODE 0x0020 22893b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 22993b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 23093b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 23193b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan/* IFE PHY MDIX Control */ 23293b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 23393b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDI-X, 0=force MDI */ 23493b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable auto, 0=disable */ 23593b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan 23693b9f8bfd72818ddb540eb19333907989fb97043Bruce Allan#endif 237