e1000_82575.c revision 82bbcdebbac75bf7636bf63ac0e6e4a49b128978
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2011 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28/* e1000_82575 29 * e1000_82576 30 */ 31 32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 33 34#include <linux/types.h> 35#include <linux/if_ether.h> 36 37#include "e1000_mac.h" 38#include "e1000_82575.h" 39 40static s32 igb_get_invariants_82575(struct e1000_hw *); 41static s32 igb_acquire_phy_82575(struct e1000_hw *); 42static void igb_release_phy_82575(struct e1000_hw *); 43static s32 igb_acquire_nvm_82575(struct e1000_hw *); 44static void igb_release_nvm_82575(struct e1000_hw *); 45static s32 igb_check_for_link_82575(struct e1000_hw *); 46static s32 igb_get_cfg_done_82575(struct e1000_hw *); 47static s32 igb_init_hw_82575(struct e1000_hw *); 48static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *); 49static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16 *); 50static s32 igb_read_phy_reg_82580(struct e1000_hw *, u32, u16 *); 51static s32 igb_write_phy_reg_82580(struct e1000_hw *, u32, u16); 52static s32 igb_reset_hw_82575(struct e1000_hw *); 53static s32 igb_reset_hw_82580(struct e1000_hw *); 54static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *, bool); 55static s32 igb_setup_copper_link_82575(struct e1000_hw *); 56static s32 igb_setup_serdes_link_82575(struct e1000_hw *); 57static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *, u32, u16); 58static void igb_clear_hw_cntrs_82575(struct e1000_hw *); 59static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *, u16); 60static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *, u16 *, 61 u16 *); 62static s32 igb_get_phy_id_82575(struct e1000_hw *); 63static void igb_release_swfw_sync_82575(struct e1000_hw *, u16); 64static bool igb_sgmii_active_82575(struct e1000_hw *); 65static s32 igb_reset_init_script_82575(struct e1000_hw *); 66static s32 igb_read_mac_addr_82575(struct e1000_hw *); 67static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw); 68static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw); 69static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw); 70static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw); 71static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw); 72static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw); 73static const u16 e1000_82580_rxpbs_table[] = 74 { 36, 72, 144, 1, 2, 4, 8, 16, 75 35, 70, 140 }; 76#define E1000_82580_RXPBS_TABLE_SIZE \ 77 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16)) 78 79/** 80 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO 81 * @hw: pointer to the HW structure 82 * 83 * Called to determine if the I2C pins are being used for I2C or as an 84 * external MDIO interface since the two options are mutually exclusive. 85 **/ 86static bool igb_sgmii_uses_mdio_82575(struct e1000_hw *hw) 87{ 88 u32 reg = 0; 89 bool ext_mdio = false; 90 91 switch (hw->mac.type) { 92 case e1000_82575: 93 case e1000_82576: 94 reg = rd32(E1000_MDIC); 95 ext_mdio = !!(reg & E1000_MDIC_DEST); 96 break; 97 case e1000_82580: 98 case e1000_i350: 99 reg = rd32(E1000_MDICNFG); 100 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO); 101 break; 102 default: 103 break; 104 } 105 return ext_mdio; 106} 107 108static s32 igb_get_invariants_82575(struct e1000_hw *hw) 109{ 110 struct e1000_phy_info *phy = &hw->phy; 111 struct e1000_nvm_info *nvm = &hw->nvm; 112 struct e1000_mac_info *mac = &hw->mac; 113 struct e1000_dev_spec_82575 * dev_spec = &hw->dev_spec._82575; 114 u32 eecd; 115 s32 ret_val; 116 u16 size; 117 u32 ctrl_ext = 0; 118 119 switch (hw->device_id) { 120 case E1000_DEV_ID_82575EB_COPPER: 121 case E1000_DEV_ID_82575EB_FIBER_SERDES: 122 case E1000_DEV_ID_82575GB_QUAD_COPPER: 123 mac->type = e1000_82575; 124 break; 125 case E1000_DEV_ID_82576: 126 case E1000_DEV_ID_82576_NS: 127 case E1000_DEV_ID_82576_NS_SERDES: 128 case E1000_DEV_ID_82576_FIBER: 129 case E1000_DEV_ID_82576_SERDES: 130 case E1000_DEV_ID_82576_QUAD_COPPER: 131 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 132 case E1000_DEV_ID_82576_SERDES_QUAD: 133 mac->type = e1000_82576; 134 break; 135 case E1000_DEV_ID_82580_COPPER: 136 case E1000_DEV_ID_82580_FIBER: 137 case E1000_DEV_ID_82580_QUAD_FIBER: 138 case E1000_DEV_ID_82580_SERDES: 139 case E1000_DEV_ID_82580_SGMII: 140 case E1000_DEV_ID_82580_COPPER_DUAL: 141 case E1000_DEV_ID_DH89XXCC_SGMII: 142 case E1000_DEV_ID_DH89XXCC_SERDES: 143 case E1000_DEV_ID_DH89XXCC_BACKPLANE: 144 case E1000_DEV_ID_DH89XXCC_SFP: 145 mac->type = e1000_82580; 146 break; 147 case E1000_DEV_ID_I350_COPPER: 148 case E1000_DEV_ID_I350_FIBER: 149 case E1000_DEV_ID_I350_SERDES: 150 case E1000_DEV_ID_I350_SGMII: 151 mac->type = e1000_i350; 152 break; 153 default: 154 return -E1000_ERR_MAC_INIT; 155 break; 156 } 157 158 /* Set media type */ 159 /* 160 * The 82575 uses bits 22:23 for link mode. The mode can be changed 161 * based on the EEPROM. We cannot rely upon device ID. There 162 * is no distinguishable difference between fiber and internal 163 * SerDes mode on the 82575. There can be an external PHY attached 164 * on the SGMII interface. For this, we'll set sgmii_active to true. 165 */ 166 phy->media_type = e1000_media_type_copper; 167 dev_spec->sgmii_active = false; 168 169 ctrl_ext = rd32(E1000_CTRL_EXT); 170 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 171 case E1000_CTRL_EXT_LINK_MODE_SGMII: 172 dev_spec->sgmii_active = true; 173 break; 174 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 175 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: 176 hw->phy.media_type = e1000_media_type_internal_serdes; 177 break; 178 default: 179 break; 180 } 181 182 /* Set mta register count */ 183 mac->mta_reg_count = 128; 184 /* Set rar entry count */ 185 mac->rar_entry_count = E1000_RAR_ENTRIES_82575; 186 if (mac->type == e1000_82576) 187 mac->rar_entry_count = E1000_RAR_ENTRIES_82576; 188 if (mac->type == e1000_82580) 189 mac->rar_entry_count = E1000_RAR_ENTRIES_82580; 190 if (mac->type == e1000_i350) 191 mac->rar_entry_count = E1000_RAR_ENTRIES_I350; 192 /* reset */ 193 if (mac->type >= e1000_82580) 194 mac->ops.reset_hw = igb_reset_hw_82580; 195 else 196 mac->ops.reset_hw = igb_reset_hw_82575; 197 /* Set if part includes ASF firmware */ 198 mac->asf_firmware_present = true; 199 /* Set if manageability features are enabled. */ 200 mac->arc_subsystem_valid = 201 (rd32(E1000_FWSM) & E1000_FWSM_MODE_MASK) 202 ? true : false; 203 /* enable EEE on i350 parts */ 204 if (mac->type == e1000_i350) 205 dev_spec->eee_disable = false; 206 else 207 dev_spec->eee_disable = true; 208 /* physical interface link setup */ 209 mac->ops.setup_physical_interface = 210 (hw->phy.media_type == e1000_media_type_copper) 211 ? igb_setup_copper_link_82575 212 : igb_setup_serdes_link_82575; 213 214 /* NVM initialization */ 215 eecd = rd32(E1000_EECD); 216 217 nvm->opcode_bits = 8; 218 nvm->delay_usec = 1; 219 switch (nvm->override) { 220 case e1000_nvm_override_spi_large: 221 nvm->page_size = 32; 222 nvm->address_bits = 16; 223 break; 224 case e1000_nvm_override_spi_small: 225 nvm->page_size = 8; 226 nvm->address_bits = 8; 227 break; 228 default: 229 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; 230 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8; 231 break; 232 } 233 234 nvm->type = e1000_nvm_eeprom_spi; 235 236 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> 237 E1000_EECD_SIZE_EX_SHIFT); 238 239 /* 240 * Added to a constant, "size" becomes the left-shift value 241 * for setting word_size. 242 */ 243 size += NVM_WORD_SIZE_BASE_SHIFT; 244 245 /* 246 * Check for invalid size 247 */ 248 if ((hw->mac.type == e1000_82576) && (size > 15)) { 249 pr_notice("The NVM size is not valid, defaulting to 32K\n"); 250 size = 15; 251 } 252 nvm->word_size = 1 << size; 253 if (nvm->word_size == (1 << 15)) 254 nvm->page_size = 128; 255 256 /* NVM Function Pointers */ 257 nvm->ops.acquire = igb_acquire_nvm_82575; 258 if (nvm->word_size < (1 << 15)) 259 nvm->ops.read = igb_read_nvm_eerd; 260 else 261 nvm->ops.read = igb_read_nvm_spi; 262 263 nvm->ops.release = igb_release_nvm_82575; 264 switch (hw->mac.type) { 265 case e1000_82580: 266 nvm->ops.validate = igb_validate_nvm_checksum_82580; 267 nvm->ops.update = igb_update_nvm_checksum_82580; 268 break; 269 case e1000_i350: 270 nvm->ops.validate = igb_validate_nvm_checksum_i350; 271 nvm->ops.update = igb_update_nvm_checksum_i350; 272 break; 273 default: 274 nvm->ops.validate = igb_validate_nvm_checksum; 275 nvm->ops.update = igb_update_nvm_checksum; 276 } 277 nvm->ops.write = igb_write_nvm_spi; 278 279 /* if part supports SR-IOV then initialize mailbox parameters */ 280 switch (mac->type) { 281 case e1000_82576: 282 case e1000_i350: 283 igb_init_mbx_params_pf(hw); 284 break; 285 default: 286 break; 287 } 288 289 /* setup PHY parameters */ 290 if (phy->media_type != e1000_media_type_copper) { 291 phy->type = e1000_phy_none; 292 return 0; 293 } 294 295 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 296 phy->reset_delay_us = 100; 297 298 ctrl_ext = rd32(E1000_CTRL_EXT); 299 300 /* PHY function pointers */ 301 if (igb_sgmii_active_82575(hw)) { 302 phy->ops.reset = igb_phy_hw_reset_sgmii_82575; 303 ctrl_ext |= E1000_CTRL_I2C_ENA; 304 } else { 305 phy->ops.reset = igb_phy_hw_reset; 306 ctrl_ext &= ~E1000_CTRL_I2C_ENA; 307 } 308 309 wr32(E1000_CTRL_EXT, ctrl_ext); 310 igb_reset_mdicnfg_82580(hw); 311 312 if (igb_sgmii_active_82575(hw) && !igb_sgmii_uses_mdio_82575(hw)) { 313 phy->ops.read_reg = igb_read_phy_reg_sgmii_82575; 314 phy->ops.write_reg = igb_write_phy_reg_sgmii_82575; 315 } else if (hw->mac.type >= e1000_82580) { 316 phy->ops.read_reg = igb_read_phy_reg_82580; 317 phy->ops.write_reg = igb_write_phy_reg_82580; 318 } else { 319 phy->ops.read_reg = igb_read_phy_reg_igp; 320 phy->ops.write_reg = igb_write_phy_reg_igp; 321 } 322 323 /* set lan id */ 324 hw->bus.func = (rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) >> 325 E1000_STATUS_FUNC_SHIFT; 326 327 /* Set phy->phy_addr and phy->id. */ 328 ret_val = igb_get_phy_id_82575(hw); 329 if (ret_val) 330 return ret_val; 331 332 /* Verify phy id and set remaining function pointers */ 333 switch (phy->id) { 334 case I347AT4_E_PHY_ID: 335 case M88E1112_E_PHY_ID: 336 case M88E1111_I_PHY_ID: 337 phy->type = e1000_phy_m88; 338 phy->ops.get_phy_info = igb_get_phy_info_m88; 339 340 if (phy->id == I347AT4_E_PHY_ID || 341 phy->id == M88E1112_E_PHY_ID) 342 phy->ops.get_cable_length = igb_get_cable_length_m88_gen2; 343 else 344 phy->ops.get_cable_length = igb_get_cable_length_m88; 345 346 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_m88; 347 break; 348 case IGP03E1000_E_PHY_ID: 349 phy->type = e1000_phy_igp_3; 350 phy->ops.get_phy_info = igb_get_phy_info_igp; 351 phy->ops.get_cable_length = igb_get_cable_length_igp_2; 352 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_igp; 353 phy->ops.set_d0_lplu_state = igb_set_d0_lplu_state_82575; 354 phy->ops.set_d3_lplu_state = igb_set_d3_lplu_state; 355 break; 356 case I82580_I_PHY_ID: 357 case I350_I_PHY_ID: 358 phy->type = e1000_phy_82580; 359 phy->ops.force_speed_duplex = igb_phy_force_speed_duplex_82580; 360 phy->ops.get_cable_length = igb_get_cable_length_82580; 361 phy->ops.get_phy_info = igb_get_phy_info_82580; 362 break; 363 default: 364 return -E1000_ERR_PHY; 365 } 366 367 return 0; 368} 369 370/** 371 * igb_acquire_phy_82575 - Acquire rights to access PHY 372 * @hw: pointer to the HW structure 373 * 374 * Acquire access rights to the correct PHY. This is a 375 * function pointer entry point called by the api module. 376 **/ 377static s32 igb_acquire_phy_82575(struct e1000_hw *hw) 378{ 379 u16 mask = E1000_SWFW_PHY0_SM; 380 381 if (hw->bus.func == E1000_FUNC_1) 382 mask = E1000_SWFW_PHY1_SM; 383 else if (hw->bus.func == E1000_FUNC_2) 384 mask = E1000_SWFW_PHY2_SM; 385 else if (hw->bus.func == E1000_FUNC_3) 386 mask = E1000_SWFW_PHY3_SM; 387 388 return igb_acquire_swfw_sync_82575(hw, mask); 389} 390 391/** 392 * igb_release_phy_82575 - Release rights to access PHY 393 * @hw: pointer to the HW structure 394 * 395 * A wrapper to release access rights to the correct PHY. This is a 396 * function pointer entry point called by the api module. 397 **/ 398static void igb_release_phy_82575(struct e1000_hw *hw) 399{ 400 u16 mask = E1000_SWFW_PHY0_SM; 401 402 if (hw->bus.func == E1000_FUNC_1) 403 mask = E1000_SWFW_PHY1_SM; 404 else if (hw->bus.func == E1000_FUNC_2) 405 mask = E1000_SWFW_PHY2_SM; 406 else if (hw->bus.func == E1000_FUNC_3) 407 mask = E1000_SWFW_PHY3_SM; 408 409 igb_release_swfw_sync_82575(hw, mask); 410} 411 412/** 413 * igb_read_phy_reg_sgmii_82575 - Read PHY register using sgmii 414 * @hw: pointer to the HW structure 415 * @offset: register offset to be read 416 * @data: pointer to the read data 417 * 418 * Reads the PHY register at offset using the serial gigabit media independent 419 * interface and stores the retrieved information in data. 420 **/ 421static s32 igb_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 422 u16 *data) 423{ 424 s32 ret_val = -E1000_ERR_PARAM; 425 426 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 427 hw_dbg("PHY Address %u is out of range\n", offset); 428 goto out; 429 } 430 431 ret_val = hw->phy.ops.acquire(hw); 432 if (ret_val) 433 goto out; 434 435 ret_val = igb_read_phy_reg_i2c(hw, offset, data); 436 437 hw->phy.ops.release(hw); 438 439out: 440 return ret_val; 441} 442 443/** 444 * igb_write_phy_reg_sgmii_82575 - Write PHY register using sgmii 445 * @hw: pointer to the HW structure 446 * @offset: register offset to write to 447 * @data: data to write at register offset 448 * 449 * Writes the data to PHY register at the offset using the serial gigabit 450 * media independent interface. 451 **/ 452static s32 igb_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, 453 u16 data) 454{ 455 s32 ret_val = -E1000_ERR_PARAM; 456 457 458 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) { 459 hw_dbg("PHY Address %d is out of range\n", offset); 460 goto out; 461 } 462 463 ret_val = hw->phy.ops.acquire(hw); 464 if (ret_val) 465 goto out; 466 467 ret_val = igb_write_phy_reg_i2c(hw, offset, data); 468 469 hw->phy.ops.release(hw); 470 471out: 472 return ret_val; 473} 474 475/** 476 * igb_get_phy_id_82575 - Retrieve PHY addr and id 477 * @hw: pointer to the HW structure 478 * 479 * Retrieves the PHY address and ID for both PHY's which do and do not use 480 * sgmi interface. 481 **/ 482static s32 igb_get_phy_id_82575(struct e1000_hw *hw) 483{ 484 struct e1000_phy_info *phy = &hw->phy; 485 s32 ret_val = 0; 486 u16 phy_id; 487 u32 ctrl_ext; 488 u32 mdic; 489 490 /* 491 * For SGMII PHYs, we try the list of possible addresses until 492 * we find one that works. For non-SGMII PHYs 493 * (e.g. integrated copper PHYs), an address of 1 should 494 * work. The result of this function should mean phy->phy_addr 495 * and phy->id are set correctly. 496 */ 497 if (!(igb_sgmii_active_82575(hw))) { 498 phy->addr = 1; 499 ret_val = igb_get_phy_id(hw); 500 goto out; 501 } 502 503 if (igb_sgmii_uses_mdio_82575(hw)) { 504 switch (hw->mac.type) { 505 case e1000_82575: 506 case e1000_82576: 507 mdic = rd32(E1000_MDIC); 508 mdic &= E1000_MDIC_PHY_MASK; 509 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT; 510 break; 511 case e1000_82580: 512 case e1000_i350: 513 mdic = rd32(E1000_MDICNFG); 514 mdic &= E1000_MDICNFG_PHY_MASK; 515 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT; 516 break; 517 default: 518 ret_val = -E1000_ERR_PHY; 519 goto out; 520 break; 521 } 522 ret_val = igb_get_phy_id(hw); 523 goto out; 524 } 525 526 /* Power on sgmii phy if it is disabled */ 527 ctrl_ext = rd32(E1000_CTRL_EXT); 528 wr32(E1000_CTRL_EXT, ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA); 529 wrfl(); 530 msleep(300); 531 532 /* 533 * The address field in the I2CCMD register is 3 bits and 0 is invalid. 534 * Therefore, we need to test 1-7 535 */ 536 for (phy->addr = 1; phy->addr < 8; phy->addr++) { 537 ret_val = igb_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id); 538 if (ret_val == 0) { 539 hw_dbg("Vendor ID 0x%08X read at address %u\n", 540 phy_id, phy->addr); 541 /* 542 * At the time of this writing, The M88 part is 543 * the only supported SGMII PHY product. 544 */ 545 if (phy_id == M88_VENDOR) 546 break; 547 } else { 548 hw_dbg("PHY address %u was unreadable\n", phy->addr); 549 } 550 } 551 552 /* A valid PHY type couldn't be found. */ 553 if (phy->addr == 8) { 554 phy->addr = 0; 555 ret_val = -E1000_ERR_PHY; 556 goto out; 557 } else { 558 ret_val = igb_get_phy_id(hw); 559 } 560 561 /* restore previous sfp cage power state */ 562 wr32(E1000_CTRL_EXT, ctrl_ext); 563 564out: 565 return ret_val; 566} 567 568/** 569 * igb_phy_hw_reset_sgmii_82575 - Performs a PHY reset 570 * @hw: pointer to the HW structure 571 * 572 * Resets the PHY using the serial gigabit media independent interface. 573 **/ 574static s32 igb_phy_hw_reset_sgmii_82575(struct e1000_hw *hw) 575{ 576 s32 ret_val; 577 578 /* 579 * This isn't a true "hard" reset, but is the only reset 580 * available to us at this time. 581 */ 582 583 hw_dbg("Soft resetting SGMII attached PHY...\n"); 584 585 /* 586 * SFP documentation requires the following to configure the SPF module 587 * to work on SGMII. No further documentation is given. 588 */ 589 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084); 590 if (ret_val) 591 goto out; 592 593 ret_val = igb_phy_sw_reset(hw); 594 595out: 596 return ret_val; 597} 598 599/** 600 * igb_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state 601 * @hw: pointer to the HW structure 602 * @active: true to enable LPLU, false to disable 603 * 604 * Sets the LPLU D0 state according to the active flag. When 605 * activating LPLU this function also disables smart speed 606 * and vice versa. LPLU will not be activated unless the 607 * device autonegotiation advertisement meets standards of 608 * either 10 or 10/100 or 10/100/1000 at all duplexes. 609 * This is a function pointer entry point only called by 610 * PHY setup routines. 611 **/ 612static s32 igb_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active) 613{ 614 struct e1000_phy_info *phy = &hw->phy; 615 s32 ret_val; 616 u16 data; 617 618 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data); 619 if (ret_val) 620 goto out; 621 622 if (active) { 623 data |= IGP02E1000_PM_D0_LPLU; 624 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 625 data); 626 if (ret_val) 627 goto out; 628 629 /* When LPLU is enabled, we should disable SmartSpeed */ 630 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 631 &data); 632 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 633 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG, 634 data); 635 if (ret_val) 636 goto out; 637 } else { 638 data &= ~IGP02E1000_PM_D0_LPLU; 639 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT, 640 data); 641 /* 642 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 643 * during Dx states where the power conservation is most 644 * important. During driver activity we should enable 645 * SmartSpeed, so performance is maintained. 646 */ 647 if (phy->smart_speed == e1000_smart_speed_on) { 648 ret_val = phy->ops.read_reg(hw, 649 IGP01E1000_PHY_PORT_CONFIG, &data); 650 if (ret_val) 651 goto out; 652 653 data |= IGP01E1000_PSCFR_SMART_SPEED; 654 ret_val = phy->ops.write_reg(hw, 655 IGP01E1000_PHY_PORT_CONFIG, data); 656 if (ret_val) 657 goto out; 658 } else if (phy->smart_speed == e1000_smart_speed_off) { 659 ret_val = phy->ops.read_reg(hw, 660 IGP01E1000_PHY_PORT_CONFIG, &data); 661 if (ret_val) 662 goto out; 663 664 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 665 ret_val = phy->ops.write_reg(hw, 666 IGP01E1000_PHY_PORT_CONFIG, data); 667 if (ret_val) 668 goto out; 669 } 670 } 671 672out: 673 return ret_val; 674} 675 676/** 677 * igb_acquire_nvm_82575 - Request for access to EEPROM 678 * @hw: pointer to the HW structure 679 * 680 * Acquire the necessary semaphores for exclusive access to the EEPROM. 681 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 682 * Return successful if access grant bit set, else clear the request for 683 * EEPROM access and return -E1000_ERR_NVM (-1). 684 **/ 685static s32 igb_acquire_nvm_82575(struct e1000_hw *hw) 686{ 687 s32 ret_val; 688 689 ret_val = igb_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 690 if (ret_val) 691 goto out; 692 693 ret_val = igb_acquire_nvm(hw); 694 695 if (ret_val) 696 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 697 698out: 699 return ret_val; 700} 701 702/** 703 * igb_release_nvm_82575 - Release exclusive access to EEPROM 704 * @hw: pointer to the HW structure 705 * 706 * Stop any current commands to the EEPROM and clear the EEPROM request bit, 707 * then release the semaphores acquired. 708 **/ 709static void igb_release_nvm_82575(struct e1000_hw *hw) 710{ 711 igb_release_nvm(hw); 712 igb_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM); 713} 714 715/** 716 * igb_acquire_swfw_sync_82575 - Acquire SW/FW semaphore 717 * @hw: pointer to the HW structure 718 * @mask: specifies which semaphore to acquire 719 * 720 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask 721 * will also specify which port we're acquiring the lock for. 722 **/ 723static s32 igb_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 724{ 725 u32 swfw_sync; 726 u32 swmask = mask; 727 u32 fwmask = mask << 16; 728 s32 ret_val = 0; 729 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */ 730 731 while (i < timeout) { 732 if (igb_get_hw_semaphore(hw)) { 733 ret_val = -E1000_ERR_SWFW_SYNC; 734 goto out; 735 } 736 737 swfw_sync = rd32(E1000_SW_FW_SYNC); 738 if (!(swfw_sync & (fwmask | swmask))) 739 break; 740 741 /* 742 * Firmware currently using resource (fwmask) 743 * or other software thread using resource (swmask) 744 */ 745 igb_put_hw_semaphore(hw); 746 mdelay(5); 747 i++; 748 } 749 750 if (i == timeout) { 751 hw_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n"); 752 ret_val = -E1000_ERR_SWFW_SYNC; 753 goto out; 754 } 755 756 swfw_sync |= swmask; 757 wr32(E1000_SW_FW_SYNC, swfw_sync); 758 759 igb_put_hw_semaphore(hw); 760 761out: 762 return ret_val; 763} 764 765/** 766 * igb_release_swfw_sync_82575 - Release SW/FW semaphore 767 * @hw: pointer to the HW structure 768 * @mask: specifies which semaphore to acquire 769 * 770 * Release the SW/FW semaphore used to access the PHY or NVM. The mask 771 * will also specify which port we're releasing the lock for. 772 **/ 773static void igb_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask) 774{ 775 u32 swfw_sync; 776 777 while (igb_get_hw_semaphore(hw) != 0); 778 /* Empty */ 779 780 swfw_sync = rd32(E1000_SW_FW_SYNC); 781 swfw_sync &= ~mask; 782 wr32(E1000_SW_FW_SYNC, swfw_sync); 783 784 igb_put_hw_semaphore(hw); 785} 786 787/** 788 * igb_get_cfg_done_82575 - Read config done bit 789 * @hw: pointer to the HW structure 790 * 791 * Read the management control register for the config done bit for 792 * completion status. NOTE: silicon which is EEPROM-less will fail trying 793 * to read the config done bit, so an error is *ONLY* logged and returns 794 * 0. If we were to return with error, EEPROM-less silicon 795 * would not be able to be reset or change link. 796 **/ 797static s32 igb_get_cfg_done_82575(struct e1000_hw *hw) 798{ 799 s32 timeout = PHY_CFG_TIMEOUT; 800 s32 ret_val = 0; 801 u32 mask = E1000_NVM_CFG_DONE_PORT_0; 802 803 if (hw->bus.func == 1) 804 mask = E1000_NVM_CFG_DONE_PORT_1; 805 else if (hw->bus.func == E1000_FUNC_2) 806 mask = E1000_NVM_CFG_DONE_PORT_2; 807 else if (hw->bus.func == E1000_FUNC_3) 808 mask = E1000_NVM_CFG_DONE_PORT_3; 809 810 while (timeout) { 811 if (rd32(E1000_EEMNGCTL) & mask) 812 break; 813 msleep(1); 814 timeout--; 815 } 816 if (!timeout) 817 hw_dbg("MNG configuration cycle has not completed.\n"); 818 819 /* If EEPROM is not marked present, init the PHY manually */ 820 if (((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) && 821 (hw->phy.type == e1000_phy_igp_3)) 822 igb_phy_init_script_igp3(hw); 823 824 return ret_val; 825} 826 827/** 828 * igb_check_for_link_82575 - Check for link 829 * @hw: pointer to the HW structure 830 * 831 * If sgmii is enabled, then use the pcs register to determine link, otherwise 832 * use the generic interface for determining link. 833 **/ 834static s32 igb_check_for_link_82575(struct e1000_hw *hw) 835{ 836 s32 ret_val; 837 u16 speed, duplex; 838 839 if (hw->phy.media_type != e1000_media_type_copper) { 840 ret_val = igb_get_pcs_speed_and_duplex_82575(hw, &speed, 841 &duplex); 842 /* 843 * Use this flag to determine if link needs to be checked or 844 * not. If we have link clear the flag so that we do not 845 * continue to check for link. 846 */ 847 hw->mac.get_link_status = !hw->mac.serdes_has_link; 848 } else { 849 ret_val = igb_check_for_copper_link(hw); 850 } 851 852 return ret_val; 853} 854 855/** 856 * igb_power_up_serdes_link_82575 - Power up the serdes link after shutdown 857 * @hw: pointer to the HW structure 858 **/ 859void igb_power_up_serdes_link_82575(struct e1000_hw *hw) 860{ 861 u32 reg; 862 863 864 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 865 !igb_sgmii_active_82575(hw)) 866 return; 867 868 /* Enable PCS to turn on link */ 869 reg = rd32(E1000_PCS_CFG0); 870 reg |= E1000_PCS_CFG_PCS_EN; 871 wr32(E1000_PCS_CFG0, reg); 872 873 /* Power up the laser */ 874 reg = rd32(E1000_CTRL_EXT); 875 reg &= ~E1000_CTRL_EXT_SDP3_DATA; 876 wr32(E1000_CTRL_EXT, reg); 877 878 /* flush the write to verify completion */ 879 wrfl(); 880 msleep(1); 881} 882 883/** 884 * igb_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex 885 * @hw: pointer to the HW structure 886 * @speed: stores the current speed 887 * @duplex: stores the current duplex 888 * 889 * Using the physical coding sub-layer (PCS), retrieve the current speed and 890 * duplex, then store the values in the pointers provided. 891 **/ 892static s32 igb_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, u16 *speed, 893 u16 *duplex) 894{ 895 struct e1000_mac_info *mac = &hw->mac; 896 u32 pcs; 897 898 /* Set up defaults for the return values of this function */ 899 mac->serdes_has_link = false; 900 *speed = 0; 901 *duplex = 0; 902 903 /* 904 * Read the PCS Status register for link state. For non-copper mode, 905 * the status register is not accurate. The PCS status register is 906 * used instead. 907 */ 908 pcs = rd32(E1000_PCS_LSTAT); 909 910 /* 911 * The link up bit determines when link is up on autoneg. The sync ok 912 * gets set once both sides sync up and agree upon link. Stable link 913 * can be determined by checking for both link up and link sync ok 914 */ 915 if ((pcs & E1000_PCS_LSTS_LINK_OK) && (pcs & E1000_PCS_LSTS_SYNK_OK)) { 916 mac->serdes_has_link = true; 917 918 /* Detect and store PCS speed */ 919 if (pcs & E1000_PCS_LSTS_SPEED_1000) { 920 *speed = SPEED_1000; 921 } else if (pcs & E1000_PCS_LSTS_SPEED_100) { 922 *speed = SPEED_100; 923 } else { 924 *speed = SPEED_10; 925 } 926 927 /* Detect and store PCS duplex */ 928 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL) { 929 *duplex = FULL_DUPLEX; 930 } else { 931 *duplex = HALF_DUPLEX; 932 } 933 } 934 935 return 0; 936} 937 938/** 939 * igb_shutdown_serdes_link_82575 - Remove link during power down 940 * @hw: pointer to the HW structure 941 * 942 * In the case of fiber serdes, shut down optics and PCS on driver unload 943 * when management pass thru is not enabled. 944 **/ 945void igb_shutdown_serdes_link_82575(struct e1000_hw *hw) 946{ 947 u32 reg; 948 949 if (hw->phy.media_type != e1000_media_type_internal_serdes && 950 igb_sgmii_active_82575(hw)) 951 return; 952 953 if (!igb_enable_mng_pass_thru(hw)) { 954 /* Disable PCS to turn off link */ 955 reg = rd32(E1000_PCS_CFG0); 956 reg &= ~E1000_PCS_CFG_PCS_EN; 957 wr32(E1000_PCS_CFG0, reg); 958 959 /* shutdown the laser */ 960 reg = rd32(E1000_CTRL_EXT); 961 reg |= E1000_CTRL_EXT_SDP3_DATA; 962 wr32(E1000_CTRL_EXT, reg); 963 964 /* flush the write to verify completion */ 965 wrfl(); 966 msleep(1); 967 } 968} 969 970/** 971 * igb_reset_hw_82575 - Reset hardware 972 * @hw: pointer to the HW structure 973 * 974 * This resets the hardware into a known state. This is a 975 * function pointer entry point called by the api module. 976 **/ 977static s32 igb_reset_hw_82575(struct e1000_hw *hw) 978{ 979 u32 ctrl, icr; 980 s32 ret_val; 981 982 /* 983 * Prevent the PCI-E bus from sticking if there is no TLP connection 984 * on the last TLP read/write transaction when MAC is reset. 985 */ 986 ret_val = igb_disable_pcie_master(hw); 987 if (ret_val) 988 hw_dbg("PCI-E Master disable polling has failed.\n"); 989 990 /* set the completion timeout for interface */ 991 ret_val = igb_set_pcie_completion_timeout(hw); 992 if (ret_val) { 993 hw_dbg("PCI-E Set completion timeout has failed.\n"); 994 } 995 996 hw_dbg("Masking off all interrupts\n"); 997 wr32(E1000_IMC, 0xffffffff); 998 999 wr32(E1000_RCTL, 0); 1000 wr32(E1000_TCTL, E1000_TCTL_PSP); 1001 wrfl(); 1002 1003 msleep(10); 1004 1005 ctrl = rd32(E1000_CTRL); 1006 1007 hw_dbg("Issuing a global reset to MAC\n"); 1008 wr32(E1000_CTRL, ctrl | E1000_CTRL_RST); 1009 1010 ret_val = igb_get_auto_rd_done(hw); 1011 if (ret_val) { 1012 /* 1013 * When auto config read does not complete, do not 1014 * return with an error. This can happen in situations 1015 * where there is no eeprom and prevents getting link. 1016 */ 1017 hw_dbg("Auto Read Done did not complete\n"); 1018 } 1019 1020 /* If EEPROM is not present, run manual init scripts */ 1021 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) 1022 igb_reset_init_script_82575(hw); 1023 1024 /* Clear any pending interrupt events. */ 1025 wr32(E1000_IMC, 0xffffffff); 1026 icr = rd32(E1000_ICR); 1027 1028 /* Install any alternate MAC address into RAR0 */ 1029 ret_val = igb_check_alt_mac_addr(hw); 1030 1031 return ret_val; 1032} 1033 1034/** 1035 * igb_init_hw_82575 - Initialize hardware 1036 * @hw: pointer to the HW structure 1037 * 1038 * This inits the hardware readying it for operation. 1039 **/ 1040static s32 igb_init_hw_82575(struct e1000_hw *hw) 1041{ 1042 struct e1000_mac_info *mac = &hw->mac; 1043 s32 ret_val; 1044 u16 i, rar_count = mac->rar_entry_count; 1045 1046 /* Initialize identification LED */ 1047 ret_val = igb_id_led_init(hw); 1048 if (ret_val) { 1049 hw_dbg("Error initializing identification LED\n"); 1050 /* This is not fatal and we should not stop init due to this */ 1051 } 1052 1053 /* Disabling VLAN filtering */ 1054 hw_dbg("Initializing the IEEE VLAN\n"); 1055 if (hw->mac.type == e1000_i350) 1056 igb_clear_vfta_i350(hw); 1057 else 1058 igb_clear_vfta(hw); 1059 1060 /* Setup the receive address */ 1061 igb_init_rx_addrs(hw, rar_count); 1062 1063 /* Zero out the Multicast HASH table */ 1064 hw_dbg("Zeroing the MTA\n"); 1065 for (i = 0; i < mac->mta_reg_count; i++) 1066 array_wr32(E1000_MTA, i, 0); 1067 1068 /* Zero out the Unicast HASH table */ 1069 hw_dbg("Zeroing the UTA\n"); 1070 for (i = 0; i < mac->uta_reg_count; i++) 1071 array_wr32(E1000_UTA, i, 0); 1072 1073 /* Setup link and flow control */ 1074 ret_val = igb_setup_link(hw); 1075 1076 /* 1077 * Clear all of the statistics registers (clear on read). It is 1078 * important that we do this after we have tried to establish link 1079 * because the symbol error count will increment wildly if there 1080 * is no link. 1081 */ 1082 igb_clear_hw_cntrs_82575(hw); 1083 1084 return ret_val; 1085} 1086 1087/** 1088 * igb_setup_copper_link_82575 - Configure copper link settings 1089 * @hw: pointer to the HW structure 1090 * 1091 * Configures the link for auto-neg or forced speed and duplex. Then we check 1092 * for link, once link is established calls to configure collision distance 1093 * and flow control are called. 1094 **/ 1095static s32 igb_setup_copper_link_82575(struct e1000_hw *hw) 1096{ 1097 u32 ctrl; 1098 s32 ret_val; 1099 1100 ctrl = rd32(E1000_CTRL); 1101 ctrl |= E1000_CTRL_SLU; 1102 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 1103 wr32(E1000_CTRL, ctrl); 1104 1105 ret_val = igb_setup_serdes_link_82575(hw); 1106 if (ret_val) 1107 goto out; 1108 1109 if (igb_sgmii_active_82575(hw) && !hw->phy.reset_disable) { 1110 /* allow time for SFP cage time to power up phy */ 1111 msleep(300); 1112 1113 ret_val = hw->phy.ops.reset(hw); 1114 if (ret_val) { 1115 hw_dbg("Error resetting the PHY.\n"); 1116 goto out; 1117 } 1118 } 1119 switch (hw->phy.type) { 1120 case e1000_phy_m88: 1121 if (hw->phy.id == I347AT4_E_PHY_ID || 1122 hw->phy.id == M88E1112_E_PHY_ID) 1123 ret_val = igb_copper_link_setup_m88_gen2(hw); 1124 else 1125 ret_val = igb_copper_link_setup_m88(hw); 1126 break; 1127 case e1000_phy_igp_3: 1128 ret_val = igb_copper_link_setup_igp(hw); 1129 break; 1130 case e1000_phy_82580: 1131 ret_val = igb_copper_link_setup_82580(hw); 1132 break; 1133 default: 1134 ret_val = -E1000_ERR_PHY; 1135 break; 1136 } 1137 1138 if (ret_val) 1139 goto out; 1140 1141 ret_val = igb_setup_copper_link(hw); 1142out: 1143 return ret_val; 1144} 1145 1146/** 1147 * igb_setup_serdes_link_82575 - Setup link for serdes 1148 * @hw: pointer to the HW structure 1149 * 1150 * Configure the physical coding sub-layer (PCS) link. The PCS link is 1151 * used on copper connections where the serialized gigabit media independent 1152 * interface (sgmii), or serdes fiber is being used. Configures the link 1153 * for auto-negotiation or forces speed/duplex. 1154 **/ 1155static s32 igb_setup_serdes_link_82575(struct e1000_hw *hw) 1156{ 1157 u32 ctrl_ext, ctrl_reg, reg; 1158 bool pcs_autoneg; 1159 s32 ret_val = E1000_SUCCESS; 1160 u16 data; 1161 1162 if ((hw->phy.media_type != e1000_media_type_internal_serdes) && 1163 !igb_sgmii_active_82575(hw)) 1164 return ret_val; 1165 1166 1167 /* 1168 * On the 82575, SerDes loopback mode persists until it is 1169 * explicitly turned off or a power cycle is performed. A read to 1170 * the register does not indicate its status. Therefore, we ensure 1171 * loopback mode is disabled during initialization. 1172 */ 1173 wr32(E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK); 1174 1175 /* power on the sfp cage if present */ 1176 ctrl_ext = rd32(E1000_CTRL_EXT); 1177 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA; 1178 wr32(E1000_CTRL_EXT, ctrl_ext); 1179 1180 ctrl_reg = rd32(E1000_CTRL); 1181 ctrl_reg |= E1000_CTRL_SLU; 1182 1183 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { 1184 /* set both sw defined pins */ 1185 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1; 1186 1187 /* Set switch control to serdes energy detect */ 1188 reg = rd32(E1000_CONNSW); 1189 reg |= E1000_CONNSW_ENRGSRC; 1190 wr32(E1000_CONNSW, reg); 1191 } 1192 1193 reg = rd32(E1000_PCS_LCTL); 1194 1195 /* default pcs_autoneg to the same setting as mac autoneg */ 1196 pcs_autoneg = hw->mac.autoneg; 1197 1198 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) { 1199 case E1000_CTRL_EXT_LINK_MODE_SGMII: 1200 /* sgmii mode lets the phy handle forcing speed/duplex */ 1201 pcs_autoneg = true; 1202 /* autoneg time out should be disabled for SGMII mode */ 1203 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT); 1204 break; 1205 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: 1206 /* disable PCS autoneg and support parallel detect only */ 1207 pcs_autoneg = false; 1208 default: 1209 if (hw->mac.type == e1000_82575 || 1210 hw->mac.type == e1000_82576) { 1211 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data); 1212 if (ret_val) { 1213 printk(KERN_DEBUG "NVM Read Error\n\n"); 1214 return ret_val; 1215 } 1216 1217 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT) 1218 pcs_autoneg = false; 1219 } 1220 1221 /* 1222 * non-SGMII modes only supports a speed of 1000/Full for the 1223 * link so it is best to just force the MAC and let the pcs 1224 * link either autoneg or be forced to 1000/Full 1225 */ 1226 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD | 1227 E1000_CTRL_FD | E1000_CTRL_FRCDPX; 1228 1229 /* set speed of 1000/Full if speed/duplex is forced */ 1230 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL; 1231 break; 1232 } 1233 1234 wr32(E1000_CTRL, ctrl_reg); 1235 1236 /* 1237 * New SerDes mode allows for forcing speed or autonegotiating speed 1238 * at 1gb. Autoneg should be default set by most drivers. This is the 1239 * mode that will be compatible with older link partners and switches. 1240 * However, both are supported by the hardware and some drivers/tools. 1241 */ 1242 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP | 1243 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK); 1244 1245 /* 1246 * We force flow control to prevent the CTRL register values from being 1247 * overwritten by the autonegotiated flow control values 1248 */ 1249 reg |= E1000_PCS_LCTL_FORCE_FCTRL; 1250 1251 if (pcs_autoneg) { 1252 /* Set PCS register for autoneg */ 1253 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */ 1254 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */ 1255 hw_dbg("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg); 1256 } else { 1257 /* Set PCS register for forced link */ 1258 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */ 1259 1260 hw_dbg("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg); 1261 } 1262 1263 wr32(E1000_PCS_LCTL, reg); 1264 1265 if (!igb_sgmii_active_82575(hw)) 1266 igb_force_mac_fc(hw); 1267 1268 return ret_val; 1269} 1270 1271/** 1272 * igb_sgmii_active_82575 - Return sgmii state 1273 * @hw: pointer to the HW structure 1274 * 1275 * 82575 silicon has a serialized gigabit media independent interface (sgmii) 1276 * which can be enabled for use in the embedded applications. Simply 1277 * return the current state of the sgmii interface. 1278 **/ 1279static bool igb_sgmii_active_82575(struct e1000_hw *hw) 1280{ 1281 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575; 1282 return dev_spec->sgmii_active; 1283} 1284 1285/** 1286 * igb_reset_init_script_82575 - Inits HW defaults after reset 1287 * @hw: pointer to the HW structure 1288 * 1289 * Inits recommended HW defaults after a reset when there is no EEPROM 1290 * detected. This is only for the 82575. 1291 **/ 1292static s32 igb_reset_init_script_82575(struct e1000_hw *hw) 1293{ 1294 if (hw->mac.type == e1000_82575) { 1295 hw_dbg("Running reset init script for 82575\n"); 1296 /* SerDes configuration via SERDESCTRL */ 1297 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x00, 0x0C); 1298 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x01, 0x78); 1299 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x1B, 0x23); 1300 igb_write_8bit_ctrl_reg(hw, E1000_SCTL, 0x23, 0x15); 1301 1302 /* CCM configuration via CCMCTL register */ 1303 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x14, 0x00); 1304 igb_write_8bit_ctrl_reg(hw, E1000_CCMCTL, 0x10, 0x00); 1305 1306 /* PCIe lanes configuration */ 1307 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x00, 0xEC); 1308 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x61, 0xDF); 1309 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x34, 0x05); 1310 igb_write_8bit_ctrl_reg(hw, E1000_GIOCTL, 0x2F, 0x81); 1311 1312 /* PCIe PLL Configuration */ 1313 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x02, 0x47); 1314 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x14, 0x00); 1315 igb_write_8bit_ctrl_reg(hw, E1000_SCCTL, 0x10, 0x00); 1316 } 1317 1318 return 0; 1319} 1320 1321/** 1322 * igb_read_mac_addr_82575 - Read device MAC address 1323 * @hw: pointer to the HW structure 1324 **/ 1325static s32 igb_read_mac_addr_82575(struct e1000_hw *hw) 1326{ 1327 s32 ret_val = 0; 1328 1329 /* 1330 * If there's an alternate MAC address place it in RAR0 1331 * so that it will override the Si installed default perm 1332 * address. 1333 */ 1334 ret_val = igb_check_alt_mac_addr(hw); 1335 if (ret_val) 1336 goto out; 1337 1338 ret_val = igb_read_mac_addr(hw); 1339 1340out: 1341 return ret_val; 1342} 1343 1344/** 1345 * igb_power_down_phy_copper_82575 - Remove link during PHY power down 1346 * @hw: pointer to the HW structure 1347 * 1348 * In the case of a PHY power down to save power, or to turn off link during a 1349 * driver unload, or wake on lan is not enabled, remove the link. 1350 **/ 1351void igb_power_down_phy_copper_82575(struct e1000_hw *hw) 1352{ 1353 /* If the management interface is not enabled, then power down */ 1354 if (!(igb_enable_mng_pass_thru(hw) || igb_check_reset_block(hw))) 1355 igb_power_down_phy_copper(hw); 1356} 1357 1358/** 1359 * igb_clear_hw_cntrs_82575 - Clear device specific hardware counters 1360 * @hw: pointer to the HW structure 1361 * 1362 * Clears the hardware counters by reading the counter registers. 1363 **/ 1364static void igb_clear_hw_cntrs_82575(struct e1000_hw *hw) 1365{ 1366 igb_clear_hw_cntrs_base(hw); 1367 1368 rd32(E1000_PRC64); 1369 rd32(E1000_PRC127); 1370 rd32(E1000_PRC255); 1371 rd32(E1000_PRC511); 1372 rd32(E1000_PRC1023); 1373 rd32(E1000_PRC1522); 1374 rd32(E1000_PTC64); 1375 rd32(E1000_PTC127); 1376 rd32(E1000_PTC255); 1377 rd32(E1000_PTC511); 1378 rd32(E1000_PTC1023); 1379 rd32(E1000_PTC1522); 1380 1381 rd32(E1000_ALGNERRC); 1382 rd32(E1000_RXERRC); 1383 rd32(E1000_TNCRS); 1384 rd32(E1000_CEXTERR); 1385 rd32(E1000_TSCTC); 1386 rd32(E1000_TSCTFC); 1387 1388 rd32(E1000_MGTPRC); 1389 rd32(E1000_MGTPDC); 1390 rd32(E1000_MGTPTC); 1391 1392 rd32(E1000_IAC); 1393 rd32(E1000_ICRXOC); 1394 1395 rd32(E1000_ICRXPTC); 1396 rd32(E1000_ICRXATC); 1397 rd32(E1000_ICTXPTC); 1398 rd32(E1000_ICTXATC); 1399 rd32(E1000_ICTXQEC); 1400 rd32(E1000_ICTXQMTC); 1401 rd32(E1000_ICRXDMTC); 1402 1403 rd32(E1000_CBTMPC); 1404 rd32(E1000_HTDPMC); 1405 rd32(E1000_CBRMPC); 1406 rd32(E1000_RPTHC); 1407 rd32(E1000_HGPTC); 1408 rd32(E1000_HTCBDPC); 1409 rd32(E1000_HGORCL); 1410 rd32(E1000_HGORCH); 1411 rd32(E1000_HGOTCL); 1412 rd32(E1000_HGOTCH); 1413 rd32(E1000_LENERRS); 1414 1415 /* This register should not be read in copper configurations */ 1416 if (hw->phy.media_type == e1000_media_type_internal_serdes || 1417 igb_sgmii_active_82575(hw)) 1418 rd32(E1000_SCVPC); 1419} 1420 1421/** 1422 * igb_rx_fifo_flush_82575 - Clean rx fifo after RX enable 1423 * @hw: pointer to the HW structure 1424 * 1425 * After rx enable if managability is enabled then there is likely some 1426 * bad data at the start of the fifo and possibly in the DMA fifo. This 1427 * function clears the fifos and flushes any packets that came in as rx was 1428 * being enabled. 1429 **/ 1430void igb_rx_fifo_flush_82575(struct e1000_hw *hw) 1431{ 1432 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; 1433 int i, ms_wait; 1434 1435 if (hw->mac.type != e1000_82575 || 1436 !(rd32(E1000_MANC) & E1000_MANC_RCV_TCO_EN)) 1437 return; 1438 1439 /* Disable all RX queues */ 1440 for (i = 0; i < 4; i++) { 1441 rxdctl[i] = rd32(E1000_RXDCTL(i)); 1442 wr32(E1000_RXDCTL(i), 1443 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); 1444 } 1445 /* Poll all queues to verify they have shut down */ 1446 for (ms_wait = 0; ms_wait < 10; ms_wait++) { 1447 msleep(1); 1448 rx_enabled = 0; 1449 for (i = 0; i < 4; i++) 1450 rx_enabled |= rd32(E1000_RXDCTL(i)); 1451 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) 1452 break; 1453 } 1454 1455 if (ms_wait == 10) 1456 hw_dbg("Queue disable timed out after 10ms\n"); 1457 1458 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all 1459 * incoming packets are rejected. Set enable and wait 2ms so that 1460 * any packet that was coming in as RCTL.EN was set is flushed 1461 */ 1462 rfctl = rd32(E1000_RFCTL); 1463 wr32(E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); 1464 1465 rlpml = rd32(E1000_RLPML); 1466 wr32(E1000_RLPML, 0); 1467 1468 rctl = rd32(E1000_RCTL); 1469 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); 1470 temp_rctl |= E1000_RCTL_LPE; 1471 1472 wr32(E1000_RCTL, temp_rctl); 1473 wr32(E1000_RCTL, temp_rctl | E1000_RCTL_EN); 1474 wrfl(); 1475 msleep(2); 1476 1477 /* Enable RX queues that were previously enabled and restore our 1478 * previous state 1479 */ 1480 for (i = 0; i < 4; i++) 1481 wr32(E1000_RXDCTL(i), rxdctl[i]); 1482 wr32(E1000_RCTL, rctl); 1483 wrfl(); 1484 1485 wr32(E1000_RLPML, rlpml); 1486 wr32(E1000_RFCTL, rfctl); 1487 1488 /* Flush receive errors generated by workaround */ 1489 rd32(E1000_ROC); 1490 rd32(E1000_RNBC); 1491 rd32(E1000_MPC); 1492} 1493 1494/** 1495 * igb_set_pcie_completion_timeout - set pci-e completion timeout 1496 * @hw: pointer to the HW structure 1497 * 1498 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms, 1499 * however the hardware default for these parts is 500us to 1ms which is less 1500 * than the 10ms recommended by the pci-e spec. To address this we need to 1501 * increase the value to either 10ms to 200ms for capability version 1 config, 1502 * or 16ms to 55ms for version 2. 1503 **/ 1504static s32 igb_set_pcie_completion_timeout(struct e1000_hw *hw) 1505{ 1506 u32 gcr = rd32(E1000_GCR); 1507 s32 ret_val = 0; 1508 u16 pcie_devctl2; 1509 1510 /* only take action if timeout value is defaulted to 0 */ 1511 if (gcr & E1000_GCR_CMPL_TMOUT_MASK) 1512 goto out; 1513 1514 /* 1515 * if capababilities version is type 1 we can write the 1516 * timeout of 10ms to 200ms through the GCR register 1517 */ 1518 if (!(gcr & E1000_GCR_CAP_VER2)) { 1519 gcr |= E1000_GCR_CMPL_TMOUT_10ms; 1520 goto out; 1521 } 1522 1523 /* 1524 * for version 2 capabilities we need to write the config space 1525 * directly in order to set the completion timeout value for 1526 * 16ms to 55ms 1527 */ 1528 ret_val = igb_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1529 &pcie_devctl2); 1530 if (ret_val) 1531 goto out; 1532 1533 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms; 1534 1535 ret_val = igb_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2, 1536 &pcie_devctl2); 1537out: 1538 /* disable completion timeout resend */ 1539 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND; 1540 1541 wr32(E1000_GCR, gcr); 1542 return ret_val; 1543} 1544 1545/** 1546 * igb_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing 1547 * @hw: pointer to the hardware struct 1548 * @enable: state to enter, either enabled or disabled 1549 * @pf: Physical Function pool - do not set anti-spoofing for the PF 1550 * 1551 * enables/disables L2 switch anti-spoofing functionality. 1552 **/ 1553void igb_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf) 1554{ 1555 u32 dtxswc; 1556 1557 switch (hw->mac.type) { 1558 case e1000_82576: 1559 case e1000_i350: 1560 dtxswc = rd32(E1000_DTXSWC); 1561 if (enable) { 1562 dtxswc |= (E1000_DTXSWC_MAC_SPOOF_MASK | 1563 E1000_DTXSWC_VLAN_SPOOF_MASK); 1564 /* The PF can spoof - it has to in order to 1565 * support emulation mode NICs */ 1566 dtxswc ^= (1 << pf | 1 << (pf + MAX_NUM_VFS)); 1567 } else { 1568 dtxswc &= ~(E1000_DTXSWC_MAC_SPOOF_MASK | 1569 E1000_DTXSWC_VLAN_SPOOF_MASK); 1570 } 1571 wr32(E1000_DTXSWC, dtxswc); 1572 break; 1573 default: 1574 break; 1575 } 1576} 1577 1578/** 1579 * igb_vmdq_set_loopback_pf - enable or disable vmdq loopback 1580 * @hw: pointer to the hardware struct 1581 * @enable: state to enter, either enabled or disabled 1582 * 1583 * enables/disables L2 switch loopback functionality. 1584 **/ 1585void igb_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable) 1586{ 1587 u32 dtxswc; 1588 1589 switch (hw->mac.type) { 1590 case e1000_82576: 1591 dtxswc = rd32(E1000_DTXSWC); 1592 if (enable) 1593 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1594 else 1595 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1596 wr32(E1000_DTXSWC, dtxswc); 1597 break; 1598 case e1000_i350: 1599 dtxswc = rd32(E1000_TXSWC); 1600 if (enable) 1601 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1602 else 1603 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN; 1604 wr32(E1000_TXSWC, dtxswc); 1605 break; 1606 default: 1607 /* Currently no other hardware supports loopback */ 1608 break; 1609 } 1610 1611 1612} 1613 1614/** 1615 * igb_vmdq_set_replication_pf - enable or disable vmdq replication 1616 * @hw: pointer to the hardware struct 1617 * @enable: state to enter, either enabled or disabled 1618 * 1619 * enables/disables replication of packets across multiple pools. 1620 **/ 1621void igb_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable) 1622{ 1623 u32 vt_ctl = rd32(E1000_VT_CTL); 1624 1625 if (enable) 1626 vt_ctl |= E1000_VT_CTL_VM_REPL_EN; 1627 else 1628 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN; 1629 1630 wr32(E1000_VT_CTL, vt_ctl); 1631} 1632 1633/** 1634 * igb_read_phy_reg_82580 - Read 82580 MDI control register 1635 * @hw: pointer to the HW structure 1636 * @offset: register offset to be read 1637 * @data: pointer to the read data 1638 * 1639 * Reads the MDI control register in the PHY at offset and stores the 1640 * information read to data. 1641 **/ 1642static s32 igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data) 1643{ 1644 s32 ret_val; 1645 1646 1647 ret_val = hw->phy.ops.acquire(hw); 1648 if (ret_val) 1649 goto out; 1650 1651 ret_val = igb_read_phy_reg_mdic(hw, offset, data); 1652 1653 hw->phy.ops.release(hw); 1654 1655out: 1656 return ret_val; 1657} 1658 1659/** 1660 * igb_write_phy_reg_82580 - Write 82580 MDI control register 1661 * @hw: pointer to the HW structure 1662 * @offset: register offset to write to 1663 * @data: data to write to register at offset 1664 * 1665 * Writes data to MDI control register in the PHY at offset. 1666 **/ 1667static s32 igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data) 1668{ 1669 s32 ret_val; 1670 1671 1672 ret_val = hw->phy.ops.acquire(hw); 1673 if (ret_val) 1674 goto out; 1675 1676 ret_val = igb_write_phy_reg_mdic(hw, offset, data); 1677 1678 hw->phy.ops.release(hw); 1679 1680out: 1681 return ret_val; 1682} 1683 1684/** 1685 * igb_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits 1686 * @hw: pointer to the HW structure 1687 * 1688 * This resets the the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on 1689 * the values found in the EEPROM. This addresses an issue in which these 1690 * bits are not restored from EEPROM after reset. 1691 **/ 1692static s32 igb_reset_mdicnfg_82580(struct e1000_hw *hw) 1693{ 1694 s32 ret_val = 0; 1695 u32 mdicnfg; 1696 u16 nvm_data = 0; 1697 1698 if (hw->mac.type != e1000_82580) 1699 goto out; 1700 if (!igb_sgmii_active_82575(hw)) 1701 goto out; 1702 1703 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 1704 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 1705 &nvm_data); 1706 if (ret_val) { 1707 hw_dbg("NVM Read Error\n"); 1708 goto out; 1709 } 1710 1711 mdicnfg = rd32(E1000_MDICNFG); 1712 if (nvm_data & NVM_WORD24_EXT_MDIO) 1713 mdicnfg |= E1000_MDICNFG_EXT_MDIO; 1714 if (nvm_data & NVM_WORD24_COM_MDIO) 1715 mdicnfg |= E1000_MDICNFG_COM_MDIO; 1716 wr32(E1000_MDICNFG, mdicnfg); 1717out: 1718 return ret_val; 1719} 1720 1721/** 1722 * igb_reset_hw_82580 - Reset hardware 1723 * @hw: pointer to the HW structure 1724 * 1725 * This resets function or entire device (all ports, etc.) 1726 * to a known state. 1727 **/ 1728static s32 igb_reset_hw_82580(struct e1000_hw *hw) 1729{ 1730 s32 ret_val = 0; 1731 /* BH SW mailbox bit in SW_FW_SYNC */ 1732 u16 swmbsw_mask = E1000_SW_SYNCH_MB; 1733 u32 ctrl, icr; 1734 bool global_device_reset = hw->dev_spec._82575.global_device_reset; 1735 1736 1737 hw->dev_spec._82575.global_device_reset = false; 1738 1739 /* Get current control state. */ 1740 ctrl = rd32(E1000_CTRL); 1741 1742 /* 1743 * Prevent the PCI-E bus from sticking if there is no TLP connection 1744 * on the last TLP read/write transaction when MAC is reset. 1745 */ 1746 ret_val = igb_disable_pcie_master(hw); 1747 if (ret_val) 1748 hw_dbg("PCI-E Master disable polling has failed.\n"); 1749 1750 hw_dbg("Masking off all interrupts\n"); 1751 wr32(E1000_IMC, 0xffffffff); 1752 wr32(E1000_RCTL, 0); 1753 wr32(E1000_TCTL, E1000_TCTL_PSP); 1754 wrfl(); 1755 1756 msleep(10); 1757 1758 /* Determine whether or not a global dev reset is requested */ 1759 if (global_device_reset && 1760 igb_acquire_swfw_sync_82575(hw, swmbsw_mask)) 1761 global_device_reset = false; 1762 1763 if (global_device_reset && 1764 !(rd32(E1000_STATUS) & E1000_STAT_DEV_RST_SET)) 1765 ctrl |= E1000_CTRL_DEV_RST; 1766 else 1767 ctrl |= E1000_CTRL_RST; 1768 1769 wr32(E1000_CTRL, ctrl); 1770 wrfl(); 1771 1772 /* Add delay to insure DEV_RST has time to complete */ 1773 if (global_device_reset) 1774 msleep(5); 1775 1776 ret_val = igb_get_auto_rd_done(hw); 1777 if (ret_val) { 1778 /* 1779 * When auto config read does not complete, do not 1780 * return with an error. This can happen in situations 1781 * where there is no eeprom and prevents getting link. 1782 */ 1783 hw_dbg("Auto Read Done did not complete\n"); 1784 } 1785 1786 /* If EEPROM is not present, run manual init scripts */ 1787 if ((rd32(E1000_EECD) & E1000_EECD_PRES) == 0) 1788 igb_reset_init_script_82575(hw); 1789 1790 /* clear global device reset status bit */ 1791 wr32(E1000_STATUS, E1000_STAT_DEV_RST_SET); 1792 1793 /* Clear any pending interrupt events. */ 1794 wr32(E1000_IMC, 0xffffffff); 1795 icr = rd32(E1000_ICR); 1796 1797 ret_val = igb_reset_mdicnfg_82580(hw); 1798 if (ret_val) 1799 hw_dbg("Could not reset MDICNFG based on EEPROM\n"); 1800 1801 /* Install any alternate MAC address into RAR0 */ 1802 ret_val = igb_check_alt_mac_addr(hw); 1803 1804 /* Release semaphore */ 1805 if (global_device_reset) 1806 igb_release_swfw_sync_82575(hw, swmbsw_mask); 1807 1808 return ret_val; 1809} 1810 1811/** 1812 * igb_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size 1813 * @data: data received by reading RXPBS register 1814 * 1815 * The 82580 uses a table based approach for packet buffer allocation sizes. 1816 * This function converts the retrieved value into the correct table value 1817 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 1818 * 0x0 36 72 144 1 2 4 8 16 1819 * 0x8 35 70 140 rsv rsv rsv rsv rsv 1820 */ 1821u16 igb_rxpbs_adjust_82580(u32 data) 1822{ 1823 u16 ret_val = 0; 1824 1825 if (data < E1000_82580_RXPBS_TABLE_SIZE) 1826 ret_val = e1000_82580_rxpbs_table[data]; 1827 1828 return ret_val; 1829} 1830 1831/** 1832 * igb_validate_nvm_checksum_with_offset - Validate EEPROM 1833 * checksum 1834 * @hw: pointer to the HW structure 1835 * @offset: offset in words of the checksum protected region 1836 * 1837 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 1838 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 1839 **/ 1840static s32 igb_validate_nvm_checksum_with_offset(struct e1000_hw *hw, 1841 u16 offset) 1842{ 1843 s32 ret_val = 0; 1844 u16 checksum = 0; 1845 u16 i, nvm_data; 1846 1847 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) { 1848 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 1849 if (ret_val) { 1850 hw_dbg("NVM Read Error\n"); 1851 goto out; 1852 } 1853 checksum += nvm_data; 1854 } 1855 1856 if (checksum != (u16) NVM_SUM) { 1857 hw_dbg("NVM Checksum Invalid\n"); 1858 ret_val = -E1000_ERR_NVM; 1859 goto out; 1860 } 1861 1862out: 1863 return ret_val; 1864} 1865 1866/** 1867 * igb_update_nvm_checksum_with_offset - Update EEPROM 1868 * checksum 1869 * @hw: pointer to the HW structure 1870 * @offset: offset in words of the checksum protected region 1871 * 1872 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 1873 * up to the checksum. Then calculates the EEPROM checksum and writes the 1874 * value to the EEPROM. 1875 **/ 1876static s32 igb_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset) 1877{ 1878 s32 ret_val; 1879 u16 checksum = 0; 1880 u16 i, nvm_data; 1881 1882 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) { 1883 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 1884 if (ret_val) { 1885 hw_dbg("NVM Read Error while updating checksum.\n"); 1886 goto out; 1887 } 1888 checksum += nvm_data; 1889 } 1890 checksum = (u16) NVM_SUM - checksum; 1891 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1, 1892 &checksum); 1893 if (ret_val) 1894 hw_dbg("NVM Write Error while updating checksum.\n"); 1895 1896out: 1897 return ret_val; 1898} 1899 1900/** 1901 * igb_validate_nvm_checksum_82580 - Validate EEPROM checksum 1902 * @hw: pointer to the HW structure 1903 * 1904 * Calculates the EEPROM section checksum by reading/adding each word of 1905 * the EEPROM and then verifies that the sum of the EEPROM is 1906 * equal to 0xBABA. 1907 **/ 1908static s32 igb_validate_nvm_checksum_82580(struct e1000_hw *hw) 1909{ 1910 s32 ret_val = 0; 1911 u16 eeprom_regions_count = 1; 1912 u16 j, nvm_data; 1913 u16 nvm_offset; 1914 1915 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 1916 if (ret_val) { 1917 hw_dbg("NVM Read Error\n"); 1918 goto out; 1919 } 1920 1921 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) { 1922 /* if checksums compatibility bit is set validate checksums 1923 * for all 4 ports. */ 1924 eeprom_regions_count = 4; 1925 } 1926 1927 for (j = 0; j < eeprom_regions_count; j++) { 1928 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 1929 ret_val = igb_validate_nvm_checksum_with_offset(hw, 1930 nvm_offset); 1931 if (ret_val != 0) 1932 goto out; 1933 } 1934 1935out: 1936 return ret_val; 1937} 1938 1939/** 1940 * igb_update_nvm_checksum_82580 - Update EEPROM checksum 1941 * @hw: pointer to the HW structure 1942 * 1943 * Updates the EEPROM section checksums for all 4 ports by reading/adding 1944 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 1945 * checksum and writes the value to the EEPROM. 1946 **/ 1947static s32 igb_update_nvm_checksum_82580(struct e1000_hw *hw) 1948{ 1949 s32 ret_val; 1950 u16 j, nvm_data; 1951 u16 nvm_offset; 1952 1953 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data); 1954 if (ret_val) { 1955 hw_dbg("NVM Read Error while updating checksum" 1956 " compatibility bit.\n"); 1957 goto out; 1958 } 1959 1960 if ((nvm_data & NVM_COMPATIBILITY_BIT_MASK) == 0) { 1961 /* set compatibility bit to validate checksums appropriately */ 1962 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK; 1963 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1, 1964 &nvm_data); 1965 if (ret_val) { 1966 hw_dbg("NVM Write Error while updating checksum" 1967 " compatibility bit.\n"); 1968 goto out; 1969 } 1970 } 1971 1972 for (j = 0; j < 4; j++) { 1973 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 1974 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); 1975 if (ret_val) 1976 goto out; 1977 } 1978 1979out: 1980 return ret_val; 1981} 1982 1983/** 1984 * igb_validate_nvm_checksum_i350 - Validate EEPROM checksum 1985 * @hw: pointer to the HW structure 1986 * 1987 * Calculates the EEPROM section checksum by reading/adding each word of 1988 * the EEPROM and then verifies that the sum of the EEPROM is 1989 * equal to 0xBABA. 1990 **/ 1991static s32 igb_validate_nvm_checksum_i350(struct e1000_hw *hw) 1992{ 1993 s32 ret_val = 0; 1994 u16 j; 1995 u16 nvm_offset; 1996 1997 for (j = 0; j < 4; j++) { 1998 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 1999 ret_val = igb_validate_nvm_checksum_with_offset(hw, 2000 nvm_offset); 2001 if (ret_val != 0) 2002 goto out; 2003 } 2004 2005out: 2006 return ret_val; 2007} 2008 2009/** 2010 * igb_update_nvm_checksum_i350 - Update EEPROM checksum 2011 * @hw: pointer to the HW structure 2012 * 2013 * Updates the EEPROM section checksums for all 4 ports by reading/adding 2014 * each word of the EEPROM up to the checksum. Then calculates the EEPROM 2015 * checksum and writes the value to the EEPROM. 2016 **/ 2017static s32 igb_update_nvm_checksum_i350(struct e1000_hw *hw) 2018{ 2019 s32 ret_val = 0; 2020 u16 j; 2021 u16 nvm_offset; 2022 2023 for (j = 0; j < 4; j++) { 2024 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j); 2025 ret_val = igb_update_nvm_checksum_with_offset(hw, nvm_offset); 2026 if (ret_val != 0) 2027 goto out; 2028 } 2029 2030out: 2031 return ret_val; 2032} 2033 2034/** 2035 * igb_set_eee_i350 - Enable/disable EEE support 2036 * @hw: pointer to the HW structure 2037 * 2038 * Enable/disable EEE based on setting in dev_spec structure. 2039 * 2040 **/ 2041s32 igb_set_eee_i350(struct e1000_hw *hw) 2042{ 2043 s32 ret_val = 0; 2044 u32 ipcnfg, eeer, ctrl_ext; 2045 2046 ctrl_ext = rd32(E1000_CTRL_EXT); 2047 if ((hw->mac.type != e1000_i350) || 2048 (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK)) 2049 goto out; 2050 ipcnfg = rd32(E1000_IPCNFG); 2051 eeer = rd32(E1000_EEER); 2052 2053 /* enable or disable per user setting */ 2054 if (!(hw->dev_spec._82575.eee_disable)) { 2055 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | 2056 E1000_IPCNFG_EEE_100M_AN); 2057 eeer |= (E1000_EEER_TX_LPI_EN | 2058 E1000_EEER_RX_LPI_EN | 2059 E1000_EEER_LPI_FC); 2060 2061 } else { 2062 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | 2063 E1000_IPCNFG_EEE_100M_AN); 2064 eeer &= ~(E1000_EEER_TX_LPI_EN | 2065 E1000_EEER_RX_LPI_EN | 2066 E1000_EEER_LPI_FC); 2067 } 2068 wr32(E1000_IPCNFG, ipcnfg); 2069 wr32(E1000_EEER, eeer); 2070out: 2071 2072 return ret_val; 2073} 2074 2075static struct e1000_mac_operations e1000_mac_ops_82575 = { 2076 .init_hw = igb_init_hw_82575, 2077 .check_for_link = igb_check_for_link_82575, 2078 .rar_set = igb_rar_set, 2079 .read_mac_addr = igb_read_mac_addr_82575, 2080 .get_speed_and_duplex = igb_get_speed_and_duplex_copper, 2081}; 2082 2083static struct e1000_phy_operations e1000_phy_ops_82575 = { 2084 .acquire = igb_acquire_phy_82575, 2085 .get_cfg_done = igb_get_cfg_done_82575, 2086 .release = igb_release_phy_82575, 2087}; 2088 2089static struct e1000_nvm_operations e1000_nvm_ops_82575 = { 2090 .acquire = igb_acquire_nvm_82575, 2091 .read = igb_read_nvm_eerd, 2092 .release = igb_release_nvm_82575, 2093 .write = igb_write_nvm_spi, 2094}; 2095 2096const struct e1000_info e1000_82575_info = { 2097 .get_invariants = igb_get_invariants_82575, 2098 .mac_ops = &e1000_mac_ops_82575, 2099 .phy_ops = &e1000_phy_ops_82575, 2100 .nvm_ops = &e1000_nvm_ops_82575, 2101}; 2102 2103