e1000_defines.h revision 27dff8b2f680ce966b5d959be9d69dd0edd92e3b
1/* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24#ifndef _E1000_DEFINES_H_ 25#define _E1000_DEFINES_H_ 26 27/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 28#define REQ_TX_DESCRIPTOR_MULTIPLE 8 29#define REQ_RX_DESCRIPTOR_MULTIPLE 8 30 31/* Definitions for power management and wakeup registers */ 32/* Wake Up Control */ 33#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 34 35/* Wake Up Filter Control */ 36#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 37#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 38#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 39#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 40#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 41 42/* Extended Device Control */ 43#define E1000_CTRL_EXT_SDP2_DATA 0x00000040 /* Value of SW Defineable Pin 2 */ 44#define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Defineable Pin 3 */ 45#define E1000_CTRL_EXT_SDP2_DIR 0x00000400 /* SDP2 Data direction */ 46#define E1000_CTRL_EXT_SDP3_DIR 0x00000800 /* SDP3 Data direction */ 47 48/* Physical Func Reset Done Indication */ 49#define E1000_CTRL_EXT_PFRSTD 0x00004000 50#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 51#define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 52#define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 53#define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 54#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 55#define E1000_CTRL_EXT_EIAME 0x01000000 56#define E1000_CTRL_EXT_IRCA 0x00000001 57/* Interrupt delay cancellation */ 58/* Driver loaded bit for FW */ 59#define E1000_CTRL_EXT_DRV_LOAD 0x10000000 60/* Interrupt acknowledge Auto-mask */ 61/* Clear Interrupt timers after IMS clear */ 62/* packet buffer parity error detection enabled */ 63/* descriptor FIFO parity error detection enable */ 64#define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 65#define E1000_I2CCMD_REG_ADDR_SHIFT 16 66#define E1000_I2CCMD_PHY_ADDR_SHIFT 24 67#define E1000_I2CCMD_OPCODE_READ 0x08000000 68#define E1000_I2CCMD_OPCODE_WRITE 0x00000000 69#define E1000_I2CCMD_READY 0x20000000 70#define E1000_I2CCMD_ERROR 0x80000000 71#define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) 72#define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) 73#define E1000_MAX_SGMII_PHY_REG_ADDR 255 74#define E1000_I2CCMD_PHY_TIMEOUT 200 75#define E1000_IVAR_VALID 0x80 76#define E1000_GPIE_NSICR 0x00000001 77#define E1000_GPIE_MSIX_MODE 0x00000010 78#define E1000_GPIE_EIAME 0x40000000 79#define E1000_GPIE_PBA 0x80000000 80 81/* Receive Descriptor bit definitions */ 82#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 83#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 84#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 85#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 86#define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 87#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 88#define E1000_RXD_STAT_TS 0x10000 /* Pkt was time stamped */ 89 90#define E1000_RXDEXT_STATERR_LB 0x00040000 91#define E1000_RXDEXT_STATERR_CE 0x01000000 92#define E1000_RXDEXT_STATERR_SE 0x02000000 93#define E1000_RXDEXT_STATERR_SEQ 0x04000000 94#define E1000_RXDEXT_STATERR_CXE 0x10000000 95#define E1000_RXDEXT_STATERR_TCPE 0x20000000 96#define E1000_RXDEXT_STATERR_IPE 0x40000000 97#define E1000_RXDEXT_STATERR_RXE 0x80000000 98 99/* Same mask, but for extended and packet split descriptors */ 100#define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 101 E1000_RXDEXT_STATERR_CE | \ 102 E1000_RXDEXT_STATERR_SE | \ 103 E1000_RXDEXT_STATERR_SEQ | \ 104 E1000_RXDEXT_STATERR_CXE | \ 105 E1000_RXDEXT_STATERR_RXE) 106 107#define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 108#define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 109#define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 110#define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 111#define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 112 113 114/* Management Control */ 115#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 116#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 117#define E1000_MANC_EN_BMC2OS 0x10000000 /* OSBMC is Enabled or not */ 118/* Enable Neighbor Discovery Filtering */ 119#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 120#define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 121/* Enable MAC address filtering */ 122#define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 123 124/* Receive Control */ 125#define E1000_RCTL_EN 0x00000002 /* enable */ 126#define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 127#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 128#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 129#define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 130#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 131#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 132#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 133#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 134#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 135#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 136#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 137#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 138#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 139#define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ 140#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 141#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 142 143/* Use byte values for the following shift parameters 144 * Usage: 145 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 146 * E1000_PSRCTL_BSIZE0_MASK) | 147 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 148 * E1000_PSRCTL_BSIZE1_MASK) | 149 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 150 * E1000_PSRCTL_BSIZE2_MASK) | 151 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 152 * E1000_PSRCTL_BSIZE3_MASK)) 153 * where value0 = [128..16256], default=256 154 * value1 = [1024..64512], default=4096 155 * value2 = [0..64512], default=4096 156 * value3 = [0..64512], default=0 157 */ 158 159#define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 160#define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 161#define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 162#define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 163 164#define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 165#define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 166#define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 167#define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 168 169/* SWFW_SYNC Definitions */ 170#define E1000_SWFW_EEP_SM 0x1 171#define E1000_SWFW_PHY0_SM 0x2 172#define E1000_SWFW_PHY1_SM 0x4 173#define E1000_SWFW_PHY2_SM 0x20 174#define E1000_SWFW_PHY3_SM 0x40 175 176/* FACTPS Definitions */ 177/* Device Control */ 178#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 179#define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 180#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 181#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 182#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 183#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 184#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 185#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 186#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 187#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 188#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 189/* Defined polarity of Dock/Undock indication in SDP[0] */ 190/* Reset both PHY ports, through PHYRST_N pin */ 191/* enable link status from external LINK_0 and LINK_1 pins */ 192#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 193#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 194#define E1000_CTRL_SDP0_DIR 0x00400000 /* SDP0 Data direction */ 195#define E1000_CTRL_SDP1_DIR 0x00800000 /* SDP1 Data direction */ 196#define E1000_CTRL_RST 0x04000000 /* Global reset */ 197#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 198#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 199#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 200#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 201/* Initiate an interrupt to manageability engine */ 202#define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 203 204/* Bit definitions for the Management Data IO (MDIO) and Management Data 205 * Clock (MDC) pins in the Device Control Register. 206 */ 207 208#define E1000_CONNSW_ENRGSRC 0x4 209#define E1000_CONNSW_PHYSD 0x400 210#define E1000_CONNSW_PHY_PDN 0x800 211#define E1000_CONNSW_SERDESD 0x200 212#define E1000_CONNSW_AUTOSENSE_CONF 0x2 213#define E1000_CONNSW_AUTOSENSE_EN 0x1 214#define E1000_PCS_CFG_PCS_EN 8 215#define E1000_PCS_LCTL_FLV_LINK_UP 1 216#define E1000_PCS_LCTL_FSV_100 2 217#define E1000_PCS_LCTL_FSV_1000 4 218#define E1000_PCS_LCTL_FDV_FULL 8 219#define E1000_PCS_LCTL_FSD 0x10 220#define E1000_PCS_LCTL_FORCE_LINK 0x20 221#define E1000_PCS_LCTL_FORCE_FCTRL 0x80 222#define E1000_PCS_LCTL_AN_ENABLE 0x10000 223#define E1000_PCS_LCTL_AN_RESTART 0x20000 224#define E1000_PCS_LCTL_AN_TIMEOUT 0x40000 225#define E1000_ENABLE_SERDES_LOOPBACK 0x0410 226 227#define E1000_PCS_LSTS_LINK_OK 1 228#define E1000_PCS_LSTS_SPEED_100 2 229#define E1000_PCS_LSTS_SPEED_1000 4 230#define E1000_PCS_LSTS_DUPLEX_FULL 8 231#define E1000_PCS_LSTS_SYNK_OK 0x10 232 233/* Device Status */ 234#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 235#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 236#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 237#define E1000_STATUS_FUNC_SHIFT 2 238#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 239#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 240#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 241#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 242/* Change in Dock/Undock state. Clear on write '0'. */ 243/* Status of Master requests. */ 244#define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 245/* BMC external code execution disabled */ 246 247#define E1000_STATUS_2P5_SKU 0x00001000 /* Val of 2.5GBE SKU strap */ 248#define E1000_STATUS_2P5_SKU_OVER 0x00002000 /* Val of 2.5GBE SKU Over */ 249/* Constants used to intrepret the masked PCI-X bus speed. */ 250 251#define SPEED_10 10 252#define SPEED_100 100 253#define SPEED_1000 1000 254#define SPEED_2500 2500 255#define HALF_DUPLEX 1 256#define FULL_DUPLEX 2 257 258 259#define ADVERTISE_10_HALF 0x0001 260#define ADVERTISE_10_FULL 0x0002 261#define ADVERTISE_100_HALF 0x0004 262#define ADVERTISE_100_FULL 0x0008 263#define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 264#define ADVERTISE_1000_FULL 0x0020 265 266/* 1000/H is not supported, nor spec-compliant. */ 267#define E1000_ALL_SPEED_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 268 ADVERTISE_100_HALF | ADVERTISE_100_FULL | \ 269 ADVERTISE_1000_FULL) 270#define E1000_ALL_NOT_GIG (ADVERTISE_10_HALF | ADVERTISE_10_FULL | \ 271 ADVERTISE_100_HALF | ADVERTISE_100_FULL) 272#define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 273#define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 274#define E1000_ALL_FULL_DUPLEX (ADVERTISE_10_FULL | ADVERTISE_100_FULL | \ 275 ADVERTISE_1000_FULL) 276#define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 277 278#define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 279 280/* LED Control */ 281#define E1000_LEDCTL_LED0_MODE_SHIFT 0 282#define E1000_LEDCTL_LED0_BLINK 0x00000080 283#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 284#define E1000_LEDCTL_LED0_IVRT 0x00000040 285 286#define E1000_LEDCTL_MODE_LED_ON 0xE 287#define E1000_LEDCTL_MODE_LED_OFF 0xF 288 289/* Transmit Descriptor bit definitions */ 290#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 291#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 292#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 293#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 294#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 295#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 296#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 297/* Extended desc bits for Linksec and timesync */ 298 299/* Transmit Control */ 300#define E1000_TCTL_EN 0x00000002 /* enable tx */ 301#define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 302#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 303#define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 304#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 305 306/* DMA Coalescing register fields */ 307#define E1000_DMACR_DMACWT_MASK 0x00003FFF /* DMA Coal Watchdog Timer */ 308#define E1000_DMACR_DMACTHR_MASK 0x00FF0000 /* DMA Coal Rx Threshold */ 309#define E1000_DMACR_DMACTHR_SHIFT 16 310#define E1000_DMACR_DMAC_LX_MASK 0x30000000 /* Lx when no PCIe trans */ 311#define E1000_DMACR_DMAC_LX_SHIFT 28 312#define E1000_DMACR_DMAC_EN 0x80000000 /* Enable DMA Coalescing */ 313/* DMA Coalescing BMC-to-OS Watchdog Enable */ 314#define E1000_DMACR_DC_BMC2OSW_EN 0x00008000 315 316#define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coal Tx Threshold */ 317 318#define E1000_DMCTLX_TTLX_MASK 0x00000FFF /* Time to LX request */ 319 320#define E1000_DMCRTRH_UTRESH_MASK 0x0007FFFF /* Rx Traffic Rate Thresh */ 321#define E1000_DMCRTRH_LRPRCW 0x80000000 /* Rx pkt rate curr window */ 322 323#define E1000_DMCCNT_CCOUNT_MASK 0x01FFFFFF /* DMA Coal Rx Current Cnt */ 324 325#define E1000_FCRTC_RTH_COAL_MASK 0x0003FFF0 /* FC Rx Thresh High val */ 326#define E1000_FCRTC_RTH_COAL_SHIFT 4 327#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power decision */ 328 329/* Timestamp in Rx buffer */ 330#define E1000_RXPBS_CFG_TS_EN 0x80000000 331 332#define I210_RXPBSIZE_DEFAULT 0x000000A2 /* RXPBSIZE default */ 333#define I210_TXPBSIZE_DEFAULT 0x04000014 /* TXPBSIZE default */ 334 335/* SerDes Control */ 336#define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 337 338/* Receive Checksum Control */ 339#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 340#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 341#define E1000_RXCSUM_CRCOFL 0x00000800 /* CRC32 offload enable */ 342#define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 343 344/* Header split receive */ 345#define E1000_RFCTL_LEF 0x00040000 346 347/* Collision related configuration parameters */ 348#define E1000_COLLISION_THRESHOLD 15 349#define E1000_CT_SHIFT 4 350#define E1000_COLLISION_DISTANCE 63 351#define E1000_COLD_SHIFT 12 352 353/* Ethertype field values */ 354#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 355 356#define MAX_JUMBO_FRAME_SIZE 0x3F00 357 358/* PBA constants */ 359#define E1000_PBA_34K 0x0022 360#define E1000_PBA_64K 0x0040 /* 64KB */ 361 362/* SW Semaphore Register */ 363#define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 364#define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 365 366/* Interrupt Cause Read */ 367#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 368#define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 369#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 370#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 371#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 372#define E1000_ICR_VMMB 0x00000100 /* VM MB event */ 373#define E1000_ICR_TS 0x00080000 /* Time Sync Interrupt */ 374#define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 375/* If this bit asserted, the driver should claim the interrupt */ 376#define E1000_ICR_INT_ASSERTED 0x80000000 377/* LAN connected device generates an interrupt */ 378#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */ 379 380/* Extended Interrupt Cause Read */ 381#define E1000_EICR_RX_QUEUE0 0x00000001 /* Rx Queue 0 Interrupt */ 382#define E1000_EICR_RX_QUEUE1 0x00000002 /* Rx Queue 1 Interrupt */ 383#define E1000_EICR_RX_QUEUE2 0x00000004 /* Rx Queue 2 Interrupt */ 384#define E1000_EICR_RX_QUEUE3 0x00000008 /* Rx Queue 3 Interrupt */ 385#define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */ 386#define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */ 387#define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */ 388#define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */ 389#define E1000_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 390/* TCP Timer */ 391 392/* This defines the bits that are set in the Interrupt Mask 393 * Set/Read Register. Each bit is documented below: 394 * o RXT0 = Receiver Timer Interrupt (ring 0) 395 * o TXDW = Transmit Descriptor Written Back 396 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 397 * o RXSEQ = Receive Sequence Error 398 * o LSC = Link Status Change 399 */ 400#define IMS_ENABLE_MASK ( \ 401 E1000_IMS_RXT0 | \ 402 E1000_IMS_TXDW | \ 403 E1000_IMS_RXDMT0 | \ 404 E1000_IMS_RXSEQ | \ 405 E1000_IMS_LSC | \ 406 E1000_IMS_DOUTSYNC) 407 408/* Interrupt Mask Set */ 409#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 410#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 411#define E1000_IMS_VMMB E1000_ICR_VMMB /* Mail box activity */ 412#define E1000_IMS_TS E1000_ICR_TS /* Time Sync Interrupt */ 413#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 414#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 415#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 416#define E1000_IMS_DRSTA E1000_ICR_DRSTA /* Device Reset Asserted */ 417#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */ 418 419/* Extended Interrupt Mask Set */ 420#define E1000_EIMS_OTHER E1000_EICR_OTHER /* Interrupt Cause Active */ 421 422/* Interrupt Cause Set */ 423#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 424#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 425#define E1000_ICS_DRSTA E1000_ICR_DRSTA /* Device Reset Aserted */ 426 427/* Extended Interrupt Cause Set */ 428/* E1000_EITR_CNT_IGNR is only for 82576 and newer */ 429#define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 430 431 432/* Transmit Descriptor Control */ 433/* Enable the counting of descriptors still to be processed. */ 434 435/* Flow Control Constants */ 436#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 437#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 438#define FLOW_CONTROL_TYPE 0x8808 439 440/* Transmit Config Word */ 441#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 442#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 443 444/* 802.1q VLAN Packet Size */ 445#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMA'd) */ 446#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 447 448/* Receive Address */ 449/* Number of high/low register pairs in the RAR. The RAR (Receive Address 450 * Registers) holds the directed and multicast addresses that we monitor. 451 * Technically, we have 16 spots. However, we reserve one of these spots 452 * (RAR[15]) for our directed address used by controllers with 453 * manageability enabled, allowing us room for 15 multicast addresses. 454 */ 455#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 456#define E1000_RAL_MAC_ADDR_LEN 4 457#define E1000_RAH_MAC_ADDR_LEN 2 458#define E1000_RAH_POOL_MASK 0x03FC0000 459#define E1000_RAH_POOL_1 0x00040000 460 461/* Error Codes */ 462#define E1000_SUCCESS 0 463#define E1000_ERR_NVM 1 464#define E1000_ERR_PHY 2 465#define E1000_ERR_CONFIG 3 466#define E1000_ERR_PARAM 4 467#define E1000_ERR_MAC_INIT 5 468#define E1000_ERR_RESET 9 469#define E1000_ERR_MASTER_REQUESTS_PENDING 10 470#define E1000_BLK_PHY_RESET 12 471#define E1000_ERR_SWFW_SYNC 13 472#define E1000_NOT_IMPLEMENTED 14 473#define E1000_ERR_MBX 15 474#define E1000_ERR_INVALID_ARGUMENT 16 475#define E1000_ERR_NO_SPACE 17 476#define E1000_ERR_NVM_PBA_SECTION 18 477#define E1000_ERR_INVM_VALUE_NOT_FOUND 19 478#define E1000_ERR_I2C 20 479 480/* Loop limit on how long we wait for auto-negotiation to complete */ 481#define COPPER_LINK_UP_LIMIT 10 482#define PHY_AUTO_NEG_LIMIT 45 483#define PHY_FORCE_LIMIT 20 484/* Number of 100 microseconds we wait for PCI Express master disable */ 485#define MASTER_DISABLE_TIMEOUT 800 486/* Number of milliseconds we wait for PHY configuration done after MAC reset */ 487#define PHY_CFG_TIMEOUT 100 488/* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 489/* Number of milliseconds for NVM auto read done after MAC reset. */ 490#define AUTO_READ_DONE_TIMEOUT 10 491 492/* Flow Control */ 493#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 494 495#define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */ 496#define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */ 497 498#define E1000_TSYNCRXCTL_VALID 0x00000001 /* rx timestamp valid */ 499#define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* rx type mask */ 500#define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 501#define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 502#define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 503#define E1000_TSYNCRXCTL_TYPE_ALL 0x08 504#define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 505#define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable rx timestampping */ 506 507#define E1000_TSYNCRXCFG_PTP_V1_CTRLT_MASK 0x000000FF 508#define E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE 0x00 509#define E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01 510#define E1000_TSYNCRXCFG_PTP_V1_FOLLOWUP_MESSAGE 0x02 511#define E1000_TSYNCRXCFG_PTP_V1_DELAY_RESP_MESSAGE 0x03 512#define E1000_TSYNCRXCFG_PTP_V1_MANAGEMENT_MESSAGE 0x04 513 514#define E1000_TSYNCRXCFG_PTP_V2_MSGID_MASK 0x00000F00 515#define E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE 0x0000 516#define E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE 0x0100 517#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_REQ_MESSAGE 0x0200 518#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_RESP_MESSAGE 0x0300 519#define E1000_TSYNCRXCFG_PTP_V2_FOLLOWUP_MESSAGE 0x0800 520#define E1000_TSYNCRXCFG_PTP_V2_DELAY_RESP_MESSAGE 0x0900 521#define E1000_TSYNCRXCFG_PTP_V2_PATH_DELAY_FOLLOWUP_MESSAGE 0x0A00 522#define E1000_TSYNCRXCFG_PTP_V2_ANNOUNCE_MESSAGE 0x0B00 523#define E1000_TSYNCRXCFG_PTP_V2_SIGNALLING_MESSAGE 0x0C00 524#define E1000_TSYNCRXCFG_PTP_V2_MANAGEMENT_MESSAGE 0x0D00 525 526#define E1000_TIMINCA_16NS_SHIFT 24 527 528/* Time Sync Interrupt Cause/Mask Register Bits */ 529 530#define TSINTR_SYS_WRAP (1 << 0) /* SYSTIM Wrap around. */ 531#define TSINTR_TXTS (1 << 1) /* Transmit Timestamp. */ 532#define TSINTR_RXTS (1 << 2) /* Receive Timestamp. */ 533#define TSINTR_TT0 (1 << 3) /* Target Time 0 Trigger. */ 534#define TSINTR_TT1 (1 << 4) /* Target Time 1 Trigger. */ 535#define TSINTR_AUTT0 (1 << 5) /* Auxiliary Timestamp 0 Taken. */ 536#define TSINTR_AUTT1 (1 << 6) /* Auxiliary Timestamp 1 Taken. */ 537#define TSINTR_TADJ (1 << 7) /* Time Adjust Done. */ 538 539#define TSYNC_INTERRUPTS TSINTR_TXTS 540#define E1000_TSICR_TXTS TSINTR_TXTS 541 542/* TSAUXC Configuration Bits */ 543#define TSAUXC_EN_TT0 (1 << 0) /* Enable target time 0. */ 544#define TSAUXC_EN_TT1 (1 << 1) /* Enable target time 1. */ 545#define TSAUXC_EN_CLK0 (1 << 2) /* Enable Configurable Frequency Clock 0. */ 546#define TSAUXC_SAMP_AUT0 (1 << 3) /* Latch SYSTIML/H into AUXSTMPL/0. */ 547#define TSAUXC_ST0 (1 << 4) /* Start Clock 0 Toggle on Target Time 0. */ 548#define TSAUXC_EN_CLK1 (1 << 5) /* Enable Configurable Frequency Clock 1. */ 549#define TSAUXC_SAMP_AUT1 (1 << 6) /* Latch SYSTIML/H into AUXSTMPL/1. */ 550#define TSAUXC_ST1 (1 << 7) /* Start Clock 1 Toggle on Target Time 1. */ 551#define TSAUXC_EN_TS0 (1 << 8) /* Enable hardware timestamp 0. */ 552#define TSAUXC_AUTT0 (1 << 9) /* Auxiliary Timestamp Taken. */ 553#define TSAUXC_EN_TS1 (1 << 10) /* Enable hardware timestamp 0. */ 554#define TSAUXC_AUTT1 (1 << 11) /* Auxiliary Timestamp Taken. */ 555#define TSAUXC_PLSG (1 << 17) /* Generate a pulse. */ 556#define TSAUXC_DISABLE (1 << 31) /* Disable SYSTIM Count Operation. */ 557 558/* SDP Configuration Bits */ 559#define AUX0_SEL_SDP0 (0 << 0) /* Assign SDP0 to auxiliary time stamp 0. */ 560#define AUX0_SEL_SDP1 (1 << 0) /* Assign SDP1 to auxiliary time stamp 0. */ 561#define AUX0_SEL_SDP2 (2 << 0) /* Assign SDP2 to auxiliary time stamp 0. */ 562#define AUX0_SEL_SDP3 (3 << 0) /* Assign SDP3 to auxiliary time stamp 0. */ 563#define AUX0_TS_SDP_EN (1 << 2) /* Enable auxiliary time stamp trigger 0. */ 564#define AUX1_SEL_SDP0 (0 << 3) /* Assign SDP0 to auxiliary time stamp 1. */ 565#define AUX1_SEL_SDP1 (1 << 3) /* Assign SDP1 to auxiliary time stamp 1. */ 566#define AUX1_SEL_SDP2 (2 << 3) /* Assign SDP2 to auxiliary time stamp 1. */ 567#define AUX1_SEL_SDP3 (3 << 3) /* Assign SDP3 to auxiliary time stamp 1. */ 568#define AUX1_TS_SDP_EN (1 << 5) /* Enable auxiliary time stamp trigger 1. */ 569#define TS_SDP0_SEL_TT0 (0 << 6) /* Target time 0 is output on SDP0. */ 570#define TS_SDP0_SEL_TT1 (1 << 6) /* Target time 1 is output on SDP0. */ 571#define TS_SDP0_SEL_FC0 (2 << 6) /* Freq clock 0 is output on SDP0. */ 572#define TS_SDP0_SEL_FC1 (3 << 6) /* Freq clock 1 is output on SDP0. */ 573#define TS_SDP0_EN (1 << 8) /* SDP0 is assigned to Tsync. */ 574#define TS_SDP1_SEL_TT0 (0 << 9) /* Target time 0 is output on SDP1. */ 575#define TS_SDP1_SEL_TT1 (1 << 9) /* Target time 1 is output on SDP1. */ 576#define TS_SDP1_SEL_FC0 (2 << 9) /* Freq clock 0 is output on SDP1. */ 577#define TS_SDP1_SEL_FC1 (3 << 9) /* Freq clock 1 is output on SDP1. */ 578#define TS_SDP1_EN (1 << 11) /* SDP1 is assigned to Tsync. */ 579#define TS_SDP2_SEL_TT0 (0 << 12) /* Target time 0 is output on SDP2. */ 580#define TS_SDP2_SEL_TT1 (1 << 12) /* Target time 1 is output on SDP2. */ 581#define TS_SDP2_SEL_FC0 (2 << 12) /* Freq clock 0 is output on SDP2. */ 582#define TS_SDP2_SEL_FC1 (3 << 12) /* Freq clock 1 is output on SDP2. */ 583#define TS_SDP2_EN (1 << 14) /* SDP2 is assigned to Tsync. */ 584#define TS_SDP3_SEL_TT0 (0 << 15) /* Target time 0 is output on SDP3. */ 585#define TS_SDP3_SEL_TT1 (1 << 15) /* Target time 1 is output on SDP3. */ 586#define TS_SDP3_SEL_FC0 (2 << 15) /* Freq clock 0 is output on SDP3. */ 587#define TS_SDP3_SEL_FC1 (3 << 15) /* Freq clock 1 is output on SDP3. */ 588#define TS_SDP3_EN (1 << 17) /* SDP3 is assigned to Tsync. */ 589 590#define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 591#define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 592#define E1000_MDICNFG_PHY_MASK 0x03E00000 593#define E1000_MDICNFG_PHY_SHIFT 21 594 595#define E1000_MEDIA_PORT_COPPER 1 596#define E1000_MEDIA_PORT_OTHER 2 597#define E1000_M88E1112_AUTO_COPPER_SGMII 0x2 598#define E1000_M88E1112_AUTO_COPPER_BASEX 0x3 599#define E1000_M88E1112_STATUS_LINK 0x0004 /* Interface Link Bit */ 600#define E1000_M88E1112_MAC_CTRL_1 0x10 601#define E1000_M88E1112_MAC_CTRL_1_MODE_MASK 0x0380 /* Mode Select */ 602#define E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT 7 603#define E1000_M88E1112_PAGE_ADDR 0x16 604#define E1000_M88E1112_STATUS 0x01 605 606/* PCI Express Control */ 607#define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 608#define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 609#define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 610#define E1000_GCR_CAP_VER2 0x00040000 611 612/* mPHY Address Control and Data Registers */ 613#define E1000_MPHY_ADDR_CTL 0x0024 /* mPHY Address Control Register */ 614#define E1000_MPHY_ADDR_CTL_OFFSET_MASK 0xFFFF0000 615#define E1000_MPHY_DATA 0x0E10 /* mPHY Data Register */ 616 617/* mPHY PCS CLK Register */ 618#define E1000_MPHY_PCS_CLK_REG_OFFSET 0x0004 /* mPHY PCS CLK AFE CSR Offset */ 619/* mPHY Near End Digital Loopback Override Bit */ 620#define E1000_MPHY_PCS_CLK_REG_DIGINELBEN 0x10 621 622#define E1000_PCS_LCTL_FORCE_FCTRL 0x80 623#define E1000_PCS_LSTS_AN_COMPLETE 0x10000 624 625/* PHY Control Register */ 626#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 627#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 628#define MII_CR_POWER_DOWN 0x0800 /* Power down */ 629#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 630#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 631#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 632#define MII_CR_SPEED_1000 0x0040 633#define MII_CR_SPEED_100 0x2000 634#define MII_CR_SPEED_10 0x0000 635 636/* PHY Status Register */ 637#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 638#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 639 640/* Autoneg Advertisement Register */ 641#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 642#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 643#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 644#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 645#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 646#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 647 648/* Link Partner Ability Register (Base Page) */ 649#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 650#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 651 652/* Autoneg Expansion Register */ 653 654/* 1000BASE-T Control Register */ 655#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 656#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 657#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 658 /* 0=Configure PHY as Slave */ 659#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 660 /* 0=Automatic Master/Slave config */ 661 662/* 1000BASE-T Status Register */ 663#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 664#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 665 666 667/* PHY 1000 MII Register/Bit Definitions */ 668/* PHY Registers defined by IEEE */ 669#define PHY_CONTROL 0x00 /* Control Register */ 670#define PHY_STATUS 0x01 /* Status Register */ 671#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 672#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 673#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 674#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 675#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 676#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 677 678/* NVM Control */ 679#define E1000_EECD_SK 0x00000001 /* NVM Clock */ 680#define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 681#define E1000_EECD_DI 0x00000004 /* NVM Data In */ 682#define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 683#define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 684#define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 685#define E1000_EECD_PRES 0x00000100 /* NVM Present */ 686/* NVM Addressing bits based on type 0=small, 1=large */ 687#define E1000_EECD_ADDR_BITS 0x00000400 688#define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 689#define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 690#define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 691#define E1000_EECD_SIZE_EX_SHIFT 11 692#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 693#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ 694#define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */ 695#define E1000_FLUDONE_ATTEMPTS 20000 696#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 697#define E1000_I210_FIFO_SEL_RX 0x00 698#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 699#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 700#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 701#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 702#define E1000_I210_FLASH_SECTOR_SIZE 0x1000 /* 4KB FLASH sector unit size */ 703/* Secure FLASH mode requires removing MSb */ 704#define E1000_I210_FW_PTR_MASK 0x7FFF 705/* Firmware code revision field word offset*/ 706#define E1000_I210_FW_VER_OFFSET 328 707#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */ 708#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/ 709#define E1000_FLUDONE_ATTEMPTS 20000 710#define E1000_EERD_EEWR_MAX_COUNT 512 /* buffered EEPROM words rw */ 711#define E1000_I210_FIFO_SEL_RX 0x00 712#define E1000_I210_FIFO_SEL_TX_QAV(_i) (0x02 + (_i)) 713#define E1000_I210_FIFO_SEL_TX_LEGACY E1000_I210_FIFO_SEL_TX_QAV(0) 714#define E1000_I210_FIFO_SEL_BMC2OS_TX 0x06 715#define E1000_I210_FIFO_SEL_BMC2OS_RX 0x01 716 717 718/* Offset to data in NVM read/write registers */ 719#define E1000_NVM_RW_REG_DATA 16 720#define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 721#define E1000_NVM_RW_REG_START 1 /* Start operation */ 722#define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 723#define E1000_NVM_POLL_READ 0 /* Flag for polling for read complete */ 724 725/* NVM Word Offsets */ 726#define NVM_COMPAT 0x0003 727#define NVM_ID_LED_SETTINGS 0x0004 /* SERDES output amplitude */ 728#define NVM_VERSION 0x0005 729#define NVM_INIT_CONTROL2_REG 0x000F 730#define NVM_INIT_CONTROL3_PORT_B 0x0014 731#define NVM_INIT_CONTROL3_PORT_A 0x0024 732#define NVM_ALT_MAC_ADDR_PTR 0x0037 733#define NVM_CHECKSUM_REG 0x003F 734#define NVM_COMPATIBILITY_REG_3 0x0003 735#define NVM_COMPATIBILITY_BIT_MASK 0x8000 736#define NVM_MAC_ADDR 0x0000 737#define NVM_SUB_DEV_ID 0x000B 738#define NVM_SUB_VEN_ID 0x000C 739#define NVM_DEV_ID 0x000D 740#define NVM_VEN_ID 0x000E 741#define NVM_INIT_CTRL_2 0x000F 742#define NVM_INIT_CTRL_4 0x0013 743#define NVM_LED_1_CFG 0x001C 744#define NVM_LED_0_2_CFG 0x001F 745#define NVM_ETRACK_WORD 0x0042 746#define NVM_ETRACK_HIWORD 0x0043 747#define NVM_COMB_VER_OFF 0x0083 748#define NVM_COMB_VER_PTR 0x003d 749 750/* NVM version defines */ 751#define NVM_MAJOR_MASK 0xF000 752#define NVM_MINOR_MASK 0x0FF0 753#define NVM_IMAGE_ID_MASK 0x000F 754#define NVM_COMB_VER_MASK 0x00FF 755#define NVM_MAJOR_SHIFT 12 756#define NVM_MINOR_SHIFT 4 757#define NVM_COMB_VER_SHFT 8 758#define NVM_VER_INVALID 0xFFFF 759#define NVM_ETRACK_SHIFT 16 760#define NVM_ETRACK_VALID 0x8000 761#define NVM_NEW_DEC_MASK 0x0F00 762#define NVM_HEX_CONV 16 763#define NVM_HEX_TENS 10 764 765#define NVM_ETS_CFG 0x003E 766#define NVM_ETS_LTHRES_DELTA_MASK 0x07C0 767#define NVM_ETS_LTHRES_DELTA_SHIFT 6 768#define NVM_ETS_TYPE_MASK 0x0038 769#define NVM_ETS_TYPE_SHIFT 3 770#define NVM_ETS_TYPE_EMC 0x000 771#define NVM_ETS_NUM_SENSORS_MASK 0x0007 772#define NVM_ETS_DATA_LOC_MASK 0x3C00 773#define NVM_ETS_DATA_LOC_SHIFT 10 774#define NVM_ETS_DATA_INDEX_MASK 0x0300 775#define NVM_ETS_DATA_INDEX_SHIFT 8 776#define NVM_ETS_DATA_HTHRESH_MASK 0x00FF 777 778#define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 779#define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 780#define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 781#define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 782 783#define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0) 784 785/* Mask bits for fields in Word 0x24 of the NVM */ 786#define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 787#define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */ 788 789/* Mask bits for fields in Word 0x0f of the NVM */ 790#define NVM_WORD0F_PAUSE_MASK 0x3000 791#define NVM_WORD0F_ASM_DIR 0x2000 792 793/* Mask bits for fields in Word 0x1a of the NVM */ 794 795/* length of string needed to store part num */ 796#define E1000_PBANUM_LENGTH 11 797 798/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 799#define NVM_SUM 0xBABA 800 801#define NVM_PBA_OFFSET_0 8 802#define NVM_PBA_OFFSET_1 9 803#define NVM_RESERVED_WORD 0xFFFF 804#define NVM_PBA_PTR_GUARD 0xFAFA 805#define NVM_WORD_SIZE_BASE_SHIFT 6 806 807/* NVM Commands - Microwire */ 808 809/* NVM Commands - SPI */ 810#define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 811#define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 812#define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 813#define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 814#define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 815#define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 816 817/* SPI NVM Status Register */ 818#define NVM_STATUS_RDY_SPI 0x01 819 820/* Word definitions for ID LED Settings */ 821#define ID_LED_RESERVED_0000 0x0000 822#define ID_LED_RESERVED_FFFF 0xFFFF 823#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 824 (ID_LED_OFF1_OFF2 << 8) | \ 825 (ID_LED_DEF1_DEF2 << 4) | \ 826 (ID_LED_DEF1_DEF2)) 827#define ID_LED_DEF1_DEF2 0x1 828#define ID_LED_DEF1_ON2 0x2 829#define ID_LED_DEF1_OFF2 0x3 830#define ID_LED_ON1_DEF2 0x4 831#define ID_LED_ON1_ON2 0x5 832#define ID_LED_ON1_OFF2 0x6 833#define ID_LED_OFF1_DEF2 0x7 834#define ID_LED_OFF1_ON2 0x8 835#define ID_LED_OFF1_OFF2 0x9 836 837#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 838#define IGP_ACTIVITY_LED_ENABLE 0x0300 839#define IGP_LED3_MODE 0x07000000 840 841/* PCI/PCI-X/PCI-EX Config space */ 842#define PCIE_DEVICE_CONTROL2 0x28 843#define PCIE_DEVICE_CONTROL2_16ms 0x0005 844 845#define PHY_REVISION_MASK 0xFFFFFFF0 846#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 847#define MAX_PHY_MULTI_PAGE_REG 0xF 848 849/* Bit definitions for valid PHY IDs. */ 850/* I = Integrated 851 * E = External 852 */ 853#define M88E1111_I_PHY_ID 0x01410CC0 854#define M88E1112_E_PHY_ID 0x01410C90 855#define I347AT4_E_PHY_ID 0x01410DC0 856#define IGP03E1000_E_PHY_ID 0x02A80390 857#define I82580_I_PHY_ID 0x015403A0 858#define I350_I_PHY_ID 0x015403B0 859#define M88_VENDOR 0x0141 860#define I210_I_PHY_ID 0x01410C00 861#define M88E1543_E_PHY_ID 0x01410EA0 862 863/* M88E1000 Specific Registers */ 864#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 865#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 866#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 867 868#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 869#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 870 871/* M88E1000 PHY Specific Control Register */ 872#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 873/* 1=CLK125 low, 0=CLK125 toggling */ 874#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 875 /* Manual MDI configuration */ 876#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 877/* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 878#define M88E1000_PSCR_AUTO_X_1000T 0x0040 879/* Auto crossover enabled all speeds */ 880#define M88E1000_PSCR_AUTO_X_MODE 0x0060 881/* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold 882 * 0=Normal 10BASE-T Rx Threshold 883 */ 884/* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */ 885#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 886 887/* M88E1000 PHY Specific Status Register */ 888#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 889#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 890#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 891/* 0 = <50M 892 * 1 = 50-80M 893 * 2 = 80-110M 894 * 3 = 110-140M 895 * 4 = >140M 896 */ 897#define M88E1000_PSSR_CABLE_LENGTH 0x0380 898#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 899#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 900 901#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 902 903/* M88E1000 Extended PHY Specific Control Register */ 904/* 1 = Lost lock detect enabled. 905 * Will assert lost lock and bring 906 * link down if idle not seen 907 * within 1ms in 1000BASE-T 908 */ 909/* Number of times we will attempt to autonegotiate before downshifting if we 910 * are the master 911 */ 912#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 913#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 914/* Number of times we will attempt to autonegotiate before downshifting if we 915 * are the slave 916 */ 917#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 918#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 919#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 920 921/* Intel i347-AT4 Registers */ 922 923#define I347AT4_PCDL 0x10 /* PHY Cable Diagnostics Length */ 924#define I347AT4_PCDC 0x15 /* PHY Cable Diagnostics Control */ 925#define I347AT4_PAGE_SELECT 0x16 926 927/* i347-AT4 Extended PHY Specific Control Register */ 928 929/* Number of times we will attempt to autonegotiate before downshifting if we 930 * are the master 931 */ 932#define I347AT4_PSCR_DOWNSHIFT_ENABLE 0x0800 933#define I347AT4_PSCR_DOWNSHIFT_MASK 0x7000 934#define I347AT4_PSCR_DOWNSHIFT_1X 0x0000 935#define I347AT4_PSCR_DOWNSHIFT_2X 0x1000 936#define I347AT4_PSCR_DOWNSHIFT_3X 0x2000 937#define I347AT4_PSCR_DOWNSHIFT_4X 0x3000 938#define I347AT4_PSCR_DOWNSHIFT_5X 0x4000 939#define I347AT4_PSCR_DOWNSHIFT_6X 0x5000 940#define I347AT4_PSCR_DOWNSHIFT_7X 0x6000 941#define I347AT4_PSCR_DOWNSHIFT_8X 0x7000 942 943/* i347-AT4 PHY Cable Diagnostics Control */ 944#define I347AT4_PCDC_CABLE_LENGTH_UNIT 0x0400 /* 0=cm 1=meters */ 945 946/* Marvell 1112 only registers */ 947#define M88E1112_VCT_DSP_DISTANCE 0x001A 948 949/* M88EC018 Rev 2 specific DownShift settings */ 950#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 951#define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 952 953/* MDI Control */ 954#define E1000_MDIC_DATA_MASK 0x0000FFFF 955#define E1000_MDIC_REG_MASK 0x001F0000 956#define E1000_MDIC_REG_SHIFT 16 957#define E1000_MDIC_PHY_MASK 0x03E00000 958#define E1000_MDIC_PHY_SHIFT 21 959#define E1000_MDIC_OP_WRITE 0x04000000 960#define E1000_MDIC_OP_READ 0x08000000 961#define E1000_MDIC_READY 0x10000000 962#define E1000_MDIC_INT_EN 0x20000000 963#define E1000_MDIC_ERROR 0x40000000 964#define E1000_MDIC_DEST 0x80000000 965 966/* Thermal Sensor */ 967#define E1000_THSTAT_PWR_DOWN 0x00000001 /* Power Down Event */ 968#define E1000_THSTAT_LINK_THROTTLE 0x00000002 /* Link Speed Throttle Event */ 969 970/* Energy Efficient Ethernet */ 971#define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* EEE Enable 1G AN */ 972#define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* EEE Enable 100M AN */ 973#define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */ 974#define E1000_EEER_RX_LPI_EN 0x00020000 /* EEE Rx LPI Enable */ 975#define E1000_EEER_FRC_AN 0x10000000 /* Enable EEE in loopback */ 976#define E1000_EEER_LPI_FC 0x00040000 /* EEE Enable on FC */ 977#define E1000_EEE_SU_LPI_CLK_STP 0X00800000 /* EEE LPI Clock Stop */ 978#define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 979#define E1000_EEE_LP_ADV_ADDR_I350 0x040F /* EEE LP Advertisement */ 980#define E1000_EEE_LP_ADV_DEV_I210 7 /* EEE LP Adv Device */ 981#define E1000_EEE_LP_ADV_ADDR_I210 61 /* EEE LP Adv Register */ 982#define E1000_MMDAC_FUNC_DATA 0x4000 /* Data, no post increment */ 983#define E1000_M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ 984#define E1000_M88E1543_EEE_CTRL_1 0x0 985#define E1000_M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ 986#define E1000_EEE_ADV_DEV_I354 7 987#define E1000_EEE_ADV_ADDR_I354 60 988#define E1000_EEE_ADV_100_SUPPORTED (1 << 1) /* 100BaseTx EEE Supported */ 989#define E1000_EEE_ADV_1000_SUPPORTED (1 << 2) /* 1000BaseT EEE Supported */ 990#define E1000_PCS_STATUS_DEV_I354 3 991#define E1000_PCS_STATUS_ADDR_I354 1 992#define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */ 993#define E1000_PCS_STATUS_RX_LPI_RCVD 0x0400 994#define E1000_PCS_STATUS_TX_LPI_RCVD 0x0800 995 996/* SerDes Control */ 997#define E1000_GEN_CTL_READY 0x80000000 998#define E1000_GEN_CTL_ADDRESS_SHIFT 8 999#define E1000_GEN_POLL_TIMEOUT 640 1000 1001#define E1000_VFTA_ENTRY_SHIFT 5 1002#define E1000_VFTA_ENTRY_MASK 0x7F 1003#define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 1004 1005/* DMA Coalescing register fields */ 1006#define E1000_PCIEMISC_LX_DECISION 0x00000080 /* Lx power on DMA coal */ 1007 1008/* Tx Rate-Scheduler Config fields */ 1009#define E1000_RTTBCNRC_RS_ENA 0x80000000 1010#define E1000_RTTBCNRC_RF_DEC_MASK 0x00003FFF 1011#define E1000_RTTBCNRC_RF_INT_SHIFT 14 1012#define E1000_RTTBCNRC_RF_INT_MASK \ 1013 (E1000_RTTBCNRC_RF_DEC_MASK << E1000_RTTBCNRC_RF_INT_SHIFT) 1014 1015#endif 1016