e1000_hw.h revision 56cec249167b44ee2ba7a3cbf4431bee937e08e3
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2013 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28#ifndef _E1000_HW_H_ 29#define _E1000_HW_H_ 30 31#include <linux/types.h> 32#include <linux/delay.h> 33#include <linux/io.h> 34#include <linux/netdevice.h> 35 36#include "e1000_regs.h" 37#include "e1000_defines.h" 38 39struct e1000_hw; 40 41#define E1000_DEV_ID_82576 0x10C9 42#define E1000_DEV_ID_82576_FIBER 0x10E6 43#define E1000_DEV_ID_82576_SERDES 0x10E7 44#define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 45#define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526 46#define E1000_DEV_ID_82576_NS 0x150A 47#define E1000_DEV_ID_82576_NS_SERDES 0x1518 48#define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 49#define E1000_DEV_ID_82575EB_COPPER 0x10A7 50#define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9 51#define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6 52#define E1000_DEV_ID_82580_COPPER 0x150E 53#define E1000_DEV_ID_82580_FIBER 0x150F 54#define E1000_DEV_ID_82580_SERDES 0x1510 55#define E1000_DEV_ID_82580_SGMII 0x1511 56#define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 57#define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 58#define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 59#define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 60#define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 61#define E1000_DEV_ID_DH89XXCC_SFP 0x0440 62#define E1000_DEV_ID_I350_COPPER 0x1521 63#define E1000_DEV_ID_I350_FIBER 0x1522 64#define E1000_DEV_ID_I350_SERDES 0x1523 65#define E1000_DEV_ID_I350_SGMII 0x1524 66#define E1000_DEV_ID_I210_COPPER 0x1533 67#define E1000_DEV_ID_I210_FIBER 0x1536 68#define E1000_DEV_ID_I210_SERDES 0x1537 69#define E1000_DEV_ID_I210_SGMII 0x1538 70#define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 71#define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 72#define E1000_DEV_ID_I211_COPPER 0x1539 73#define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 74#define E1000_DEV_ID_I354_SGMII 0x1F41 75#define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 76 77#define E1000_REVISION_2 2 78#define E1000_REVISION_4 4 79 80#define E1000_FUNC_0 0 81#define E1000_FUNC_1 1 82#define E1000_FUNC_2 2 83#define E1000_FUNC_3 3 84 85#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0 86#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3 87#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6 88#define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9 89 90enum e1000_mac_type { 91 e1000_undefined = 0, 92 e1000_82575, 93 e1000_82576, 94 e1000_82580, 95 e1000_i350, 96 e1000_i354, 97 e1000_i210, 98 e1000_i211, 99 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */ 100}; 101 102enum e1000_media_type { 103 e1000_media_type_unknown = 0, 104 e1000_media_type_copper = 1, 105 e1000_media_type_fiber = 2, 106 e1000_media_type_internal_serdes = 3, 107 e1000_num_media_types 108}; 109 110enum e1000_nvm_type { 111 e1000_nvm_unknown = 0, 112 e1000_nvm_none, 113 e1000_nvm_eeprom_spi, 114 e1000_nvm_flash_hw, 115 e1000_nvm_invm, 116 e1000_nvm_flash_sw 117}; 118 119enum e1000_nvm_override { 120 e1000_nvm_override_none = 0, 121 e1000_nvm_override_spi_small, 122 e1000_nvm_override_spi_large, 123}; 124 125enum e1000_phy_type { 126 e1000_phy_unknown = 0, 127 e1000_phy_none, 128 e1000_phy_m88, 129 e1000_phy_igp, 130 e1000_phy_igp_2, 131 e1000_phy_gg82563, 132 e1000_phy_igp_3, 133 e1000_phy_ife, 134 e1000_phy_82580, 135 e1000_phy_i210, 136}; 137 138enum e1000_bus_type { 139 e1000_bus_type_unknown = 0, 140 e1000_bus_type_pci, 141 e1000_bus_type_pcix, 142 e1000_bus_type_pci_express, 143 e1000_bus_type_reserved 144}; 145 146enum e1000_bus_speed { 147 e1000_bus_speed_unknown = 0, 148 e1000_bus_speed_33, 149 e1000_bus_speed_66, 150 e1000_bus_speed_100, 151 e1000_bus_speed_120, 152 e1000_bus_speed_133, 153 e1000_bus_speed_2500, 154 e1000_bus_speed_5000, 155 e1000_bus_speed_reserved 156}; 157 158enum e1000_bus_width { 159 e1000_bus_width_unknown = 0, 160 e1000_bus_width_pcie_x1, 161 e1000_bus_width_pcie_x2, 162 e1000_bus_width_pcie_x4 = 4, 163 e1000_bus_width_pcie_x8 = 8, 164 e1000_bus_width_32, 165 e1000_bus_width_64, 166 e1000_bus_width_reserved 167}; 168 169enum e1000_1000t_rx_status { 170 e1000_1000t_rx_status_not_ok = 0, 171 e1000_1000t_rx_status_ok, 172 e1000_1000t_rx_status_undefined = 0xFF 173}; 174 175enum e1000_rev_polarity { 176 e1000_rev_polarity_normal = 0, 177 e1000_rev_polarity_reversed, 178 e1000_rev_polarity_undefined = 0xFF 179}; 180 181enum e1000_fc_mode { 182 e1000_fc_none = 0, 183 e1000_fc_rx_pause, 184 e1000_fc_tx_pause, 185 e1000_fc_full, 186 e1000_fc_default = 0xFF 187}; 188 189/* Statistics counters collected by the MAC */ 190struct e1000_hw_stats { 191 u64 crcerrs; 192 u64 algnerrc; 193 u64 symerrs; 194 u64 rxerrc; 195 u64 mpc; 196 u64 scc; 197 u64 ecol; 198 u64 mcc; 199 u64 latecol; 200 u64 colc; 201 u64 dc; 202 u64 tncrs; 203 u64 sec; 204 u64 cexterr; 205 u64 rlec; 206 u64 xonrxc; 207 u64 xontxc; 208 u64 xoffrxc; 209 u64 xofftxc; 210 u64 fcruc; 211 u64 prc64; 212 u64 prc127; 213 u64 prc255; 214 u64 prc511; 215 u64 prc1023; 216 u64 prc1522; 217 u64 gprc; 218 u64 bprc; 219 u64 mprc; 220 u64 gptc; 221 u64 gorc; 222 u64 gotc; 223 u64 rnbc; 224 u64 ruc; 225 u64 rfc; 226 u64 roc; 227 u64 rjc; 228 u64 mgprc; 229 u64 mgpdc; 230 u64 mgptc; 231 u64 tor; 232 u64 tot; 233 u64 tpr; 234 u64 tpt; 235 u64 ptc64; 236 u64 ptc127; 237 u64 ptc255; 238 u64 ptc511; 239 u64 ptc1023; 240 u64 ptc1522; 241 u64 mptc; 242 u64 bptc; 243 u64 tsctc; 244 u64 tsctfc; 245 u64 iac; 246 u64 icrxptc; 247 u64 icrxatc; 248 u64 ictxptc; 249 u64 ictxatc; 250 u64 ictxqec; 251 u64 ictxqmtc; 252 u64 icrxdmtc; 253 u64 icrxoc; 254 u64 cbtmpc; 255 u64 htdpmc; 256 u64 cbrdpc; 257 u64 cbrmpc; 258 u64 rpthc; 259 u64 hgptc; 260 u64 htcbdpc; 261 u64 hgorc; 262 u64 hgotc; 263 u64 lenerrs; 264 u64 scvpc; 265 u64 hrmpc; 266 u64 doosync; 267 u64 o2bgptc; 268 u64 o2bspc; 269 u64 b2ospc; 270 u64 b2ogprc; 271}; 272 273struct e1000_phy_stats { 274 u32 idle_errors; 275 u32 receive_errors; 276}; 277 278struct e1000_host_mng_dhcp_cookie { 279 u32 signature; 280 u8 status; 281 u8 reserved0; 282 u16 vlan_id; 283 u32 reserved1; 284 u16 reserved2; 285 u8 reserved3; 286 u8 checksum; 287}; 288 289/* Host Interface "Rev 1" */ 290struct e1000_host_command_header { 291 u8 command_id; 292 u8 command_length; 293 u8 command_options; 294 u8 checksum; 295}; 296 297#define E1000_HI_MAX_DATA_LENGTH 252 298struct e1000_host_command_info { 299 struct e1000_host_command_header command_header; 300 u8 command_data[E1000_HI_MAX_DATA_LENGTH]; 301}; 302 303/* Host Interface "Rev 2" */ 304struct e1000_host_mng_command_header { 305 u8 command_id; 306 u8 checksum; 307 u16 reserved1; 308 u16 reserved2; 309 u16 command_length; 310}; 311 312#define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 313struct e1000_host_mng_command_info { 314 struct e1000_host_mng_command_header command_header; 315 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; 316}; 317 318#include "e1000_mac.h" 319#include "e1000_phy.h" 320#include "e1000_nvm.h" 321#include "e1000_mbx.h" 322 323struct e1000_mac_operations { 324 s32 (*check_for_link)(struct e1000_hw *); 325 s32 (*reset_hw)(struct e1000_hw *); 326 s32 (*init_hw)(struct e1000_hw *); 327 bool (*check_mng_mode)(struct e1000_hw *); 328 s32 (*setup_physical_interface)(struct e1000_hw *); 329 void (*rar_set)(struct e1000_hw *, u8 *, u32); 330 s32 (*read_mac_addr)(struct e1000_hw *); 331 s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *); 332 s32 (*acquire_swfw_sync)(struct e1000_hw *, u16); 333 void (*release_swfw_sync)(struct e1000_hw *, u16); 334#ifdef CONFIG_IGB_HWMON 335 s32 (*get_thermal_sensor_data)(struct e1000_hw *); 336 s32 (*init_thermal_sensor_thresh)(struct e1000_hw *); 337#endif 338 339}; 340 341struct e1000_phy_operations { 342 s32 (*acquire)(struct e1000_hw *); 343 s32 (*check_polarity)(struct e1000_hw *); 344 s32 (*check_reset_block)(struct e1000_hw *); 345 s32 (*force_speed_duplex)(struct e1000_hw *); 346 s32 (*get_cfg_done)(struct e1000_hw *hw); 347 s32 (*get_cable_length)(struct e1000_hw *); 348 s32 (*get_phy_info)(struct e1000_hw *); 349 s32 (*read_reg)(struct e1000_hw *, u32, u16 *); 350 void (*release)(struct e1000_hw *); 351 s32 (*reset)(struct e1000_hw *); 352 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool); 353 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool); 354 s32 (*write_reg)(struct e1000_hw *, u32, u16); 355 s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *); 356 s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8); 357}; 358 359struct e1000_nvm_operations { 360 s32 (*acquire)(struct e1000_hw *); 361 s32 (*read)(struct e1000_hw *, u16, u16, u16 *); 362 void (*release)(struct e1000_hw *); 363 s32 (*write)(struct e1000_hw *, u16, u16, u16 *); 364 s32 (*update)(struct e1000_hw *); 365 s32 (*validate)(struct e1000_hw *); 366 s32 (*valid_led_default)(struct e1000_hw *, u16 *); 367}; 368 369#define E1000_MAX_SENSORS 3 370 371struct e1000_thermal_diode_data { 372 u8 location; 373 u8 temp; 374 u8 caution_thresh; 375 u8 max_op_thresh; 376}; 377 378struct e1000_thermal_sensor_data { 379 struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS]; 380}; 381 382struct e1000_info { 383 s32 (*get_invariants)(struct e1000_hw *); 384 struct e1000_mac_operations *mac_ops; 385 struct e1000_phy_operations *phy_ops; 386 struct e1000_nvm_operations *nvm_ops; 387}; 388 389extern const struct e1000_info e1000_82575_info; 390 391struct e1000_mac_info { 392 struct e1000_mac_operations ops; 393 394 u8 addr[6]; 395 u8 perm_addr[6]; 396 397 enum e1000_mac_type type; 398 399 u32 ledctl_default; 400 u32 ledctl_mode1; 401 u32 ledctl_mode2; 402 u32 mc_filter_type; 403 u32 txcw; 404 405 u16 mta_reg_count; 406 u16 uta_reg_count; 407 408 /* Maximum size of the MTA register table in all supported adapters */ 409 #define MAX_MTA_REG 128 410 u32 mta_shadow[MAX_MTA_REG]; 411 u16 rar_entry_count; 412 413 u8 forced_speed_duplex; 414 415 bool adaptive_ifs; 416 bool arc_subsystem_valid; 417 bool asf_firmware_present; 418 bool autoneg; 419 bool autoneg_failed; 420 bool disable_hw_init_bits; 421 bool get_link_status; 422 bool ifs_params_forced; 423 bool in_ifs_mode; 424 bool report_tx_early; 425 bool serdes_has_link; 426 bool tx_pkt_filtering; 427 struct e1000_thermal_sensor_data thermal_sensor_data; 428}; 429 430struct e1000_phy_info { 431 struct e1000_phy_operations ops; 432 433 enum e1000_phy_type type; 434 435 enum e1000_1000t_rx_status local_rx; 436 enum e1000_1000t_rx_status remote_rx; 437 enum e1000_ms_type ms_type; 438 enum e1000_ms_type original_ms_type; 439 enum e1000_rev_polarity cable_polarity; 440 enum e1000_smart_speed smart_speed; 441 442 u32 addr; 443 u32 id; 444 u32 reset_delay_us; /* in usec */ 445 u32 revision; 446 447 enum e1000_media_type media_type; 448 449 u16 autoneg_advertised; 450 u16 autoneg_mask; 451 u16 cable_length; 452 u16 max_cable_length; 453 u16 min_cable_length; 454 455 u8 mdix; 456 457 bool disable_polarity_correction; 458 bool is_mdix; 459 bool polarity_correction; 460 bool reset_disable; 461 bool speed_downgraded; 462 bool autoneg_wait_to_complete; 463}; 464 465struct e1000_nvm_info { 466 struct e1000_nvm_operations ops; 467 enum e1000_nvm_type type; 468 enum e1000_nvm_override override; 469 470 u32 flash_bank_size; 471 u32 flash_base_addr; 472 473 u16 word_size; 474 u16 delay_usec; 475 u16 address_bits; 476 u16 opcode_bits; 477 u16 page_size; 478}; 479 480struct e1000_bus_info { 481 enum e1000_bus_type type; 482 enum e1000_bus_speed speed; 483 enum e1000_bus_width width; 484 485 u32 snoop; 486 487 u16 func; 488 u16 pci_cmd_word; 489}; 490 491struct e1000_fc_info { 492 u32 high_water; /* Flow control high-water mark */ 493 u32 low_water; /* Flow control low-water mark */ 494 u16 pause_time; /* Flow control pause timer */ 495 bool send_xon; /* Flow control send XON */ 496 bool strict_ieee; /* Strict IEEE mode */ 497 enum e1000_fc_mode current_mode; /* Type of flow control */ 498 enum e1000_fc_mode requested_mode; 499}; 500 501struct e1000_mbx_operations { 502 s32 (*init_params)(struct e1000_hw *hw); 503 s32 (*read)(struct e1000_hw *, u32 *, u16, u16); 504 s32 (*write)(struct e1000_hw *, u32 *, u16, u16); 505 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16); 506 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16); 507 s32 (*check_for_msg)(struct e1000_hw *, u16); 508 s32 (*check_for_ack)(struct e1000_hw *, u16); 509 s32 (*check_for_rst)(struct e1000_hw *, u16); 510}; 511 512struct e1000_mbx_stats { 513 u32 msgs_tx; 514 u32 msgs_rx; 515 516 u32 acks; 517 u32 reqs; 518 u32 rsts; 519}; 520 521struct e1000_mbx_info { 522 struct e1000_mbx_operations ops; 523 struct e1000_mbx_stats stats; 524 u32 timeout; 525 u32 usec_delay; 526 u16 size; 527}; 528 529struct e1000_dev_spec_82575 { 530 bool sgmii_active; 531 bool global_device_reset; 532 bool eee_disable; 533 bool clear_semaphore_once; 534 struct e1000_sfp_flags eth_flags; 535 bool module_plugged; 536 u8 media_port; 537 bool media_changed; 538 bool mas_capable; 539}; 540 541struct e1000_hw { 542 void *back; 543 544 u8 __iomem *hw_addr; 545 u8 __iomem *flash_address; 546 unsigned long io_base; 547 548 struct e1000_mac_info mac; 549 struct e1000_fc_info fc; 550 struct e1000_phy_info phy; 551 struct e1000_nvm_info nvm; 552 struct e1000_bus_info bus; 553 struct e1000_mbx_info mbx; 554 struct e1000_host_mng_dhcp_cookie mng_cookie; 555 556 union { 557 struct e1000_dev_spec_82575 _82575; 558 } dev_spec; 559 560 u16 device_id; 561 u16 subsystem_vendor_id; 562 u16 subsystem_device_id; 563 u16 vendor_id; 564 565 u8 revision_id; 566}; 567 568struct net_device *igb_get_hw_dev(struct e1000_hw *hw); 569#define hw_dbg(format, arg...) \ 570 netdev_dbg(igb_get_hw_dev(hw), format, ##arg) 571 572/* These functions must be implemented by drivers */ 573s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 574s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value); 575#endif /* _E1000_HW_H_ */ 576