igb.h revision a24006ed12616bde1bbdb26868495906a212d8dc
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28 29/* Linux PRO/1000 Ethernet Driver main header file */ 30 31#ifndef _IGB_H_ 32#define _IGB_H_ 33 34#include "e1000_mac.h" 35#include "e1000_82575.h" 36 37#include <linux/clocksource.h> 38#include <linux/net_tstamp.h> 39#include <linux/ptp_clock_kernel.h> 40#include <linux/bitops.h> 41#include <linux/if_vlan.h> 42 43struct igb_adapter; 44 45/* Interrupt defines */ 46#define IGB_START_ITR 648 /* ~6000 ints/sec */ 47#define IGB_4K_ITR 980 48#define IGB_20K_ITR 196 49#define IGB_70K_ITR 56 50 51/* TX/RX descriptor defines */ 52#define IGB_DEFAULT_TXD 256 53#define IGB_DEFAULT_TX_WORK 128 54#define IGB_MIN_TXD 80 55#define IGB_MAX_TXD 4096 56 57#define IGB_DEFAULT_RXD 256 58#define IGB_MIN_RXD 80 59#define IGB_MAX_RXD 4096 60 61#define IGB_DEFAULT_ITR 3 /* dynamic */ 62#define IGB_MAX_ITR_USECS 10000 63#define IGB_MIN_ITR_USECS 10 64#define NON_Q_VECTORS 1 65#define MAX_Q_VECTORS 8 66 67/* Transmit and receive queues */ 68#define IGB_MAX_RX_QUEUES 8 69#define IGB_MAX_RX_QUEUES_82575 4 70#define IGB_MAX_RX_QUEUES_I211 2 71#define IGB_MAX_TX_QUEUES 8 72#define IGB_MAX_VF_MC_ENTRIES 30 73#define IGB_MAX_VF_FUNCTIONS 8 74#define IGB_MAX_VFTA_ENTRIES 128 75#define IGB_82576_VF_DEV_ID 0x10CA 76#define IGB_I350_VF_DEV_ID 0x1520 77 78/* NVM version defines */ 79#define IGB_MAJOR_MASK 0xF000 80#define IGB_MINOR_MASK 0x0FF0 81#define IGB_BUILD_MASK 0x000F 82#define IGB_COMB_VER_MASK 0x00FF 83#define IGB_MAJOR_SHIFT 12 84#define IGB_MINOR_SHIFT 4 85#define IGB_COMB_VER_SHFT 8 86#define IGB_NVM_VER_INVALID 0xFFFF 87#define IGB_ETRACK_SHIFT 16 88#define NVM_ETRACK_WORD 0x0042 89#define NVM_COMB_VER_OFF 0x0083 90#define NVM_COMB_VER_PTR 0x003d 91 92struct vf_data_storage { 93 unsigned char vf_mac_addresses[ETH_ALEN]; 94 u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES]; 95 u16 num_vf_mc_hashes; 96 u16 vlans_enabled; 97 u32 flags; 98 unsigned long last_nack; 99 u16 pf_vlan; /* When set, guest VLAN config not allowed. */ 100 u16 pf_qos; 101 u16 tx_rate; 102}; 103 104#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */ 105#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */ 106#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */ 107#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */ 108 109/* RX descriptor control thresholds. 110 * PTHRESH - MAC will consider prefetch if it has fewer than this number of 111 * descriptors available in its onboard memory. 112 * Setting this to 0 disables RX descriptor prefetch. 113 * HTHRESH - MAC will only prefetch if there are at least this many descriptors 114 * available in host memory. 115 * If PTHRESH is 0, this should also be 0. 116 * WTHRESH - RX descriptor writeback threshold - MAC will delay writing back 117 * descriptors until either it has this many to write back, or the 118 * ITR timer expires. 119 */ 120#define IGB_RX_PTHRESH 8 121#define IGB_RX_HTHRESH 8 122#define IGB_TX_PTHRESH 8 123#define IGB_TX_HTHRESH 1 124#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \ 125 adapter->msix_entries) ? 1 : 4) 126#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \ 127 adapter->msix_entries) ? 1 : 16) 128 129/* this is the size past which hardware will drop packets when setting LPE=0 */ 130#define MAXIMUM_ETHERNET_VLAN_SIZE 1522 131 132/* Supported Rx Buffer Sizes */ 133#define IGB_RXBUFFER_256 256 134#define IGB_RXBUFFER_2048 2048 135#define IGB_RX_HDR_LEN IGB_RXBUFFER_256 136#define IGB_RX_BUFSZ IGB_RXBUFFER_2048 137 138/* How many Tx Descriptors do we need to call netif_wake_queue ? */ 139#define IGB_TX_QUEUE_WAKE 16 140/* How many Rx Buffers do we bundle into one write to the hardware ? */ 141#define IGB_RX_BUFFER_WRITE 16 /* Must be power of 2 */ 142 143#define AUTO_ALL_MODES 0 144#define IGB_EEPROM_APME 0x0400 145 146#ifndef IGB_MASTER_SLAVE 147/* Switch to override PHY master/slave setting */ 148#define IGB_MASTER_SLAVE e1000_ms_hw_default 149#endif 150 151#define IGB_MNG_VLAN_NONE -1 152 153#define IGB_TX_FLAGS_CSUM 0x00000001 154#define IGB_TX_FLAGS_VLAN 0x00000002 155#define IGB_TX_FLAGS_TSO 0x00000004 156#define IGB_TX_FLAGS_IPV4 0x00000008 157#define IGB_TX_FLAGS_TSTAMP 0x00000010 158#define IGB_TX_FLAGS_VLAN_MASK 0xffff0000 159#define IGB_TX_FLAGS_VLAN_SHIFT 16 160 161/* wrapper around a pointer to a socket buffer, 162 * so a DMA handle can be stored along with the buffer */ 163struct igb_tx_buffer { 164 union e1000_adv_tx_desc *next_to_watch; 165 unsigned long time_stamp; 166 struct sk_buff *skb; 167 unsigned int bytecount; 168 u16 gso_segs; 169 __be16 protocol; 170 DEFINE_DMA_UNMAP_ADDR(dma); 171 DEFINE_DMA_UNMAP_LEN(len); 172 u32 tx_flags; 173}; 174 175struct igb_rx_buffer { 176 dma_addr_t dma; 177 struct page *page; 178 unsigned int page_offset; 179}; 180 181struct igb_tx_queue_stats { 182 u64 packets; 183 u64 bytes; 184 u64 restart_queue; 185 u64 restart_queue2; 186}; 187 188struct igb_rx_queue_stats { 189 u64 packets; 190 u64 bytes; 191 u64 drops; 192 u64 csum_err; 193 u64 alloc_failed; 194}; 195 196struct igb_ring_container { 197 struct igb_ring *ring; /* pointer to linked list of rings */ 198 unsigned int total_bytes; /* total bytes processed this int */ 199 unsigned int total_packets; /* total packets processed this int */ 200 u16 work_limit; /* total work allowed per interrupt */ 201 u8 count; /* total number of rings in vector */ 202 u8 itr; /* current ITR setting for ring */ 203}; 204 205struct igb_ring { 206 struct igb_q_vector *q_vector; /* backlink to q_vector */ 207 struct net_device *netdev; /* back pointer to net_device */ 208 struct device *dev; /* device pointer for dma mapping */ 209 union { /* array of buffer info structs */ 210 struct igb_tx_buffer *tx_buffer_info; 211 struct igb_rx_buffer *rx_buffer_info; 212 }; 213 void *desc; /* descriptor ring memory */ 214 unsigned long flags; /* ring specific flags */ 215 void __iomem *tail; /* pointer to ring tail register */ 216 dma_addr_t dma; /* phys address of the ring */ 217 unsigned int size; /* length of desc. ring in bytes */ 218 219 u16 count; /* number of desc. in the ring */ 220 u8 queue_index; /* logical index of the ring*/ 221 u8 reg_idx; /* physical index of the ring */ 222 223 /* everything past this point are written often */ 224 u16 next_to_clean; 225 u16 next_to_use; 226 u16 next_to_alloc; 227 228 union { 229 /* TX */ 230 struct { 231 struct igb_tx_queue_stats tx_stats; 232 struct u64_stats_sync tx_syncp; 233 struct u64_stats_sync tx_syncp2; 234 }; 235 /* RX */ 236 struct { 237 struct sk_buff *skb; 238 struct igb_rx_queue_stats rx_stats; 239 struct u64_stats_sync rx_syncp; 240 }; 241 }; 242} ____cacheline_internodealigned_in_smp; 243 244struct igb_q_vector { 245 struct igb_adapter *adapter; /* backlink */ 246 int cpu; /* CPU for DCA */ 247 u32 eims_value; /* EIMS mask value */ 248 249 u16 itr_val; 250 u8 set_itr; 251 void __iomem *itr_register; 252 253 struct igb_ring_container rx, tx; 254 255 struct napi_struct napi; 256 struct rcu_head rcu; /* to avoid race with update stats on free */ 257 char name[IFNAMSIZ + 9]; 258 259 /* for dynamic allocation of rings associated with this q_vector */ 260 struct igb_ring ring[0] ____cacheline_internodealigned_in_smp; 261}; 262 263enum e1000_ring_flags_t { 264 IGB_RING_FLAG_RX_SCTP_CSUM, 265 IGB_RING_FLAG_RX_LB_VLAN_BSWAP, 266 IGB_RING_FLAG_TX_CTX_IDX, 267 IGB_RING_FLAG_TX_DETECT_HANG 268}; 269 270#define IGB_TXD_DCMD (E1000_ADVTXD_DCMD_EOP | E1000_ADVTXD_DCMD_RS) 271 272#define IGB_RX_DESC(R, i) \ 273 (&(((union e1000_adv_rx_desc *)((R)->desc))[i])) 274#define IGB_TX_DESC(R, i) \ 275 (&(((union e1000_adv_tx_desc *)((R)->desc))[i])) 276#define IGB_TX_CTXTDESC(R, i) \ 277 (&(((struct e1000_adv_tx_context_desc *)((R)->desc))[i])) 278 279/* igb_test_staterr - tests bits within Rx descriptor status and error fields */ 280static inline __le32 igb_test_staterr(union e1000_adv_rx_desc *rx_desc, 281 const u32 stat_err_bits) 282{ 283 return rx_desc->wb.upper.status_error & cpu_to_le32(stat_err_bits); 284} 285 286/* igb_desc_unused - calculate if we have unused descriptors */ 287static inline int igb_desc_unused(struct igb_ring *ring) 288{ 289 if (ring->next_to_clean > ring->next_to_use) 290 return ring->next_to_clean - ring->next_to_use - 1; 291 292 return ring->count + ring->next_to_clean - ring->next_to_use - 1; 293} 294 295/* board specific private data structure */ 296struct igb_adapter { 297 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 298 299 struct net_device *netdev; 300 301 unsigned long state; 302 unsigned int flags; 303 304 unsigned int num_q_vectors; 305 struct msix_entry *msix_entries; 306 307 /* Interrupt Throttle Rate */ 308 u32 rx_itr_setting; 309 u32 tx_itr_setting; 310 u16 tx_itr; 311 u16 rx_itr; 312 313 /* TX */ 314 u16 tx_work_limit; 315 u32 tx_timeout_count; 316 int num_tx_queues; 317 struct igb_ring *tx_ring[16]; 318 319 /* RX */ 320 int num_rx_queues; 321 struct igb_ring *rx_ring[16]; 322 323 u32 max_frame_size; 324 u32 min_frame_size; 325 326 struct timer_list watchdog_timer; 327 struct timer_list phy_info_timer; 328 329 u16 mng_vlan_id; 330 u32 bd_number; 331 u32 wol; 332 u32 en_mng_pt; 333 u16 link_speed; 334 u16 link_duplex; 335 336 struct work_struct reset_task; 337 struct work_struct watchdog_task; 338 bool fc_autoneg; 339 u8 tx_timeout_factor; 340 struct timer_list blink_timer; 341 unsigned long led_status; 342 343 /* OS defined structs */ 344 struct pci_dev *pdev; 345 346 spinlock_t stats64_lock; 347 struct rtnl_link_stats64 stats64; 348 349 /* structs defined in e1000_hw.h */ 350 struct e1000_hw hw; 351 struct e1000_hw_stats stats; 352 struct e1000_phy_info phy_info; 353 struct e1000_phy_stats phy_stats; 354 355 u32 test_icr; 356 struct igb_ring test_tx_ring; 357 struct igb_ring test_rx_ring; 358 359 int msg_enable; 360 361 struct igb_q_vector *q_vector[MAX_Q_VECTORS]; 362 u32 eims_enable_mask; 363 u32 eims_other; 364 365 /* to not mess up cache alignment, always add to the bottom */ 366 u32 eeprom_wol; 367 368 u16 tx_ring_count; 369 u16 rx_ring_count; 370 unsigned int vfs_allocated_count; 371 struct vf_data_storage *vf_data; 372 int vf_rate_link_speed; 373 u32 rss_queues; 374 u32 wvbr; 375 u32 *shadow_vfta; 376 377 struct ptp_clock *ptp_clock; 378 struct ptp_clock_info ptp_caps; 379 struct delayed_work ptp_overflow_work; 380 struct work_struct ptp_tx_work; 381 struct sk_buff *ptp_tx_skb; 382 spinlock_t tmreg_lock; 383 struct cyclecounter cc; 384 struct timecounter tc; 385 386 char fw_version[32]; 387}; 388 389#define IGB_FLAG_HAS_MSI (1 << 0) 390#define IGB_FLAG_DCA_ENABLED (1 << 1) 391#define IGB_FLAG_QUAD_PORT_A (1 << 2) 392#define IGB_FLAG_QUEUE_PAIRS (1 << 3) 393#define IGB_FLAG_DMAC (1 << 4) 394#define IGB_FLAG_PTP (1 << 5) 395 396/* DMA Coalescing defines */ 397#define IGB_MIN_TXPBSIZE 20408 398#define IGB_TX_BUF_4096 4096 399#define IGB_DMCTLX_DCFLUSH_DIS 0x80000000 /* Disable DMA Coal Flush */ 400 401#define IGB_82576_TSYNC_SHIFT 19 402#define IGB_TS_HDR_LEN 16 403enum e1000_state_t { 404 __IGB_TESTING, 405 __IGB_RESETTING, 406 __IGB_DOWN 407}; 408 409enum igb_boards { 410 board_82575, 411}; 412 413extern char igb_driver_name[]; 414extern char igb_driver_version[]; 415 416extern int igb_up(struct igb_adapter *); 417extern void igb_down(struct igb_adapter *); 418extern void igb_reinit_locked(struct igb_adapter *); 419extern void igb_reset(struct igb_adapter *); 420extern int igb_set_spd_dplx(struct igb_adapter *, u32, u8); 421extern int igb_setup_tx_resources(struct igb_ring *); 422extern int igb_setup_rx_resources(struct igb_ring *); 423extern void igb_free_tx_resources(struct igb_ring *); 424extern void igb_free_rx_resources(struct igb_ring *); 425extern void igb_configure_tx_ring(struct igb_adapter *, struct igb_ring *); 426extern void igb_configure_rx_ring(struct igb_adapter *, struct igb_ring *); 427extern void igb_setup_tctl(struct igb_adapter *); 428extern void igb_setup_rctl(struct igb_adapter *); 429extern netdev_tx_t igb_xmit_frame_ring(struct sk_buff *, struct igb_ring *); 430extern void igb_unmap_and_free_tx_resource(struct igb_ring *, 431 struct igb_tx_buffer *); 432extern void igb_alloc_rx_buffers(struct igb_ring *, u16); 433extern void igb_update_stats(struct igb_adapter *, struct rtnl_link_stats64 *); 434extern bool igb_has_link(struct igb_adapter *adapter); 435extern void igb_set_ethtool_ops(struct net_device *); 436extern void igb_power_up_link(struct igb_adapter *); 437extern void igb_set_fw_version(struct igb_adapter *); 438extern void igb_ptp_init(struct igb_adapter *adapter); 439extern void igb_ptp_stop(struct igb_adapter *adapter); 440extern void igb_ptp_reset(struct igb_adapter *adapter); 441extern void igb_ptp_tx_work(struct work_struct *work); 442extern void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 443extern void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, 444 struct sk_buff *skb); 445extern void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, 446 unsigned char *va, 447 struct sk_buff *skb); 448static inline void igb_ptp_rx_hwtstamp(struct igb_q_vector *q_vector, 449 union e1000_adv_rx_desc *rx_desc, 450 struct sk_buff *skb) 451{ 452 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 453 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 454 igb_ptp_rx_rgtstamp(q_vector, skb); 455} 456 457extern int igb_ptp_hwtstamp_ioctl(struct net_device *netdev, 458 struct ifreq *ifr, int cmd); 459 460static inline s32 igb_reset_phy(struct e1000_hw *hw) 461{ 462 if (hw->phy.ops.reset) 463 return hw->phy.ops.reset(hw); 464 465 return 0; 466} 467 468static inline s32 igb_read_phy_reg(struct e1000_hw *hw, u32 offset, u16 *data) 469{ 470 if (hw->phy.ops.read_reg) 471 return hw->phy.ops.read_reg(hw, offset, data); 472 473 return 0; 474} 475 476static inline s32 igb_write_phy_reg(struct e1000_hw *hw, u32 offset, u16 data) 477{ 478 if (hw->phy.ops.write_reg) 479 return hw->phy.ops.write_reg(hw, offset, data); 480 481 return 0; 482} 483 484static inline s32 igb_get_phy_info(struct e1000_hw *hw) 485{ 486 if (hw->phy.ops.get_phy_info) 487 return hw->phy.ops.get_phy_info(hw); 488 489 return 0; 490} 491 492static inline struct netdev_queue *txring_txq(const struct igb_ring *tx_ring) 493{ 494 return netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 495} 496 497#endif /* _IGB_H_ */ 498