igb_ethtool.c revision 428f1f715131ea5ae32e29502541ce007f556b5b
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28/* ethtool support for igb */ 29 30#include <linux/vmalloc.h> 31#include <linux/netdevice.h> 32#include <linux/pci.h> 33#include <linux/delay.h> 34#include <linux/interrupt.h> 35#include <linux/if_ether.h> 36#include <linux/ethtool.h> 37#include <linux/sched.h> 38#include <linux/slab.h> 39#include <linux/pm_runtime.h> 40#include <linux/highmem.h> 41 42#include "igb.h" 43 44struct igb_stats { 45 char stat_string[ETH_GSTRING_LEN]; 46 int sizeof_stat; 47 int stat_offset; 48}; 49 50#define IGB_STAT(_name, _stat) { \ 51 .stat_string = _name, \ 52 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \ 53 .stat_offset = offsetof(struct igb_adapter, _stat) \ 54} 55static const struct igb_stats igb_gstrings_stats[] = { 56 IGB_STAT("rx_packets", stats.gprc), 57 IGB_STAT("tx_packets", stats.gptc), 58 IGB_STAT("rx_bytes", stats.gorc), 59 IGB_STAT("tx_bytes", stats.gotc), 60 IGB_STAT("rx_broadcast", stats.bprc), 61 IGB_STAT("tx_broadcast", stats.bptc), 62 IGB_STAT("rx_multicast", stats.mprc), 63 IGB_STAT("tx_multicast", stats.mptc), 64 IGB_STAT("multicast", stats.mprc), 65 IGB_STAT("collisions", stats.colc), 66 IGB_STAT("rx_crc_errors", stats.crcerrs), 67 IGB_STAT("rx_no_buffer_count", stats.rnbc), 68 IGB_STAT("rx_missed_errors", stats.mpc), 69 IGB_STAT("tx_aborted_errors", stats.ecol), 70 IGB_STAT("tx_carrier_errors", stats.tncrs), 71 IGB_STAT("tx_window_errors", stats.latecol), 72 IGB_STAT("tx_abort_late_coll", stats.latecol), 73 IGB_STAT("tx_deferred_ok", stats.dc), 74 IGB_STAT("tx_single_coll_ok", stats.scc), 75 IGB_STAT("tx_multi_coll_ok", stats.mcc), 76 IGB_STAT("tx_timeout_count", tx_timeout_count), 77 IGB_STAT("rx_long_length_errors", stats.roc), 78 IGB_STAT("rx_short_length_errors", stats.ruc), 79 IGB_STAT("rx_align_errors", stats.algnerrc), 80 IGB_STAT("tx_tcp_seg_good", stats.tsctc), 81 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc), 82 IGB_STAT("rx_flow_control_xon", stats.xonrxc), 83 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc), 84 IGB_STAT("tx_flow_control_xon", stats.xontxc), 85 IGB_STAT("tx_flow_control_xoff", stats.xofftxc), 86 IGB_STAT("rx_long_byte_count", stats.gorc), 87 IGB_STAT("tx_dma_out_of_sync", stats.doosync), 88 IGB_STAT("tx_smbus", stats.mgptc), 89 IGB_STAT("rx_smbus", stats.mgprc), 90 IGB_STAT("dropped_smbus", stats.mgpdc), 91 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc), 92 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc), 93 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc), 94 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc), 95 IGB_STAT("tx_hwtstamp_timeouts", tx_hwtstamp_timeouts), 96}; 97 98#define IGB_NETDEV_STAT(_net_stat) { \ 99 .stat_string = __stringify(_net_stat), \ 100 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \ 101 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \ 102} 103static const struct igb_stats igb_gstrings_net_stats[] = { 104 IGB_NETDEV_STAT(rx_errors), 105 IGB_NETDEV_STAT(tx_errors), 106 IGB_NETDEV_STAT(tx_dropped), 107 IGB_NETDEV_STAT(rx_length_errors), 108 IGB_NETDEV_STAT(rx_over_errors), 109 IGB_NETDEV_STAT(rx_frame_errors), 110 IGB_NETDEV_STAT(rx_fifo_errors), 111 IGB_NETDEV_STAT(tx_fifo_errors), 112 IGB_NETDEV_STAT(tx_heartbeat_errors) 113}; 114 115#define IGB_GLOBAL_STATS_LEN \ 116 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)) 117#define IGB_NETDEV_STATS_LEN \ 118 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats)) 119#define IGB_RX_QUEUE_STATS_LEN \ 120 (sizeof(struct igb_rx_queue_stats) / sizeof(u64)) 121 122#define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */ 123 124#define IGB_QUEUE_STATS_LEN \ 125 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \ 126 IGB_RX_QUEUE_STATS_LEN) + \ 127 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \ 128 IGB_TX_QUEUE_STATS_LEN)) 129#define IGB_STATS_LEN \ 130 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN) 131 132static const char igb_gstrings_test[][ETH_GSTRING_LEN] = { 133 "Register test (offline)", "Eeprom test (offline)", 134 "Interrupt test (offline)", "Loopback test (offline)", 135 "Link test (on/offline)" 136}; 137#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN) 138 139static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 140{ 141 struct igb_adapter *adapter = netdev_priv(netdev); 142 struct e1000_hw *hw = &adapter->hw; 143 u32 status; 144 145 if (hw->phy.media_type == e1000_media_type_copper) { 146 147 ecmd->supported = (SUPPORTED_10baseT_Half | 148 SUPPORTED_10baseT_Full | 149 SUPPORTED_100baseT_Half | 150 SUPPORTED_100baseT_Full | 151 SUPPORTED_1000baseT_Full| 152 SUPPORTED_Autoneg | 153 SUPPORTED_TP | 154 SUPPORTED_Pause); 155 ecmd->advertising = ADVERTISED_TP; 156 157 if (hw->mac.autoneg == 1) { 158 ecmd->advertising |= ADVERTISED_Autoneg; 159 /* the e1000 autoneg seems to match ethtool nicely */ 160 ecmd->advertising |= hw->phy.autoneg_advertised; 161 } 162 163 if (hw->mac.autoneg != 1) 164 ecmd->advertising &= ~(ADVERTISED_Pause | 165 ADVERTISED_Asym_Pause); 166 167 if (hw->fc.requested_mode == e1000_fc_full) 168 ecmd->advertising |= ADVERTISED_Pause; 169 else if (hw->fc.requested_mode == e1000_fc_rx_pause) 170 ecmd->advertising |= (ADVERTISED_Pause | 171 ADVERTISED_Asym_Pause); 172 else if (hw->fc.requested_mode == e1000_fc_tx_pause) 173 ecmd->advertising |= ADVERTISED_Asym_Pause; 174 else 175 ecmd->advertising &= ~(ADVERTISED_Pause | 176 ADVERTISED_Asym_Pause); 177 178 ecmd->port = PORT_TP; 179 ecmd->phy_address = hw->phy.addr; 180 } else { 181 ecmd->supported = (SUPPORTED_1000baseT_Full | 182 SUPPORTED_FIBRE | 183 SUPPORTED_Autoneg); 184 185 ecmd->advertising = (ADVERTISED_1000baseT_Full | 186 ADVERTISED_FIBRE | 187 ADVERTISED_Autoneg | 188 ADVERTISED_Pause); 189 190 ecmd->port = PORT_FIBRE; 191 } 192 193 ecmd->transceiver = XCVR_INTERNAL; 194 195 status = rd32(E1000_STATUS); 196 197 if (status & E1000_STATUS_LU) { 198 199 if ((status & E1000_STATUS_SPEED_1000) || 200 hw->phy.media_type != e1000_media_type_copper) 201 ethtool_cmd_speed_set(ecmd, SPEED_1000); 202 else if (status & E1000_STATUS_SPEED_100) 203 ethtool_cmd_speed_set(ecmd, SPEED_100); 204 else 205 ethtool_cmd_speed_set(ecmd, SPEED_10); 206 207 if ((status & E1000_STATUS_FD) || 208 hw->phy.media_type != e1000_media_type_copper) 209 ecmd->duplex = DUPLEX_FULL; 210 else 211 ecmd->duplex = DUPLEX_HALF; 212 } else { 213 ethtool_cmd_speed_set(ecmd, -1); 214 ecmd->duplex = -1; 215 } 216 217 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; 218 219 /* MDI-X => 2; MDI =>1; Invalid =>0 */ 220 if (hw->phy.media_type == e1000_media_type_copper) 221 ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X : 222 ETH_TP_MDI; 223 else 224 ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID; 225 226 if (hw->phy.mdix == AUTO_ALL_MODES) 227 ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO; 228 else 229 ecmd->eth_tp_mdix_ctrl = hw->phy.mdix; 230 231 return 0; 232} 233 234static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 235{ 236 struct igb_adapter *adapter = netdev_priv(netdev); 237 struct e1000_hw *hw = &adapter->hw; 238 239 /* When SoL/IDER sessions are active, autoneg/speed/duplex 240 * cannot be changed */ 241 if (igb_check_reset_block(hw)) { 242 dev_err(&adapter->pdev->dev, 243 "Cannot change link characteristics when SoL/IDER is active.\n"); 244 return -EINVAL; 245 } 246 247 /* 248 * MDI setting is only allowed when autoneg enabled because 249 * some hardware doesn't allow MDI setting when speed or 250 * duplex is forced. 251 */ 252 if (ecmd->eth_tp_mdix_ctrl) { 253 if (hw->phy.media_type != e1000_media_type_copper) 254 return -EOPNOTSUPP; 255 256 if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) && 257 (ecmd->autoneg != AUTONEG_ENABLE)) { 258 dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n"); 259 return -EINVAL; 260 } 261 } 262 263 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 264 msleep(1); 265 266 if (ecmd->autoneg == AUTONEG_ENABLE) { 267 hw->mac.autoneg = 1; 268 hw->phy.autoneg_advertised = ecmd->advertising | 269 ADVERTISED_TP | 270 ADVERTISED_Autoneg; 271 ecmd->advertising = hw->phy.autoneg_advertised; 272 if (adapter->fc_autoneg) 273 hw->fc.requested_mode = e1000_fc_default; 274 } else { 275 u32 speed = ethtool_cmd_speed(ecmd); 276 /* calling this overrides forced MDI setting */ 277 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) { 278 clear_bit(__IGB_RESETTING, &adapter->state); 279 return -EINVAL; 280 } 281 } 282 283 /* MDI-X => 2; MDI => 1; Auto => 3 */ 284 if (ecmd->eth_tp_mdix_ctrl) { 285 /* 286 * fix up the value for auto (3 => 0) as zero is mapped 287 * internally to auto 288 */ 289 if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO) 290 hw->phy.mdix = AUTO_ALL_MODES; 291 else 292 hw->phy.mdix = ecmd->eth_tp_mdix_ctrl; 293 } 294 295 /* reset the link */ 296 if (netif_running(adapter->netdev)) { 297 igb_down(adapter); 298 igb_up(adapter); 299 } else 300 igb_reset(adapter); 301 302 clear_bit(__IGB_RESETTING, &adapter->state); 303 return 0; 304} 305 306static u32 igb_get_link(struct net_device *netdev) 307{ 308 struct igb_adapter *adapter = netdev_priv(netdev); 309 struct e1000_mac_info *mac = &adapter->hw.mac; 310 311 /* 312 * If the link is not reported up to netdev, interrupts are disabled, 313 * and so the physical link state may have changed since we last 314 * looked. Set get_link_status to make sure that the true link 315 * state is interrogated, rather than pulling a cached and possibly 316 * stale link state from the driver. 317 */ 318 if (!netif_carrier_ok(netdev)) 319 mac->get_link_status = 1; 320 321 return igb_has_link(adapter); 322} 323 324static void igb_get_pauseparam(struct net_device *netdev, 325 struct ethtool_pauseparam *pause) 326{ 327 struct igb_adapter *adapter = netdev_priv(netdev); 328 struct e1000_hw *hw = &adapter->hw; 329 330 pause->autoneg = 331 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); 332 333 if (hw->fc.current_mode == e1000_fc_rx_pause) 334 pause->rx_pause = 1; 335 else if (hw->fc.current_mode == e1000_fc_tx_pause) 336 pause->tx_pause = 1; 337 else if (hw->fc.current_mode == e1000_fc_full) { 338 pause->rx_pause = 1; 339 pause->tx_pause = 1; 340 } 341} 342 343static int igb_set_pauseparam(struct net_device *netdev, 344 struct ethtool_pauseparam *pause) 345{ 346 struct igb_adapter *adapter = netdev_priv(netdev); 347 struct e1000_hw *hw = &adapter->hw; 348 int retval = 0; 349 350 adapter->fc_autoneg = pause->autoneg; 351 352 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 353 msleep(1); 354 355 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 356 hw->fc.requested_mode = e1000_fc_default; 357 if (netif_running(adapter->netdev)) { 358 igb_down(adapter); 359 igb_up(adapter); 360 } else { 361 igb_reset(adapter); 362 } 363 } else { 364 if (pause->rx_pause && pause->tx_pause) 365 hw->fc.requested_mode = e1000_fc_full; 366 else if (pause->rx_pause && !pause->tx_pause) 367 hw->fc.requested_mode = e1000_fc_rx_pause; 368 else if (!pause->rx_pause && pause->tx_pause) 369 hw->fc.requested_mode = e1000_fc_tx_pause; 370 else if (!pause->rx_pause && !pause->tx_pause) 371 hw->fc.requested_mode = e1000_fc_none; 372 373 hw->fc.current_mode = hw->fc.requested_mode; 374 375 retval = ((hw->phy.media_type == e1000_media_type_copper) ? 376 igb_force_mac_fc(hw) : igb_setup_link(hw)); 377 } 378 379 clear_bit(__IGB_RESETTING, &adapter->state); 380 return retval; 381} 382 383static u32 igb_get_msglevel(struct net_device *netdev) 384{ 385 struct igb_adapter *adapter = netdev_priv(netdev); 386 return adapter->msg_enable; 387} 388 389static void igb_set_msglevel(struct net_device *netdev, u32 data) 390{ 391 struct igb_adapter *adapter = netdev_priv(netdev); 392 adapter->msg_enable = data; 393} 394 395static int igb_get_regs_len(struct net_device *netdev) 396{ 397#define IGB_REGS_LEN 739 398 return IGB_REGS_LEN * sizeof(u32); 399} 400 401static void igb_get_regs(struct net_device *netdev, 402 struct ethtool_regs *regs, void *p) 403{ 404 struct igb_adapter *adapter = netdev_priv(netdev); 405 struct e1000_hw *hw = &adapter->hw; 406 u32 *regs_buff = p; 407 u8 i; 408 409 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); 410 411 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 412 413 /* General Registers */ 414 regs_buff[0] = rd32(E1000_CTRL); 415 regs_buff[1] = rd32(E1000_STATUS); 416 regs_buff[2] = rd32(E1000_CTRL_EXT); 417 regs_buff[3] = rd32(E1000_MDIC); 418 regs_buff[4] = rd32(E1000_SCTL); 419 regs_buff[5] = rd32(E1000_CONNSW); 420 regs_buff[6] = rd32(E1000_VET); 421 regs_buff[7] = rd32(E1000_LEDCTL); 422 regs_buff[8] = rd32(E1000_PBA); 423 regs_buff[9] = rd32(E1000_PBS); 424 regs_buff[10] = rd32(E1000_FRTIMER); 425 regs_buff[11] = rd32(E1000_TCPTIMER); 426 427 /* NVM Register */ 428 regs_buff[12] = rd32(E1000_EECD); 429 430 /* Interrupt */ 431 /* Reading EICS for EICR because they read the 432 * same but EICS does not clear on read */ 433 regs_buff[13] = rd32(E1000_EICS); 434 regs_buff[14] = rd32(E1000_EICS); 435 regs_buff[15] = rd32(E1000_EIMS); 436 regs_buff[16] = rd32(E1000_EIMC); 437 regs_buff[17] = rd32(E1000_EIAC); 438 regs_buff[18] = rd32(E1000_EIAM); 439 /* Reading ICS for ICR because they read the 440 * same but ICS does not clear on read */ 441 regs_buff[19] = rd32(E1000_ICS); 442 regs_buff[20] = rd32(E1000_ICS); 443 regs_buff[21] = rd32(E1000_IMS); 444 regs_buff[22] = rd32(E1000_IMC); 445 regs_buff[23] = rd32(E1000_IAC); 446 regs_buff[24] = rd32(E1000_IAM); 447 regs_buff[25] = rd32(E1000_IMIRVP); 448 449 /* Flow Control */ 450 regs_buff[26] = rd32(E1000_FCAL); 451 regs_buff[27] = rd32(E1000_FCAH); 452 regs_buff[28] = rd32(E1000_FCTTV); 453 regs_buff[29] = rd32(E1000_FCRTL); 454 regs_buff[30] = rd32(E1000_FCRTH); 455 regs_buff[31] = rd32(E1000_FCRTV); 456 457 /* Receive */ 458 regs_buff[32] = rd32(E1000_RCTL); 459 regs_buff[33] = rd32(E1000_RXCSUM); 460 regs_buff[34] = rd32(E1000_RLPML); 461 regs_buff[35] = rd32(E1000_RFCTL); 462 regs_buff[36] = rd32(E1000_MRQC); 463 regs_buff[37] = rd32(E1000_VT_CTL); 464 465 /* Transmit */ 466 regs_buff[38] = rd32(E1000_TCTL); 467 regs_buff[39] = rd32(E1000_TCTL_EXT); 468 regs_buff[40] = rd32(E1000_TIPG); 469 regs_buff[41] = rd32(E1000_DTXCTL); 470 471 /* Wake Up */ 472 regs_buff[42] = rd32(E1000_WUC); 473 regs_buff[43] = rd32(E1000_WUFC); 474 regs_buff[44] = rd32(E1000_WUS); 475 regs_buff[45] = rd32(E1000_IPAV); 476 regs_buff[46] = rd32(E1000_WUPL); 477 478 /* MAC */ 479 regs_buff[47] = rd32(E1000_PCS_CFG0); 480 regs_buff[48] = rd32(E1000_PCS_LCTL); 481 regs_buff[49] = rd32(E1000_PCS_LSTAT); 482 regs_buff[50] = rd32(E1000_PCS_ANADV); 483 regs_buff[51] = rd32(E1000_PCS_LPAB); 484 regs_buff[52] = rd32(E1000_PCS_NPTX); 485 regs_buff[53] = rd32(E1000_PCS_LPABNP); 486 487 /* Statistics */ 488 regs_buff[54] = adapter->stats.crcerrs; 489 regs_buff[55] = adapter->stats.algnerrc; 490 regs_buff[56] = adapter->stats.symerrs; 491 regs_buff[57] = adapter->stats.rxerrc; 492 regs_buff[58] = adapter->stats.mpc; 493 regs_buff[59] = adapter->stats.scc; 494 regs_buff[60] = adapter->stats.ecol; 495 regs_buff[61] = adapter->stats.mcc; 496 regs_buff[62] = adapter->stats.latecol; 497 regs_buff[63] = adapter->stats.colc; 498 regs_buff[64] = adapter->stats.dc; 499 regs_buff[65] = adapter->stats.tncrs; 500 regs_buff[66] = adapter->stats.sec; 501 regs_buff[67] = adapter->stats.htdpmc; 502 regs_buff[68] = adapter->stats.rlec; 503 regs_buff[69] = adapter->stats.xonrxc; 504 regs_buff[70] = adapter->stats.xontxc; 505 regs_buff[71] = adapter->stats.xoffrxc; 506 regs_buff[72] = adapter->stats.xofftxc; 507 regs_buff[73] = adapter->stats.fcruc; 508 regs_buff[74] = adapter->stats.prc64; 509 regs_buff[75] = adapter->stats.prc127; 510 regs_buff[76] = adapter->stats.prc255; 511 regs_buff[77] = adapter->stats.prc511; 512 regs_buff[78] = adapter->stats.prc1023; 513 regs_buff[79] = adapter->stats.prc1522; 514 regs_buff[80] = adapter->stats.gprc; 515 regs_buff[81] = adapter->stats.bprc; 516 regs_buff[82] = adapter->stats.mprc; 517 regs_buff[83] = adapter->stats.gptc; 518 regs_buff[84] = adapter->stats.gorc; 519 regs_buff[86] = adapter->stats.gotc; 520 regs_buff[88] = adapter->stats.rnbc; 521 regs_buff[89] = adapter->stats.ruc; 522 regs_buff[90] = adapter->stats.rfc; 523 regs_buff[91] = adapter->stats.roc; 524 regs_buff[92] = adapter->stats.rjc; 525 regs_buff[93] = adapter->stats.mgprc; 526 regs_buff[94] = adapter->stats.mgpdc; 527 regs_buff[95] = adapter->stats.mgptc; 528 regs_buff[96] = adapter->stats.tor; 529 regs_buff[98] = adapter->stats.tot; 530 regs_buff[100] = adapter->stats.tpr; 531 regs_buff[101] = adapter->stats.tpt; 532 regs_buff[102] = adapter->stats.ptc64; 533 regs_buff[103] = adapter->stats.ptc127; 534 regs_buff[104] = adapter->stats.ptc255; 535 regs_buff[105] = adapter->stats.ptc511; 536 regs_buff[106] = adapter->stats.ptc1023; 537 regs_buff[107] = adapter->stats.ptc1522; 538 regs_buff[108] = adapter->stats.mptc; 539 regs_buff[109] = adapter->stats.bptc; 540 regs_buff[110] = adapter->stats.tsctc; 541 regs_buff[111] = adapter->stats.iac; 542 regs_buff[112] = adapter->stats.rpthc; 543 regs_buff[113] = adapter->stats.hgptc; 544 regs_buff[114] = adapter->stats.hgorc; 545 regs_buff[116] = adapter->stats.hgotc; 546 regs_buff[118] = adapter->stats.lenerrs; 547 regs_buff[119] = adapter->stats.scvpc; 548 regs_buff[120] = adapter->stats.hrmpc; 549 550 for (i = 0; i < 4; i++) 551 regs_buff[121 + i] = rd32(E1000_SRRCTL(i)); 552 for (i = 0; i < 4; i++) 553 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i)); 554 for (i = 0; i < 4; i++) 555 regs_buff[129 + i] = rd32(E1000_RDBAL(i)); 556 for (i = 0; i < 4; i++) 557 regs_buff[133 + i] = rd32(E1000_RDBAH(i)); 558 for (i = 0; i < 4; i++) 559 regs_buff[137 + i] = rd32(E1000_RDLEN(i)); 560 for (i = 0; i < 4; i++) 561 regs_buff[141 + i] = rd32(E1000_RDH(i)); 562 for (i = 0; i < 4; i++) 563 regs_buff[145 + i] = rd32(E1000_RDT(i)); 564 for (i = 0; i < 4; i++) 565 regs_buff[149 + i] = rd32(E1000_RXDCTL(i)); 566 567 for (i = 0; i < 10; i++) 568 regs_buff[153 + i] = rd32(E1000_EITR(i)); 569 for (i = 0; i < 8; i++) 570 regs_buff[163 + i] = rd32(E1000_IMIR(i)); 571 for (i = 0; i < 8; i++) 572 regs_buff[171 + i] = rd32(E1000_IMIREXT(i)); 573 for (i = 0; i < 16; i++) 574 regs_buff[179 + i] = rd32(E1000_RAL(i)); 575 for (i = 0; i < 16; i++) 576 regs_buff[195 + i] = rd32(E1000_RAH(i)); 577 578 for (i = 0; i < 4; i++) 579 regs_buff[211 + i] = rd32(E1000_TDBAL(i)); 580 for (i = 0; i < 4; i++) 581 regs_buff[215 + i] = rd32(E1000_TDBAH(i)); 582 for (i = 0; i < 4; i++) 583 regs_buff[219 + i] = rd32(E1000_TDLEN(i)); 584 for (i = 0; i < 4; i++) 585 regs_buff[223 + i] = rd32(E1000_TDH(i)); 586 for (i = 0; i < 4; i++) 587 regs_buff[227 + i] = rd32(E1000_TDT(i)); 588 for (i = 0; i < 4; i++) 589 regs_buff[231 + i] = rd32(E1000_TXDCTL(i)); 590 for (i = 0; i < 4; i++) 591 regs_buff[235 + i] = rd32(E1000_TDWBAL(i)); 592 for (i = 0; i < 4; i++) 593 regs_buff[239 + i] = rd32(E1000_TDWBAH(i)); 594 for (i = 0; i < 4; i++) 595 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i)); 596 597 for (i = 0; i < 4; i++) 598 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i)); 599 for (i = 0; i < 4; i++) 600 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i)); 601 for (i = 0; i < 32; i++) 602 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i)); 603 for (i = 0; i < 128; i++) 604 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i)); 605 for (i = 0; i < 128; i++) 606 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i)); 607 for (i = 0; i < 4; i++) 608 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i)); 609 610 regs_buff[547] = rd32(E1000_TDFH); 611 regs_buff[548] = rd32(E1000_TDFT); 612 regs_buff[549] = rd32(E1000_TDFHS); 613 regs_buff[550] = rd32(E1000_TDFPC); 614 615 if (hw->mac.type > e1000_82580) { 616 regs_buff[551] = adapter->stats.o2bgptc; 617 regs_buff[552] = adapter->stats.b2ospc; 618 regs_buff[553] = adapter->stats.o2bspc; 619 regs_buff[554] = adapter->stats.b2ogprc; 620 } 621 622 if (hw->mac.type != e1000_82576) 623 return; 624 for (i = 0; i < 12; i++) 625 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4)); 626 for (i = 0; i < 4; i++) 627 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4)); 628 for (i = 0; i < 12; i++) 629 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4)); 630 for (i = 0; i < 12; i++) 631 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4)); 632 for (i = 0; i < 12; i++) 633 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4)); 634 for (i = 0; i < 12; i++) 635 regs_buff[607 + i] = rd32(E1000_RDH(i + 4)); 636 for (i = 0; i < 12; i++) 637 regs_buff[619 + i] = rd32(E1000_RDT(i + 4)); 638 for (i = 0; i < 12; i++) 639 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4)); 640 641 for (i = 0; i < 12; i++) 642 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4)); 643 for (i = 0; i < 12; i++) 644 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4)); 645 for (i = 0; i < 12; i++) 646 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4)); 647 for (i = 0; i < 12; i++) 648 regs_buff[679 + i] = rd32(E1000_TDH(i + 4)); 649 for (i = 0; i < 12; i++) 650 regs_buff[691 + i] = rd32(E1000_TDT(i + 4)); 651 for (i = 0; i < 12; i++) 652 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4)); 653 for (i = 0; i < 12; i++) 654 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4)); 655 for (i = 0; i < 12; i++) 656 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4)); 657} 658 659static int igb_get_eeprom_len(struct net_device *netdev) 660{ 661 struct igb_adapter *adapter = netdev_priv(netdev); 662 return adapter->hw.nvm.word_size * 2; 663} 664 665static int igb_get_eeprom(struct net_device *netdev, 666 struct ethtool_eeprom *eeprom, u8 *bytes) 667{ 668 struct igb_adapter *adapter = netdev_priv(netdev); 669 struct e1000_hw *hw = &adapter->hw; 670 u16 *eeprom_buff; 671 int first_word, last_word; 672 int ret_val = 0; 673 u16 i; 674 675 if (eeprom->len == 0) 676 return -EINVAL; 677 678 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 679 680 first_word = eeprom->offset >> 1; 681 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 682 683 eeprom_buff = kmalloc(sizeof(u16) * 684 (last_word - first_word + 1), GFP_KERNEL); 685 if (!eeprom_buff) 686 return -ENOMEM; 687 688 if (hw->nvm.type == e1000_nvm_eeprom_spi) 689 ret_val = hw->nvm.ops.read(hw, first_word, 690 last_word - first_word + 1, 691 eeprom_buff); 692 else { 693 for (i = 0; i < last_word - first_word + 1; i++) { 694 ret_val = hw->nvm.ops.read(hw, first_word + i, 1, 695 &eeprom_buff[i]); 696 if (ret_val) 697 break; 698 } 699 } 700 701 /* Device's eeprom is always little-endian, word addressable */ 702 for (i = 0; i < last_word - first_word + 1; i++) 703 le16_to_cpus(&eeprom_buff[i]); 704 705 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), 706 eeprom->len); 707 kfree(eeprom_buff); 708 709 return ret_val; 710} 711 712static int igb_set_eeprom(struct net_device *netdev, 713 struct ethtool_eeprom *eeprom, u8 *bytes) 714{ 715 struct igb_adapter *adapter = netdev_priv(netdev); 716 struct e1000_hw *hw = &adapter->hw; 717 u16 *eeprom_buff; 718 void *ptr; 719 int max_len, first_word, last_word, ret_val = 0; 720 u16 i; 721 722 if (eeprom->len == 0) 723 return -EOPNOTSUPP; 724 725 if (hw->mac.type == e1000_i211) 726 return -EOPNOTSUPP; 727 728 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 729 return -EFAULT; 730 731 max_len = hw->nvm.word_size * 2; 732 733 first_word = eeprom->offset >> 1; 734 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 735 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 736 if (!eeprom_buff) 737 return -ENOMEM; 738 739 ptr = (void *)eeprom_buff; 740 741 if (eeprom->offset & 1) { 742 /* need read/modify/write of first changed EEPROM word */ 743 /* only the second byte of the word is being modified */ 744 ret_val = hw->nvm.ops.read(hw, first_word, 1, 745 &eeprom_buff[0]); 746 ptr++; 747 } 748 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { 749 /* need read/modify/write of last changed EEPROM word */ 750 /* only the first byte of the word is being modified */ 751 ret_val = hw->nvm.ops.read(hw, last_word, 1, 752 &eeprom_buff[last_word - first_word]); 753 } 754 755 /* Device's eeprom is always little-endian, word addressable */ 756 for (i = 0; i < last_word - first_word + 1; i++) 757 le16_to_cpus(&eeprom_buff[i]); 758 759 memcpy(ptr, bytes, eeprom->len); 760 761 for (i = 0; i < last_word - first_word + 1; i++) 762 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); 763 764 ret_val = hw->nvm.ops.write(hw, first_word, 765 last_word - first_word + 1, eeprom_buff); 766 767 /* Update the checksum over the first part of the EEPROM if needed 768 * and flush shadow RAM for 82573 controllers */ 769 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG))) 770 hw->nvm.ops.update(hw); 771 772 igb_set_fw_version(adapter); 773 kfree(eeprom_buff); 774 return ret_val; 775} 776 777static void igb_get_drvinfo(struct net_device *netdev, 778 struct ethtool_drvinfo *drvinfo) 779{ 780 struct igb_adapter *adapter = netdev_priv(netdev); 781 782 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver)); 783 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version)); 784 785 /* 786 * EEPROM image version # is reported as firmware version # for 787 * 82575 controllers 788 */ 789 strlcpy(drvinfo->fw_version, adapter->fw_version, 790 sizeof(drvinfo->fw_version)); 791 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 792 sizeof(drvinfo->bus_info)); 793 drvinfo->n_stats = IGB_STATS_LEN; 794 drvinfo->testinfo_len = IGB_TEST_LEN; 795 drvinfo->regdump_len = igb_get_regs_len(netdev); 796 drvinfo->eedump_len = igb_get_eeprom_len(netdev); 797} 798 799static void igb_get_ringparam(struct net_device *netdev, 800 struct ethtool_ringparam *ring) 801{ 802 struct igb_adapter *adapter = netdev_priv(netdev); 803 804 ring->rx_max_pending = IGB_MAX_RXD; 805 ring->tx_max_pending = IGB_MAX_TXD; 806 ring->rx_pending = adapter->rx_ring_count; 807 ring->tx_pending = adapter->tx_ring_count; 808} 809 810static int igb_set_ringparam(struct net_device *netdev, 811 struct ethtool_ringparam *ring) 812{ 813 struct igb_adapter *adapter = netdev_priv(netdev); 814 struct igb_ring *temp_ring; 815 int i, err = 0; 816 u16 new_rx_count, new_tx_count; 817 818 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 819 return -EINVAL; 820 821 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD); 822 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD); 823 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE); 824 825 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD); 826 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD); 827 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE); 828 829 if ((new_tx_count == adapter->tx_ring_count) && 830 (new_rx_count == adapter->rx_ring_count)) { 831 /* nothing to do */ 832 return 0; 833 } 834 835 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 836 msleep(1); 837 838 if (!netif_running(adapter->netdev)) { 839 for (i = 0; i < adapter->num_tx_queues; i++) 840 adapter->tx_ring[i]->count = new_tx_count; 841 for (i = 0; i < adapter->num_rx_queues; i++) 842 adapter->rx_ring[i]->count = new_rx_count; 843 adapter->tx_ring_count = new_tx_count; 844 adapter->rx_ring_count = new_rx_count; 845 goto clear_reset; 846 } 847 848 if (adapter->num_tx_queues > adapter->num_rx_queues) 849 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring)); 850 else 851 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring)); 852 853 if (!temp_ring) { 854 err = -ENOMEM; 855 goto clear_reset; 856 } 857 858 igb_down(adapter); 859 860 /* 861 * We can't just free everything and then setup again, 862 * because the ISRs in MSI-X mode get passed pointers 863 * to the tx and rx ring structs. 864 */ 865 if (new_tx_count != adapter->tx_ring_count) { 866 for (i = 0; i < adapter->num_tx_queues; i++) { 867 memcpy(&temp_ring[i], adapter->tx_ring[i], 868 sizeof(struct igb_ring)); 869 870 temp_ring[i].count = new_tx_count; 871 err = igb_setup_tx_resources(&temp_ring[i]); 872 if (err) { 873 while (i) { 874 i--; 875 igb_free_tx_resources(&temp_ring[i]); 876 } 877 goto err_setup; 878 } 879 } 880 881 for (i = 0; i < adapter->num_tx_queues; i++) { 882 igb_free_tx_resources(adapter->tx_ring[i]); 883 884 memcpy(adapter->tx_ring[i], &temp_ring[i], 885 sizeof(struct igb_ring)); 886 } 887 888 adapter->tx_ring_count = new_tx_count; 889 } 890 891 if (new_rx_count != adapter->rx_ring_count) { 892 for (i = 0; i < adapter->num_rx_queues; i++) { 893 memcpy(&temp_ring[i], adapter->rx_ring[i], 894 sizeof(struct igb_ring)); 895 896 temp_ring[i].count = new_rx_count; 897 err = igb_setup_rx_resources(&temp_ring[i]); 898 if (err) { 899 while (i) { 900 i--; 901 igb_free_rx_resources(&temp_ring[i]); 902 } 903 goto err_setup; 904 } 905 906 } 907 908 for (i = 0; i < adapter->num_rx_queues; i++) { 909 igb_free_rx_resources(adapter->rx_ring[i]); 910 911 memcpy(adapter->rx_ring[i], &temp_ring[i], 912 sizeof(struct igb_ring)); 913 } 914 915 adapter->rx_ring_count = new_rx_count; 916 } 917err_setup: 918 igb_up(adapter); 919 vfree(temp_ring); 920clear_reset: 921 clear_bit(__IGB_RESETTING, &adapter->state); 922 return err; 923} 924 925/* ethtool register test data */ 926struct igb_reg_test { 927 u16 reg; 928 u16 reg_offset; 929 u16 array_len; 930 u16 test_type; 931 u32 mask; 932 u32 write; 933}; 934 935/* In the hardware, registers are laid out either singly, in arrays 936 * spaced 0x100 bytes apart, or in contiguous tables. We assume 937 * most tests take place on arrays or single registers (handled 938 * as a single-element array) and special-case the tables. 939 * Table tests are always pattern tests. 940 * 941 * We also make provision for some required setup steps by specifying 942 * registers to be written without any read-back testing. 943 */ 944 945#define PATTERN_TEST 1 946#define SET_READ_TEST 2 947#define WRITE_NO_TEST 3 948#define TABLE32_TEST 4 949#define TABLE64_TEST_LO 5 950#define TABLE64_TEST_HI 6 951 952/* i210 reg test */ 953static struct igb_reg_test reg_test_i210[] = { 954 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 955 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 956 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 957 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 958 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 959 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 960 /* RDH is read-only for i210, only test RDT. */ 961 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 962 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 963 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 964 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 965 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 966 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 967 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 968 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 969 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 970 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 971 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 972 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 973 { E1000_RA, 0, 16, TABLE64_TEST_LO, 974 0xFFFFFFFF, 0xFFFFFFFF }, 975 { E1000_RA, 0, 16, TABLE64_TEST_HI, 976 0x900FFFFF, 0xFFFFFFFF }, 977 { E1000_MTA, 0, 128, TABLE32_TEST, 978 0xFFFFFFFF, 0xFFFFFFFF }, 979 { 0, 0, 0, 0, 0 } 980}; 981 982/* i350 reg test */ 983static struct igb_reg_test reg_test_i350[] = { 984 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 985 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 986 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 987 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 }, 988 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 989 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 990 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 991 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 992 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 993 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 994 /* RDH is read-only for i350, only test RDT. */ 995 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 996 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 997 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 998 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 999 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1000 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1001 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1002 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1003 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1004 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1005 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1006 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1007 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1008 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1009 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1010 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1011 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1012 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1013 0xFFFFFFFF, 0xFFFFFFFF }, 1014 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1015 0xC3FFFFFF, 0xFFFFFFFF }, 1016 { E1000_RA2, 0, 16, TABLE64_TEST_LO, 1017 0xFFFFFFFF, 0xFFFFFFFF }, 1018 { E1000_RA2, 0, 16, TABLE64_TEST_HI, 1019 0xC3FFFFFF, 0xFFFFFFFF }, 1020 { E1000_MTA, 0, 128, TABLE32_TEST, 1021 0xFFFFFFFF, 0xFFFFFFFF }, 1022 { 0, 0, 0, 0 } 1023}; 1024 1025/* 82580 reg test */ 1026static struct igb_reg_test reg_test_82580[] = { 1027 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1028 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1029 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1030 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1031 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1032 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1033 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1034 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1035 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1036 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1037 /* RDH is read-only for 82580, only test RDT. */ 1038 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1039 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1040 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1041 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1042 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1043 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1044 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1045 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1046 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1047 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1048 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1049 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1050 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1051 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1052 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1053 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1054 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1055 { E1000_RA, 0, 16, TABLE64_TEST_LO, 1056 0xFFFFFFFF, 0xFFFFFFFF }, 1057 { E1000_RA, 0, 16, TABLE64_TEST_HI, 1058 0x83FFFFFF, 0xFFFFFFFF }, 1059 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 1060 0xFFFFFFFF, 0xFFFFFFFF }, 1061 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 1062 0x83FFFFFF, 0xFFFFFFFF }, 1063 { E1000_MTA, 0, 128, TABLE32_TEST, 1064 0xFFFFFFFF, 0xFFFFFFFF }, 1065 { 0, 0, 0, 0 } 1066}; 1067 1068/* 82576 reg test */ 1069static struct igb_reg_test reg_test_82576[] = { 1070 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1071 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1072 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1073 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1074 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1075 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1076 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1077 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1078 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1079 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1080 /* Enable all RX queues before testing. */ 1081 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, 1082 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, 1083 /* RDH is read-only for 82576, only test RDT. */ 1084 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1085 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1086 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1087 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 }, 1088 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1089 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1090 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1091 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1092 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1093 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1094 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1095 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1096 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1097 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1098 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1099 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1100 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1101 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1102 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1103 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1104 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1105 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1106 { 0, 0, 0, 0 } 1107}; 1108 1109/* 82575 register test */ 1110static struct igb_reg_test reg_test_82575[] = { 1111 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1112 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1113 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1114 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1115 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1116 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1117 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1118 /* Enable all four RX queues before testing. */ 1119 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, 1120 /* RDH is read-only for 82575, only test RDT. */ 1121 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1122 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1123 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1124 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1125 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1126 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1127 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1128 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1129 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1130 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, 1131 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, 1132 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1133 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, 1134 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1135 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, 1136 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1137 { 0, 0, 0, 0 } 1138}; 1139 1140static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data, 1141 int reg, u32 mask, u32 write) 1142{ 1143 struct e1000_hw *hw = &adapter->hw; 1144 u32 pat, val; 1145 static const u32 _test[] = 1146 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1147 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { 1148 wr32(reg, (_test[pat] & write)); 1149 val = rd32(reg) & mask; 1150 if (val != (_test[pat] & write & mask)) { 1151 dev_err(&adapter->pdev->dev, 1152 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1153 reg, val, (_test[pat] & write & mask)); 1154 *data = reg; 1155 return 1; 1156 } 1157 } 1158 1159 return 0; 1160} 1161 1162static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data, 1163 int reg, u32 mask, u32 write) 1164{ 1165 struct e1000_hw *hw = &adapter->hw; 1166 u32 val; 1167 wr32(reg, write & mask); 1168 val = rd32(reg); 1169 if ((write & mask) != (val & mask)) { 1170 dev_err(&adapter->pdev->dev, 1171 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", reg, 1172 (val & mask), (write & mask)); 1173 *data = reg; 1174 return 1; 1175 } 1176 1177 return 0; 1178} 1179 1180#define REG_PATTERN_TEST(reg, mask, write) \ 1181 do { \ 1182 if (reg_pattern_test(adapter, data, reg, mask, write)) \ 1183 return 1; \ 1184 } while (0) 1185 1186#define REG_SET_AND_CHECK(reg, mask, write) \ 1187 do { \ 1188 if (reg_set_and_check(adapter, data, reg, mask, write)) \ 1189 return 1; \ 1190 } while (0) 1191 1192static int igb_reg_test(struct igb_adapter *adapter, u64 *data) 1193{ 1194 struct e1000_hw *hw = &adapter->hw; 1195 struct igb_reg_test *test; 1196 u32 value, before, after; 1197 u32 i, toggle; 1198 1199 switch (adapter->hw.mac.type) { 1200 case e1000_i350: 1201 test = reg_test_i350; 1202 toggle = 0x7FEFF3FF; 1203 break; 1204 case e1000_i210: 1205 case e1000_i211: 1206 test = reg_test_i210; 1207 toggle = 0x7FEFF3FF; 1208 break; 1209 case e1000_82580: 1210 test = reg_test_82580; 1211 toggle = 0x7FEFF3FF; 1212 break; 1213 case e1000_82576: 1214 test = reg_test_82576; 1215 toggle = 0x7FFFF3FF; 1216 break; 1217 default: 1218 test = reg_test_82575; 1219 toggle = 0x7FFFF3FF; 1220 break; 1221 } 1222 1223 /* Because the status register is such a special case, 1224 * we handle it separately from the rest of the register 1225 * tests. Some bits are read-only, some toggle, and some 1226 * are writable on newer MACs. 1227 */ 1228 before = rd32(E1000_STATUS); 1229 value = (rd32(E1000_STATUS) & toggle); 1230 wr32(E1000_STATUS, toggle); 1231 after = rd32(E1000_STATUS) & toggle; 1232 if (value != after) { 1233 dev_err(&adapter->pdev->dev, 1234 "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1235 after, value); 1236 *data = 1; 1237 return 1; 1238 } 1239 /* restore previous status */ 1240 wr32(E1000_STATUS, before); 1241 1242 /* Perform the remainder of the register test, looping through 1243 * the test table until we either fail or reach the null entry. 1244 */ 1245 while (test->reg) { 1246 for (i = 0; i < test->array_len; i++) { 1247 switch (test->test_type) { 1248 case PATTERN_TEST: 1249 REG_PATTERN_TEST(test->reg + 1250 (i * test->reg_offset), 1251 test->mask, 1252 test->write); 1253 break; 1254 case SET_READ_TEST: 1255 REG_SET_AND_CHECK(test->reg + 1256 (i * test->reg_offset), 1257 test->mask, 1258 test->write); 1259 break; 1260 case WRITE_NO_TEST: 1261 writel(test->write, 1262 (adapter->hw.hw_addr + test->reg) 1263 + (i * test->reg_offset)); 1264 break; 1265 case TABLE32_TEST: 1266 REG_PATTERN_TEST(test->reg + (i * 4), 1267 test->mask, 1268 test->write); 1269 break; 1270 case TABLE64_TEST_LO: 1271 REG_PATTERN_TEST(test->reg + (i * 8), 1272 test->mask, 1273 test->write); 1274 break; 1275 case TABLE64_TEST_HI: 1276 REG_PATTERN_TEST((test->reg + 4) + (i * 8), 1277 test->mask, 1278 test->write); 1279 break; 1280 } 1281 } 1282 test++; 1283 } 1284 1285 *data = 0; 1286 return 0; 1287} 1288 1289static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data) 1290{ 1291 *data = 0; 1292 1293 /* Validate eeprom on all parts but i211 */ 1294 if (adapter->hw.mac.type != e1000_i211) { 1295 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1296 *data = 2; 1297 } 1298 1299 return *data; 1300} 1301 1302static irqreturn_t igb_test_intr(int irq, void *data) 1303{ 1304 struct igb_adapter *adapter = (struct igb_adapter *) data; 1305 struct e1000_hw *hw = &adapter->hw; 1306 1307 adapter->test_icr |= rd32(E1000_ICR); 1308 1309 return IRQ_HANDLED; 1310} 1311 1312static int igb_intr_test(struct igb_adapter *adapter, u64 *data) 1313{ 1314 struct e1000_hw *hw = &adapter->hw; 1315 struct net_device *netdev = adapter->netdev; 1316 u32 mask, ics_mask, i = 0, shared_int = true; 1317 u32 irq = adapter->pdev->irq; 1318 1319 *data = 0; 1320 1321 /* Hook up test interrupt handler just for this test */ 1322 if (adapter->msix_entries) { 1323 if (request_irq(adapter->msix_entries[0].vector, 1324 igb_test_intr, 0, netdev->name, adapter)) { 1325 *data = 1; 1326 return -1; 1327 } 1328 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 1329 shared_int = false; 1330 if (request_irq(irq, 1331 igb_test_intr, 0, netdev->name, adapter)) { 1332 *data = 1; 1333 return -1; 1334 } 1335 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED, 1336 netdev->name, adapter)) { 1337 shared_int = false; 1338 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED, 1339 netdev->name, adapter)) { 1340 *data = 1; 1341 return -1; 1342 } 1343 dev_info(&adapter->pdev->dev, "testing %s interrupt\n", 1344 (shared_int ? "shared" : "unshared")); 1345 1346 /* Disable all the interrupts */ 1347 wr32(E1000_IMC, ~0); 1348 wrfl(); 1349 msleep(10); 1350 1351 /* Define all writable bits for ICS */ 1352 switch (hw->mac.type) { 1353 case e1000_82575: 1354 ics_mask = 0x37F47EDD; 1355 break; 1356 case e1000_82576: 1357 ics_mask = 0x77D4FBFD; 1358 break; 1359 case e1000_82580: 1360 ics_mask = 0x77DCFED5; 1361 break; 1362 case e1000_i350: 1363 case e1000_i210: 1364 case e1000_i211: 1365 ics_mask = 0x77DCFED5; 1366 break; 1367 default: 1368 ics_mask = 0x7FFFFFFF; 1369 break; 1370 } 1371 1372 /* Test each interrupt */ 1373 for (; i < 31; i++) { 1374 /* Interrupt to test */ 1375 mask = 1 << i; 1376 1377 if (!(mask & ics_mask)) 1378 continue; 1379 1380 if (!shared_int) { 1381 /* Disable the interrupt to be reported in 1382 * the cause register and then force the same 1383 * interrupt and see if one gets posted. If 1384 * an interrupt was posted to the bus, the 1385 * test failed. 1386 */ 1387 adapter->test_icr = 0; 1388 1389 /* Flush any pending interrupts */ 1390 wr32(E1000_ICR, ~0); 1391 1392 wr32(E1000_IMC, mask); 1393 wr32(E1000_ICS, mask); 1394 wrfl(); 1395 msleep(10); 1396 1397 if (adapter->test_icr & mask) { 1398 *data = 3; 1399 break; 1400 } 1401 } 1402 1403 /* Enable the interrupt to be reported in 1404 * the cause register and then force the same 1405 * interrupt and see if one gets posted. If 1406 * an interrupt was not posted to the bus, the 1407 * test failed. 1408 */ 1409 adapter->test_icr = 0; 1410 1411 /* Flush any pending interrupts */ 1412 wr32(E1000_ICR, ~0); 1413 1414 wr32(E1000_IMS, mask); 1415 wr32(E1000_ICS, mask); 1416 wrfl(); 1417 msleep(10); 1418 1419 if (!(adapter->test_icr & mask)) { 1420 *data = 4; 1421 break; 1422 } 1423 1424 if (!shared_int) { 1425 /* Disable the other interrupts to be reported in 1426 * the cause register and then force the other 1427 * interrupts and see if any get posted. If 1428 * an interrupt was posted to the bus, the 1429 * test failed. 1430 */ 1431 adapter->test_icr = 0; 1432 1433 /* Flush any pending interrupts */ 1434 wr32(E1000_ICR, ~0); 1435 1436 wr32(E1000_IMC, ~mask); 1437 wr32(E1000_ICS, ~mask); 1438 wrfl(); 1439 msleep(10); 1440 1441 if (adapter->test_icr & mask) { 1442 *data = 5; 1443 break; 1444 } 1445 } 1446 } 1447 1448 /* Disable all the interrupts */ 1449 wr32(E1000_IMC, ~0); 1450 wrfl(); 1451 msleep(10); 1452 1453 /* Unhook test interrupt handler */ 1454 if (adapter->msix_entries) 1455 free_irq(adapter->msix_entries[0].vector, adapter); 1456 else 1457 free_irq(irq, adapter); 1458 1459 return *data; 1460} 1461 1462static void igb_free_desc_rings(struct igb_adapter *adapter) 1463{ 1464 igb_free_tx_resources(&adapter->test_tx_ring); 1465 igb_free_rx_resources(&adapter->test_rx_ring); 1466} 1467 1468static int igb_setup_desc_rings(struct igb_adapter *adapter) 1469{ 1470 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1471 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1472 struct e1000_hw *hw = &adapter->hw; 1473 int ret_val; 1474 1475 /* Setup Tx descriptor ring and Tx buffers */ 1476 tx_ring->count = IGB_DEFAULT_TXD; 1477 tx_ring->dev = &adapter->pdev->dev; 1478 tx_ring->netdev = adapter->netdev; 1479 tx_ring->reg_idx = adapter->vfs_allocated_count; 1480 1481 if (igb_setup_tx_resources(tx_ring)) { 1482 ret_val = 1; 1483 goto err_nomem; 1484 } 1485 1486 igb_setup_tctl(adapter); 1487 igb_configure_tx_ring(adapter, tx_ring); 1488 1489 /* Setup Rx descriptor ring and Rx buffers */ 1490 rx_ring->count = IGB_DEFAULT_RXD; 1491 rx_ring->dev = &adapter->pdev->dev; 1492 rx_ring->netdev = adapter->netdev; 1493 rx_ring->reg_idx = adapter->vfs_allocated_count; 1494 1495 if (igb_setup_rx_resources(rx_ring)) { 1496 ret_val = 3; 1497 goto err_nomem; 1498 } 1499 1500 /* set the default queue to queue 0 of PF */ 1501 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3); 1502 1503 /* enable receive ring */ 1504 igb_setup_rctl(adapter); 1505 igb_configure_rx_ring(adapter, rx_ring); 1506 1507 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring)); 1508 1509 return 0; 1510 1511err_nomem: 1512 igb_free_desc_rings(adapter); 1513 return ret_val; 1514} 1515 1516static void igb_phy_disable_receiver(struct igb_adapter *adapter) 1517{ 1518 struct e1000_hw *hw = &adapter->hw; 1519 1520 /* Write out to PHY registers 29 and 30 to disable the Receiver. */ 1521 igb_write_phy_reg(hw, 29, 0x001F); 1522 igb_write_phy_reg(hw, 30, 0x8FFC); 1523 igb_write_phy_reg(hw, 29, 0x001A); 1524 igb_write_phy_reg(hw, 30, 0x8FF0); 1525} 1526 1527static int igb_integrated_phy_loopback(struct igb_adapter *adapter) 1528{ 1529 struct e1000_hw *hw = &adapter->hw; 1530 u32 ctrl_reg = 0; 1531 1532 hw->mac.autoneg = false; 1533 1534 if (hw->phy.type == e1000_phy_m88) { 1535 if (hw->phy.id != I210_I_PHY_ID) { 1536 /* Auto-MDI/MDIX Off */ 1537 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 1538 /* reset to update Auto-MDI/MDIX */ 1539 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); 1540 /* autoneg off */ 1541 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); 1542 } else { 1543 /* force 1000, set loopback */ 1544 igb_write_phy_reg(hw, I347AT4_PAGE_SELECT, 0); 1545 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1546 } 1547 } 1548 1549 /* add small delay to avoid loopback test failure */ 1550 msleep(50); 1551 1552 /* force 1000, set loopback */ 1553 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1554 1555 /* Now set up the MAC to the same speed/duplex as the PHY. */ 1556 ctrl_reg = rd32(E1000_CTRL); 1557 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1558 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1559 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 1560 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ 1561 E1000_CTRL_FD | /* Force Duplex to FULL */ 1562 E1000_CTRL_SLU); /* Set link up enable bit */ 1563 1564 if (hw->phy.type == e1000_phy_m88) 1565 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1566 1567 wr32(E1000_CTRL, ctrl_reg); 1568 1569 /* Disable the receiver on the PHY so when a cable is plugged in, the 1570 * PHY does not begin to autoneg when a cable is reconnected to the NIC. 1571 */ 1572 if (hw->phy.type == e1000_phy_m88) 1573 igb_phy_disable_receiver(adapter); 1574 1575 mdelay(500); 1576 return 0; 1577} 1578 1579static int igb_set_phy_loopback(struct igb_adapter *adapter) 1580{ 1581 return igb_integrated_phy_loopback(adapter); 1582} 1583 1584static int igb_setup_loopback_test(struct igb_adapter *adapter) 1585{ 1586 struct e1000_hw *hw = &adapter->hw; 1587 u32 reg; 1588 1589 reg = rd32(E1000_CTRL_EXT); 1590 1591 /* use CTRL_EXT to identify link type as SGMII can appear as copper */ 1592 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) { 1593 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1594 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1595 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1596 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) { 1597 1598 /* Enable DH89xxCC MPHY for near end loopback */ 1599 reg = rd32(E1000_MPHY_ADDR_CTL); 1600 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1601 E1000_MPHY_PCS_CLK_REG_OFFSET; 1602 wr32(E1000_MPHY_ADDR_CTL, reg); 1603 1604 reg = rd32(E1000_MPHY_DATA); 1605 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1606 wr32(E1000_MPHY_DATA, reg); 1607 } 1608 1609 reg = rd32(E1000_RCTL); 1610 reg |= E1000_RCTL_LBM_TCVR; 1611 wr32(E1000_RCTL, reg); 1612 1613 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); 1614 1615 reg = rd32(E1000_CTRL); 1616 reg &= ~(E1000_CTRL_RFCE | 1617 E1000_CTRL_TFCE | 1618 E1000_CTRL_LRST); 1619 reg |= E1000_CTRL_SLU | 1620 E1000_CTRL_FD; 1621 wr32(E1000_CTRL, reg); 1622 1623 /* Unset switch control to serdes energy detect */ 1624 reg = rd32(E1000_CONNSW); 1625 reg &= ~E1000_CONNSW_ENRGSRC; 1626 wr32(E1000_CONNSW, reg); 1627 1628 /* Unset sigdetect for SERDES loopback on 1629 * 82580 and i350 devices. 1630 */ 1631 switch (hw->mac.type) { 1632 case e1000_82580: 1633 case e1000_i350: 1634 reg = rd32(E1000_PCS_CFG0); 1635 reg |= E1000_PCS_CFG_IGN_SD; 1636 wr32(E1000_PCS_CFG0, reg); 1637 break; 1638 default: 1639 break; 1640 } 1641 1642 /* Set PCS register for forced speed */ 1643 reg = rd32(E1000_PCS_LCTL); 1644 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ 1645 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1646 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1647 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1648 E1000_PCS_LCTL_FSD | /* Force Speed */ 1649 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1650 wr32(E1000_PCS_LCTL, reg); 1651 1652 return 0; 1653 } 1654 1655 return igb_set_phy_loopback(adapter); 1656} 1657 1658static void igb_loopback_cleanup(struct igb_adapter *adapter) 1659{ 1660 struct e1000_hw *hw = &adapter->hw; 1661 u32 rctl; 1662 u16 phy_reg; 1663 1664 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1665 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1666 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1667 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) { 1668 u32 reg; 1669 1670 /* Disable near end loopback on DH89xxCC */ 1671 reg = rd32(E1000_MPHY_ADDR_CTL); 1672 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1673 E1000_MPHY_PCS_CLK_REG_OFFSET; 1674 wr32(E1000_MPHY_ADDR_CTL, reg); 1675 1676 reg = rd32(E1000_MPHY_DATA); 1677 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1678 wr32(E1000_MPHY_DATA, reg); 1679 } 1680 1681 rctl = rd32(E1000_RCTL); 1682 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 1683 wr32(E1000_RCTL, rctl); 1684 1685 hw->mac.autoneg = true; 1686 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); 1687 if (phy_reg & MII_CR_LOOPBACK) { 1688 phy_reg &= ~MII_CR_LOOPBACK; 1689 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); 1690 igb_phy_sw_reset(hw); 1691 } 1692} 1693 1694static void igb_create_lbtest_frame(struct sk_buff *skb, 1695 unsigned int frame_size) 1696{ 1697 memset(skb->data, 0xFF, frame_size); 1698 frame_size /= 2; 1699 memset(&skb->data[frame_size], 0xAA, frame_size - 1); 1700 memset(&skb->data[frame_size + 10], 0xBE, 1); 1701 memset(&skb->data[frame_size + 12], 0xAF, 1); 1702} 1703 1704static int igb_check_lbtest_frame(struct igb_rx_buffer *rx_buffer, 1705 unsigned int frame_size) 1706{ 1707 unsigned char *data; 1708 bool match = true; 1709 1710 frame_size >>= 1; 1711 1712 data = kmap(rx_buffer->page); 1713 1714 if (data[3] != 0xFF || 1715 data[frame_size + 10] != 0xBE || 1716 data[frame_size + 12] != 0xAF) 1717 match = false; 1718 1719 kunmap(rx_buffer->page); 1720 1721 return match; 1722} 1723 1724static int igb_clean_test_rings(struct igb_ring *rx_ring, 1725 struct igb_ring *tx_ring, 1726 unsigned int size) 1727{ 1728 union e1000_adv_rx_desc *rx_desc; 1729 struct igb_rx_buffer *rx_buffer_info; 1730 struct igb_tx_buffer *tx_buffer_info; 1731 u16 rx_ntc, tx_ntc, count = 0; 1732 1733 /* initialize next to clean and descriptor values */ 1734 rx_ntc = rx_ring->next_to_clean; 1735 tx_ntc = tx_ring->next_to_clean; 1736 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1737 1738 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) { 1739 /* check rx buffer */ 1740 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc]; 1741 1742 /* sync Rx buffer for CPU read */ 1743 dma_sync_single_for_cpu(rx_ring->dev, 1744 rx_buffer_info->dma, 1745 IGB_RX_BUFSZ, 1746 DMA_FROM_DEVICE); 1747 1748 /* verify contents of skb */ 1749 if (igb_check_lbtest_frame(rx_buffer_info, size)) 1750 count++; 1751 1752 /* sync Rx buffer for device write */ 1753 dma_sync_single_for_device(rx_ring->dev, 1754 rx_buffer_info->dma, 1755 IGB_RX_BUFSZ, 1756 DMA_FROM_DEVICE); 1757 1758 /* unmap buffer on tx side */ 1759 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; 1760 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 1761 1762 /* increment rx/tx next to clean counters */ 1763 rx_ntc++; 1764 if (rx_ntc == rx_ring->count) 1765 rx_ntc = 0; 1766 tx_ntc++; 1767 if (tx_ntc == tx_ring->count) 1768 tx_ntc = 0; 1769 1770 /* fetch next descriptor */ 1771 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1772 } 1773 1774 netdev_tx_reset_queue(txring_txq(tx_ring)); 1775 1776 /* re-map buffers to ring, store next to clean values */ 1777 igb_alloc_rx_buffers(rx_ring, count); 1778 rx_ring->next_to_clean = rx_ntc; 1779 tx_ring->next_to_clean = tx_ntc; 1780 1781 return count; 1782} 1783 1784static int igb_run_loopback_test(struct igb_adapter *adapter) 1785{ 1786 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1787 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1788 u16 i, j, lc, good_cnt; 1789 int ret_val = 0; 1790 unsigned int size = IGB_RX_HDR_LEN; 1791 netdev_tx_t tx_ret_val; 1792 struct sk_buff *skb; 1793 1794 /* allocate test skb */ 1795 skb = alloc_skb(size, GFP_KERNEL); 1796 if (!skb) 1797 return 11; 1798 1799 /* place data into test skb */ 1800 igb_create_lbtest_frame(skb, size); 1801 skb_put(skb, size); 1802 1803 /* 1804 * Calculate the loop count based on the largest descriptor ring 1805 * The idea is to wrap the largest ring a number of times using 64 1806 * send/receive pairs during each loop 1807 */ 1808 1809 if (rx_ring->count <= tx_ring->count) 1810 lc = ((tx_ring->count / 64) * 2) + 1; 1811 else 1812 lc = ((rx_ring->count / 64) * 2) + 1; 1813 1814 for (j = 0; j <= lc; j++) { /* loop count loop */ 1815 /* reset count of good packets */ 1816 good_cnt = 0; 1817 1818 /* place 64 packets on the transmit queue*/ 1819 for (i = 0; i < 64; i++) { 1820 skb_get(skb); 1821 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring); 1822 if (tx_ret_val == NETDEV_TX_OK) 1823 good_cnt++; 1824 } 1825 1826 if (good_cnt != 64) { 1827 ret_val = 12; 1828 break; 1829 } 1830 1831 /* allow 200 milliseconds for packets to go from tx to rx */ 1832 msleep(200); 1833 1834 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size); 1835 if (good_cnt != 64) { 1836 ret_val = 13; 1837 break; 1838 } 1839 } /* end loop count loop */ 1840 1841 /* free the original skb */ 1842 kfree_skb(skb); 1843 1844 return ret_val; 1845} 1846 1847static int igb_loopback_test(struct igb_adapter *adapter, u64 *data) 1848{ 1849 /* PHY loopback cannot be performed if SoL/IDER 1850 * sessions are active */ 1851 if (igb_check_reset_block(&adapter->hw)) { 1852 dev_err(&adapter->pdev->dev, 1853 "Cannot do PHY loopback test when SoL/IDER is active.\n"); 1854 *data = 0; 1855 goto out; 1856 } 1857 *data = igb_setup_desc_rings(adapter); 1858 if (*data) 1859 goto out; 1860 *data = igb_setup_loopback_test(adapter); 1861 if (*data) 1862 goto err_loopback; 1863 *data = igb_run_loopback_test(adapter); 1864 igb_loopback_cleanup(adapter); 1865 1866err_loopback: 1867 igb_free_desc_rings(adapter); 1868out: 1869 return *data; 1870} 1871 1872static int igb_link_test(struct igb_adapter *adapter, u64 *data) 1873{ 1874 struct e1000_hw *hw = &adapter->hw; 1875 *data = 0; 1876 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 1877 int i = 0; 1878 hw->mac.serdes_has_link = false; 1879 1880 /* On some blade server designs, link establishment 1881 * could take as long as 2-3 minutes */ 1882 do { 1883 hw->mac.ops.check_for_link(&adapter->hw); 1884 if (hw->mac.serdes_has_link) 1885 return *data; 1886 msleep(20); 1887 } while (i++ < 3750); 1888 1889 *data = 1; 1890 } else { 1891 hw->mac.ops.check_for_link(&adapter->hw); 1892 if (hw->mac.autoneg) 1893 msleep(4000); 1894 1895 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) 1896 *data = 1; 1897 } 1898 return *data; 1899} 1900 1901static void igb_diag_test(struct net_device *netdev, 1902 struct ethtool_test *eth_test, u64 *data) 1903{ 1904 struct igb_adapter *adapter = netdev_priv(netdev); 1905 u16 autoneg_advertised; 1906 u8 forced_speed_duplex, autoneg; 1907 bool if_running = netif_running(netdev); 1908 1909 set_bit(__IGB_TESTING, &adapter->state); 1910 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 1911 /* Offline tests */ 1912 1913 /* save speed, duplex, autoneg settings */ 1914 autoneg_advertised = adapter->hw.phy.autoneg_advertised; 1915 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; 1916 autoneg = adapter->hw.mac.autoneg; 1917 1918 dev_info(&adapter->pdev->dev, "offline testing starting\n"); 1919 1920 /* power up link for link test */ 1921 igb_power_up_link(adapter); 1922 1923 /* Link test performed before hardware reset so autoneg doesn't 1924 * interfere with test result */ 1925 if (igb_link_test(adapter, &data[4])) 1926 eth_test->flags |= ETH_TEST_FL_FAILED; 1927 1928 if (if_running) 1929 /* indicate we're in test mode */ 1930 dev_close(netdev); 1931 else 1932 igb_reset(adapter); 1933 1934 if (igb_reg_test(adapter, &data[0])) 1935 eth_test->flags |= ETH_TEST_FL_FAILED; 1936 1937 igb_reset(adapter); 1938 if (igb_eeprom_test(adapter, &data[1])) 1939 eth_test->flags |= ETH_TEST_FL_FAILED; 1940 1941 igb_reset(adapter); 1942 if (igb_intr_test(adapter, &data[2])) 1943 eth_test->flags |= ETH_TEST_FL_FAILED; 1944 1945 igb_reset(adapter); 1946 /* power up link for loopback test */ 1947 igb_power_up_link(adapter); 1948 if (igb_loopback_test(adapter, &data[3])) 1949 eth_test->flags |= ETH_TEST_FL_FAILED; 1950 1951 /* restore speed, duplex, autoneg settings */ 1952 adapter->hw.phy.autoneg_advertised = autoneg_advertised; 1953 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; 1954 adapter->hw.mac.autoneg = autoneg; 1955 1956 /* force this routine to wait until autoneg complete/timeout */ 1957 adapter->hw.phy.autoneg_wait_to_complete = true; 1958 igb_reset(adapter); 1959 adapter->hw.phy.autoneg_wait_to_complete = false; 1960 1961 clear_bit(__IGB_TESTING, &adapter->state); 1962 if (if_running) 1963 dev_open(netdev); 1964 } else { 1965 dev_info(&adapter->pdev->dev, "online testing starting\n"); 1966 1967 /* PHY is powered down when interface is down */ 1968 if (if_running && igb_link_test(adapter, &data[4])) 1969 eth_test->flags |= ETH_TEST_FL_FAILED; 1970 else 1971 data[4] = 0; 1972 1973 /* Online tests aren't run; pass by default */ 1974 data[0] = 0; 1975 data[1] = 0; 1976 data[2] = 0; 1977 data[3] = 0; 1978 1979 clear_bit(__IGB_TESTING, &adapter->state); 1980 } 1981 msleep_interruptible(4 * 1000); 1982} 1983 1984static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 1985{ 1986 struct igb_adapter *adapter = netdev_priv(netdev); 1987 1988 wol->supported = WAKE_UCAST | WAKE_MCAST | 1989 WAKE_BCAST | WAKE_MAGIC | 1990 WAKE_PHY; 1991 wol->wolopts = 0; 1992 1993 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 1994 return; 1995 1996 /* apply any specific unsupported masks here */ 1997 switch (adapter->hw.device_id) { 1998 default: 1999 break; 2000 } 2001 2002 if (adapter->wol & E1000_WUFC_EX) 2003 wol->wolopts |= WAKE_UCAST; 2004 if (adapter->wol & E1000_WUFC_MC) 2005 wol->wolopts |= WAKE_MCAST; 2006 if (adapter->wol & E1000_WUFC_BC) 2007 wol->wolopts |= WAKE_BCAST; 2008 if (adapter->wol & E1000_WUFC_MAG) 2009 wol->wolopts |= WAKE_MAGIC; 2010 if (adapter->wol & E1000_WUFC_LNKC) 2011 wol->wolopts |= WAKE_PHY; 2012} 2013 2014static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2015{ 2016 struct igb_adapter *adapter = netdev_priv(netdev); 2017 2018 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2019 return -EOPNOTSUPP; 2020 2021 if (!(adapter->flags & IGB_FLAG_WOL_SUPPORTED)) 2022 return wol->wolopts ? -EOPNOTSUPP : 0; 2023 2024 /* these settings will always override what we currently have */ 2025 adapter->wol = 0; 2026 2027 if (wol->wolopts & WAKE_UCAST) 2028 adapter->wol |= E1000_WUFC_EX; 2029 if (wol->wolopts & WAKE_MCAST) 2030 adapter->wol |= E1000_WUFC_MC; 2031 if (wol->wolopts & WAKE_BCAST) 2032 adapter->wol |= E1000_WUFC_BC; 2033 if (wol->wolopts & WAKE_MAGIC) 2034 adapter->wol |= E1000_WUFC_MAG; 2035 if (wol->wolopts & WAKE_PHY) 2036 adapter->wol |= E1000_WUFC_LNKC; 2037 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2038 2039 return 0; 2040} 2041 2042/* bit defines for adapter->led_status */ 2043#define IGB_LED_ON 0 2044 2045static int igb_set_phys_id(struct net_device *netdev, 2046 enum ethtool_phys_id_state state) 2047{ 2048 struct igb_adapter *adapter = netdev_priv(netdev); 2049 struct e1000_hw *hw = &adapter->hw; 2050 2051 switch (state) { 2052 case ETHTOOL_ID_ACTIVE: 2053 igb_blink_led(hw); 2054 return 2; 2055 case ETHTOOL_ID_ON: 2056 igb_blink_led(hw); 2057 break; 2058 case ETHTOOL_ID_OFF: 2059 igb_led_off(hw); 2060 break; 2061 case ETHTOOL_ID_INACTIVE: 2062 igb_led_off(hw); 2063 clear_bit(IGB_LED_ON, &adapter->led_status); 2064 igb_cleanup_led(hw); 2065 break; 2066 } 2067 2068 return 0; 2069} 2070 2071static int igb_set_coalesce(struct net_device *netdev, 2072 struct ethtool_coalesce *ec) 2073{ 2074 struct igb_adapter *adapter = netdev_priv(netdev); 2075 int i; 2076 2077 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2078 ((ec->rx_coalesce_usecs > 3) && 2079 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2080 (ec->rx_coalesce_usecs == 2)) 2081 return -EINVAL; 2082 2083 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2084 ((ec->tx_coalesce_usecs > 3) && 2085 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2086 (ec->tx_coalesce_usecs == 2)) 2087 return -EINVAL; 2088 2089 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs) 2090 return -EINVAL; 2091 2092 /* If ITR is disabled, disable DMAC */ 2093 if (ec->rx_coalesce_usecs == 0) { 2094 if (adapter->flags & IGB_FLAG_DMAC) 2095 adapter->flags &= ~IGB_FLAG_DMAC; 2096 } 2097 2098 /* convert to rate of irq's per second */ 2099 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) 2100 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2101 else 2102 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2103 2104 /* convert to rate of irq's per second */ 2105 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS) 2106 adapter->tx_itr_setting = adapter->rx_itr_setting; 2107 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3) 2108 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2109 else 2110 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2111 2112 for (i = 0; i < adapter->num_q_vectors; i++) { 2113 struct igb_q_vector *q_vector = adapter->q_vector[i]; 2114 q_vector->tx.work_limit = adapter->tx_work_limit; 2115 if (q_vector->rx.ring) 2116 q_vector->itr_val = adapter->rx_itr_setting; 2117 else 2118 q_vector->itr_val = adapter->tx_itr_setting; 2119 if (q_vector->itr_val && q_vector->itr_val <= 3) 2120 q_vector->itr_val = IGB_START_ITR; 2121 q_vector->set_itr = 1; 2122 } 2123 2124 return 0; 2125} 2126 2127static int igb_get_coalesce(struct net_device *netdev, 2128 struct ethtool_coalesce *ec) 2129{ 2130 struct igb_adapter *adapter = netdev_priv(netdev); 2131 2132 if (adapter->rx_itr_setting <= 3) 2133 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2134 else 2135 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2136 2137 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) { 2138 if (adapter->tx_itr_setting <= 3) 2139 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2140 else 2141 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2142 } 2143 2144 return 0; 2145} 2146 2147static int igb_nway_reset(struct net_device *netdev) 2148{ 2149 struct igb_adapter *adapter = netdev_priv(netdev); 2150 if (netif_running(netdev)) 2151 igb_reinit_locked(adapter); 2152 return 0; 2153} 2154 2155static int igb_get_sset_count(struct net_device *netdev, int sset) 2156{ 2157 switch (sset) { 2158 case ETH_SS_STATS: 2159 return IGB_STATS_LEN; 2160 case ETH_SS_TEST: 2161 return IGB_TEST_LEN; 2162 default: 2163 return -ENOTSUPP; 2164 } 2165} 2166 2167static void igb_get_ethtool_stats(struct net_device *netdev, 2168 struct ethtool_stats *stats, u64 *data) 2169{ 2170 struct igb_adapter *adapter = netdev_priv(netdev); 2171 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 2172 unsigned int start; 2173 struct igb_ring *ring; 2174 int i, j; 2175 char *p; 2176 2177 spin_lock(&adapter->stats64_lock); 2178 igb_update_stats(adapter, net_stats); 2179 2180 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2181 p = (char *)adapter + igb_gstrings_stats[i].stat_offset; 2182 data[i] = (igb_gstrings_stats[i].sizeof_stat == 2183 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2184 } 2185 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) { 2186 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset; 2187 data[i] = (igb_gstrings_net_stats[j].sizeof_stat == 2188 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2189 } 2190 for (j = 0; j < adapter->num_tx_queues; j++) { 2191 u64 restart2; 2192 2193 ring = adapter->tx_ring[j]; 2194 do { 2195 start = u64_stats_fetch_begin_bh(&ring->tx_syncp); 2196 data[i] = ring->tx_stats.packets; 2197 data[i+1] = ring->tx_stats.bytes; 2198 data[i+2] = ring->tx_stats.restart_queue; 2199 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); 2200 do { 2201 start = u64_stats_fetch_begin_bh(&ring->tx_syncp2); 2202 restart2 = ring->tx_stats.restart_queue2; 2203 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start)); 2204 data[i+2] += restart2; 2205 2206 i += IGB_TX_QUEUE_STATS_LEN; 2207 } 2208 for (j = 0; j < adapter->num_rx_queues; j++) { 2209 ring = adapter->rx_ring[j]; 2210 do { 2211 start = u64_stats_fetch_begin_bh(&ring->rx_syncp); 2212 data[i] = ring->rx_stats.packets; 2213 data[i+1] = ring->rx_stats.bytes; 2214 data[i+2] = ring->rx_stats.drops; 2215 data[i+3] = ring->rx_stats.csum_err; 2216 data[i+4] = ring->rx_stats.alloc_failed; 2217 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); 2218 i += IGB_RX_QUEUE_STATS_LEN; 2219 } 2220 spin_unlock(&adapter->stats64_lock); 2221} 2222 2223static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2224{ 2225 struct igb_adapter *adapter = netdev_priv(netdev); 2226 u8 *p = data; 2227 int i; 2228 2229 switch (stringset) { 2230 case ETH_SS_TEST: 2231 memcpy(data, *igb_gstrings_test, 2232 IGB_TEST_LEN*ETH_GSTRING_LEN); 2233 break; 2234 case ETH_SS_STATS: 2235 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2236 memcpy(p, igb_gstrings_stats[i].stat_string, 2237 ETH_GSTRING_LEN); 2238 p += ETH_GSTRING_LEN; 2239 } 2240 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) { 2241 memcpy(p, igb_gstrings_net_stats[i].stat_string, 2242 ETH_GSTRING_LEN); 2243 p += ETH_GSTRING_LEN; 2244 } 2245 for (i = 0; i < adapter->num_tx_queues; i++) { 2246 sprintf(p, "tx_queue_%u_packets", i); 2247 p += ETH_GSTRING_LEN; 2248 sprintf(p, "tx_queue_%u_bytes", i); 2249 p += ETH_GSTRING_LEN; 2250 sprintf(p, "tx_queue_%u_restart", i); 2251 p += ETH_GSTRING_LEN; 2252 } 2253 for (i = 0; i < adapter->num_rx_queues; i++) { 2254 sprintf(p, "rx_queue_%u_packets", i); 2255 p += ETH_GSTRING_LEN; 2256 sprintf(p, "rx_queue_%u_bytes", i); 2257 p += ETH_GSTRING_LEN; 2258 sprintf(p, "rx_queue_%u_drops", i); 2259 p += ETH_GSTRING_LEN; 2260 sprintf(p, "rx_queue_%u_csum_err", i); 2261 p += ETH_GSTRING_LEN; 2262 sprintf(p, "rx_queue_%u_alloc_failed", i); 2263 p += ETH_GSTRING_LEN; 2264 } 2265/* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */ 2266 break; 2267 } 2268} 2269 2270static int igb_get_ts_info(struct net_device *dev, 2271 struct ethtool_ts_info *info) 2272{ 2273 struct igb_adapter *adapter = netdev_priv(dev); 2274 2275 switch (adapter->hw.mac.type) { 2276 case e1000_82575: 2277 info->so_timestamping = 2278 SOF_TIMESTAMPING_TX_SOFTWARE | 2279 SOF_TIMESTAMPING_RX_SOFTWARE | 2280 SOF_TIMESTAMPING_SOFTWARE; 2281 return 0; 2282 case e1000_82576: 2283 case e1000_82580: 2284 case e1000_i350: 2285 case e1000_i210: 2286 case e1000_i211: 2287 info->so_timestamping = 2288 SOF_TIMESTAMPING_TX_SOFTWARE | 2289 SOF_TIMESTAMPING_RX_SOFTWARE | 2290 SOF_TIMESTAMPING_SOFTWARE | 2291 SOF_TIMESTAMPING_TX_HARDWARE | 2292 SOF_TIMESTAMPING_RX_HARDWARE | 2293 SOF_TIMESTAMPING_RAW_HARDWARE; 2294 2295 if (adapter->ptp_clock) 2296 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2297 else 2298 info->phc_index = -1; 2299 2300 info->tx_types = 2301 (1 << HWTSTAMP_TX_OFF) | 2302 (1 << HWTSTAMP_TX_ON); 2303 2304 info->rx_filters = 1 << HWTSTAMP_FILTER_NONE; 2305 2306 /* 82576 does not support timestamping all packets. */ 2307 if (adapter->hw.mac.type >= e1000_82580) 2308 info->rx_filters |= 1 << HWTSTAMP_FILTER_ALL; 2309 else 2310 info->rx_filters |= 2311 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2312 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2313 (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) | 2314 (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) | 2315 (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) | 2316 (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) | 2317 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 2318 2319 return 0; 2320 default: 2321 return -EOPNOTSUPP; 2322 } 2323} 2324 2325static int igb_get_rss_hash_opts(struct igb_adapter *adapter, 2326 struct ethtool_rxnfc *cmd) 2327{ 2328 cmd->data = 0; 2329 2330 /* Report default options for RSS on igb */ 2331 switch (cmd->flow_type) { 2332 case TCP_V4_FLOW: 2333 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2334 case UDP_V4_FLOW: 2335 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2336 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2337 case SCTP_V4_FLOW: 2338 case AH_ESP_V4_FLOW: 2339 case AH_V4_FLOW: 2340 case ESP_V4_FLOW: 2341 case IPV4_FLOW: 2342 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2343 break; 2344 case TCP_V6_FLOW: 2345 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2346 case UDP_V6_FLOW: 2347 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2348 cmd->data |= RXH_L4_B_0_1 | RXH_L4_B_2_3; 2349 case SCTP_V6_FLOW: 2350 case AH_ESP_V6_FLOW: 2351 case AH_V6_FLOW: 2352 case ESP_V6_FLOW: 2353 case IPV6_FLOW: 2354 cmd->data |= RXH_IP_SRC | RXH_IP_DST; 2355 break; 2356 default: 2357 return -EINVAL; 2358 } 2359 2360 return 0; 2361} 2362 2363static int igb_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 2364 u32 *rule_locs) 2365{ 2366 struct igb_adapter *adapter = netdev_priv(dev); 2367 int ret = -EOPNOTSUPP; 2368 2369 switch (cmd->cmd) { 2370 case ETHTOOL_GRXRINGS: 2371 cmd->data = adapter->num_rx_queues; 2372 ret = 0; 2373 break; 2374 case ETHTOOL_GRXFH: 2375 ret = igb_get_rss_hash_opts(adapter, cmd); 2376 break; 2377 default: 2378 break; 2379 } 2380 2381 return ret; 2382} 2383 2384#define UDP_RSS_FLAGS (IGB_FLAG_RSS_FIELD_IPV4_UDP | \ 2385 IGB_FLAG_RSS_FIELD_IPV6_UDP) 2386static int igb_set_rss_hash_opt(struct igb_adapter *adapter, 2387 struct ethtool_rxnfc *nfc) 2388{ 2389 u32 flags = adapter->flags; 2390 2391 /* RSS does not support anything other than hashing 2392 * to queues on src and dst IPs and ports 2393 */ 2394 if (nfc->data & ~(RXH_IP_SRC | RXH_IP_DST | 2395 RXH_L4_B_0_1 | RXH_L4_B_2_3)) 2396 return -EINVAL; 2397 2398 switch (nfc->flow_type) { 2399 case TCP_V4_FLOW: 2400 case TCP_V6_FLOW: 2401 if (!(nfc->data & RXH_IP_SRC) || 2402 !(nfc->data & RXH_IP_DST) || 2403 !(nfc->data & RXH_L4_B_0_1) || 2404 !(nfc->data & RXH_L4_B_2_3)) 2405 return -EINVAL; 2406 break; 2407 case UDP_V4_FLOW: 2408 if (!(nfc->data & RXH_IP_SRC) || 2409 !(nfc->data & RXH_IP_DST)) 2410 return -EINVAL; 2411 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2412 case 0: 2413 flags &= ~IGB_FLAG_RSS_FIELD_IPV4_UDP; 2414 break; 2415 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2416 flags |= IGB_FLAG_RSS_FIELD_IPV4_UDP; 2417 break; 2418 default: 2419 return -EINVAL; 2420 } 2421 break; 2422 case UDP_V6_FLOW: 2423 if (!(nfc->data & RXH_IP_SRC) || 2424 !(nfc->data & RXH_IP_DST)) 2425 return -EINVAL; 2426 switch (nfc->data & (RXH_L4_B_0_1 | RXH_L4_B_2_3)) { 2427 case 0: 2428 flags &= ~IGB_FLAG_RSS_FIELD_IPV6_UDP; 2429 break; 2430 case (RXH_L4_B_0_1 | RXH_L4_B_2_3): 2431 flags |= IGB_FLAG_RSS_FIELD_IPV6_UDP; 2432 break; 2433 default: 2434 return -EINVAL; 2435 } 2436 break; 2437 case AH_ESP_V4_FLOW: 2438 case AH_V4_FLOW: 2439 case ESP_V4_FLOW: 2440 case SCTP_V4_FLOW: 2441 case AH_ESP_V6_FLOW: 2442 case AH_V6_FLOW: 2443 case ESP_V6_FLOW: 2444 case SCTP_V6_FLOW: 2445 if (!(nfc->data & RXH_IP_SRC) || 2446 !(nfc->data & RXH_IP_DST) || 2447 (nfc->data & RXH_L4_B_0_1) || 2448 (nfc->data & RXH_L4_B_2_3)) 2449 return -EINVAL; 2450 break; 2451 default: 2452 return -EINVAL; 2453 } 2454 2455 /* if we changed something we need to update flags */ 2456 if (flags != adapter->flags) { 2457 struct e1000_hw *hw = &adapter->hw; 2458 u32 mrqc = rd32(E1000_MRQC); 2459 2460 if ((flags & UDP_RSS_FLAGS) && 2461 !(adapter->flags & UDP_RSS_FLAGS)) 2462 dev_err(&adapter->pdev->dev, 2463 "enabling UDP RSS: fragmented packets may arrive out of order to the stack above\n"); 2464 2465 adapter->flags = flags; 2466 2467 /* Perform hash on these packet types */ 2468 mrqc |= E1000_MRQC_RSS_FIELD_IPV4 | 2469 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2470 E1000_MRQC_RSS_FIELD_IPV6 | 2471 E1000_MRQC_RSS_FIELD_IPV6_TCP; 2472 2473 mrqc &= ~(E1000_MRQC_RSS_FIELD_IPV4_UDP | 2474 E1000_MRQC_RSS_FIELD_IPV6_UDP); 2475 2476 if (flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2477 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 2478 2479 if (flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2480 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 2481 2482 wr32(E1000_MRQC, mrqc); 2483 } 2484 2485 return 0; 2486} 2487 2488static int igb_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 2489{ 2490 struct igb_adapter *adapter = netdev_priv(dev); 2491 int ret = -EOPNOTSUPP; 2492 2493 switch (cmd->cmd) { 2494 case ETHTOOL_SRXFH: 2495 ret = igb_set_rss_hash_opt(adapter, cmd); 2496 break; 2497 default: 2498 break; 2499 } 2500 2501 return ret; 2502} 2503 2504static int igb_get_eee(struct net_device *netdev, struct ethtool_eee *edata) 2505{ 2506 struct igb_adapter *adapter = netdev_priv(netdev); 2507 struct e1000_hw *hw = &adapter->hw; 2508 u32 ipcnfg, eeer; 2509 2510 if ((hw->mac.type < e1000_i350) || 2511 (hw->phy.media_type != e1000_media_type_copper)) 2512 return -EOPNOTSUPP; 2513 2514 edata->supported = (SUPPORTED_1000baseT_Full | 2515 SUPPORTED_100baseT_Full); 2516 2517 ipcnfg = rd32(E1000_IPCNFG); 2518 eeer = rd32(E1000_EEER); 2519 2520 /* EEE status on negotiated link */ 2521 if (ipcnfg & E1000_IPCNFG_EEE_1G_AN) 2522 edata->advertised = ADVERTISED_1000baseT_Full; 2523 2524 if (ipcnfg & E1000_IPCNFG_EEE_100M_AN) 2525 edata->advertised |= ADVERTISED_100baseT_Full; 2526 2527 if (eeer & E1000_EEER_EEE_NEG) 2528 edata->eee_active = true; 2529 2530 edata->eee_enabled = !hw->dev_spec._82575.eee_disable; 2531 2532 if (eeer & E1000_EEER_TX_LPI_EN) 2533 edata->tx_lpi_enabled = true; 2534 2535 /* Report correct negotiated EEE status for devices that 2536 * wrongly report EEE at half-duplex 2537 */ 2538 if (adapter->link_duplex == HALF_DUPLEX) { 2539 edata->eee_enabled = false; 2540 edata->eee_active = false; 2541 edata->tx_lpi_enabled = false; 2542 edata->advertised &= ~edata->advertised; 2543 } 2544 2545 return 0; 2546} 2547 2548static int igb_set_eee(struct net_device *netdev, 2549 struct ethtool_eee *edata) 2550{ 2551 struct igb_adapter *adapter = netdev_priv(netdev); 2552 struct e1000_hw *hw = &adapter->hw; 2553 struct ethtool_eee eee_curr; 2554 s32 ret_val; 2555 2556 if ((hw->mac.type < e1000_i350) || 2557 (hw->phy.media_type != e1000_media_type_copper)) 2558 return -EOPNOTSUPP; 2559 2560 ret_val = igb_get_eee(netdev, &eee_curr); 2561 if (ret_val) 2562 return ret_val; 2563 2564 if (eee_curr.eee_enabled) { 2565 if (eee_curr.tx_lpi_enabled != edata->tx_lpi_enabled) { 2566 dev_err(&adapter->pdev->dev, 2567 "Setting EEE tx-lpi is not supported\n"); 2568 return -EINVAL; 2569 } 2570 2571 /* Tx LPI timer is not implemented currently */ 2572 if (edata->tx_lpi_timer) { 2573 dev_err(&adapter->pdev->dev, 2574 "Setting EEE Tx LPI timer is not supported\n"); 2575 return -EINVAL; 2576 } 2577 2578 if (eee_curr.advertised != edata->advertised) { 2579 dev_err(&adapter->pdev->dev, 2580 "Setting EEE Advertisement is not supported\n"); 2581 return -EINVAL; 2582 } 2583 2584 } else if (!edata->eee_enabled) { 2585 dev_err(&adapter->pdev->dev, 2586 "Setting EEE options are not supported with EEE disabled\n"); 2587 return -EINVAL; 2588 } 2589 2590 if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) { 2591 hw->dev_spec._82575.eee_disable = !edata->eee_enabled; 2592 igb_set_eee_i350(hw); 2593 2594 /* reset link */ 2595 if (!netif_running(netdev)) 2596 igb_reset(adapter); 2597 } 2598 2599 return 0; 2600} 2601 2602static int igb_ethtool_begin(struct net_device *netdev) 2603{ 2604 struct igb_adapter *adapter = netdev_priv(netdev); 2605 pm_runtime_get_sync(&adapter->pdev->dev); 2606 return 0; 2607} 2608 2609static void igb_ethtool_complete(struct net_device *netdev) 2610{ 2611 struct igb_adapter *adapter = netdev_priv(netdev); 2612 pm_runtime_put(&adapter->pdev->dev); 2613} 2614 2615static const struct ethtool_ops igb_ethtool_ops = { 2616 .get_settings = igb_get_settings, 2617 .set_settings = igb_set_settings, 2618 .get_drvinfo = igb_get_drvinfo, 2619 .get_regs_len = igb_get_regs_len, 2620 .get_regs = igb_get_regs, 2621 .get_wol = igb_get_wol, 2622 .set_wol = igb_set_wol, 2623 .get_msglevel = igb_get_msglevel, 2624 .set_msglevel = igb_set_msglevel, 2625 .nway_reset = igb_nway_reset, 2626 .get_link = igb_get_link, 2627 .get_eeprom_len = igb_get_eeprom_len, 2628 .get_eeprom = igb_get_eeprom, 2629 .set_eeprom = igb_set_eeprom, 2630 .get_ringparam = igb_get_ringparam, 2631 .set_ringparam = igb_set_ringparam, 2632 .get_pauseparam = igb_get_pauseparam, 2633 .set_pauseparam = igb_set_pauseparam, 2634 .self_test = igb_diag_test, 2635 .get_strings = igb_get_strings, 2636 .set_phys_id = igb_set_phys_id, 2637 .get_sset_count = igb_get_sset_count, 2638 .get_ethtool_stats = igb_get_ethtool_stats, 2639 .get_coalesce = igb_get_coalesce, 2640 .set_coalesce = igb_set_coalesce, 2641 .get_ts_info = igb_get_ts_info, 2642 .get_rxnfc = igb_get_rxnfc, 2643 .set_rxnfc = igb_set_rxnfc, 2644 .get_eee = igb_get_eee, 2645 .set_eee = igb_set_eee, 2646 .begin = igb_ethtool_begin, 2647 .complete = igb_ethtool_complete, 2648}; 2649 2650void igb_set_ethtool_ops(struct net_device *netdev) 2651{ 2652 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops); 2653} 2654