igb_ethtool.c revision 8376dad0c877bc691b2feadd3390a162aa3c3bd9
1/*******************************************************************************
2
3  Intel(R) Gigabit Ethernet Linux driver
4  Copyright(c) 2007-2012 Intel Corporation.
5
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  more details.
14
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19  The full GNU General Public License is included in this distribution in
20  the file called "COPYING".
21
22  Contact Information:
23  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28/* ethtool support for igb */
29
30#include <linux/vmalloc.h>
31#include <linux/netdevice.h>
32#include <linux/pci.h>
33#include <linux/delay.h>
34#include <linux/interrupt.h>
35#include <linux/if_ether.h>
36#include <linux/ethtool.h>
37#include <linux/sched.h>
38#include <linux/slab.h>
39#include <linux/pm_runtime.h>
40
41#include "igb.h"
42
43struct igb_stats {
44	char stat_string[ETH_GSTRING_LEN];
45	int sizeof_stat;
46	int stat_offset;
47};
48
49#define IGB_STAT(_name, _stat) { \
50	.stat_string = _name, \
51	.sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \
52	.stat_offset = offsetof(struct igb_adapter, _stat) \
53}
54static const struct igb_stats igb_gstrings_stats[] = {
55	IGB_STAT("rx_packets", stats.gprc),
56	IGB_STAT("tx_packets", stats.gptc),
57	IGB_STAT("rx_bytes", stats.gorc),
58	IGB_STAT("tx_bytes", stats.gotc),
59	IGB_STAT("rx_broadcast", stats.bprc),
60	IGB_STAT("tx_broadcast", stats.bptc),
61	IGB_STAT("rx_multicast", stats.mprc),
62	IGB_STAT("tx_multicast", stats.mptc),
63	IGB_STAT("multicast", stats.mprc),
64	IGB_STAT("collisions", stats.colc),
65	IGB_STAT("rx_crc_errors", stats.crcerrs),
66	IGB_STAT("rx_no_buffer_count", stats.rnbc),
67	IGB_STAT("rx_missed_errors", stats.mpc),
68	IGB_STAT("tx_aborted_errors", stats.ecol),
69	IGB_STAT("tx_carrier_errors", stats.tncrs),
70	IGB_STAT("tx_window_errors", stats.latecol),
71	IGB_STAT("tx_abort_late_coll", stats.latecol),
72	IGB_STAT("tx_deferred_ok", stats.dc),
73	IGB_STAT("tx_single_coll_ok", stats.scc),
74	IGB_STAT("tx_multi_coll_ok", stats.mcc),
75	IGB_STAT("tx_timeout_count", tx_timeout_count),
76	IGB_STAT("rx_long_length_errors", stats.roc),
77	IGB_STAT("rx_short_length_errors", stats.ruc),
78	IGB_STAT("rx_align_errors", stats.algnerrc),
79	IGB_STAT("tx_tcp_seg_good", stats.tsctc),
80	IGB_STAT("tx_tcp_seg_failed", stats.tsctfc),
81	IGB_STAT("rx_flow_control_xon", stats.xonrxc),
82	IGB_STAT("rx_flow_control_xoff", stats.xoffrxc),
83	IGB_STAT("tx_flow_control_xon", stats.xontxc),
84	IGB_STAT("tx_flow_control_xoff", stats.xofftxc),
85	IGB_STAT("rx_long_byte_count", stats.gorc),
86	IGB_STAT("tx_dma_out_of_sync", stats.doosync),
87	IGB_STAT("tx_smbus", stats.mgptc),
88	IGB_STAT("rx_smbus", stats.mgprc),
89	IGB_STAT("dropped_smbus", stats.mgpdc),
90	IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc),
91	IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc),
92	IGB_STAT("os2bmc_tx_by_host", stats.o2bspc),
93	IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc),
94};
95
96#define IGB_NETDEV_STAT(_net_stat) { \
97	.stat_string = __stringify(_net_stat), \
98	.sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \
99	.stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \
100}
101static const struct igb_stats igb_gstrings_net_stats[] = {
102	IGB_NETDEV_STAT(rx_errors),
103	IGB_NETDEV_STAT(tx_errors),
104	IGB_NETDEV_STAT(tx_dropped),
105	IGB_NETDEV_STAT(rx_length_errors),
106	IGB_NETDEV_STAT(rx_over_errors),
107	IGB_NETDEV_STAT(rx_frame_errors),
108	IGB_NETDEV_STAT(rx_fifo_errors),
109	IGB_NETDEV_STAT(tx_fifo_errors),
110	IGB_NETDEV_STAT(tx_heartbeat_errors)
111};
112
113#define IGB_GLOBAL_STATS_LEN	\
114	(sizeof(igb_gstrings_stats) / sizeof(struct igb_stats))
115#define IGB_NETDEV_STATS_LEN	\
116	(sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats))
117#define IGB_RX_QUEUE_STATS_LEN \
118	(sizeof(struct igb_rx_queue_stats) / sizeof(u64))
119
120#define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */
121
122#define IGB_QUEUE_STATS_LEN \
123	((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \
124	  IGB_RX_QUEUE_STATS_LEN) + \
125	 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \
126	  IGB_TX_QUEUE_STATS_LEN))
127#define IGB_STATS_LEN \
128	(IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN)
129
130static const char igb_gstrings_test[][ETH_GSTRING_LEN] = {
131	"Register test  (offline)", "Eeprom test    (offline)",
132	"Interrupt test (offline)", "Loopback test  (offline)",
133	"Link test   (on/offline)"
134};
135#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN)
136
137static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
138{
139	struct igb_adapter *adapter = netdev_priv(netdev);
140	struct e1000_hw *hw = &adapter->hw;
141	u32 status;
142
143	if (hw->phy.media_type == e1000_media_type_copper) {
144
145		ecmd->supported = (SUPPORTED_10baseT_Half |
146				   SUPPORTED_10baseT_Full |
147				   SUPPORTED_100baseT_Half |
148				   SUPPORTED_100baseT_Full |
149				   SUPPORTED_1000baseT_Full|
150				   SUPPORTED_Autoneg |
151				   SUPPORTED_TP);
152		ecmd->advertising = (ADVERTISED_TP |
153				     ADVERTISED_Pause);
154
155		if (hw->mac.autoneg == 1) {
156			ecmd->advertising |= ADVERTISED_Autoneg;
157			/* the e1000 autoneg seems to match ethtool nicely */
158			ecmd->advertising |= hw->phy.autoneg_advertised;
159		}
160
161		ecmd->port = PORT_TP;
162		ecmd->phy_address = hw->phy.addr;
163	} else {
164		ecmd->supported   = (SUPPORTED_1000baseT_Full |
165				     SUPPORTED_FIBRE |
166				     SUPPORTED_Autoneg);
167
168		ecmd->advertising = (ADVERTISED_1000baseT_Full |
169				     ADVERTISED_FIBRE |
170				     ADVERTISED_Autoneg |
171				     ADVERTISED_Pause);
172
173		ecmd->port = PORT_FIBRE;
174	}
175
176	ecmd->transceiver = XCVR_INTERNAL;
177
178	status = rd32(E1000_STATUS);
179
180	if (status & E1000_STATUS_LU) {
181
182		if ((status & E1000_STATUS_SPEED_1000) ||
183		    hw->phy.media_type != e1000_media_type_copper)
184			ethtool_cmd_speed_set(ecmd, SPEED_1000);
185		else if (status & E1000_STATUS_SPEED_100)
186			ethtool_cmd_speed_set(ecmd, SPEED_100);
187		else
188			ethtool_cmd_speed_set(ecmd, SPEED_10);
189
190		if ((status & E1000_STATUS_FD) ||
191		    hw->phy.media_type != e1000_media_type_copper)
192			ecmd->duplex = DUPLEX_FULL;
193		else
194			ecmd->duplex = DUPLEX_HALF;
195	} else {
196		ethtool_cmd_speed_set(ecmd, -1);
197		ecmd->duplex = -1;
198	}
199
200	ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
201
202	/* MDI-X => 2; MDI =>1; Invalid =>0 */
203	if (hw->phy.media_type == e1000_media_type_copper)
204		ecmd->eth_tp_mdix = hw->phy.is_mdix ? ETH_TP_MDI_X :
205						      ETH_TP_MDI;
206	else
207		ecmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
208
209	if (hw->phy.mdix == AUTO_ALL_MODES)
210		ecmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
211	else
212		ecmd->eth_tp_mdix_ctrl = hw->phy.mdix;
213
214	return 0;
215}
216
217static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd)
218{
219	struct igb_adapter *adapter = netdev_priv(netdev);
220	struct e1000_hw *hw = &adapter->hw;
221
222	/* When SoL/IDER sessions are active, autoneg/speed/duplex
223	 * cannot be changed */
224	if (igb_check_reset_block(hw)) {
225		dev_err(&adapter->pdev->dev, "Cannot change link "
226			"characteristics when SoL/IDER is active.\n");
227		return -EINVAL;
228	}
229
230	/*
231	 * MDI setting is only allowed when autoneg enabled because
232	 * some hardware doesn't allow MDI setting when speed or
233	 * duplex is forced.
234	 */
235	if (ecmd->eth_tp_mdix_ctrl) {
236		if (hw->phy.media_type != e1000_media_type_copper)
237			return -EOPNOTSUPP;
238
239		if ((ecmd->eth_tp_mdix_ctrl != ETH_TP_MDI_AUTO) &&
240		    (ecmd->autoneg != AUTONEG_ENABLE)) {
241			dev_err(&adapter->pdev->dev, "forcing MDI/MDI-X state is not supported when link speed and/or duplex are forced\n");
242			return -EINVAL;
243		}
244	}
245
246	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
247		msleep(1);
248
249	if (ecmd->autoneg == AUTONEG_ENABLE) {
250		hw->mac.autoneg = 1;
251		hw->phy.autoneg_advertised = ecmd->advertising |
252					     ADVERTISED_TP |
253					     ADVERTISED_Autoneg;
254		ecmd->advertising = hw->phy.autoneg_advertised;
255		if (adapter->fc_autoneg)
256			hw->fc.requested_mode = e1000_fc_default;
257	} else {
258		u32 speed = ethtool_cmd_speed(ecmd);
259		/* calling this overrides forced MDI setting */
260		if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) {
261			clear_bit(__IGB_RESETTING, &adapter->state);
262			return -EINVAL;
263		}
264	}
265
266	/* MDI-X => 2; MDI => 1; Auto => 3 */
267	if (ecmd->eth_tp_mdix_ctrl) {
268		/*
269		 * fix up the value for auto (3 => 0) as zero is mapped
270		 * internally to auto
271		 */
272		if (ecmd->eth_tp_mdix_ctrl == ETH_TP_MDI_AUTO)
273			hw->phy.mdix = AUTO_ALL_MODES;
274		else
275			hw->phy.mdix = ecmd->eth_tp_mdix_ctrl;
276	}
277
278	/* reset the link */
279	if (netif_running(adapter->netdev)) {
280		igb_down(adapter);
281		igb_up(adapter);
282	} else
283		igb_reset(adapter);
284
285	clear_bit(__IGB_RESETTING, &adapter->state);
286	return 0;
287}
288
289static u32 igb_get_link(struct net_device *netdev)
290{
291	struct igb_adapter *adapter = netdev_priv(netdev);
292	struct e1000_mac_info *mac = &adapter->hw.mac;
293
294	/*
295	 * If the link is not reported up to netdev, interrupts are disabled,
296	 * and so the physical link state may have changed since we last
297	 * looked. Set get_link_status to make sure that the true link
298	 * state is interrogated, rather than pulling a cached and possibly
299	 * stale link state from the driver.
300	 */
301	if (!netif_carrier_ok(netdev))
302		mac->get_link_status = 1;
303
304	return igb_has_link(adapter);
305}
306
307static void igb_get_pauseparam(struct net_device *netdev,
308			       struct ethtool_pauseparam *pause)
309{
310	struct igb_adapter *adapter = netdev_priv(netdev);
311	struct e1000_hw *hw = &adapter->hw;
312
313	pause->autoneg =
314		(adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
315
316	if (hw->fc.current_mode == e1000_fc_rx_pause)
317		pause->rx_pause = 1;
318	else if (hw->fc.current_mode == e1000_fc_tx_pause)
319		pause->tx_pause = 1;
320	else if (hw->fc.current_mode == e1000_fc_full) {
321		pause->rx_pause = 1;
322		pause->tx_pause = 1;
323	}
324}
325
326static int igb_set_pauseparam(struct net_device *netdev,
327			      struct ethtool_pauseparam *pause)
328{
329	struct igb_adapter *adapter = netdev_priv(netdev);
330	struct e1000_hw *hw = &adapter->hw;
331	int retval = 0;
332
333	adapter->fc_autoneg = pause->autoneg;
334
335	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
336		msleep(1);
337
338	if (adapter->fc_autoneg == AUTONEG_ENABLE) {
339		hw->fc.requested_mode = e1000_fc_default;
340		if (netif_running(adapter->netdev)) {
341			igb_down(adapter);
342			igb_up(adapter);
343		} else {
344			igb_reset(adapter);
345		}
346	} else {
347		if (pause->rx_pause && pause->tx_pause)
348			hw->fc.requested_mode = e1000_fc_full;
349		else if (pause->rx_pause && !pause->tx_pause)
350			hw->fc.requested_mode = e1000_fc_rx_pause;
351		else if (!pause->rx_pause && pause->tx_pause)
352			hw->fc.requested_mode = e1000_fc_tx_pause;
353		else if (!pause->rx_pause && !pause->tx_pause)
354			hw->fc.requested_mode = e1000_fc_none;
355
356		hw->fc.current_mode = hw->fc.requested_mode;
357
358		retval = ((hw->phy.media_type == e1000_media_type_copper) ?
359			  igb_force_mac_fc(hw) : igb_setup_link(hw));
360	}
361
362	clear_bit(__IGB_RESETTING, &adapter->state);
363	return retval;
364}
365
366static u32 igb_get_msglevel(struct net_device *netdev)
367{
368	struct igb_adapter *adapter = netdev_priv(netdev);
369	return adapter->msg_enable;
370}
371
372static void igb_set_msglevel(struct net_device *netdev, u32 data)
373{
374	struct igb_adapter *adapter = netdev_priv(netdev);
375	adapter->msg_enable = data;
376}
377
378static int igb_get_regs_len(struct net_device *netdev)
379{
380#define IGB_REGS_LEN 739
381	return IGB_REGS_LEN * sizeof(u32);
382}
383
384static void igb_get_regs(struct net_device *netdev,
385			 struct ethtool_regs *regs, void *p)
386{
387	struct igb_adapter *adapter = netdev_priv(netdev);
388	struct e1000_hw *hw = &adapter->hw;
389	u32 *regs_buff = p;
390	u8 i;
391
392	memset(p, 0, IGB_REGS_LEN * sizeof(u32));
393
394	regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id;
395
396	/* General Registers */
397	regs_buff[0] = rd32(E1000_CTRL);
398	regs_buff[1] = rd32(E1000_STATUS);
399	regs_buff[2] = rd32(E1000_CTRL_EXT);
400	regs_buff[3] = rd32(E1000_MDIC);
401	regs_buff[4] = rd32(E1000_SCTL);
402	regs_buff[5] = rd32(E1000_CONNSW);
403	regs_buff[6] = rd32(E1000_VET);
404	regs_buff[7] = rd32(E1000_LEDCTL);
405	regs_buff[8] = rd32(E1000_PBA);
406	regs_buff[9] = rd32(E1000_PBS);
407	regs_buff[10] = rd32(E1000_FRTIMER);
408	regs_buff[11] = rd32(E1000_TCPTIMER);
409
410	/* NVM Register */
411	regs_buff[12] = rd32(E1000_EECD);
412
413	/* Interrupt */
414	/* Reading EICS for EICR because they read the
415	 * same but EICS does not clear on read */
416	regs_buff[13] = rd32(E1000_EICS);
417	regs_buff[14] = rd32(E1000_EICS);
418	regs_buff[15] = rd32(E1000_EIMS);
419	regs_buff[16] = rd32(E1000_EIMC);
420	regs_buff[17] = rd32(E1000_EIAC);
421	regs_buff[18] = rd32(E1000_EIAM);
422	/* Reading ICS for ICR because they read the
423	 * same but ICS does not clear on read */
424	regs_buff[19] = rd32(E1000_ICS);
425	regs_buff[20] = rd32(E1000_ICS);
426	regs_buff[21] = rd32(E1000_IMS);
427	regs_buff[22] = rd32(E1000_IMC);
428	regs_buff[23] = rd32(E1000_IAC);
429	regs_buff[24] = rd32(E1000_IAM);
430	regs_buff[25] = rd32(E1000_IMIRVP);
431
432	/* Flow Control */
433	regs_buff[26] = rd32(E1000_FCAL);
434	regs_buff[27] = rd32(E1000_FCAH);
435	regs_buff[28] = rd32(E1000_FCTTV);
436	regs_buff[29] = rd32(E1000_FCRTL);
437	regs_buff[30] = rd32(E1000_FCRTH);
438	regs_buff[31] = rd32(E1000_FCRTV);
439
440	/* Receive */
441	regs_buff[32] = rd32(E1000_RCTL);
442	regs_buff[33] = rd32(E1000_RXCSUM);
443	regs_buff[34] = rd32(E1000_RLPML);
444	regs_buff[35] = rd32(E1000_RFCTL);
445	regs_buff[36] = rd32(E1000_MRQC);
446	regs_buff[37] = rd32(E1000_VT_CTL);
447
448	/* Transmit */
449	regs_buff[38] = rd32(E1000_TCTL);
450	regs_buff[39] = rd32(E1000_TCTL_EXT);
451	regs_buff[40] = rd32(E1000_TIPG);
452	regs_buff[41] = rd32(E1000_DTXCTL);
453
454	/* Wake Up */
455	regs_buff[42] = rd32(E1000_WUC);
456	regs_buff[43] = rd32(E1000_WUFC);
457	regs_buff[44] = rd32(E1000_WUS);
458	regs_buff[45] = rd32(E1000_IPAV);
459	regs_buff[46] = rd32(E1000_WUPL);
460
461	/* MAC */
462	regs_buff[47] = rd32(E1000_PCS_CFG0);
463	regs_buff[48] = rd32(E1000_PCS_LCTL);
464	regs_buff[49] = rd32(E1000_PCS_LSTAT);
465	regs_buff[50] = rd32(E1000_PCS_ANADV);
466	regs_buff[51] = rd32(E1000_PCS_LPAB);
467	regs_buff[52] = rd32(E1000_PCS_NPTX);
468	regs_buff[53] = rd32(E1000_PCS_LPABNP);
469
470	/* Statistics */
471	regs_buff[54] = adapter->stats.crcerrs;
472	regs_buff[55] = adapter->stats.algnerrc;
473	regs_buff[56] = adapter->stats.symerrs;
474	regs_buff[57] = adapter->stats.rxerrc;
475	regs_buff[58] = adapter->stats.mpc;
476	regs_buff[59] = adapter->stats.scc;
477	regs_buff[60] = adapter->stats.ecol;
478	regs_buff[61] = adapter->stats.mcc;
479	regs_buff[62] = adapter->stats.latecol;
480	regs_buff[63] = adapter->stats.colc;
481	regs_buff[64] = adapter->stats.dc;
482	regs_buff[65] = adapter->stats.tncrs;
483	regs_buff[66] = adapter->stats.sec;
484	regs_buff[67] = adapter->stats.htdpmc;
485	regs_buff[68] = adapter->stats.rlec;
486	regs_buff[69] = adapter->stats.xonrxc;
487	regs_buff[70] = adapter->stats.xontxc;
488	regs_buff[71] = adapter->stats.xoffrxc;
489	regs_buff[72] = adapter->stats.xofftxc;
490	regs_buff[73] = adapter->stats.fcruc;
491	regs_buff[74] = adapter->stats.prc64;
492	regs_buff[75] = adapter->stats.prc127;
493	regs_buff[76] = adapter->stats.prc255;
494	regs_buff[77] = adapter->stats.prc511;
495	regs_buff[78] = adapter->stats.prc1023;
496	regs_buff[79] = adapter->stats.prc1522;
497	regs_buff[80] = adapter->stats.gprc;
498	regs_buff[81] = adapter->stats.bprc;
499	regs_buff[82] = adapter->stats.mprc;
500	regs_buff[83] = adapter->stats.gptc;
501	regs_buff[84] = adapter->stats.gorc;
502	regs_buff[86] = adapter->stats.gotc;
503	regs_buff[88] = adapter->stats.rnbc;
504	regs_buff[89] = adapter->stats.ruc;
505	regs_buff[90] = adapter->stats.rfc;
506	regs_buff[91] = adapter->stats.roc;
507	regs_buff[92] = adapter->stats.rjc;
508	regs_buff[93] = adapter->stats.mgprc;
509	regs_buff[94] = adapter->stats.mgpdc;
510	regs_buff[95] = adapter->stats.mgptc;
511	regs_buff[96] = adapter->stats.tor;
512	regs_buff[98] = adapter->stats.tot;
513	regs_buff[100] = adapter->stats.tpr;
514	regs_buff[101] = adapter->stats.tpt;
515	regs_buff[102] = adapter->stats.ptc64;
516	regs_buff[103] = adapter->stats.ptc127;
517	regs_buff[104] = adapter->stats.ptc255;
518	regs_buff[105] = adapter->stats.ptc511;
519	regs_buff[106] = adapter->stats.ptc1023;
520	regs_buff[107] = adapter->stats.ptc1522;
521	regs_buff[108] = adapter->stats.mptc;
522	regs_buff[109] = adapter->stats.bptc;
523	regs_buff[110] = adapter->stats.tsctc;
524	regs_buff[111] = adapter->stats.iac;
525	regs_buff[112] = adapter->stats.rpthc;
526	regs_buff[113] = adapter->stats.hgptc;
527	regs_buff[114] = adapter->stats.hgorc;
528	regs_buff[116] = adapter->stats.hgotc;
529	regs_buff[118] = adapter->stats.lenerrs;
530	regs_buff[119] = adapter->stats.scvpc;
531	regs_buff[120] = adapter->stats.hrmpc;
532
533	for (i = 0; i < 4; i++)
534		regs_buff[121 + i] = rd32(E1000_SRRCTL(i));
535	for (i = 0; i < 4; i++)
536		regs_buff[125 + i] = rd32(E1000_PSRTYPE(i));
537	for (i = 0; i < 4; i++)
538		regs_buff[129 + i] = rd32(E1000_RDBAL(i));
539	for (i = 0; i < 4; i++)
540		regs_buff[133 + i] = rd32(E1000_RDBAH(i));
541	for (i = 0; i < 4; i++)
542		regs_buff[137 + i] = rd32(E1000_RDLEN(i));
543	for (i = 0; i < 4; i++)
544		regs_buff[141 + i] = rd32(E1000_RDH(i));
545	for (i = 0; i < 4; i++)
546		regs_buff[145 + i] = rd32(E1000_RDT(i));
547	for (i = 0; i < 4; i++)
548		regs_buff[149 + i] = rd32(E1000_RXDCTL(i));
549
550	for (i = 0; i < 10; i++)
551		regs_buff[153 + i] = rd32(E1000_EITR(i));
552	for (i = 0; i < 8; i++)
553		regs_buff[163 + i] = rd32(E1000_IMIR(i));
554	for (i = 0; i < 8; i++)
555		regs_buff[171 + i] = rd32(E1000_IMIREXT(i));
556	for (i = 0; i < 16; i++)
557		regs_buff[179 + i] = rd32(E1000_RAL(i));
558	for (i = 0; i < 16; i++)
559		regs_buff[195 + i] = rd32(E1000_RAH(i));
560
561	for (i = 0; i < 4; i++)
562		regs_buff[211 + i] = rd32(E1000_TDBAL(i));
563	for (i = 0; i < 4; i++)
564		regs_buff[215 + i] = rd32(E1000_TDBAH(i));
565	for (i = 0; i < 4; i++)
566		regs_buff[219 + i] = rd32(E1000_TDLEN(i));
567	for (i = 0; i < 4; i++)
568		regs_buff[223 + i] = rd32(E1000_TDH(i));
569	for (i = 0; i < 4; i++)
570		regs_buff[227 + i] = rd32(E1000_TDT(i));
571	for (i = 0; i < 4; i++)
572		regs_buff[231 + i] = rd32(E1000_TXDCTL(i));
573	for (i = 0; i < 4; i++)
574		regs_buff[235 + i] = rd32(E1000_TDWBAL(i));
575	for (i = 0; i < 4; i++)
576		regs_buff[239 + i] = rd32(E1000_TDWBAH(i));
577	for (i = 0; i < 4; i++)
578		regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i));
579
580	for (i = 0; i < 4; i++)
581		regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i));
582	for (i = 0; i < 4; i++)
583		regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i));
584	for (i = 0; i < 32; i++)
585		regs_buff[255 + i] = rd32(E1000_WUPM_REG(i));
586	for (i = 0; i < 128; i++)
587		regs_buff[287 + i] = rd32(E1000_FFMT_REG(i));
588	for (i = 0; i < 128; i++)
589		regs_buff[415 + i] = rd32(E1000_FFVT_REG(i));
590	for (i = 0; i < 4; i++)
591		regs_buff[543 + i] = rd32(E1000_FFLT_REG(i));
592
593	regs_buff[547] = rd32(E1000_TDFH);
594	regs_buff[548] = rd32(E1000_TDFT);
595	regs_buff[549] = rd32(E1000_TDFHS);
596	regs_buff[550] = rd32(E1000_TDFPC);
597
598	if (hw->mac.type > e1000_82580) {
599		regs_buff[551] = adapter->stats.o2bgptc;
600		regs_buff[552] = adapter->stats.b2ospc;
601		regs_buff[553] = adapter->stats.o2bspc;
602		regs_buff[554] = adapter->stats.b2ogprc;
603	}
604
605	if (hw->mac.type != e1000_82576)
606		return;
607	for (i = 0; i < 12; i++)
608		regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4));
609	for (i = 0; i < 4; i++)
610		regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4));
611	for (i = 0; i < 12; i++)
612		regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4));
613	for (i = 0; i < 12; i++)
614		regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4));
615	for (i = 0; i < 12; i++)
616		regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4));
617	for (i = 0; i < 12; i++)
618		regs_buff[607 + i] = rd32(E1000_RDH(i + 4));
619	for (i = 0; i < 12; i++)
620		regs_buff[619 + i] = rd32(E1000_RDT(i + 4));
621	for (i = 0; i < 12; i++)
622		regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4));
623
624	for (i = 0; i < 12; i++)
625		regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4));
626	for (i = 0; i < 12; i++)
627		regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4));
628	for (i = 0; i < 12; i++)
629		regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4));
630	for (i = 0; i < 12; i++)
631		regs_buff[679 + i] = rd32(E1000_TDH(i + 4));
632	for (i = 0; i < 12; i++)
633		regs_buff[691 + i] = rd32(E1000_TDT(i + 4));
634	for (i = 0; i < 12; i++)
635		regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4));
636	for (i = 0; i < 12; i++)
637		regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4));
638	for (i = 0; i < 12; i++)
639		regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4));
640}
641
642static int igb_get_eeprom_len(struct net_device *netdev)
643{
644	struct igb_adapter *adapter = netdev_priv(netdev);
645	return adapter->hw.nvm.word_size * 2;
646}
647
648static int igb_get_eeprom(struct net_device *netdev,
649			  struct ethtool_eeprom *eeprom, u8 *bytes)
650{
651	struct igb_adapter *adapter = netdev_priv(netdev);
652	struct e1000_hw *hw = &adapter->hw;
653	u16 *eeprom_buff;
654	int first_word, last_word;
655	int ret_val = 0;
656	u16 i;
657
658	if (eeprom->len == 0)
659		return -EINVAL;
660
661	eeprom->magic = hw->vendor_id | (hw->device_id << 16);
662
663	first_word = eeprom->offset >> 1;
664	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
665
666	eeprom_buff = kmalloc(sizeof(u16) *
667			(last_word - first_word + 1), GFP_KERNEL);
668	if (!eeprom_buff)
669		return -ENOMEM;
670
671	if (hw->nvm.type == e1000_nvm_eeprom_spi)
672		ret_val = hw->nvm.ops.read(hw, first_word,
673					    last_word - first_word + 1,
674					    eeprom_buff);
675	else {
676		for (i = 0; i < last_word - first_word + 1; i++) {
677			ret_val = hw->nvm.ops.read(hw, first_word + i, 1,
678						    &eeprom_buff[i]);
679			if (ret_val)
680				break;
681		}
682	}
683
684	/* Device's eeprom is always little-endian, word addressable */
685	for (i = 0; i < last_word - first_word + 1; i++)
686		le16_to_cpus(&eeprom_buff[i]);
687
688	memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1),
689			eeprom->len);
690	kfree(eeprom_buff);
691
692	return ret_val;
693}
694
695static int igb_set_eeprom(struct net_device *netdev,
696			  struct ethtool_eeprom *eeprom, u8 *bytes)
697{
698	struct igb_adapter *adapter = netdev_priv(netdev);
699	struct e1000_hw *hw = &adapter->hw;
700	u16 *eeprom_buff;
701	void *ptr;
702	int max_len, first_word, last_word, ret_val = 0;
703	u16 i;
704
705	if (eeprom->len == 0)
706		return -EOPNOTSUPP;
707
708	if (hw->mac.type == e1000_i211)
709		return -EOPNOTSUPP;
710
711	if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16)))
712		return -EFAULT;
713
714	max_len = hw->nvm.word_size * 2;
715
716	first_word = eeprom->offset >> 1;
717	last_word = (eeprom->offset + eeprom->len - 1) >> 1;
718	eeprom_buff = kmalloc(max_len, GFP_KERNEL);
719	if (!eeprom_buff)
720		return -ENOMEM;
721
722	ptr = (void *)eeprom_buff;
723
724	if (eeprom->offset & 1) {
725		/* need read/modify/write of first changed EEPROM word */
726		/* only the second byte of the word is being modified */
727		ret_val = hw->nvm.ops.read(hw, first_word, 1,
728					    &eeprom_buff[0]);
729		ptr++;
730	}
731	if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) {
732		/* need read/modify/write of last changed EEPROM word */
733		/* only the first byte of the word is being modified */
734		ret_val = hw->nvm.ops.read(hw, last_word, 1,
735				   &eeprom_buff[last_word - first_word]);
736	}
737
738	/* Device's eeprom is always little-endian, word addressable */
739	for (i = 0; i < last_word - first_word + 1; i++)
740		le16_to_cpus(&eeprom_buff[i]);
741
742	memcpy(ptr, bytes, eeprom->len);
743
744	for (i = 0; i < last_word - first_word + 1; i++)
745		eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]);
746
747	ret_val = hw->nvm.ops.write(hw, first_word,
748				     last_word - first_word + 1, eeprom_buff);
749
750	/* Update the checksum over the first part of the EEPROM if needed
751	 * and flush shadow RAM for 82573 controllers */
752	if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG)))
753		hw->nvm.ops.update(hw);
754
755	igb_set_fw_version(adapter);
756	kfree(eeprom_buff);
757	return ret_val;
758}
759
760static void igb_get_drvinfo(struct net_device *netdev,
761			    struct ethtool_drvinfo *drvinfo)
762{
763	struct igb_adapter *adapter = netdev_priv(netdev);
764
765	strlcpy(drvinfo->driver,  igb_driver_name, sizeof(drvinfo->driver));
766	strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version));
767
768	/*
769	 * EEPROM image version # is reported as firmware version # for
770	 * 82575 controllers
771	 */
772	strlcpy(drvinfo->fw_version, adapter->fw_version,
773		sizeof(drvinfo->fw_version));
774	strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
775		sizeof(drvinfo->bus_info));
776	drvinfo->n_stats = IGB_STATS_LEN;
777	drvinfo->testinfo_len = IGB_TEST_LEN;
778	drvinfo->regdump_len = igb_get_regs_len(netdev);
779	drvinfo->eedump_len = igb_get_eeprom_len(netdev);
780}
781
782static void igb_get_ringparam(struct net_device *netdev,
783			      struct ethtool_ringparam *ring)
784{
785	struct igb_adapter *adapter = netdev_priv(netdev);
786
787	ring->rx_max_pending = IGB_MAX_RXD;
788	ring->tx_max_pending = IGB_MAX_TXD;
789	ring->rx_pending = adapter->rx_ring_count;
790	ring->tx_pending = adapter->tx_ring_count;
791}
792
793static int igb_set_ringparam(struct net_device *netdev,
794			     struct ethtool_ringparam *ring)
795{
796	struct igb_adapter *adapter = netdev_priv(netdev);
797	struct igb_ring *temp_ring;
798	int i, err = 0;
799	u16 new_rx_count, new_tx_count;
800
801	if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
802		return -EINVAL;
803
804	new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD);
805	new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD);
806	new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE);
807
808	new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD);
809	new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD);
810	new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE);
811
812	if ((new_tx_count == adapter->tx_ring_count) &&
813	    (new_rx_count == adapter->rx_ring_count)) {
814		/* nothing to do */
815		return 0;
816	}
817
818	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
819		msleep(1);
820
821	if (!netif_running(adapter->netdev)) {
822		for (i = 0; i < adapter->num_tx_queues; i++)
823			adapter->tx_ring[i]->count = new_tx_count;
824		for (i = 0; i < adapter->num_rx_queues; i++)
825			adapter->rx_ring[i]->count = new_rx_count;
826		adapter->tx_ring_count = new_tx_count;
827		adapter->rx_ring_count = new_rx_count;
828		goto clear_reset;
829	}
830
831	if (adapter->num_tx_queues > adapter->num_rx_queues)
832		temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring));
833	else
834		temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring));
835
836	if (!temp_ring) {
837		err = -ENOMEM;
838		goto clear_reset;
839	}
840
841	igb_down(adapter);
842
843	/*
844	 * We can't just free everything and then setup again,
845	 * because the ISRs in MSI-X mode get passed pointers
846	 * to the tx and rx ring structs.
847	 */
848	if (new_tx_count != adapter->tx_ring_count) {
849		for (i = 0; i < adapter->num_tx_queues; i++) {
850			memcpy(&temp_ring[i], adapter->tx_ring[i],
851			       sizeof(struct igb_ring));
852
853			temp_ring[i].count = new_tx_count;
854			err = igb_setup_tx_resources(&temp_ring[i]);
855			if (err) {
856				while (i) {
857					i--;
858					igb_free_tx_resources(&temp_ring[i]);
859				}
860				goto err_setup;
861			}
862		}
863
864		for (i = 0; i < adapter->num_tx_queues; i++) {
865			igb_free_tx_resources(adapter->tx_ring[i]);
866
867			memcpy(adapter->tx_ring[i], &temp_ring[i],
868			       sizeof(struct igb_ring));
869		}
870
871		adapter->tx_ring_count = new_tx_count;
872	}
873
874	if (new_rx_count != adapter->rx_ring_count) {
875		for (i = 0; i < adapter->num_rx_queues; i++) {
876			memcpy(&temp_ring[i], adapter->rx_ring[i],
877			       sizeof(struct igb_ring));
878
879			temp_ring[i].count = new_rx_count;
880			err = igb_setup_rx_resources(&temp_ring[i]);
881			if (err) {
882				while (i) {
883					i--;
884					igb_free_rx_resources(&temp_ring[i]);
885				}
886				goto err_setup;
887			}
888
889		}
890
891		for (i = 0; i < adapter->num_rx_queues; i++) {
892			igb_free_rx_resources(adapter->rx_ring[i]);
893
894			memcpy(adapter->rx_ring[i], &temp_ring[i],
895			       sizeof(struct igb_ring));
896		}
897
898		adapter->rx_ring_count = new_rx_count;
899	}
900err_setup:
901	igb_up(adapter);
902	vfree(temp_ring);
903clear_reset:
904	clear_bit(__IGB_RESETTING, &adapter->state);
905	return err;
906}
907
908/* ethtool register test data */
909struct igb_reg_test {
910	u16 reg;
911	u16 reg_offset;
912	u16 array_len;
913	u16 test_type;
914	u32 mask;
915	u32 write;
916};
917
918/* In the hardware, registers are laid out either singly, in arrays
919 * spaced 0x100 bytes apart, or in contiguous tables.  We assume
920 * most tests take place on arrays or single registers (handled
921 * as a single-element array) and special-case the tables.
922 * Table tests are always pattern tests.
923 *
924 * We also make provision for some required setup steps by specifying
925 * registers to be written without any read-back testing.
926 */
927
928#define PATTERN_TEST	1
929#define SET_READ_TEST	2
930#define WRITE_NO_TEST	3
931#define TABLE32_TEST	4
932#define TABLE64_TEST_LO	5
933#define TABLE64_TEST_HI	6
934
935/* i210 reg test */
936static struct igb_reg_test reg_test_i210[] = {
937	{ E1000_FCAL,	   0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
938	{ E1000_FCAH,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
939	{ E1000_FCT,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
940	{ E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
941	{ E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
942	{ E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
943	/* RDH is read-only for i210, only test RDT. */
944	{ E1000_RDT(0),	   0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
945	{ E1000_FCRTH,	   0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
946	{ E1000_FCTTV,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
947	{ E1000_TIPG,	   0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
948	{ E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
949	{ E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
950	{ E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
951	{ E1000_TDT(0),	   0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
952	{ E1000_RCTL,	   0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
953	{ E1000_RCTL,	   0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
954	{ E1000_RCTL,	   0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
955	{ E1000_TCTL,	   0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
956	{ E1000_RA,	   0, 16, TABLE64_TEST_LO,
957						0xFFFFFFFF, 0xFFFFFFFF },
958	{ E1000_RA,	   0, 16, TABLE64_TEST_HI,
959						0x900FFFFF, 0xFFFFFFFF },
960	{ E1000_MTA,	   0, 128, TABLE32_TEST,
961						0xFFFFFFFF, 0xFFFFFFFF },
962	{ 0, 0, 0, 0, 0 }
963};
964
965/* i350 reg test */
966static struct igb_reg_test reg_test_i350[] = {
967	{ E1000_FCAL,	   0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
968	{ E1000_FCAH,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
969	{ E1000_FCT,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
970	{ E1000_VET,	   0x100, 1,  PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 },
971	{ E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
972	{ E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
973	{ E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
974	{ E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
975	{ E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
976	{ E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
977	/* RDH is read-only for i350, only test RDT. */
978	{ E1000_RDT(0),	   0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
979	{ E1000_RDT(4),	   0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
980	{ E1000_FCRTH,	   0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
981	{ E1000_FCTTV,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
982	{ E1000_TIPG,	   0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
983	{ E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
984	{ E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
985	{ E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
986	{ E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
987	{ E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
988	{ E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
989	{ E1000_TDT(0),	   0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
990	{ E1000_TDT(4),	   0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
991	{ E1000_RCTL,	   0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
992	{ E1000_RCTL, 	   0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
993	{ E1000_RCTL, 	   0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
994	{ E1000_TCTL,	   0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
995	{ E1000_RA,	   0, 16, TABLE64_TEST_LO,
996						0xFFFFFFFF, 0xFFFFFFFF },
997	{ E1000_RA,	   0, 16, TABLE64_TEST_HI,
998						0xC3FFFFFF, 0xFFFFFFFF },
999	{ E1000_RA2,	   0, 16, TABLE64_TEST_LO,
1000						0xFFFFFFFF, 0xFFFFFFFF },
1001	{ E1000_RA2,	   0, 16, TABLE64_TEST_HI,
1002						0xC3FFFFFF, 0xFFFFFFFF },
1003	{ E1000_MTA,	   0, 128, TABLE32_TEST,
1004						0xFFFFFFFF, 0xFFFFFFFF },
1005	{ 0, 0, 0, 0 }
1006};
1007
1008/* 82580 reg test */
1009static struct igb_reg_test reg_test_82580[] = {
1010	{ E1000_FCAL,	   0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1011	{ E1000_FCAH,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1012	{ E1000_FCT,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1013	{ E1000_VET,	   0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1014	{ E1000_RDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1015	{ E1000_RDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1016	{ E1000_RDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1017	{ E1000_RDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1018	{ E1000_RDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1019	{ E1000_RDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1020	/* RDH is read-only for 82580, only test RDT. */
1021	{ E1000_RDT(0),	   0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1022	{ E1000_RDT(4),	   0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1023	{ E1000_FCRTH,	   0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1024	{ E1000_FCTTV,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1025	{ E1000_TIPG,	   0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1026	{ E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1027	{ E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1028	{ E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1029	{ E1000_TDBAL(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1030	{ E1000_TDBAH(4),  0x40,  4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1031	{ E1000_TDLEN(4),  0x40,  4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1032	{ E1000_TDT(0),	   0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1033	{ E1000_TDT(4),	   0x40,  4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1034	{ E1000_RCTL,	   0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1035	{ E1000_RCTL, 	   0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1036	{ E1000_RCTL, 	   0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1037	{ E1000_TCTL,	   0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1038	{ E1000_RA,	   0, 16, TABLE64_TEST_LO,
1039						0xFFFFFFFF, 0xFFFFFFFF },
1040	{ E1000_RA,	   0, 16, TABLE64_TEST_HI,
1041						0x83FFFFFF, 0xFFFFFFFF },
1042	{ E1000_RA2,	   0, 8, TABLE64_TEST_LO,
1043						0xFFFFFFFF, 0xFFFFFFFF },
1044	{ E1000_RA2,	   0, 8, TABLE64_TEST_HI,
1045						0x83FFFFFF, 0xFFFFFFFF },
1046	{ E1000_MTA,	   0, 128, TABLE32_TEST,
1047						0xFFFFFFFF, 0xFFFFFFFF },
1048	{ 0, 0, 0, 0 }
1049};
1050
1051/* 82576 reg test */
1052static struct igb_reg_test reg_test_82576[] = {
1053	{ E1000_FCAL,	   0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1054	{ E1000_FCAH,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1055	{ E1000_FCT,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1056	{ E1000_VET,	   0x100, 1,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1057	{ E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1058	{ E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1059	{ E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1060	{ E1000_RDBAL(4),  0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1061	{ E1000_RDBAH(4),  0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1062	{ E1000_RDLEN(4),  0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1063	/* Enable all RX queues before testing. */
1064	{ E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1065	{ E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1066	/* RDH is read-only for 82576, only test RDT. */
1067	{ E1000_RDT(0),	   0x100, 4,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1068	{ E1000_RDT(4),	   0x40, 12,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1069	{ E1000_RXDCTL(0), 0x100, 4,  WRITE_NO_TEST, 0, 0 },
1070	{ E1000_RXDCTL(4), 0x40, 12,  WRITE_NO_TEST, 0, 0 },
1071	{ E1000_FCRTH,	   0x100, 1,  PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1072	{ E1000_FCTTV,	   0x100, 1,  PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1073	{ E1000_TIPG,	   0x100, 1,  PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1074	{ E1000_TDBAL(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1075	{ E1000_TDBAH(0),  0x100, 4,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1076	{ E1000_TDLEN(0),  0x100, 4,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1077	{ E1000_TDBAL(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1078	{ E1000_TDBAH(4),  0x40, 12,  PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1079	{ E1000_TDLEN(4),  0x40, 12,  PATTERN_TEST, 0x000FFFF0, 0x000FFFFF },
1080	{ E1000_RCTL,	   0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1081	{ E1000_RCTL, 	   0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB },
1082	{ E1000_RCTL, 	   0x100, 1,  SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF },
1083	{ E1000_TCTL,	   0x100, 1,  SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1084	{ E1000_RA,	   0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1085	{ E1000_RA,	   0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1086	{ E1000_RA2,	   0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1087	{ E1000_RA2,	   0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF },
1088	{ E1000_MTA,	   0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1089	{ 0, 0, 0, 0 }
1090};
1091
1092/* 82575 register test */
1093static struct igb_reg_test reg_test_82575[] = {
1094	{ E1000_FCAL,      0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1095	{ E1000_FCAH,      0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1096	{ E1000_FCT,       0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF },
1097	{ E1000_VET,       0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1098	{ E1000_RDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1099	{ E1000_RDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1100	{ E1000_RDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1101	/* Enable all four RX queues before testing. */
1102	{ E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE },
1103	/* RDH is read-only for 82575, only test RDT. */
1104	{ E1000_RDT(0),    0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1105	{ E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 },
1106	{ E1000_FCRTH,     0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 },
1107	{ E1000_FCTTV,     0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF },
1108	{ E1000_TIPG,      0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF },
1109	{ E1000_TDBAL(0),  0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF },
1110	{ E1000_TDBAH(0),  0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1111	{ E1000_TDLEN(0),  0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF },
1112	{ E1000_RCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1113	{ E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB },
1114	{ E1000_RCTL,      0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF },
1115	{ E1000_TCTL,      0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 },
1116	{ E1000_TXCW,      0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF },
1117	{ E1000_RA,        0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF },
1118	{ E1000_RA,        0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF },
1119	{ E1000_MTA,       0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF },
1120	{ 0, 0, 0, 0 }
1121};
1122
1123static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data,
1124			     int reg, u32 mask, u32 write)
1125{
1126	struct e1000_hw *hw = &adapter->hw;
1127	u32 pat, val;
1128	static const u32 _test[] =
1129		{0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
1130	for (pat = 0; pat < ARRAY_SIZE(_test); pat++) {
1131		wr32(reg, (_test[pat] & write));
1132		val = rd32(reg) & mask;
1133		if (val != (_test[pat] & write & mask)) {
1134			dev_err(&adapter->pdev->dev, "pattern test reg %04X "
1135				"failed: got 0x%08X expected 0x%08X\n",
1136				reg, val, (_test[pat] & write & mask));
1137			*data = reg;
1138			return 1;
1139		}
1140	}
1141
1142	return 0;
1143}
1144
1145static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data,
1146			      int reg, u32 mask, u32 write)
1147{
1148	struct e1000_hw *hw = &adapter->hw;
1149	u32 val;
1150	wr32(reg, write & mask);
1151	val = rd32(reg);
1152	if ((write & mask) != (val & mask)) {
1153		dev_err(&adapter->pdev->dev, "set/check reg %04X test failed:"
1154			" got 0x%08X expected 0x%08X\n", reg,
1155			(val & mask), (write & mask));
1156		*data = reg;
1157		return 1;
1158	}
1159
1160	return 0;
1161}
1162
1163#define REG_PATTERN_TEST(reg, mask, write) \
1164	do { \
1165		if (reg_pattern_test(adapter, data, reg, mask, write)) \
1166			return 1; \
1167	} while (0)
1168
1169#define REG_SET_AND_CHECK(reg, mask, write) \
1170	do { \
1171		if (reg_set_and_check(adapter, data, reg, mask, write)) \
1172			return 1; \
1173	} while (0)
1174
1175static int igb_reg_test(struct igb_adapter *adapter, u64 *data)
1176{
1177	struct e1000_hw *hw = &adapter->hw;
1178	struct igb_reg_test *test;
1179	u32 value, before, after;
1180	u32 i, toggle;
1181
1182	switch (adapter->hw.mac.type) {
1183	case e1000_i350:
1184		test = reg_test_i350;
1185		toggle = 0x7FEFF3FF;
1186		break;
1187	case e1000_i210:
1188	case e1000_i211:
1189		test = reg_test_i210;
1190		toggle = 0x7FEFF3FF;
1191		break;
1192	case e1000_82580:
1193		test = reg_test_82580;
1194		toggle = 0x7FEFF3FF;
1195		break;
1196	case e1000_82576:
1197		test = reg_test_82576;
1198		toggle = 0x7FFFF3FF;
1199		break;
1200	default:
1201		test = reg_test_82575;
1202		toggle = 0x7FFFF3FF;
1203		break;
1204	}
1205
1206	/* Because the status register is such a special case,
1207	 * we handle it separately from the rest of the register
1208	 * tests.  Some bits are read-only, some toggle, and some
1209	 * are writable on newer MACs.
1210	 */
1211	before = rd32(E1000_STATUS);
1212	value = (rd32(E1000_STATUS) & toggle);
1213	wr32(E1000_STATUS, toggle);
1214	after = rd32(E1000_STATUS) & toggle;
1215	if (value != after) {
1216		dev_err(&adapter->pdev->dev, "failed STATUS register test "
1217			"got: 0x%08X expected: 0x%08X\n", after, value);
1218		*data = 1;
1219		return 1;
1220	}
1221	/* restore previous status */
1222	wr32(E1000_STATUS, before);
1223
1224	/* Perform the remainder of the register test, looping through
1225	 * the test table until we either fail or reach the null entry.
1226	 */
1227	while (test->reg) {
1228		for (i = 0; i < test->array_len; i++) {
1229			switch (test->test_type) {
1230			case PATTERN_TEST:
1231				REG_PATTERN_TEST(test->reg +
1232						(i * test->reg_offset),
1233						test->mask,
1234						test->write);
1235				break;
1236			case SET_READ_TEST:
1237				REG_SET_AND_CHECK(test->reg +
1238						(i * test->reg_offset),
1239						test->mask,
1240						test->write);
1241				break;
1242			case WRITE_NO_TEST:
1243				writel(test->write,
1244				    (adapter->hw.hw_addr + test->reg)
1245					+ (i * test->reg_offset));
1246				break;
1247			case TABLE32_TEST:
1248				REG_PATTERN_TEST(test->reg + (i * 4),
1249						test->mask,
1250						test->write);
1251				break;
1252			case TABLE64_TEST_LO:
1253				REG_PATTERN_TEST(test->reg + (i * 8),
1254						test->mask,
1255						test->write);
1256				break;
1257			case TABLE64_TEST_HI:
1258				REG_PATTERN_TEST((test->reg + 4) + (i * 8),
1259						test->mask,
1260						test->write);
1261				break;
1262			}
1263		}
1264		test++;
1265	}
1266
1267	*data = 0;
1268	return 0;
1269}
1270
1271static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data)
1272{
1273	*data = 0;
1274
1275	/* Validate eeprom on all parts but i211 */
1276	if (adapter->hw.mac.type != e1000_i211) {
1277		if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0)
1278			*data = 2;
1279	}
1280
1281	return *data;
1282}
1283
1284static irqreturn_t igb_test_intr(int irq, void *data)
1285{
1286	struct igb_adapter *adapter = (struct igb_adapter *) data;
1287	struct e1000_hw *hw = &adapter->hw;
1288
1289	adapter->test_icr |= rd32(E1000_ICR);
1290
1291	return IRQ_HANDLED;
1292}
1293
1294static int igb_intr_test(struct igb_adapter *adapter, u64 *data)
1295{
1296	struct e1000_hw *hw = &adapter->hw;
1297	struct net_device *netdev = adapter->netdev;
1298	u32 mask, ics_mask, i = 0, shared_int = true;
1299	u32 irq = adapter->pdev->irq;
1300
1301	*data = 0;
1302
1303	/* Hook up test interrupt handler just for this test */
1304	if (adapter->msix_entries) {
1305		if (request_irq(adapter->msix_entries[0].vector,
1306		                igb_test_intr, 0, netdev->name, adapter)) {
1307			*data = 1;
1308			return -1;
1309		}
1310	} else if (adapter->flags & IGB_FLAG_HAS_MSI) {
1311		shared_int = false;
1312		if (request_irq(irq,
1313		                igb_test_intr, 0, netdev->name, adapter)) {
1314			*data = 1;
1315			return -1;
1316		}
1317	} else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED,
1318				netdev->name, adapter)) {
1319		shared_int = false;
1320	} else if (request_irq(irq, igb_test_intr, IRQF_SHARED,
1321		 netdev->name, adapter)) {
1322		*data = 1;
1323		return -1;
1324	}
1325	dev_info(&adapter->pdev->dev, "testing %s interrupt\n",
1326		(shared_int ? "shared" : "unshared"));
1327
1328	/* Disable all the interrupts */
1329	wr32(E1000_IMC, ~0);
1330	wrfl();
1331	msleep(10);
1332
1333	/* Define all writable bits for ICS */
1334	switch (hw->mac.type) {
1335	case e1000_82575:
1336		ics_mask = 0x37F47EDD;
1337		break;
1338	case e1000_82576:
1339		ics_mask = 0x77D4FBFD;
1340		break;
1341	case e1000_82580:
1342		ics_mask = 0x77DCFED5;
1343		break;
1344	case e1000_i350:
1345	case e1000_i210:
1346	case e1000_i211:
1347		ics_mask = 0x77DCFED5;
1348		break;
1349	default:
1350		ics_mask = 0x7FFFFFFF;
1351		break;
1352	}
1353
1354	/* Test each interrupt */
1355	for (; i < 31; i++) {
1356		/* Interrupt to test */
1357		mask = 1 << i;
1358
1359		if (!(mask & ics_mask))
1360			continue;
1361
1362		if (!shared_int) {
1363			/* Disable the interrupt to be reported in
1364			 * the cause register and then force the same
1365			 * interrupt and see if one gets posted.  If
1366			 * an interrupt was posted to the bus, the
1367			 * test failed.
1368			 */
1369			adapter->test_icr = 0;
1370
1371			/* Flush any pending interrupts */
1372			wr32(E1000_ICR, ~0);
1373
1374			wr32(E1000_IMC, mask);
1375			wr32(E1000_ICS, mask);
1376			wrfl();
1377			msleep(10);
1378
1379			if (adapter->test_icr & mask) {
1380				*data = 3;
1381				break;
1382			}
1383		}
1384
1385		/* Enable the interrupt to be reported in
1386		 * the cause register and then force the same
1387		 * interrupt and see if one gets posted.  If
1388		 * an interrupt was not posted to the bus, the
1389		 * test failed.
1390		 */
1391		adapter->test_icr = 0;
1392
1393		/* Flush any pending interrupts */
1394		wr32(E1000_ICR, ~0);
1395
1396		wr32(E1000_IMS, mask);
1397		wr32(E1000_ICS, mask);
1398		wrfl();
1399		msleep(10);
1400
1401		if (!(adapter->test_icr & mask)) {
1402			*data = 4;
1403			break;
1404		}
1405
1406		if (!shared_int) {
1407			/* Disable the other interrupts to be reported in
1408			 * the cause register and then force the other
1409			 * interrupts and see if any get posted.  If
1410			 * an interrupt was posted to the bus, the
1411			 * test failed.
1412			 */
1413			adapter->test_icr = 0;
1414
1415			/* Flush any pending interrupts */
1416			wr32(E1000_ICR, ~0);
1417
1418			wr32(E1000_IMC, ~mask);
1419			wr32(E1000_ICS, ~mask);
1420			wrfl();
1421			msleep(10);
1422
1423			if (adapter->test_icr & mask) {
1424				*data = 5;
1425				break;
1426			}
1427		}
1428	}
1429
1430	/* Disable all the interrupts */
1431	wr32(E1000_IMC, ~0);
1432	wrfl();
1433	msleep(10);
1434
1435	/* Unhook test interrupt handler */
1436	if (adapter->msix_entries)
1437		free_irq(adapter->msix_entries[0].vector, adapter);
1438	else
1439		free_irq(irq, adapter);
1440
1441	return *data;
1442}
1443
1444static void igb_free_desc_rings(struct igb_adapter *adapter)
1445{
1446	igb_free_tx_resources(&adapter->test_tx_ring);
1447	igb_free_rx_resources(&adapter->test_rx_ring);
1448}
1449
1450static int igb_setup_desc_rings(struct igb_adapter *adapter)
1451{
1452	struct igb_ring *tx_ring = &adapter->test_tx_ring;
1453	struct igb_ring *rx_ring = &adapter->test_rx_ring;
1454	struct e1000_hw *hw = &adapter->hw;
1455	int ret_val;
1456
1457	/* Setup Tx descriptor ring and Tx buffers */
1458	tx_ring->count = IGB_DEFAULT_TXD;
1459	tx_ring->dev = &adapter->pdev->dev;
1460	tx_ring->netdev = adapter->netdev;
1461	tx_ring->reg_idx = adapter->vfs_allocated_count;
1462
1463	if (igb_setup_tx_resources(tx_ring)) {
1464		ret_val = 1;
1465		goto err_nomem;
1466	}
1467
1468	igb_setup_tctl(adapter);
1469	igb_configure_tx_ring(adapter, tx_ring);
1470
1471	/* Setup Rx descriptor ring and Rx buffers */
1472	rx_ring->count = IGB_DEFAULT_RXD;
1473	rx_ring->dev = &adapter->pdev->dev;
1474	rx_ring->netdev = adapter->netdev;
1475	rx_ring->reg_idx = adapter->vfs_allocated_count;
1476
1477	if (igb_setup_rx_resources(rx_ring)) {
1478		ret_val = 3;
1479		goto err_nomem;
1480	}
1481
1482	/* set the default queue to queue 0 of PF */
1483	wr32(E1000_MRQC, adapter->vfs_allocated_count << 3);
1484
1485	/* enable receive ring */
1486	igb_setup_rctl(adapter);
1487	igb_configure_rx_ring(adapter, rx_ring);
1488
1489	igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring));
1490
1491	return 0;
1492
1493err_nomem:
1494	igb_free_desc_rings(adapter);
1495	return ret_val;
1496}
1497
1498static void igb_phy_disable_receiver(struct igb_adapter *adapter)
1499{
1500	struct e1000_hw *hw = &adapter->hw;
1501
1502	/* Write out to PHY registers 29 and 30 to disable the Receiver. */
1503	igb_write_phy_reg(hw, 29, 0x001F);
1504	igb_write_phy_reg(hw, 30, 0x8FFC);
1505	igb_write_phy_reg(hw, 29, 0x001A);
1506	igb_write_phy_reg(hw, 30, 0x8FF0);
1507}
1508
1509static int igb_integrated_phy_loopback(struct igb_adapter *adapter)
1510{
1511	struct e1000_hw *hw = &adapter->hw;
1512	u32 ctrl_reg = 0;
1513	u16 phy_reg = 0;
1514
1515	hw->mac.autoneg = false;
1516
1517	switch (hw->phy.type) {
1518	case e1000_phy_m88:
1519		/* Auto-MDI/MDIX Off */
1520		igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808);
1521		/* reset to update Auto-MDI/MDIX */
1522		igb_write_phy_reg(hw, PHY_CONTROL, 0x9140);
1523		/* autoneg off */
1524		igb_write_phy_reg(hw, PHY_CONTROL, 0x8140);
1525		break;
1526	case e1000_phy_82580:
1527		/* enable MII loopback */
1528		igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041);
1529		break;
1530	case e1000_phy_i210:
1531		/* set loopback speed in PHY */
1532		igb_read_phy_reg(hw, (GS40G_PAGE_SELECT & GS40G_PAGE_2),
1533					&phy_reg);
1534		phy_reg |= GS40G_MAC_SPEED_1G;
1535		igb_write_phy_reg(hw, (GS40G_PAGE_SELECT & GS40G_PAGE_2),
1536					phy_reg);
1537		ctrl_reg = rd32(E1000_CTRL_EXT);
1538	default:
1539		break;
1540	}
1541
1542	/* force 1000, set loopback */
1543	igb_write_phy_reg(hw, PHY_CONTROL, 0x4140);
1544
1545	/* Now set up the MAC to the same speed/duplex as the PHY. */
1546	ctrl_reg = rd32(E1000_CTRL);
1547	ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */
1548	ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */
1549		     E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */
1550		     E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */
1551		     E1000_CTRL_FD |	 /* Force Duplex to FULL */
1552		     E1000_CTRL_SLU);	 /* Set link up enable bit */
1553
1554	if ((hw->phy.type == e1000_phy_m88) || (hw->phy.type == e1000_phy_i210))
1555		ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
1556
1557	wr32(E1000_CTRL, ctrl_reg);
1558
1559	/* Disable the receiver on the PHY so when a cable is plugged in, the
1560	 * PHY does not begin to autoneg when a cable is reconnected to the NIC.
1561	 */
1562	if ((hw->phy.type == e1000_phy_m88) || (hw->phy.type == e1000_phy_i210))
1563		igb_phy_disable_receiver(adapter);
1564
1565	udelay(500);
1566
1567	return 0;
1568}
1569
1570static int igb_set_phy_loopback(struct igb_adapter *adapter)
1571{
1572	return igb_integrated_phy_loopback(adapter);
1573}
1574
1575static int igb_setup_loopback_test(struct igb_adapter *adapter)
1576{
1577	struct e1000_hw *hw = &adapter->hw;
1578	u32 reg;
1579
1580	reg = rd32(E1000_CTRL_EXT);
1581
1582	/* use CTRL_EXT to identify link type as SGMII can appear as copper */
1583	if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) {
1584		if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1585		(hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1586		(hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1587		(hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1588
1589			/* Enable DH89xxCC MPHY for near end loopback */
1590			reg = rd32(E1000_MPHY_ADDR_CTL);
1591			reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1592			E1000_MPHY_PCS_CLK_REG_OFFSET;
1593			wr32(E1000_MPHY_ADDR_CTL, reg);
1594
1595			reg = rd32(E1000_MPHY_DATA);
1596			reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1597			wr32(E1000_MPHY_DATA, reg);
1598		}
1599
1600		reg = rd32(E1000_RCTL);
1601		reg |= E1000_RCTL_LBM_TCVR;
1602		wr32(E1000_RCTL, reg);
1603
1604		wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK);
1605
1606		reg = rd32(E1000_CTRL);
1607		reg &= ~(E1000_CTRL_RFCE |
1608			 E1000_CTRL_TFCE |
1609			 E1000_CTRL_LRST);
1610		reg |= E1000_CTRL_SLU |
1611		       E1000_CTRL_FD;
1612		wr32(E1000_CTRL, reg);
1613
1614		/* Unset switch control to serdes energy detect */
1615		reg = rd32(E1000_CONNSW);
1616		reg &= ~E1000_CONNSW_ENRGSRC;
1617		wr32(E1000_CONNSW, reg);
1618
1619		/* Set PCS register for forced speed */
1620		reg = rd32(E1000_PCS_LCTL);
1621		reg &= ~E1000_PCS_LCTL_AN_ENABLE;     /* Disable Autoneg*/
1622		reg |= E1000_PCS_LCTL_FLV_LINK_UP |   /* Force link up */
1623		       E1000_PCS_LCTL_FSV_1000 |      /* Force 1000    */
1624		       E1000_PCS_LCTL_FDV_FULL |      /* SerDes Full duplex */
1625		       E1000_PCS_LCTL_FSD |           /* Force Speed */
1626		       E1000_PCS_LCTL_FORCE_LINK;     /* Force Link */
1627		wr32(E1000_PCS_LCTL, reg);
1628
1629		return 0;
1630	}
1631
1632	return igb_set_phy_loopback(adapter);
1633}
1634
1635static void igb_loopback_cleanup(struct igb_adapter *adapter)
1636{
1637	struct e1000_hw *hw = &adapter->hw;
1638	u32 rctl;
1639	u16 phy_reg;
1640
1641	if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) ||
1642	(hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) ||
1643	(hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) ||
1644	(hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) {
1645		u32 reg;
1646
1647		/* Disable near end loopback on DH89xxCC */
1648		reg = rd32(E1000_MPHY_ADDR_CTL);
1649		reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) |
1650		E1000_MPHY_PCS_CLK_REG_OFFSET;
1651		wr32(E1000_MPHY_ADDR_CTL, reg);
1652
1653		reg = rd32(E1000_MPHY_DATA);
1654		reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN;
1655		wr32(E1000_MPHY_DATA, reg);
1656	}
1657
1658	rctl = rd32(E1000_RCTL);
1659	rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
1660	wr32(E1000_RCTL, rctl);
1661
1662	hw->mac.autoneg = true;
1663	igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg);
1664	if (phy_reg & MII_CR_LOOPBACK) {
1665		phy_reg &= ~MII_CR_LOOPBACK;
1666		igb_write_phy_reg(hw, PHY_CONTROL, phy_reg);
1667		igb_phy_sw_reset(hw);
1668	}
1669}
1670
1671static void igb_create_lbtest_frame(struct sk_buff *skb,
1672				    unsigned int frame_size)
1673{
1674	memset(skb->data, 0xFF, frame_size);
1675	frame_size /= 2;
1676	memset(&skb->data[frame_size], 0xAA, frame_size - 1);
1677	memset(&skb->data[frame_size + 10], 0xBE, 1);
1678	memset(&skb->data[frame_size + 12], 0xAF, 1);
1679}
1680
1681static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size)
1682{
1683	frame_size /= 2;
1684	if (*(skb->data + 3) == 0xFF) {
1685		if ((*(skb->data + frame_size + 10) == 0xBE) &&
1686		   (*(skb->data + frame_size + 12) == 0xAF)) {
1687			return 0;
1688		}
1689	}
1690	return 13;
1691}
1692
1693static int igb_clean_test_rings(struct igb_ring *rx_ring,
1694                                struct igb_ring *tx_ring,
1695                                unsigned int size)
1696{
1697	union e1000_adv_rx_desc *rx_desc;
1698	struct igb_rx_buffer *rx_buffer_info;
1699	struct igb_tx_buffer *tx_buffer_info;
1700	struct netdev_queue *txq;
1701	u16 rx_ntc, tx_ntc, count = 0;
1702	unsigned int total_bytes = 0, total_packets = 0;
1703
1704	/* initialize next to clean and descriptor values */
1705	rx_ntc = rx_ring->next_to_clean;
1706	tx_ntc = tx_ring->next_to_clean;
1707	rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1708
1709	while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
1710		/* check rx buffer */
1711		rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc];
1712
1713		/* unmap rx buffer, will be remapped by alloc_rx_buffers */
1714		dma_unmap_single(rx_ring->dev,
1715				 rx_buffer_info->dma,
1716				 IGB_RX_HDR_LEN,
1717				 DMA_FROM_DEVICE);
1718		rx_buffer_info->dma = 0;
1719
1720		/* verify contents of skb */
1721		if (!igb_check_lbtest_frame(rx_buffer_info->skb, size))
1722			count++;
1723
1724		/* unmap buffer on tx side */
1725		tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc];
1726		total_bytes += tx_buffer_info->bytecount;
1727		total_packets += tx_buffer_info->gso_segs;
1728		igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
1729
1730		/* increment rx/tx next to clean counters */
1731		rx_ntc++;
1732		if (rx_ntc == rx_ring->count)
1733			rx_ntc = 0;
1734		tx_ntc++;
1735		if (tx_ntc == tx_ring->count)
1736			tx_ntc = 0;
1737
1738		/* fetch next descriptor */
1739		rx_desc = IGB_RX_DESC(rx_ring, rx_ntc);
1740	}
1741
1742	txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
1743	netdev_tx_completed_queue(txq, total_packets, total_bytes);
1744
1745	/* re-map buffers to ring, store next to clean values */
1746	igb_alloc_rx_buffers(rx_ring, count);
1747	rx_ring->next_to_clean = rx_ntc;
1748	tx_ring->next_to_clean = tx_ntc;
1749
1750	return count;
1751}
1752
1753static int igb_run_loopback_test(struct igb_adapter *adapter)
1754{
1755	struct igb_ring *tx_ring = &adapter->test_tx_ring;
1756	struct igb_ring *rx_ring = &adapter->test_rx_ring;
1757	u16 i, j, lc, good_cnt;
1758	int ret_val = 0;
1759	unsigned int size = IGB_RX_HDR_LEN;
1760	netdev_tx_t tx_ret_val;
1761	struct sk_buff *skb;
1762
1763	/* allocate test skb */
1764	skb = alloc_skb(size, GFP_KERNEL);
1765	if (!skb)
1766		return 11;
1767
1768	/* place data into test skb */
1769	igb_create_lbtest_frame(skb, size);
1770	skb_put(skb, size);
1771
1772	/*
1773	 * Calculate the loop count based on the largest descriptor ring
1774	 * The idea is to wrap the largest ring a number of times using 64
1775	 * send/receive pairs during each loop
1776	 */
1777
1778	if (rx_ring->count <= tx_ring->count)
1779		lc = ((tx_ring->count / 64) * 2) + 1;
1780	else
1781		lc = ((rx_ring->count / 64) * 2) + 1;
1782
1783	for (j = 0; j <= lc; j++) { /* loop count loop */
1784		/* reset count of good packets */
1785		good_cnt = 0;
1786
1787		/* place 64 packets on the transmit queue*/
1788		for (i = 0; i < 64; i++) {
1789			skb_get(skb);
1790			tx_ret_val = igb_xmit_frame_ring(skb, tx_ring);
1791			if (tx_ret_val == NETDEV_TX_OK)
1792				good_cnt++;
1793		}
1794
1795		if (good_cnt != 64) {
1796			ret_val = 12;
1797			break;
1798		}
1799
1800		/* allow 200 milliseconds for packets to go from tx to rx */
1801		msleep(200);
1802
1803		good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size);
1804		if (good_cnt != 64) {
1805			ret_val = 13;
1806			break;
1807		}
1808	} /* end loop count loop */
1809
1810	/* free the original skb */
1811	kfree_skb(skb);
1812
1813	return ret_val;
1814}
1815
1816static int igb_loopback_test(struct igb_adapter *adapter, u64 *data)
1817{
1818	/* PHY loopback cannot be performed if SoL/IDER
1819	 * sessions are active */
1820	if (igb_check_reset_block(&adapter->hw)) {
1821		dev_err(&adapter->pdev->dev,
1822			"Cannot do PHY loopback test "
1823			"when SoL/IDER is active.\n");
1824		*data = 0;
1825		goto out;
1826	}
1827	if ((adapter->hw.mac.type == e1000_i210)
1828		|| (adapter->hw.mac.type == e1000_i210)) {
1829		dev_err(&adapter->pdev->dev,
1830			"Loopback test not supported "
1831			"on this part at this time.\n");
1832		*data = 0;
1833		goto out;
1834	}
1835	*data = igb_setup_desc_rings(adapter);
1836	if (*data)
1837		goto out;
1838	*data = igb_setup_loopback_test(adapter);
1839	if (*data)
1840		goto err_loopback;
1841	*data = igb_run_loopback_test(adapter);
1842	igb_loopback_cleanup(adapter);
1843
1844err_loopback:
1845	igb_free_desc_rings(adapter);
1846out:
1847	return *data;
1848}
1849
1850static int igb_link_test(struct igb_adapter *adapter, u64 *data)
1851{
1852	struct e1000_hw *hw = &adapter->hw;
1853	*data = 0;
1854	if (hw->phy.media_type == e1000_media_type_internal_serdes) {
1855		int i = 0;
1856		hw->mac.serdes_has_link = false;
1857
1858		/* On some blade server designs, link establishment
1859		 * could take as long as 2-3 minutes */
1860		do {
1861			hw->mac.ops.check_for_link(&adapter->hw);
1862			if (hw->mac.serdes_has_link)
1863				return *data;
1864			msleep(20);
1865		} while (i++ < 3750);
1866
1867		*data = 1;
1868	} else {
1869		hw->mac.ops.check_for_link(&adapter->hw);
1870		if (hw->mac.autoneg)
1871			msleep(4000);
1872
1873		if (!(rd32(E1000_STATUS) & E1000_STATUS_LU))
1874			*data = 1;
1875	}
1876	return *data;
1877}
1878
1879static void igb_diag_test(struct net_device *netdev,
1880			  struct ethtool_test *eth_test, u64 *data)
1881{
1882	struct igb_adapter *adapter = netdev_priv(netdev);
1883	u16 autoneg_advertised;
1884	u8 forced_speed_duplex, autoneg;
1885	bool if_running = netif_running(netdev);
1886
1887	set_bit(__IGB_TESTING, &adapter->state);
1888	if (eth_test->flags == ETH_TEST_FL_OFFLINE) {
1889		/* Offline tests */
1890
1891		/* save speed, duplex, autoneg settings */
1892		autoneg_advertised = adapter->hw.phy.autoneg_advertised;
1893		forced_speed_duplex = adapter->hw.mac.forced_speed_duplex;
1894		autoneg = adapter->hw.mac.autoneg;
1895
1896		dev_info(&adapter->pdev->dev, "offline testing starting\n");
1897
1898		/* power up link for link test */
1899		igb_power_up_link(adapter);
1900
1901		/* Link test performed before hardware reset so autoneg doesn't
1902		 * interfere with test result */
1903		if (igb_link_test(adapter, &data[4]))
1904			eth_test->flags |= ETH_TEST_FL_FAILED;
1905
1906		if (if_running)
1907			/* indicate we're in test mode */
1908			dev_close(netdev);
1909		else
1910			igb_reset(adapter);
1911
1912		if (igb_reg_test(adapter, &data[0]))
1913			eth_test->flags |= ETH_TEST_FL_FAILED;
1914
1915		igb_reset(adapter);
1916		if (igb_eeprom_test(adapter, &data[1]))
1917			eth_test->flags |= ETH_TEST_FL_FAILED;
1918
1919		igb_reset(adapter);
1920		if (igb_intr_test(adapter, &data[2]))
1921			eth_test->flags |= ETH_TEST_FL_FAILED;
1922
1923		igb_reset(adapter);
1924		/* power up link for loopback test */
1925		igb_power_up_link(adapter);
1926		if (igb_loopback_test(adapter, &data[3]))
1927			eth_test->flags |= ETH_TEST_FL_FAILED;
1928
1929		/* restore speed, duplex, autoneg settings */
1930		adapter->hw.phy.autoneg_advertised = autoneg_advertised;
1931		adapter->hw.mac.forced_speed_duplex = forced_speed_duplex;
1932		adapter->hw.mac.autoneg = autoneg;
1933
1934		/* force this routine to wait until autoneg complete/timeout */
1935		adapter->hw.phy.autoneg_wait_to_complete = true;
1936		igb_reset(adapter);
1937		adapter->hw.phy.autoneg_wait_to_complete = false;
1938
1939		clear_bit(__IGB_TESTING, &adapter->state);
1940		if (if_running)
1941			dev_open(netdev);
1942	} else {
1943		dev_info(&adapter->pdev->dev, "online testing starting\n");
1944
1945		/* PHY is powered down when interface is down */
1946		if (if_running && igb_link_test(adapter, &data[4]))
1947			eth_test->flags |= ETH_TEST_FL_FAILED;
1948		else
1949			data[4] = 0;
1950
1951		/* Online tests aren't run; pass by default */
1952		data[0] = 0;
1953		data[1] = 0;
1954		data[2] = 0;
1955		data[3] = 0;
1956
1957		clear_bit(__IGB_TESTING, &adapter->state);
1958	}
1959	msleep_interruptible(4 * 1000);
1960}
1961
1962static int igb_wol_exclusion(struct igb_adapter *adapter,
1963			     struct ethtool_wolinfo *wol)
1964{
1965	struct e1000_hw *hw = &adapter->hw;
1966	int retval = 1; /* fail by default */
1967
1968	switch (hw->device_id) {
1969	case E1000_DEV_ID_82575GB_QUAD_COPPER:
1970		/* WoL not supported */
1971		wol->supported = 0;
1972		break;
1973	case E1000_DEV_ID_82575EB_FIBER_SERDES:
1974	case E1000_DEV_ID_82576_FIBER:
1975	case E1000_DEV_ID_82576_SERDES:
1976		/* Wake events not supported on port B */
1977		if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) {
1978			wol->supported = 0;
1979			break;
1980		}
1981		/* return success for non excluded adapter ports */
1982		retval = 0;
1983		break;
1984	case E1000_DEV_ID_82576_QUAD_COPPER:
1985	case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
1986		/* quad port adapters only support WoL on port A */
1987		if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) {
1988			wol->supported = 0;
1989			break;
1990		}
1991		/* return success for non excluded adapter ports */
1992		retval = 0;
1993		break;
1994	default:
1995		/* dual port cards only support WoL on port A from now on
1996		 * unless it was enabled in the eeprom for port B
1997		 * so exclude FUNC_1 ports from having WoL enabled */
1998		if ((rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) &&
1999		    !adapter->eeprom_wol) {
2000			wol->supported = 0;
2001			break;
2002		}
2003
2004		retval = 0;
2005	}
2006
2007	return retval;
2008}
2009
2010static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2011{
2012	struct igb_adapter *adapter = netdev_priv(netdev);
2013
2014	wol->supported = WAKE_UCAST | WAKE_MCAST |
2015	                 WAKE_BCAST | WAKE_MAGIC |
2016	                 WAKE_PHY;
2017	wol->wolopts = 0;
2018
2019	/* this function will set ->supported = 0 and return 1 if wol is not
2020	 * supported by this hardware */
2021	if (igb_wol_exclusion(adapter, wol) ||
2022	    !device_can_wakeup(&adapter->pdev->dev))
2023		return;
2024
2025	/* apply any specific unsupported masks here */
2026	switch (adapter->hw.device_id) {
2027	default:
2028		break;
2029	}
2030
2031	if (adapter->wol & E1000_WUFC_EX)
2032		wol->wolopts |= WAKE_UCAST;
2033	if (adapter->wol & E1000_WUFC_MC)
2034		wol->wolopts |= WAKE_MCAST;
2035	if (adapter->wol & E1000_WUFC_BC)
2036		wol->wolopts |= WAKE_BCAST;
2037	if (adapter->wol & E1000_WUFC_MAG)
2038		wol->wolopts |= WAKE_MAGIC;
2039	if (adapter->wol & E1000_WUFC_LNKC)
2040		wol->wolopts |= WAKE_PHY;
2041}
2042
2043static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
2044{
2045	struct igb_adapter *adapter = netdev_priv(netdev);
2046
2047	if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE))
2048		return -EOPNOTSUPP;
2049
2050	if (igb_wol_exclusion(adapter, wol) ||
2051	    !device_can_wakeup(&adapter->pdev->dev))
2052		return wol->wolopts ? -EOPNOTSUPP : 0;
2053
2054	/* these settings will always override what we currently have */
2055	adapter->wol = 0;
2056
2057	if (wol->wolopts & WAKE_UCAST)
2058		adapter->wol |= E1000_WUFC_EX;
2059	if (wol->wolopts & WAKE_MCAST)
2060		adapter->wol |= E1000_WUFC_MC;
2061	if (wol->wolopts & WAKE_BCAST)
2062		adapter->wol |= E1000_WUFC_BC;
2063	if (wol->wolopts & WAKE_MAGIC)
2064		adapter->wol |= E1000_WUFC_MAG;
2065	if (wol->wolopts & WAKE_PHY)
2066		adapter->wol |= E1000_WUFC_LNKC;
2067	device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2068
2069	return 0;
2070}
2071
2072/* bit defines for adapter->led_status */
2073#define IGB_LED_ON		0
2074
2075static int igb_set_phys_id(struct net_device *netdev,
2076			   enum ethtool_phys_id_state state)
2077{
2078	struct igb_adapter *adapter = netdev_priv(netdev);
2079	struct e1000_hw *hw = &adapter->hw;
2080
2081	switch (state) {
2082	case ETHTOOL_ID_ACTIVE:
2083		igb_blink_led(hw);
2084		return 2;
2085	case ETHTOOL_ID_ON:
2086		igb_blink_led(hw);
2087		break;
2088	case ETHTOOL_ID_OFF:
2089		igb_led_off(hw);
2090		break;
2091	case ETHTOOL_ID_INACTIVE:
2092		igb_led_off(hw);
2093		clear_bit(IGB_LED_ON, &adapter->led_status);
2094		igb_cleanup_led(hw);
2095		break;
2096	}
2097
2098	return 0;
2099}
2100
2101static int igb_set_coalesce(struct net_device *netdev,
2102			    struct ethtool_coalesce *ec)
2103{
2104	struct igb_adapter *adapter = netdev_priv(netdev);
2105	int i;
2106
2107	if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2108	    ((ec->rx_coalesce_usecs > 3) &&
2109	     (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2110	    (ec->rx_coalesce_usecs == 2))
2111		return -EINVAL;
2112
2113	if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) ||
2114	    ((ec->tx_coalesce_usecs > 3) &&
2115	     (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) ||
2116	    (ec->tx_coalesce_usecs == 2))
2117		return -EINVAL;
2118
2119	if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs)
2120		return -EINVAL;
2121
2122	/* If ITR is disabled, disable DMAC */
2123	if (ec->rx_coalesce_usecs == 0) {
2124		if (adapter->flags & IGB_FLAG_DMAC)
2125			adapter->flags &= ~IGB_FLAG_DMAC;
2126	}
2127
2128	/* convert to rate of irq's per second */
2129	if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3)
2130		adapter->rx_itr_setting = ec->rx_coalesce_usecs;
2131	else
2132		adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2;
2133
2134	/* convert to rate of irq's per second */
2135	if (adapter->flags & IGB_FLAG_QUEUE_PAIRS)
2136		adapter->tx_itr_setting = adapter->rx_itr_setting;
2137	else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3)
2138		adapter->tx_itr_setting = ec->tx_coalesce_usecs;
2139	else
2140		adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2;
2141
2142	for (i = 0; i < adapter->num_q_vectors; i++) {
2143		struct igb_q_vector *q_vector = adapter->q_vector[i];
2144		q_vector->tx.work_limit = adapter->tx_work_limit;
2145		if (q_vector->rx.ring)
2146			q_vector->itr_val = adapter->rx_itr_setting;
2147		else
2148			q_vector->itr_val = adapter->tx_itr_setting;
2149		if (q_vector->itr_val && q_vector->itr_val <= 3)
2150			q_vector->itr_val = IGB_START_ITR;
2151		q_vector->set_itr = 1;
2152	}
2153
2154	return 0;
2155}
2156
2157static int igb_get_coalesce(struct net_device *netdev,
2158			    struct ethtool_coalesce *ec)
2159{
2160	struct igb_adapter *adapter = netdev_priv(netdev);
2161
2162	if (adapter->rx_itr_setting <= 3)
2163		ec->rx_coalesce_usecs = adapter->rx_itr_setting;
2164	else
2165		ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2;
2166
2167	if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) {
2168		if (adapter->tx_itr_setting <= 3)
2169			ec->tx_coalesce_usecs = adapter->tx_itr_setting;
2170		else
2171			ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2;
2172	}
2173
2174	return 0;
2175}
2176
2177static int igb_nway_reset(struct net_device *netdev)
2178{
2179	struct igb_adapter *adapter = netdev_priv(netdev);
2180	if (netif_running(netdev))
2181		igb_reinit_locked(adapter);
2182	return 0;
2183}
2184
2185static int igb_get_sset_count(struct net_device *netdev, int sset)
2186{
2187	switch (sset) {
2188	case ETH_SS_STATS:
2189		return IGB_STATS_LEN;
2190	case ETH_SS_TEST:
2191		return IGB_TEST_LEN;
2192	default:
2193		return -ENOTSUPP;
2194	}
2195}
2196
2197static void igb_get_ethtool_stats(struct net_device *netdev,
2198				  struct ethtool_stats *stats, u64 *data)
2199{
2200	struct igb_adapter *adapter = netdev_priv(netdev);
2201	struct rtnl_link_stats64 *net_stats = &adapter->stats64;
2202	unsigned int start;
2203	struct igb_ring *ring;
2204	int i, j;
2205	char *p;
2206
2207	spin_lock(&adapter->stats64_lock);
2208	igb_update_stats(adapter, net_stats);
2209
2210	for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2211		p = (char *)adapter + igb_gstrings_stats[i].stat_offset;
2212		data[i] = (igb_gstrings_stats[i].sizeof_stat ==
2213			sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2214	}
2215	for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) {
2216		p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset;
2217		data[i] = (igb_gstrings_net_stats[j].sizeof_stat ==
2218			sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
2219	}
2220	for (j = 0; j < adapter->num_tx_queues; j++) {
2221		u64	restart2;
2222
2223		ring = adapter->tx_ring[j];
2224		do {
2225			start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
2226			data[i]   = ring->tx_stats.packets;
2227			data[i+1] = ring->tx_stats.bytes;
2228			data[i+2] = ring->tx_stats.restart_queue;
2229		} while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
2230		do {
2231			start = u64_stats_fetch_begin_bh(&ring->tx_syncp2);
2232			restart2  = ring->tx_stats.restart_queue2;
2233		} while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start));
2234		data[i+2] += restart2;
2235
2236		i += IGB_TX_QUEUE_STATS_LEN;
2237	}
2238	for (j = 0; j < adapter->num_rx_queues; j++) {
2239		ring = adapter->rx_ring[j];
2240		do {
2241			start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
2242			data[i]   = ring->rx_stats.packets;
2243			data[i+1] = ring->rx_stats.bytes;
2244			data[i+2] = ring->rx_stats.drops;
2245			data[i+3] = ring->rx_stats.csum_err;
2246			data[i+4] = ring->rx_stats.alloc_failed;
2247		} while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
2248		i += IGB_RX_QUEUE_STATS_LEN;
2249	}
2250	spin_unlock(&adapter->stats64_lock);
2251}
2252
2253static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
2254{
2255	struct igb_adapter *adapter = netdev_priv(netdev);
2256	u8 *p = data;
2257	int i;
2258
2259	switch (stringset) {
2260	case ETH_SS_TEST:
2261		memcpy(data, *igb_gstrings_test,
2262			IGB_TEST_LEN*ETH_GSTRING_LEN);
2263		break;
2264	case ETH_SS_STATS:
2265		for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) {
2266			memcpy(p, igb_gstrings_stats[i].stat_string,
2267			       ETH_GSTRING_LEN);
2268			p += ETH_GSTRING_LEN;
2269		}
2270		for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) {
2271			memcpy(p, igb_gstrings_net_stats[i].stat_string,
2272			       ETH_GSTRING_LEN);
2273			p += ETH_GSTRING_LEN;
2274		}
2275		for (i = 0; i < adapter->num_tx_queues; i++) {
2276			sprintf(p, "tx_queue_%u_packets", i);
2277			p += ETH_GSTRING_LEN;
2278			sprintf(p, "tx_queue_%u_bytes", i);
2279			p += ETH_GSTRING_LEN;
2280			sprintf(p, "tx_queue_%u_restart", i);
2281			p += ETH_GSTRING_LEN;
2282		}
2283		for (i = 0; i < adapter->num_rx_queues; i++) {
2284			sprintf(p, "rx_queue_%u_packets", i);
2285			p += ETH_GSTRING_LEN;
2286			sprintf(p, "rx_queue_%u_bytes", i);
2287			p += ETH_GSTRING_LEN;
2288			sprintf(p, "rx_queue_%u_drops", i);
2289			p += ETH_GSTRING_LEN;
2290			sprintf(p, "rx_queue_%u_csum_err", i);
2291			p += ETH_GSTRING_LEN;
2292			sprintf(p, "rx_queue_%u_alloc_failed", i);
2293			p += ETH_GSTRING_LEN;
2294		}
2295/*		BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */
2296		break;
2297	}
2298}
2299
2300static int igb_ethtool_begin(struct net_device *netdev)
2301{
2302	struct igb_adapter *adapter = netdev_priv(netdev);
2303	pm_runtime_get_sync(&adapter->pdev->dev);
2304	return 0;
2305}
2306
2307static void igb_ethtool_complete(struct net_device *netdev)
2308{
2309	struct igb_adapter *adapter = netdev_priv(netdev);
2310	pm_runtime_put(&adapter->pdev->dev);
2311}
2312
2313#ifdef CONFIG_IGB_PTP
2314static int igb_ethtool_get_ts_info(struct net_device *dev,
2315				   struct ethtool_ts_info *info)
2316{
2317	struct igb_adapter *adapter = netdev_priv(dev);
2318
2319	info->so_timestamping =
2320		SOF_TIMESTAMPING_TX_HARDWARE |
2321		SOF_TIMESTAMPING_RX_HARDWARE |
2322		SOF_TIMESTAMPING_RAW_HARDWARE;
2323
2324	if (adapter->ptp_clock)
2325		info->phc_index = ptp_clock_index(adapter->ptp_clock);
2326	else
2327		info->phc_index = -1;
2328
2329	info->tx_types =
2330		(1 << HWTSTAMP_TX_OFF) |
2331		(1 << HWTSTAMP_TX_ON);
2332
2333	info->rx_filters =
2334		(1 << HWTSTAMP_FILTER_NONE) |
2335		(1 << HWTSTAMP_FILTER_ALL) |
2336		(1 << HWTSTAMP_FILTER_SOME) |
2337		(1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
2338		(1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
2339		(1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2340
2341	return 0;
2342}
2343
2344#endif
2345static const struct ethtool_ops igb_ethtool_ops = {
2346	.get_settings           = igb_get_settings,
2347	.set_settings           = igb_set_settings,
2348	.get_drvinfo            = igb_get_drvinfo,
2349	.get_regs_len           = igb_get_regs_len,
2350	.get_regs               = igb_get_regs,
2351	.get_wol                = igb_get_wol,
2352	.set_wol                = igb_set_wol,
2353	.get_msglevel           = igb_get_msglevel,
2354	.set_msglevel           = igb_set_msglevel,
2355	.nway_reset             = igb_nway_reset,
2356	.get_link               = igb_get_link,
2357	.get_eeprom_len         = igb_get_eeprom_len,
2358	.get_eeprom             = igb_get_eeprom,
2359	.set_eeprom             = igb_set_eeprom,
2360	.get_ringparam          = igb_get_ringparam,
2361	.set_ringparam          = igb_set_ringparam,
2362	.get_pauseparam         = igb_get_pauseparam,
2363	.set_pauseparam         = igb_set_pauseparam,
2364	.self_test              = igb_diag_test,
2365	.get_strings            = igb_get_strings,
2366	.set_phys_id            = igb_set_phys_id,
2367	.get_sset_count         = igb_get_sset_count,
2368	.get_ethtool_stats      = igb_get_ethtool_stats,
2369	.get_coalesce           = igb_get_coalesce,
2370	.set_coalesce           = igb_set_coalesce,
2371	.begin			= igb_ethtool_begin,
2372	.complete		= igb_ethtool_complete,
2373#ifdef CONFIG_IGB_PTP
2374	.get_ts_info		= igb_ethtool_get_ts_info,
2375#endif
2376};
2377
2378void igb_set_ethtool_ops(struct net_device *netdev)
2379{
2380	SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops);
2381}
2382