igb_ethtool.c revision d836200a1c239a488cd2ed9867f4792f25f721d5
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28/* ethtool support for igb */ 29 30#include <linux/vmalloc.h> 31#include <linux/netdevice.h> 32#include <linux/pci.h> 33#include <linux/delay.h> 34#include <linux/interrupt.h> 35#include <linux/if_ether.h> 36#include <linux/ethtool.h> 37#include <linux/sched.h> 38#include <linux/slab.h> 39#include <linux/pm_runtime.h> 40 41#include "igb.h" 42 43struct igb_stats { 44 char stat_string[ETH_GSTRING_LEN]; 45 int sizeof_stat; 46 int stat_offset; 47}; 48 49#define IGB_STAT(_name, _stat) { \ 50 .stat_string = _name, \ 51 .sizeof_stat = FIELD_SIZEOF(struct igb_adapter, _stat), \ 52 .stat_offset = offsetof(struct igb_adapter, _stat) \ 53} 54static const struct igb_stats igb_gstrings_stats[] = { 55 IGB_STAT("rx_packets", stats.gprc), 56 IGB_STAT("tx_packets", stats.gptc), 57 IGB_STAT("rx_bytes", stats.gorc), 58 IGB_STAT("tx_bytes", stats.gotc), 59 IGB_STAT("rx_broadcast", stats.bprc), 60 IGB_STAT("tx_broadcast", stats.bptc), 61 IGB_STAT("rx_multicast", stats.mprc), 62 IGB_STAT("tx_multicast", stats.mptc), 63 IGB_STAT("multicast", stats.mprc), 64 IGB_STAT("collisions", stats.colc), 65 IGB_STAT("rx_crc_errors", stats.crcerrs), 66 IGB_STAT("rx_no_buffer_count", stats.rnbc), 67 IGB_STAT("rx_missed_errors", stats.mpc), 68 IGB_STAT("tx_aborted_errors", stats.ecol), 69 IGB_STAT("tx_carrier_errors", stats.tncrs), 70 IGB_STAT("tx_window_errors", stats.latecol), 71 IGB_STAT("tx_abort_late_coll", stats.latecol), 72 IGB_STAT("tx_deferred_ok", stats.dc), 73 IGB_STAT("tx_single_coll_ok", stats.scc), 74 IGB_STAT("tx_multi_coll_ok", stats.mcc), 75 IGB_STAT("tx_timeout_count", tx_timeout_count), 76 IGB_STAT("rx_long_length_errors", stats.roc), 77 IGB_STAT("rx_short_length_errors", stats.ruc), 78 IGB_STAT("rx_align_errors", stats.algnerrc), 79 IGB_STAT("tx_tcp_seg_good", stats.tsctc), 80 IGB_STAT("tx_tcp_seg_failed", stats.tsctfc), 81 IGB_STAT("rx_flow_control_xon", stats.xonrxc), 82 IGB_STAT("rx_flow_control_xoff", stats.xoffrxc), 83 IGB_STAT("tx_flow_control_xon", stats.xontxc), 84 IGB_STAT("tx_flow_control_xoff", stats.xofftxc), 85 IGB_STAT("rx_long_byte_count", stats.gorc), 86 IGB_STAT("tx_dma_out_of_sync", stats.doosync), 87 IGB_STAT("tx_smbus", stats.mgptc), 88 IGB_STAT("rx_smbus", stats.mgprc), 89 IGB_STAT("dropped_smbus", stats.mgpdc), 90 IGB_STAT("os2bmc_rx_by_bmc", stats.o2bgptc), 91 IGB_STAT("os2bmc_tx_by_bmc", stats.b2ospc), 92 IGB_STAT("os2bmc_tx_by_host", stats.o2bspc), 93 IGB_STAT("os2bmc_rx_by_host", stats.b2ogprc), 94}; 95 96#define IGB_NETDEV_STAT(_net_stat) { \ 97 .stat_string = __stringify(_net_stat), \ 98 .sizeof_stat = FIELD_SIZEOF(struct rtnl_link_stats64, _net_stat), \ 99 .stat_offset = offsetof(struct rtnl_link_stats64, _net_stat) \ 100} 101static const struct igb_stats igb_gstrings_net_stats[] = { 102 IGB_NETDEV_STAT(rx_errors), 103 IGB_NETDEV_STAT(tx_errors), 104 IGB_NETDEV_STAT(tx_dropped), 105 IGB_NETDEV_STAT(rx_length_errors), 106 IGB_NETDEV_STAT(rx_over_errors), 107 IGB_NETDEV_STAT(rx_frame_errors), 108 IGB_NETDEV_STAT(rx_fifo_errors), 109 IGB_NETDEV_STAT(tx_fifo_errors), 110 IGB_NETDEV_STAT(tx_heartbeat_errors) 111}; 112 113#define IGB_GLOBAL_STATS_LEN \ 114 (sizeof(igb_gstrings_stats) / sizeof(struct igb_stats)) 115#define IGB_NETDEV_STATS_LEN \ 116 (sizeof(igb_gstrings_net_stats) / sizeof(struct igb_stats)) 117#define IGB_RX_QUEUE_STATS_LEN \ 118 (sizeof(struct igb_rx_queue_stats) / sizeof(u64)) 119 120#define IGB_TX_QUEUE_STATS_LEN 3 /* packets, bytes, restart_queue */ 121 122#define IGB_QUEUE_STATS_LEN \ 123 ((((struct igb_adapter *)netdev_priv(netdev))->num_rx_queues * \ 124 IGB_RX_QUEUE_STATS_LEN) + \ 125 (((struct igb_adapter *)netdev_priv(netdev))->num_tx_queues * \ 126 IGB_TX_QUEUE_STATS_LEN)) 127#define IGB_STATS_LEN \ 128 (IGB_GLOBAL_STATS_LEN + IGB_NETDEV_STATS_LEN + IGB_QUEUE_STATS_LEN) 129 130static const char igb_gstrings_test[][ETH_GSTRING_LEN] = { 131 "Register test (offline)", "Eeprom test (offline)", 132 "Interrupt test (offline)", "Loopback test (offline)", 133 "Link test (on/offline)" 134}; 135#define IGB_TEST_LEN (sizeof(igb_gstrings_test) / ETH_GSTRING_LEN) 136 137static int igb_get_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 138{ 139 struct igb_adapter *adapter = netdev_priv(netdev); 140 struct e1000_hw *hw = &adapter->hw; 141 u32 status; 142 143 if (hw->phy.media_type == e1000_media_type_copper) { 144 145 ecmd->supported = (SUPPORTED_10baseT_Half | 146 SUPPORTED_10baseT_Full | 147 SUPPORTED_100baseT_Half | 148 SUPPORTED_100baseT_Full | 149 SUPPORTED_1000baseT_Full| 150 SUPPORTED_Autoneg | 151 SUPPORTED_TP); 152 ecmd->advertising = (ADVERTISED_TP | 153 ADVERTISED_Pause); 154 155 if (hw->mac.autoneg == 1) { 156 ecmd->advertising |= ADVERTISED_Autoneg; 157 /* the e1000 autoneg seems to match ethtool nicely */ 158 ecmd->advertising |= hw->phy.autoneg_advertised; 159 } 160 161 ecmd->port = PORT_TP; 162 ecmd->phy_address = hw->phy.addr; 163 } else { 164 ecmd->supported = (SUPPORTED_1000baseT_Full | 165 SUPPORTED_FIBRE | 166 SUPPORTED_Autoneg); 167 168 ecmd->advertising = (ADVERTISED_1000baseT_Full | 169 ADVERTISED_FIBRE | 170 ADVERTISED_Autoneg | 171 ADVERTISED_Pause); 172 173 ecmd->port = PORT_FIBRE; 174 } 175 176 ecmd->transceiver = XCVR_INTERNAL; 177 178 status = rd32(E1000_STATUS); 179 180 if (status & E1000_STATUS_LU) { 181 182 if ((status & E1000_STATUS_SPEED_1000) || 183 hw->phy.media_type != e1000_media_type_copper) 184 ethtool_cmd_speed_set(ecmd, SPEED_1000); 185 else if (status & E1000_STATUS_SPEED_100) 186 ethtool_cmd_speed_set(ecmd, SPEED_100); 187 else 188 ethtool_cmd_speed_set(ecmd, SPEED_10); 189 190 if ((status & E1000_STATUS_FD) || 191 hw->phy.media_type != e1000_media_type_copper) 192 ecmd->duplex = DUPLEX_FULL; 193 else 194 ecmd->duplex = DUPLEX_HALF; 195 } else { 196 ethtool_cmd_speed_set(ecmd, -1); 197 ecmd->duplex = -1; 198 } 199 200 ecmd->autoneg = hw->mac.autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE; 201 return 0; 202} 203 204static int igb_set_settings(struct net_device *netdev, struct ethtool_cmd *ecmd) 205{ 206 struct igb_adapter *adapter = netdev_priv(netdev); 207 struct e1000_hw *hw = &adapter->hw; 208 209 /* When SoL/IDER sessions are active, autoneg/speed/duplex 210 * cannot be changed */ 211 if (igb_check_reset_block(hw)) { 212 dev_err(&adapter->pdev->dev, 213 "Cannot change link characteristics when SoL/IDER is active.\n"); 214 return -EINVAL; 215 } 216 217 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 218 msleep(1); 219 220 if (ecmd->autoneg == AUTONEG_ENABLE) { 221 hw->mac.autoneg = 1; 222 hw->phy.autoneg_advertised = ecmd->advertising | 223 ADVERTISED_TP | 224 ADVERTISED_Autoneg; 225 ecmd->advertising = hw->phy.autoneg_advertised; 226 if (adapter->fc_autoneg) 227 hw->fc.requested_mode = e1000_fc_default; 228 } else { 229 u32 speed = ethtool_cmd_speed(ecmd); 230 if (igb_set_spd_dplx(adapter, speed, ecmd->duplex)) { 231 clear_bit(__IGB_RESETTING, &adapter->state); 232 return -EINVAL; 233 } 234 } 235 236 /* reset the link */ 237 if (netif_running(adapter->netdev)) { 238 igb_down(adapter); 239 igb_up(adapter); 240 } else 241 igb_reset(adapter); 242 243 clear_bit(__IGB_RESETTING, &adapter->state); 244 return 0; 245} 246 247static u32 igb_get_link(struct net_device *netdev) 248{ 249 struct igb_adapter *adapter = netdev_priv(netdev); 250 struct e1000_mac_info *mac = &adapter->hw.mac; 251 252 /* 253 * If the link is not reported up to netdev, interrupts are disabled, 254 * and so the physical link state may have changed since we last 255 * looked. Set get_link_status to make sure that the true link 256 * state is interrogated, rather than pulling a cached and possibly 257 * stale link state from the driver. 258 */ 259 if (!netif_carrier_ok(netdev)) 260 mac->get_link_status = 1; 261 262 return igb_has_link(adapter); 263} 264 265static void igb_get_pauseparam(struct net_device *netdev, 266 struct ethtool_pauseparam *pause) 267{ 268 struct igb_adapter *adapter = netdev_priv(netdev); 269 struct e1000_hw *hw = &adapter->hw; 270 271 pause->autoneg = 272 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE); 273 274 if (hw->fc.current_mode == e1000_fc_rx_pause) 275 pause->rx_pause = 1; 276 else if (hw->fc.current_mode == e1000_fc_tx_pause) 277 pause->tx_pause = 1; 278 else if (hw->fc.current_mode == e1000_fc_full) { 279 pause->rx_pause = 1; 280 pause->tx_pause = 1; 281 } 282} 283 284static int igb_set_pauseparam(struct net_device *netdev, 285 struct ethtool_pauseparam *pause) 286{ 287 struct igb_adapter *adapter = netdev_priv(netdev); 288 struct e1000_hw *hw = &adapter->hw; 289 int retval = 0; 290 291 adapter->fc_autoneg = pause->autoneg; 292 293 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 294 msleep(1); 295 296 if (adapter->fc_autoneg == AUTONEG_ENABLE) { 297 hw->fc.requested_mode = e1000_fc_default; 298 if (netif_running(adapter->netdev)) { 299 igb_down(adapter); 300 igb_up(adapter); 301 } else { 302 igb_reset(adapter); 303 } 304 } else { 305 if (pause->rx_pause && pause->tx_pause) 306 hw->fc.requested_mode = e1000_fc_full; 307 else if (pause->rx_pause && !pause->tx_pause) 308 hw->fc.requested_mode = e1000_fc_rx_pause; 309 else if (!pause->rx_pause && pause->tx_pause) 310 hw->fc.requested_mode = e1000_fc_tx_pause; 311 else if (!pause->rx_pause && !pause->tx_pause) 312 hw->fc.requested_mode = e1000_fc_none; 313 314 hw->fc.current_mode = hw->fc.requested_mode; 315 316 retval = ((hw->phy.media_type == e1000_media_type_copper) ? 317 igb_force_mac_fc(hw) : igb_setup_link(hw)); 318 } 319 320 clear_bit(__IGB_RESETTING, &adapter->state); 321 return retval; 322} 323 324static u32 igb_get_msglevel(struct net_device *netdev) 325{ 326 struct igb_adapter *adapter = netdev_priv(netdev); 327 return adapter->msg_enable; 328} 329 330static void igb_set_msglevel(struct net_device *netdev, u32 data) 331{ 332 struct igb_adapter *adapter = netdev_priv(netdev); 333 adapter->msg_enable = data; 334} 335 336static int igb_get_regs_len(struct net_device *netdev) 337{ 338#define IGB_REGS_LEN 739 339 return IGB_REGS_LEN * sizeof(u32); 340} 341 342static void igb_get_regs(struct net_device *netdev, 343 struct ethtool_regs *regs, void *p) 344{ 345 struct igb_adapter *adapter = netdev_priv(netdev); 346 struct e1000_hw *hw = &adapter->hw; 347 u32 *regs_buff = p; 348 u8 i; 349 350 memset(p, 0, IGB_REGS_LEN * sizeof(u32)); 351 352 regs->version = (1 << 24) | (hw->revision_id << 16) | hw->device_id; 353 354 /* General Registers */ 355 regs_buff[0] = rd32(E1000_CTRL); 356 regs_buff[1] = rd32(E1000_STATUS); 357 regs_buff[2] = rd32(E1000_CTRL_EXT); 358 regs_buff[3] = rd32(E1000_MDIC); 359 regs_buff[4] = rd32(E1000_SCTL); 360 regs_buff[5] = rd32(E1000_CONNSW); 361 regs_buff[6] = rd32(E1000_VET); 362 regs_buff[7] = rd32(E1000_LEDCTL); 363 regs_buff[8] = rd32(E1000_PBA); 364 regs_buff[9] = rd32(E1000_PBS); 365 regs_buff[10] = rd32(E1000_FRTIMER); 366 regs_buff[11] = rd32(E1000_TCPTIMER); 367 368 /* NVM Register */ 369 regs_buff[12] = rd32(E1000_EECD); 370 371 /* Interrupt */ 372 /* Reading EICS for EICR because they read the 373 * same but EICS does not clear on read */ 374 regs_buff[13] = rd32(E1000_EICS); 375 regs_buff[14] = rd32(E1000_EICS); 376 regs_buff[15] = rd32(E1000_EIMS); 377 regs_buff[16] = rd32(E1000_EIMC); 378 regs_buff[17] = rd32(E1000_EIAC); 379 regs_buff[18] = rd32(E1000_EIAM); 380 /* Reading ICS for ICR because they read the 381 * same but ICS does not clear on read */ 382 regs_buff[19] = rd32(E1000_ICS); 383 regs_buff[20] = rd32(E1000_ICS); 384 regs_buff[21] = rd32(E1000_IMS); 385 regs_buff[22] = rd32(E1000_IMC); 386 regs_buff[23] = rd32(E1000_IAC); 387 regs_buff[24] = rd32(E1000_IAM); 388 regs_buff[25] = rd32(E1000_IMIRVP); 389 390 /* Flow Control */ 391 regs_buff[26] = rd32(E1000_FCAL); 392 regs_buff[27] = rd32(E1000_FCAH); 393 regs_buff[28] = rd32(E1000_FCTTV); 394 regs_buff[29] = rd32(E1000_FCRTL); 395 regs_buff[30] = rd32(E1000_FCRTH); 396 regs_buff[31] = rd32(E1000_FCRTV); 397 398 /* Receive */ 399 regs_buff[32] = rd32(E1000_RCTL); 400 regs_buff[33] = rd32(E1000_RXCSUM); 401 regs_buff[34] = rd32(E1000_RLPML); 402 regs_buff[35] = rd32(E1000_RFCTL); 403 regs_buff[36] = rd32(E1000_MRQC); 404 regs_buff[37] = rd32(E1000_VT_CTL); 405 406 /* Transmit */ 407 regs_buff[38] = rd32(E1000_TCTL); 408 regs_buff[39] = rd32(E1000_TCTL_EXT); 409 regs_buff[40] = rd32(E1000_TIPG); 410 regs_buff[41] = rd32(E1000_DTXCTL); 411 412 /* Wake Up */ 413 regs_buff[42] = rd32(E1000_WUC); 414 regs_buff[43] = rd32(E1000_WUFC); 415 regs_buff[44] = rd32(E1000_WUS); 416 regs_buff[45] = rd32(E1000_IPAV); 417 regs_buff[46] = rd32(E1000_WUPL); 418 419 /* MAC */ 420 regs_buff[47] = rd32(E1000_PCS_CFG0); 421 regs_buff[48] = rd32(E1000_PCS_LCTL); 422 regs_buff[49] = rd32(E1000_PCS_LSTAT); 423 regs_buff[50] = rd32(E1000_PCS_ANADV); 424 regs_buff[51] = rd32(E1000_PCS_LPAB); 425 regs_buff[52] = rd32(E1000_PCS_NPTX); 426 regs_buff[53] = rd32(E1000_PCS_LPABNP); 427 428 /* Statistics */ 429 regs_buff[54] = adapter->stats.crcerrs; 430 regs_buff[55] = adapter->stats.algnerrc; 431 regs_buff[56] = adapter->stats.symerrs; 432 regs_buff[57] = adapter->stats.rxerrc; 433 regs_buff[58] = adapter->stats.mpc; 434 regs_buff[59] = adapter->stats.scc; 435 regs_buff[60] = adapter->stats.ecol; 436 regs_buff[61] = adapter->stats.mcc; 437 regs_buff[62] = adapter->stats.latecol; 438 regs_buff[63] = adapter->stats.colc; 439 regs_buff[64] = adapter->stats.dc; 440 regs_buff[65] = adapter->stats.tncrs; 441 regs_buff[66] = adapter->stats.sec; 442 regs_buff[67] = adapter->stats.htdpmc; 443 regs_buff[68] = adapter->stats.rlec; 444 regs_buff[69] = adapter->stats.xonrxc; 445 regs_buff[70] = adapter->stats.xontxc; 446 regs_buff[71] = adapter->stats.xoffrxc; 447 regs_buff[72] = adapter->stats.xofftxc; 448 regs_buff[73] = adapter->stats.fcruc; 449 regs_buff[74] = adapter->stats.prc64; 450 regs_buff[75] = adapter->stats.prc127; 451 regs_buff[76] = adapter->stats.prc255; 452 regs_buff[77] = adapter->stats.prc511; 453 regs_buff[78] = adapter->stats.prc1023; 454 regs_buff[79] = adapter->stats.prc1522; 455 regs_buff[80] = adapter->stats.gprc; 456 regs_buff[81] = adapter->stats.bprc; 457 regs_buff[82] = adapter->stats.mprc; 458 regs_buff[83] = adapter->stats.gptc; 459 regs_buff[84] = adapter->stats.gorc; 460 regs_buff[86] = adapter->stats.gotc; 461 regs_buff[88] = adapter->stats.rnbc; 462 regs_buff[89] = adapter->stats.ruc; 463 regs_buff[90] = adapter->stats.rfc; 464 regs_buff[91] = adapter->stats.roc; 465 regs_buff[92] = adapter->stats.rjc; 466 regs_buff[93] = adapter->stats.mgprc; 467 regs_buff[94] = adapter->stats.mgpdc; 468 regs_buff[95] = adapter->stats.mgptc; 469 regs_buff[96] = adapter->stats.tor; 470 regs_buff[98] = adapter->stats.tot; 471 regs_buff[100] = adapter->stats.tpr; 472 regs_buff[101] = adapter->stats.tpt; 473 regs_buff[102] = adapter->stats.ptc64; 474 regs_buff[103] = adapter->stats.ptc127; 475 regs_buff[104] = adapter->stats.ptc255; 476 regs_buff[105] = adapter->stats.ptc511; 477 regs_buff[106] = adapter->stats.ptc1023; 478 regs_buff[107] = adapter->stats.ptc1522; 479 regs_buff[108] = adapter->stats.mptc; 480 regs_buff[109] = adapter->stats.bptc; 481 regs_buff[110] = adapter->stats.tsctc; 482 regs_buff[111] = adapter->stats.iac; 483 regs_buff[112] = adapter->stats.rpthc; 484 regs_buff[113] = adapter->stats.hgptc; 485 regs_buff[114] = adapter->stats.hgorc; 486 regs_buff[116] = adapter->stats.hgotc; 487 regs_buff[118] = adapter->stats.lenerrs; 488 regs_buff[119] = adapter->stats.scvpc; 489 regs_buff[120] = adapter->stats.hrmpc; 490 491 for (i = 0; i < 4; i++) 492 regs_buff[121 + i] = rd32(E1000_SRRCTL(i)); 493 for (i = 0; i < 4; i++) 494 regs_buff[125 + i] = rd32(E1000_PSRTYPE(i)); 495 for (i = 0; i < 4; i++) 496 regs_buff[129 + i] = rd32(E1000_RDBAL(i)); 497 for (i = 0; i < 4; i++) 498 regs_buff[133 + i] = rd32(E1000_RDBAH(i)); 499 for (i = 0; i < 4; i++) 500 regs_buff[137 + i] = rd32(E1000_RDLEN(i)); 501 for (i = 0; i < 4; i++) 502 regs_buff[141 + i] = rd32(E1000_RDH(i)); 503 for (i = 0; i < 4; i++) 504 regs_buff[145 + i] = rd32(E1000_RDT(i)); 505 for (i = 0; i < 4; i++) 506 regs_buff[149 + i] = rd32(E1000_RXDCTL(i)); 507 508 for (i = 0; i < 10; i++) 509 regs_buff[153 + i] = rd32(E1000_EITR(i)); 510 for (i = 0; i < 8; i++) 511 regs_buff[163 + i] = rd32(E1000_IMIR(i)); 512 for (i = 0; i < 8; i++) 513 regs_buff[171 + i] = rd32(E1000_IMIREXT(i)); 514 for (i = 0; i < 16; i++) 515 regs_buff[179 + i] = rd32(E1000_RAL(i)); 516 for (i = 0; i < 16; i++) 517 regs_buff[195 + i] = rd32(E1000_RAH(i)); 518 519 for (i = 0; i < 4; i++) 520 regs_buff[211 + i] = rd32(E1000_TDBAL(i)); 521 for (i = 0; i < 4; i++) 522 regs_buff[215 + i] = rd32(E1000_TDBAH(i)); 523 for (i = 0; i < 4; i++) 524 regs_buff[219 + i] = rd32(E1000_TDLEN(i)); 525 for (i = 0; i < 4; i++) 526 regs_buff[223 + i] = rd32(E1000_TDH(i)); 527 for (i = 0; i < 4; i++) 528 regs_buff[227 + i] = rd32(E1000_TDT(i)); 529 for (i = 0; i < 4; i++) 530 regs_buff[231 + i] = rd32(E1000_TXDCTL(i)); 531 for (i = 0; i < 4; i++) 532 regs_buff[235 + i] = rd32(E1000_TDWBAL(i)); 533 for (i = 0; i < 4; i++) 534 regs_buff[239 + i] = rd32(E1000_TDWBAH(i)); 535 for (i = 0; i < 4; i++) 536 regs_buff[243 + i] = rd32(E1000_DCA_TXCTRL(i)); 537 538 for (i = 0; i < 4; i++) 539 regs_buff[247 + i] = rd32(E1000_IP4AT_REG(i)); 540 for (i = 0; i < 4; i++) 541 regs_buff[251 + i] = rd32(E1000_IP6AT_REG(i)); 542 for (i = 0; i < 32; i++) 543 regs_buff[255 + i] = rd32(E1000_WUPM_REG(i)); 544 for (i = 0; i < 128; i++) 545 regs_buff[287 + i] = rd32(E1000_FFMT_REG(i)); 546 for (i = 0; i < 128; i++) 547 regs_buff[415 + i] = rd32(E1000_FFVT_REG(i)); 548 for (i = 0; i < 4; i++) 549 regs_buff[543 + i] = rd32(E1000_FFLT_REG(i)); 550 551 regs_buff[547] = rd32(E1000_TDFH); 552 regs_buff[548] = rd32(E1000_TDFT); 553 regs_buff[549] = rd32(E1000_TDFHS); 554 regs_buff[550] = rd32(E1000_TDFPC); 555 556 if (hw->mac.type > e1000_82580) { 557 regs_buff[551] = adapter->stats.o2bgptc; 558 regs_buff[552] = adapter->stats.b2ospc; 559 regs_buff[553] = adapter->stats.o2bspc; 560 regs_buff[554] = adapter->stats.b2ogprc; 561 } 562 563 if (hw->mac.type != e1000_82576) 564 return; 565 for (i = 0; i < 12; i++) 566 regs_buff[555 + i] = rd32(E1000_SRRCTL(i + 4)); 567 for (i = 0; i < 4; i++) 568 regs_buff[567 + i] = rd32(E1000_PSRTYPE(i + 4)); 569 for (i = 0; i < 12; i++) 570 regs_buff[571 + i] = rd32(E1000_RDBAL(i + 4)); 571 for (i = 0; i < 12; i++) 572 regs_buff[583 + i] = rd32(E1000_RDBAH(i + 4)); 573 for (i = 0; i < 12; i++) 574 regs_buff[595 + i] = rd32(E1000_RDLEN(i + 4)); 575 for (i = 0; i < 12; i++) 576 regs_buff[607 + i] = rd32(E1000_RDH(i + 4)); 577 for (i = 0; i < 12; i++) 578 regs_buff[619 + i] = rd32(E1000_RDT(i + 4)); 579 for (i = 0; i < 12; i++) 580 regs_buff[631 + i] = rd32(E1000_RXDCTL(i + 4)); 581 582 for (i = 0; i < 12; i++) 583 regs_buff[643 + i] = rd32(E1000_TDBAL(i + 4)); 584 for (i = 0; i < 12; i++) 585 regs_buff[655 + i] = rd32(E1000_TDBAH(i + 4)); 586 for (i = 0; i < 12; i++) 587 regs_buff[667 + i] = rd32(E1000_TDLEN(i + 4)); 588 for (i = 0; i < 12; i++) 589 regs_buff[679 + i] = rd32(E1000_TDH(i + 4)); 590 for (i = 0; i < 12; i++) 591 regs_buff[691 + i] = rd32(E1000_TDT(i + 4)); 592 for (i = 0; i < 12; i++) 593 regs_buff[703 + i] = rd32(E1000_TXDCTL(i + 4)); 594 for (i = 0; i < 12; i++) 595 regs_buff[715 + i] = rd32(E1000_TDWBAL(i + 4)); 596 for (i = 0; i < 12; i++) 597 regs_buff[727 + i] = rd32(E1000_TDWBAH(i + 4)); 598} 599 600static int igb_get_eeprom_len(struct net_device *netdev) 601{ 602 struct igb_adapter *adapter = netdev_priv(netdev); 603 return adapter->hw.nvm.word_size * 2; 604} 605 606static int igb_get_eeprom(struct net_device *netdev, 607 struct ethtool_eeprom *eeprom, u8 *bytes) 608{ 609 struct igb_adapter *adapter = netdev_priv(netdev); 610 struct e1000_hw *hw = &adapter->hw; 611 u16 *eeprom_buff; 612 int first_word, last_word; 613 int ret_val = 0; 614 u16 i; 615 616 if (eeprom->len == 0) 617 return -EINVAL; 618 619 eeprom->magic = hw->vendor_id | (hw->device_id << 16); 620 621 first_word = eeprom->offset >> 1; 622 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 623 624 eeprom_buff = kmalloc(sizeof(u16) * 625 (last_word - first_word + 1), GFP_KERNEL); 626 if (!eeprom_buff) 627 return -ENOMEM; 628 629 if (hw->nvm.type == e1000_nvm_eeprom_spi) 630 ret_val = hw->nvm.ops.read(hw, first_word, 631 last_word - first_word + 1, 632 eeprom_buff); 633 else { 634 for (i = 0; i < last_word - first_word + 1; i++) { 635 ret_val = hw->nvm.ops.read(hw, first_word + i, 1, 636 &eeprom_buff[i]); 637 if (ret_val) 638 break; 639 } 640 } 641 642 /* Device's eeprom is always little-endian, word addressable */ 643 for (i = 0; i < last_word - first_word + 1; i++) 644 le16_to_cpus(&eeprom_buff[i]); 645 646 memcpy(bytes, (u8 *)eeprom_buff + (eeprom->offset & 1), 647 eeprom->len); 648 kfree(eeprom_buff); 649 650 return ret_val; 651} 652 653static int igb_set_eeprom(struct net_device *netdev, 654 struct ethtool_eeprom *eeprom, u8 *bytes) 655{ 656 struct igb_adapter *adapter = netdev_priv(netdev); 657 struct e1000_hw *hw = &adapter->hw; 658 u16 *eeprom_buff; 659 void *ptr; 660 int max_len, first_word, last_word, ret_val = 0; 661 u16 i; 662 663 if (eeprom->len == 0) 664 return -EOPNOTSUPP; 665 666 if (hw->mac.type == e1000_i211) 667 return -EOPNOTSUPP; 668 669 if (eeprom->magic != (hw->vendor_id | (hw->device_id << 16))) 670 return -EFAULT; 671 672 max_len = hw->nvm.word_size * 2; 673 674 first_word = eeprom->offset >> 1; 675 last_word = (eeprom->offset + eeprom->len - 1) >> 1; 676 eeprom_buff = kmalloc(max_len, GFP_KERNEL); 677 if (!eeprom_buff) 678 return -ENOMEM; 679 680 ptr = (void *)eeprom_buff; 681 682 if (eeprom->offset & 1) { 683 /* need read/modify/write of first changed EEPROM word */ 684 /* only the second byte of the word is being modified */ 685 ret_val = hw->nvm.ops.read(hw, first_word, 1, 686 &eeprom_buff[0]); 687 ptr++; 688 } 689 if (((eeprom->offset + eeprom->len) & 1) && (ret_val == 0)) { 690 /* need read/modify/write of last changed EEPROM word */ 691 /* only the first byte of the word is being modified */ 692 ret_val = hw->nvm.ops.read(hw, last_word, 1, 693 &eeprom_buff[last_word - first_word]); 694 } 695 696 /* Device's eeprom is always little-endian, word addressable */ 697 for (i = 0; i < last_word - first_word + 1; i++) 698 le16_to_cpus(&eeprom_buff[i]); 699 700 memcpy(ptr, bytes, eeprom->len); 701 702 for (i = 0; i < last_word - first_word + 1; i++) 703 eeprom_buff[i] = cpu_to_le16(eeprom_buff[i]); 704 705 ret_val = hw->nvm.ops.write(hw, first_word, 706 last_word - first_word + 1, eeprom_buff); 707 708 /* Update the checksum over the first part of the EEPROM if needed 709 * and flush shadow RAM for 82573 controllers */ 710 if ((ret_val == 0) && ((first_word <= NVM_CHECKSUM_REG))) 711 hw->nvm.ops.update(hw); 712 713 igb_set_fw_version(adapter); 714 kfree(eeprom_buff); 715 return ret_val; 716} 717 718static void igb_get_drvinfo(struct net_device *netdev, 719 struct ethtool_drvinfo *drvinfo) 720{ 721 struct igb_adapter *adapter = netdev_priv(netdev); 722 723 strlcpy(drvinfo->driver, igb_driver_name, sizeof(drvinfo->driver)); 724 strlcpy(drvinfo->version, igb_driver_version, sizeof(drvinfo->version)); 725 726 /* 727 * EEPROM image version # is reported as firmware version # for 728 * 82575 controllers 729 */ 730 strlcpy(drvinfo->fw_version, adapter->fw_version, 731 sizeof(drvinfo->fw_version)); 732 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev), 733 sizeof(drvinfo->bus_info)); 734 drvinfo->n_stats = IGB_STATS_LEN; 735 drvinfo->testinfo_len = IGB_TEST_LEN; 736 drvinfo->regdump_len = igb_get_regs_len(netdev); 737 drvinfo->eedump_len = igb_get_eeprom_len(netdev); 738} 739 740static void igb_get_ringparam(struct net_device *netdev, 741 struct ethtool_ringparam *ring) 742{ 743 struct igb_adapter *adapter = netdev_priv(netdev); 744 745 ring->rx_max_pending = IGB_MAX_RXD; 746 ring->tx_max_pending = IGB_MAX_TXD; 747 ring->rx_pending = adapter->rx_ring_count; 748 ring->tx_pending = adapter->tx_ring_count; 749} 750 751static int igb_set_ringparam(struct net_device *netdev, 752 struct ethtool_ringparam *ring) 753{ 754 struct igb_adapter *adapter = netdev_priv(netdev); 755 struct igb_ring *temp_ring; 756 int i, err = 0; 757 u16 new_rx_count, new_tx_count; 758 759 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending)) 760 return -EINVAL; 761 762 new_rx_count = min_t(u32, ring->rx_pending, IGB_MAX_RXD); 763 new_rx_count = max_t(u16, new_rx_count, IGB_MIN_RXD); 764 new_rx_count = ALIGN(new_rx_count, REQ_RX_DESCRIPTOR_MULTIPLE); 765 766 new_tx_count = min_t(u32, ring->tx_pending, IGB_MAX_TXD); 767 new_tx_count = max_t(u16, new_tx_count, IGB_MIN_TXD); 768 new_tx_count = ALIGN(new_tx_count, REQ_TX_DESCRIPTOR_MULTIPLE); 769 770 if ((new_tx_count == adapter->tx_ring_count) && 771 (new_rx_count == adapter->rx_ring_count)) { 772 /* nothing to do */ 773 return 0; 774 } 775 776 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 777 msleep(1); 778 779 if (!netif_running(adapter->netdev)) { 780 for (i = 0; i < adapter->num_tx_queues; i++) 781 adapter->tx_ring[i]->count = new_tx_count; 782 for (i = 0; i < adapter->num_rx_queues; i++) 783 adapter->rx_ring[i]->count = new_rx_count; 784 adapter->tx_ring_count = new_tx_count; 785 adapter->rx_ring_count = new_rx_count; 786 goto clear_reset; 787 } 788 789 if (adapter->num_tx_queues > adapter->num_rx_queues) 790 temp_ring = vmalloc(adapter->num_tx_queues * sizeof(struct igb_ring)); 791 else 792 temp_ring = vmalloc(adapter->num_rx_queues * sizeof(struct igb_ring)); 793 794 if (!temp_ring) { 795 err = -ENOMEM; 796 goto clear_reset; 797 } 798 799 igb_down(adapter); 800 801 /* 802 * We can't just free everything and then setup again, 803 * because the ISRs in MSI-X mode get passed pointers 804 * to the tx and rx ring structs. 805 */ 806 if (new_tx_count != adapter->tx_ring_count) { 807 for (i = 0; i < adapter->num_tx_queues; i++) { 808 memcpy(&temp_ring[i], adapter->tx_ring[i], 809 sizeof(struct igb_ring)); 810 811 temp_ring[i].count = new_tx_count; 812 err = igb_setup_tx_resources(&temp_ring[i]); 813 if (err) { 814 while (i) { 815 i--; 816 igb_free_tx_resources(&temp_ring[i]); 817 } 818 goto err_setup; 819 } 820 } 821 822 for (i = 0; i < adapter->num_tx_queues; i++) { 823 igb_free_tx_resources(adapter->tx_ring[i]); 824 825 memcpy(adapter->tx_ring[i], &temp_ring[i], 826 sizeof(struct igb_ring)); 827 } 828 829 adapter->tx_ring_count = new_tx_count; 830 } 831 832 if (new_rx_count != adapter->rx_ring_count) { 833 for (i = 0; i < adapter->num_rx_queues; i++) { 834 memcpy(&temp_ring[i], adapter->rx_ring[i], 835 sizeof(struct igb_ring)); 836 837 temp_ring[i].count = new_rx_count; 838 err = igb_setup_rx_resources(&temp_ring[i]); 839 if (err) { 840 while (i) { 841 i--; 842 igb_free_rx_resources(&temp_ring[i]); 843 } 844 goto err_setup; 845 } 846 847 } 848 849 for (i = 0; i < adapter->num_rx_queues; i++) { 850 igb_free_rx_resources(adapter->rx_ring[i]); 851 852 memcpy(adapter->rx_ring[i], &temp_ring[i], 853 sizeof(struct igb_ring)); 854 } 855 856 adapter->rx_ring_count = new_rx_count; 857 } 858err_setup: 859 igb_up(adapter); 860 vfree(temp_ring); 861clear_reset: 862 clear_bit(__IGB_RESETTING, &adapter->state); 863 return err; 864} 865 866/* ethtool register test data */ 867struct igb_reg_test { 868 u16 reg; 869 u16 reg_offset; 870 u16 array_len; 871 u16 test_type; 872 u32 mask; 873 u32 write; 874}; 875 876/* In the hardware, registers are laid out either singly, in arrays 877 * spaced 0x100 bytes apart, or in contiguous tables. We assume 878 * most tests take place on arrays or single registers (handled 879 * as a single-element array) and special-case the tables. 880 * Table tests are always pattern tests. 881 * 882 * We also make provision for some required setup steps by specifying 883 * registers to be written without any read-back testing. 884 */ 885 886#define PATTERN_TEST 1 887#define SET_READ_TEST 2 888#define WRITE_NO_TEST 3 889#define TABLE32_TEST 4 890#define TABLE64_TEST_LO 5 891#define TABLE64_TEST_HI 6 892 893/* i210 reg test */ 894static struct igb_reg_test reg_test_i210[] = { 895 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 896 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 897 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 898 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 899 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 900 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 901 /* RDH is read-only for i210, only test RDT. */ 902 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 903 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 904 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 905 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 906 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 907 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 908 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 909 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 910 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 911 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 912 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 913 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 914 { E1000_RA, 0, 16, TABLE64_TEST_LO, 915 0xFFFFFFFF, 0xFFFFFFFF }, 916 { E1000_RA, 0, 16, TABLE64_TEST_HI, 917 0x900FFFFF, 0xFFFFFFFF }, 918 { E1000_MTA, 0, 128, TABLE32_TEST, 919 0xFFFFFFFF, 0xFFFFFFFF }, 920 { 0, 0, 0, 0, 0 } 921}; 922 923/* i350 reg test */ 924static struct igb_reg_test reg_test_i350[] = { 925 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 926 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 927 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 928 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFF0000, 0xFFFF0000 }, 929 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 930 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 931 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 932 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 933 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 934 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 935 /* RDH is read-only for i350, only test RDT. */ 936 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 937 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 938 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 939 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 940 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 941 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 942 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 943 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 944 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 945 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 946 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 947 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 948 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 949 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 950 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 951 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 952 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 953 { E1000_RA, 0, 16, TABLE64_TEST_LO, 954 0xFFFFFFFF, 0xFFFFFFFF }, 955 { E1000_RA, 0, 16, TABLE64_TEST_HI, 956 0xC3FFFFFF, 0xFFFFFFFF }, 957 { E1000_RA2, 0, 16, TABLE64_TEST_LO, 958 0xFFFFFFFF, 0xFFFFFFFF }, 959 { E1000_RA2, 0, 16, TABLE64_TEST_HI, 960 0xC3FFFFFF, 0xFFFFFFFF }, 961 { E1000_MTA, 0, 128, TABLE32_TEST, 962 0xFFFFFFFF, 0xFFFFFFFF }, 963 { 0, 0, 0, 0 } 964}; 965 966/* 82580 reg test */ 967static struct igb_reg_test reg_test_82580[] = { 968 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 969 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 970 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 971 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 972 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 973 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 974 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 975 { E1000_RDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 976 { E1000_RDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 977 { E1000_RDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 978 /* RDH is read-only for 82580, only test RDT. */ 979 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 980 { E1000_RDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 981 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 982 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 983 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 984 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 985 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 986 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 987 { E1000_TDBAL(4), 0x40, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 988 { E1000_TDBAH(4), 0x40, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 989 { E1000_TDLEN(4), 0x40, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 990 { E1000_TDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 991 { E1000_TDT(4), 0x40, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 992 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 993 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 994 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 995 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 996 { E1000_RA, 0, 16, TABLE64_TEST_LO, 997 0xFFFFFFFF, 0xFFFFFFFF }, 998 { E1000_RA, 0, 16, TABLE64_TEST_HI, 999 0x83FFFFFF, 0xFFFFFFFF }, 1000 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 1001 0xFFFFFFFF, 0xFFFFFFFF }, 1002 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 1003 0x83FFFFFF, 0xFFFFFFFF }, 1004 { E1000_MTA, 0, 128, TABLE32_TEST, 1005 0xFFFFFFFF, 0xFFFFFFFF }, 1006 { 0, 0, 0, 0 } 1007}; 1008 1009/* 82576 reg test */ 1010static struct igb_reg_test reg_test_82576[] = { 1011 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1012 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1013 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1014 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1015 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1016 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1017 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1018 { E1000_RDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1019 { E1000_RDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1020 { E1000_RDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1021 /* Enable all RX queues before testing. */ 1022 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, 1023 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, 1024 /* RDH is read-only for 82576, only test RDT. */ 1025 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1026 { E1000_RDT(4), 0x40, 12, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1027 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1028 { E1000_RXDCTL(4), 0x40, 12, WRITE_NO_TEST, 0, 0 }, 1029 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1030 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1031 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1032 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1033 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1034 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1035 { E1000_TDBAL(4), 0x40, 12, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1036 { E1000_TDBAH(4), 0x40, 12, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1037 { E1000_TDLEN(4), 0x40, 12, PATTERN_TEST, 0x000FFFF0, 0x000FFFFF }, 1038 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1039 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0x003FFFFB }, 1040 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB0FE, 0xFFFFFFFF }, 1041 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1042 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1043 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1044 { E1000_RA2, 0, 8, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1045 { E1000_RA2, 0, 8, TABLE64_TEST_HI, 0x83FFFFFF, 0xFFFFFFFF }, 1046 { E1000_MTA, 0, 128,TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1047 { 0, 0, 0, 0 } 1048}; 1049 1050/* 82575 register test */ 1051static struct igb_reg_test reg_test_82575[] = { 1052 { E1000_FCAL, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1053 { E1000_FCAH, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1054 { E1000_FCT, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0xFFFFFFFF }, 1055 { E1000_VET, 0x100, 1, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1056 { E1000_RDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1057 { E1000_RDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1058 { E1000_RDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1059 /* Enable all four RX queues before testing. */ 1060 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, E1000_RXDCTL_QUEUE_ENABLE }, 1061 /* RDH is read-only for 82575, only test RDT. */ 1062 { E1000_RDT(0), 0x100, 4, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1063 { E1000_RXDCTL(0), 0x100, 4, WRITE_NO_TEST, 0, 0 }, 1064 { E1000_FCRTH, 0x100, 1, PATTERN_TEST, 0x0000FFF0, 0x0000FFF0 }, 1065 { E1000_FCTTV, 0x100, 1, PATTERN_TEST, 0x0000FFFF, 0x0000FFFF }, 1066 { E1000_TIPG, 0x100, 1, PATTERN_TEST, 0x3FFFFFFF, 0x3FFFFFFF }, 1067 { E1000_TDBAL(0), 0x100, 4, PATTERN_TEST, 0xFFFFFF80, 0xFFFFFFFF }, 1068 { E1000_TDBAH(0), 0x100, 4, PATTERN_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1069 { E1000_TDLEN(0), 0x100, 4, PATTERN_TEST, 0x000FFF80, 0x000FFFFF }, 1070 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1071 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0x003FFFFB }, 1072 { E1000_RCTL, 0x100, 1, SET_READ_TEST, 0x04CFB3FE, 0xFFFFFFFF }, 1073 { E1000_TCTL, 0x100, 1, SET_READ_TEST, 0xFFFFFFFF, 0x00000000 }, 1074 { E1000_TXCW, 0x100, 1, PATTERN_TEST, 0xC000FFFF, 0x0000FFFF }, 1075 { E1000_RA, 0, 16, TABLE64_TEST_LO, 0xFFFFFFFF, 0xFFFFFFFF }, 1076 { E1000_RA, 0, 16, TABLE64_TEST_HI, 0x800FFFFF, 0xFFFFFFFF }, 1077 { E1000_MTA, 0, 128, TABLE32_TEST, 0xFFFFFFFF, 0xFFFFFFFF }, 1078 { 0, 0, 0, 0 } 1079}; 1080 1081static bool reg_pattern_test(struct igb_adapter *adapter, u64 *data, 1082 int reg, u32 mask, u32 write) 1083{ 1084 struct e1000_hw *hw = &adapter->hw; 1085 u32 pat, val; 1086 static const u32 _test[] = 1087 {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF}; 1088 for (pat = 0; pat < ARRAY_SIZE(_test); pat++) { 1089 wr32(reg, (_test[pat] & write)); 1090 val = rd32(reg) & mask; 1091 if (val != (_test[pat] & write & mask)) { 1092 dev_err(&adapter->pdev->dev, 1093 "pattern test reg %04X failed: got 0x%08X expected 0x%08X\n", 1094 reg, val, (_test[pat] & write & mask)); 1095 *data = reg; 1096 return 1; 1097 } 1098 } 1099 1100 return 0; 1101} 1102 1103static bool reg_set_and_check(struct igb_adapter *adapter, u64 *data, 1104 int reg, u32 mask, u32 write) 1105{ 1106 struct e1000_hw *hw = &adapter->hw; 1107 u32 val; 1108 wr32(reg, write & mask); 1109 val = rd32(reg); 1110 if ((write & mask) != (val & mask)) { 1111 dev_err(&adapter->pdev->dev, 1112 "set/check reg %04X test failed: got 0x%08X expected 0x%08X\n", reg, 1113 (val & mask), (write & mask)); 1114 *data = reg; 1115 return 1; 1116 } 1117 1118 return 0; 1119} 1120 1121#define REG_PATTERN_TEST(reg, mask, write) \ 1122 do { \ 1123 if (reg_pattern_test(adapter, data, reg, mask, write)) \ 1124 return 1; \ 1125 } while (0) 1126 1127#define REG_SET_AND_CHECK(reg, mask, write) \ 1128 do { \ 1129 if (reg_set_and_check(adapter, data, reg, mask, write)) \ 1130 return 1; \ 1131 } while (0) 1132 1133static int igb_reg_test(struct igb_adapter *adapter, u64 *data) 1134{ 1135 struct e1000_hw *hw = &adapter->hw; 1136 struct igb_reg_test *test; 1137 u32 value, before, after; 1138 u32 i, toggle; 1139 1140 switch (adapter->hw.mac.type) { 1141 case e1000_i350: 1142 test = reg_test_i350; 1143 toggle = 0x7FEFF3FF; 1144 break; 1145 case e1000_i210: 1146 case e1000_i211: 1147 test = reg_test_i210; 1148 toggle = 0x7FEFF3FF; 1149 break; 1150 case e1000_82580: 1151 test = reg_test_82580; 1152 toggle = 0x7FEFF3FF; 1153 break; 1154 case e1000_82576: 1155 test = reg_test_82576; 1156 toggle = 0x7FFFF3FF; 1157 break; 1158 default: 1159 test = reg_test_82575; 1160 toggle = 0x7FFFF3FF; 1161 break; 1162 } 1163 1164 /* Because the status register is such a special case, 1165 * we handle it separately from the rest of the register 1166 * tests. Some bits are read-only, some toggle, and some 1167 * are writable on newer MACs. 1168 */ 1169 before = rd32(E1000_STATUS); 1170 value = (rd32(E1000_STATUS) & toggle); 1171 wr32(E1000_STATUS, toggle); 1172 after = rd32(E1000_STATUS) & toggle; 1173 if (value != after) { 1174 dev_err(&adapter->pdev->dev, 1175 "failed STATUS register test got: 0x%08X expected: 0x%08X\n", 1176 after, value); 1177 *data = 1; 1178 return 1; 1179 } 1180 /* restore previous status */ 1181 wr32(E1000_STATUS, before); 1182 1183 /* Perform the remainder of the register test, looping through 1184 * the test table until we either fail or reach the null entry. 1185 */ 1186 while (test->reg) { 1187 for (i = 0; i < test->array_len; i++) { 1188 switch (test->test_type) { 1189 case PATTERN_TEST: 1190 REG_PATTERN_TEST(test->reg + 1191 (i * test->reg_offset), 1192 test->mask, 1193 test->write); 1194 break; 1195 case SET_READ_TEST: 1196 REG_SET_AND_CHECK(test->reg + 1197 (i * test->reg_offset), 1198 test->mask, 1199 test->write); 1200 break; 1201 case WRITE_NO_TEST: 1202 writel(test->write, 1203 (adapter->hw.hw_addr + test->reg) 1204 + (i * test->reg_offset)); 1205 break; 1206 case TABLE32_TEST: 1207 REG_PATTERN_TEST(test->reg + (i * 4), 1208 test->mask, 1209 test->write); 1210 break; 1211 case TABLE64_TEST_LO: 1212 REG_PATTERN_TEST(test->reg + (i * 8), 1213 test->mask, 1214 test->write); 1215 break; 1216 case TABLE64_TEST_HI: 1217 REG_PATTERN_TEST((test->reg + 4) + (i * 8), 1218 test->mask, 1219 test->write); 1220 break; 1221 } 1222 } 1223 test++; 1224 } 1225 1226 *data = 0; 1227 return 0; 1228} 1229 1230static int igb_eeprom_test(struct igb_adapter *adapter, u64 *data) 1231{ 1232 *data = 0; 1233 1234 /* Validate eeprom on all parts but i211 */ 1235 if (adapter->hw.mac.type != e1000_i211) { 1236 if (adapter->hw.nvm.ops.validate(&adapter->hw) < 0) 1237 *data = 2; 1238 } 1239 1240 return *data; 1241} 1242 1243static irqreturn_t igb_test_intr(int irq, void *data) 1244{ 1245 struct igb_adapter *adapter = (struct igb_adapter *) data; 1246 struct e1000_hw *hw = &adapter->hw; 1247 1248 adapter->test_icr |= rd32(E1000_ICR); 1249 1250 return IRQ_HANDLED; 1251} 1252 1253static int igb_intr_test(struct igb_adapter *adapter, u64 *data) 1254{ 1255 struct e1000_hw *hw = &adapter->hw; 1256 struct net_device *netdev = adapter->netdev; 1257 u32 mask, ics_mask, i = 0, shared_int = true; 1258 u32 irq = adapter->pdev->irq; 1259 1260 *data = 0; 1261 1262 /* Hook up test interrupt handler just for this test */ 1263 if (adapter->msix_entries) { 1264 if (request_irq(adapter->msix_entries[0].vector, 1265 igb_test_intr, 0, netdev->name, adapter)) { 1266 *data = 1; 1267 return -1; 1268 } 1269 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 1270 shared_int = false; 1271 if (request_irq(irq, 1272 igb_test_intr, 0, netdev->name, adapter)) { 1273 *data = 1; 1274 return -1; 1275 } 1276 } else if (!request_irq(irq, igb_test_intr, IRQF_PROBE_SHARED, 1277 netdev->name, adapter)) { 1278 shared_int = false; 1279 } else if (request_irq(irq, igb_test_intr, IRQF_SHARED, 1280 netdev->name, adapter)) { 1281 *data = 1; 1282 return -1; 1283 } 1284 dev_info(&adapter->pdev->dev, "testing %s interrupt\n", 1285 (shared_int ? "shared" : "unshared")); 1286 1287 /* Disable all the interrupts */ 1288 wr32(E1000_IMC, ~0); 1289 wrfl(); 1290 msleep(10); 1291 1292 /* Define all writable bits for ICS */ 1293 switch (hw->mac.type) { 1294 case e1000_82575: 1295 ics_mask = 0x37F47EDD; 1296 break; 1297 case e1000_82576: 1298 ics_mask = 0x77D4FBFD; 1299 break; 1300 case e1000_82580: 1301 ics_mask = 0x77DCFED5; 1302 break; 1303 case e1000_i350: 1304 case e1000_i210: 1305 case e1000_i211: 1306 ics_mask = 0x77DCFED5; 1307 break; 1308 default: 1309 ics_mask = 0x7FFFFFFF; 1310 break; 1311 } 1312 1313 /* Test each interrupt */ 1314 for (; i < 31; i++) { 1315 /* Interrupt to test */ 1316 mask = 1 << i; 1317 1318 if (!(mask & ics_mask)) 1319 continue; 1320 1321 if (!shared_int) { 1322 /* Disable the interrupt to be reported in 1323 * the cause register and then force the same 1324 * interrupt and see if one gets posted. If 1325 * an interrupt was posted to the bus, the 1326 * test failed. 1327 */ 1328 adapter->test_icr = 0; 1329 1330 /* Flush any pending interrupts */ 1331 wr32(E1000_ICR, ~0); 1332 1333 wr32(E1000_IMC, mask); 1334 wr32(E1000_ICS, mask); 1335 wrfl(); 1336 msleep(10); 1337 1338 if (adapter->test_icr & mask) { 1339 *data = 3; 1340 break; 1341 } 1342 } 1343 1344 /* Enable the interrupt to be reported in 1345 * the cause register and then force the same 1346 * interrupt and see if one gets posted. If 1347 * an interrupt was not posted to the bus, the 1348 * test failed. 1349 */ 1350 adapter->test_icr = 0; 1351 1352 /* Flush any pending interrupts */ 1353 wr32(E1000_ICR, ~0); 1354 1355 wr32(E1000_IMS, mask); 1356 wr32(E1000_ICS, mask); 1357 wrfl(); 1358 msleep(10); 1359 1360 if (!(adapter->test_icr & mask)) { 1361 *data = 4; 1362 break; 1363 } 1364 1365 if (!shared_int) { 1366 /* Disable the other interrupts to be reported in 1367 * the cause register and then force the other 1368 * interrupts and see if any get posted. If 1369 * an interrupt was posted to the bus, the 1370 * test failed. 1371 */ 1372 adapter->test_icr = 0; 1373 1374 /* Flush any pending interrupts */ 1375 wr32(E1000_ICR, ~0); 1376 1377 wr32(E1000_IMC, ~mask); 1378 wr32(E1000_ICS, ~mask); 1379 wrfl(); 1380 msleep(10); 1381 1382 if (adapter->test_icr & mask) { 1383 *data = 5; 1384 break; 1385 } 1386 } 1387 } 1388 1389 /* Disable all the interrupts */ 1390 wr32(E1000_IMC, ~0); 1391 wrfl(); 1392 msleep(10); 1393 1394 /* Unhook test interrupt handler */ 1395 if (adapter->msix_entries) 1396 free_irq(adapter->msix_entries[0].vector, adapter); 1397 else 1398 free_irq(irq, adapter); 1399 1400 return *data; 1401} 1402 1403static void igb_free_desc_rings(struct igb_adapter *adapter) 1404{ 1405 igb_free_tx_resources(&adapter->test_tx_ring); 1406 igb_free_rx_resources(&adapter->test_rx_ring); 1407} 1408 1409static int igb_setup_desc_rings(struct igb_adapter *adapter) 1410{ 1411 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1412 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1413 struct e1000_hw *hw = &adapter->hw; 1414 int ret_val; 1415 1416 /* Setup Tx descriptor ring and Tx buffers */ 1417 tx_ring->count = IGB_DEFAULT_TXD; 1418 tx_ring->dev = &adapter->pdev->dev; 1419 tx_ring->netdev = adapter->netdev; 1420 tx_ring->reg_idx = adapter->vfs_allocated_count; 1421 1422 if (igb_setup_tx_resources(tx_ring)) { 1423 ret_val = 1; 1424 goto err_nomem; 1425 } 1426 1427 igb_setup_tctl(adapter); 1428 igb_configure_tx_ring(adapter, tx_ring); 1429 1430 /* Setup Rx descriptor ring and Rx buffers */ 1431 rx_ring->count = IGB_DEFAULT_RXD; 1432 rx_ring->dev = &adapter->pdev->dev; 1433 rx_ring->netdev = adapter->netdev; 1434 rx_ring->reg_idx = adapter->vfs_allocated_count; 1435 1436 if (igb_setup_rx_resources(rx_ring)) { 1437 ret_val = 3; 1438 goto err_nomem; 1439 } 1440 1441 /* set the default queue to queue 0 of PF */ 1442 wr32(E1000_MRQC, adapter->vfs_allocated_count << 3); 1443 1444 /* enable receive ring */ 1445 igb_setup_rctl(adapter); 1446 igb_configure_rx_ring(adapter, rx_ring); 1447 1448 igb_alloc_rx_buffers(rx_ring, igb_desc_unused(rx_ring)); 1449 1450 return 0; 1451 1452err_nomem: 1453 igb_free_desc_rings(adapter); 1454 return ret_val; 1455} 1456 1457static void igb_phy_disable_receiver(struct igb_adapter *adapter) 1458{ 1459 struct e1000_hw *hw = &adapter->hw; 1460 1461 /* Write out to PHY registers 29 and 30 to disable the Receiver. */ 1462 igb_write_phy_reg(hw, 29, 0x001F); 1463 igb_write_phy_reg(hw, 30, 0x8FFC); 1464 igb_write_phy_reg(hw, 29, 0x001A); 1465 igb_write_phy_reg(hw, 30, 0x8FF0); 1466} 1467 1468static int igb_integrated_phy_loopback(struct igb_adapter *adapter) 1469{ 1470 struct e1000_hw *hw = &adapter->hw; 1471 u32 ctrl_reg = 0; 1472 u16 phy_reg = 0; 1473 1474 hw->mac.autoneg = false; 1475 1476 switch (hw->phy.type) { 1477 case e1000_phy_m88: 1478 /* Auto-MDI/MDIX Off */ 1479 igb_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, 0x0808); 1480 /* reset to update Auto-MDI/MDIX */ 1481 igb_write_phy_reg(hw, PHY_CONTROL, 0x9140); 1482 /* autoneg off */ 1483 igb_write_phy_reg(hw, PHY_CONTROL, 0x8140); 1484 break; 1485 case e1000_phy_82580: 1486 /* enable MII loopback */ 1487 igb_write_phy_reg(hw, I82580_PHY_LBK_CTRL, 0x8041); 1488 break; 1489 case e1000_phy_i210: 1490 /* set loopback speed in PHY */ 1491 igb_read_phy_reg(hw, (GS40G_PAGE_SELECT & GS40G_PAGE_2), 1492 &phy_reg); 1493 phy_reg |= GS40G_MAC_SPEED_1G; 1494 igb_write_phy_reg(hw, (GS40G_PAGE_SELECT & GS40G_PAGE_2), 1495 phy_reg); 1496 ctrl_reg = rd32(E1000_CTRL_EXT); 1497 default: 1498 break; 1499 } 1500 1501 /* force 1000, set loopback */ 1502 igb_write_phy_reg(hw, PHY_CONTROL, 0x4140); 1503 1504 /* Now set up the MAC to the same speed/duplex as the PHY. */ 1505 ctrl_reg = rd32(E1000_CTRL); 1506 ctrl_reg &= ~E1000_CTRL_SPD_SEL; /* Clear the speed sel bits */ 1507 ctrl_reg |= (E1000_CTRL_FRCSPD | /* Set the Force Speed Bit */ 1508 E1000_CTRL_FRCDPX | /* Set the Force Duplex Bit */ 1509 E1000_CTRL_SPD_1000 |/* Force Speed to 1000 */ 1510 E1000_CTRL_FD | /* Force Duplex to FULL */ 1511 E1000_CTRL_SLU); /* Set link up enable bit */ 1512 1513 if ((hw->phy.type == e1000_phy_m88) || (hw->phy.type == e1000_phy_i210)) 1514 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */ 1515 1516 wr32(E1000_CTRL, ctrl_reg); 1517 1518 /* Disable the receiver on the PHY so when a cable is plugged in, the 1519 * PHY does not begin to autoneg when a cable is reconnected to the NIC. 1520 */ 1521 if ((hw->phy.type == e1000_phy_m88) || (hw->phy.type == e1000_phy_i210)) 1522 igb_phy_disable_receiver(adapter); 1523 1524 udelay(500); 1525 1526 return 0; 1527} 1528 1529static int igb_set_phy_loopback(struct igb_adapter *adapter) 1530{ 1531 return igb_integrated_phy_loopback(adapter); 1532} 1533 1534static int igb_setup_loopback_test(struct igb_adapter *adapter) 1535{ 1536 struct e1000_hw *hw = &adapter->hw; 1537 u32 reg; 1538 1539 reg = rd32(E1000_CTRL_EXT); 1540 1541 /* use CTRL_EXT to identify link type as SGMII can appear as copper */ 1542 if (reg & E1000_CTRL_EXT_LINK_MODE_MASK) { 1543 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1544 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1545 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1546 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) { 1547 1548 /* Enable DH89xxCC MPHY for near end loopback */ 1549 reg = rd32(E1000_MPHY_ADDR_CTL); 1550 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1551 E1000_MPHY_PCS_CLK_REG_OFFSET; 1552 wr32(E1000_MPHY_ADDR_CTL, reg); 1553 1554 reg = rd32(E1000_MPHY_DATA); 1555 reg |= E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1556 wr32(E1000_MPHY_DATA, reg); 1557 } 1558 1559 reg = rd32(E1000_RCTL); 1560 reg |= E1000_RCTL_LBM_TCVR; 1561 wr32(E1000_RCTL, reg); 1562 1563 wr32(E1000_SCTL, E1000_ENABLE_SERDES_LOOPBACK); 1564 1565 reg = rd32(E1000_CTRL); 1566 reg &= ~(E1000_CTRL_RFCE | 1567 E1000_CTRL_TFCE | 1568 E1000_CTRL_LRST); 1569 reg |= E1000_CTRL_SLU | 1570 E1000_CTRL_FD; 1571 wr32(E1000_CTRL, reg); 1572 1573 /* Unset switch control to serdes energy detect */ 1574 reg = rd32(E1000_CONNSW); 1575 reg &= ~E1000_CONNSW_ENRGSRC; 1576 wr32(E1000_CONNSW, reg); 1577 1578 /* Set PCS register for forced speed */ 1579 reg = rd32(E1000_PCS_LCTL); 1580 reg &= ~E1000_PCS_LCTL_AN_ENABLE; /* Disable Autoneg*/ 1581 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */ 1582 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */ 1583 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */ 1584 E1000_PCS_LCTL_FSD | /* Force Speed */ 1585 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */ 1586 wr32(E1000_PCS_LCTL, reg); 1587 1588 return 0; 1589 } 1590 1591 return igb_set_phy_loopback(adapter); 1592} 1593 1594static void igb_loopback_cleanup(struct igb_adapter *adapter) 1595{ 1596 struct e1000_hw *hw = &adapter->hw; 1597 u32 rctl; 1598 u16 phy_reg; 1599 1600 if ((hw->device_id == E1000_DEV_ID_DH89XXCC_SGMII) || 1601 (hw->device_id == E1000_DEV_ID_DH89XXCC_SERDES) || 1602 (hw->device_id == E1000_DEV_ID_DH89XXCC_BACKPLANE) || 1603 (hw->device_id == E1000_DEV_ID_DH89XXCC_SFP)) { 1604 u32 reg; 1605 1606 /* Disable near end loopback on DH89xxCC */ 1607 reg = rd32(E1000_MPHY_ADDR_CTL); 1608 reg = (reg & E1000_MPHY_ADDR_CTL_OFFSET_MASK) | 1609 E1000_MPHY_PCS_CLK_REG_OFFSET; 1610 wr32(E1000_MPHY_ADDR_CTL, reg); 1611 1612 reg = rd32(E1000_MPHY_DATA); 1613 reg &= ~E1000_MPHY_PCS_CLK_REG_DIGINELBEN; 1614 wr32(E1000_MPHY_DATA, reg); 1615 } 1616 1617 rctl = rd32(E1000_RCTL); 1618 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 1619 wr32(E1000_RCTL, rctl); 1620 1621 hw->mac.autoneg = true; 1622 igb_read_phy_reg(hw, PHY_CONTROL, &phy_reg); 1623 if (phy_reg & MII_CR_LOOPBACK) { 1624 phy_reg &= ~MII_CR_LOOPBACK; 1625 igb_write_phy_reg(hw, PHY_CONTROL, phy_reg); 1626 igb_phy_sw_reset(hw); 1627 } 1628} 1629 1630static void igb_create_lbtest_frame(struct sk_buff *skb, 1631 unsigned int frame_size) 1632{ 1633 memset(skb->data, 0xFF, frame_size); 1634 frame_size /= 2; 1635 memset(&skb->data[frame_size], 0xAA, frame_size - 1); 1636 memset(&skb->data[frame_size + 10], 0xBE, 1); 1637 memset(&skb->data[frame_size + 12], 0xAF, 1); 1638} 1639 1640static int igb_check_lbtest_frame(struct sk_buff *skb, unsigned int frame_size) 1641{ 1642 frame_size /= 2; 1643 if (*(skb->data + 3) == 0xFF) { 1644 if ((*(skb->data + frame_size + 10) == 0xBE) && 1645 (*(skb->data + frame_size + 12) == 0xAF)) { 1646 return 0; 1647 } 1648 } 1649 return 13; 1650} 1651 1652static int igb_clean_test_rings(struct igb_ring *rx_ring, 1653 struct igb_ring *tx_ring, 1654 unsigned int size) 1655{ 1656 union e1000_adv_rx_desc *rx_desc; 1657 struct igb_rx_buffer *rx_buffer_info; 1658 struct igb_tx_buffer *tx_buffer_info; 1659 struct netdev_queue *txq; 1660 u16 rx_ntc, tx_ntc, count = 0; 1661 unsigned int total_bytes = 0, total_packets = 0; 1662 1663 /* initialize next to clean and descriptor values */ 1664 rx_ntc = rx_ring->next_to_clean; 1665 tx_ntc = tx_ring->next_to_clean; 1666 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1667 1668 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) { 1669 /* check rx buffer */ 1670 rx_buffer_info = &rx_ring->rx_buffer_info[rx_ntc]; 1671 1672 /* unmap rx buffer, will be remapped by alloc_rx_buffers */ 1673 dma_unmap_single(rx_ring->dev, 1674 rx_buffer_info->dma, 1675 IGB_RX_HDR_LEN, 1676 DMA_FROM_DEVICE); 1677 rx_buffer_info->dma = 0; 1678 1679 /* verify contents of skb */ 1680 if (!igb_check_lbtest_frame(rx_buffer_info->skb, size)) 1681 count++; 1682 1683 /* unmap buffer on tx side */ 1684 tx_buffer_info = &tx_ring->tx_buffer_info[tx_ntc]; 1685 total_bytes += tx_buffer_info->bytecount; 1686 total_packets += tx_buffer_info->gso_segs; 1687 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 1688 1689 /* increment rx/tx next to clean counters */ 1690 rx_ntc++; 1691 if (rx_ntc == rx_ring->count) 1692 rx_ntc = 0; 1693 tx_ntc++; 1694 if (tx_ntc == tx_ring->count) 1695 tx_ntc = 0; 1696 1697 /* fetch next descriptor */ 1698 rx_desc = IGB_RX_DESC(rx_ring, rx_ntc); 1699 } 1700 1701 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index); 1702 netdev_tx_completed_queue(txq, total_packets, total_bytes); 1703 1704 /* re-map buffers to ring, store next to clean values */ 1705 igb_alloc_rx_buffers(rx_ring, count); 1706 rx_ring->next_to_clean = rx_ntc; 1707 tx_ring->next_to_clean = tx_ntc; 1708 1709 return count; 1710} 1711 1712static int igb_run_loopback_test(struct igb_adapter *adapter) 1713{ 1714 struct igb_ring *tx_ring = &adapter->test_tx_ring; 1715 struct igb_ring *rx_ring = &adapter->test_rx_ring; 1716 u16 i, j, lc, good_cnt; 1717 int ret_val = 0; 1718 unsigned int size = IGB_RX_HDR_LEN; 1719 netdev_tx_t tx_ret_val; 1720 struct sk_buff *skb; 1721 1722 /* allocate test skb */ 1723 skb = alloc_skb(size, GFP_KERNEL); 1724 if (!skb) 1725 return 11; 1726 1727 /* place data into test skb */ 1728 igb_create_lbtest_frame(skb, size); 1729 skb_put(skb, size); 1730 1731 /* 1732 * Calculate the loop count based on the largest descriptor ring 1733 * The idea is to wrap the largest ring a number of times using 64 1734 * send/receive pairs during each loop 1735 */ 1736 1737 if (rx_ring->count <= tx_ring->count) 1738 lc = ((tx_ring->count / 64) * 2) + 1; 1739 else 1740 lc = ((rx_ring->count / 64) * 2) + 1; 1741 1742 for (j = 0; j <= lc; j++) { /* loop count loop */ 1743 /* reset count of good packets */ 1744 good_cnt = 0; 1745 1746 /* place 64 packets on the transmit queue*/ 1747 for (i = 0; i < 64; i++) { 1748 skb_get(skb); 1749 tx_ret_val = igb_xmit_frame_ring(skb, tx_ring); 1750 if (tx_ret_val == NETDEV_TX_OK) 1751 good_cnt++; 1752 } 1753 1754 if (good_cnt != 64) { 1755 ret_val = 12; 1756 break; 1757 } 1758 1759 /* allow 200 milliseconds for packets to go from tx to rx */ 1760 msleep(200); 1761 1762 good_cnt = igb_clean_test_rings(rx_ring, tx_ring, size); 1763 if (good_cnt != 64) { 1764 ret_val = 13; 1765 break; 1766 } 1767 } /* end loop count loop */ 1768 1769 /* free the original skb */ 1770 kfree_skb(skb); 1771 1772 return ret_val; 1773} 1774 1775static int igb_loopback_test(struct igb_adapter *adapter, u64 *data) 1776{ 1777 /* PHY loopback cannot be performed if SoL/IDER 1778 * sessions are active */ 1779 if (igb_check_reset_block(&adapter->hw)) { 1780 dev_err(&adapter->pdev->dev, 1781 "Cannot do PHY loopback test when SoL/IDER is active.\n"); 1782 *data = 0; 1783 goto out; 1784 } 1785 if ((adapter->hw.mac.type == e1000_i210) 1786 || (adapter->hw.mac.type == e1000_i211)) { 1787 dev_err(&adapter->pdev->dev, 1788 "Loopback test not supported on this part at this time.\n"); 1789 *data = 0; 1790 goto out; 1791 } 1792 *data = igb_setup_desc_rings(adapter); 1793 if (*data) 1794 goto out; 1795 *data = igb_setup_loopback_test(adapter); 1796 if (*data) 1797 goto err_loopback; 1798 *data = igb_run_loopback_test(adapter); 1799 igb_loopback_cleanup(adapter); 1800 1801err_loopback: 1802 igb_free_desc_rings(adapter); 1803out: 1804 return *data; 1805} 1806 1807static int igb_link_test(struct igb_adapter *adapter, u64 *data) 1808{ 1809 struct e1000_hw *hw = &adapter->hw; 1810 *data = 0; 1811 if (hw->phy.media_type == e1000_media_type_internal_serdes) { 1812 int i = 0; 1813 hw->mac.serdes_has_link = false; 1814 1815 /* On some blade server designs, link establishment 1816 * could take as long as 2-3 minutes */ 1817 do { 1818 hw->mac.ops.check_for_link(&adapter->hw); 1819 if (hw->mac.serdes_has_link) 1820 return *data; 1821 msleep(20); 1822 } while (i++ < 3750); 1823 1824 *data = 1; 1825 } else { 1826 hw->mac.ops.check_for_link(&adapter->hw); 1827 if (hw->mac.autoneg) 1828 msleep(4000); 1829 1830 if (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) 1831 *data = 1; 1832 } 1833 return *data; 1834} 1835 1836static void igb_diag_test(struct net_device *netdev, 1837 struct ethtool_test *eth_test, u64 *data) 1838{ 1839 struct igb_adapter *adapter = netdev_priv(netdev); 1840 u16 autoneg_advertised; 1841 u8 forced_speed_duplex, autoneg; 1842 bool if_running = netif_running(netdev); 1843 1844 set_bit(__IGB_TESTING, &adapter->state); 1845 if (eth_test->flags == ETH_TEST_FL_OFFLINE) { 1846 /* Offline tests */ 1847 1848 /* save speed, duplex, autoneg settings */ 1849 autoneg_advertised = adapter->hw.phy.autoneg_advertised; 1850 forced_speed_duplex = adapter->hw.mac.forced_speed_duplex; 1851 autoneg = adapter->hw.mac.autoneg; 1852 1853 dev_info(&adapter->pdev->dev, "offline testing starting\n"); 1854 1855 /* power up link for link test */ 1856 igb_power_up_link(adapter); 1857 1858 /* Link test performed before hardware reset so autoneg doesn't 1859 * interfere with test result */ 1860 if (igb_link_test(adapter, &data[4])) 1861 eth_test->flags |= ETH_TEST_FL_FAILED; 1862 1863 if (if_running) 1864 /* indicate we're in test mode */ 1865 dev_close(netdev); 1866 else 1867 igb_reset(adapter); 1868 1869 if (igb_reg_test(adapter, &data[0])) 1870 eth_test->flags |= ETH_TEST_FL_FAILED; 1871 1872 igb_reset(adapter); 1873 if (igb_eeprom_test(adapter, &data[1])) 1874 eth_test->flags |= ETH_TEST_FL_FAILED; 1875 1876 igb_reset(adapter); 1877 if (igb_intr_test(adapter, &data[2])) 1878 eth_test->flags |= ETH_TEST_FL_FAILED; 1879 1880 igb_reset(adapter); 1881 /* power up link for loopback test */ 1882 igb_power_up_link(adapter); 1883 if (igb_loopback_test(adapter, &data[3])) 1884 eth_test->flags |= ETH_TEST_FL_FAILED; 1885 1886 /* restore speed, duplex, autoneg settings */ 1887 adapter->hw.phy.autoneg_advertised = autoneg_advertised; 1888 adapter->hw.mac.forced_speed_duplex = forced_speed_duplex; 1889 adapter->hw.mac.autoneg = autoneg; 1890 1891 /* force this routine to wait until autoneg complete/timeout */ 1892 adapter->hw.phy.autoneg_wait_to_complete = true; 1893 igb_reset(adapter); 1894 adapter->hw.phy.autoneg_wait_to_complete = false; 1895 1896 clear_bit(__IGB_TESTING, &adapter->state); 1897 if (if_running) 1898 dev_open(netdev); 1899 } else { 1900 dev_info(&adapter->pdev->dev, "online testing starting\n"); 1901 1902 /* PHY is powered down when interface is down */ 1903 if (if_running && igb_link_test(adapter, &data[4])) 1904 eth_test->flags |= ETH_TEST_FL_FAILED; 1905 else 1906 data[4] = 0; 1907 1908 /* Online tests aren't run; pass by default */ 1909 data[0] = 0; 1910 data[1] = 0; 1911 data[2] = 0; 1912 data[3] = 0; 1913 1914 clear_bit(__IGB_TESTING, &adapter->state); 1915 } 1916 msleep_interruptible(4 * 1000); 1917} 1918 1919static int igb_wol_exclusion(struct igb_adapter *adapter, 1920 struct ethtool_wolinfo *wol) 1921{ 1922 struct e1000_hw *hw = &adapter->hw; 1923 int retval = 1; /* fail by default */ 1924 1925 switch (hw->device_id) { 1926 case E1000_DEV_ID_82575GB_QUAD_COPPER: 1927 /* WoL not supported */ 1928 wol->supported = 0; 1929 break; 1930 case E1000_DEV_ID_82575EB_FIBER_SERDES: 1931 case E1000_DEV_ID_82576_FIBER: 1932 case E1000_DEV_ID_82576_SERDES: 1933 /* Wake events not supported on port B */ 1934 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) { 1935 wol->supported = 0; 1936 break; 1937 } 1938 /* return success for non excluded adapter ports */ 1939 retval = 0; 1940 break; 1941 case E1000_DEV_ID_82576_QUAD_COPPER: 1942 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 1943 /* quad port adapters only support WoL on port A */ 1944 if (!(adapter->flags & IGB_FLAG_QUAD_PORT_A)) { 1945 wol->supported = 0; 1946 break; 1947 } 1948 /* return success for non excluded adapter ports */ 1949 retval = 0; 1950 break; 1951 default: 1952 /* dual port cards only support WoL on port A from now on 1953 * unless it was enabled in the eeprom for port B 1954 * so exclude FUNC_1 ports from having WoL enabled */ 1955 if ((rd32(E1000_STATUS) & E1000_STATUS_FUNC_MASK) && 1956 !adapter->eeprom_wol) { 1957 wol->supported = 0; 1958 break; 1959 } 1960 1961 retval = 0; 1962 } 1963 1964 return retval; 1965} 1966 1967static void igb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 1968{ 1969 struct igb_adapter *adapter = netdev_priv(netdev); 1970 1971 wol->supported = WAKE_UCAST | WAKE_MCAST | 1972 WAKE_BCAST | WAKE_MAGIC | 1973 WAKE_PHY; 1974 wol->wolopts = 0; 1975 1976 /* this function will set ->supported = 0 and return 1 if wol is not 1977 * supported by this hardware */ 1978 if (igb_wol_exclusion(adapter, wol) || 1979 !device_can_wakeup(&adapter->pdev->dev)) 1980 return; 1981 1982 /* apply any specific unsupported masks here */ 1983 switch (adapter->hw.device_id) { 1984 default: 1985 break; 1986 } 1987 1988 if (adapter->wol & E1000_WUFC_EX) 1989 wol->wolopts |= WAKE_UCAST; 1990 if (adapter->wol & E1000_WUFC_MC) 1991 wol->wolopts |= WAKE_MCAST; 1992 if (adapter->wol & E1000_WUFC_BC) 1993 wol->wolopts |= WAKE_BCAST; 1994 if (adapter->wol & E1000_WUFC_MAG) 1995 wol->wolopts |= WAKE_MAGIC; 1996 if (adapter->wol & E1000_WUFC_LNKC) 1997 wol->wolopts |= WAKE_PHY; 1998} 1999 2000static int igb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol) 2001{ 2002 struct igb_adapter *adapter = netdev_priv(netdev); 2003 2004 if (wol->wolopts & (WAKE_ARP | WAKE_MAGICSECURE)) 2005 return -EOPNOTSUPP; 2006 2007 if (igb_wol_exclusion(adapter, wol) || 2008 !device_can_wakeup(&adapter->pdev->dev)) 2009 return wol->wolopts ? -EOPNOTSUPP : 0; 2010 2011 /* these settings will always override what we currently have */ 2012 adapter->wol = 0; 2013 2014 if (wol->wolopts & WAKE_UCAST) 2015 adapter->wol |= E1000_WUFC_EX; 2016 if (wol->wolopts & WAKE_MCAST) 2017 adapter->wol |= E1000_WUFC_MC; 2018 if (wol->wolopts & WAKE_BCAST) 2019 adapter->wol |= E1000_WUFC_BC; 2020 if (wol->wolopts & WAKE_MAGIC) 2021 adapter->wol |= E1000_WUFC_MAG; 2022 if (wol->wolopts & WAKE_PHY) 2023 adapter->wol |= E1000_WUFC_LNKC; 2024 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2025 2026 return 0; 2027} 2028 2029/* bit defines for adapter->led_status */ 2030#define IGB_LED_ON 0 2031 2032static int igb_set_phys_id(struct net_device *netdev, 2033 enum ethtool_phys_id_state state) 2034{ 2035 struct igb_adapter *adapter = netdev_priv(netdev); 2036 struct e1000_hw *hw = &adapter->hw; 2037 2038 switch (state) { 2039 case ETHTOOL_ID_ACTIVE: 2040 igb_blink_led(hw); 2041 return 2; 2042 case ETHTOOL_ID_ON: 2043 igb_blink_led(hw); 2044 break; 2045 case ETHTOOL_ID_OFF: 2046 igb_led_off(hw); 2047 break; 2048 case ETHTOOL_ID_INACTIVE: 2049 igb_led_off(hw); 2050 clear_bit(IGB_LED_ON, &adapter->led_status); 2051 igb_cleanup_led(hw); 2052 break; 2053 } 2054 2055 return 0; 2056} 2057 2058static int igb_set_coalesce(struct net_device *netdev, 2059 struct ethtool_coalesce *ec) 2060{ 2061 struct igb_adapter *adapter = netdev_priv(netdev); 2062 int i; 2063 2064 if ((ec->rx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2065 ((ec->rx_coalesce_usecs > 3) && 2066 (ec->rx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2067 (ec->rx_coalesce_usecs == 2)) 2068 return -EINVAL; 2069 2070 if ((ec->tx_coalesce_usecs > IGB_MAX_ITR_USECS) || 2071 ((ec->tx_coalesce_usecs > 3) && 2072 (ec->tx_coalesce_usecs < IGB_MIN_ITR_USECS)) || 2073 (ec->tx_coalesce_usecs == 2)) 2074 return -EINVAL; 2075 2076 if ((adapter->flags & IGB_FLAG_QUEUE_PAIRS) && ec->tx_coalesce_usecs) 2077 return -EINVAL; 2078 2079 /* If ITR is disabled, disable DMAC */ 2080 if (ec->rx_coalesce_usecs == 0) { 2081 if (adapter->flags & IGB_FLAG_DMAC) 2082 adapter->flags &= ~IGB_FLAG_DMAC; 2083 } 2084 2085 /* convert to rate of irq's per second */ 2086 if (ec->rx_coalesce_usecs && ec->rx_coalesce_usecs <= 3) 2087 adapter->rx_itr_setting = ec->rx_coalesce_usecs; 2088 else 2089 adapter->rx_itr_setting = ec->rx_coalesce_usecs << 2; 2090 2091 /* convert to rate of irq's per second */ 2092 if (adapter->flags & IGB_FLAG_QUEUE_PAIRS) 2093 adapter->tx_itr_setting = adapter->rx_itr_setting; 2094 else if (ec->tx_coalesce_usecs && ec->tx_coalesce_usecs <= 3) 2095 adapter->tx_itr_setting = ec->tx_coalesce_usecs; 2096 else 2097 adapter->tx_itr_setting = ec->tx_coalesce_usecs << 2; 2098 2099 for (i = 0; i < adapter->num_q_vectors; i++) { 2100 struct igb_q_vector *q_vector = adapter->q_vector[i]; 2101 q_vector->tx.work_limit = adapter->tx_work_limit; 2102 if (q_vector->rx.ring) 2103 q_vector->itr_val = adapter->rx_itr_setting; 2104 else 2105 q_vector->itr_val = adapter->tx_itr_setting; 2106 if (q_vector->itr_val && q_vector->itr_val <= 3) 2107 q_vector->itr_val = IGB_START_ITR; 2108 q_vector->set_itr = 1; 2109 } 2110 2111 return 0; 2112} 2113 2114static int igb_get_coalesce(struct net_device *netdev, 2115 struct ethtool_coalesce *ec) 2116{ 2117 struct igb_adapter *adapter = netdev_priv(netdev); 2118 2119 if (adapter->rx_itr_setting <= 3) 2120 ec->rx_coalesce_usecs = adapter->rx_itr_setting; 2121 else 2122 ec->rx_coalesce_usecs = adapter->rx_itr_setting >> 2; 2123 2124 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) { 2125 if (adapter->tx_itr_setting <= 3) 2126 ec->tx_coalesce_usecs = adapter->tx_itr_setting; 2127 else 2128 ec->tx_coalesce_usecs = adapter->tx_itr_setting >> 2; 2129 } 2130 2131 return 0; 2132} 2133 2134static int igb_nway_reset(struct net_device *netdev) 2135{ 2136 struct igb_adapter *adapter = netdev_priv(netdev); 2137 if (netif_running(netdev)) 2138 igb_reinit_locked(adapter); 2139 return 0; 2140} 2141 2142static int igb_get_sset_count(struct net_device *netdev, int sset) 2143{ 2144 switch (sset) { 2145 case ETH_SS_STATS: 2146 return IGB_STATS_LEN; 2147 case ETH_SS_TEST: 2148 return IGB_TEST_LEN; 2149 default: 2150 return -ENOTSUPP; 2151 } 2152} 2153 2154static void igb_get_ethtool_stats(struct net_device *netdev, 2155 struct ethtool_stats *stats, u64 *data) 2156{ 2157 struct igb_adapter *adapter = netdev_priv(netdev); 2158 struct rtnl_link_stats64 *net_stats = &adapter->stats64; 2159 unsigned int start; 2160 struct igb_ring *ring; 2161 int i, j; 2162 char *p; 2163 2164 spin_lock(&adapter->stats64_lock); 2165 igb_update_stats(adapter, net_stats); 2166 2167 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2168 p = (char *)adapter + igb_gstrings_stats[i].stat_offset; 2169 data[i] = (igb_gstrings_stats[i].sizeof_stat == 2170 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2171 } 2172 for (j = 0; j < IGB_NETDEV_STATS_LEN; j++, i++) { 2173 p = (char *)net_stats + igb_gstrings_net_stats[j].stat_offset; 2174 data[i] = (igb_gstrings_net_stats[j].sizeof_stat == 2175 sizeof(u64)) ? *(u64 *)p : *(u32 *)p; 2176 } 2177 for (j = 0; j < adapter->num_tx_queues; j++) { 2178 u64 restart2; 2179 2180 ring = adapter->tx_ring[j]; 2181 do { 2182 start = u64_stats_fetch_begin_bh(&ring->tx_syncp); 2183 data[i] = ring->tx_stats.packets; 2184 data[i+1] = ring->tx_stats.bytes; 2185 data[i+2] = ring->tx_stats.restart_queue; 2186 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); 2187 do { 2188 start = u64_stats_fetch_begin_bh(&ring->tx_syncp2); 2189 restart2 = ring->tx_stats.restart_queue2; 2190 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp2, start)); 2191 data[i+2] += restart2; 2192 2193 i += IGB_TX_QUEUE_STATS_LEN; 2194 } 2195 for (j = 0; j < adapter->num_rx_queues; j++) { 2196 ring = adapter->rx_ring[j]; 2197 do { 2198 start = u64_stats_fetch_begin_bh(&ring->rx_syncp); 2199 data[i] = ring->rx_stats.packets; 2200 data[i+1] = ring->rx_stats.bytes; 2201 data[i+2] = ring->rx_stats.drops; 2202 data[i+3] = ring->rx_stats.csum_err; 2203 data[i+4] = ring->rx_stats.alloc_failed; 2204 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); 2205 i += IGB_RX_QUEUE_STATS_LEN; 2206 } 2207 spin_unlock(&adapter->stats64_lock); 2208} 2209 2210static void igb_get_strings(struct net_device *netdev, u32 stringset, u8 *data) 2211{ 2212 struct igb_adapter *adapter = netdev_priv(netdev); 2213 u8 *p = data; 2214 int i; 2215 2216 switch (stringset) { 2217 case ETH_SS_TEST: 2218 memcpy(data, *igb_gstrings_test, 2219 IGB_TEST_LEN*ETH_GSTRING_LEN); 2220 break; 2221 case ETH_SS_STATS: 2222 for (i = 0; i < IGB_GLOBAL_STATS_LEN; i++) { 2223 memcpy(p, igb_gstrings_stats[i].stat_string, 2224 ETH_GSTRING_LEN); 2225 p += ETH_GSTRING_LEN; 2226 } 2227 for (i = 0; i < IGB_NETDEV_STATS_LEN; i++) { 2228 memcpy(p, igb_gstrings_net_stats[i].stat_string, 2229 ETH_GSTRING_LEN); 2230 p += ETH_GSTRING_LEN; 2231 } 2232 for (i = 0; i < adapter->num_tx_queues; i++) { 2233 sprintf(p, "tx_queue_%u_packets", i); 2234 p += ETH_GSTRING_LEN; 2235 sprintf(p, "tx_queue_%u_bytes", i); 2236 p += ETH_GSTRING_LEN; 2237 sprintf(p, "tx_queue_%u_restart", i); 2238 p += ETH_GSTRING_LEN; 2239 } 2240 for (i = 0; i < adapter->num_rx_queues; i++) { 2241 sprintf(p, "rx_queue_%u_packets", i); 2242 p += ETH_GSTRING_LEN; 2243 sprintf(p, "rx_queue_%u_bytes", i); 2244 p += ETH_GSTRING_LEN; 2245 sprintf(p, "rx_queue_%u_drops", i); 2246 p += ETH_GSTRING_LEN; 2247 sprintf(p, "rx_queue_%u_csum_err", i); 2248 p += ETH_GSTRING_LEN; 2249 sprintf(p, "rx_queue_%u_alloc_failed", i); 2250 p += ETH_GSTRING_LEN; 2251 } 2252/* BUG_ON(p - data != IGB_STATS_LEN * ETH_GSTRING_LEN); */ 2253 break; 2254 } 2255} 2256 2257static int igb_ethtool_begin(struct net_device *netdev) 2258{ 2259 struct igb_adapter *adapter = netdev_priv(netdev); 2260 pm_runtime_get_sync(&adapter->pdev->dev); 2261 return 0; 2262} 2263 2264static void igb_ethtool_complete(struct net_device *netdev) 2265{ 2266 struct igb_adapter *adapter = netdev_priv(netdev); 2267 pm_runtime_put(&adapter->pdev->dev); 2268} 2269 2270#ifdef CONFIG_IGB_PTP 2271static int igb_ethtool_get_ts_info(struct net_device *dev, 2272 struct ethtool_ts_info *info) 2273{ 2274 struct igb_adapter *adapter = netdev_priv(dev); 2275 2276 info->so_timestamping = 2277 SOF_TIMESTAMPING_TX_HARDWARE | 2278 SOF_TIMESTAMPING_RX_HARDWARE | 2279 SOF_TIMESTAMPING_RAW_HARDWARE; 2280 2281 if (adapter->ptp_clock) 2282 info->phc_index = ptp_clock_index(adapter->ptp_clock); 2283 else 2284 info->phc_index = -1; 2285 2286 info->tx_types = 2287 (1 << HWTSTAMP_TX_OFF) | 2288 (1 << HWTSTAMP_TX_ON); 2289 2290 info->rx_filters = 2291 (1 << HWTSTAMP_FILTER_NONE) | 2292 (1 << HWTSTAMP_FILTER_ALL) | 2293 (1 << HWTSTAMP_FILTER_SOME) | 2294 (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) | 2295 (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) | 2296 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 2297 2298 return 0; 2299} 2300 2301#endif 2302static const struct ethtool_ops igb_ethtool_ops = { 2303 .get_settings = igb_get_settings, 2304 .set_settings = igb_set_settings, 2305 .get_drvinfo = igb_get_drvinfo, 2306 .get_regs_len = igb_get_regs_len, 2307 .get_regs = igb_get_regs, 2308 .get_wol = igb_get_wol, 2309 .set_wol = igb_set_wol, 2310 .get_msglevel = igb_get_msglevel, 2311 .set_msglevel = igb_set_msglevel, 2312 .nway_reset = igb_nway_reset, 2313 .get_link = igb_get_link, 2314 .get_eeprom_len = igb_get_eeprom_len, 2315 .get_eeprom = igb_get_eeprom, 2316 .set_eeprom = igb_set_eeprom, 2317 .get_ringparam = igb_get_ringparam, 2318 .set_ringparam = igb_set_ringparam, 2319 .get_pauseparam = igb_get_pauseparam, 2320 .set_pauseparam = igb_set_pauseparam, 2321 .self_test = igb_diag_test, 2322 .get_strings = igb_get_strings, 2323 .set_phys_id = igb_set_phys_id, 2324 .get_sset_count = igb_get_sset_count, 2325 .get_ethtool_stats = igb_get_ethtool_stats, 2326 .get_coalesce = igb_get_coalesce, 2327 .set_coalesce = igb_set_coalesce, 2328 .begin = igb_ethtool_begin, 2329 .complete = igb_ethtool_complete, 2330#ifdef CONFIG_IGB_PTP 2331 .get_ts_info = igb_ethtool_get_ts_info, 2332#endif 2333}; 2334 2335void igb_set_ethtool_ops(struct net_device *netdev) 2336{ 2337 SET_ETHTOOL_OPS(netdev, &igb_ethtool_ops); 2338} 2339