igb_main.c revision 039454a818b4bfdb530d84b2cdcf014b2f4d2b53
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30#include <linux/module.h> 31#include <linux/types.h> 32#include <linux/init.h> 33#include <linux/bitops.h> 34#include <linux/vmalloc.h> 35#include <linux/pagemap.h> 36#include <linux/netdevice.h> 37#include <linux/ipv6.h> 38#include <linux/slab.h> 39#include <net/checksum.h> 40#include <net/ip6_checksum.h> 41#include <linux/net_tstamp.h> 42#include <linux/mii.h> 43#include <linux/ethtool.h> 44#include <linux/if.h> 45#include <linux/if_vlan.h> 46#include <linux/pci.h> 47#include <linux/pci-aspm.h> 48#include <linux/delay.h> 49#include <linux/interrupt.h> 50#include <linux/ip.h> 51#include <linux/tcp.h> 52#include <linux/sctp.h> 53#include <linux/if_ether.h> 54#include <linux/aer.h> 55#include <linux/prefetch.h> 56#include <linux/pm_runtime.h> 57#ifdef CONFIG_IGB_DCA 58#include <linux/dca.h> 59#endif 60#include "igb.h" 61 62#define MAJ 4 63#define MIN 0 64#define BUILD 17 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 66__stringify(BUILD) "-k" 67char igb_driver_name[] = "igb"; 68char igb_driver_version[] = DRV_VERSION; 69static const char igb_driver_string[] = 70 "Intel(R) Gigabit Ethernet Network Driver"; 71static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation."; 72 73static const struct e1000_info *igb_info_tbl[] = { 74 [board_82575] = &e1000_82575_info, 75}; 76 77static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 108 /* required last entry */ 109 {0, } 110}; 111 112MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 113 114void igb_reset(struct igb_adapter *); 115static int igb_setup_all_tx_resources(struct igb_adapter *); 116static int igb_setup_all_rx_resources(struct igb_adapter *); 117static void igb_free_all_tx_resources(struct igb_adapter *); 118static void igb_free_all_rx_resources(struct igb_adapter *); 119static void igb_setup_mrqc(struct igb_adapter *); 120static int igb_probe(struct pci_dev *, const struct pci_device_id *); 121static void __devexit igb_remove(struct pci_dev *pdev); 122static int igb_sw_init(struct igb_adapter *); 123static int igb_open(struct net_device *); 124static int igb_close(struct net_device *); 125static void igb_configure_tx(struct igb_adapter *); 126static void igb_configure_rx(struct igb_adapter *); 127static void igb_clean_all_tx_rings(struct igb_adapter *); 128static void igb_clean_all_rx_rings(struct igb_adapter *); 129static void igb_clean_tx_ring(struct igb_ring *); 130static void igb_clean_rx_ring(struct igb_ring *); 131static void igb_set_rx_mode(struct net_device *); 132static void igb_update_phy_info(unsigned long); 133static void igb_watchdog(unsigned long); 134static void igb_watchdog_task(struct work_struct *); 135static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 136static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 137 struct rtnl_link_stats64 *stats); 138static int igb_change_mtu(struct net_device *, int); 139static int igb_set_mac(struct net_device *, void *); 140static void igb_set_uta(struct igb_adapter *adapter); 141static irqreturn_t igb_intr(int irq, void *); 142static irqreturn_t igb_intr_msi(int irq, void *); 143static irqreturn_t igb_msix_other(int irq, void *); 144static irqreturn_t igb_msix_ring(int irq, void *); 145#ifdef CONFIG_IGB_DCA 146static void igb_update_dca(struct igb_q_vector *); 147static void igb_setup_dca(struct igb_adapter *); 148#endif /* CONFIG_IGB_DCA */ 149static int igb_poll(struct napi_struct *, int); 150static bool igb_clean_tx_irq(struct igb_q_vector *); 151static bool igb_clean_rx_irq(struct igb_q_vector *, int); 152static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 153static void igb_tx_timeout(struct net_device *); 154static void igb_reset_task(struct work_struct *); 155static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); 156static int igb_vlan_rx_add_vid(struct net_device *, u16); 157static int igb_vlan_rx_kill_vid(struct net_device *, u16); 158static void igb_restore_vlan(struct igb_adapter *); 159static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 160static void igb_ping_all_vfs(struct igb_adapter *); 161static void igb_msg_task(struct igb_adapter *); 162static void igb_vmm_control(struct igb_adapter *); 163static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 164static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 165static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 166static int igb_ndo_set_vf_vlan(struct net_device *netdev, 167 int vf, u16 vlan, u8 qos); 168static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 169static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 170 struct ifla_vf_info *ivi); 171static void igb_check_vf_rate_limit(struct igb_adapter *); 172 173#ifdef CONFIG_PCI_IOV 174static int igb_vf_configure(struct igb_adapter *adapter, int vf); 175static bool igb_vfs_are_assigned(struct igb_adapter *adapter); 176#endif 177 178#ifdef CONFIG_PM 179#ifdef CONFIG_PM_SLEEP 180static int igb_suspend(struct device *); 181#endif 182static int igb_resume(struct device *); 183#ifdef CONFIG_PM_RUNTIME 184static int igb_runtime_suspend(struct device *dev); 185static int igb_runtime_resume(struct device *dev); 186static int igb_runtime_idle(struct device *dev); 187#endif 188static const struct dev_pm_ops igb_pm_ops = { 189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 191 igb_runtime_idle) 192}; 193#endif 194static void igb_shutdown(struct pci_dev *); 195#ifdef CONFIG_IGB_DCA 196static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 197static struct notifier_block dca_notifier = { 198 .notifier_call = igb_notify_dca, 199 .next = NULL, 200 .priority = 0 201}; 202#endif 203#ifdef CONFIG_NET_POLL_CONTROLLER 204/* for netdump / net console */ 205static void igb_netpoll(struct net_device *); 206#endif 207#ifdef CONFIG_PCI_IOV 208static unsigned int max_vfs = 0; 209module_param(max_vfs, uint, 0); 210MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " 211 "per physical function"); 212#endif /* CONFIG_PCI_IOV */ 213 214static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 215 pci_channel_state_t); 216static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 217static void igb_io_resume(struct pci_dev *); 218 219static const struct pci_error_handlers igb_err_handler = { 220 .error_detected = igb_io_error_detected, 221 .slot_reset = igb_io_slot_reset, 222 .resume = igb_io_resume, 223}; 224 225static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 226 227static struct pci_driver igb_driver = { 228 .name = igb_driver_name, 229 .id_table = igb_pci_tbl, 230 .probe = igb_probe, 231 .remove = __devexit_p(igb_remove), 232#ifdef CONFIG_PM 233 .driver.pm = &igb_pm_ops, 234#endif 235 .shutdown = igb_shutdown, 236 .err_handler = &igb_err_handler 237}; 238 239MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 240MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 241MODULE_LICENSE("GPL"); 242MODULE_VERSION(DRV_VERSION); 243 244#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 245static int debug = -1; 246module_param(debug, int, 0); 247MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 248 249struct igb_reg_info { 250 u32 ofs; 251 char *name; 252}; 253 254static const struct igb_reg_info igb_reg_info_tbl[] = { 255 256 /* General Registers */ 257 {E1000_CTRL, "CTRL"}, 258 {E1000_STATUS, "STATUS"}, 259 {E1000_CTRL_EXT, "CTRL_EXT"}, 260 261 /* Interrupt Registers */ 262 {E1000_ICR, "ICR"}, 263 264 /* RX Registers */ 265 {E1000_RCTL, "RCTL"}, 266 {E1000_RDLEN(0), "RDLEN"}, 267 {E1000_RDH(0), "RDH"}, 268 {E1000_RDT(0), "RDT"}, 269 {E1000_RXDCTL(0), "RXDCTL"}, 270 {E1000_RDBAL(0), "RDBAL"}, 271 {E1000_RDBAH(0), "RDBAH"}, 272 273 /* TX Registers */ 274 {E1000_TCTL, "TCTL"}, 275 {E1000_TDBAL(0), "TDBAL"}, 276 {E1000_TDBAH(0), "TDBAH"}, 277 {E1000_TDLEN(0), "TDLEN"}, 278 {E1000_TDH(0), "TDH"}, 279 {E1000_TDT(0), "TDT"}, 280 {E1000_TXDCTL(0), "TXDCTL"}, 281 {E1000_TDFH, "TDFH"}, 282 {E1000_TDFT, "TDFT"}, 283 {E1000_TDFHS, "TDFHS"}, 284 {E1000_TDFPC, "TDFPC"}, 285 286 /* List Terminator */ 287 {} 288}; 289 290/* 291 * igb_regdump - register printout routine 292 */ 293static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 294{ 295 int n = 0; 296 char rname[16]; 297 u32 regs[8]; 298 299 switch (reginfo->ofs) { 300 case E1000_RDLEN(0): 301 for (n = 0; n < 4; n++) 302 regs[n] = rd32(E1000_RDLEN(n)); 303 break; 304 case E1000_RDH(0): 305 for (n = 0; n < 4; n++) 306 regs[n] = rd32(E1000_RDH(n)); 307 break; 308 case E1000_RDT(0): 309 for (n = 0; n < 4; n++) 310 regs[n] = rd32(E1000_RDT(n)); 311 break; 312 case E1000_RXDCTL(0): 313 for (n = 0; n < 4; n++) 314 regs[n] = rd32(E1000_RXDCTL(n)); 315 break; 316 case E1000_RDBAL(0): 317 for (n = 0; n < 4; n++) 318 regs[n] = rd32(E1000_RDBAL(n)); 319 break; 320 case E1000_RDBAH(0): 321 for (n = 0; n < 4; n++) 322 regs[n] = rd32(E1000_RDBAH(n)); 323 break; 324 case E1000_TDBAL(0): 325 for (n = 0; n < 4; n++) 326 regs[n] = rd32(E1000_RDBAL(n)); 327 break; 328 case E1000_TDBAH(0): 329 for (n = 0; n < 4; n++) 330 regs[n] = rd32(E1000_TDBAH(n)); 331 break; 332 case E1000_TDLEN(0): 333 for (n = 0; n < 4; n++) 334 regs[n] = rd32(E1000_TDLEN(n)); 335 break; 336 case E1000_TDH(0): 337 for (n = 0; n < 4; n++) 338 regs[n] = rd32(E1000_TDH(n)); 339 break; 340 case E1000_TDT(0): 341 for (n = 0; n < 4; n++) 342 regs[n] = rd32(E1000_TDT(n)); 343 break; 344 case E1000_TXDCTL(0): 345 for (n = 0; n < 4; n++) 346 regs[n] = rd32(E1000_TXDCTL(n)); 347 break; 348 default: 349 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 350 return; 351 } 352 353 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 354 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 355 regs[2], regs[3]); 356} 357 358/* 359 * igb_dump - Print registers, tx-rings and rx-rings 360 */ 361static void igb_dump(struct igb_adapter *adapter) 362{ 363 struct net_device *netdev = adapter->netdev; 364 struct e1000_hw *hw = &adapter->hw; 365 struct igb_reg_info *reginfo; 366 struct igb_ring *tx_ring; 367 union e1000_adv_tx_desc *tx_desc; 368 struct my_u0 { u64 a; u64 b; } *u0; 369 struct igb_ring *rx_ring; 370 union e1000_adv_rx_desc *rx_desc; 371 u32 staterr; 372 u16 i, n; 373 374 if (!netif_msg_hw(adapter)) 375 return; 376 377 /* Print netdevice Info */ 378 if (netdev) { 379 dev_info(&adapter->pdev->dev, "Net device Info\n"); 380 pr_info("Device Name state trans_start " 381 "last_rx\n"); 382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 383 netdev->state, netdev->trans_start, netdev->last_rx); 384 } 385 386 /* Print Registers */ 387 dev_info(&adapter->pdev->dev, "Register Dump\n"); 388 pr_info(" Register Name Value\n"); 389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 390 reginfo->name; reginfo++) { 391 igb_regdump(hw, reginfo); 392 } 393 394 /* Print TX Ring Summary */ 395 if (!netdev || !netif_running(netdev)) 396 goto exit; 397 398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 400 for (n = 0; n < adapter->num_tx_queues; n++) { 401 struct igb_tx_buffer *buffer_info; 402 tx_ring = adapter->tx_ring[n]; 403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 405 n, tx_ring->next_to_use, tx_ring->next_to_clean, 406 (u64)dma_unmap_addr(buffer_info, dma), 407 dma_unmap_len(buffer_info, len), 408 buffer_info->next_to_watch, 409 (u64)buffer_info->time_stamp); 410 } 411 412 /* Print TX Rings */ 413 if (!netif_msg_tx_done(adapter)) 414 goto rx_ring_summary; 415 416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 417 418 /* Transmit Descriptor Formats 419 * 420 * Advanced Transmit Descriptor 421 * +--------------------------------------------------------------+ 422 * 0 | Buffer Address [63:0] | 423 * +--------------------------------------------------------------+ 424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 425 * +--------------------------------------------------------------+ 426 * 63 46 45 40 39 38 36 35 32 31 24 15 0 427 */ 428 429 for (n = 0; n < adapter->num_tx_queues; n++) { 430 tx_ring = adapter->tx_ring[n]; 431 pr_info("------------------------------------\n"); 432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 433 pr_info("------------------------------------\n"); 434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] " 435 "[bi->dma ] leng ntw timestamp " 436 "bi->skb\n"); 437 438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 439 const char *next_desc; 440 struct igb_tx_buffer *buffer_info; 441 tx_desc = IGB_TX_DESC(tx_ring, i); 442 buffer_info = &tx_ring->tx_buffer_info[i]; 443 u0 = (struct my_u0 *)tx_desc; 444 if (i == tx_ring->next_to_use && 445 i == tx_ring->next_to_clean) 446 next_desc = " NTC/U"; 447 else if (i == tx_ring->next_to_use) 448 next_desc = " NTU"; 449 else if (i == tx_ring->next_to_clean) 450 next_desc = " NTC"; 451 else 452 next_desc = ""; 453 454 pr_info("T [0x%03X] %016llX %016llX %016llX" 455 " %04X %p %016llX %p%s\n", i, 456 le64_to_cpu(u0->a), 457 le64_to_cpu(u0->b), 458 (u64)dma_unmap_addr(buffer_info, dma), 459 dma_unmap_len(buffer_info, len), 460 buffer_info->next_to_watch, 461 (u64)buffer_info->time_stamp, 462 buffer_info->skb, next_desc); 463 464 if (netif_msg_pktdata(adapter) && buffer_info->skb) 465 print_hex_dump(KERN_INFO, "", 466 DUMP_PREFIX_ADDRESS, 467 16, 1, buffer_info->skb->data, 468 dma_unmap_len(buffer_info, len), 469 true); 470 } 471 } 472 473 /* Print RX Rings Summary */ 474rx_ring_summary: 475 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 476 pr_info("Queue [NTU] [NTC]\n"); 477 for (n = 0; n < adapter->num_rx_queues; n++) { 478 rx_ring = adapter->rx_ring[n]; 479 pr_info(" %5d %5X %5X\n", 480 n, rx_ring->next_to_use, rx_ring->next_to_clean); 481 } 482 483 /* Print RX Rings */ 484 if (!netif_msg_rx_status(adapter)) 485 goto exit; 486 487 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 488 489 /* Advanced Receive Descriptor (Read) Format 490 * 63 1 0 491 * +-----------------------------------------------------+ 492 * 0 | Packet Buffer Address [63:1] |A0/NSE| 493 * +----------------------------------------------+------+ 494 * 8 | Header Buffer Address [63:1] | DD | 495 * +-----------------------------------------------------+ 496 * 497 * 498 * Advanced Receive Descriptor (Write-Back) Format 499 * 500 * 63 48 47 32 31 30 21 20 17 16 4 3 0 501 * +------------------------------------------------------+ 502 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 503 * | Checksum Ident | | | | Type | Type | 504 * +------------------------------------------------------+ 505 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 506 * +------------------------------------------------------+ 507 * 63 48 47 32 31 20 19 0 508 */ 509 510 for (n = 0; n < adapter->num_rx_queues; n++) { 511 rx_ring = adapter->rx_ring[n]; 512 pr_info("------------------------------------\n"); 513 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 514 pr_info("------------------------------------\n"); 515 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] " 516 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 517 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----" 518 "----------- [bi->skb] <-- Adv Rx Write-Back format\n"); 519 520 for (i = 0; i < rx_ring->count; i++) { 521 const char *next_desc; 522 struct igb_rx_buffer *buffer_info; 523 buffer_info = &rx_ring->rx_buffer_info[i]; 524 rx_desc = IGB_RX_DESC(rx_ring, i); 525 u0 = (struct my_u0 *)rx_desc; 526 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 527 528 if (i == rx_ring->next_to_use) 529 next_desc = " NTU"; 530 else if (i == rx_ring->next_to_clean) 531 next_desc = " NTC"; 532 else 533 next_desc = ""; 534 535 if (staterr & E1000_RXD_STAT_DD) { 536 /* Descriptor Done */ 537 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 538 "RWB", i, 539 le64_to_cpu(u0->a), 540 le64_to_cpu(u0->b), 541 next_desc); 542 } else { 543 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 544 "R ", i, 545 le64_to_cpu(u0->a), 546 le64_to_cpu(u0->b), 547 (u64)buffer_info->dma, 548 next_desc); 549 550 if (netif_msg_pktdata(adapter) && 551 buffer_info->dma && buffer_info->page) { 552 print_hex_dump(KERN_INFO, "", 553 DUMP_PREFIX_ADDRESS, 554 16, 1, 555 page_address(buffer_info->page) + 556 buffer_info->page_offset, 557 IGB_RX_BUFSZ, true); 558 } 559 } 560 } 561 } 562 563exit: 564 return; 565} 566 567/** 568 * igb_get_hw_dev - return device 569 * used by hardware layer to print debugging information 570 **/ 571struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 572{ 573 struct igb_adapter *adapter = hw->back; 574 return adapter->netdev; 575} 576 577/** 578 * igb_init_module - Driver Registration Routine 579 * 580 * igb_init_module is the first routine called when the driver is 581 * loaded. All it does is register with the PCI subsystem. 582 **/ 583static int __init igb_init_module(void) 584{ 585 int ret; 586 pr_info("%s - version %s\n", 587 igb_driver_string, igb_driver_version); 588 589 pr_info("%s\n", igb_copyright); 590 591#ifdef CONFIG_IGB_DCA 592 dca_register_notify(&dca_notifier); 593#endif 594 ret = pci_register_driver(&igb_driver); 595 return ret; 596} 597 598module_init(igb_init_module); 599 600/** 601 * igb_exit_module - Driver Exit Cleanup Routine 602 * 603 * igb_exit_module is called just before the driver is removed 604 * from memory. 605 **/ 606static void __exit igb_exit_module(void) 607{ 608#ifdef CONFIG_IGB_DCA 609 dca_unregister_notify(&dca_notifier); 610#endif 611 pci_unregister_driver(&igb_driver); 612} 613 614module_exit(igb_exit_module); 615 616#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 617/** 618 * igb_cache_ring_register - Descriptor ring to register mapping 619 * @adapter: board private structure to initialize 620 * 621 * Once we know the feature-set enabled for the device, we'll cache 622 * the register offset the descriptor ring is assigned to. 623 **/ 624static void igb_cache_ring_register(struct igb_adapter *adapter) 625{ 626 int i = 0, j = 0; 627 u32 rbase_offset = adapter->vfs_allocated_count; 628 629 switch (adapter->hw.mac.type) { 630 case e1000_82576: 631 /* The queues are allocated for virtualization such that VF 0 632 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 633 * In order to avoid collision we start at the first free queue 634 * and continue consuming queues in the same sequence 635 */ 636 if (adapter->vfs_allocated_count) { 637 for (; i < adapter->rss_queues; i++) 638 adapter->rx_ring[i]->reg_idx = rbase_offset + 639 Q_IDX_82576(i); 640 } 641 case e1000_82575: 642 case e1000_82580: 643 case e1000_i350: 644 case e1000_i210: 645 case e1000_i211: 646 default: 647 for (; i < adapter->num_rx_queues; i++) 648 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 649 for (; j < adapter->num_tx_queues; j++) 650 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 651 break; 652 } 653} 654 655/** 656 * igb_write_ivar - configure ivar for given MSI-X vector 657 * @hw: pointer to the HW structure 658 * @msix_vector: vector number we are allocating to a given ring 659 * @index: row index of IVAR register to write within IVAR table 660 * @offset: column offset of in IVAR, should be multiple of 8 661 * 662 * This function is intended to handle the writing of the IVAR register 663 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 664 * each containing an cause allocation for an Rx and Tx ring, and a 665 * variable number of rows depending on the number of queues supported. 666 **/ 667static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 668 int index, int offset) 669{ 670 u32 ivar = array_rd32(E1000_IVAR0, index); 671 672 /* clear any bits that are currently set */ 673 ivar &= ~((u32)0xFF << offset); 674 675 /* write vector and valid bit */ 676 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 677 678 array_wr32(E1000_IVAR0, index, ivar); 679} 680 681#define IGB_N0_QUEUE -1 682static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 683{ 684 struct igb_adapter *adapter = q_vector->adapter; 685 struct e1000_hw *hw = &adapter->hw; 686 int rx_queue = IGB_N0_QUEUE; 687 int tx_queue = IGB_N0_QUEUE; 688 u32 msixbm = 0; 689 690 if (q_vector->rx.ring) 691 rx_queue = q_vector->rx.ring->reg_idx; 692 if (q_vector->tx.ring) 693 tx_queue = q_vector->tx.ring->reg_idx; 694 695 switch (hw->mac.type) { 696 case e1000_82575: 697 /* The 82575 assigns vectors using a bitmask, which matches the 698 bitmask for the EICR/EIMS/EIMC registers. To assign one 699 or more queues to a vector, we write the appropriate bits 700 into the MSIXBM register for that vector. */ 701 if (rx_queue > IGB_N0_QUEUE) 702 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 703 if (tx_queue > IGB_N0_QUEUE) 704 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 705 if (!adapter->msix_entries && msix_vector == 0) 706 msixbm |= E1000_EIMS_OTHER; 707 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 708 q_vector->eims_value = msixbm; 709 break; 710 case e1000_82576: 711 /* 712 * 82576 uses a table that essentially consists of 2 columns 713 * with 8 rows. The ordering is column-major so we use the 714 * lower 3 bits as the row index, and the 4th bit as the 715 * column offset. 716 */ 717 if (rx_queue > IGB_N0_QUEUE) 718 igb_write_ivar(hw, msix_vector, 719 rx_queue & 0x7, 720 (rx_queue & 0x8) << 1); 721 if (tx_queue > IGB_N0_QUEUE) 722 igb_write_ivar(hw, msix_vector, 723 tx_queue & 0x7, 724 ((tx_queue & 0x8) << 1) + 8); 725 q_vector->eims_value = 1 << msix_vector; 726 break; 727 case e1000_82580: 728 case e1000_i350: 729 case e1000_i210: 730 case e1000_i211: 731 /* 732 * On 82580 and newer adapters the scheme is similar to 82576 733 * however instead of ordering column-major we have things 734 * ordered row-major. So we traverse the table by using 735 * bit 0 as the column offset, and the remaining bits as the 736 * row index. 737 */ 738 if (rx_queue > IGB_N0_QUEUE) 739 igb_write_ivar(hw, msix_vector, 740 rx_queue >> 1, 741 (rx_queue & 0x1) << 4); 742 if (tx_queue > IGB_N0_QUEUE) 743 igb_write_ivar(hw, msix_vector, 744 tx_queue >> 1, 745 ((tx_queue & 0x1) << 4) + 8); 746 q_vector->eims_value = 1 << msix_vector; 747 break; 748 default: 749 BUG(); 750 break; 751 } 752 753 /* add q_vector eims value to global eims_enable_mask */ 754 adapter->eims_enable_mask |= q_vector->eims_value; 755 756 /* configure q_vector to set itr on first interrupt */ 757 q_vector->set_itr = 1; 758} 759 760/** 761 * igb_configure_msix - Configure MSI-X hardware 762 * 763 * igb_configure_msix sets up the hardware to properly 764 * generate MSI-X interrupts. 765 **/ 766static void igb_configure_msix(struct igb_adapter *adapter) 767{ 768 u32 tmp; 769 int i, vector = 0; 770 struct e1000_hw *hw = &adapter->hw; 771 772 adapter->eims_enable_mask = 0; 773 774 /* set vector for other causes, i.e. link changes */ 775 switch (hw->mac.type) { 776 case e1000_82575: 777 tmp = rd32(E1000_CTRL_EXT); 778 /* enable MSI-X PBA support*/ 779 tmp |= E1000_CTRL_EXT_PBA_CLR; 780 781 /* Auto-Mask interrupts upon ICR read. */ 782 tmp |= E1000_CTRL_EXT_EIAME; 783 tmp |= E1000_CTRL_EXT_IRCA; 784 785 wr32(E1000_CTRL_EXT, tmp); 786 787 /* enable msix_other interrupt */ 788 array_wr32(E1000_MSIXBM(0), vector++, 789 E1000_EIMS_OTHER); 790 adapter->eims_other = E1000_EIMS_OTHER; 791 792 break; 793 794 case e1000_82576: 795 case e1000_82580: 796 case e1000_i350: 797 case e1000_i210: 798 case e1000_i211: 799 /* Turn on MSI-X capability first, or our settings 800 * won't stick. And it will take days to debug. */ 801 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 802 E1000_GPIE_PBA | E1000_GPIE_EIAME | 803 E1000_GPIE_NSICR); 804 805 /* enable msix_other interrupt */ 806 adapter->eims_other = 1 << vector; 807 tmp = (vector++ | E1000_IVAR_VALID) << 8; 808 809 wr32(E1000_IVAR_MISC, tmp); 810 break; 811 default: 812 /* do nothing, since nothing else supports MSI-X */ 813 break; 814 } /* switch (hw->mac.type) */ 815 816 adapter->eims_enable_mask |= adapter->eims_other; 817 818 for (i = 0; i < adapter->num_q_vectors; i++) 819 igb_assign_vector(adapter->q_vector[i], vector++); 820 821 wrfl(); 822} 823 824/** 825 * igb_request_msix - Initialize MSI-X interrupts 826 * 827 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 828 * kernel. 829 **/ 830static int igb_request_msix(struct igb_adapter *adapter) 831{ 832 struct net_device *netdev = adapter->netdev; 833 struct e1000_hw *hw = &adapter->hw; 834 int i, err = 0, vector = 0; 835 836 err = request_irq(adapter->msix_entries[vector].vector, 837 igb_msix_other, 0, netdev->name, adapter); 838 if (err) 839 goto out; 840 vector++; 841 842 for (i = 0; i < adapter->num_q_vectors; i++) { 843 struct igb_q_vector *q_vector = adapter->q_vector[i]; 844 845 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 846 847 if (q_vector->rx.ring && q_vector->tx.ring) 848 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 849 q_vector->rx.ring->queue_index); 850 else if (q_vector->tx.ring) 851 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 852 q_vector->tx.ring->queue_index); 853 else if (q_vector->rx.ring) 854 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 855 q_vector->rx.ring->queue_index); 856 else 857 sprintf(q_vector->name, "%s-unused", netdev->name); 858 859 err = request_irq(adapter->msix_entries[vector].vector, 860 igb_msix_ring, 0, q_vector->name, 861 q_vector); 862 if (err) 863 goto out; 864 vector++; 865 } 866 867 igb_configure_msix(adapter); 868 return 0; 869out: 870 return err; 871} 872 873static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 874{ 875 if (adapter->msix_entries) { 876 pci_disable_msix(adapter->pdev); 877 kfree(adapter->msix_entries); 878 adapter->msix_entries = NULL; 879 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 880 pci_disable_msi(adapter->pdev); 881 } 882} 883 884/** 885 * igb_free_q_vector - Free memory allocated for specific interrupt vector 886 * @adapter: board private structure to initialize 887 * @v_idx: Index of vector to be freed 888 * 889 * This function frees the memory allocated to the q_vector. In addition if 890 * NAPI is enabled it will delete any references to the NAPI struct prior 891 * to freeing the q_vector. 892 **/ 893static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 894{ 895 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 896 897 if (q_vector->tx.ring) 898 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 899 900 if (q_vector->rx.ring) 901 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; 902 903 adapter->q_vector[v_idx] = NULL; 904 netif_napi_del(&q_vector->napi); 905 906 /* 907 * ixgbe_get_stats64() might access the rings on this vector, 908 * we must wait a grace period before freeing it. 909 */ 910 kfree_rcu(q_vector, rcu); 911} 912 913/** 914 * igb_free_q_vectors - Free memory allocated for interrupt vectors 915 * @adapter: board private structure to initialize 916 * 917 * This function frees the memory allocated to the q_vectors. In addition if 918 * NAPI is enabled it will delete any references to the NAPI struct prior 919 * to freeing the q_vector. 920 **/ 921static void igb_free_q_vectors(struct igb_adapter *adapter) 922{ 923 int v_idx = adapter->num_q_vectors; 924 925 adapter->num_tx_queues = 0; 926 adapter->num_rx_queues = 0; 927 adapter->num_q_vectors = 0; 928 929 while (v_idx--) 930 igb_free_q_vector(adapter, v_idx); 931} 932 933/** 934 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 935 * 936 * This function resets the device so that it has 0 rx queues, tx queues, and 937 * MSI-X interrupts allocated. 938 */ 939static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 940{ 941 igb_free_q_vectors(adapter); 942 igb_reset_interrupt_capability(adapter); 943} 944 945/** 946 * igb_set_interrupt_capability - set MSI or MSI-X if supported 947 * 948 * Attempt to configure interrupts using the best available 949 * capabilities of the hardware and kernel. 950 **/ 951static void igb_set_interrupt_capability(struct igb_adapter *adapter) 952{ 953 int err; 954 int numvecs, i; 955 956 /* Number of supported queues. */ 957 adapter->num_rx_queues = adapter->rss_queues; 958 if (adapter->vfs_allocated_count) 959 adapter->num_tx_queues = 1; 960 else 961 adapter->num_tx_queues = adapter->rss_queues; 962 963 /* start with one vector for every rx queue */ 964 numvecs = adapter->num_rx_queues; 965 966 /* if tx handler is separate add 1 for every tx queue */ 967 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 968 numvecs += adapter->num_tx_queues; 969 970 /* store the number of vectors reserved for queues */ 971 adapter->num_q_vectors = numvecs; 972 973 /* add 1 vector for link status interrupts */ 974 numvecs++; 975 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), 976 GFP_KERNEL); 977 978 if (!adapter->msix_entries) 979 goto msi_only; 980 981 for (i = 0; i < numvecs; i++) 982 adapter->msix_entries[i].entry = i; 983 984 err = pci_enable_msix(adapter->pdev, 985 adapter->msix_entries, 986 numvecs); 987 if (err == 0) 988 return; 989 990 igb_reset_interrupt_capability(adapter); 991 992 /* If we can't do MSI-X, try MSI */ 993msi_only: 994#ifdef CONFIG_PCI_IOV 995 /* disable SR-IOV for non MSI-X configurations */ 996 if (adapter->vf_data) { 997 struct e1000_hw *hw = &adapter->hw; 998 /* disable iov and allow time for transactions to clear */ 999 pci_disable_sriov(adapter->pdev); 1000 msleep(500); 1001 1002 kfree(adapter->vf_data); 1003 adapter->vf_data = NULL; 1004 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1005 wrfl(); 1006 msleep(100); 1007 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1008 } 1009#endif 1010 adapter->vfs_allocated_count = 0; 1011 adapter->rss_queues = 1; 1012 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1013 adapter->num_rx_queues = 1; 1014 adapter->num_tx_queues = 1; 1015 adapter->num_q_vectors = 1; 1016 if (!pci_enable_msi(adapter->pdev)) 1017 adapter->flags |= IGB_FLAG_HAS_MSI; 1018} 1019 1020static void igb_add_ring(struct igb_ring *ring, 1021 struct igb_ring_container *head) 1022{ 1023 head->ring = ring; 1024 head->count++; 1025} 1026 1027/** 1028 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1029 * @adapter: board private structure to initialize 1030 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1031 * @v_idx: index of vector in adapter struct 1032 * @txr_count: total number of Tx rings to allocate 1033 * @txr_idx: index of first Tx ring to allocate 1034 * @rxr_count: total number of Rx rings to allocate 1035 * @rxr_idx: index of first Rx ring to allocate 1036 * 1037 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1038 **/ 1039static int igb_alloc_q_vector(struct igb_adapter *adapter, 1040 int v_count, int v_idx, 1041 int txr_count, int txr_idx, 1042 int rxr_count, int rxr_idx) 1043{ 1044 struct igb_q_vector *q_vector; 1045 struct igb_ring *ring; 1046 int ring_count, size; 1047 1048 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1049 if (txr_count > 1 || rxr_count > 1) 1050 return -ENOMEM; 1051 1052 ring_count = txr_count + rxr_count; 1053 size = sizeof(struct igb_q_vector) + 1054 (sizeof(struct igb_ring) * ring_count); 1055 1056 /* allocate q_vector and rings */ 1057 q_vector = kzalloc(size, GFP_KERNEL); 1058 if (!q_vector) 1059 return -ENOMEM; 1060 1061 /* initialize NAPI */ 1062 netif_napi_add(adapter->netdev, &q_vector->napi, 1063 igb_poll, 64); 1064 1065 /* tie q_vector and adapter together */ 1066 adapter->q_vector[v_idx] = q_vector; 1067 q_vector->adapter = adapter; 1068 1069 /* initialize work limits */ 1070 q_vector->tx.work_limit = adapter->tx_work_limit; 1071 1072 /* initialize ITR configuration */ 1073 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); 1074 q_vector->itr_val = IGB_START_ITR; 1075 1076 /* initialize pointer to rings */ 1077 ring = q_vector->ring; 1078 1079 if (txr_count) { 1080 /* assign generic ring traits */ 1081 ring->dev = &adapter->pdev->dev; 1082 ring->netdev = adapter->netdev; 1083 1084 /* configure backlink on ring */ 1085 ring->q_vector = q_vector; 1086 1087 /* update q_vector Tx values */ 1088 igb_add_ring(ring, &q_vector->tx); 1089 1090 /* For 82575, context index must be unique per ring. */ 1091 if (adapter->hw.mac.type == e1000_82575) 1092 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1093 1094 /* apply Tx specific ring traits */ 1095 ring->count = adapter->tx_ring_count; 1096 ring->queue_index = txr_idx; 1097 1098 /* assign ring to adapter */ 1099 adapter->tx_ring[txr_idx] = ring; 1100 1101 /* push pointer to next ring */ 1102 ring++; 1103 } 1104 1105 if (rxr_count) { 1106 /* assign generic ring traits */ 1107 ring->dev = &adapter->pdev->dev; 1108 ring->netdev = adapter->netdev; 1109 1110 /* configure backlink on ring */ 1111 ring->q_vector = q_vector; 1112 1113 /* update q_vector Rx values */ 1114 igb_add_ring(ring, &q_vector->rx); 1115 1116 /* set flag indicating ring supports SCTP checksum offload */ 1117 if (adapter->hw.mac.type >= e1000_82576) 1118 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1119 1120 /* 1121 * On i350, i210, and i211, loopback VLAN packets 1122 * have the tag byte-swapped. 1123 * */ 1124 if (adapter->hw.mac.type >= e1000_i350) 1125 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1126 1127 /* apply Rx specific ring traits */ 1128 ring->count = adapter->rx_ring_count; 1129 ring->queue_index = rxr_idx; 1130 1131 /* assign ring to adapter */ 1132 adapter->rx_ring[rxr_idx] = ring; 1133 } 1134 1135 return 0; 1136} 1137 1138 1139/** 1140 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1141 * @adapter: board private structure to initialize 1142 * 1143 * We allocate one q_vector per queue interrupt. If allocation fails we 1144 * return -ENOMEM. 1145 **/ 1146static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1147{ 1148 int q_vectors = adapter->num_q_vectors; 1149 int rxr_remaining = adapter->num_rx_queues; 1150 int txr_remaining = adapter->num_tx_queues; 1151 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1152 int err; 1153 1154 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1155 for (; rxr_remaining; v_idx++) { 1156 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1157 0, 0, 1, rxr_idx); 1158 1159 if (err) 1160 goto err_out; 1161 1162 /* update counts and index */ 1163 rxr_remaining--; 1164 rxr_idx++; 1165 } 1166 } 1167 1168 for (; v_idx < q_vectors; v_idx++) { 1169 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1170 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1171 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1172 tqpv, txr_idx, rqpv, rxr_idx); 1173 1174 if (err) 1175 goto err_out; 1176 1177 /* update counts and index */ 1178 rxr_remaining -= rqpv; 1179 txr_remaining -= tqpv; 1180 rxr_idx++; 1181 txr_idx++; 1182 } 1183 1184 return 0; 1185 1186err_out: 1187 adapter->num_tx_queues = 0; 1188 adapter->num_rx_queues = 0; 1189 adapter->num_q_vectors = 0; 1190 1191 while (v_idx--) 1192 igb_free_q_vector(adapter, v_idx); 1193 1194 return -ENOMEM; 1195} 1196 1197/** 1198 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1199 * 1200 * This function initializes the interrupts and allocates all of the queues. 1201 **/ 1202static int igb_init_interrupt_scheme(struct igb_adapter *adapter) 1203{ 1204 struct pci_dev *pdev = adapter->pdev; 1205 int err; 1206 1207 igb_set_interrupt_capability(adapter); 1208 1209 err = igb_alloc_q_vectors(adapter); 1210 if (err) { 1211 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1212 goto err_alloc_q_vectors; 1213 } 1214 1215 igb_cache_ring_register(adapter); 1216 1217 return 0; 1218 1219err_alloc_q_vectors: 1220 igb_reset_interrupt_capability(adapter); 1221 return err; 1222} 1223 1224/** 1225 * igb_request_irq - initialize interrupts 1226 * 1227 * Attempts to configure interrupts using the best available 1228 * capabilities of the hardware and kernel. 1229 **/ 1230static int igb_request_irq(struct igb_adapter *adapter) 1231{ 1232 struct net_device *netdev = adapter->netdev; 1233 struct pci_dev *pdev = adapter->pdev; 1234 int err = 0; 1235 1236 if (adapter->msix_entries) { 1237 err = igb_request_msix(adapter); 1238 if (!err) 1239 goto request_done; 1240 /* fall back to MSI */ 1241 igb_free_all_tx_resources(adapter); 1242 igb_free_all_rx_resources(adapter); 1243 igb_clear_interrupt_scheme(adapter); 1244 if (!pci_enable_msi(pdev)) 1245 adapter->flags |= IGB_FLAG_HAS_MSI; 1246 adapter->num_tx_queues = 1; 1247 adapter->num_rx_queues = 1; 1248 adapter->num_q_vectors = 1; 1249 err = igb_alloc_q_vectors(adapter); 1250 if (err) { 1251 dev_err(&pdev->dev, 1252 "Unable to allocate memory for vectors\n"); 1253 goto request_done; 1254 } 1255 igb_setup_all_tx_resources(adapter); 1256 igb_setup_all_rx_resources(adapter); 1257 } 1258 1259 igb_assign_vector(adapter->q_vector[0], 0); 1260 1261 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1262 err = request_irq(pdev->irq, igb_intr_msi, 0, 1263 netdev->name, adapter); 1264 if (!err) 1265 goto request_done; 1266 1267 /* fall back to legacy interrupts */ 1268 igb_reset_interrupt_capability(adapter); 1269 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1270 } 1271 1272 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1273 netdev->name, adapter); 1274 1275 if (err) 1276 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1277 err); 1278 1279request_done: 1280 return err; 1281} 1282 1283static void igb_free_irq(struct igb_adapter *adapter) 1284{ 1285 if (adapter->msix_entries) { 1286 int vector = 0, i; 1287 1288 free_irq(adapter->msix_entries[vector++].vector, adapter); 1289 1290 for (i = 0; i < adapter->num_q_vectors; i++) 1291 free_irq(adapter->msix_entries[vector++].vector, 1292 adapter->q_vector[i]); 1293 } else { 1294 free_irq(adapter->pdev->irq, adapter); 1295 } 1296} 1297 1298/** 1299 * igb_irq_disable - Mask off interrupt generation on the NIC 1300 * @adapter: board private structure 1301 **/ 1302static void igb_irq_disable(struct igb_adapter *adapter) 1303{ 1304 struct e1000_hw *hw = &adapter->hw; 1305 1306 /* 1307 * we need to be careful when disabling interrupts. The VFs are also 1308 * mapped into these registers and so clearing the bits can cause 1309 * issues on the VF drivers so we only need to clear what we set 1310 */ 1311 if (adapter->msix_entries) { 1312 u32 regval = rd32(E1000_EIAM); 1313 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1314 wr32(E1000_EIMC, adapter->eims_enable_mask); 1315 regval = rd32(E1000_EIAC); 1316 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1317 } 1318 1319 wr32(E1000_IAM, 0); 1320 wr32(E1000_IMC, ~0); 1321 wrfl(); 1322 if (adapter->msix_entries) { 1323 int i; 1324 for (i = 0; i < adapter->num_q_vectors; i++) 1325 synchronize_irq(adapter->msix_entries[i].vector); 1326 } else { 1327 synchronize_irq(adapter->pdev->irq); 1328 } 1329} 1330 1331/** 1332 * igb_irq_enable - Enable default interrupt generation settings 1333 * @adapter: board private structure 1334 **/ 1335static void igb_irq_enable(struct igb_adapter *adapter) 1336{ 1337 struct e1000_hw *hw = &adapter->hw; 1338 1339 if (adapter->msix_entries) { 1340 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1341 u32 regval = rd32(E1000_EIAC); 1342 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1343 regval = rd32(E1000_EIAM); 1344 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1345 wr32(E1000_EIMS, adapter->eims_enable_mask); 1346 if (adapter->vfs_allocated_count) { 1347 wr32(E1000_MBVFIMR, 0xFF); 1348 ims |= E1000_IMS_VMMB; 1349 } 1350 wr32(E1000_IMS, ims); 1351 } else { 1352 wr32(E1000_IMS, IMS_ENABLE_MASK | 1353 E1000_IMS_DRSTA); 1354 wr32(E1000_IAM, IMS_ENABLE_MASK | 1355 E1000_IMS_DRSTA); 1356 } 1357} 1358 1359static void igb_update_mng_vlan(struct igb_adapter *adapter) 1360{ 1361 struct e1000_hw *hw = &adapter->hw; 1362 u16 vid = adapter->hw.mng_cookie.vlan_id; 1363 u16 old_vid = adapter->mng_vlan_id; 1364 1365 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1366 /* add VID to filter table */ 1367 igb_vfta_set(hw, vid, true); 1368 adapter->mng_vlan_id = vid; 1369 } else { 1370 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1371 } 1372 1373 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1374 (vid != old_vid) && 1375 !test_bit(old_vid, adapter->active_vlans)) { 1376 /* remove VID from filter table */ 1377 igb_vfta_set(hw, old_vid, false); 1378 } 1379} 1380 1381/** 1382 * igb_release_hw_control - release control of the h/w to f/w 1383 * @adapter: address of board private structure 1384 * 1385 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1386 * For ASF and Pass Through versions of f/w this means that the 1387 * driver is no longer loaded. 1388 * 1389 **/ 1390static void igb_release_hw_control(struct igb_adapter *adapter) 1391{ 1392 struct e1000_hw *hw = &adapter->hw; 1393 u32 ctrl_ext; 1394 1395 /* Let firmware take over control of h/w */ 1396 ctrl_ext = rd32(E1000_CTRL_EXT); 1397 wr32(E1000_CTRL_EXT, 1398 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1399} 1400 1401/** 1402 * igb_get_hw_control - get control of the h/w from f/w 1403 * @adapter: address of board private structure 1404 * 1405 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1406 * For ASF and Pass Through versions of f/w this means that 1407 * the driver is loaded. 1408 * 1409 **/ 1410static void igb_get_hw_control(struct igb_adapter *adapter) 1411{ 1412 struct e1000_hw *hw = &adapter->hw; 1413 u32 ctrl_ext; 1414 1415 /* Let firmware know the driver has taken over */ 1416 ctrl_ext = rd32(E1000_CTRL_EXT); 1417 wr32(E1000_CTRL_EXT, 1418 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1419} 1420 1421/** 1422 * igb_configure - configure the hardware for RX and TX 1423 * @adapter: private board structure 1424 **/ 1425static void igb_configure(struct igb_adapter *adapter) 1426{ 1427 struct net_device *netdev = adapter->netdev; 1428 int i; 1429 1430 igb_get_hw_control(adapter); 1431 igb_set_rx_mode(netdev); 1432 1433 igb_restore_vlan(adapter); 1434 1435 igb_setup_tctl(adapter); 1436 igb_setup_mrqc(adapter); 1437 igb_setup_rctl(adapter); 1438 1439 igb_configure_tx(adapter); 1440 igb_configure_rx(adapter); 1441 1442 igb_rx_fifo_flush_82575(&adapter->hw); 1443 1444 /* call igb_desc_unused which always leaves 1445 * at least 1 descriptor unused to make sure 1446 * next_to_use != next_to_clean */ 1447 for (i = 0; i < adapter->num_rx_queues; i++) { 1448 struct igb_ring *ring = adapter->rx_ring[i]; 1449 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1450 } 1451} 1452 1453/** 1454 * igb_power_up_link - Power up the phy/serdes link 1455 * @adapter: address of board private structure 1456 **/ 1457void igb_power_up_link(struct igb_adapter *adapter) 1458{ 1459 igb_reset_phy(&adapter->hw); 1460 1461 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1462 igb_power_up_phy_copper(&adapter->hw); 1463 else 1464 igb_power_up_serdes_link_82575(&adapter->hw); 1465} 1466 1467/** 1468 * igb_power_down_link - Power down the phy/serdes link 1469 * @adapter: address of board private structure 1470 */ 1471static void igb_power_down_link(struct igb_adapter *adapter) 1472{ 1473 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1474 igb_power_down_phy_copper_82575(&adapter->hw); 1475 else 1476 igb_shutdown_serdes_link_82575(&adapter->hw); 1477} 1478 1479/** 1480 * igb_up - Open the interface and prepare it to handle traffic 1481 * @adapter: board private structure 1482 **/ 1483int igb_up(struct igb_adapter *adapter) 1484{ 1485 struct e1000_hw *hw = &adapter->hw; 1486 int i; 1487 1488 /* hardware has been reset, we need to reload some things */ 1489 igb_configure(adapter); 1490 1491 clear_bit(__IGB_DOWN, &adapter->state); 1492 1493 for (i = 0; i < adapter->num_q_vectors; i++) 1494 napi_enable(&(adapter->q_vector[i]->napi)); 1495 1496 if (adapter->msix_entries) 1497 igb_configure_msix(adapter); 1498 else 1499 igb_assign_vector(adapter->q_vector[0], 0); 1500 1501 /* Clear any pending interrupts. */ 1502 rd32(E1000_ICR); 1503 igb_irq_enable(adapter); 1504 1505 /* notify VFs that reset has been completed */ 1506 if (adapter->vfs_allocated_count) { 1507 u32 reg_data = rd32(E1000_CTRL_EXT); 1508 reg_data |= E1000_CTRL_EXT_PFRSTD; 1509 wr32(E1000_CTRL_EXT, reg_data); 1510 } 1511 1512 netif_tx_start_all_queues(adapter->netdev); 1513 1514 /* start the watchdog. */ 1515 hw->mac.get_link_status = 1; 1516 schedule_work(&adapter->watchdog_task); 1517 1518 return 0; 1519} 1520 1521void igb_down(struct igb_adapter *adapter) 1522{ 1523 struct net_device *netdev = adapter->netdev; 1524 struct e1000_hw *hw = &adapter->hw; 1525 u32 tctl, rctl; 1526 int i; 1527 1528 /* signal that we're down so the interrupt handler does not 1529 * reschedule our watchdog timer */ 1530 set_bit(__IGB_DOWN, &adapter->state); 1531 1532 /* disable receives in the hardware */ 1533 rctl = rd32(E1000_RCTL); 1534 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1535 /* flush and sleep below */ 1536 1537 netif_tx_stop_all_queues(netdev); 1538 1539 /* disable transmits in the hardware */ 1540 tctl = rd32(E1000_TCTL); 1541 tctl &= ~E1000_TCTL_EN; 1542 wr32(E1000_TCTL, tctl); 1543 /* flush both disables and wait for them to finish */ 1544 wrfl(); 1545 msleep(10); 1546 1547 for (i = 0; i < adapter->num_q_vectors; i++) 1548 napi_disable(&(adapter->q_vector[i]->napi)); 1549 1550 igb_irq_disable(adapter); 1551 1552 del_timer_sync(&adapter->watchdog_timer); 1553 del_timer_sync(&adapter->phy_info_timer); 1554 1555 netif_carrier_off(netdev); 1556 1557 /* record the stats before reset*/ 1558 spin_lock(&adapter->stats64_lock); 1559 igb_update_stats(adapter, &adapter->stats64); 1560 spin_unlock(&adapter->stats64_lock); 1561 1562 adapter->link_speed = 0; 1563 adapter->link_duplex = 0; 1564 1565 if (!pci_channel_offline(adapter->pdev)) 1566 igb_reset(adapter); 1567 igb_clean_all_tx_rings(adapter); 1568 igb_clean_all_rx_rings(adapter); 1569#ifdef CONFIG_IGB_DCA 1570 1571 /* since we reset the hardware DCA settings were cleared */ 1572 igb_setup_dca(adapter); 1573#endif 1574} 1575 1576void igb_reinit_locked(struct igb_adapter *adapter) 1577{ 1578 WARN_ON(in_interrupt()); 1579 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1580 msleep(1); 1581 igb_down(adapter); 1582 igb_up(adapter); 1583 clear_bit(__IGB_RESETTING, &adapter->state); 1584} 1585 1586void igb_reset(struct igb_adapter *adapter) 1587{ 1588 struct pci_dev *pdev = adapter->pdev; 1589 struct e1000_hw *hw = &adapter->hw; 1590 struct e1000_mac_info *mac = &hw->mac; 1591 struct e1000_fc_info *fc = &hw->fc; 1592 u32 pba = 0, tx_space, min_tx_space, min_rx_space; 1593 u16 hwm; 1594 1595 /* Repartition Pba for greater than 9k mtu 1596 * To take effect CTRL.RST is required. 1597 */ 1598 switch (mac->type) { 1599 case e1000_i350: 1600 case e1000_82580: 1601 pba = rd32(E1000_RXPBS); 1602 pba = igb_rxpbs_adjust_82580(pba); 1603 break; 1604 case e1000_82576: 1605 pba = rd32(E1000_RXPBS); 1606 pba &= E1000_RXPBS_SIZE_MASK_82576; 1607 break; 1608 case e1000_82575: 1609 case e1000_i210: 1610 case e1000_i211: 1611 default: 1612 pba = E1000_PBA_34K; 1613 break; 1614 } 1615 1616 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1617 (mac->type < e1000_82576)) { 1618 /* adjust PBA for jumbo frames */ 1619 wr32(E1000_PBA, pba); 1620 1621 /* To maintain wire speed transmits, the Tx FIFO should be 1622 * large enough to accommodate two full transmit packets, 1623 * rounded up to the next 1KB and expressed in KB. Likewise, 1624 * the Rx FIFO should be large enough to accommodate at least 1625 * one full receive packet and is similarly rounded up and 1626 * expressed in KB. */ 1627 pba = rd32(E1000_PBA); 1628 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1629 tx_space = pba >> 16; 1630 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1631 pba &= 0xffff; 1632 /* the tx fifo also stores 16 bytes of information about the tx 1633 * but don't include ethernet FCS because hardware appends it */ 1634 min_tx_space = (adapter->max_frame_size + 1635 sizeof(union e1000_adv_tx_desc) - 1636 ETH_FCS_LEN) * 2; 1637 min_tx_space = ALIGN(min_tx_space, 1024); 1638 min_tx_space >>= 10; 1639 /* software strips receive CRC, so leave room for it */ 1640 min_rx_space = adapter->max_frame_size; 1641 min_rx_space = ALIGN(min_rx_space, 1024); 1642 min_rx_space >>= 10; 1643 1644 /* If current Tx allocation is less than the min Tx FIFO size, 1645 * and the min Tx FIFO size is less than the current Rx FIFO 1646 * allocation, take space away from current Rx allocation */ 1647 if (tx_space < min_tx_space && 1648 ((min_tx_space - tx_space) < pba)) { 1649 pba = pba - (min_tx_space - tx_space); 1650 1651 /* if short on rx space, rx wins and must trump tx 1652 * adjustment */ 1653 if (pba < min_rx_space) 1654 pba = min_rx_space; 1655 } 1656 wr32(E1000_PBA, pba); 1657 } 1658 1659 /* flow control settings */ 1660 /* The high water mark must be low enough to fit one full frame 1661 * (or the size used for early receive) above it in the Rx FIFO. 1662 * Set it to the lower of: 1663 * - 90% of the Rx FIFO size, or 1664 * - the full Rx FIFO size minus one full frame */ 1665 hwm = min(((pba << 10) * 9 / 10), 1666 ((pba << 10) - 2 * adapter->max_frame_size)); 1667 1668 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ 1669 fc->low_water = fc->high_water - 16; 1670 fc->pause_time = 0xFFFF; 1671 fc->send_xon = 1; 1672 fc->current_mode = fc->requested_mode; 1673 1674 /* disable receive for all VFs and wait one second */ 1675 if (adapter->vfs_allocated_count) { 1676 int i; 1677 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1678 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1679 1680 /* ping all the active vfs to let them know we are going down */ 1681 igb_ping_all_vfs(adapter); 1682 1683 /* disable transmits and receives */ 1684 wr32(E1000_VFRE, 0); 1685 wr32(E1000_VFTE, 0); 1686 } 1687 1688 /* Allow time for pending master requests to run */ 1689 hw->mac.ops.reset_hw(hw); 1690 wr32(E1000_WUC, 0); 1691 1692 if (hw->mac.ops.init_hw(hw)) 1693 dev_err(&pdev->dev, "Hardware Error\n"); 1694 1695 /* 1696 * Flow control settings reset on hardware reset, so guarantee flow 1697 * control is off when forcing speed. 1698 */ 1699 if (!hw->mac.autoneg) 1700 igb_force_mac_fc(hw); 1701 1702 igb_init_dmac(adapter, pba); 1703 if (!netif_running(adapter->netdev)) 1704 igb_power_down_link(adapter); 1705 1706 igb_update_mng_vlan(adapter); 1707 1708 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 1709 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 1710 1711 /* Re-enable PTP, where applicable. */ 1712 igb_ptp_reset(adapter); 1713 1714 igb_get_phy_info(hw); 1715} 1716 1717static netdev_features_t igb_fix_features(struct net_device *netdev, 1718 netdev_features_t features) 1719{ 1720 /* 1721 * Since there is no support for separate rx/tx vlan accel 1722 * enable/disable make sure tx flag is always in same state as rx. 1723 */ 1724 if (features & NETIF_F_HW_VLAN_RX) 1725 features |= NETIF_F_HW_VLAN_TX; 1726 else 1727 features &= ~NETIF_F_HW_VLAN_TX; 1728 1729 return features; 1730} 1731 1732static int igb_set_features(struct net_device *netdev, 1733 netdev_features_t features) 1734{ 1735 netdev_features_t changed = netdev->features ^ features; 1736 struct igb_adapter *adapter = netdev_priv(netdev); 1737 1738 if (changed & NETIF_F_HW_VLAN_RX) 1739 igb_vlan_mode(netdev, features); 1740 1741 if (!(changed & NETIF_F_RXALL)) 1742 return 0; 1743 1744 netdev->features = features; 1745 1746 if (netif_running(netdev)) 1747 igb_reinit_locked(adapter); 1748 else 1749 igb_reset(adapter); 1750 1751 return 0; 1752} 1753 1754static const struct net_device_ops igb_netdev_ops = { 1755 .ndo_open = igb_open, 1756 .ndo_stop = igb_close, 1757 .ndo_start_xmit = igb_xmit_frame, 1758 .ndo_get_stats64 = igb_get_stats64, 1759 .ndo_set_rx_mode = igb_set_rx_mode, 1760 .ndo_set_mac_address = igb_set_mac, 1761 .ndo_change_mtu = igb_change_mtu, 1762 .ndo_do_ioctl = igb_ioctl, 1763 .ndo_tx_timeout = igb_tx_timeout, 1764 .ndo_validate_addr = eth_validate_addr, 1765 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 1766 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 1767 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 1768 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 1769 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, 1770 .ndo_get_vf_config = igb_ndo_get_vf_config, 1771#ifdef CONFIG_NET_POLL_CONTROLLER 1772 .ndo_poll_controller = igb_netpoll, 1773#endif 1774 .ndo_fix_features = igb_fix_features, 1775 .ndo_set_features = igb_set_features, 1776}; 1777 1778/** 1779 * igb_set_fw_version - Configure version string for ethtool 1780 * @adapter: adapter struct 1781 * 1782 **/ 1783void igb_set_fw_version(struct igb_adapter *adapter) 1784{ 1785 struct e1000_hw *hw = &adapter->hw; 1786 struct e1000_fw_version fw; 1787 1788 igb_get_fw_version(hw, &fw); 1789 1790 switch (hw->mac.type) { 1791 case e1000_i211: 1792 snprintf(adapter->fw_version, sizeof(adapter->fw_version), 1793 "%2d.%2d-%d", 1794 fw.invm_major, fw.invm_minor, fw.invm_img_type); 1795 break; 1796 1797 default: 1798 /* if option is rom valid, display its version too */ 1799 if (fw.or_valid) { 1800 snprintf(adapter->fw_version, 1801 sizeof(adapter->fw_version), 1802 "%d.%d, 0x%08x, %d.%d.%d", 1803 fw.eep_major, fw.eep_minor, fw.etrack_id, 1804 fw.or_major, fw.or_build, fw.or_patch); 1805 /* no option rom */ 1806 } else { 1807 snprintf(adapter->fw_version, 1808 sizeof(adapter->fw_version), 1809 "%d.%d, 0x%08x", 1810 fw.eep_major, fw.eep_minor, fw.etrack_id); 1811 } 1812 break; 1813 } 1814 return; 1815} 1816 1817/** 1818 * igb_probe - Device Initialization Routine 1819 * @pdev: PCI device information struct 1820 * @ent: entry in igb_pci_tbl 1821 * 1822 * Returns 0 on success, negative on failure 1823 * 1824 * igb_probe initializes an adapter identified by a pci_dev structure. 1825 * The OS initialization, configuring of the adapter private structure, 1826 * and a hardware reset occur. 1827 **/ 1828static int __devinit igb_probe(struct pci_dev *pdev, 1829 const struct pci_device_id *ent) 1830{ 1831 struct net_device *netdev; 1832 struct igb_adapter *adapter; 1833 struct e1000_hw *hw; 1834 u16 eeprom_data = 0; 1835 s32 ret_val; 1836 static int global_quad_port_a; /* global quad port a indication */ 1837 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 1838 unsigned long mmio_start, mmio_len; 1839 int err, pci_using_dac; 1840 u16 eeprom_apme_mask = IGB_EEPROM_APME; 1841 u8 part_str[E1000_PBANUM_LENGTH]; 1842 1843 /* Catch broken hardware that put the wrong VF device ID in 1844 * the PCIe SR-IOV capability. 1845 */ 1846 if (pdev->is_virtfn) { 1847 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 1848 pci_name(pdev), pdev->vendor, pdev->device); 1849 return -EINVAL; 1850 } 1851 1852 err = pci_enable_device_mem(pdev); 1853 if (err) 1854 return err; 1855 1856 pci_using_dac = 0; 1857 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 1858 if (!err) { 1859 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 1860 if (!err) 1861 pci_using_dac = 1; 1862 } else { 1863 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1864 if (err) { 1865 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 1866 if (err) { 1867 dev_err(&pdev->dev, "No usable DMA " 1868 "configuration, aborting\n"); 1869 goto err_dma; 1870 } 1871 } 1872 } 1873 1874 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 1875 IORESOURCE_MEM), 1876 igb_driver_name); 1877 if (err) 1878 goto err_pci_reg; 1879 1880 pci_enable_pcie_error_reporting(pdev); 1881 1882 pci_set_master(pdev); 1883 pci_save_state(pdev); 1884 1885 err = -ENOMEM; 1886 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 1887 IGB_MAX_TX_QUEUES); 1888 if (!netdev) 1889 goto err_alloc_etherdev; 1890 1891 SET_NETDEV_DEV(netdev, &pdev->dev); 1892 1893 pci_set_drvdata(pdev, netdev); 1894 adapter = netdev_priv(netdev); 1895 adapter->netdev = netdev; 1896 adapter->pdev = pdev; 1897 hw = &adapter->hw; 1898 hw->back = adapter; 1899 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 1900 1901 mmio_start = pci_resource_start(pdev, 0); 1902 mmio_len = pci_resource_len(pdev, 0); 1903 1904 err = -EIO; 1905 hw->hw_addr = ioremap(mmio_start, mmio_len); 1906 if (!hw->hw_addr) 1907 goto err_ioremap; 1908 1909 netdev->netdev_ops = &igb_netdev_ops; 1910 igb_set_ethtool_ops(netdev); 1911 netdev->watchdog_timeo = 5 * HZ; 1912 1913 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 1914 1915 netdev->mem_start = mmio_start; 1916 netdev->mem_end = mmio_start + mmio_len; 1917 1918 /* PCI config space info */ 1919 hw->vendor_id = pdev->vendor; 1920 hw->device_id = pdev->device; 1921 hw->revision_id = pdev->revision; 1922 hw->subsystem_vendor_id = pdev->subsystem_vendor; 1923 hw->subsystem_device_id = pdev->subsystem_device; 1924 1925 /* Copy the default MAC, PHY and NVM function pointers */ 1926 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 1927 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 1928 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 1929 /* Initialize skew-specific constants */ 1930 err = ei->get_invariants(hw); 1931 if (err) 1932 goto err_sw_init; 1933 1934 /* setup the private structure */ 1935 err = igb_sw_init(adapter); 1936 if (err) 1937 goto err_sw_init; 1938 1939 igb_get_bus_info_pcie(hw); 1940 1941 hw->phy.autoneg_wait_to_complete = false; 1942 1943 /* Copper options */ 1944 if (hw->phy.media_type == e1000_media_type_copper) { 1945 hw->phy.mdix = AUTO_ALL_MODES; 1946 hw->phy.disable_polarity_correction = false; 1947 hw->phy.ms_type = e1000_ms_hw_default; 1948 } 1949 1950 if (igb_check_reset_block(hw)) 1951 dev_info(&pdev->dev, 1952 "PHY reset is blocked due to SOL/IDER session.\n"); 1953 1954 /* 1955 * features is initialized to 0 in allocation, it might have bits 1956 * set by igb_sw_init so we should use an or instead of an 1957 * assignment. 1958 */ 1959 netdev->features |= NETIF_F_SG | 1960 NETIF_F_IP_CSUM | 1961 NETIF_F_IPV6_CSUM | 1962 NETIF_F_TSO | 1963 NETIF_F_TSO6 | 1964 NETIF_F_RXHASH | 1965 NETIF_F_RXCSUM | 1966 NETIF_F_HW_VLAN_RX | 1967 NETIF_F_HW_VLAN_TX; 1968 1969 /* copy netdev features into list of user selectable features */ 1970 netdev->hw_features |= netdev->features; 1971 netdev->hw_features |= NETIF_F_RXALL; 1972 1973 /* set this bit last since it cannot be part of hw_features */ 1974 netdev->features |= NETIF_F_HW_VLAN_FILTER; 1975 1976 netdev->vlan_features |= NETIF_F_TSO | 1977 NETIF_F_TSO6 | 1978 NETIF_F_IP_CSUM | 1979 NETIF_F_IPV6_CSUM | 1980 NETIF_F_SG; 1981 1982 netdev->priv_flags |= IFF_SUPP_NOFCS; 1983 1984 if (pci_using_dac) { 1985 netdev->features |= NETIF_F_HIGHDMA; 1986 netdev->vlan_features |= NETIF_F_HIGHDMA; 1987 } 1988 1989 if (hw->mac.type >= e1000_82576) { 1990 netdev->hw_features |= NETIF_F_SCTP_CSUM; 1991 netdev->features |= NETIF_F_SCTP_CSUM; 1992 } 1993 1994 netdev->priv_flags |= IFF_UNICAST_FLT; 1995 1996 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 1997 1998 /* before reading the NVM, reset the controller to put the device in a 1999 * known good starting state */ 2000 hw->mac.ops.reset_hw(hw); 2001 2002 /* 2003 * make sure the NVM is good , i211 parts have special NVM that 2004 * doesn't contain a checksum 2005 */ 2006 if (hw->mac.type != e1000_i211) { 2007 if (hw->nvm.ops.validate(hw) < 0) { 2008 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2009 err = -EIO; 2010 goto err_eeprom; 2011 } 2012 } 2013 2014 /* copy the MAC address out of the NVM */ 2015 if (hw->mac.ops.read_mac_addr(hw)) 2016 dev_err(&pdev->dev, "NVM Read Error\n"); 2017 2018 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2019 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); 2020 2021 if (!is_valid_ether_addr(netdev->perm_addr)) { 2022 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2023 err = -EIO; 2024 goto err_eeprom; 2025 } 2026 2027 /* get firmware version for ethtool -i */ 2028 igb_set_fw_version(adapter); 2029 2030 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2031 (unsigned long) adapter); 2032 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2033 (unsigned long) adapter); 2034 2035 INIT_WORK(&adapter->reset_task, igb_reset_task); 2036 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2037 2038 /* Initialize link properties that are user-changeable */ 2039 adapter->fc_autoneg = true; 2040 hw->mac.autoneg = true; 2041 hw->phy.autoneg_advertised = 0x2f; 2042 2043 hw->fc.requested_mode = e1000_fc_default; 2044 hw->fc.current_mode = e1000_fc_default; 2045 2046 igb_validate_mdi_setting(hw); 2047 2048 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, 2049 * enable the ACPI Magic Packet filter 2050 */ 2051 2052 if (hw->bus.func == 0) 2053 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 2054 else if (hw->mac.type >= e1000_82580) 2055 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2056 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2057 &eeprom_data); 2058 else if (hw->bus.func == 1) 2059 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2060 2061 if (eeprom_data & eeprom_apme_mask) 2062 adapter->eeprom_wol |= E1000_WUFC_MAG; 2063 2064 /* now that we have the eeprom settings, apply the special cases where 2065 * the eeprom may be wrong or the board simply won't support wake on 2066 * lan on a particular port */ 2067 switch (pdev->device) { 2068 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2069 adapter->eeprom_wol = 0; 2070 break; 2071 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2072 case E1000_DEV_ID_82576_FIBER: 2073 case E1000_DEV_ID_82576_SERDES: 2074 /* Wake events only supported on port A for dual fiber 2075 * regardless of eeprom setting */ 2076 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2077 adapter->eeprom_wol = 0; 2078 break; 2079 case E1000_DEV_ID_82576_QUAD_COPPER: 2080 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2081 /* if quad port adapter, disable WoL on all but port A */ 2082 if (global_quad_port_a != 0) 2083 adapter->eeprom_wol = 0; 2084 else 2085 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2086 /* Reset for multiple quad port adapters */ 2087 if (++global_quad_port_a == 4) 2088 global_quad_port_a = 0; 2089 break; 2090 } 2091 2092 /* initialize the wol settings based on the eeprom settings */ 2093 adapter->wol = adapter->eeprom_wol; 2094 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2095 2096 /* reset the hardware with the new settings */ 2097 igb_reset(adapter); 2098 2099 /* let the f/w know that the h/w is now under the control of the 2100 * driver. */ 2101 igb_get_hw_control(adapter); 2102 2103 strcpy(netdev->name, "eth%d"); 2104 err = register_netdev(netdev); 2105 if (err) 2106 goto err_register; 2107 2108 /* carrier off reporting is important to ethtool even BEFORE open */ 2109 netif_carrier_off(netdev); 2110 2111#ifdef CONFIG_IGB_DCA 2112 if (dca_add_requester(&pdev->dev) == 0) { 2113 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2114 dev_info(&pdev->dev, "DCA enabled\n"); 2115 igb_setup_dca(adapter); 2116 } 2117 2118#endif 2119 2120 /* do hw tstamp init after resetting */ 2121 igb_ptp_init(adapter); 2122 2123 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2124 /* print bus type/speed/width info */ 2125 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2126 netdev->name, 2127 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2128 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2129 "unknown"), 2130 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 2131 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" : 2132 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" : 2133 "unknown"), 2134 netdev->dev_addr); 2135 2136 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH); 2137 if (ret_val) 2138 strcpy(part_str, "Unknown"); 2139 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2140 dev_info(&pdev->dev, 2141 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2142 adapter->msix_entries ? "MSI-X" : 2143 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2144 adapter->num_rx_queues, adapter->num_tx_queues); 2145 switch (hw->mac.type) { 2146 case e1000_i350: 2147 case e1000_i210: 2148 case e1000_i211: 2149 igb_set_eee_i350(hw); 2150 break; 2151 default: 2152 break; 2153 } 2154 2155 pm_runtime_put_noidle(&pdev->dev); 2156 return 0; 2157 2158err_register: 2159 igb_release_hw_control(adapter); 2160err_eeprom: 2161 if (!igb_check_reset_block(hw)) 2162 igb_reset_phy(hw); 2163 2164 if (hw->flash_address) 2165 iounmap(hw->flash_address); 2166err_sw_init: 2167 igb_clear_interrupt_scheme(adapter); 2168 iounmap(hw->hw_addr); 2169err_ioremap: 2170 free_netdev(netdev); 2171err_alloc_etherdev: 2172 pci_release_selected_regions(pdev, 2173 pci_select_bars(pdev, IORESOURCE_MEM)); 2174err_pci_reg: 2175err_dma: 2176 pci_disable_device(pdev); 2177 return err; 2178} 2179 2180/** 2181 * igb_remove - Device Removal Routine 2182 * @pdev: PCI device information struct 2183 * 2184 * igb_remove is called by the PCI subsystem to alert the driver 2185 * that it should release a PCI device. The could be caused by a 2186 * Hot-Plug event, or because the driver is going to be removed from 2187 * memory. 2188 **/ 2189static void __devexit igb_remove(struct pci_dev *pdev) 2190{ 2191 struct net_device *netdev = pci_get_drvdata(pdev); 2192 struct igb_adapter *adapter = netdev_priv(netdev); 2193 struct e1000_hw *hw = &adapter->hw; 2194 2195 pm_runtime_get_noresume(&pdev->dev); 2196 igb_ptp_stop(adapter); 2197 2198 /* 2199 * The watchdog timer may be rescheduled, so explicitly 2200 * disable watchdog from being rescheduled. 2201 */ 2202 set_bit(__IGB_DOWN, &adapter->state); 2203 del_timer_sync(&adapter->watchdog_timer); 2204 del_timer_sync(&adapter->phy_info_timer); 2205 2206 cancel_work_sync(&adapter->reset_task); 2207 cancel_work_sync(&adapter->watchdog_task); 2208 2209#ifdef CONFIG_IGB_DCA 2210 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2211 dev_info(&pdev->dev, "DCA disabled\n"); 2212 dca_remove_requester(&pdev->dev); 2213 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2214 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2215 } 2216#endif 2217 2218 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2219 * would have already happened in close and is redundant. */ 2220 igb_release_hw_control(adapter); 2221 2222 unregister_netdev(netdev); 2223 2224 igb_clear_interrupt_scheme(adapter); 2225 2226#ifdef CONFIG_PCI_IOV 2227 /* reclaim resources allocated to VFs */ 2228 if (adapter->vf_data) { 2229 /* disable iov and allow time for transactions to clear */ 2230 if (igb_vfs_are_assigned(adapter)) { 2231 dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n"); 2232 } else { 2233 pci_disable_sriov(pdev); 2234 msleep(500); 2235 } 2236 2237 kfree(adapter->vf_data); 2238 adapter->vf_data = NULL; 2239 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2240 wrfl(); 2241 msleep(100); 2242 dev_info(&pdev->dev, "IOV Disabled\n"); 2243 } 2244#endif 2245 2246 iounmap(hw->hw_addr); 2247 if (hw->flash_address) 2248 iounmap(hw->flash_address); 2249 pci_release_selected_regions(pdev, 2250 pci_select_bars(pdev, IORESOURCE_MEM)); 2251 2252 kfree(adapter->shadow_vfta); 2253 free_netdev(netdev); 2254 2255 pci_disable_pcie_error_reporting(pdev); 2256 2257 pci_disable_device(pdev); 2258} 2259 2260/** 2261 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2262 * @adapter: board private structure to initialize 2263 * 2264 * This function initializes the vf specific data storage and then attempts to 2265 * allocate the VFs. The reason for ordering it this way is because it is much 2266 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2267 * the memory for the VFs. 2268 **/ 2269static void __devinit igb_probe_vfs(struct igb_adapter * adapter) 2270{ 2271#ifdef CONFIG_PCI_IOV 2272 struct pci_dev *pdev = adapter->pdev; 2273 struct e1000_hw *hw = &adapter->hw; 2274 int old_vfs = pci_num_vf(adapter->pdev); 2275 int i; 2276 2277 /* Virtualization features not supported on i210 family. */ 2278 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2279 return; 2280 2281 if (old_vfs) { 2282 dev_info(&pdev->dev, "%d pre-allocated VFs found - override " 2283 "max_vfs setting of %d\n", old_vfs, max_vfs); 2284 adapter->vfs_allocated_count = old_vfs; 2285 } 2286 2287 if (!adapter->vfs_allocated_count) 2288 return; 2289 2290 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2291 sizeof(struct vf_data_storage), GFP_KERNEL); 2292 2293 /* if allocation failed then we do not support SR-IOV */ 2294 if (!adapter->vf_data) { 2295 adapter->vfs_allocated_count = 0; 2296 dev_err(&pdev->dev, "Unable to allocate memory for VF " 2297 "Data Storage\n"); 2298 goto out; 2299 } 2300 2301 if (!old_vfs) { 2302 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) 2303 goto err_out; 2304 } 2305 dev_info(&pdev->dev, "%d VFs allocated\n", 2306 adapter->vfs_allocated_count); 2307 for (i = 0; i < adapter->vfs_allocated_count; i++) 2308 igb_vf_configure(adapter, i); 2309 2310 /* DMA Coalescing is not supported in IOV mode. */ 2311 adapter->flags &= ~IGB_FLAG_DMAC; 2312 goto out; 2313err_out: 2314 kfree(adapter->vf_data); 2315 adapter->vf_data = NULL; 2316 adapter->vfs_allocated_count = 0; 2317out: 2318 return; 2319#endif /* CONFIG_PCI_IOV */ 2320} 2321 2322/** 2323 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2324 * @adapter: board private structure to initialize 2325 * 2326 * igb_sw_init initializes the Adapter private data structure. 2327 * Fields are initialized based on PCI device information and 2328 * OS network device settings (MTU size). 2329 **/ 2330static int __devinit igb_sw_init(struct igb_adapter *adapter) 2331{ 2332 struct e1000_hw *hw = &adapter->hw; 2333 struct net_device *netdev = adapter->netdev; 2334 struct pci_dev *pdev = adapter->pdev; 2335 u32 max_rss_queues; 2336 2337 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2338 2339 /* set default ring sizes */ 2340 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2341 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2342 2343 /* set default ITR values */ 2344 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2345 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2346 2347 /* set default work limits */ 2348 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2349 2350 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2351 VLAN_HLEN; 2352 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2353 2354 spin_lock_init(&adapter->stats64_lock); 2355#ifdef CONFIG_PCI_IOV 2356 switch (hw->mac.type) { 2357 case e1000_82576: 2358 case e1000_i350: 2359 if (max_vfs > 7) { 2360 dev_warn(&pdev->dev, 2361 "Maximum of 7 VFs per PF, using max\n"); 2362 adapter->vfs_allocated_count = 7; 2363 } else 2364 adapter->vfs_allocated_count = max_vfs; 2365 break; 2366 default: 2367 break; 2368 } 2369#endif /* CONFIG_PCI_IOV */ 2370 2371 /* Determine the maximum number of RSS queues supported. */ 2372 switch (hw->mac.type) { 2373 case e1000_i211: 2374 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2375 break; 2376 case e1000_82575: 2377 case e1000_i210: 2378 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2379 break; 2380 case e1000_i350: 2381 /* I350 cannot do RSS and SR-IOV at the same time */ 2382 if (!!adapter->vfs_allocated_count) { 2383 max_rss_queues = 1; 2384 break; 2385 } 2386 /* fall through */ 2387 case e1000_82576: 2388 if (!!adapter->vfs_allocated_count) { 2389 max_rss_queues = 2; 2390 break; 2391 } 2392 /* fall through */ 2393 case e1000_82580: 2394 default: 2395 max_rss_queues = IGB_MAX_RX_QUEUES; 2396 break; 2397 } 2398 2399 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2400 2401 /* Determine if we need to pair queues. */ 2402 switch (hw->mac.type) { 2403 case e1000_82575: 2404 case e1000_i211: 2405 /* Device supports enough interrupts without queue pairing. */ 2406 break; 2407 case e1000_82576: 2408 /* 2409 * If VFs are going to be allocated with RSS queues then we 2410 * should pair the queues in order to conserve interrupts due 2411 * to limited supply. 2412 */ 2413 if ((adapter->rss_queues > 1) && 2414 (adapter->vfs_allocated_count > 6)) 2415 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2416 /* fall through */ 2417 case e1000_82580: 2418 case e1000_i350: 2419 case e1000_i210: 2420 default: 2421 /* 2422 * If rss_queues > half of max_rss_queues, pair the queues in 2423 * order to conserve interrupts due to limited supply. 2424 */ 2425 if (adapter->rss_queues > (max_rss_queues / 2)) 2426 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2427 break; 2428 } 2429 2430 /* Setup and initialize a copy of the hw vlan table array */ 2431 adapter->shadow_vfta = kzalloc(sizeof(u32) * 2432 E1000_VLAN_FILTER_TBL_SIZE, 2433 GFP_ATOMIC); 2434 2435 /* This call may decrease the number of queues */ 2436 if (igb_init_interrupt_scheme(adapter)) { 2437 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2438 return -ENOMEM; 2439 } 2440 2441 igb_probe_vfs(adapter); 2442 2443 /* Explicitly disable IRQ since the NIC can be in any state. */ 2444 igb_irq_disable(adapter); 2445 2446 if (hw->mac.type >= e1000_i350) 2447 adapter->flags &= ~IGB_FLAG_DMAC; 2448 2449 set_bit(__IGB_DOWN, &adapter->state); 2450 return 0; 2451} 2452 2453/** 2454 * igb_open - Called when a network interface is made active 2455 * @netdev: network interface device structure 2456 * 2457 * Returns 0 on success, negative value on failure 2458 * 2459 * The open entry point is called when a network interface is made 2460 * active by the system (IFF_UP). At this point all resources needed 2461 * for transmit and receive operations are allocated, the interrupt 2462 * handler is registered with the OS, the watchdog timer is started, 2463 * and the stack is notified that the interface is ready. 2464 **/ 2465static int __igb_open(struct net_device *netdev, bool resuming) 2466{ 2467 struct igb_adapter *adapter = netdev_priv(netdev); 2468 struct e1000_hw *hw = &adapter->hw; 2469 struct pci_dev *pdev = adapter->pdev; 2470 int err; 2471 int i; 2472 2473 /* disallow open during test */ 2474 if (test_bit(__IGB_TESTING, &adapter->state)) { 2475 WARN_ON(resuming); 2476 return -EBUSY; 2477 } 2478 2479 if (!resuming) 2480 pm_runtime_get_sync(&pdev->dev); 2481 2482 netif_carrier_off(netdev); 2483 2484 /* allocate transmit descriptors */ 2485 err = igb_setup_all_tx_resources(adapter); 2486 if (err) 2487 goto err_setup_tx; 2488 2489 /* allocate receive descriptors */ 2490 err = igb_setup_all_rx_resources(adapter); 2491 if (err) 2492 goto err_setup_rx; 2493 2494 igb_power_up_link(adapter); 2495 2496 /* before we allocate an interrupt, we must be ready to handle it. 2497 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 2498 * as soon as we call pci_request_irq, so we have to setup our 2499 * clean_rx handler before we do so. */ 2500 igb_configure(adapter); 2501 2502 err = igb_request_irq(adapter); 2503 if (err) 2504 goto err_req_irq; 2505 2506 /* Notify the stack of the actual queue counts. */ 2507 err = netif_set_real_num_tx_queues(adapter->netdev, 2508 adapter->num_tx_queues); 2509 if (err) 2510 goto err_set_queues; 2511 2512 err = netif_set_real_num_rx_queues(adapter->netdev, 2513 adapter->num_rx_queues); 2514 if (err) 2515 goto err_set_queues; 2516 2517 /* From here on the code is the same as igb_up() */ 2518 clear_bit(__IGB_DOWN, &adapter->state); 2519 2520 for (i = 0; i < adapter->num_q_vectors; i++) 2521 napi_enable(&(adapter->q_vector[i]->napi)); 2522 2523 /* Clear any pending interrupts. */ 2524 rd32(E1000_ICR); 2525 2526 igb_irq_enable(adapter); 2527 2528 /* notify VFs that reset has been completed */ 2529 if (adapter->vfs_allocated_count) { 2530 u32 reg_data = rd32(E1000_CTRL_EXT); 2531 reg_data |= E1000_CTRL_EXT_PFRSTD; 2532 wr32(E1000_CTRL_EXT, reg_data); 2533 } 2534 2535 netif_tx_start_all_queues(netdev); 2536 2537 if (!resuming) 2538 pm_runtime_put(&pdev->dev); 2539 2540 /* start the watchdog. */ 2541 hw->mac.get_link_status = 1; 2542 schedule_work(&adapter->watchdog_task); 2543 2544 return 0; 2545 2546err_set_queues: 2547 igb_free_irq(adapter); 2548err_req_irq: 2549 igb_release_hw_control(adapter); 2550 igb_power_down_link(adapter); 2551 igb_free_all_rx_resources(adapter); 2552err_setup_rx: 2553 igb_free_all_tx_resources(adapter); 2554err_setup_tx: 2555 igb_reset(adapter); 2556 if (!resuming) 2557 pm_runtime_put(&pdev->dev); 2558 2559 return err; 2560} 2561 2562static int igb_open(struct net_device *netdev) 2563{ 2564 return __igb_open(netdev, false); 2565} 2566 2567/** 2568 * igb_close - Disables a network interface 2569 * @netdev: network interface device structure 2570 * 2571 * Returns 0, this is not allowed to fail 2572 * 2573 * The close entry point is called when an interface is de-activated 2574 * by the OS. The hardware is still under the driver's control, but 2575 * needs to be disabled. A global MAC reset is issued to stop the 2576 * hardware, and all transmit and receive resources are freed. 2577 **/ 2578static int __igb_close(struct net_device *netdev, bool suspending) 2579{ 2580 struct igb_adapter *adapter = netdev_priv(netdev); 2581 struct pci_dev *pdev = adapter->pdev; 2582 2583 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 2584 2585 if (!suspending) 2586 pm_runtime_get_sync(&pdev->dev); 2587 2588 igb_down(adapter); 2589 igb_free_irq(adapter); 2590 2591 igb_free_all_tx_resources(adapter); 2592 igb_free_all_rx_resources(adapter); 2593 2594 if (!suspending) 2595 pm_runtime_put_sync(&pdev->dev); 2596 return 0; 2597} 2598 2599static int igb_close(struct net_device *netdev) 2600{ 2601 return __igb_close(netdev, false); 2602} 2603 2604/** 2605 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 2606 * @tx_ring: tx descriptor ring (for a specific queue) to setup 2607 * 2608 * Return 0 on success, negative on failure 2609 **/ 2610int igb_setup_tx_resources(struct igb_ring *tx_ring) 2611{ 2612 struct device *dev = tx_ring->dev; 2613 int size; 2614 2615 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 2616 2617 tx_ring->tx_buffer_info = vzalloc(size); 2618 if (!tx_ring->tx_buffer_info) 2619 goto err; 2620 2621 /* round up to nearest 4K */ 2622 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 2623 tx_ring->size = ALIGN(tx_ring->size, 4096); 2624 2625 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2626 &tx_ring->dma, GFP_KERNEL); 2627 if (!tx_ring->desc) 2628 goto err; 2629 2630 tx_ring->next_to_use = 0; 2631 tx_ring->next_to_clean = 0; 2632 2633 return 0; 2634 2635err: 2636 vfree(tx_ring->tx_buffer_info); 2637 tx_ring->tx_buffer_info = NULL; 2638 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 2639 return -ENOMEM; 2640} 2641 2642/** 2643 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 2644 * (Descriptors) for all queues 2645 * @adapter: board private structure 2646 * 2647 * Return 0 on success, negative on failure 2648 **/ 2649static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 2650{ 2651 struct pci_dev *pdev = adapter->pdev; 2652 int i, err = 0; 2653 2654 for (i = 0; i < adapter->num_tx_queues; i++) { 2655 err = igb_setup_tx_resources(adapter->tx_ring[i]); 2656 if (err) { 2657 dev_err(&pdev->dev, 2658 "Allocation for Tx Queue %u failed\n", i); 2659 for (i--; i >= 0; i--) 2660 igb_free_tx_resources(adapter->tx_ring[i]); 2661 break; 2662 } 2663 } 2664 2665 return err; 2666} 2667 2668/** 2669 * igb_setup_tctl - configure the transmit control registers 2670 * @adapter: Board private structure 2671 **/ 2672void igb_setup_tctl(struct igb_adapter *adapter) 2673{ 2674 struct e1000_hw *hw = &adapter->hw; 2675 u32 tctl; 2676 2677 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 2678 wr32(E1000_TXDCTL(0), 0); 2679 2680 /* Program the Transmit Control Register */ 2681 tctl = rd32(E1000_TCTL); 2682 tctl &= ~E1000_TCTL_CT; 2683 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2684 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2685 2686 igb_config_collision_dist(hw); 2687 2688 /* Enable transmits */ 2689 tctl |= E1000_TCTL_EN; 2690 2691 wr32(E1000_TCTL, tctl); 2692} 2693 2694/** 2695 * igb_configure_tx_ring - Configure transmit ring after Reset 2696 * @adapter: board private structure 2697 * @ring: tx ring to configure 2698 * 2699 * Configure a transmit ring after a reset. 2700 **/ 2701void igb_configure_tx_ring(struct igb_adapter *adapter, 2702 struct igb_ring *ring) 2703{ 2704 struct e1000_hw *hw = &adapter->hw; 2705 u32 txdctl = 0; 2706 u64 tdba = ring->dma; 2707 int reg_idx = ring->reg_idx; 2708 2709 /* disable the queue */ 2710 wr32(E1000_TXDCTL(reg_idx), 0); 2711 wrfl(); 2712 mdelay(10); 2713 2714 wr32(E1000_TDLEN(reg_idx), 2715 ring->count * sizeof(union e1000_adv_tx_desc)); 2716 wr32(E1000_TDBAL(reg_idx), 2717 tdba & 0x00000000ffffffffULL); 2718 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 2719 2720 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 2721 wr32(E1000_TDH(reg_idx), 0); 2722 writel(0, ring->tail); 2723 2724 txdctl |= IGB_TX_PTHRESH; 2725 txdctl |= IGB_TX_HTHRESH << 8; 2726 txdctl |= IGB_TX_WTHRESH << 16; 2727 2728 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 2729 wr32(E1000_TXDCTL(reg_idx), txdctl); 2730} 2731 2732/** 2733 * igb_configure_tx - Configure transmit Unit after Reset 2734 * @adapter: board private structure 2735 * 2736 * Configure the Tx unit of the MAC after a reset. 2737 **/ 2738static void igb_configure_tx(struct igb_adapter *adapter) 2739{ 2740 int i; 2741 2742 for (i = 0; i < adapter->num_tx_queues; i++) 2743 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 2744} 2745 2746/** 2747 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 2748 * @rx_ring: rx descriptor ring (for a specific queue) to setup 2749 * 2750 * Returns 0 on success, negative on failure 2751 **/ 2752int igb_setup_rx_resources(struct igb_ring *rx_ring) 2753{ 2754 struct device *dev = rx_ring->dev; 2755 int size; 2756 2757 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 2758 2759 rx_ring->rx_buffer_info = vzalloc(size); 2760 if (!rx_ring->rx_buffer_info) 2761 goto err; 2762 2763 /* Round up to nearest 4K */ 2764 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 2765 rx_ring->size = ALIGN(rx_ring->size, 4096); 2766 2767 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2768 &rx_ring->dma, GFP_KERNEL); 2769 if (!rx_ring->desc) 2770 goto err; 2771 2772 rx_ring->next_to_alloc = 0; 2773 rx_ring->next_to_clean = 0; 2774 rx_ring->next_to_use = 0; 2775 2776 return 0; 2777 2778err: 2779 vfree(rx_ring->rx_buffer_info); 2780 rx_ring->rx_buffer_info = NULL; 2781 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 2782 return -ENOMEM; 2783} 2784 2785/** 2786 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 2787 * (Descriptors) for all queues 2788 * @adapter: board private structure 2789 * 2790 * Return 0 on success, negative on failure 2791 **/ 2792static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 2793{ 2794 struct pci_dev *pdev = adapter->pdev; 2795 int i, err = 0; 2796 2797 for (i = 0; i < adapter->num_rx_queues; i++) { 2798 err = igb_setup_rx_resources(adapter->rx_ring[i]); 2799 if (err) { 2800 dev_err(&pdev->dev, 2801 "Allocation for Rx Queue %u failed\n", i); 2802 for (i--; i >= 0; i--) 2803 igb_free_rx_resources(adapter->rx_ring[i]); 2804 break; 2805 } 2806 } 2807 2808 return err; 2809} 2810 2811/** 2812 * igb_setup_mrqc - configure the multiple receive queue control registers 2813 * @adapter: Board private structure 2814 **/ 2815static void igb_setup_mrqc(struct igb_adapter *adapter) 2816{ 2817 struct e1000_hw *hw = &adapter->hw; 2818 u32 mrqc, rxcsum; 2819 u32 j, num_rx_queues, shift = 0; 2820 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, 2821 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, 2822 0xA32DCB77, 0x0CF23080, 0x3BB7426A, 2823 0xFA01ACBE }; 2824 2825 /* Fill out hash function seeds */ 2826 for (j = 0; j < 10; j++) 2827 wr32(E1000_RSSRK(j), rsskey[j]); 2828 2829 num_rx_queues = adapter->rss_queues; 2830 2831 switch (hw->mac.type) { 2832 case e1000_82575: 2833 shift = 6; 2834 break; 2835 case e1000_82576: 2836 /* 82576 supports 2 RSS queues for SR-IOV */ 2837 if (adapter->vfs_allocated_count) { 2838 shift = 3; 2839 num_rx_queues = 2; 2840 } 2841 break; 2842 default: 2843 break; 2844 } 2845 2846 /* 2847 * Populate the indirection table 4 entries at a time. To do this 2848 * we are generating the results for n and n+2 and then interleaving 2849 * those with the results with n+1 and n+3. 2850 */ 2851 for (j = 0; j < 32; j++) { 2852 /* first pass generates n and n+2 */ 2853 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues; 2854 u32 reta = (base & 0x07800780) >> (7 - shift); 2855 2856 /* second pass generates n+1 and n+3 */ 2857 base += 0x00010001 * num_rx_queues; 2858 reta |= (base & 0x07800780) << (1 + shift); 2859 2860 wr32(E1000_RETA(j), reta); 2861 } 2862 2863 /* 2864 * Disable raw packet checksumming so that RSS hash is placed in 2865 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 2866 * offloads as they are enabled by default 2867 */ 2868 rxcsum = rd32(E1000_RXCSUM); 2869 rxcsum |= E1000_RXCSUM_PCSD; 2870 2871 if (adapter->hw.mac.type >= e1000_82576) 2872 /* Enable Receive Checksum Offload for SCTP */ 2873 rxcsum |= E1000_RXCSUM_CRCOFL; 2874 2875 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 2876 wr32(E1000_RXCSUM, rxcsum); 2877 2878 /* Generate RSS hash based on packet types, TCP/UDP 2879 * port numbers and/or IPv4/v6 src and dst addresses 2880 */ 2881 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 2882 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2883 E1000_MRQC_RSS_FIELD_IPV6 | 2884 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2885 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 2886 2887 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 2888 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 2889 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 2890 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 2891 2892 /* If VMDq is enabled then we set the appropriate mode for that, else 2893 * we default to RSS so that an RSS hash is calculated per packet even 2894 * if we are only using one queue */ 2895 if (adapter->vfs_allocated_count) { 2896 if (hw->mac.type > e1000_82575) { 2897 /* Set the default pool for the PF's first queue */ 2898 u32 vtctl = rd32(E1000_VT_CTL); 2899 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 2900 E1000_VT_CTL_DISABLE_DEF_POOL); 2901 vtctl |= adapter->vfs_allocated_count << 2902 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 2903 wr32(E1000_VT_CTL, vtctl); 2904 } 2905 if (adapter->rss_queues > 1) 2906 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 2907 else 2908 mrqc |= E1000_MRQC_ENABLE_VMDQ; 2909 } else { 2910 if (hw->mac.type != e1000_i211) 2911 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 2912 } 2913 igb_vmm_control(adapter); 2914 2915 wr32(E1000_MRQC, mrqc); 2916} 2917 2918/** 2919 * igb_setup_rctl - configure the receive control registers 2920 * @adapter: Board private structure 2921 **/ 2922void igb_setup_rctl(struct igb_adapter *adapter) 2923{ 2924 struct e1000_hw *hw = &adapter->hw; 2925 u32 rctl; 2926 2927 rctl = rd32(E1000_RCTL); 2928 2929 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2930 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 2931 2932 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 2933 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2934 2935 /* 2936 * enable stripping of CRC. It's unlikely this will break BMC 2937 * redirection as it did with e1000. Newer features require 2938 * that the HW strips the CRC. 2939 */ 2940 rctl |= E1000_RCTL_SECRC; 2941 2942 /* disable store bad packets and clear size bits. */ 2943 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 2944 2945 /* enable LPE to prevent packets larger than max_frame_size */ 2946 rctl |= E1000_RCTL_LPE; 2947 2948 /* disable queue 0 to prevent tail write w/o re-config */ 2949 wr32(E1000_RXDCTL(0), 0); 2950 2951 /* Attention!!! For SR-IOV PF driver operations you must enable 2952 * queue drop for all VF and PF queues to prevent head of line blocking 2953 * if an un-trusted VF does not provide descriptors to hardware. 2954 */ 2955 if (adapter->vfs_allocated_count) { 2956 /* set all queue drop enable bits */ 2957 wr32(E1000_QDE, ALL_QUEUES); 2958 } 2959 2960 /* This is useful for sniffing bad packets. */ 2961 if (adapter->netdev->features & NETIF_F_RXALL) { 2962 /* UPE and MPE will be handled by normal PROMISC logic 2963 * in e1000e_set_rx_mode */ 2964 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 2965 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 2966 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 2967 2968 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 2969 E1000_RCTL_DPF | /* Allow filtered pause */ 2970 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 2971 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 2972 * and that breaks VLANs. 2973 */ 2974 } 2975 2976 wr32(E1000_RCTL, rctl); 2977} 2978 2979static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 2980 int vfn) 2981{ 2982 struct e1000_hw *hw = &adapter->hw; 2983 u32 vmolr; 2984 2985 /* if it isn't the PF check to see if VFs are enabled and 2986 * increase the size to support vlan tags */ 2987 if (vfn < adapter->vfs_allocated_count && 2988 adapter->vf_data[vfn].vlans_enabled) 2989 size += VLAN_TAG_SIZE; 2990 2991 vmolr = rd32(E1000_VMOLR(vfn)); 2992 vmolr &= ~E1000_VMOLR_RLPML_MASK; 2993 vmolr |= size | E1000_VMOLR_LPE; 2994 wr32(E1000_VMOLR(vfn), vmolr); 2995 2996 return 0; 2997} 2998 2999/** 3000 * igb_rlpml_set - set maximum receive packet size 3001 * @adapter: board private structure 3002 * 3003 * Configure maximum receivable packet size. 3004 **/ 3005static void igb_rlpml_set(struct igb_adapter *adapter) 3006{ 3007 u32 max_frame_size = adapter->max_frame_size; 3008 struct e1000_hw *hw = &adapter->hw; 3009 u16 pf_id = adapter->vfs_allocated_count; 3010 3011 if (pf_id) { 3012 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3013 /* 3014 * If we're in VMDQ or SR-IOV mode, then set global RLPML 3015 * to our max jumbo frame size, in case we need to enable 3016 * jumbo frames on one of the rings later. 3017 * This will not pass over-length frames into the default 3018 * queue because it's gated by the VMOLR.RLPML. 3019 */ 3020 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3021 } 3022 3023 wr32(E1000_RLPML, max_frame_size); 3024} 3025 3026static inline void igb_set_vmolr(struct igb_adapter *adapter, 3027 int vfn, bool aupe) 3028{ 3029 struct e1000_hw *hw = &adapter->hw; 3030 u32 vmolr; 3031 3032 /* 3033 * This register exists only on 82576 and newer so if we are older then 3034 * we should exit and do nothing 3035 */ 3036 if (hw->mac.type < e1000_82576) 3037 return; 3038 3039 vmolr = rd32(E1000_VMOLR(vfn)); 3040 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3041 if (aupe) 3042 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3043 else 3044 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3045 3046 /* clear all bits that might not be set */ 3047 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3048 3049 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3050 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3051 /* 3052 * for VMDq only allow the VFs and pool 0 to accept broadcast and 3053 * multicast packets 3054 */ 3055 if (vfn <= adapter->vfs_allocated_count) 3056 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3057 3058 wr32(E1000_VMOLR(vfn), vmolr); 3059} 3060 3061/** 3062 * igb_configure_rx_ring - Configure a receive ring after Reset 3063 * @adapter: board private structure 3064 * @ring: receive ring to be configured 3065 * 3066 * Configure the Rx unit of the MAC after a reset. 3067 **/ 3068void igb_configure_rx_ring(struct igb_adapter *adapter, 3069 struct igb_ring *ring) 3070{ 3071 struct e1000_hw *hw = &adapter->hw; 3072 u64 rdba = ring->dma; 3073 int reg_idx = ring->reg_idx; 3074 u32 srrctl = 0, rxdctl = 0; 3075 3076 /* disable the queue */ 3077 wr32(E1000_RXDCTL(reg_idx), 0); 3078 3079 /* Set DMA base address registers */ 3080 wr32(E1000_RDBAL(reg_idx), 3081 rdba & 0x00000000ffffffffULL); 3082 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3083 wr32(E1000_RDLEN(reg_idx), 3084 ring->count * sizeof(union e1000_adv_rx_desc)); 3085 3086 /* initialize head and tail */ 3087 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3088 wr32(E1000_RDH(reg_idx), 0); 3089 writel(0, ring->tail); 3090 3091 /* set descriptor configuration */ 3092 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3093 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3094 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3095 if (hw->mac.type >= e1000_82580) 3096 srrctl |= E1000_SRRCTL_TIMESTAMP; 3097 /* Only set Drop Enable if we are supporting multiple queues */ 3098 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3099 srrctl |= E1000_SRRCTL_DROP_EN; 3100 3101 wr32(E1000_SRRCTL(reg_idx), srrctl); 3102 3103 /* set filtering for VMDQ pools */ 3104 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3105 3106 rxdctl |= IGB_RX_PTHRESH; 3107 rxdctl |= IGB_RX_HTHRESH << 8; 3108 rxdctl |= IGB_RX_WTHRESH << 16; 3109 3110 /* enable receive descriptor fetching */ 3111 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3112 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3113} 3114 3115/** 3116 * igb_configure_rx - Configure receive Unit after Reset 3117 * @adapter: board private structure 3118 * 3119 * Configure the Rx unit of the MAC after a reset. 3120 **/ 3121static void igb_configure_rx(struct igb_adapter *adapter) 3122{ 3123 int i; 3124 3125 /* set UTA to appropriate mode */ 3126 igb_set_uta(adapter); 3127 3128 /* set the correct pool for the PF default MAC address in entry 0 */ 3129 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3130 adapter->vfs_allocated_count); 3131 3132 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3133 * the Base and Length of the Rx Descriptor Ring */ 3134 for (i = 0; i < adapter->num_rx_queues; i++) 3135 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3136} 3137 3138/** 3139 * igb_free_tx_resources - Free Tx Resources per Queue 3140 * @tx_ring: Tx descriptor ring for a specific queue 3141 * 3142 * Free all transmit software resources 3143 **/ 3144void igb_free_tx_resources(struct igb_ring *tx_ring) 3145{ 3146 igb_clean_tx_ring(tx_ring); 3147 3148 vfree(tx_ring->tx_buffer_info); 3149 tx_ring->tx_buffer_info = NULL; 3150 3151 /* if not set, then don't free */ 3152 if (!tx_ring->desc) 3153 return; 3154 3155 dma_free_coherent(tx_ring->dev, tx_ring->size, 3156 tx_ring->desc, tx_ring->dma); 3157 3158 tx_ring->desc = NULL; 3159} 3160 3161/** 3162 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3163 * @adapter: board private structure 3164 * 3165 * Free all transmit software resources 3166 **/ 3167static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3168{ 3169 int i; 3170 3171 for (i = 0; i < adapter->num_tx_queues; i++) 3172 igb_free_tx_resources(adapter->tx_ring[i]); 3173} 3174 3175void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3176 struct igb_tx_buffer *tx_buffer) 3177{ 3178 if (tx_buffer->skb) { 3179 dev_kfree_skb_any(tx_buffer->skb); 3180 if (dma_unmap_len(tx_buffer, len)) 3181 dma_unmap_single(ring->dev, 3182 dma_unmap_addr(tx_buffer, dma), 3183 dma_unmap_len(tx_buffer, len), 3184 DMA_TO_DEVICE); 3185 } else if (dma_unmap_len(tx_buffer, len)) { 3186 dma_unmap_page(ring->dev, 3187 dma_unmap_addr(tx_buffer, dma), 3188 dma_unmap_len(tx_buffer, len), 3189 DMA_TO_DEVICE); 3190 } 3191 tx_buffer->next_to_watch = NULL; 3192 tx_buffer->skb = NULL; 3193 dma_unmap_len_set(tx_buffer, len, 0); 3194 /* buffer_info must be completely set up in the transmit path */ 3195} 3196 3197/** 3198 * igb_clean_tx_ring - Free Tx Buffers 3199 * @tx_ring: ring to be cleaned 3200 **/ 3201static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3202{ 3203 struct igb_tx_buffer *buffer_info; 3204 unsigned long size; 3205 u16 i; 3206 3207 if (!tx_ring->tx_buffer_info) 3208 return; 3209 /* Free all the Tx ring sk_buffs */ 3210 3211 for (i = 0; i < tx_ring->count; i++) { 3212 buffer_info = &tx_ring->tx_buffer_info[i]; 3213 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3214 } 3215 3216 netdev_tx_reset_queue(txring_txq(tx_ring)); 3217 3218 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3219 memset(tx_ring->tx_buffer_info, 0, size); 3220 3221 /* Zero out the descriptor ring */ 3222 memset(tx_ring->desc, 0, tx_ring->size); 3223 3224 tx_ring->next_to_use = 0; 3225 tx_ring->next_to_clean = 0; 3226} 3227 3228/** 3229 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3230 * @adapter: board private structure 3231 **/ 3232static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3233{ 3234 int i; 3235 3236 for (i = 0; i < adapter->num_tx_queues; i++) 3237 igb_clean_tx_ring(adapter->tx_ring[i]); 3238} 3239 3240/** 3241 * igb_free_rx_resources - Free Rx Resources 3242 * @rx_ring: ring to clean the resources from 3243 * 3244 * Free all receive software resources 3245 **/ 3246void igb_free_rx_resources(struct igb_ring *rx_ring) 3247{ 3248 igb_clean_rx_ring(rx_ring); 3249 3250 vfree(rx_ring->rx_buffer_info); 3251 rx_ring->rx_buffer_info = NULL; 3252 3253 /* if not set, then don't free */ 3254 if (!rx_ring->desc) 3255 return; 3256 3257 dma_free_coherent(rx_ring->dev, rx_ring->size, 3258 rx_ring->desc, rx_ring->dma); 3259 3260 rx_ring->desc = NULL; 3261} 3262 3263/** 3264 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3265 * @adapter: board private structure 3266 * 3267 * Free all receive software resources 3268 **/ 3269static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3270{ 3271 int i; 3272 3273 for (i = 0; i < adapter->num_rx_queues; i++) 3274 igb_free_rx_resources(adapter->rx_ring[i]); 3275} 3276 3277/** 3278 * igb_clean_rx_ring - Free Rx Buffers per Queue 3279 * @rx_ring: ring to free buffers from 3280 **/ 3281static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3282{ 3283 unsigned long size; 3284 u16 i; 3285 3286 if (rx_ring->skb) 3287 dev_kfree_skb(rx_ring->skb); 3288 rx_ring->skb = NULL; 3289 3290 if (!rx_ring->rx_buffer_info) 3291 return; 3292 3293 /* Free all the Rx ring sk_buffs */ 3294 for (i = 0; i < rx_ring->count; i++) { 3295 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3296 3297 if (!buffer_info->page) 3298 continue; 3299 3300 dma_unmap_page(rx_ring->dev, 3301 buffer_info->dma, 3302 PAGE_SIZE, 3303 DMA_FROM_DEVICE); 3304 __free_page(buffer_info->page); 3305 3306 buffer_info->page = NULL; 3307 } 3308 3309 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3310 memset(rx_ring->rx_buffer_info, 0, size); 3311 3312 /* Zero out the descriptor ring */ 3313 memset(rx_ring->desc, 0, rx_ring->size); 3314 3315 rx_ring->next_to_alloc = 0; 3316 rx_ring->next_to_clean = 0; 3317 rx_ring->next_to_use = 0; 3318} 3319 3320/** 3321 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3322 * @adapter: board private structure 3323 **/ 3324static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3325{ 3326 int i; 3327 3328 for (i = 0; i < adapter->num_rx_queues; i++) 3329 igb_clean_rx_ring(adapter->rx_ring[i]); 3330} 3331 3332/** 3333 * igb_set_mac - Change the Ethernet Address of the NIC 3334 * @netdev: network interface device structure 3335 * @p: pointer to an address structure 3336 * 3337 * Returns 0 on success, negative on failure 3338 **/ 3339static int igb_set_mac(struct net_device *netdev, void *p) 3340{ 3341 struct igb_adapter *adapter = netdev_priv(netdev); 3342 struct e1000_hw *hw = &adapter->hw; 3343 struct sockaddr *addr = p; 3344 3345 if (!is_valid_ether_addr(addr->sa_data)) 3346 return -EADDRNOTAVAIL; 3347 3348 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3349 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3350 3351 /* set the correct pool for the new PF MAC address in entry 0 */ 3352 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3353 adapter->vfs_allocated_count); 3354 3355 return 0; 3356} 3357 3358/** 3359 * igb_write_mc_addr_list - write multicast addresses to MTA 3360 * @netdev: network interface device structure 3361 * 3362 * Writes multicast address list to the MTA hash table. 3363 * Returns: -ENOMEM on failure 3364 * 0 on no addresses written 3365 * X on writing X addresses to MTA 3366 **/ 3367static int igb_write_mc_addr_list(struct net_device *netdev) 3368{ 3369 struct igb_adapter *adapter = netdev_priv(netdev); 3370 struct e1000_hw *hw = &adapter->hw; 3371 struct netdev_hw_addr *ha; 3372 u8 *mta_list; 3373 int i; 3374 3375 if (netdev_mc_empty(netdev)) { 3376 /* nothing to program, so clear mc list */ 3377 igb_update_mc_addr_list(hw, NULL, 0); 3378 igb_restore_vf_multicasts(adapter); 3379 return 0; 3380 } 3381 3382 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3383 if (!mta_list) 3384 return -ENOMEM; 3385 3386 /* The shared function expects a packed array of only addresses. */ 3387 i = 0; 3388 netdev_for_each_mc_addr(ha, netdev) 3389 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3390 3391 igb_update_mc_addr_list(hw, mta_list, i); 3392 kfree(mta_list); 3393 3394 return netdev_mc_count(netdev); 3395} 3396 3397/** 3398 * igb_write_uc_addr_list - write unicast addresses to RAR table 3399 * @netdev: network interface device structure 3400 * 3401 * Writes unicast address list to the RAR table. 3402 * Returns: -ENOMEM on failure/insufficient address space 3403 * 0 on no addresses written 3404 * X on writing X addresses to the RAR table 3405 **/ 3406static int igb_write_uc_addr_list(struct net_device *netdev) 3407{ 3408 struct igb_adapter *adapter = netdev_priv(netdev); 3409 struct e1000_hw *hw = &adapter->hw; 3410 unsigned int vfn = adapter->vfs_allocated_count; 3411 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3412 int count = 0; 3413 3414 /* return ENOMEM indicating insufficient memory for addresses */ 3415 if (netdev_uc_count(netdev) > rar_entries) 3416 return -ENOMEM; 3417 3418 if (!netdev_uc_empty(netdev) && rar_entries) { 3419 struct netdev_hw_addr *ha; 3420 3421 netdev_for_each_uc_addr(ha, netdev) { 3422 if (!rar_entries) 3423 break; 3424 igb_rar_set_qsel(adapter, ha->addr, 3425 rar_entries--, 3426 vfn); 3427 count++; 3428 } 3429 } 3430 /* write the addresses in reverse order to avoid write combining */ 3431 for (; rar_entries > 0 ; rar_entries--) { 3432 wr32(E1000_RAH(rar_entries), 0); 3433 wr32(E1000_RAL(rar_entries), 0); 3434 } 3435 wrfl(); 3436 3437 return count; 3438} 3439 3440/** 3441 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3442 * @netdev: network interface device structure 3443 * 3444 * The set_rx_mode entry point is called whenever the unicast or multicast 3445 * address lists or the network interface flags are updated. This routine is 3446 * responsible for configuring the hardware for proper unicast, multicast, 3447 * promiscuous mode, and all-multi behavior. 3448 **/ 3449static void igb_set_rx_mode(struct net_device *netdev) 3450{ 3451 struct igb_adapter *adapter = netdev_priv(netdev); 3452 struct e1000_hw *hw = &adapter->hw; 3453 unsigned int vfn = adapter->vfs_allocated_count; 3454 u32 rctl, vmolr = 0; 3455 int count; 3456 3457 /* Check for Promiscuous and All Multicast modes */ 3458 rctl = rd32(E1000_RCTL); 3459 3460 /* clear the effected bits */ 3461 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 3462 3463 if (netdev->flags & IFF_PROMISC) { 3464 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3465 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 3466 } else { 3467 if (netdev->flags & IFF_ALLMULTI) { 3468 rctl |= E1000_RCTL_MPE; 3469 vmolr |= E1000_VMOLR_MPME; 3470 } else { 3471 /* 3472 * Write addresses to the MTA, if the attempt fails 3473 * then we should just turn on promiscuous mode so 3474 * that we can at least receive multicast traffic 3475 */ 3476 count = igb_write_mc_addr_list(netdev); 3477 if (count < 0) { 3478 rctl |= E1000_RCTL_MPE; 3479 vmolr |= E1000_VMOLR_MPME; 3480 } else if (count) { 3481 vmolr |= E1000_VMOLR_ROMPE; 3482 } 3483 } 3484 /* 3485 * Write addresses to available RAR registers, if there is not 3486 * sufficient space to store all the addresses then enable 3487 * unicast promiscuous mode 3488 */ 3489 count = igb_write_uc_addr_list(netdev); 3490 if (count < 0) { 3491 rctl |= E1000_RCTL_UPE; 3492 vmolr |= E1000_VMOLR_ROPE; 3493 } 3494 rctl |= E1000_RCTL_VFE; 3495 } 3496 wr32(E1000_RCTL, rctl); 3497 3498 /* 3499 * In order to support SR-IOV and eventually VMDq it is necessary to set 3500 * the VMOLR to enable the appropriate modes. Without this workaround 3501 * we will have issues with VLAN tag stripping not being done for frames 3502 * that are only arriving because we are the default pool 3503 */ 3504 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 3505 return; 3506 3507 vmolr |= rd32(E1000_VMOLR(vfn)) & 3508 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 3509 wr32(E1000_VMOLR(vfn), vmolr); 3510 igb_restore_vf_multicasts(adapter); 3511} 3512 3513static void igb_check_wvbr(struct igb_adapter *adapter) 3514{ 3515 struct e1000_hw *hw = &adapter->hw; 3516 u32 wvbr = 0; 3517 3518 switch (hw->mac.type) { 3519 case e1000_82576: 3520 case e1000_i350: 3521 if (!(wvbr = rd32(E1000_WVBR))) 3522 return; 3523 break; 3524 default: 3525 break; 3526 } 3527 3528 adapter->wvbr |= wvbr; 3529} 3530 3531#define IGB_STAGGERED_QUEUE_OFFSET 8 3532 3533static void igb_spoof_check(struct igb_adapter *adapter) 3534{ 3535 int j; 3536 3537 if (!adapter->wvbr) 3538 return; 3539 3540 for(j = 0; j < adapter->vfs_allocated_count; j++) { 3541 if (adapter->wvbr & (1 << j) || 3542 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 3543 dev_warn(&adapter->pdev->dev, 3544 "Spoof event(s) detected on VF %d\n", j); 3545 adapter->wvbr &= 3546 ~((1 << j) | 3547 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 3548 } 3549 } 3550} 3551 3552/* Need to wait a few seconds after link up to get diagnostic information from 3553 * the phy */ 3554static void igb_update_phy_info(unsigned long data) 3555{ 3556 struct igb_adapter *adapter = (struct igb_adapter *) data; 3557 igb_get_phy_info(&adapter->hw); 3558} 3559 3560/** 3561 * igb_has_link - check shared code for link and determine up/down 3562 * @adapter: pointer to driver private info 3563 **/ 3564bool igb_has_link(struct igb_adapter *adapter) 3565{ 3566 struct e1000_hw *hw = &adapter->hw; 3567 bool link_active = false; 3568 s32 ret_val = 0; 3569 3570 /* get_link_status is set on LSC (link status) interrupt or 3571 * rx sequence error interrupt. get_link_status will stay 3572 * false until the e1000_check_for_link establishes link 3573 * for copper adapters ONLY 3574 */ 3575 switch (hw->phy.media_type) { 3576 case e1000_media_type_copper: 3577 if (hw->mac.get_link_status) { 3578 ret_val = hw->mac.ops.check_for_link(hw); 3579 link_active = !hw->mac.get_link_status; 3580 } else { 3581 link_active = true; 3582 } 3583 break; 3584 case e1000_media_type_internal_serdes: 3585 ret_val = hw->mac.ops.check_for_link(hw); 3586 link_active = hw->mac.serdes_has_link; 3587 break; 3588 default: 3589 case e1000_media_type_unknown: 3590 break; 3591 } 3592 3593 return link_active; 3594} 3595 3596static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 3597{ 3598 bool ret = false; 3599 u32 ctrl_ext, thstat; 3600 3601 /* check for thermal sensor event on i350 copper only */ 3602 if (hw->mac.type == e1000_i350) { 3603 thstat = rd32(E1000_THSTAT); 3604 ctrl_ext = rd32(E1000_CTRL_EXT); 3605 3606 if ((hw->phy.media_type == e1000_media_type_copper) && 3607 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3608 ret = !!(thstat & event); 3609 } 3610 } 3611 3612 return ret; 3613} 3614 3615/** 3616 * igb_watchdog - Timer Call-back 3617 * @data: pointer to adapter cast into an unsigned long 3618 **/ 3619static void igb_watchdog(unsigned long data) 3620{ 3621 struct igb_adapter *adapter = (struct igb_adapter *)data; 3622 /* Do the rest outside of interrupt context */ 3623 schedule_work(&adapter->watchdog_task); 3624} 3625 3626static void igb_watchdog_task(struct work_struct *work) 3627{ 3628 struct igb_adapter *adapter = container_of(work, 3629 struct igb_adapter, 3630 watchdog_task); 3631 struct e1000_hw *hw = &adapter->hw; 3632 struct net_device *netdev = adapter->netdev; 3633 u32 link; 3634 int i; 3635 3636 link = igb_has_link(adapter); 3637 if (link) { 3638 /* Cancel scheduled suspend requests. */ 3639 pm_runtime_resume(netdev->dev.parent); 3640 3641 if (!netif_carrier_ok(netdev)) { 3642 u32 ctrl; 3643 hw->mac.ops.get_speed_and_duplex(hw, 3644 &adapter->link_speed, 3645 &adapter->link_duplex); 3646 3647 ctrl = rd32(E1000_CTRL); 3648 /* Links status message must follow this format */ 3649 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s " 3650 "Duplex, Flow Control: %s\n", 3651 netdev->name, 3652 adapter->link_speed, 3653 adapter->link_duplex == FULL_DUPLEX ? 3654 "Full" : "Half", 3655 (ctrl & E1000_CTRL_TFCE) && 3656 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 3657 (ctrl & E1000_CTRL_RFCE) ? "RX" : 3658 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 3659 3660 /* check for thermal sensor event */ 3661 if (igb_thermal_sensor_event(hw, 3662 E1000_THSTAT_LINK_THROTTLE)) { 3663 netdev_info(netdev, "The network adapter link " 3664 "speed was downshifted because it " 3665 "overheated\n"); 3666 } 3667 3668 /* adjust timeout factor according to speed/duplex */ 3669 adapter->tx_timeout_factor = 1; 3670 switch (adapter->link_speed) { 3671 case SPEED_10: 3672 adapter->tx_timeout_factor = 14; 3673 break; 3674 case SPEED_100: 3675 /* maybe add some timeout factor ? */ 3676 break; 3677 } 3678 3679 netif_carrier_on(netdev); 3680 3681 igb_ping_all_vfs(adapter); 3682 igb_check_vf_rate_limit(adapter); 3683 3684 /* link state has changed, schedule phy info update */ 3685 if (!test_bit(__IGB_DOWN, &adapter->state)) 3686 mod_timer(&adapter->phy_info_timer, 3687 round_jiffies(jiffies + 2 * HZ)); 3688 } 3689 } else { 3690 if (netif_carrier_ok(netdev)) { 3691 adapter->link_speed = 0; 3692 adapter->link_duplex = 0; 3693 3694 /* check for thermal sensor event */ 3695 if (igb_thermal_sensor_event(hw, 3696 E1000_THSTAT_PWR_DOWN)) { 3697 netdev_err(netdev, "The network adapter was " 3698 "stopped because it overheated\n"); 3699 } 3700 3701 /* Links status message must follow this format */ 3702 printk(KERN_INFO "igb: %s NIC Link is Down\n", 3703 netdev->name); 3704 netif_carrier_off(netdev); 3705 3706 igb_ping_all_vfs(adapter); 3707 3708 /* link state has changed, schedule phy info update */ 3709 if (!test_bit(__IGB_DOWN, &adapter->state)) 3710 mod_timer(&adapter->phy_info_timer, 3711 round_jiffies(jiffies + 2 * HZ)); 3712 3713 pm_schedule_suspend(netdev->dev.parent, 3714 MSEC_PER_SEC * 5); 3715 } 3716 } 3717 3718 spin_lock(&adapter->stats64_lock); 3719 igb_update_stats(adapter, &adapter->stats64); 3720 spin_unlock(&adapter->stats64_lock); 3721 3722 for (i = 0; i < adapter->num_tx_queues; i++) { 3723 struct igb_ring *tx_ring = adapter->tx_ring[i]; 3724 if (!netif_carrier_ok(netdev)) { 3725 /* We've lost link, so the controller stops DMA, 3726 * but we've got queued Tx work that's never going 3727 * to get done, so reset controller to flush Tx. 3728 * (Do the reset outside of interrupt context). */ 3729 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 3730 adapter->tx_timeout_count++; 3731 schedule_work(&adapter->reset_task); 3732 /* return immediately since reset is imminent */ 3733 return; 3734 } 3735 } 3736 3737 /* Force detection of hung controller every watchdog period */ 3738 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 3739 } 3740 3741 /* Cause software interrupt to ensure rx ring is cleaned */ 3742 if (adapter->msix_entries) { 3743 u32 eics = 0; 3744 for (i = 0; i < adapter->num_q_vectors; i++) 3745 eics |= adapter->q_vector[i]->eims_value; 3746 wr32(E1000_EICS, eics); 3747 } else { 3748 wr32(E1000_ICS, E1000_ICS_RXDMT0); 3749 } 3750 3751 igb_spoof_check(adapter); 3752 3753 /* Reset the timer */ 3754 if (!test_bit(__IGB_DOWN, &adapter->state)) 3755 mod_timer(&adapter->watchdog_timer, 3756 round_jiffies(jiffies + 2 * HZ)); 3757} 3758 3759enum latency_range { 3760 lowest_latency = 0, 3761 low_latency = 1, 3762 bulk_latency = 2, 3763 latency_invalid = 255 3764}; 3765 3766/** 3767 * igb_update_ring_itr - update the dynamic ITR value based on packet size 3768 * 3769 * Stores a new ITR value based on strictly on packet size. This 3770 * algorithm is less sophisticated than that used in igb_update_itr, 3771 * due to the difficulty of synchronizing statistics across multiple 3772 * receive rings. The divisors and thresholds used by this function 3773 * were determined based on theoretical maximum wire speed and testing 3774 * data, in order to minimize response time while increasing bulk 3775 * throughput. 3776 * This functionality is controlled by the InterruptThrottleRate module 3777 * parameter (see igb_param.c) 3778 * NOTE: This function is called only when operating in a multiqueue 3779 * receive environment. 3780 * @q_vector: pointer to q_vector 3781 **/ 3782static void igb_update_ring_itr(struct igb_q_vector *q_vector) 3783{ 3784 int new_val = q_vector->itr_val; 3785 int avg_wire_size = 0; 3786 struct igb_adapter *adapter = q_vector->adapter; 3787 unsigned int packets; 3788 3789 /* For non-gigabit speeds, just fix the interrupt rate at 4000 3790 * ints/sec - ITR timer value of 120 ticks. 3791 */ 3792 if (adapter->link_speed != SPEED_1000) { 3793 new_val = IGB_4K_ITR; 3794 goto set_itr_val; 3795 } 3796 3797 packets = q_vector->rx.total_packets; 3798 if (packets) 3799 avg_wire_size = q_vector->rx.total_bytes / packets; 3800 3801 packets = q_vector->tx.total_packets; 3802 if (packets) 3803 avg_wire_size = max_t(u32, avg_wire_size, 3804 q_vector->tx.total_bytes / packets); 3805 3806 /* if avg_wire_size isn't set no work was done */ 3807 if (!avg_wire_size) 3808 goto clear_counts; 3809 3810 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 3811 avg_wire_size += 24; 3812 3813 /* Don't starve jumbo frames */ 3814 avg_wire_size = min(avg_wire_size, 3000); 3815 3816 /* Give a little boost to mid-size frames */ 3817 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 3818 new_val = avg_wire_size / 3; 3819 else 3820 new_val = avg_wire_size / 2; 3821 3822 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 3823 if (new_val < IGB_20K_ITR && 3824 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 3825 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 3826 new_val = IGB_20K_ITR; 3827 3828set_itr_val: 3829 if (new_val != q_vector->itr_val) { 3830 q_vector->itr_val = new_val; 3831 q_vector->set_itr = 1; 3832 } 3833clear_counts: 3834 q_vector->rx.total_bytes = 0; 3835 q_vector->rx.total_packets = 0; 3836 q_vector->tx.total_bytes = 0; 3837 q_vector->tx.total_packets = 0; 3838} 3839 3840/** 3841 * igb_update_itr - update the dynamic ITR value based on statistics 3842 * Stores a new ITR value based on packets and byte 3843 * counts during the last interrupt. The advantage of per interrupt 3844 * computation is faster updates and more accurate ITR for the current 3845 * traffic pattern. Constants in this function were computed 3846 * based on theoretical maximum wire speed and thresholds were set based 3847 * on testing data as well as attempting to minimize response time 3848 * while increasing bulk throughput. 3849 * this functionality is controlled by the InterruptThrottleRate module 3850 * parameter (see igb_param.c) 3851 * NOTE: These calculations are only valid when operating in a single- 3852 * queue environment. 3853 * @q_vector: pointer to q_vector 3854 * @ring_container: ring info to update the itr for 3855 **/ 3856static void igb_update_itr(struct igb_q_vector *q_vector, 3857 struct igb_ring_container *ring_container) 3858{ 3859 unsigned int packets = ring_container->total_packets; 3860 unsigned int bytes = ring_container->total_bytes; 3861 u8 itrval = ring_container->itr; 3862 3863 /* no packets, exit with status unchanged */ 3864 if (packets == 0) 3865 return; 3866 3867 switch (itrval) { 3868 case lowest_latency: 3869 /* handle TSO and jumbo frames */ 3870 if (bytes/packets > 8000) 3871 itrval = bulk_latency; 3872 else if ((packets < 5) && (bytes > 512)) 3873 itrval = low_latency; 3874 break; 3875 case low_latency: /* 50 usec aka 20000 ints/s */ 3876 if (bytes > 10000) { 3877 /* this if handles the TSO accounting */ 3878 if (bytes/packets > 8000) { 3879 itrval = bulk_latency; 3880 } else if ((packets < 10) || ((bytes/packets) > 1200)) { 3881 itrval = bulk_latency; 3882 } else if ((packets > 35)) { 3883 itrval = lowest_latency; 3884 } 3885 } else if (bytes/packets > 2000) { 3886 itrval = bulk_latency; 3887 } else if (packets <= 2 && bytes < 512) { 3888 itrval = lowest_latency; 3889 } 3890 break; 3891 case bulk_latency: /* 250 usec aka 4000 ints/s */ 3892 if (bytes > 25000) { 3893 if (packets > 35) 3894 itrval = low_latency; 3895 } else if (bytes < 1500) { 3896 itrval = low_latency; 3897 } 3898 break; 3899 } 3900 3901 /* clear work counters since we have the values we need */ 3902 ring_container->total_bytes = 0; 3903 ring_container->total_packets = 0; 3904 3905 /* write updated itr to ring container */ 3906 ring_container->itr = itrval; 3907} 3908 3909static void igb_set_itr(struct igb_q_vector *q_vector) 3910{ 3911 struct igb_adapter *adapter = q_vector->adapter; 3912 u32 new_itr = q_vector->itr_val; 3913 u8 current_itr = 0; 3914 3915 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 3916 if (adapter->link_speed != SPEED_1000) { 3917 current_itr = 0; 3918 new_itr = IGB_4K_ITR; 3919 goto set_itr_now; 3920 } 3921 3922 igb_update_itr(q_vector, &q_vector->tx); 3923 igb_update_itr(q_vector, &q_vector->rx); 3924 3925 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 3926 3927 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 3928 if (current_itr == lowest_latency && 3929 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 3930 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 3931 current_itr = low_latency; 3932 3933 switch (current_itr) { 3934 /* counts and packets in update_itr are dependent on these numbers */ 3935 case lowest_latency: 3936 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 3937 break; 3938 case low_latency: 3939 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 3940 break; 3941 case bulk_latency: 3942 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 3943 break; 3944 default: 3945 break; 3946 } 3947 3948set_itr_now: 3949 if (new_itr != q_vector->itr_val) { 3950 /* this attempts to bias the interrupt rate towards Bulk 3951 * by adding intermediate steps when interrupt rate is 3952 * increasing */ 3953 new_itr = new_itr > q_vector->itr_val ? 3954 max((new_itr * q_vector->itr_val) / 3955 (new_itr + (q_vector->itr_val >> 2)), 3956 new_itr) : 3957 new_itr; 3958 /* Don't write the value here; it resets the adapter's 3959 * internal timer, and causes us to delay far longer than 3960 * we should between interrupts. Instead, we write the ITR 3961 * value at the beginning of the next interrupt so the timing 3962 * ends up being correct. 3963 */ 3964 q_vector->itr_val = new_itr; 3965 q_vector->set_itr = 1; 3966 } 3967} 3968 3969static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 3970 u32 type_tucmd, u32 mss_l4len_idx) 3971{ 3972 struct e1000_adv_tx_context_desc *context_desc; 3973 u16 i = tx_ring->next_to_use; 3974 3975 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 3976 3977 i++; 3978 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 3979 3980 /* set bits to identify this as an advanced context descriptor */ 3981 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 3982 3983 /* For 82575, context index must be unique per ring. */ 3984 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 3985 mss_l4len_idx |= tx_ring->reg_idx << 4; 3986 3987 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 3988 context_desc->seqnum_seed = 0; 3989 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 3990 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 3991} 3992 3993static int igb_tso(struct igb_ring *tx_ring, 3994 struct igb_tx_buffer *first, 3995 u8 *hdr_len) 3996{ 3997 struct sk_buff *skb = first->skb; 3998 u32 vlan_macip_lens, type_tucmd; 3999 u32 mss_l4len_idx, l4len; 4000 4001 if (!skb_is_gso(skb)) 4002 return 0; 4003 4004 if (skb_header_cloned(skb)) { 4005 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 4006 if (err) 4007 return err; 4008 } 4009 4010 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4011 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4012 4013 if (first->protocol == __constant_htons(ETH_P_IP)) { 4014 struct iphdr *iph = ip_hdr(skb); 4015 iph->tot_len = 0; 4016 iph->check = 0; 4017 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4018 iph->daddr, 0, 4019 IPPROTO_TCP, 4020 0); 4021 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4022 first->tx_flags |= IGB_TX_FLAGS_TSO | 4023 IGB_TX_FLAGS_CSUM | 4024 IGB_TX_FLAGS_IPV4; 4025 } else if (skb_is_gso_v6(skb)) { 4026 ipv6_hdr(skb)->payload_len = 0; 4027 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4028 &ipv6_hdr(skb)->daddr, 4029 0, IPPROTO_TCP, 0); 4030 first->tx_flags |= IGB_TX_FLAGS_TSO | 4031 IGB_TX_FLAGS_CSUM; 4032 } 4033 4034 /* compute header lengths */ 4035 l4len = tcp_hdrlen(skb); 4036 *hdr_len = skb_transport_offset(skb) + l4len; 4037 4038 /* update gso size and bytecount with header size */ 4039 first->gso_segs = skb_shinfo(skb)->gso_segs; 4040 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4041 4042 /* MSS L4LEN IDX */ 4043 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4044 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4045 4046 /* VLAN MACLEN IPLEN */ 4047 vlan_macip_lens = skb_network_header_len(skb); 4048 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4049 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4050 4051 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4052 4053 return 1; 4054} 4055 4056static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4057{ 4058 struct sk_buff *skb = first->skb; 4059 u32 vlan_macip_lens = 0; 4060 u32 mss_l4len_idx = 0; 4061 u32 type_tucmd = 0; 4062 4063 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4064 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4065 return; 4066 } else { 4067 u8 l4_hdr = 0; 4068 switch (first->protocol) { 4069 case __constant_htons(ETH_P_IP): 4070 vlan_macip_lens |= skb_network_header_len(skb); 4071 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4072 l4_hdr = ip_hdr(skb)->protocol; 4073 break; 4074 case __constant_htons(ETH_P_IPV6): 4075 vlan_macip_lens |= skb_network_header_len(skb); 4076 l4_hdr = ipv6_hdr(skb)->nexthdr; 4077 break; 4078 default: 4079 if (unlikely(net_ratelimit())) { 4080 dev_warn(tx_ring->dev, 4081 "partial checksum but proto=%x!\n", 4082 first->protocol); 4083 } 4084 break; 4085 } 4086 4087 switch (l4_hdr) { 4088 case IPPROTO_TCP: 4089 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4090 mss_l4len_idx = tcp_hdrlen(skb) << 4091 E1000_ADVTXD_L4LEN_SHIFT; 4092 break; 4093 case IPPROTO_SCTP: 4094 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4095 mss_l4len_idx = sizeof(struct sctphdr) << 4096 E1000_ADVTXD_L4LEN_SHIFT; 4097 break; 4098 case IPPROTO_UDP: 4099 mss_l4len_idx = sizeof(struct udphdr) << 4100 E1000_ADVTXD_L4LEN_SHIFT; 4101 break; 4102 default: 4103 if (unlikely(net_ratelimit())) { 4104 dev_warn(tx_ring->dev, 4105 "partial checksum but l4 proto=%x!\n", 4106 l4_hdr); 4107 } 4108 break; 4109 } 4110 4111 /* update TX checksum flag */ 4112 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4113 } 4114 4115 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4116 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4117 4118 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4119} 4120 4121static __le32 igb_tx_cmd_type(u32 tx_flags) 4122{ 4123 /* set type for advanced descriptor with frame checksum insertion */ 4124 __le32 cmd_type = cpu_to_le32(E1000_ADVTXD_DTYP_DATA | 4125 E1000_ADVTXD_DCMD_IFCS | 4126 E1000_ADVTXD_DCMD_DEXT); 4127 4128 /* set HW vlan bit if vlan is present */ 4129 if (tx_flags & IGB_TX_FLAGS_VLAN) 4130 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_VLE); 4131 4132 /* set timestamp bit if present */ 4133 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) 4134 cmd_type |= cpu_to_le32(E1000_ADVTXD_MAC_TSTAMP); 4135 4136 /* set segmentation bits for TSO */ 4137 if (tx_flags & IGB_TX_FLAGS_TSO) 4138 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_TSE); 4139 4140 return cmd_type; 4141} 4142 4143static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4144 union e1000_adv_tx_desc *tx_desc, 4145 u32 tx_flags, unsigned int paylen) 4146{ 4147 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4148 4149 /* 82575 requires a unique index per ring if any offload is enabled */ 4150 if ((tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_VLAN)) && 4151 test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4152 olinfo_status |= tx_ring->reg_idx << 4; 4153 4154 /* insert L4 checksum */ 4155 if (tx_flags & IGB_TX_FLAGS_CSUM) { 4156 olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 4157 4158 /* insert IPv4 checksum */ 4159 if (tx_flags & IGB_TX_FLAGS_IPV4) 4160 olinfo_status |= E1000_TXD_POPTS_IXSM << 8; 4161 } 4162 4163 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4164} 4165 4166/* 4167 * The largest size we can write to the descriptor is 65535. In order to 4168 * maintain a power of two alignment we have to limit ourselves to 32K. 4169 */ 4170#define IGB_MAX_TXD_PWR 15 4171#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) 4172 4173static void igb_tx_map(struct igb_ring *tx_ring, 4174 struct igb_tx_buffer *first, 4175 const u8 hdr_len) 4176{ 4177 struct sk_buff *skb = first->skb; 4178 struct igb_tx_buffer *tx_buffer; 4179 union e1000_adv_tx_desc *tx_desc; 4180 dma_addr_t dma; 4181 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 4182 unsigned int data_len = skb->data_len; 4183 unsigned int size = skb_headlen(skb); 4184 unsigned int paylen = skb->len - hdr_len; 4185 __le32 cmd_type; 4186 u32 tx_flags = first->tx_flags; 4187 u16 i = tx_ring->next_to_use; 4188 4189 tx_desc = IGB_TX_DESC(tx_ring, i); 4190 4191 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, paylen); 4192 cmd_type = igb_tx_cmd_type(tx_flags); 4193 4194 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4195 if (dma_mapping_error(tx_ring->dev, dma)) 4196 goto dma_error; 4197 4198 /* record length, and DMA address */ 4199 dma_unmap_len_set(first, len, size); 4200 dma_unmap_addr_set(first, dma, dma); 4201 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4202 4203 for (;;) { 4204 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4205 tx_desc->read.cmd_type_len = 4206 cmd_type | cpu_to_le32(IGB_MAX_DATA_PER_TXD); 4207 4208 i++; 4209 tx_desc++; 4210 if (i == tx_ring->count) { 4211 tx_desc = IGB_TX_DESC(tx_ring, 0); 4212 i = 0; 4213 } 4214 4215 dma += IGB_MAX_DATA_PER_TXD; 4216 size -= IGB_MAX_DATA_PER_TXD; 4217 4218 tx_desc->read.olinfo_status = 0; 4219 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4220 } 4221 4222 if (likely(!data_len)) 4223 break; 4224 4225 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); 4226 4227 i++; 4228 tx_desc++; 4229 if (i == tx_ring->count) { 4230 tx_desc = IGB_TX_DESC(tx_ring, 0); 4231 i = 0; 4232 } 4233 4234 size = skb_frag_size(frag); 4235 data_len -= size; 4236 4237 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4238 size, DMA_TO_DEVICE); 4239 if (dma_mapping_error(tx_ring->dev, dma)) 4240 goto dma_error; 4241 4242 tx_buffer = &tx_ring->tx_buffer_info[i]; 4243 dma_unmap_len_set(tx_buffer, len, size); 4244 dma_unmap_addr_set(tx_buffer, dma, dma); 4245 4246 tx_desc->read.olinfo_status = 0; 4247 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4248 4249 frag++; 4250 } 4251 4252 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4253 4254 /* write last descriptor with RS and EOP bits */ 4255 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IGB_TXD_DCMD); 4256 if (unlikely(skb->no_fcs)) 4257 cmd_type &= ~(cpu_to_le32(E1000_ADVTXD_DCMD_IFCS)); 4258 tx_desc->read.cmd_type_len = cmd_type; 4259 4260 /* set the timestamp */ 4261 first->time_stamp = jiffies; 4262 4263 /* 4264 * Force memory writes to complete before letting h/w know there 4265 * are new descriptors to fetch. (Only applicable for weak-ordered 4266 * memory model archs, such as IA-64). 4267 * 4268 * We also need this memory barrier to make certain all of the 4269 * status bits have been updated before next_to_watch is written. 4270 */ 4271 wmb(); 4272 4273 /* set next_to_watch value indicating a packet is present */ 4274 first->next_to_watch = tx_desc; 4275 4276 i++; 4277 if (i == tx_ring->count) 4278 i = 0; 4279 4280 tx_ring->next_to_use = i; 4281 4282 writel(i, tx_ring->tail); 4283 4284 /* we need this if more than one processor can write to our tail 4285 * at a time, it syncronizes IO on IA64/Altix systems */ 4286 mmiowb(); 4287 4288 return; 4289 4290dma_error: 4291 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4292 4293 /* clear dma mappings for failed tx_buffer_info map */ 4294 for (;;) { 4295 tx_buffer = &tx_ring->tx_buffer_info[i]; 4296 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4297 if (tx_buffer == first) 4298 break; 4299 if (i == 0) 4300 i = tx_ring->count; 4301 i--; 4302 } 4303 4304 tx_ring->next_to_use = i; 4305} 4306 4307static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4308{ 4309 struct net_device *netdev = tx_ring->netdev; 4310 4311 netif_stop_subqueue(netdev, tx_ring->queue_index); 4312 4313 /* Herbert's original patch had: 4314 * smp_mb__after_netif_stop_queue(); 4315 * but since that doesn't exist yet, just open code it. */ 4316 smp_mb(); 4317 4318 /* We need to check again in a case another CPU has just 4319 * made room available. */ 4320 if (igb_desc_unused(tx_ring) < size) 4321 return -EBUSY; 4322 4323 /* A reprieve! */ 4324 netif_wake_subqueue(netdev, tx_ring->queue_index); 4325 4326 u64_stats_update_begin(&tx_ring->tx_syncp2); 4327 tx_ring->tx_stats.restart_queue2++; 4328 u64_stats_update_end(&tx_ring->tx_syncp2); 4329 4330 return 0; 4331} 4332 4333static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4334{ 4335 if (igb_desc_unused(tx_ring) >= size) 4336 return 0; 4337 return __igb_maybe_stop_tx(tx_ring, size); 4338} 4339 4340netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4341 struct igb_ring *tx_ring) 4342{ 4343 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 4344 struct igb_tx_buffer *first; 4345 int tso; 4346 u32 tx_flags = 0; 4347 __be16 protocol = vlan_get_protocol(skb); 4348 u8 hdr_len = 0; 4349 4350 /* need: 1 descriptor per page, 4351 * + 2 desc gap to keep tail from touching head, 4352 * + 1 desc for skb->data, 4353 * + 1 desc for context descriptor, 4354 * otherwise try next time */ 4355 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) { 4356 /* this is a hard error */ 4357 return NETDEV_TX_BUSY; 4358 } 4359 4360 /* record the location of the first descriptor for this packet */ 4361 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 4362 first->skb = skb; 4363 first->bytecount = skb->len; 4364 first->gso_segs = 1; 4365 4366 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4367 !(adapter->ptp_tx_skb))) { 4368 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4369 tx_flags |= IGB_TX_FLAGS_TSTAMP; 4370 4371 adapter->ptp_tx_skb = skb_get(skb); 4372 if (adapter->hw.mac.type == e1000_82576) 4373 schedule_work(&adapter->ptp_tx_work); 4374 } 4375 4376 if (vlan_tx_tag_present(skb)) { 4377 tx_flags |= IGB_TX_FLAGS_VLAN; 4378 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 4379 } 4380 4381 /* record initial flags and protocol */ 4382 first->tx_flags = tx_flags; 4383 first->protocol = protocol; 4384 4385 tso = igb_tso(tx_ring, first, &hdr_len); 4386 if (tso < 0) 4387 goto out_drop; 4388 else if (!tso) 4389 igb_tx_csum(tx_ring, first); 4390 4391 igb_tx_map(tx_ring, first, hdr_len); 4392 4393 /* Make sure there is space in the ring for the next send. */ 4394 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4); 4395 4396 return NETDEV_TX_OK; 4397 4398out_drop: 4399 igb_unmap_and_free_tx_resource(tx_ring, first); 4400 4401 return NETDEV_TX_OK; 4402} 4403 4404static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 4405 struct sk_buff *skb) 4406{ 4407 unsigned int r_idx = skb->queue_mapping; 4408 4409 if (r_idx >= adapter->num_tx_queues) 4410 r_idx = r_idx % adapter->num_tx_queues; 4411 4412 return adapter->tx_ring[r_idx]; 4413} 4414 4415static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 4416 struct net_device *netdev) 4417{ 4418 struct igb_adapter *adapter = netdev_priv(netdev); 4419 4420 if (test_bit(__IGB_DOWN, &adapter->state)) { 4421 dev_kfree_skb_any(skb); 4422 return NETDEV_TX_OK; 4423 } 4424 4425 if (skb->len <= 0) { 4426 dev_kfree_skb_any(skb); 4427 return NETDEV_TX_OK; 4428 } 4429 4430 /* 4431 * The minimum packet size with TCTL.PSP set is 17 so pad the skb 4432 * in order to meet this minimum size requirement. 4433 */ 4434 if (unlikely(skb->len < 17)) { 4435 if (skb_pad(skb, 17 - skb->len)) 4436 return NETDEV_TX_OK; 4437 skb->len = 17; 4438 skb_set_tail_pointer(skb, 17); 4439 } 4440 4441 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 4442} 4443 4444/** 4445 * igb_tx_timeout - Respond to a Tx Hang 4446 * @netdev: network interface device structure 4447 **/ 4448static void igb_tx_timeout(struct net_device *netdev) 4449{ 4450 struct igb_adapter *adapter = netdev_priv(netdev); 4451 struct e1000_hw *hw = &adapter->hw; 4452 4453 /* Do the reset outside of interrupt context */ 4454 adapter->tx_timeout_count++; 4455 4456 if (hw->mac.type >= e1000_82580) 4457 hw->dev_spec._82575.global_device_reset = true; 4458 4459 schedule_work(&adapter->reset_task); 4460 wr32(E1000_EICS, 4461 (adapter->eims_enable_mask & ~adapter->eims_other)); 4462} 4463 4464static void igb_reset_task(struct work_struct *work) 4465{ 4466 struct igb_adapter *adapter; 4467 adapter = container_of(work, struct igb_adapter, reset_task); 4468 4469 igb_dump(adapter); 4470 netdev_err(adapter->netdev, "Reset adapter\n"); 4471 igb_reinit_locked(adapter); 4472} 4473 4474/** 4475 * igb_get_stats64 - Get System Network Statistics 4476 * @netdev: network interface device structure 4477 * @stats: rtnl_link_stats64 pointer 4478 * 4479 **/ 4480static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 4481 struct rtnl_link_stats64 *stats) 4482{ 4483 struct igb_adapter *adapter = netdev_priv(netdev); 4484 4485 spin_lock(&adapter->stats64_lock); 4486 igb_update_stats(adapter, &adapter->stats64); 4487 memcpy(stats, &adapter->stats64, sizeof(*stats)); 4488 spin_unlock(&adapter->stats64_lock); 4489 4490 return stats; 4491} 4492 4493/** 4494 * igb_change_mtu - Change the Maximum Transfer Unit 4495 * @netdev: network interface device structure 4496 * @new_mtu: new value for maximum frame size 4497 * 4498 * Returns 0 on success, negative on failure 4499 **/ 4500static int igb_change_mtu(struct net_device *netdev, int new_mtu) 4501{ 4502 struct igb_adapter *adapter = netdev_priv(netdev); 4503 struct pci_dev *pdev = adapter->pdev; 4504 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 4505 4506 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 4507 dev_err(&pdev->dev, "Invalid MTU setting\n"); 4508 return -EINVAL; 4509 } 4510 4511#define MAX_STD_JUMBO_FRAME_SIZE 9238 4512 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 4513 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 4514 return -EINVAL; 4515 } 4516 4517 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 4518 msleep(1); 4519 4520 /* igb_down has a dependency on max_frame_size */ 4521 adapter->max_frame_size = max_frame; 4522 4523 if (netif_running(netdev)) 4524 igb_down(adapter); 4525 4526 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 4527 netdev->mtu, new_mtu); 4528 netdev->mtu = new_mtu; 4529 4530 if (netif_running(netdev)) 4531 igb_up(adapter); 4532 else 4533 igb_reset(adapter); 4534 4535 clear_bit(__IGB_RESETTING, &adapter->state); 4536 4537 return 0; 4538} 4539 4540/** 4541 * igb_update_stats - Update the board statistics counters 4542 * @adapter: board private structure 4543 **/ 4544 4545void igb_update_stats(struct igb_adapter *adapter, 4546 struct rtnl_link_stats64 *net_stats) 4547{ 4548 struct e1000_hw *hw = &adapter->hw; 4549 struct pci_dev *pdev = adapter->pdev; 4550 u32 reg, mpc; 4551 u16 phy_tmp; 4552 int i; 4553 u64 bytes, packets; 4554 unsigned int start; 4555 u64 _bytes, _packets; 4556 4557#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF 4558 4559 /* 4560 * Prevent stats update while adapter is being reset, or if the pci 4561 * connection is down. 4562 */ 4563 if (adapter->link_speed == 0) 4564 return; 4565 if (pci_channel_offline(pdev)) 4566 return; 4567 4568 bytes = 0; 4569 packets = 0; 4570 for (i = 0; i < adapter->num_rx_queues; i++) { 4571 u32 rqdpc = rd32(E1000_RQDPC(i)); 4572 struct igb_ring *ring = adapter->rx_ring[i]; 4573 4574 if (rqdpc) { 4575 ring->rx_stats.drops += rqdpc; 4576 net_stats->rx_fifo_errors += rqdpc; 4577 } 4578 4579 do { 4580 start = u64_stats_fetch_begin_bh(&ring->rx_syncp); 4581 _bytes = ring->rx_stats.bytes; 4582 _packets = ring->rx_stats.packets; 4583 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); 4584 bytes += _bytes; 4585 packets += _packets; 4586 } 4587 4588 net_stats->rx_bytes = bytes; 4589 net_stats->rx_packets = packets; 4590 4591 bytes = 0; 4592 packets = 0; 4593 for (i = 0; i < adapter->num_tx_queues; i++) { 4594 struct igb_ring *ring = adapter->tx_ring[i]; 4595 do { 4596 start = u64_stats_fetch_begin_bh(&ring->tx_syncp); 4597 _bytes = ring->tx_stats.bytes; 4598 _packets = ring->tx_stats.packets; 4599 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); 4600 bytes += _bytes; 4601 packets += _packets; 4602 } 4603 net_stats->tx_bytes = bytes; 4604 net_stats->tx_packets = packets; 4605 4606 /* read stats registers */ 4607 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 4608 adapter->stats.gprc += rd32(E1000_GPRC); 4609 adapter->stats.gorc += rd32(E1000_GORCL); 4610 rd32(E1000_GORCH); /* clear GORCL */ 4611 adapter->stats.bprc += rd32(E1000_BPRC); 4612 adapter->stats.mprc += rd32(E1000_MPRC); 4613 adapter->stats.roc += rd32(E1000_ROC); 4614 4615 adapter->stats.prc64 += rd32(E1000_PRC64); 4616 adapter->stats.prc127 += rd32(E1000_PRC127); 4617 adapter->stats.prc255 += rd32(E1000_PRC255); 4618 adapter->stats.prc511 += rd32(E1000_PRC511); 4619 adapter->stats.prc1023 += rd32(E1000_PRC1023); 4620 adapter->stats.prc1522 += rd32(E1000_PRC1522); 4621 adapter->stats.symerrs += rd32(E1000_SYMERRS); 4622 adapter->stats.sec += rd32(E1000_SEC); 4623 4624 mpc = rd32(E1000_MPC); 4625 adapter->stats.mpc += mpc; 4626 net_stats->rx_fifo_errors += mpc; 4627 adapter->stats.scc += rd32(E1000_SCC); 4628 adapter->stats.ecol += rd32(E1000_ECOL); 4629 adapter->stats.mcc += rd32(E1000_MCC); 4630 adapter->stats.latecol += rd32(E1000_LATECOL); 4631 adapter->stats.dc += rd32(E1000_DC); 4632 adapter->stats.rlec += rd32(E1000_RLEC); 4633 adapter->stats.xonrxc += rd32(E1000_XONRXC); 4634 adapter->stats.xontxc += rd32(E1000_XONTXC); 4635 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 4636 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 4637 adapter->stats.fcruc += rd32(E1000_FCRUC); 4638 adapter->stats.gptc += rd32(E1000_GPTC); 4639 adapter->stats.gotc += rd32(E1000_GOTCL); 4640 rd32(E1000_GOTCH); /* clear GOTCL */ 4641 adapter->stats.rnbc += rd32(E1000_RNBC); 4642 adapter->stats.ruc += rd32(E1000_RUC); 4643 adapter->stats.rfc += rd32(E1000_RFC); 4644 adapter->stats.rjc += rd32(E1000_RJC); 4645 adapter->stats.tor += rd32(E1000_TORH); 4646 adapter->stats.tot += rd32(E1000_TOTH); 4647 adapter->stats.tpr += rd32(E1000_TPR); 4648 4649 adapter->stats.ptc64 += rd32(E1000_PTC64); 4650 adapter->stats.ptc127 += rd32(E1000_PTC127); 4651 adapter->stats.ptc255 += rd32(E1000_PTC255); 4652 adapter->stats.ptc511 += rd32(E1000_PTC511); 4653 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 4654 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 4655 4656 adapter->stats.mptc += rd32(E1000_MPTC); 4657 adapter->stats.bptc += rd32(E1000_BPTC); 4658 4659 adapter->stats.tpt += rd32(E1000_TPT); 4660 adapter->stats.colc += rd32(E1000_COLC); 4661 4662 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 4663 /* read internal phy specific stats */ 4664 reg = rd32(E1000_CTRL_EXT); 4665 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 4666 adapter->stats.rxerrc += rd32(E1000_RXERRC); 4667 4668 /* this stat has invalid values on i210/i211 */ 4669 if ((hw->mac.type != e1000_i210) && 4670 (hw->mac.type != e1000_i211)) 4671 adapter->stats.tncrs += rd32(E1000_TNCRS); 4672 } 4673 4674 adapter->stats.tsctc += rd32(E1000_TSCTC); 4675 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 4676 4677 adapter->stats.iac += rd32(E1000_IAC); 4678 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 4679 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 4680 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 4681 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 4682 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 4683 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 4684 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 4685 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 4686 4687 /* Fill out the OS statistics structure */ 4688 net_stats->multicast = adapter->stats.mprc; 4689 net_stats->collisions = adapter->stats.colc; 4690 4691 /* Rx Errors */ 4692 4693 /* RLEC on some newer hardware can be incorrect so build 4694 * our own version based on RUC and ROC */ 4695 net_stats->rx_errors = adapter->stats.rxerrc + 4696 adapter->stats.crcerrs + adapter->stats.algnerrc + 4697 adapter->stats.ruc + adapter->stats.roc + 4698 adapter->stats.cexterr; 4699 net_stats->rx_length_errors = adapter->stats.ruc + 4700 adapter->stats.roc; 4701 net_stats->rx_crc_errors = adapter->stats.crcerrs; 4702 net_stats->rx_frame_errors = adapter->stats.algnerrc; 4703 net_stats->rx_missed_errors = adapter->stats.mpc; 4704 4705 /* Tx Errors */ 4706 net_stats->tx_errors = adapter->stats.ecol + 4707 adapter->stats.latecol; 4708 net_stats->tx_aborted_errors = adapter->stats.ecol; 4709 net_stats->tx_window_errors = adapter->stats.latecol; 4710 net_stats->tx_carrier_errors = adapter->stats.tncrs; 4711 4712 /* Tx Dropped needs to be maintained elsewhere */ 4713 4714 /* Phy Stats */ 4715 if (hw->phy.media_type == e1000_media_type_copper) { 4716 if ((adapter->link_speed == SPEED_1000) && 4717 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 4718 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; 4719 adapter->phy_stats.idle_errors += phy_tmp; 4720 } 4721 } 4722 4723 /* Management Stats */ 4724 adapter->stats.mgptc += rd32(E1000_MGTPTC); 4725 adapter->stats.mgprc += rd32(E1000_MGTPRC); 4726 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 4727 4728 /* OS2BMC Stats */ 4729 reg = rd32(E1000_MANC); 4730 if (reg & E1000_MANC_EN_BMC2OS) { 4731 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 4732 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 4733 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 4734 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 4735 } 4736} 4737 4738static irqreturn_t igb_msix_other(int irq, void *data) 4739{ 4740 struct igb_adapter *adapter = data; 4741 struct e1000_hw *hw = &adapter->hw; 4742 u32 icr = rd32(E1000_ICR); 4743 /* reading ICR causes bit 31 of EICR to be cleared */ 4744 4745 if (icr & E1000_ICR_DRSTA) 4746 schedule_work(&adapter->reset_task); 4747 4748 if (icr & E1000_ICR_DOUTSYNC) { 4749 /* HW is reporting DMA is out of sync */ 4750 adapter->stats.doosync++; 4751 /* The DMA Out of Sync is also indication of a spoof event 4752 * in IOV mode. Check the Wrong VM Behavior register to 4753 * see if it is really a spoof event. */ 4754 igb_check_wvbr(adapter); 4755 } 4756 4757 /* Check for a mailbox event */ 4758 if (icr & E1000_ICR_VMMB) 4759 igb_msg_task(adapter); 4760 4761 if (icr & E1000_ICR_LSC) { 4762 hw->mac.get_link_status = 1; 4763 /* guard against interrupt when we're going down */ 4764 if (!test_bit(__IGB_DOWN, &adapter->state)) 4765 mod_timer(&adapter->watchdog_timer, jiffies + 1); 4766 } 4767 4768 if (icr & E1000_ICR_TS) { 4769 u32 tsicr = rd32(E1000_TSICR); 4770 4771 if (tsicr & E1000_TSICR_TXTS) { 4772 /* acknowledge the interrupt */ 4773 wr32(E1000_TSICR, E1000_TSICR_TXTS); 4774 /* retrieve hardware timestamp */ 4775 schedule_work(&adapter->ptp_tx_work); 4776 } 4777 } 4778 4779 wr32(E1000_EIMS, adapter->eims_other); 4780 4781 return IRQ_HANDLED; 4782} 4783 4784static void igb_write_itr(struct igb_q_vector *q_vector) 4785{ 4786 struct igb_adapter *adapter = q_vector->adapter; 4787 u32 itr_val = q_vector->itr_val & 0x7FFC; 4788 4789 if (!q_vector->set_itr) 4790 return; 4791 4792 if (!itr_val) 4793 itr_val = 0x4; 4794 4795 if (adapter->hw.mac.type == e1000_82575) 4796 itr_val |= itr_val << 16; 4797 else 4798 itr_val |= E1000_EITR_CNT_IGNR; 4799 4800 writel(itr_val, q_vector->itr_register); 4801 q_vector->set_itr = 0; 4802} 4803 4804static irqreturn_t igb_msix_ring(int irq, void *data) 4805{ 4806 struct igb_q_vector *q_vector = data; 4807 4808 /* Write the ITR value calculated from the previous interrupt. */ 4809 igb_write_itr(q_vector); 4810 4811 napi_schedule(&q_vector->napi); 4812 4813 return IRQ_HANDLED; 4814} 4815 4816#ifdef CONFIG_IGB_DCA 4817static void igb_update_tx_dca(struct igb_adapter *adapter, 4818 struct igb_ring *tx_ring, 4819 int cpu) 4820{ 4821 struct e1000_hw *hw = &adapter->hw; 4822 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 4823 4824 if (hw->mac.type != e1000_82575) 4825 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 4826 4827 /* 4828 * We can enable relaxed ordering for reads, but not writes when 4829 * DCA is enabled. This is due to a known issue in some chipsets 4830 * which will cause the DCA tag to be cleared. 4831 */ 4832 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 4833 E1000_DCA_TXCTRL_DATA_RRO_EN | 4834 E1000_DCA_TXCTRL_DESC_DCA_EN; 4835 4836 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 4837} 4838 4839static void igb_update_rx_dca(struct igb_adapter *adapter, 4840 struct igb_ring *rx_ring, 4841 int cpu) 4842{ 4843 struct e1000_hw *hw = &adapter->hw; 4844 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 4845 4846 if (hw->mac.type != e1000_82575) 4847 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 4848 4849 /* 4850 * We can enable relaxed ordering for reads, but not writes when 4851 * DCA is enabled. This is due to a known issue in some chipsets 4852 * which will cause the DCA tag to be cleared. 4853 */ 4854 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 4855 E1000_DCA_RXCTRL_DESC_DCA_EN; 4856 4857 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 4858} 4859 4860static void igb_update_dca(struct igb_q_vector *q_vector) 4861{ 4862 struct igb_adapter *adapter = q_vector->adapter; 4863 int cpu = get_cpu(); 4864 4865 if (q_vector->cpu == cpu) 4866 goto out_no_update; 4867 4868 if (q_vector->tx.ring) 4869 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 4870 4871 if (q_vector->rx.ring) 4872 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 4873 4874 q_vector->cpu = cpu; 4875out_no_update: 4876 put_cpu(); 4877} 4878 4879static void igb_setup_dca(struct igb_adapter *adapter) 4880{ 4881 struct e1000_hw *hw = &adapter->hw; 4882 int i; 4883 4884 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 4885 return; 4886 4887 /* Always use CB2 mode, difference is masked in the CB driver. */ 4888 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 4889 4890 for (i = 0; i < adapter->num_q_vectors; i++) { 4891 adapter->q_vector[i]->cpu = -1; 4892 igb_update_dca(adapter->q_vector[i]); 4893 } 4894} 4895 4896static int __igb_notify_dca(struct device *dev, void *data) 4897{ 4898 struct net_device *netdev = dev_get_drvdata(dev); 4899 struct igb_adapter *adapter = netdev_priv(netdev); 4900 struct pci_dev *pdev = adapter->pdev; 4901 struct e1000_hw *hw = &adapter->hw; 4902 unsigned long event = *(unsigned long *)data; 4903 4904 switch (event) { 4905 case DCA_PROVIDER_ADD: 4906 /* if already enabled, don't do it again */ 4907 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 4908 break; 4909 if (dca_add_requester(dev) == 0) { 4910 adapter->flags |= IGB_FLAG_DCA_ENABLED; 4911 dev_info(&pdev->dev, "DCA enabled\n"); 4912 igb_setup_dca(adapter); 4913 break; 4914 } 4915 /* Fall Through since DCA is disabled. */ 4916 case DCA_PROVIDER_REMOVE: 4917 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 4918 /* without this a class_device is left 4919 * hanging around in the sysfs model */ 4920 dca_remove_requester(dev); 4921 dev_info(&pdev->dev, "DCA disabled\n"); 4922 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 4923 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 4924 } 4925 break; 4926 } 4927 4928 return 0; 4929} 4930 4931static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 4932 void *p) 4933{ 4934 int ret_val; 4935 4936 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 4937 __igb_notify_dca); 4938 4939 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 4940} 4941#endif /* CONFIG_IGB_DCA */ 4942 4943#ifdef CONFIG_PCI_IOV 4944static int igb_vf_configure(struct igb_adapter *adapter, int vf) 4945{ 4946 unsigned char mac_addr[ETH_ALEN]; 4947 4948 eth_random_addr(mac_addr); 4949 igb_set_vf_mac(adapter, vf, mac_addr); 4950 4951 return 0; 4952} 4953 4954static bool igb_vfs_are_assigned(struct igb_adapter *adapter) 4955{ 4956 struct pci_dev *pdev = adapter->pdev; 4957 struct pci_dev *vfdev; 4958 int dev_id; 4959 4960 switch (adapter->hw.mac.type) { 4961 case e1000_82576: 4962 dev_id = IGB_82576_VF_DEV_ID; 4963 break; 4964 case e1000_i350: 4965 dev_id = IGB_I350_VF_DEV_ID; 4966 break; 4967 default: 4968 return false; 4969 } 4970 4971 /* loop through all the VFs to see if we own any that are assigned */ 4972 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL); 4973 while (vfdev) { 4974 /* if we don't own it we don't care */ 4975 if (vfdev->is_virtfn && vfdev->physfn == pdev) { 4976 /* if it is assigned we cannot release it */ 4977 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) 4978 return true; 4979 } 4980 4981 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev); 4982 } 4983 4984 return false; 4985} 4986 4987#endif 4988static void igb_ping_all_vfs(struct igb_adapter *adapter) 4989{ 4990 struct e1000_hw *hw = &adapter->hw; 4991 u32 ping; 4992 int i; 4993 4994 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 4995 ping = E1000_PF_CONTROL_MSG; 4996 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 4997 ping |= E1000_VT_MSGTYPE_CTS; 4998 igb_write_mbx(hw, &ping, 1, i); 4999 } 5000} 5001 5002static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5003{ 5004 struct e1000_hw *hw = &adapter->hw; 5005 u32 vmolr = rd32(E1000_VMOLR(vf)); 5006 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5007 5008 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5009 IGB_VF_FLAG_MULTI_PROMISC); 5010 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5011 5012 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5013 vmolr |= E1000_VMOLR_MPME; 5014 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5015 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5016 } else { 5017 /* 5018 * if we have hashes and we are clearing a multicast promisc 5019 * flag we need to write the hashes to the MTA as this step 5020 * was previously skipped 5021 */ 5022 if (vf_data->num_vf_mc_hashes > 30) { 5023 vmolr |= E1000_VMOLR_MPME; 5024 } else if (vf_data->num_vf_mc_hashes) { 5025 int j; 5026 vmolr |= E1000_VMOLR_ROMPE; 5027 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5028 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5029 } 5030 } 5031 5032 wr32(E1000_VMOLR(vf), vmolr); 5033 5034 /* there are flags left unprocessed, likely not supported */ 5035 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5036 return -EINVAL; 5037 5038 return 0; 5039 5040} 5041 5042static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5043 u32 *msgbuf, u32 vf) 5044{ 5045 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5046 u16 *hash_list = (u16 *)&msgbuf[1]; 5047 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5048 int i; 5049 5050 /* salt away the number of multicast addresses assigned 5051 * to this VF for later use to restore when the PF multi cast 5052 * list changes 5053 */ 5054 vf_data->num_vf_mc_hashes = n; 5055 5056 /* only up to 30 hash values supported */ 5057 if (n > 30) 5058 n = 30; 5059 5060 /* store the hashes for later use */ 5061 for (i = 0; i < n; i++) 5062 vf_data->vf_mc_hashes[i] = hash_list[i]; 5063 5064 /* Flush and reset the mta with the new values */ 5065 igb_set_rx_mode(adapter->netdev); 5066 5067 return 0; 5068} 5069 5070static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5071{ 5072 struct e1000_hw *hw = &adapter->hw; 5073 struct vf_data_storage *vf_data; 5074 int i, j; 5075 5076 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5077 u32 vmolr = rd32(E1000_VMOLR(i)); 5078 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5079 5080 vf_data = &adapter->vf_data[i]; 5081 5082 if ((vf_data->num_vf_mc_hashes > 30) || 5083 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5084 vmolr |= E1000_VMOLR_MPME; 5085 } else if (vf_data->num_vf_mc_hashes) { 5086 vmolr |= E1000_VMOLR_ROMPE; 5087 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5088 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5089 } 5090 wr32(E1000_VMOLR(i), vmolr); 5091 } 5092} 5093 5094static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5095{ 5096 struct e1000_hw *hw = &adapter->hw; 5097 u32 pool_mask, reg, vid; 5098 int i; 5099 5100 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5101 5102 /* Find the vlan filter for this id */ 5103 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5104 reg = rd32(E1000_VLVF(i)); 5105 5106 /* remove the vf from the pool */ 5107 reg &= ~pool_mask; 5108 5109 /* if pool is empty then remove entry from vfta */ 5110 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5111 (reg & E1000_VLVF_VLANID_ENABLE)) { 5112 reg = 0; 5113 vid = reg & E1000_VLVF_VLANID_MASK; 5114 igb_vfta_set(hw, vid, false); 5115 } 5116 5117 wr32(E1000_VLVF(i), reg); 5118 } 5119 5120 adapter->vf_data[vf].vlans_enabled = 0; 5121} 5122 5123static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5124{ 5125 struct e1000_hw *hw = &adapter->hw; 5126 u32 reg, i; 5127 5128 /* The vlvf table only exists on 82576 hardware and newer */ 5129 if (hw->mac.type < e1000_82576) 5130 return -1; 5131 5132 /* we only need to do this if VMDq is enabled */ 5133 if (!adapter->vfs_allocated_count) 5134 return -1; 5135 5136 /* Find the vlan filter for this id */ 5137 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5138 reg = rd32(E1000_VLVF(i)); 5139 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5140 vid == (reg & E1000_VLVF_VLANID_MASK)) 5141 break; 5142 } 5143 5144 if (add) { 5145 if (i == E1000_VLVF_ARRAY_SIZE) { 5146 /* Did not find a matching VLAN ID entry that was 5147 * enabled. Search for a free filter entry, i.e. 5148 * one without the enable bit set 5149 */ 5150 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5151 reg = rd32(E1000_VLVF(i)); 5152 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5153 break; 5154 } 5155 } 5156 if (i < E1000_VLVF_ARRAY_SIZE) { 5157 /* Found an enabled/available entry */ 5158 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5159 5160 /* if !enabled we need to set this up in vfta */ 5161 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5162 /* add VID to filter table */ 5163 igb_vfta_set(hw, vid, true); 5164 reg |= E1000_VLVF_VLANID_ENABLE; 5165 } 5166 reg &= ~E1000_VLVF_VLANID_MASK; 5167 reg |= vid; 5168 wr32(E1000_VLVF(i), reg); 5169 5170 /* do not modify RLPML for PF devices */ 5171 if (vf >= adapter->vfs_allocated_count) 5172 return 0; 5173 5174 if (!adapter->vf_data[vf].vlans_enabled) { 5175 u32 size; 5176 reg = rd32(E1000_VMOLR(vf)); 5177 size = reg & E1000_VMOLR_RLPML_MASK; 5178 size += 4; 5179 reg &= ~E1000_VMOLR_RLPML_MASK; 5180 reg |= size; 5181 wr32(E1000_VMOLR(vf), reg); 5182 } 5183 5184 adapter->vf_data[vf].vlans_enabled++; 5185 } 5186 } else { 5187 if (i < E1000_VLVF_ARRAY_SIZE) { 5188 /* remove vf from the pool */ 5189 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5190 /* if pool is empty then remove entry from vfta */ 5191 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5192 reg = 0; 5193 igb_vfta_set(hw, vid, false); 5194 } 5195 wr32(E1000_VLVF(i), reg); 5196 5197 /* do not modify RLPML for PF devices */ 5198 if (vf >= adapter->vfs_allocated_count) 5199 return 0; 5200 5201 adapter->vf_data[vf].vlans_enabled--; 5202 if (!adapter->vf_data[vf].vlans_enabled) { 5203 u32 size; 5204 reg = rd32(E1000_VMOLR(vf)); 5205 size = reg & E1000_VMOLR_RLPML_MASK; 5206 size -= 4; 5207 reg &= ~E1000_VMOLR_RLPML_MASK; 5208 reg |= size; 5209 wr32(E1000_VMOLR(vf), reg); 5210 } 5211 } 5212 } 5213 return 0; 5214} 5215 5216static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5217{ 5218 struct e1000_hw *hw = &adapter->hw; 5219 5220 if (vid) 5221 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5222 else 5223 wr32(E1000_VMVIR(vf), 0); 5224} 5225 5226static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5227 int vf, u16 vlan, u8 qos) 5228{ 5229 int err = 0; 5230 struct igb_adapter *adapter = netdev_priv(netdev); 5231 5232 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5233 return -EINVAL; 5234 if (vlan || qos) { 5235 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5236 if (err) 5237 goto out; 5238 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5239 igb_set_vmolr(adapter, vf, !vlan); 5240 adapter->vf_data[vf].pf_vlan = vlan; 5241 adapter->vf_data[vf].pf_qos = qos; 5242 dev_info(&adapter->pdev->dev, 5243 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5244 if (test_bit(__IGB_DOWN, &adapter->state)) { 5245 dev_warn(&adapter->pdev->dev, 5246 "The VF VLAN has been set," 5247 " but the PF device is not up.\n"); 5248 dev_warn(&adapter->pdev->dev, 5249 "Bring the PF device up before" 5250 " attempting to use the VF device.\n"); 5251 } 5252 } else { 5253 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5254 false, vf); 5255 igb_set_vmvir(adapter, vlan, vf); 5256 igb_set_vmolr(adapter, vf, true); 5257 adapter->vf_data[vf].pf_vlan = 0; 5258 adapter->vf_data[vf].pf_qos = 0; 5259 } 5260out: 5261 return err; 5262} 5263 5264static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5265{ 5266 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5267 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5268 5269 return igb_vlvf_set(adapter, vid, add, vf); 5270} 5271 5272static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 5273{ 5274 /* clear flags - except flag that indicates PF has set the MAC */ 5275 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 5276 adapter->vf_data[vf].last_nack = jiffies; 5277 5278 /* reset offloads to defaults */ 5279 igb_set_vmolr(adapter, vf, true); 5280 5281 /* reset vlans for device */ 5282 igb_clear_vf_vfta(adapter, vf); 5283 if (adapter->vf_data[vf].pf_vlan) 5284 igb_ndo_set_vf_vlan(adapter->netdev, vf, 5285 adapter->vf_data[vf].pf_vlan, 5286 adapter->vf_data[vf].pf_qos); 5287 else 5288 igb_clear_vf_vfta(adapter, vf); 5289 5290 /* reset multicast table array for vf */ 5291 adapter->vf_data[vf].num_vf_mc_hashes = 0; 5292 5293 /* Flush and reset the mta with the new values */ 5294 igb_set_rx_mode(adapter->netdev); 5295} 5296 5297static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 5298{ 5299 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5300 5301 /* generate a new mac address as we were hotplug removed/added */ 5302 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 5303 eth_random_addr(vf_mac); 5304 5305 /* process remaining reset events */ 5306 igb_vf_reset(adapter, vf); 5307} 5308 5309static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 5310{ 5311 struct e1000_hw *hw = &adapter->hw; 5312 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5313 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 5314 u32 reg, msgbuf[3]; 5315 u8 *addr = (u8 *)(&msgbuf[1]); 5316 5317 /* process all the same items cleared in a function level reset */ 5318 igb_vf_reset(adapter, vf); 5319 5320 /* set vf mac address */ 5321 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 5322 5323 /* enable transmit and receive for vf */ 5324 reg = rd32(E1000_VFTE); 5325 wr32(E1000_VFTE, reg | (1 << vf)); 5326 reg = rd32(E1000_VFRE); 5327 wr32(E1000_VFRE, reg | (1 << vf)); 5328 5329 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 5330 5331 /* reply to reset with ack and vf mac address */ 5332 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 5333 memcpy(addr, vf_mac, 6); 5334 igb_write_mbx(hw, msgbuf, 3, vf); 5335} 5336 5337static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 5338{ 5339 /* 5340 * The VF MAC Address is stored in a packed array of bytes 5341 * starting at the second 32 bit word of the msg array 5342 */ 5343 unsigned char *addr = (char *)&msg[1]; 5344 int err = -1; 5345 5346 if (is_valid_ether_addr(addr)) 5347 err = igb_set_vf_mac(adapter, vf, addr); 5348 5349 return err; 5350} 5351 5352static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 5353{ 5354 struct e1000_hw *hw = &adapter->hw; 5355 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5356 u32 msg = E1000_VT_MSGTYPE_NACK; 5357 5358 /* if device isn't clear to send it shouldn't be reading either */ 5359 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 5360 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 5361 igb_write_mbx(hw, &msg, 1, vf); 5362 vf_data->last_nack = jiffies; 5363 } 5364} 5365 5366static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 5367{ 5368 struct pci_dev *pdev = adapter->pdev; 5369 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 5370 struct e1000_hw *hw = &adapter->hw; 5371 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5372 s32 retval; 5373 5374 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 5375 5376 if (retval) { 5377 /* if receive failed revoke VF CTS stats and restart init */ 5378 dev_err(&pdev->dev, "Error receiving message from VF\n"); 5379 vf_data->flags &= ~IGB_VF_FLAG_CTS; 5380 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 5381 return; 5382 goto out; 5383 } 5384 5385 /* this is a message we already processed, do nothing */ 5386 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 5387 return; 5388 5389 /* 5390 * until the vf completes a reset it should not be 5391 * allowed to start any configuration. 5392 */ 5393 5394 if (msgbuf[0] == E1000_VF_RESET) { 5395 igb_vf_reset_msg(adapter, vf); 5396 return; 5397 } 5398 5399 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 5400 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 5401 return; 5402 retval = -1; 5403 goto out; 5404 } 5405 5406 switch ((msgbuf[0] & 0xFFFF)) { 5407 case E1000_VF_SET_MAC_ADDR: 5408 retval = -EINVAL; 5409 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 5410 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 5411 else 5412 dev_warn(&pdev->dev, 5413 "VF %d attempted to override administratively " 5414 "set MAC address\nReload the VF driver to " 5415 "resume operations\n", vf); 5416 break; 5417 case E1000_VF_SET_PROMISC: 5418 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 5419 break; 5420 case E1000_VF_SET_MULTICAST: 5421 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 5422 break; 5423 case E1000_VF_SET_LPE: 5424 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 5425 break; 5426 case E1000_VF_SET_VLAN: 5427 retval = -1; 5428 if (vf_data->pf_vlan) 5429 dev_warn(&pdev->dev, 5430 "VF %d attempted to override administratively " 5431 "set VLAN tag\nReload the VF driver to " 5432 "resume operations\n", vf); 5433 else 5434 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 5435 break; 5436 default: 5437 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 5438 retval = -1; 5439 break; 5440 } 5441 5442 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 5443out: 5444 /* notify the VF of the results of what it sent us */ 5445 if (retval) 5446 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 5447 else 5448 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 5449 5450 igb_write_mbx(hw, msgbuf, 1, vf); 5451} 5452 5453static void igb_msg_task(struct igb_adapter *adapter) 5454{ 5455 struct e1000_hw *hw = &adapter->hw; 5456 u32 vf; 5457 5458 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 5459 /* process any reset requests */ 5460 if (!igb_check_for_rst(hw, vf)) 5461 igb_vf_reset_event(adapter, vf); 5462 5463 /* process any messages pending */ 5464 if (!igb_check_for_msg(hw, vf)) 5465 igb_rcv_msg_from_vf(adapter, vf); 5466 5467 /* process any acks */ 5468 if (!igb_check_for_ack(hw, vf)) 5469 igb_rcv_ack_from_vf(adapter, vf); 5470 } 5471} 5472 5473/** 5474 * igb_set_uta - Set unicast filter table address 5475 * @adapter: board private structure 5476 * 5477 * The unicast table address is a register array of 32-bit registers. 5478 * The table is meant to be used in a way similar to how the MTA is used 5479 * however due to certain limitations in the hardware it is necessary to 5480 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 5481 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 5482 **/ 5483static void igb_set_uta(struct igb_adapter *adapter) 5484{ 5485 struct e1000_hw *hw = &adapter->hw; 5486 int i; 5487 5488 /* The UTA table only exists on 82576 hardware and newer */ 5489 if (hw->mac.type < e1000_82576) 5490 return; 5491 5492 /* we only need to do this if VMDq is enabled */ 5493 if (!adapter->vfs_allocated_count) 5494 return; 5495 5496 for (i = 0; i < hw->mac.uta_reg_count; i++) 5497 array_wr32(E1000_UTA, i, ~0); 5498} 5499 5500/** 5501 * igb_intr_msi - Interrupt Handler 5502 * @irq: interrupt number 5503 * @data: pointer to a network interface device structure 5504 **/ 5505static irqreturn_t igb_intr_msi(int irq, void *data) 5506{ 5507 struct igb_adapter *adapter = data; 5508 struct igb_q_vector *q_vector = adapter->q_vector[0]; 5509 struct e1000_hw *hw = &adapter->hw; 5510 /* read ICR disables interrupts using IAM */ 5511 u32 icr = rd32(E1000_ICR); 5512 5513 igb_write_itr(q_vector); 5514 5515 if (icr & E1000_ICR_DRSTA) 5516 schedule_work(&adapter->reset_task); 5517 5518 if (icr & E1000_ICR_DOUTSYNC) { 5519 /* HW is reporting DMA is out of sync */ 5520 adapter->stats.doosync++; 5521 } 5522 5523 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 5524 hw->mac.get_link_status = 1; 5525 if (!test_bit(__IGB_DOWN, &adapter->state)) 5526 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5527 } 5528 5529 if (icr & E1000_ICR_TS) { 5530 u32 tsicr = rd32(E1000_TSICR); 5531 5532 if (tsicr & E1000_TSICR_TXTS) { 5533 /* acknowledge the interrupt */ 5534 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5535 /* retrieve hardware timestamp */ 5536 schedule_work(&adapter->ptp_tx_work); 5537 } 5538 } 5539 5540 napi_schedule(&q_vector->napi); 5541 5542 return IRQ_HANDLED; 5543} 5544 5545/** 5546 * igb_intr - Legacy Interrupt Handler 5547 * @irq: interrupt number 5548 * @data: pointer to a network interface device structure 5549 **/ 5550static irqreturn_t igb_intr(int irq, void *data) 5551{ 5552 struct igb_adapter *adapter = data; 5553 struct igb_q_vector *q_vector = adapter->q_vector[0]; 5554 struct e1000_hw *hw = &adapter->hw; 5555 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 5556 * need for the IMC write */ 5557 u32 icr = rd32(E1000_ICR); 5558 5559 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 5560 * not set, then the adapter didn't send an interrupt */ 5561 if (!(icr & E1000_ICR_INT_ASSERTED)) 5562 return IRQ_NONE; 5563 5564 igb_write_itr(q_vector); 5565 5566 if (icr & E1000_ICR_DRSTA) 5567 schedule_work(&adapter->reset_task); 5568 5569 if (icr & E1000_ICR_DOUTSYNC) { 5570 /* HW is reporting DMA is out of sync */ 5571 adapter->stats.doosync++; 5572 } 5573 5574 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 5575 hw->mac.get_link_status = 1; 5576 /* guard against interrupt when we're going down */ 5577 if (!test_bit(__IGB_DOWN, &adapter->state)) 5578 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5579 } 5580 5581 if (icr & E1000_ICR_TS) { 5582 u32 tsicr = rd32(E1000_TSICR); 5583 5584 if (tsicr & E1000_TSICR_TXTS) { 5585 /* acknowledge the interrupt */ 5586 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5587 /* retrieve hardware timestamp */ 5588 schedule_work(&adapter->ptp_tx_work); 5589 } 5590 } 5591 5592 napi_schedule(&q_vector->napi); 5593 5594 return IRQ_HANDLED; 5595} 5596 5597static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 5598{ 5599 struct igb_adapter *adapter = q_vector->adapter; 5600 struct e1000_hw *hw = &adapter->hw; 5601 5602 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 5603 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 5604 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 5605 igb_set_itr(q_vector); 5606 else 5607 igb_update_ring_itr(q_vector); 5608 } 5609 5610 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5611 if (adapter->msix_entries) 5612 wr32(E1000_EIMS, q_vector->eims_value); 5613 else 5614 igb_irq_enable(adapter); 5615 } 5616} 5617 5618/** 5619 * igb_poll - NAPI Rx polling callback 5620 * @napi: napi polling structure 5621 * @budget: count of how many packets we should handle 5622 **/ 5623static int igb_poll(struct napi_struct *napi, int budget) 5624{ 5625 struct igb_q_vector *q_vector = container_of(napi, 5626 struct igb_q_vector, 5627 napi); 5628 bool clean_complete = true; 5629 5630#ifdef CONFIG_IGB_DCA 5631 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 5632 igb_update_dca(q_vector); 5633#endif 5634 if (q_vector->tx.ring) 5635 clean_complete = igb_clean_tx_irq(q_vector); 5636 5637 if (q_vector->rx.ring) 5638 clean_complete &= igb_clean_rx_irq(q_vector, budget); 5639 5640 /* If all work not completed, return budget and keep polling */ 5641 if (!clean_complete) 5642 return budget; 5643 5644 /* If not enough Rx work done, exit the polling mode */ 5645 napi_complete(napi); 5646 igb_ring_irq_enable(q_vector); 5647 5648 return 0; 5649} 5650 5651/** 5652 * igb_clean_tx_irq - Reclaim resources after transmit completes 5653 * @q_vector: pointer to q_vector containing needed info 5654 * 5655 * returns true if ring is completely cleaned 5656 **/ 5657static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 5658{ 5659 struct igb_adapter *adapter = q_vector->adapter; 5660 struct igb_ring *tx_ring = q_vector->tx.ring; 5661 struct igb_tx_buffer *tx_buffer; 5662 union e1000_adv_tx_desc *tx_desc; 5663 unsigned int total_bytes = 0, total_packets = 0; 5664 unsigned int budget = q_vector->tx.work_limit; 5665 unsigned int i = tx_ring->next_to_clean; 5666 5667 if (test_bit(__IGB_DOWN, &adapter->state)) 5668 return true; 5669 5670 tx_buffer = &tx_ring->tx_buffer_info[i]; 5671 tx_desc = IGB_TX_DESC(tx_ring, i); 5672 i -= tx_ring->count; 5673 5674 do { 5675 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 5676 5677 /* if next_to_watch is not set then there is no work pending */ 5678 if (!eop_desc) 5679 break; 5680 5681 /* prevent any other reads prior to eop_desc */ 5682 rmb(); 5683 5684 /* if DD is not set pending work has not been completed */ 5685 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 5686 break; 5687 5688 /* clear next_to_watch to prevent false hangs */ 5689 tx_buffer->next_to_watch = NULL; 5690 5691 /* update the statistics for this packet */ 5692 total_bytes += tx_buffer->bytecount; 5693 total_packets += tx_buffer->gso_segs; 5694 5695 /* free the skb */ 5696 dev_kfree_skb_any(tx_buffer->skb); 5697 5698 /* unmap skb header data */ 5699 dma_unmap_single(tx_ring->dev, 5700 dma_unmap_addr(tx_buffer, dma), 5701 dma_unmap_len(tx_buffer, len), 5702 DMA_TO_DEVICE); 5703 5704 /* clear tx_buffer data */ 5705 tx_buffer->skb = NULL; 5706 dma_unmap_len_set(tx_buffer, len, 0); 5707 5708 /* clear last DMA location and unmap remaining buffers */ 5709 while (tx_desc != eop_desc) { 5710 tx_buffer++; 5711 tx_desc++; 5712 i++; 5713 if (unlikely(!i)) { 5714 i -= tx_ring->count; 5715 tx_buffer = tx_ring->tx_buffer_info; 5716 tx_desc = IGB_TX_DESC(tx_ring, 0); 5717 } 5718 5719 /* unmap any remaining paged data */ 5720 if (dma_unmap_len(tx_buffer, len)) { 5721 dma_unmap_page(tx_ring->dev, 5722 dma_unmap_addr(tx_buffer, dma), 5723 dma_unmap_len(tx_buffer, len), 5724 DMA_TO_DEVICE); 5725 dma_unmap_len_set(tx_buffer, len, 0); 5726 } 5727 } 5728 5729 /* move us one more past the eop_desc for start of next pkt */ 5730 tx_buffer++; 5731 tx_desc++; 5732 i++; 5733 if (unlikely(!i)) { 5734 i -= tx_ring->count; 5735 tx_buffer = tx_ring->tx_buffer_info; 5736 tx_desc = IGB_TX_DESC(tx_ring, 0); 5737 } 5738 5739 /* issue prefetch for next Tx descriptor */ 5740 prefetch(tx_desc); 5741 5742 /* update budget accounting */ 5743 budget--; 5744 } while (likely(budget)); 5745 5746 netdev_tx_completed_queue(txring_txq(tx_ring), 5747 total_packets, total_bytes); 5748 i += tx_ring->count; 5749 tx_ring->next_to_clean = i; 5750 u64_stats_update_begin(&tx_ring->tx_syncp); 5751 tx_ring->tx_stats.bytes += total_bytes; 5752 tx_ring->tx_stats.packets += total_packets; 5753 u64_stats_update_end(&tx_ring->tx_syncp); 5754 q_vector->tx.total_bytes += total_bytes; 5755 q_vector->tx.total_packets += total_packets; 5756 5757 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 5758 struct e1000_hw *hw = &adapter->hw; 5759 5760 /* Detect a transmit hang in hardware, this serializes the 5761 * check with the clearing of time_stamp and movement of i */ 5762 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5763 if (tx_buffer->next_to_watch && 5764 time_after(jiffies, tx_buffer->time_stamp + 5765 (adapter->tx_timeout_factor * HZ)) && 5766 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 5767 5768 /* detected Tx unit hang */ 5769 dev_err(tx_ring->dev, 5770 "Detected Tx Unit Hang\n" 5771 " Tx Queue <%d>\n" 5772 " TDH <%x>\n" 5773 " TDT <%x>\n" 5774 " next_to_use <%x>\n" 5775 " next_to_clean <%x>\n" 5776 "buffer_info[next_to_clean]\n" 5777 " time_stamp <%lx>\n" 5778 " next_to_watch <%p>\n" 5779 " jiffies <%lx>\n" 5780 " desc.status <%x>\n", 5781 tx_ring->queue_index, 5782 rd32(E1000_TDH(tx_ring->reg_idx)), 5783 readl(tx_ring->tail), 5784 tx_ring->next_to_use, 5785 tx_ring->next_to_clean, 5786 tx_buffer->time_stamp, 5787 tx_buffer->next_to_watch, 5788 jiffies, 5789 tx_buffer->next_to_watch->wb.status); 5790 netif_stop_subqueue(tx_ring->netdev, 5791 tx_ring->queue_index); 5792 5793 /* we are about to reset, no point in enabling stuff */ 5794 return true; 5795 } 5796 } 5797 5798 if (unlikely(total_packets && 5799 netif_carrier_ok(tx_ring->netdev) && 5800 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) { 5801 /* Make sure that anybody stopping the queue after this 5802 * sees the new next_to_clean. 5803 */ 5804 smp_mb(); 5805 if (__netif_subqueue_stopped(tx_ring->netdev, 5806 tx_ring->queue_index) && 5807 !(test_bit(__IGB_DOWN, &adapter->state))) { 5808 netif_wake_subqueue(tx_ring->netdev, 5809 tx_ring->queue_index); 5810 5811 u64_stats_update_begin(&tx_ring->tx_syncp); 5812 tx_ring->tx_stats.restart_queue++; 5813 u64_stats_update_end(&tx_ring->tx_syncp); 5814 } 5815 } 5816 5817 return !!budget; 5818} 5819 5820/** 5821 * igb_reuse_rx_page - page flip buffer and store it back on the ring 5822 * @rx_ring: rx descriptor ring to store buffers on 5823 * @old_buff: donor buffer to have page reused 5824 * 5825 * Synchronizes page for reuse by the adapter 5826 **/ 5827static void igb_reuse_rx_page(struct igb_ring *rx_ring, 5828 struct igb_rx_buffer *old_buff) 5829{ 5830 struct igb_rx_buffer *new_buff; 5831 u16 nta = rx_ring->next_to_alloc; 5832 5833 new_buff = &rx_ring->rx_buffer_info[nta]; 5834 5835 /* update, and store next to alloc */ 5836 nta++; 5837 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 5838 5839 /* transfer page from old buffer to new buffer */ 5840 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); 5841 5842 /* sync the buffer for use by the device */ 5843 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 5844 old_buff->page_offset, 5845 IGB_RX_BUFSZ, 5846 DMA_FROM_DEVICE); 5847} 5848 5849/** 5850 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 5851 * @rx_ring: rx descriptor ring to transact packets on 5852 * @rx_buffer: buffer containing page to add 5853 * @rx_desc: descriptor containing length of buffer written by hardware 5854 * @skb: sk_buff to place the data into 5855 * 5856 * This function will add the data contained in rx_buffer->page to the skb. 5857 * This is done either through a direct copy if the data in the buffer is 5858 * less than the skb header size, otherwise it will just attach the page as 5859 * a frag to the skb. 5860 * 5861 * The function will then update the page offset if necessary and return 5862 * true if the buffer can be reused by the adapter. 5863 **/ 5864static bool igb_add_rx_frag(struct igb_ring *rx_ring, 5865 struct igb_rx_buffer *rx_buffer, 5866 union e1000_adv_rx_desc *rx_desc, 5867 struct sk_buff *skb) 5868{ 5869 struct page *page = rx_buffer->page; 5870 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 5871 5872 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { 5873 unsigned char *va = page_address(page) + rx_buffer->page_offset; 5874 5875 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 5876 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 5877 va += IGB_TS_HDR_LEN; 5878 size -= IGB_TS_HDR_LEN; 5879 } 5880 5881 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 5882 5883 /* we can reuse buffer as-is, just make sure it is local */ 5884 if (likely(page_to_nid(page) == numa_node_id())) 5885 return true; 5886 5887 /* this page cannot be reused so discard it */ 5888 put_page(page); 5889 return false; 5890 } 5891 5892 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 5893 rx_buffer->page_offset, size, IGB_RX_BUFSZ); 5894 5895 /* avoid re-using remote pages */ 5896 if (unlikely(page_to_nid(page) != numa_node_id())) 5897 return false; 5898 5899#if (PAGE_SIZE < 8192) 5900 /* if we are only owner of page we can reuse it */ 5901 if (unlikely(page_count(page) != 1)) 5902 return false; 5903 5904 /* flip page offset to other buffer */ 5905 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 5906 5907 /* 5908 * since we are the only owner of the page and we need to 5909 * increment it, just set the value to 2 in order to avoid 5910 * an unnecessary locked operation 5911 */ 5912 atomic_set(&page->_count, 2); 5913#else 5914 /* move offset up to the next cache line */ 5915 rx_buffer->page_offset += SKB_DATA_ALIGN(size); 5916 5917 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 5918 return false; 5919 5920 /* bump ref count on page before it is given to the stack */ 5921 get_page(page); 5922#endif 5923 5924 return true; 5925} 5926 5927static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 5928 union e1000_adv_rx_desc *rx_desc, 5929 struct sk_buff *skb) 5930{ 5931 struct igb_rx_buffer *rx_buffer; 5932 struct page *page; 5933 5934 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 5935 5936 /* 5937 * This memory barrier is needed to keep us from reading 5938 * any other fields out of the rx_desc until we know the 5939 * RXD_STAT_DD bit is set 5940 */ 5941 rmb(); 5942 5943 page = rx_buffer->page; 5944 prefetchw(page); 5945 5946 if (likely(!skb)) { 5947 void *page_addr = page_address(page) + 5948 rx_buffer->page_offset; 5949 5950 /* prefetch first cache line of first page */ 5951 prefetch(page_addr); 5952#if L1_CACHE_BYTES < 128 5953 prefetch(page_addr + L1_CACHE_BYTES); 5954#endif 5955 5956 /* allocate a skb to store the frags */ 5957 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 5958 IGB_RX_HDR_LEN); 5959 if (unlikely(!skb)) { 5960 rx_ring->rx_stats.alloc_failed++; 5961 return NULL; 5962 } 5963 5964 /* 5965 * we will be copying header into skb->data in 5966 * pskb_may_pull so it is in our interest to prefetch 5967 * it now to avoid a possible cache miss 5968 */ 5969 prefetchw(skb->data); 5970 } 5971 5972 /* we are reusing so sync this buffer for CPU use */ 5973 dma_sync_single_range_for_cpu(rx_ring->dev, 5974 rx_buffer->dma, 5975 rx_buffer->page_offset, 5976 IGB_RX_BUFSZ, 5977 DMA_FROM_DEVICE); 5978 5979 /* pull page into skb */ 5980 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 5981 /* hand second half of page back to the ring */ 5982 igb_reuse_rx_page(rx_ring, rx_buffer); 5983 } else { 5984 /* we are not reusing the buffer so unmap it */ 5985 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 5986 PAGE_SIZE, DMA_FROM_DEVICE); 5987 } 5988 5989 /* clear contents of rx_buffer */ 5990 rx_buffer->page = NULL; 5991 5992 return skb; 5993} 5994 5995static inline void igb_rx_checksum(struct igb_ring *ring, 5996 union e1000_adv_rx_desc *rx_desc, 5997 struct sk_buff *skb) 5998{ 5999 skb_checksum_none_assert(skb); 6000 6001 /* Ignore Checksum bit is set */ 6002 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6003 return; 6004 6005 /* Rx checksum disabled via ethtool */ 6006 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6007 return; 6008 6009 /* TCP/UDP checksum error bit is set */ 6010 if (igb_test_staterr(rx_desc, 6011 E1000_RXDEXT_STATERR_TCPE | 6012 E1000_RXDEXT_STATERR_IPE)) { 6013 /* 6014 * work around errata with sctp packets where the TCPE aka 6015 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6016 * packets, (aka let the stack check the crc32c) 6017 */ 6018 if (!((skb->len == 60) && 6019 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6020 u64_stats_update_begin(&ring->rx_syncp); 6021 ring->rx_stats.csum_err++; 6022 u64_stats_update_end(&ring->rx_syncp); 6023 } 6024 /* let the stack verify checksum errors */ 6025 return; 6026 } 6027 /* It must be a TCP or UDP packet with a valid checksum */ 6028 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 6029 E1000_RXD_STAT_UDPCS)) 6030 skb->ip_summed = CHECKSUM_UNNECESSARY; 6031 6032 dev_dbg(ring->dev, "cksum success: bits %08X\n", 6033 le32_to_cpu(rx_desc->wb.upper.status_error)); 6034} 6035 6036static inline void igb_rx_hash(struct igb_ring *ring, 6037 union e1000_adv_rx_desc *rx_desc, 6038 struct sk_buff *skb) 6039{ 6040 if (ring->netdev->features & NETIF_F_RXHASH) 6041 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); 6042} 6043 6044/** 6045 * igb_is_non_eop - process handling of non-EOP buffers 6046 * @rx_ring: Rx ring being processed 6047 * @rx_desc: Rx descriptor for current buffer 6048 * @skb: current socket buffer containing buffer in progress 6049 * 6050 * This function updates next to clean. If the buffer is an EOP buffer 6051 * this function exits returning false, otherwise it will place the 6052 * sk_buff in the next buffer to be chained and return true indicating 6053 * that this is in fact a non-EOP buffer. 6054 **/ 6055static bool igb_is_non_eop(struct igb_ring *rx_ring, 6056 union e1000_adv_rx_desc *rx_desc) 6057{ 6058 u32 ntc = rx_ring->next_to_clean + 1; 6059 6060 /* fetch, update, and store next to clean */ 6061 ntc = (ntc < rx_ring->count) ? ntc : 0; 6062 rx_ring->next_to_clean = ntc; 6063 6064 prefetch(IGB_RX_DESC(rx_ring, ntc)); 6065 6066 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 6067 return false; 6068 6069 return true; 6070} 6071 6072/** 6073 * igb_get_headlen - determine size of header for LRO/GRO 6074 * @data: pointer to the start of the headers 6075 * @max_len: total length of section to find headers in 6076 * 6077 * This function is meant to determine the length of headers that will 6078 * be recognized by hardware for LRO, and GRO offloads. The main 6079 * motivation of doing this is to only perform one pull for IPv4 TCP 6080 * packets so that we can do basic things like calculating the gso_size 6081 * based on the average data per packet. 6082 **/ 6083static unsigned int igb_get_headlen(unsigned char *data, 6084 unsigned int max_len) 6085{ 6086 union { 6087 unsigned char *network; 6088 /* l2 headers */ 6089 struct ethhdr *eth; 6090 struct vlan_hdr *vlan; 6091 /* l3 headers */ 6092 struct iphdr *ipv4; 6093 struct ipv6hdr *ipv6; 6094 } hdr; 6095 __be16 protocol; 6096 u8 nexthdr = 0; /* default to not TCP */ 6097 u8 hlen; 6098 6099 /* this should never happen, but better safe than sorry */ 6100 if (max_len < ETH_HLEN) 6101 return max_len; 6102 6103 /* initialize network frame pointer */ 6104 hdr.network = data; 6105 6106 /* set first protocol and move network header forward */ 6107 protocol = hdr.eth->h_proto; 6108 hdr.network += ETH_HLEN; 6109 6110 /* handle any vlan tag if present */ 6111 if (protocol == __constant_htons(ETH_P_8021Q)) { 6112 if ((hdr.network - data) > (max_len - VLAN_HLEN)) 6113 return max_len; 6114 6115 protocol = hdr.vlan->h_vlan_encapsulated_proto; 6116 hdr.network += VLAN_HLEN; 6117 } 6118 6119 /* handle L3 protocols */ 6120 if (protocol == __constant_htons(ETH_P_IP)) { 6121 if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) 6122 return max_len; 6123 6124 /* access ihl as a u8 to avoid unaligned access on ia64 */ 6125 hlen = (hdr.network[0] & 0x0F) << 2; 6126 6127 /* verify hlen meets minimum size requirements */ 6128 if (hlen < sizeof(struct iphdr)) 6129 return hdr.network - data; 6130 6131 /* record next protocol */ 6132 nexthdr = hdr.ipv4->protocol; 6133 hdr.network += hlen; 6134 } else if (protocol == __constant_htons(ETH_P_IPV6)) { 6135 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) 6136 return max_len; 6137 6138 /* record next protocol */ 6139 nexthdr = hdr.ipv6->nexthdr; 6140 hdr.network += sizeof(struct ipv6hdr); 6141 } else { 6142 return hdr.network - data; 6143 } 6144 6145 /* finally sort out TCP */ 6146 if (nexthdr == IPPROTO_TCP) { 6147 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) 6148 return max_len; 6149 6150 /* access doff as a u8 to avoid unaligned access on ia64 */ 6151 hlen = (hdr.network[12] & 0xF0) >> 2; 6152 6153 /* verify hlen meets minimum size requirements */ 6154 if (hlen < sizeof(struct tcphdr)) 6155 return hdr.network - data; 6156 6157 hdr.network += hlen; 6158 } else if (nexthdr == IPPROTO_UDP) { 6159 if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) 6160 return max_len; 6161 6162 hdr.network += sizeof(struct udphdr); 6163 } 6164 6165 /* 6166 * If everything has gone correctly hdr.network should be the 6167 * data section of the packet and will be the end of the header. 6168 * If not then it probably represents the end of the last recognized 6169 * header. 6170 */ 6171 if ((hdr.network - data) < max_len) 6172 return hdr.network - data; 6173 else 6174 return max_len; 6175} 6176 6177/** 6178 * igb_pull_tail - igb specific version of skb_pull_tail 6179 * @rx_ring: rx descriptor ring packet is being transacted on 6180 * @rx_desc: pointer to the EOP Rx descriptor 6181 * @skb: pointer to current skb being adjusted 6182 * 6183 * This function is an igb specific version of __pskb_pull_tail. The 6184 * main difference between this version and the original function is that 6185 * this function can make several assumptions about the state of things 6186 * that allow for significant optimizations versus the standard function. 6187 * As a result we can do things like drop a frag and maintain an accurate 6188 * truesize for the skb. 6189 */ 6190static void igb_pull_tail(struct igb_ring *rx_ring, 6191 union e1000_adv_rx_desc *rx_desc, 6192 struct sk_buff *skb) 6193{ 6194 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6195 unsigned char *va; 6196 unsigned int pull_len; 6197 6198 /* 6199 * it is valid to use page_address instead of kmap since we are 6200 * working with pages allocated out of the lomem pool per 6201 * alloc_page(GFP_ATOMIC) 6202 */ 6203 va = skb_frag_address(frag); 6204 6205 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6206 /* retrieve timestamp from buffer */ 6207 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6208 6209 /* update pointers to remove timestamp header */ 6210 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); 6211 frag->page_offset += IGB_TS_HDR_LEN; 6212 skb->data_len -= IGB_TS_HDR_LEN; 6213 skb->len -= IGB_TS_HDR_LEN; 6214 6215 /* move va to start of packet data */ 6216 va += IGB_TS_HDR_LEN; 6217 } 6218 6219 /* 6220 * we need the header to contain the greater of either ETH_HLEN or 6221 * 60 bytes if the skb->len is less than 60 for skb_pad. 6222 */ 6223 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); 6224 6225 /* align pull length to size of long to optimize memcpy performance */ 6226 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 6227 6228 /* update all of the pointers */ 6229 skb_frag_size_sub(frag, pull_len); 6230 frag->page_offset += pull_len; 6231 skb->data_len -= pull_len; 6232 skb->tail += pull_len; 6233} 6234 6235/** 6236 * igb_cleanup_headers - Correct corrupted or empty headers 6237 * @rx_ring: rx descriptor ring packet is being transacted on 6238 * @rx_desc: pointer to the EOP Rx descriptor 6239 * @skb: pointer to current skb being fixed 6240 * 6241 * Address the case where we are pulling data in on pages only 6242 * and as such no data is present in the skb header. 6243 * 6244 * In addition if skb is not at least 60 bytes we need to pad it so that 6245 * it is large enough to qualify as a valid Ethernet frame. 6246 * 6247 * Returns true if an error was encountered and skb was freed. 6248 **/ 6249static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6250 union e1000_adv_rx_desc *rx_desc, 6251 struct sk_buff *skb) 6252{ 6253 6254 if (unlikely((igb_test_staterr(rx_desc, 6255 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6256 struct net_device *netdev = rx_ring->netdev; 6257 if (!(netdev->features & NETIF_F_RXALL)) { 6258 dev_kfree_skb_any(skb); 6259 return true; 6260 } 6261 } 6262 6263 /* place header in linear portion of buffer */ 6264 if (skb_is_nonlinear(skb)) 6265 igb_pull_tail(rx_ring, rx_desc, skb); 6266 6267 /* if skb_pad returns an error the skb was freed */ 6268 if (unlikely(skb->len < 60)) { 6269 int pad_len = 60 - skb->len; 6270 6271 if (skb_pad(skb, pad_len)) 6272 return true; 6273 __skb_put(skb, pad_len); 6274 } 6275 6276 return false; 6277} 6278 6279/** 6280 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6281 * @rx_ring: rx descriptor ring packet is being transacted on 6282 * @rx_desc: pointer to the EOP Rx descriptor 6283 * @skb: pointer to current skb being populated 6284 * 6285 * This function checks the ring, descriptor, and packet information in 6286 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6287 * other fields within the skb. 6288 **/ 6289static void igb_process_skb_fields(struct igb_ring *rx_ring, 6290 union e1000_adv_rx_desc *rx_desc, 6291 struct sk_buff *skb) 6292{ 6293 struct net_device *dev = rx_ring->netdev; 6294 6295 igb_rx_hash(rx_ring, rx_desc, skb); 6296 6297 igb_rx_checksum(rx_ring, rx_desc, skb); 6298 6299 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb); 6300 6301 if ((dev->features & NETIF_F_HW_VLAN_RX) && 6302 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6303 u16 vid; 6304 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6305 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6306 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6307 else 6308 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6309 6310 __vlan_hwaccel_put_tag(skb, vid); 6311 } 6312 6313 skb_record_rx_queue(skb, rx_ring->queue_index); 6314 6315 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6316} 6317 6318static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 6319{ 6320 struct igb_ring *rx_ring = q_vector->rx.ring; 6321 struct sk_buff *skb = rx_ring->skb; 6322 unsigned int total_bytes = 0, total_packets = 0; 6323 u16 cleaned_count = igb_desc_unused(rx_ring); 6324 6325 do { 6326 union e1000_adv_rx_desc *rx_desc; 6327 6328 /* return some buffers to hardware, one at a time is too slow */ 6329 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6330 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6331 cleaned_count = 0; 6332 } 6333 6334 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 6335 6336 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) 6337 break; 6338 6339 /* retrieve a buffer from the ring */ 6340 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 6341 6342 /* exit if we failed to retrieve a buffer */ 6343 if (!skb) 6344 break; 6345 6346 cleaned_count++; 6347 6348 /* fetch next buffer in frame if non-eop */ 6349 if (igb_is_non_eop(rx_ring, rx_desc)) 6350 continue; 6351 6352 /* verify the packet layout is correct */ 6353 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 6354 skb = NULL; 6355 continue; 6356 } 6357 6358 /* probably a little skewed due to removing CRC */ 6359 total_bytes += skb->len; 6360 6361 /* populate checksum, timestamp, VLAN, and protocol */ 6362 igb_process_skb_fields(rx_ring, rx_desc, skb); 6363 6364 napi_gro_receive(&q_vector->napi, skb); 6365 6366 /* reset skb pointer */ 6367 skb = NULL; 6368 6369 /* update budget accounting */ 6370 total_packets++; 6371 } while (likely(total_packets < budget)); 6372 6373 /* place incomplete frames back on ring for completion */ 6374 rx_ring->skb = skb; 6375 6376 u64_stats_update_begin(&rx_ring->rx_syncp); 6377 rx_ring->rx_stats.packets += total_packets; 6378 rx_ring->rx_stats.bytes += total_bytes; 6379 u64_stats_update_end(&rx_ring->rx_syncp); 6380 q_vector->rx.total_packets += total_packets; 6381 q_vector->rx.total_bytes += total_bytes; 6382 6383 if (cleaned_count) 6384 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6385 6386 return (total_packets < budget); 6387} 6388 6389static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 6390 struct igb_rx_buffer *bi) 6391{ 6392 struct page *page = bi->page; 6393 dma_addr_t dma; 6394 6395 /* since we are recycling buffers we should seldom need to alloc */ 6396 if (likely(page)) 6397 return true; 6398 6399 /* alloc new page for storage */ 6400 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); 6401 if (unlikely(!page)) { 6402 rx_ring->rx_stats.alloc_failed++; 6403 return false; 6404 } 6405 6406 /* map page for use */ 6407 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 6408 6409 /* 6410 * if mapping failed free memory back to system since 6411 * there isn't much point in holding memory we can't use 6412 */ 6413 if (dma_mapping_error(rx_ring->dev, dma)) { 6414 __free_page(page); 6415 6416 rx_ring->rx_stats.alloc_failed++; 6417 return false; 6418 } 6419 6420 bi->dma = dma; 6421 bi->page = page; 6422 bi->page_offset = 0; 6423 6424 return true; 6425} 6426 6427/** 6428 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 6429 * @adapter: address of board private structure 6430 **/ 6431void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 6432{ 6433 union e1000_adv_rx_desc *rx_desc; 6434 struct igb_rx_buffer *bi; 6435 u16 i = rx_ring->next_to_use; 6436 6437 /* nothing to do */ 6438 if (!cleaned_count) 6439 return; 6440 6441 rx_desc = IGB_RX_DESC(rx_ring, i); 6442 bi = &rx_ring->rx_buffer_info[i]; 6443 i -= rx_ring->count; 6444 6445 do { 6446 if (!igb_alloc_mapped_page(rx_ring, bi)) 6447 break; 6448 6449 /* 6450 * Refresh the desc even if buffer_addrs didn't change 6451 * because each write-back erases this info. 6452 */ 6453 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 6454 6455 rx_desc++; 6456 bi++; 6457 i++; 6458 if (unlikely(!i)) { 6459 rx_desc = IGB_RX_DESC(rx_ring, 0); 6460 bi = rx_ring->rx_buffer_info; 6461 i -= rx_ring->count; 6462 } 6463 6464 /* clear the hdr_addr for the next_to_use descriptor */ 6465 rx_desc->read.hdr_addr = 0; 6466 6467 cleaned_count--; 6468 } while (cleaned_count); 6469 6470 i += rx_ring->count; 6471 6472 if (rx_ring->next_to_use != i) { 6473 /* record the next descriptor to use */ 6474 rx_ring->next_to_use = i; 6475 6476 /* update next to alloc since we have filled the ring */ 6477 rx_ring->next_to_alloc = i; 6478 6479 /* 6480 * Force memory writes to complete before letting h/w 6481 * know there are new descriptors to fetch. (Only 6482 * applicable for weak-ordered memory model archs, 6483 * such as IA-64). 6484 */ 6485 wmb(); 6486 writel(i, rx_ring->tail); 6487 } 6488} 6489 6490/** 6491 * igb_mii_ioctl - 6492 * @netdev: 6493 * @ifreq: 6494 * @cmd: 6495 **/ 6496static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6497{ 6498 struct igb_adapter *adapter = netdev_priv(netdev); 6499 struct mii_ioctl_data *data = if_mii(ifr); 6500 6501 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6502 return -EOPNOTSUPP; 6503 6504 switch (cmd) { 6505 case SIOCGMIIPHY: 6506 data->phy_id = adapter->hw.phy.addr; 6507 break; 6508 case SIOCGMIIREG: 6509 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 6510 &data->val_out)) 6511 return -EIO; 6512 break; 6513 case SIOCSMIIREG: 6514 default: 6515 return -EOPNOTSUPP; 6516 } 6517 return 0; 6518} 6519 6520/** 6521 * igb_ioctl - 6522 * @netdev: 6523 * @ifreq: 6524 * @cmd: 6525 **/ 6526static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6527{ 6528 switch (cmd) { 6529 case SIOCGMIIPHY: 6530 case SIOCGMIIREG: 6531 case SIOCSMIIREG: 6532 return igb_mii_ioctl(netdev, ifr, cmd); 6533 case SIOCSHWTSTAMP: 6534 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd); 6535 default: 6536 return -EOPNOTSUPP; 6537 } 6538} 6539 6540s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 6541{ 6542 struct igb_adapter *adapter = hw->back; 6543 6544 if (pcie_capability_read_word(adapter->pdev, reg, value)) 6545 return -E1000_ERR_CONFIG; 6546 6547 return 0; 6548} 6549 6550s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 6551{ 6552 struct igb_adapter *adapter = hw->back; 6553 6554 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 6555 return -E1000_ERR_CONFIG; 6556 6557 return 0; 6558} 6559 6560static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 6561{ 6562 struct igb_adapter *adapter = netdev_priv(netdev); 6563 struct e1000_hw *hw = &adapter->hw; 6564 u32 ctrl, rctl; 6565 bool enable = !!(features & NETIF_F_HW_VLAN_RX); 6566 6567 if (enable) { 6568 /* enable VLAN tag insert/strip */ 6569 ctrl = rd32(E1000_CTRL); 6570 ctrl |= E1000_CTRL_VME; 6571 wr32(E1000_CTRL, ctrl); 6572 6573 /* Disable CFI check */ 6574 rctl = rd32(E1000_RCTL); 6575 rctl &= ~E1000_RCTL_CFIEN; 6576 wr32(E1000_RCTL, rctl); 6577 } else { 6578 /* disable VLAN tag insert/strip */ 6579 ctrl = rd32(E1000_CTRL); 6580 ctrl &= ~E1000_CTRL_VME; 6581 wr32(E1000_CTRL, ctrl); 6582 } 6583 6584 igb_rlpml_set(adapter); 6585} 6586 6587static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) 6588{ 6589 struct igb_adapter *adapter = netdev_priv(netdev); 6590 struct e1000_hw *hw = &adapter->hw; 6591 int pf_id = adapter->vfs_allocated_count; 6592 6593 /* attempt to add filter to vlvf array */ 6594 igb_vlvf_set(adapter, vid, true, pf_id); 6595 6596 /* add the filter since PF can receive vlans w/o entry in vlvf */ 6597 igb_vfta_set(hw, vid, true); 6598 6599 set_bit(vid, adapter->active_vlans); 6600 6601 return 0; 6602} 6603 6604static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) 6605{ 6606 struct igb_adapter *adapter = netdev_priv(netdev); 6607 struct e1000_hw *hw = &adapter->hw; 6608 int pf_id = adapter->vfs_allocated_count; 6609 s32 err; 6610 6611 /* remove vlan from VLVF table array */ 6612 err = igb_vlvf_set(adapter, vid, false, pf_id); 6613 6614 /* if vid was not present in VLVF just remove it from table */ 6615 if (err) 6616 igb_vfta_set(hw, vid, false); 6617 6618 clear_bit(vid, adapter->active_vlans); 6619 6620 return 0; 6621} 6622 6623static void igb_restore_vlan(struct igb_adapter *adapter) 6624{ 6625 u16 vid; 6626 6627 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 6628 6629 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 6630 igb_vlan_rx_add_vid(adapter->netdev, vid); 6631} 6632 6633int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 6634{ 6635 struct pci_dev *pdev = adapter->pdev; 6636 struct e1000_mac_info *mac = &adapter->hw.mac; 6637 6638 mac->autoneg = 0; 6639 6640 /* Make sure dplx is at most 1 bit and lsb of speed is not set 6641 * for the switch() below to work */ 6642 if ((spd & 1) || (dplx & ~1)) 6643 goto err_inval; 6644 6645 /* Fiber NIC's only allow 1000 Gbps Full duplex */ 6646 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) && 6647 spd != SPEED_1000 && 6648 dplx != DUPLEX_FULL) 6649 goto err_inval; 6650 6651 switch (spd + dplx) { 6652 case SPEED_10 + DUPLEX_HALF: 6653 mac->forced_speed_duplex = ADVERTISE_10_HALF; 6654 break; 6655 case SPEED_10 + DUPLEX_FULL: 6656 mac->forced_speed_duplex = ADVERTISE_10_FULL; 6657 break; 6658 case SPEED_100 + DUPLEX_HALF: 6659 mac->forced_speed_duplex = ADVERTISE_100_HALF; 6660 break; 6661 case SPEED_100 + DUPLEX_FULL: 6662 mac->forced_speed_duplex = ADVERTISE_100_FULL; 6663 break; 6664 case SPEED_1000 + DUPLEX_FULL: 6665 mac->autoneg = 1; 6666 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 6667 break; 6668 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 6669 default: 6670 goto err_inval; 6671 } 6672 6673 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 6674 adapter->hw.phy.mdix = AUTO_ALL_MODES; 6675 6676 return 0; 6677 6678err_inval: 6679 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 6680 return -EINVAL; 6681} 6682 6683static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 6684 bool runtime) 6685{ 6686 struct net_device *netdev = pci_get_drvdata(pdev); 6687 struct igb_adapter *adapter = netdev_priv(netdev); 6688 struct e1000_hw *hw = &adapter->hw; 6689 u32 ctrl, rctl, status; 6690 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 6691#ifdef CONFIG_PM 6692 int retval = 0; 6693#endif 6694 6695 netif_device_detach(netdev); 6696 6697 if (netif_running(netdev)) 6698 __igb_close(netdev, true); 6699 6700 igb_clear_interrupt_scheme(adapter); 6701 6702#ifdef CONFIG_PM 6703 retval = pci_save_state(pdev); 6704 if (retval) 6705 return retval; 6706#endif 6707 6708 status = rd32(E1000_STATUS); 6709 if (status & E1000_STATUS_LU) 6710 wufc &= ~E1000_WUFC_LNKC; 6711 6712 if (wufc) { 6713 igb_setup_rctl(adapter); 6714 igb_set_rx_mode(netdev); 6715 6716 /* turn on all-multi mode if wake on multicast is enabled */ 6717 if (wufc & E1000_WUFC_MC) { 6718 rctl = rd32(E1000_RCTL); 6719 rctl |= E1000_RCTL_MPE; 6720 wr32(E1000_RCTL, rctl); 6721 } 6722 6723 ctrl = rd32(E1000_CTRL); 6724 /* advertise wake from D3Cold */ 6725 #define E1000_CTRL_ADVD3WUC 0x00100000 6726 /* phy power management enable */ 6727 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 6728 ctrl |= E1000_CTRL_ADVD3WUC; 6729 wr32(E1000_CTRL, ctrl); 6730 6731 /* Allow time for pending master requests to run */ 6732 igb_disable_pcie_master(hw); 6733 6734 wr32(E1000_WUC, E1000_WUC_PME_EN); 6735 wr32(E1000_WUFC, wufc); 6736 } else { 6737 wr32(E1000_WUC, 0); 6738 wr32(E1000_WUFC, 0); 6739 } 6740 6741 *enable_wake = wufc || adapter->en_mng_pt; 6742 if (!*enable_wake) 6743 igb_power_down_link(adapter); 6744 else 6745 igb_power_up_link(adapter); 6746 6747 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6748 * would have already happened in close and is redundant. */ 6749 igb_release_hw_control(adapter); 6750 6751 pci_disable_device(pdev); 6752 6753 return 0; 6754} 6755 6756#ifdef CONFIG_PM 6757#ifdef CONFIG_PM_SLEEP 6758static int igb_suspend(struct device *dev) 6759{ 6760 int retval; 6761 bool wake; 6762 struct pci_dev *pdev = to_pci_dev(dev); 6763 6764 retval = __igb_shutdown(pdev, &wake, 0); 6765 if (retval) 6766 return retval; 6767 6768 if (wake) { 6769 pci_prepare_to_sleep(pdev); 6770 } else { 6771 pci_wake_from_d3(pdev, false); 6772 pci_set_power_state(pdev, PCI_D3hot); 6773 } 6774 6775 return 0; 6776} 6777#endif /* CONFIG_PM_SLEEP */ 6778 6779static int igb_resume(struct device *dev) 6780{ 6781 struct pci_dev *pdev = to_pci_dev(dev); 6782 struct net_device *netdev = pci_get_drvdata(pdev); 6783 struct igb_adapter *adapter = netdev_priv(netdev); 6784 struct e1000_hw *hw = &adapter->hw; 6785 u32 err; 6786 6787 pci_set_power_state(pdev, PCI_D0); 6788 pci_restore_state(pdev); 6789 pci_save_state(pdev); 6790 6791 err = pci_enable_device_mem(pdev); 6792 if (err) { 6793 dev_err(&pdev->dev, 6794 "igb: Cannot enable PCI device from suspend\n"); 6795 return err; 6796 } 6797 pci_set_master(pdev); 6798 6799 pci_enable_wake(pdev, PCI_D3hot, 0); 6800 pci_enable_wake(pdev, PCI_D3cold, 0); 6801 6802 if (igb_init_interrupt_scheme(adapter)) { 6803 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 6804 return -ENOMEM; 6805 } 6806 6807 igb_reset(adapter); 6808 6809 /* let the f/w know that the h/w is now under the control of the 6810 * driver. */ 6811 igb_get_hw_control(adapter); 6812 6813 wr32(E1000_WUS, ~0); 6814 6815 if (netdev->flags & IFF_UP) { 6816 rtnl_lock(); 6817 err = __igb_open(netdev, true); 6818 rtnl_unlock(); 6819 if (err) 6820 return err; 6821 } 6822 6823 netif_device_attach(netdev); 6824 return 0; 6825} 6826 6827#ifdef CONFIG_PM_RUNTIME 6828static int igb_runtime_idle(struct device *dev) 6829{ 6830 struct pci_dev *pdev = to_pci_dev(dev); 6831 struct net_device *netdev = pci_get_drvdata(pdev); 6832 struct igb_adapter *adapter = netdev_priv(netdev); 6833 6834 if (!igb_has_link(adapter)) 6835 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 6836 6837 return -EBUSY; 6838} 6839 6840static int igb_runtime_suspend(struct device *dev) 6841{ 6842 struct pci_dev *pdev = to_pci_dev(dev); 6843 int retval; 6844 bool wake; 6845 6846 retval = __igb_shutdown(pdev, &wake, 1); 6847 if (retval) 6848 return retval; 6849 6850 if (wake) { 6851 pci_prepare_to_sleep(pdev); 6852 } else { 6853 pci_wake_from_d3(pdev, false); 6854 pci_set_power_state(pdev, PCI_D3hot); 6855 } 6856 6857 return 0; 6858} 6859 6860static int igb_runtime_resume(struct device *dev) 6861{ 6862 return igb_resume(dev); 6863} 6864#endif /* CONFIG_PM_RUNTIME */ 6865#endif 6866 6867static void igb_shutdown(struct pci_dev *pdev) 6868{ 6869 bool wake; 6870 6871 __igb_shutdown(pdev, &wake, 0); 6872 6873 if (system_state == SYSTEM_POWER_OFF) { 6874 pci_wake_from_d3(pdev, wake); 6875 pci_set_power_state(pdev, PCI_D3hot); 6876 } 6877} 6878 6879#ifdef CONFIG_NET_POLL_CONTROLLER 6880/* 6881 * Polling 'interrupt' - used by things like netconsole to send skbs 6882 * without having to re-enable interrupts. It's not called while 6883 * the interrupt routine is executing. 6884 */ 6885static void igb_netpoll(struct net_device *netdev) 6886{ 6887 struct igb_adapter *adapter = netdev_priv(netdev); 6888 struct e1000_hw *hw = &adapter->hw; 6889 struct igb_q_vector *q_vector; 6890 int i; 6891 6892 for (i = 0; i < adapter->num_q_vectors; i++) { 6893 q_vector = adapter->q_vector[i]; 6894 if (adapter->msix_entries) 6895 wr32(E1000_EIMC, q_vector->eims_value); 6896 else 6897 igb_irq_disable(adapter); 6898 napi_schedule(&q_vector->napi); 6899 } 6900} 6901#endif /* CONFIG_NET_POLL_CONTROLLER */ 6902 6903/** 6904 * igb_io_error_detected - called when PCI error is detected 6905 * @pdev: Pointer to PCI device 6906 * @state: The current pci connection state 6907 * 6908 * This function is called after a PCI bus error affecting 6909 * this device has been detected. 6910 */ 6911static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 6912 pci_channel_state_t state) 6913{ 6914 struct net_device *netdev = pci_get_drvdata(pdev); 6915 struct igb_adapter *adapter = netdev_priv(netdev); 6916 6917 netif_device_detach(netdev); 6918 6919 if (state == pci_channel_io_perm_failure) 6920 return PCI_ERS_RESULT_DISCONNECT; 6921 6922 if (netif_running(netdev)) 6923 igb_down(adapter); 6924 pci_disable_device(pdev); 6925 6926 /* Request a slot slot reset. */ 6927 return PCI_ERS_RESULT_NEED_RESET; 6928} 6929 6930/** 6931 * igb_io_slot_reset - called after the pci bus has been reset. 6932 * @pdev: Pointer to PCI device 6933 * 6934 * Restart the card from scratch, as if from a cold-boot. Implementation 6935 * resembles the first-half of the igb_resume routine. 6936 */ 6937static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 6938{ 6939 struct net_device *netdev = pci_get_drvdata(pdev); 6940 struct igb_adapter *adapter = netdev_priv(netdev); 6941 struct e1000_hw *hw = &adapter->hw; 6942 pci_ers_result_t result; 6943 int err; 6944 6945 if (pci_enable_device_mem(pdev)) { 6946 dev_err(&pdev->dev, 6947 "Cannot re-enable PCI device after reset.\n"); 6948 result = PCI_ERS_RESULT_DISCONNECT; 6949 } else { 6950 pci_set_master(pdev); 6951 pci_restore_state(pdev); 6952 pci_save_state(pdev); 6953 6954 pci_enable_wake(pdev, PCI_D3hot, 0); 6955 pci_enable_wake(pdev, PCI_D3cold, 0); 6956 6957 igb_reset(adapter); 6958 wr32(E1000_WUS, ~0); 6959 result = PCI_ERS_RESULT_RECOVERED; 6960 } 6961 6962 err = pci_cleanup_aer_uncorrect_error_status(pdev); 6963 if (err) { 6964 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status " 6965 "failed 0x%0x\n", err); 6966 /* non-fatal, continue */ 6967 } 6968 6969 return result; 6970} 6971 6972/** 6973 * igb_io_resume - called when traffic can start flowing again. 6974 * @pdev: Pointer to PCI device 6975 * 6976 * This callback is called when the error recovery driver tells us that 6977 * its OK to resume normal operation. Implementation resembles the 6978 * second-half of the igb_resume routine. 6979 */ 6980static void igb_io_resume(struct pci_dev *pdev) 6981{ 6982 struct net_device *netdev = pci_get_drvdata(pdev); 6983 struct igb_adapter *adapter = netdev_priv(netdev); 6984 6985 if (netif_running(netdev)) { 6986 if (igb_up(adapter)) { 6987 dev_err(&pdev->dev, "igb_up failed after reset\n"); 6988 return; 6989 } 6990 } 6991 6992 netif_device_attach(netdev); 6993 6994 /* let the f/w know that the h/w is now under the control of the 6995 * driver. */ 6996 igb_get_hw_control(adapter); 6997} 6998 6999static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7000 u8 qsel) 7001{ 7002 u32 rar_low, rar_high; 7003 struct e1000_hw *hw = &adapter->hw; 7004 7005 /* HW expects these in little endian so we reverse the byte order 7006 * from network order (big endian) to little endian 7007 */ 7008 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 7009 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 7010 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 7011 7012 /* Indicate to hardware the Address is Valid. */ 7013 rar_high |= E1000_RAH_AV; 7014 7015 if (hw->mac.type == e1000_82575) 7016 rar_high |= E1000_RAH_POOL_1 * qsel; 7017 else 7018 rar_high |= E1000_RAH_POOL_1 << qsel; 7019 7020 wr32(E1000_RAL(index), rar_low); 7021 wrfl(); 7022 wr32(E1000_RAH(index), rar_high); 7023 wrfl(); 7024} 7025 7026static int igb_set_vf_mac(struct igb_adapter *adapter, 7027 int vf, unsigned char *mac_addr) 7028{ 7029 struct e1000_hw *hw = &adapter->hw; 7030 /* VF MAC addresses start at end of receive addresses and moves 7031 * torwards the first, as a result a collision should not be possible */ 7032 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7033 7034 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7035 7036 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7037 7038 return 0; 7039} 7040 7041static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7042{ 7043 struct igb_adapter *adapter = netdev_priv(netdev); 7044 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7045 return -EINVAL; 7046 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7047 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7048 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this" 7049 " change effective."); 7050 if (test_bit(__IGB_DOWN, &adapter->state)) { 7051 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set," 7052 " but the PF device is not up.\n"); 7053 dev_warn(&adapter->pdev->dev, "Bring the PF device up before" 7054 " attempting to use the VF device.\n"); 7055 } 7056 return igb_set_vf_mac(adapter, vf, mac); 7057} 7058 7059static int igb_link_mbps(int internal_link_speed) 7060{ 7061 switch (internal_link_speed) { 7062 case SPEED_100: 7063 return 100; 7064 case SPEED_1000: 7065 return 1000; 7066 default: 7067 return 0; 7068 } 7069} 7070 7071static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7072 int link_speed) 7073{ 7074 int rf_dec, rf_int; 7075 u32 bcnrc_val; 7076 7077 if (tx_rate != 0) { 7078 /* Calculate the rate factor values to set */ 7079 rf_int = link_speed / tx_rate; 7080 rf_dec = (link_speed - (rf_int * tx_rate)); 7081 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate; 7082 7083 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7084 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) & 7085 E1000_RTTBCNRC_RF_INT_MASK); 7086 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7087 } else { 7088 bcnrc_val = 0; 7089 } 7090 7091 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7092 /* 7093 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7094 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7095 */ 7096 wr32(E1000_RTTBCNRM, 0x14); 7097 wr32(E1000_RTTBCNRC, bcnrc_val); 7098} 7099 7100static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7101{ 7102 int actual_link_speed, i; 7103 bool reset_rate = false; 7104 7105 /* VF TX rate limit was not set or not supported */ 7106 if ((adapter->vf_rate_link_speed == 0) || 7107 (adapter->hw.mac.type != e1000_82576)) 7108 return; 7109 7110 actual_link_speed = igb_link_mbps(adapter->link_speed); 7111 if (actual_link_speed != adapter->vf_rate_link_speed) { 7112 reset_rate = true; 7113 adapter->vf_rate_link_speed = 0; 7114 dev_info(&adapter->pdev->dev, 7115 "Link speed has been changed. VF Transmit " 7116 "rate is disabled\n"); 7117 } 7118 7119 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7120 if (reset_rate) 7121 adapter->vf_data[i].tx_rate = 0; 7122 7123 igb_set_vf_rate_limit(&adapter->hw, i, 7124 adapter->vf_data[i].tx_rate, 7125 actual_link_speed); 7126 } 7127} 7128 7129static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) 7130{ 7131 struct igb_adapter *adapter = netdev_priv(netdev); 7132 struct e1000_hw *hw = &adapter->hw; 7133 int actual_link_speed; 7134 7135 if (hw->mac.type != e1000_82576) 7136 return -EOPNOTSUPP; 7137 7138 actual_link_speed = igb_link_mbps(adapter->link_speed); 7139 if ((vf >= adapter->vfs_allocated_count) || 7140 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7141 (tx_rate < 0) || (tx_rate > actual_link_speed)) 7142 return -EINVAL; 7143 7144 adapter->vf_rate_link_speed = actual_link_speed; 7145 adapter->vf_data[vf].tx_rate = (u16)tx_rate; 7146 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); 7147 7148 return 0; 7149} 7150 7151static int igb_ndo_get_vf_config(struct net_device *netdev, 7152 int vf, struct ifla_vf_info *ivi) 7153{ 7154 struct igb_adapter *adapter = netdev_priv(netdev); 7155 if (vf >= adapter->vfs_allocated_count) 7156 return -EINVAL; 7157 ivi->vf = vf; 7158 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7159 ivi->tx_rate = adapter->vf_data[vf].tx_rate; 7160 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7161 ivi->qos = adapter->vf_data[vf].pf_qos; 7162 return 0; 7163} 7164 7165static void igb_vmm_control(struct igb_adapter *adapter) 7166{ 7167 struct e1000_hw *hw = &adapter->hw; 7168 u32 reg; 7169 7170 switch (hw->mac.type) { 7171 case e1000_82575: 7172 case e1000_i210: 7173 case e1000_i211: 7174 default: 7175 /* replication is not supported for 82575 */ 7176 return; 7177 case e1000_82576: 7178 /* notify HW that the MAC is adding vlan tags */ 7179 reg = rd32(E1000_DTXCTL); 7180 reg |= E1000_DTXCTL_VLAN_ADDED; 7181 wr32(E1000_DTXCTL, reg); 7182 case e1000_82580: 7183 /* enable replication vlan tag stripping */ 7184 reg = rd32(E1000_RPLOLR); 7185 reg |= E1000_RPLOLR_STRVLAN; 7186 wr32(E1000_RPLOLR, reg); 7187 case e1000_i350: 7188 /* none of the above registers are supported by i350 */ 7189 break; 7190 } 7191 7192 if (adapter->vfs_allocated_count) { 7193 igb_vmdq_set_loopback_pf(hw, true); 7194 igb_vmdq_set_replication_pf(hw, true); 7195 igb_vmdq_set_anti_spoofing_pf(hw, true, 7196 adapter->vfs_allocated_count); 7197 } else { 7198 igb_vmdq_set_loopback_pf(hw, false); 7199 igb_vmdq_set_replication_pf(hw, false); 7200 } 7201} 7202 7203static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7204{ 7205 struct e1000_hw *hw = &adapter->hw; 7206 u32 dmac_thr; 7207 u16 hwm; 7208 7209 if (hw->mac.type > e1000_82580) { 7210 if (adapter->flags & IGB_FLAG_DMAC) { 7211 u32 reg; 7212 7213 /* force threshold to 0. */ 7214 wr32(E1000_DMCTXTH, 0); 7215 7216 /* 7217 * DMA Coalescing high water mark needs to be greater 7218 * than the Rx threshold. Set hwm to PBA - max frame 7219 * size in 16B units, capping it at PBA - 6KB. 7220 */ 7221 hwm = 64 * pba - adapter->max_frame_size / 16; 7222 if (hwm < 64 * (pba - 6)) 7223 hwm = 64 * (pba - 6); 7224 reg = rd32(E1000_FCRTC); 7225 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 7226 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 7227 & E1000_FCRTC_RTH_COAL_MASK); 7228 wr32(E1000_FCRTC, reg); 7229 7230 /* 7231 * Set the DMA Coalescing Rx threshold to PBA - 2 * max 7232 * frame size, capping it at PBA - 10KB. 7233 */ 7234 dmac_thr = pba - adapter->max_frame_size / 512; 7235 if (dmac_thr < pba - 10) 7236 dmac_thr = pba - 10; 7237 reg = rd32(E1000_DMACR); 7238 reg &= ~E1000_DMACR_DMACTHR_MASK; 7239 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 7240 & E1000_DMACR_DMACTHR_MASK); 7241 7242 /* transition to L0x or L1 if available..*/ 7243 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 7244 7245 /* watchdog timer= +-1000 usec in 32usec intervals */ 7246 reg |= (1000 >> 5); 7247 7248 /* Disable BMC-to-OS Watchdog Enable */ 7249 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 7250 wr32(E1000_DMACR, reg); 7251 7252 /* 7253 * no lower threshold to disable 7254 * coalescing(smart fifb)-UTRESH=0 7255 */ 7256 wr32(E1000_DMCRTRH, 0); 7257 7258 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 7259 7260 wr32(E1000_DMCTLX, reg); 7261 7262 /* 7263 * free space in tx packet buffer to wake from 7264 * DMA coal 7265 */ 7266 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 7267 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 7268 7269 /* 7270 * make low power state decision controlled 7271 * by DMA coal 7272 */ 7273 reg = rd32(E1000_PCIEMISC); 7274 reg &= ~E1000_PCIEMISC_LX_DECISION; 7275 wr32(E1000_PCIEMISC, reg); 7276 } /* endif adapter->dmac is not disabled */ 7277 } else if (hw->mac.type == e1000_82580) { 7278 u32 reg = rd32(E1000_PCIEMISC); 7279 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 7280 wr32(E1000_DMACR, 0); 7281 } 7282} 7283 7284/* igb_main.c */ 7285