igb_main.c revision 0b1a6f2ee85d77d02e73ea8be43e1a9d8d97ccee
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30#include <linux/module.h> 31#include <linux/types.h> 32#include <linux/init.h> 33#include <linux/bitops.h> 34#include <linux/vmalloc.h> 35#include <linux/pagemap.h> 36#include <linux/netdevice.h> 37#include <linux/ipv6.h> 38#include <linux/slab.h> 39#include <net/checksum.h> 40#include <net/ip6_checksum.h> 41#include <linux/net_tstamp.h> 42#include <linux/mii.h> 43#include <linux/ethtool.h> 44#include <linux/if.h> 45#include <linux/if_vlan.h> 46#include <linux/pci.h> 47#include <linux/pci-aspm.h> 48#include <linux/delay.h> 49#include <linux/interrupt.h> 50#include <linux/ip.h> 51#include <linux/tcp.h> 52#include <linux/sctp.h> 53#include <linux/if_ether.h> 54#include <linux/aer.h> 55#include <linux/prefetch.h> 56#include <linux/pm_runtime.h> 57#ifdef CONFIG_IGB_DCA 58#include <linux/dca.h> 59#endif 60#include "igb.h" 61 62#define MAJ 4 63#define MIN 0 64#define BUILD 17 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 66__stringify(BUILD) "-k" 67char igb_driver_name[] = "igb"; 68char igb_driver_version[] = DRV_VERSION; 69static const char igb_driver_string[] = 70 "Intel(R) Gigabit Ethernet Network Driver"; 71static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation."; 72 73static const struct e1000_info *igb_info_tbl[] = { 74 [board_82575] = &e1000_82575_info, 75}; 76 77static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 108 /* required last entry */ 109 {0, } 110}; 111 112MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 113 114void igb_reset(struct igb_adapter *); 115static int igb_setup_all_tx_resources(struct igb_adapter *); 116static int igb_setup_all_rx_resources(struct igb_adapter *); 117static void igb_free_all_tx_resources(struct igb_adapter *); 118static void igb_free_all_rx_resources(struct igb_adapter *); 119static void igb_setup_mrqc(struct igb_adapter *); 120static int igb_probe(struct pci_dev *, const struct pci_device_id *); 121static void __devexit igb_remove(struct pci_dev *pdev); 122static int igb_sw_init(struct igb_adapter *); 123static int igb_open(struct net_device *); 124static int igb_close(struct net_device *); 125static void igb_configure_tx(struct igb_adapter *); 126static void igb_configure_rx(struct igb_adapter *); 127static void igb_clean_all_tx_rings(struct igb_adapter *); 128static void igb_clean_all_rx_rings(struct igb_adapter *); 129static void igb_clean_tx_ring(struct igb_ring *); 130static void igb_clean_rx_ring(struct igb_ring *); 131static void igb_set_rx_mode(struct net_device *); 132static void igb_update_phy_info(unsigned long); 133static void igb_watchdog(unsigned long); 134static void igb_watchdog_task(struct work_struct *); 135static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 136static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 137 struct rtnl_link_stats64 *stats); 138static int igb_change_mtu(struct net_device *, int); 139static int igb_set_mac(struct net_device *, void *); 140static void igb_set_uta(struct igb_adapter *adapter); 141static irqreturn_t igb_intr(int irq, void *); 142static irqreturn_t igb_intr_msi(int irq, void *); 143static irqreturn_t igb_msix_other(int irq, void *); 144static irqreturn_t igb_msix_ring(int irq, void *); 145#ifdef CONFIG_IGB_DCA 146static void igb_update_dca(struct igb_q_vector *); 147static void igb_setup_dca(struct igb_adapter *); 148#endif /* CONFIG_IGB_DCA */ 149static int igb_poll(struct napi_struct *, int); 150static bool igb_clean_tx_irq(struct igb_q_vector *); 151static bool igb_clean_rx_irq(struct igb_q_vector *, int); 152static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 153static void igb_tx_timeout(struct net_device *); 154static void igb_reset_task(struct work_struct *); 155static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); 156static int igb_vlan_rx_add_vid(struct net_device *, u16); 157static int igb_vlan_rx_kill_vid(struct net_device *, u16); 158static void igb_restore_vlan(struct igb_adapter *); 159static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 160static void igb_ping_all_vfs(struct igb_adapter *); 161static void igb_msg_task(struct igb_adapter *); 162static void igb_vmm_control(struct igb_adapter *); 163static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 164static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 165static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 166static int igb_ndo_set_vf_vlan(struct net_device *netdev, 167 int vf, u16 vlan, u8 qos); 168static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 169static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 170 struct ifla_vf_info *ivi); 171static void igb_check_vf_rate_limit(struct igb_adapter *); 172 173#ifdef CONFIG_PCI_IOV 174static int igb_vf_configure(struct igb_adapter *adapter, int vf); 175static bool igb_vfs_are_assigned(struct igb_adapter *adapter); 176#endif 177 178#ifdef CONFIG_PM 179#ifdef CONFIG_PM_SLEEP 180static int igb_suspend(struct device *); 181#endif 182static int igb_resume(struct device *); 183#ifdef CONFIG_PM_RUNTIME 184static int igb_runtime_suspend(struct device *dev); 185static int igb_runtime_resume(struct device *dev); 186static int igb_runtime_idle(struct device *dev); 187#endif 188static const struct dev_pm_ops igb_pm_ops = { 189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 191 igb_runtime_idle) 192}; 193#endif 194static void igb_shutdown(struct pci_dev *); 195#ifdef CONFIG_IGB_DCA 196static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 197static struct notifier_block dca_notifier = { 198 .notifier_call = igb_notify_dca, 199 .next = NULL, 200 .priority = 0 201}; 202#endif 203#ifdef CONFIG_NET_POLL_CONTROLLER 204/* for netdump / net console */ 205static void igb_netpoll(struct net_device *); 206#endif 207#ifdef CONFIG_PCI_IOV 208static unsigned int max_vfs = 0; 209module_param(max_vfs, uint, 0); 210MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " 211 "per physical function"); 212#endif /* CONFIG_PCI_IOV */ 213 214static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 215 pci_channel_state_t); 216static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 217static void igb_io_resume(struct pci_dev *); 218 219static const struct pci_error_handlers igb_err_handler = { 220 .error_detected = igb_io_error_detected, 221 .slot_reset = igb_io_slot_reset, 222 .resume = igb_io_resume, 223}; 224 225static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 226 227static struct pci_driver igb_driver = { 228 .name = igb_driver_name, 229 .id_table = igb_pci_tbl, 230 .probe = igb_probe, 231 .remove = __devexit_p(igb_remove), 232#ifdef CONFIG_PM 233 .driver.pm = &igb_pm_ops, 234#endif 235 .shutdown = igb_shutdown, 236 .err_handler = &igb_err_handler 237}; 238 239MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 240MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 241MODULE_LICENSE("GPL"); 242MODULE_VERSION(DRV_VERSION); 243 244#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 245static int debug = -1; 246module_param(debug, int, 0); 247MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 248 249struct igb_reg_info { 250 u32 ofs; 251 char *name; 252}; 253 254static const struct igb_reg_info igb_reg_info_tbl[] = { 255 256 /* General Registers */ 257 {E1000_CTRL, "CTRL"}, 258 {E1000_STATUS, "STATUS"}, 259 {E1000_CTRL_EXT, "CTRL_EXT"}, 260 261 /* Interrupt Registers */ 262 {E1000_ICR, "ICR"}, 263 264 /* RX Registers */ 265 {E1000_RCTL, "RCTL"}, 266 {E1000_RDLEN(0), "RDLEN"}, 267 {E1000_RDH(0), "RDH"}, 268 {E1000_RDT(0), "RDT"}, 269 {E1000_RXDCTL(0), "RXDCTL"}, 270 {E1000_RDBAL(0), "RDBAL"}, 271 {E1000_RDBAH(0), "RDBAH"}, 272 273 /* TX Registers */ 274 {E1000_TCTL, "TCTL"}, 275 {E1000_TDBAL(0), "TDBAL"}, 276 {E1000_TDBAH(0), "TDBAH"}, 277 {E1000_TDLEN(0), "TDLEN"}, 278 {E1000_TDH(0), "TDH"}, 279 {E1000_TDT(0), "TDT"}, 280 {E1000_TXDCTL(0), "TXDCTL"}, 281 {E1000_TDFH, "TDFH"}, 282 {E1000_TDFT, "TDFT"}, 283 {E1000_TDFHS, "TDFHS"}, 284 {E1000_TDFPC, "TDFPC"}, 285 286 /* List Terminator */ 287 {} 288}; 289 290/* 291 * igb_regdump - register printout routine 292 */ 293static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 294{ 295 int n = 0; 296 char rname[16]; 297 u32 regs[8]; 298 299 switch (reginfo->ofs) { 300 case E1000_RDLEN(0): 301 for (n = 0; n < 4; n++) 302 regs[n] = rd32(E1000_RDLEN(n)); 303 break; 304 case E1000_RDH(0): 305 for (n = 0; n < 4; n++) 306 regs[n] = rd32(E1000_RDH(n)); 307 break; 308 case E1000_RDT(0): 309 for (n = 0; n < 4; n++) 310 regs[n] = rd32(E1000_RDT(n)); 311 break; 312 case E1000_RXDCTL(0): 313 for (n = 0; n < 4; n++) 314 regs[n] = rd32(E1000_RXDCTL(n)); 315 break; 316 case E1000_RDBAL(0): 317 for (n = 0; n < 4; n++) 318 regs[n] = rd32(E1000_RDBAL(n)); 319 break; 320 case E1000_RDBAH(0): 321 for (n = 0; n < 4; n++) 322 regs[n] = rd32(E1000_RDBAH(n)); 323 break; 324 case E1000_TDBAL(0): 325 for (n = 0; n < 4; n++) 326 regs[n] = rd32(E1000_RDBAL(n)); 327 break; 328 case E1000_TDBAH(0): 329 for (n = 0; n < 4; n++) 330 regs[n] = rd32(E1000_TDBAH(n)); 331 break; 332 case E1000_TDLEN(0): 333 for (n = 0; n < 4; n++) 334 regs[n] = rd32(E1000_TDLEN(n)); 335 break; 336 case E1000_TDH(0): 337 for (n = 0; n < 4; n++) 338 regs[n] = rd32(E1000_TDH(n)); 339 break; 340 case E1000_TDT(0): 341 for (n = 0; n < 4; n++) 342 regs[n] = rd32(E1000_TDT(n)); 343 break; 344 case E1000_TXDCTL(0): 345 for (n = 0; n < 4; n++) 346 regs[n] = rd32(E1000_TXDCTL(n)); 347 break; 348 default: 349 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 350 return; 351 } 352 353 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 354 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 355 regs[2], regs[3]); 356} 357 358/* 359 * igb_dump - Print registers, tx-rings and rx-rings 360 */ 361static void igb_dump(struct igb_adapter *adapter) 362{ 363 struct net_device *netdev = adapter->netdev; 364 struct e1000_hw *hw = &adapter->hw; 365 struct igb_reg_info *reginfo; 366 struct igb_ring *tx_ring; 367 union e1000_adv_tx_desc *tx_desc; 368 struct my_u0 { u64 a; u64 b; } *u0; 369 struct igb_ring *rx_ring; 370 union e1000_adv_rx_desc *rx_desc; 371 u32 staterr; 372 u16 i, n; 373 374 if (!netif_msg_hw(adapter)) 375 return; 376 377 /* Print netdevice Info */ 378 if (netdev) { 379 dev_info(&adapter->pdev->dev, "Net device Info\n"); 380 pr_info("Device Name state trans_start " 381 "last_rx\n"); 382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 383 netdev->state, netdev->trans_start, netdev->last_rx); 384 } 385 386 /* Print Registers */ 387 dev_info(&adapter->pdev->dev, "Register Dump\n"); 388 pr_info(" Register Name Value\n"); 389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 390 reginfo->name; reginfo++) { 391 igb_regdump(hw, reginfo); 392 } 393 394 /* Print TX Ring Summary */ 395 if (!netdev || !netif_running(netdev)) 396 goto exit; 397 398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 400 for (n = 0; n < adapter->num_tx_queues; n++) { 401 struct igb_tx_buffer *buffer_info; 402 tx_ring = adapter->tx_ring[n]; 403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 405 n, tx_ring->next_to_use, tx_ring->next_to_clean, 406 (u64)dma_unmap_addr(buffer_info, dma), 407 dma_unmap_len(buffer_info, len), 408 buffer_info->next_to_watch, 409 (u64)buffer_info->time_stamp); 410 } 411 412 /* Print TX Rings */ 413 if (!netif_msg_tx_done(adapter)) 414 goto rx_ring_summary; 415 416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 417 418 /* Transmit Descriptor Formats 419 * 420 * Advanced Transmit Descriptor 421 * +--------------------------------------------------------------+ 422 * 0 | Buffer Address [63:0] | 423 * +--------------------------------------------------------------+ 424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 425 * +--------------------------------------------------------------+ 426 * 63 46 45 40 39 38 36 35 32 31 24 15 0 427 */ 428 429 for (n = 0; n < adapter->num_tx_queues; n++) { 430 tx_ring = adapter->tx_ring[n]; 431 pr_info("------------------------------------\n"); 432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 433 pr_info("------------------------------------\n"); 434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] " 435 "[bi->dma ] leng ntw timestamp " 436 "bi->skb\n"); 437 438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 439 const char *next_desc; 440 struct igb_tx_buffer *buffer_info; 441 tx_desc = IGB_TX_DESC(tx_ring, i); 442 buffer_info = &tx_ring->tx_buffer_info[i]; 443 u0 = (struct my_u0 *)tx_desc; 444 if (i == tx_ring->next_to_use && 445 i == tx_ring->next_to_clean) 446 next_desc = " NTC/U"; 447 else if (i == tx_ring->next_to_use) 448 next_desc = " NTU"; 449 else if (i == tx_ring->next_to_clean) 450 next_desc = " NTC"; 451 else 452 next_desc = ""; 453 454 pr_info("T [0x%03X] %016llX %016llX %016llX" 455 " %04X %p %016llX %p%s\n", i, 456 le64_to_cpu(u0->a), 457 le64_to_cpu(u0->b), 458 (u64)dma_unmap_addr(buffer_info, dma), 459 dma_unmap_len(buffer_info, len), 460 buffer_info->next_to_watch, 461 (u64)buffer_info->time_stamp, 462 buffer_info->skb, next_desc); 463 464 if (netif_msg_pktdata(adapter) && buffer_info->skb) 465 print_hex_dump(KERN_INFO, "", 466 DUMP_PREFIX_ADDRESS, 467 16, 1, buffer_info->skb->data, 468 dma_unmap_len(buffer_info, len), 469 true); 470 } 471 } 472 473 /* Print RX Rings Summary */ 474rx_ring_summary: 475 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 476 pr_info("Queue [NTU] [NTC]\n"); 477 for (n = 0; n < adapter->num_rx_queues; n++) { 478 rx_ring = adapter->rx_ring[n]; 479 pr_info(" %5d %5X %5X\n", 480 n, rx_ring->next_to_use, rx_ring->next_to_clean); 481 } 482 483 /* Print RX Rings */ 484 if (!netif_msg_rx_status(adapter)) 485 goto exit; 486 487 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 488 489 /* Advanced Receive Descriptor (Read) Format 490 * 63 1 0 491 * +-----------------------------------------------------+ 492 * 0 | Packet Buffer Address [63:1] |A0/NSE| 493 * +----------------------------------------------+------+ 494 * 8 | Header Buffer Address [63:1] | DD | 495 * +-----------------------------------------------------+ 496 * 497 * 498 * Advanced Receive Descriptor (Write-Back) Format 499 * 500 * 63 48 47 32 31 30 21 20 17 16 4 3 0 501 * +------------------------------------------------------+ 502 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 503 * | Checksum Ident | | | | Type | Type | 504 * +------------------------------------------------------+ 505 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 506 * +------------------------------------------------------+ 507 * 63 48 47 32 31 20 19 0 508 */ 509 510 for (n = 0; n < adapter->num_rx_queues; n++) { 511 rx_ring = adapter->rx_ring[n]; 512 pr_info("------------------------------------\n"); 513 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 514 pr_info("------------------------------------\n"); 515 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] " 516 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 517 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----" 518 "----------- [bi->skb] <-- Adv Rx Write-Back format\n"); 519 520 for (i = 0; i < rx_ring->count; i++) { 521 const char *next_desc; 522 struct igb_rx_buffer *buffer_info; 523 buffer_info = &rx_ring->rx_buffer_info[i]; 524 rx_desc = IGB_RX_DESC(rx_ring, i); 525 u0 = (struct my_u0 *)rx_desc; 526 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 527 528 if (i == rx_ring->next_to_use) 529 next_desc = " NTU"; 530 else if (i == rx_ring->next_to_clean) 531 next_desc = " NTC"; 532 else 533 next_desc = ""; 534 535 if (staterr & E1000_RXD_STAT_DD) { 536 /* Descriptor Done */ 537 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 538 "RWB", i, 539 le64_to_cpu(u0->a), 540 le64_to_cpu(u0->b), 541 next_desc); 542 } else { 543 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 544 "R ", i, 545 le64_to_cpu(u0->a), 546 le64_to_cpu(u0->b), 547 (u64)buffer_info->dma, 548 next_desc); 549 550 if (netif_msg_pktdata(adapter) && 551 buffer_info->dma && buffer_info->page) { 552 print_hex_dump(KERN_INFO, "", 553 DUMP_PREFIX_ADDRESS, 554 16, 1, 555 page_address(buffer_info->page) + 556 buffer_info->page_offset, 557 IGB_RX_BUFSZ, true); 558 } 559 } 560 } 561 } 562 563exit: 564 return; 565} 566 567/** 568 * igb_get_hw_dev - return device 569 * used by hardware layer to print debugging information 570 **/ 571struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 572{ 573 struct igb_adapter *adapter = hw->back; 574 return adapter->netdev; 575} 576 577/** 578 * igb_init_module - Driver Registration Routine 579 * 580 * igb_init_module is the first routine called when the driver is 581 * loaded. All it does is register with the PCI subsystem. 582 **/ 583static int __init igb_init_module(void) 584{ 585 int ret; 586 pr_info("%s - version %s\n", 587 igb_driver_string, igb_driver_version); 588 589 pr_info("%s\n", igb_copyright); 590 591#ifdef CONFIG_IGB_DCA 592 dca_register_notify(&dca_notifier); 593#endif 594 ret = pci_register_driver(&igb_driver); 595 return ret; 596} 597 598module_init(igb_init_module); 599 600/** 601 * igb_exit_module - Driver Exit Cleanup Routine 602 * 603 * igb_exit_module is called just before the driver is removed 604 * from memory. 605 **/ 606static void __exit igb_exit_module(void) 607{ 608#ifdef CONFIG_IGB_DCA 609 dca_unregister_notify(&dca_notifier); 610#endif 611 pci_unregister_driver(&igb_driver); 612} 613 614module_exit(igb_exit_module); 615 616#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 617/** 618 * igb_cache_ring_register - Descriptor ring to register mapping 619 * @adapter: board private structure to initialize 620 * 621 * Once we know the feature-set enabled for the device, we'll cache 622 * the register offset the descriptor ring is assigned to. 623 **/ 624static void igb_cache_ring_register(struct igb_adapter *adapter) 625{ 626 int i = 0, j = 0; 627 u32 rbase_offset = adapter->vfs_allocated_count; 628 629 switch (adapter->hw.mac.type) { 630 case e1000_82576: 631 /* The queues are allocated for virtualization such that VF 0 632 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 633 * In order to avoid collision we start at the first free queue 634 * and continue consuming queues in the same sequence 635 */ 636 if (adapter->vfs_allocated_count) { 637 for (; i < adapter->rss_queues; i++) 638 adapter->rx_ring[i]->reg_idx = rbase_offset + 639 Q_IDX_82576(i); 640 } 641 case e1000_82575: 642 case e1000_82580: 643 case e1000_i350: 644 case e1000_i210: 645 case e1000_i211: 646 default: 647 for (; i < adapter->num_rx_queues; i++) 648 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 649 for (; j < adapter->num_tx_queues; j++) 650 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 651 break; 652 } 653} 654 655/** 656 * igb_write_ivar - configure ivar for given MSI-X vector 657 * @hw: pointer to the HW structure 658 * @msix_vector: vector number we are allocating to a given ring 659 * @index: row index of IVAR register to write within IVAR table 660 * @offset: column offset of in IVAR, should be multiple of 8 661 * 662 * This function is intended to handle the writing of the IVAR register 663 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 664 * each containing an cause allocation for an Rx and Tx ring, and a 665 * variable number of rows depending on the number of queues supported. 666 **/ 667static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 668 int index, int offset) 669{ 670 u32 ivar = array_rd32(E1000_IVAR0, index); 671 672 /* clear any bits that are currently set */ 673 ivar &= ~((u32)0xFF << offset); 674 675 /* write vector and valid bit */ 676 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 677 678 array_wr32(E1000_IVAR0, index, ivar); 679} 680 681#define IGB_N0_QUEUE -1 682static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 683{ 684 struct igb_adapter *adapter = q_vector->adapter; 685 struct e1000_hw *hw = &adapter->hw; 686 int rx_queue = IGB_N0_QUEUE; 687 int tx_queue = IGB_N0_QUEUE; 688 u32 msixbm = 0; 689 690 if (q_vector->rx.ring) 691 rx_queue = q_vector->rx.ring->reg_idx; 692 if (q_vector->tx.ring) 693 tx_queue = q_vector->tx.ring->reg_idx; 694 695 switch (hw->mac.type) { 696 case e1000_82575: 697 /* The 82575 assigns vectors using a bitmask, which matches the 698 bitmask for the EICR/EIMS/EIMC registers. To assign one 699 or more queues to a vector, we write the appropriate bits 700 into the MSIXBM register for that vector. */ 701 if (rx_queue > IGB_N0_QUEUE) 702 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 703 if (tx_queue > IGB_N0_QUEUE) 704 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 705 if (!adapter->msix_entries && msix_vector == 0) 706 msixbm |= E1000_EIMS_OTHER; 707 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 708 q_vector->eims_value = msixbm; 709 break; 710 case e1000_82576: 711 /* 712 * 82576 uses a table that essentially consists of 2 columns 713 * with 8 rows. The ordering is column-major so we use the 714 * lower 3 bits as the row index, and the 4th bit as the 715 * column offset. 716 */ 717 if (rx_queue > IGB_N0_QUEUE) 718 igb_write_ivar(hw, msix_vector, 719 rx_queue & 0x7, 720 (rx_queue & 0x8) << 1); 721 if (tx_queue > IGB_N0_QUEUE) 722 igb_write_ivar(hw, msix_vector, 723 tx_queue & 0x7, 724 ((tx_queue & 0x8) << 1) + 8); 725 q_vector->eims_value = 1 << msix_vector; 726 break; 727 case e1000_82580: 728 case e1000_i350: 729 case e1000_i210: 730 case e1000_i211: 731 /* 732 * On 82580 and newer adapters the scheme is similar to 82576 733 * however instead of ordering column-major we have things 734 * ordered row-major. So we traverse the table by using 735 * bit 0 as the column offset, and the remaining bits as the 736 * row index. 737 */ 738 if (rx_queue > IGB_N0_QUEUE) 739 igb_write_ivar(hw, msix_vector, 740 rx_queue >> 1, 741 (rx_queue & 0x1) << 4); 742 if (tx_queue > IGB_N0_QUEUE) 743 igb_write_ivar(hw, msix_vector, 744 tx_queue >> 1, 745 ((tx_queue & 0x1) << 4) + 8); 746 q_vector->eims_value = 1 << msix_vector; 747 break; 748 default: 749 BUG(); 750 break; 751 } 752 753 /* add q_vector eims value to global eims_enable_mask */ 754 adapter->eims_enable_mask |= q_vector->eims_value; 755 756 /* configure q_vector to set itr on first interrupt */ 757 q_vector->set_itr = 1; 758} 759 760/** 761 * igb_configure_msix - Configure MSI-X hardware 762 * 763 * igb_configure_msix sets up the hardware to properly 764 * generate MSI-X interrupts. 765 **/ 766static void igb_configure_msix(struct igb_adapter *adapter) 767{ 768 u32 tmp; 769 int i, vector = 0; 770 struct e1000_hw *hw = &adapter->hw; 771 772 adapter->eims_enable_mask = 0; 773 774 /* set vector for other causes, i.e. link changes */ 775 switch (hw->mac.type) { 776 case e1000_82575: 777 tmp = rd32(E1000_CTRL_EXT); 778 /* enable MSI-X PBA support*/ 779 tmp |= E1000_CTRL_EXT_PBA_CLR; 780 781 /* Auto-Mask interrupts upon ICR read. */ 782 tmp |= E1000_CTRL_EXT_EIAME; 783 tmp |= E1000_CTRL_EXT_IRCA; 784 785 wr32(E1000_CTRL_EXT, tmp); 786 787 /* enable msix_other interrupt */ 788 array_wr32(E1000_MSIXBM(0), vector++, 789 E1000_EIMS_OTHER); 790 adapter->eims_other = E1000_EIMS_OTHER; 791 792 break; 793 794 case e1000_82576: 795 case e1000_82580: 796 case e1000_i350: 797 case e1000_i210: 798 case e1000_i211: 799 /* Turn on MSI-X capability first, or our settings 800 * won't stick. And it will take days to debug. */ 801 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 802 E1000_GPIE_PBA | E1000_GPIE_EIAME | 803 E1000_GPIE_NSICR); 804 805 /* enable msix_other interrupt */ 806 adapter->eims_other = 1 << vector; 807 tmp = (vector++ | E1000_IVAR_VALID) << 8; 808 809 wr32(E1000_IVAR_MISC, tmp); 810 break; 811 default: 812 /* do nothing, since nothing else supports MSI-X */ 813 break; 814 } /* switch (hw->mac.type) */ 815 816 adapter->eims_enable_mask |= adapter->eims_other; 817 818 for (i = 0; i < adapter->num_q_vectors; i++) 819 igb_assign_vector(adapter->q_vector[i], vector++); 820 821 wrfl(); 822} 823 824/** 825 * igb_request_msix - Initialize MSI-X interrupts 826 * 827 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 828 * kernel. 829 **/ 830static int igb_request_msix(struct igb_adapter *adapter) 831{ 832 struct net_device *netdev = adapter->netdev; 833 struct e1000_hw *hw = &adapter->hw; 834 int i, err = 0, vector = 0; 835 836 err = request_irq(adapter->msix_entries[vector].vector, 837 igb_msix_other, 0, netdev->name, adapter); 838 if (err) 839 goto out; 840 vector++; 841 842 for (i = 0; i < adapter->num_q_vectors; i++) { 843 struct igb_q_vector *q_vector = adapter->q_vector[i]; 844 845 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 846 847 if (q_vector->rx.ring && q_vector->tx.ring) 848 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 849 q_vector->rx.ring->queue_index); 850 else if (q_vector->tx.ring) 851 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 852 q_vector->tx.ring->queue_index); 853 else if (q_vector->rx.ring) 854 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 855 q_vector->rx.ring->queue_index); 856 else 857 sprintf(q_vector->name, "%s-unused", netdev->name); 858 859 err = request_irq(adapter->msix_entries[vector].vector, 860 igb_msix_ring, 0, q_vector->name, 861 q_vector); 862 if (err) 863 goto out; 864 vector++; 865 } 866 867 igb_configure_msix(adapter); 868 return 0; 869out: 870 return err; 871} 872 873static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 874{ 875 if (adapter->msix_entries) { 876 pci_disable_msix(adapter->pdev); 877 kfree(adapter->msix_entries); 878 adapter->msix_entries = NULL; 879 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 880 pci_disable_msi(adapter->pdev); 881 } 882} 883 884/** 885 * igb_free_q_vector - Free memory allocated for specific interrupt vector 886 * @adapter: board private structure to initialize 887 * @v_idx: Index of vector to be freed 888 * 889 * This function frees the memory allocated to the q_vector. In addition if 890 * NAPI is enabled it will delete any references to the NAPI struct prior 891 * to freeing the q_vector. 892 **/ 893static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 894{ 895 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 896 897 if (q_vector->tx.ring) 898 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 899 900 if (q_vector->rx.ring) 901 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; 902 903 adapter->q_vector[v_idx] = NULL; 904 netif_napi_del(&q_vector->napi); 905 906 /* 907 * ixgbe_get_stats64() might access the rings on this vector, 908 * we must wait a grace period before freeing it. 909 */ 910 kfree_rcu(q_vector, rcu); 911} 912 913/** 914 * igb_free_q_vectors - Free memory allocated for interrupt vectors 915 * @adapter: board private structure to initialize 916 * 917 * This function frees the memory allocated to the q_vectors. In addition if 918 * NAPI is enabled it will delete any references to the NAPI struct prior 919 * to freeing the q_vector. 920 **/ 921static void igb_free_q_vectors(struct igb_adapter *adapter) 922{ 923 int v_idx = adapter->num_q_vectors; 924 925 adapter->num_tx_queues = 0; 926 adapter->num_rx_queues = 0; 927 adapter->num_q_vectors = 0; 928 929 while (v_idx--) 930 igb_free_q_vector(adapter, v_idx); 931} 932 933/** 934 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 935 * 936 * This function resets the device so that it has 0 rx queues, tx queues, and 937 * MSI-X interrupts allocated. 938 */ 939static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 940{ 941 igb_free_q_vectors(adapter); 942 igb_reset_interrupt_capability(adapter); 943} 944 945/** 946 * igb_set_interrupt_capability - set MSI or MSI-X if supported 947 * 948 * Attempt to configure interrupts using the best available 949 * capabilities of the hardware and kernel. 950 **/ 951static void igb_set_interrupt_capability(struct igb_adapter *adapter) 952{ 953 int err; 954 int numvecs, i; 955 956 /* Number of supported queues. */ 957 adapter->num_rx_queues = adapter->rss_queues; 958 if (adapter->vfs_allocated_count) 959 adapter->num_tx_queues = 1; 960 else 961 adapter->num_tx_queues = adapter->rss_queues; 962 963 /* start with one vector for every rx queue */ 964 numvecs = adapter->num_rx_queues; 965 966 /* if tx handler is separate add 1 for every tx queue */ 967 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 968 numvecs += adapter->num_tx_queues; 969 970 /* store the number of vectors reserved for queues */ 971 adapter->num_q_vectors = numvecs; 972 973 /* add 1 vector for link status interrupts */ 974 numvecs++; 975 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), 976 GFP_KERNEL); 977 978 if (!adapter->msix_entries) 979 goto msi_only; 980 981 for (i = 0; i < numvecs; i++) 982 adapter->msix_entries[i].entry = i; 983 984 err = pci_enable_msix(adapter->pdev, 985 adapter->msix_entries, 986 numvecs); 987 if (err == 0) 988 return; 989 990 igb_reset_interrupt_capability(adapter); 991 992 /* If we can't do MSI-X, try MSI */ 993msi_only: 994#ifdef CONFIG_PCI_IOV 995 /* disable SR-IOV for non MSI-X configurations */ 996 if (adapter->vf_data) { 997 struct e1000_hw *hw = &adapter->hw; 998 /* disable iov and allow time for transactions to clear */ 999 pci_disable_sriov(adapter->pdev); 1000 msleep(500); 1001 1002 kfree(adapter->vf_data); 1003 adapter->vf_data = NULL; 1004 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1005 wrfl(); 1006 msleep(100); 1007 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1008 } 1009#endif 1010 adapter->vfs_allocated_count = 0; 1011 adapter->rss_queues = 1; 1012 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1013 adapter->num_rx_queues = 1; 1014 adapter->num_tx_queues = 1; 1015 adapter->num_q_vectors = 1; 1016 if (!pci_enable_msi(adapter->pdev)) 1017 adapter->flags |= IGB_FLAG_HAS_MSI; 1018} 1019 1020static void igb_add_ring(struct igb_ring *ring, 1021 struct igb_ring_container *head) 1022{ 1023 head->ring = ring; 1024 head->count++; 1025} 1026 1027/** 1028 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1029 * @adapter: board private structure to initialize 1030 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1031 * @v_idx: index of vector in adapter struct 1032 * @txr_count: total number of Tx rings to allocate 1033 * @txr_idx: index of first Tx ring to allocate 1034 * @rxr_count: total number of Rx rings to allocate 1035 * @rxr_idx: index of first Rx ring to allocate 1036 * 1037 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1038 **/ 1039static int igb_alloc_q_vector(struct igb_adapter *adapter, 1040 int v_count, int v_idx, 1041 int txr_count, int txr_idx, 1042 int rxr_count, int rxr_idx) 1043{ 1044 struct igb_q_vector *q_vector; 1045 struct igb_ring *ring; 1046 int ring_count, size; 1047 1048 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1049 if (txr_count > 1 || rxr_count > 1) 1050 return -ENOMEM; 1051 1052 ring_count = txr_count + rxr_count; 1053 size = sizeof(struct igb_q_vector) + 1054 (sizeof(struct igb_ring) * ring_count); 1055 1056 /* allocate q_vector and rings */ 1057 q_vector = kzalloc(size, GFP_KERNEL); 1058 if (!q_vector) 1059 return -ENOMEM; 1060 1061 /* initialize NAPI */ 1062 netif_napi_add(adapter->netdev, &q_vector->napi, 1063 igb_poll, 64); 1064 1065 /* tie q_vector and adapter together */ 1066 adapter->q_vector[v_idx] = q_vector; 1067 q_vector->adapter = adapter; 1068 1069 /* initialize work limits */ 1070 q_vector->tx.work_limit = adapter->tx_work_limit; 1071 1072 /* initialize ITR configuration */ 1073 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); 1074 q_vector->itr_val = IGB_START_ITR; 1075 1076 /* initialize pointer to rings */ 1077 ring = q_vector->ring; 1078 1079 if (txr_count) { 1080 /* assign generic ring traits */ 1081 ring->dev = &adapter->pdev->dev; 1082 ring->netdev = adapter->netdev; 1083 1084 /* configure backlink on ring */ 1085 ring->q_vector = q_vector; 1086 1087 /* update q_vector Tx values */ 1088 igb_add_ring(ring, &q_vector->tx); 1089 1090 /* For 82575, context index must be unique per ring. */ 1091 if (adapter->hw.mac.type == e1000_82575) 1092 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1093 1094 /* apply Tx specific ring traits */ 1095 ring->count = adapter->tx_ring_count; 1096 ring->queue_index = txr_idx; 1097 1098 /* assign ring to adapter */ 1099 adapter->tx_ring[txr_idx] = ring; 1100 1101 /* push pointer to next ring */ 1102 ring++; 1103 } 1104 1105 if (rxr_count) { 1106 /* assign generic ring traits */ 1107 ring->dev = &adapter->pdev->dev; 1108 ring->netdev = adapter->netdev; 1109 1110 /* configure backlink on ring */ 1111 ring->q_vector = q_vector; 1112 1113 /* update q_vector Rx values */ 1114 igb_add_ring(ring, &q_vector->rx); 1115 1116 /* set flag indicating ring supports SCTP checksum offload */ 1117 if (adapter->hw.mac.type >= e1000_82576) 1118 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1119 1120 /* 1121 * On i350, i210, and i211, loopback VLAN packets 1122 * have the tag byte-swapped. 1123 * */ 1124 if (adapter->hw.mac.type >= e1000_i350) 1125 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1126 1127 /* apply Rx specific ring traits */ 1128 ring->count = adapter->rx_ring_count; 1129 ring->queue_index = rxr_idx; 1130 1131 /* assign ring to adapter */ 1132 adapter->rx_ring[rxr_idx] = ring; 1133 } 1134 1135 return 0; 1136} 1137 1138 1139/** 1140 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1141 * @adapter: board private structure to initialize 1142 * 1143 * We allocate one q_vector per queue interrupt. If allocation fails we 1144 * return -ENOMEM. 1145 **/ 1146static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1147{ 1148 int q_vectors = adapter->num_q_vectors; 1149 int rxr_remaining = adapter->num_rx_queues; 1150 int txr_remaining = adapter->num_tx_queues; 1151 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1152 int err; 1153 1154 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1155 for (; rxr_remaining; v_idx++) { 1156 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1157 0, 0, 1, rxr_idx); 1158 1159 if (err) 1160 goto err_out; 1161 1162 /* update counts and index */ 1163 rxr_remaining--; 1164 rxr_idx++; 1165 } 1166 } 1167 1168 for (; v_idx < q_vectors; v_idx++) { 1169 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1170 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1171 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1172 tqpv, txr_idx, rqpv, rxr_idx); 1173 1174 if (err) 1175 goto err_out; 1176 1177 /* update counts and index */ 1178 rxr_remaining -= rqpv; 1179 txr_remaining -= tqpv; 1180 rxr_idx++; 1181 txr_idx++; 1182 } 1183 1184 return 0; 1185 1186err_out: 1187 adapter->num_tx_queues = 0; 1188 adapter->num_rx_queues = 0; 1189 adapter->num_q_vectors = 0; 1190 1191 while (v_idx--) 1192 igb_free_q_vector(adapter, v_idx); 1193 1194 return -ENOMEM; 1195} 1196 1197/** 1198 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1199 * 1200 * This function initializes the interrupts and allocates all of the queues. 1201 **/ 1202static int igb_init_interrupt_scheme(struct igb_adapter *adapter) 1203{ 1204 struct pci_dev *pdev = adapter->pdev; 1205 int err; 1206 1207 igb_set_interrupt_capability(adapter); 1208 1209 err = igb_alloc_q_vectors(adapter); 1210 if (err) { 1211 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1212 goto err_alloc_q_vectors; 1213 } 1214 1215 igb_cache_ring_register(adapter); 1216 1217 return 0; 1218 1219err_alloc_q_vectors: 1220 igb_reset_interrupt_capability(adapter); 1221 return err; 1222} 1223 1224/** 1225 * igb_request_irq - initialize interrupts 1226 * 1227 * Attempts to configure interrupts using the best available 1228 * capabilities of the hardware and kernel. 1229 **/ 1230static int igb_request_irq(struct igb_adapter *adapter) 1231{ 1232 struct net_device *netdev = adapter->netdev; 1233 struct pci_dev *pdev = adapter->pdev; 1234 int err = 0; 1235 1236 if (adapter->msix_entries) { 1237 err = igb_request_msix(adapter); 1238 if (!err) 1239 goto request_done; 1240 /* fall back to MSI */ 1241 igb_free_all_tx_resources(adapter); 1242 igb_free_all_rx_resources(adapter); 1243 igb_clear_interrupt_scheme(adapter); 1244 if (!pci_enable_msi(pdev)) 1245 adapter->flags |= IGB_FLAG_HAS_MSI; 1246 adapter->num_tx_queues = 1; 1247 adapter->num_rx_queues = 1; 1248 adapter->num_q_vectors = 1; 1249 err = igb_alloc_q_vectors(adapter); 1250 if (err) { 1251 dev_err(&pdev->dev, 1252 "Unable to allocate memory for vectors\n"); 1253 goto request_done; 1254 } 1255 igb_setup_all_tx_resources(adapter); 1256 igb_setup_all_rx_resources(adapter); 1257 } 1258 1259 igb_assign_vector(adapter->q_vector[0], 0); 1260 1261 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1262 err = request_irq(pdev->irq, igb_intr_msi, 0, 1263 netdev->name, adapter); 1264 if (!err) 1265 goto request_done; 1266 1267 /* fall back to legacy interrupts */ 1268 igb_reset_interrupt_capability(adapter); 1269 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1270 } 1271 1272 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1273 netdev->name, adapter); 1274 1275 if (err) 1276 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1277 err); 1278 1279request_done: 1280 return err; 1281} 1282 1283static void igb_free_irq(struct igb_adapter *adapter) 1284{ 1285 if (adapter->msix_entries) { 1286 int vector = 0, i; 1287 1288 free_irq(adapter->msix_entries[vector++].vector, adapter); 1289 1290 for (i = 0; i < adapter->num_q_vectors; i++) 1291 free_irq(adapter->msix_entries[vector++].vector, 1292 adapter->q_vector[i]); 1293 } else { 1294 free_irq(adapter->pdev->irq, adapter); 1295 } 1296} 1297 1298/** 1299 * igb_irq_disable - Mask off interrupt generation on the NIC 1300 * @adapter: board private structure 1301 **/ 1302static void igb_irq_disable(struct igb_adapter *adapter) 1303{ 1304 struct e1000_hw *hw = &adapter->hw; 1305 1306 /* 1307 * we need to be careful when disabling interrupts. The VFs are also 1308 * mapped into these registers and so clearing the bits can cause 1309 * issues on the VF drivers so we only need to clear what we set 1310 */ 1311 if (adapter->msix_entries) { 1312 u32 regval = rd32(E1000_EIAM); 1313 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1314 wr32(E1000_EIMC, adapter->eims_enable_mask); 1315 regval = rd32(E1000_EIAC); 1316 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1317 } 1318 1319 wr32(E1000_IAM, 0); 1320 wr32(E1000_IMC, ~0); 1321 wrfl(); 1322 if (adapter->msix_entries) { 1323 int i; 1324 for (i = 0; i < adapter->num_q_vectors; i++) 1325 synchronize_irq(adapter->msix_entries[i].vector); 1326 } else { 1327 synchronize_irq(adapter->pdev->irq); 1328 } 1329} 1330 1331/** 1332 * igb_irq_enable - Enable default interrupt generation settings 1333 * @adapter: board private structure 1334 **/ 1335static void igb_irq_enable(struct igb_adapter *adapter) 1336{ 1337 struct e1000_hw *hw = &adapter->hw; 1338 1339 if (adapter->msix_entries) { 1340 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1341 u32 regval = rd32(E1000_EIAC); 1342 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1343 regval = rd32(E1000_EIAM); 1344 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1345 wr32(E1000_EIMS, adapter->eims_enable_mask); 1346 if (adapter->vfs_allocated_count) { 1347 wr32(E1000_MBVFIMR, 0xFF); 1348 ims |= E1000_IMS_VMMB; 1349 } 1350 wr32(E1000_IMS, ims); 1351 } else { 1352 wr32(E1000_IMS, IMS_ENABLE_MASK | 1353 E1000_IMS_DRSTA); 1354 wr32(E1000_IAM, IMS_ENABLE_MASK | 1355 E1000_IMS_DRSTA); 1356 } 1357} 1358 1359static void igb_update_mng_vlan(struct igb_adapter *adapter) 1360{ 1361 struct e1000_hw *hw = &adapter->hw; 1362 u16 vid = adapter->hw.mng_cookie.vlan_id; 1363 u16 old_vid = adapter->mng_vlan_id; 1364 1365 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1366 /* add VID to filter table */ 1367 igb_vfta_set(hw, vid, true); 1368 adapter->mng_vlan_id = vid; 1369 } else { 1370 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1371 } 1372 1373 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1374 (vid != old_vid) && 1375 !test_bit(old_vid, adapter->active_vlans)) { 1376 /* remove VID from filter table */ 1377 igb_vfta_set(hw, old_vid, false); 1378 } 1379} 1380 1381/** 1382 * igb_release_hw_control - release control of the h/w to f/w 1383 * @adapter: address of board private structure 1384 * 1385 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1386 * For ASF and Pass Through versions of f/w this means that the 1387 * driver is no longer loaded. 1388 * 1389 **/ 1390static void igb_release_hw_control(struct igb_adapter *adapter) 1391{ 1392 struct e1000_hw *hw = &adapter->hw; 1393 u32 ctrl_ext; 1394 1395 /* Let firmware take over control of h/w */ 1396 ctrl_ext = rd32(E1000_CTRL_EXT); 1397 wr32(E1000_CTRL_EXT, 1398 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1399} 1400 1401/** 1402 * igb_get_hw_control - get control of the h/w from f/w 1403 * @adapter: address of board private structure 1404 * 1405 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1406 * For ASF and Pass Through versions of f/w this means that 1407 * the driver is loaded. 1408 * 1409 **/ 1410static void igb_get_hw_control(struct igb_adapter *adapter) 1411{ 1412 struct e1000_hw *hw = &adapter->hw; 1413 u32 ctrl_ext; 1414 1415 /* Let firmware know the driver has taken over */ 1416 ctrl_ext = rd32(E1000_CTRL_EXT); 1417 wr32(E1000_CTRL_EXT, 1418 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1419} 1420 1421/** 1422 * igb_configure - configure the hardware for RX and TX 1423 * @adapter: private board structure 1424 **/ 1425static void igb_configure(struct igb_adapter *adapter) 1426{ 1427 struct net_device *netdev = adapter->netdev; 1428 int i; 1429 1430 igb_get_hw_control(adapter); 1431 igb_set_rx_mode(netdev); 1432 1433 igb_restore_vlan(adapter); 1434 1435 igb_setup_tctl(adapter); 1436 igb_setup_mrqc(adapter); 1437 igb_setup_rctl(adapter); 1438 1439 igb_configure_tx(adapter); 1440 igb_configure_rx(adapter); 1441 1442 igb_rx_fifo_flush_82575(&adapter->hw); 1443 1444 /* call igb_desc_unused which always leaves 1445 * at least 1 descriptor unused to make sure 1446 * next_to_use != next_to_clean */ 1447 for (i = 0; i < adapter->num_rx_queues; i++) { 1448 struct igb_ring *ring = adapter->rx_ring[i]; 1449 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1450 } 1451} 1452 1453/** 1454 * igb_power_up_link - Power up the phy/serdes link 1455 * @adapter: address of board private structure 1456 **/ 1457void igb_power_up_link(struct igb_adapter *adapter) 1458{ 1459 igb_reset_phy(&adapter->hw); 1460 1461 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1462 igb_power_up_phy_copper(&adapter->hw); 1463 else 1464 igb_power_up_serdes_link_82575(&adapter->hw); 1465} 1466 1467/** 1468 * igb_power_down_link - Power down the phy/serdes link 1469 * @adapter: address of board private structure 1470 */ 1471static void igb_power_down_link(struct igb_adapter *adapter) 1472{ 1473 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1474 igb_power_down_phy_copper_82575(&adapter->hw); 1475 else 1476 igb_shutdown_serdes_link_82575(&adapter->hw); 1477} 1478 1479/** 1480 * igb_up - Open the interface and prepare it to handle traffic 1481 * @adapter: board private structure 1482 **/ 1483int igb_up(struct igb_adapter *adapter) 1484{ 1485 struct e1000_hw *hw = &adapter->hw; 1486 int i; 1487 1488 /* hardware has been reset, we need to reload some things */ 1489 igb_configure(adapter); 1490 1491 clear_bit(__IGB_DOWN, &adapter->state); 1492 1493 for (i = 0; i < adapter->num_q_vectors; i++) 1494 napi_enable(&(adapter->q_vector[i]->napi)); 1495 1496 if (adapter->msix_entries) 1497 igb_configure_msix(adapter); 1498 else 1499 igb_assign_vector(adapter->q_vector[0], 0); 1500 1501 /* Clear any pending interrupts. */ 1502 rd32(E1000_ICR); 1503 igb_irq_enable(adapter); 1504 1505 /* notify VFs that reset has been completed */ 1506 if (adapter->vfs_allocated_count) { 1507 u32 reg_data = rd32(E1000_CTRL_EXT); 1508 reg_data |= E1000_CTRL_EXT_PFRSTD; 1509 wr32(E1000_CTRL_EXT, reg_data); 1510 } 1511 1512 netif_tx_start_all_queues(adapter->netdev); 1513 1514 /* start the watchdog. */ 1515 hw->mac.get_link_status = 1; 1516 schedule_work(&adapter->watchdog_task); 1517 1518 return 0; 1519} 1520 1521void igb_down(struct igb_adapter *adapter) 1522{ 1523 struct net_device *netdev = adapter->netdev; 1524 struct e1000_hw *hw = &adapter->hw; 1525 u32 tctl, rctl; 1526 int i; 1527 1528 /* signal that we're down so the interrupt handler does not 1529 * reschedule our watchdog timer */ 1530 set_bit(__IGB_DOWN, &adapter->state); 1531 1532 /* disable receives in the hardware */ 1533 rctl = rd32(E1000_RCTL); 1534 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1535 /* flush and sleep below */ 1536 1537 netif_tx_stop_all_queues(netdev); 1538 1539 /* disable transmits in the hardware */ 1540 tctl = rd32(E1000_TCTL); 1541 tctl &= ~E1000_TCTL_EN; 1542 wr32(E1000_TCTL, tctl); 1543 /* flush both disables and wait for them to finish */ 1544 wrfl(); 1545 msleep(10); 1546 1547 for (i = 0; i < adapter->num_q_vectors; i++) 1548 napi_disable(&(adapter->q_vector[i]->napi)); 1549 1550 igb_irq_disable(adapter); 1551 1552 del_timer_sync(&adapter->watchdog_timer); 1553 del_timer_sync(&adapter->phy_info_timer); 1554 1555 netif_carrier_off(netdev); 1556 1557 /* record the stats before reset*/ 1558 spin_lock(&adapter->stats64_lock); 1559 igb_update_stats(adapter, &adapter->stats64); 1560 spin_unlock(&adapter->stats64_lock); 1561 1562 adapter->link_speed = 0; 1563 adapter->link_duplex = 0; 1564 1565 if (!pci_channel_offline(adapter->pdev)) 1566 igb_reset(adapter); 1567 igb_clean_all_tx_rings(adapter); 1568 igb_clean_all_rx_rings(adapter); 1569#ifdef CONFIG_IGB_DCA 1570 1571 /* since we reset the hardware DCA settings were cleared */ 1572 igb_setup_dca(adapter); 1573#endif 1574} 1575 1576void igb_reinit_locked(struct igb_adapter *adapter) 1577{ 1578 WARN_ON(in_interrupt()); 1579 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1580 msleep(1); 1581 igb_down(adapter); 1582 igb_up(adapter); 1583 clear_bit(__IGB_RESETTING, &adapter->state); 1584} 1585 1586void igb_reset(struct igb_adapter *adapter) 1587{ 1588 struct pci_dev *pdev = adapter->pdev; 1589 struct e1000_hw *hw = &adapter->hw; 1590 struct e1000_mac_info *mac = &hw->mac; 1591 struct e1000_fc_info *fc = &hw->fc; 1592 u32 pba = 0, tx_space, min_tx_space, min_rx_space; 1593 u16 hwm; 1594 1595 /* Repartition Pba for greater than 9k mtu 1596 * To take effect CTRL.RST is required. 1597 */ 1598 switch (mac->type) { 1599 case e1000_i350: 1600 case e1000_82580: 1601 pba = rd32(E1000_RXPBS); 1602 pba = igb_rxpbs_adjust_82580(pba); 1603 break; 1604 case e1000_82576: 1605 pba = rd32(E1000_RXPBS); 1606 pba &= E1000_RXPBS_SIZE_MASK_82576; 1607 break; 1608 case e1000_82575: 1609 case e1000_i210: 1610 case e1000_i211: 1611 default: 1612 pba = E1000_PBA_34K; 1613 break; 1614 } 1615 1616 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1617 (mac->type < e1000_82576)) { 1618 /* adjust PBA for jumbo frames */ 1619 wr32(E1000_PBA, pba); 1620 1621 /* To maintain wire speed transmits, the Tx FIFO should be 1622 * large enough to accommodate two full transmit packets, 1623 * rounded up to the next 1KB and expressed in KB. Likewise, 1624 * the Rx FIFO should be large enough to accommodate at least 1625 * one full receive packet and is similarly rounded up and 1626 * expressed in KB. */ 1627 pba = rd32(E1000_PBA); 1628 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1629 tx_space = pba >> 16; 1630 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1631 pba &= 0xffff; 1632 /* the tx fifo also stores 16 bytes of information about the tx 1633 * but don't include ethernet FCS because hardware appends it */ 1634 min_tx_space = (adapter->max_frame_size + 1635 sizeof(union e1000_adv_tx_desc) - 1636 ETH_FCS_LEN) * 2; 1637 min_tx_space = ALIGN(min_tx_space, 1024); 1638 min_tx_space >>= 10; 1639 /* software strips receive CRC, so leave room for it */ 1640 min_rx_space = adapter->max_frame_size; 1641 min_rx_space = ALIGN(min_rx_space, 1024); 1642 min_rx_space >>= 10; 1643 1644 /* If current Tx allocation is less than the min Tx FIFO size, 1645 * and the min Tx FIFO size is less than the current Rx FIFO 1646 * allocation, take space away from current Rx allocation */ 1647 if (tx_space < min_tx_space && 1648 ((min_tx_space - tx_space) < pba)) { 1649 pba = pba - (min_tx_space - tx_space); 1650 1651 /* if short on rx space, rx wins and must trump tx 1652 * adjustment */ 1653 if (pba < min_rx_space) 1654 pba = min_rx_space; 1655 } 1656 wr32(E1000_PBA, pba); 1657 } 1658 1659 /* flow control settings */ 1660 /* The high water mark must be low enough to fit one full frame 1661 * (or the size used for early receive) above it in the Rx FIFO. 1662 * Set it to the lower of: 1663 * - 90% of the Rx FIFO size, or 1664 * - the full Rx FIFO size minus one full frame */ 1665 hwm = min(((pba << 10) * 9 / 10), 1666 ((pba << 10) - 2 * adapter->max_frame_size)); 1667 1668 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ 1669 fc->low_water = fc->high_water - 16; 1670 fc->pause_time = 0xFFFF; 1671 fc->send_xon = 1; 1672 fc->current_mode = fc->requested_mode; 1673 1674 /* disable receive for all VFs and wait one second */ 1675 if (adapter->vfs_allocated_count) { 1676 int i; 1677 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1678 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1679 1680 /* ping all the active vfs to let them know we are going down */ 1681 igb_ping_all_vfs(adapter); 1682 1683 /* disable transmits and receives */ 1684 wr32(E1000_VFRE, 0); 1685 wr32(E1000_VFTE, 0); 1686 } 1687 1688 /* Allow time for pending master requests to run */ 1689 hw->mac.ops.reset_hw(hw); 1690 wr32(E1000_WUC, 0); 1691 1692 if (hw->mac.ops.init_hw(hw)) 1693 dev_err(&pdev->dev, "Hardware Error\n"); 1694 1695 /* 1696 * Flow control settings reset on hardware reset, so guarantee flow 1697 * control is off when forcing speed. 1698 */ 1699 if (!hw->mac.autoneg) 1700 igb_force_mac_fc(hw); 1701 1702 igb_init_dmac(adapter, pba); 1703 if (!netif_running(adapter->netdev)) 1704 igb_power_down_link(adapter); 1705 1706 igb_update_mng_vlan(adapter); 1707 1708 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 1709 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 1710 1711#ifdef CONFIG_IGB_PTP 1712 /* Re-enable PTP, where applicable. */ 1713 igb_ptp_reset(adapter); 1714#endif /* CONFIG_IGB_PTP */ 1715 1716 igb_get_phy_info(hw); 1717} 1718 1719static netdev_features_t igb_fix_features(struct net_device *netdev, 1720 netdev_features_t features) 1721{ 1722 /* 1723 * Since there is no support for separate rx/tx vlan accel 1724 * enable/disable make sure tx flag is always in same state as rx. 1725 */ 1726 if (features & NETIF_F_HW_VLAN_RX) 1727 features |= NETIF_F_HW_VLAN_TX; 1728 else 1729 features &= ~NETIF_F_HW_VLAN_TX; 1730 1731 return features; 1732} 1733 1734static int igb_set_features(struct net_device *netdev, 1735 netdev_features_t features) 1736{ 1737 netdev_features_t changed = netdev->features ^ features; 1738 struct igb_adapter *adapter = netdev_priv(netdev); 1739 1740 if (changed & NETIF_F_HW_VLAN_RX) 1741 igb_vlan_mode(netdev, features); 1742 1743 if (!(changed & NETIF_F_RXALL)) 1744 return 0; 1745 1746 netdev->features = features; 1747 1748 if (netif_running(netdev)) 1749 igb_reinit_locked(adapter); 1750 else 1751 igb_reset(adapter); 1752 1753 return 0; 1754} 1755 1756static const struct net_device_ops igb_netdev_ops = { 1757 .ndo_open = igb_open, 1758 .ndo_stop = igb_close, 1759 .ndo_start_xmit = igb_xmit_frame, 1760 .ndo_get_stats64 = igb_get_stats64, 1761 .ndo_set_rx_mode = igb_set_rx_mode, 1762 .ndo_set_mac_address = igb_set_mac, 1763 .ndo_change_mtu = igb_change_mtu, 1764 .ndo_do_ioctl = igb_ioctl, 1765 .ndo_tx_timeout = igb_tx_timeout, 1766 .ndo_validate_addr = eth_validate_addr, 1767 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 1768 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 1769 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 1770 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 1771 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, 1772 .ndo_get_vf_config = igb_ndo_get_vf_config, 1773#ifdef CONFIG_NET_POLL_CONTROLLER 1774 .ndo_poll_controller = igb_netpoll, 1775#endif 1776 .ndo_fix_features = igb_fix_features, 1777 .ndo_set_features = igb_set_features, 1778}; 1779 1780/** 1781 * igb_set_fw_version - Configure version string for ethtool 1782 * @adapter: adapter struct 1783 * 1784 **/ 1785void igb_set_fw_version(struct igb_adapter *adapter) 1786{ 1787 struct e1000_hw *hw = &adapter->hw; 1788 struct e1000_fw_version fw; 1789 1790 igb_get_fw_version(hw, &fw); 1791 1792 switch (hw->mac.type) { 1793 case e1000_i211: 1794 snprintf(adapter->fw_version, sizeof(adapter->fw_version), 1795 "%2d.%2d-%d", 1796 fw.invm_major, fw.invm_minor, fw.invm_img_type); 1797 break; 1798 1799 default: 1800 /* if option is rom valid, display its version too */ 1801 if (fw.or_valid) { 1802 snprintf(adapter->fw_version, 1803 sizeof(adapter->fw_version), 1804 "%d.%d, 0x%08x, %d.%d.%d", 1805 fw.eep_major, fw.eep_minor, fw.etrack_id, 1806 fw.or_major, fw.or_build, fw.or_patch); 1807 /* no option rom */ 1808 } else { 1809 snprintf(adapter->fw_version, 1810 sizeof(adapter->fw_version), 1811 "%d.%d, 0x%08x", 1812 fw.eep_major, fw.eep_minor, fw.etrack_id); 1813 } 1814 break; 1815 } 1816 return; 1817} 1818 1819/** 1820 * igb_probe - Device Initialization Routine 1821 * @pdev: PCI device information struct 1822 * @ent: entry in igb_pci_tbl 1823 * 1824 * Returns 0 on success, negative on failure 1825 * 1826 * igb_probe initializes an adapter identified by a pci_dev structure. 1827 * The OS initialization, configuring of the adapter private structure, 1828 * and a hardware reset occur. 1829 **/ 1830static int __devinit igb_probe(struct pci_dev *pdev, 1831 const struct pci_device_id *ent) 1832{ 1833 struct net_device *netdev; 1834 struct igb_adapter *adapter; 1835 struct e1000_hw *hw; 1836 u16 eeprom_data = 0; 1837 s32 ret_val; 1838 static int global_quad_port_a; /* global quad port a indication */ 1839 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 1840 unsigned long mmio_start, mmio_len; 1841 int err, pci_using_dac; 1842 u16 eeprom_apme_mask = IGB_EEPROM_APME; 1843 u8 part_str[E1000_PBANUM_LENGTH]; 1844 1845 /* Catch broken hardware that put the wrong VF device ID in 1846 * the PCIe SR-IOV capability. 1847 */ 1848 if (pdev->is_virtfn) { 1849 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 1850 pci_name(pdev), pdev->vendor, pdev->device); 1851 return -EINVAL; 1852 } 1853 1854 err = pci_enable_device_mem(pdev); 1855 if (err) 1856 return err; 1857 1858 pci_using_dac = 0; 1859 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 1860 if (!err) { 1861 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 1862 if (!err) 1863 pci_using_dac = 1; 1864 } else { 1865 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1866 if (err) { 1867 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 1868 if (err) { 1869 dev_err(&pdev->dev, "No usable DMA " 1870 "configuration, aborting\n"); 1871 goto err_dma; 1872 } 1873 } 1874 } 1875 1876 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 1877 IORESOURCE_MEM), 1878 igb_driver_name); 1879 if (err) 1880 goto err_pci_reg; 1881 1882 pci_enable_pcie_error_reporting(pdev); 1883 1884 pci_set_master(pdev); 1885 pci_save_state(pdev); 1886 1887 err = -ENOMEM; 1888 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 1889 IGB_MAX_TX_QUEUES); 1890 if (!netdev) 1891 goto err_alloc_etherdev; 1892 1893 SET_NETDEV_DEV(netdev, &pdev->dev); 1894 1895 pci_set_drvdata(pdev, netdev); 1896 adapter = netdev_priv(netdev); 1897 adapter->netdev = netdev; 1898 adapter->pdev = pdev; 1899 hw = &adapter->hw; 1900 hw->back = adapter; 1901 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 1902 1903 mmio_start = pci_resource_start(pdev, 0); 1904 mmio_len = pci_resource_len(pdev, 0); 1905 1906 err = -EIO; 1907 hw->hw_addr = ioremap(mmio_start, mmio_len); 1908 if (!hw->hw_addr) 1909 goto err_ioremap; 1910 1911 netdev->netdev_ops = &igb_netdev_ops; 1912 igb_set_ethtool_ops(netdev); 1913 netdev->watchdog_timeo = 5 * HZ; 1914 1915 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 1916 1917 netdev->mem_start = mmio_start; 1918 netdev->mem_end = mmio_start + mmio_len; 1919 1920 /* PCI config space info */ 1921 hw->vendor_id = pdev->vendor; 1922 hw->device_id = pdev->device; 1923 hw->revision_id = pdev->revision; 1924 hw->subsystem_vendor_id = pdev->subsystem_vendor; 1925 hw->subsystem_device_id = pdev->subsystem_device; 1926 1927 /* Copy the default MAC, PHY and NVM function pointers */ 1928 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 1929 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 1930 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 1931 /* Initialize skew-specific constants */ 1932 err = ei->get_invariants(hw); 1933 if (err) 1934 goto err_sw_init; 1935 1936 /* setup the private structure */ 1937 err = igb_sw_init(adapter); 1938 if (err) 1939 goto err_sw_init; 1940 1941 igb_get_bus_info_pcie(hw); 1942 1943 hw->phy.autoneg_wait_to_complete = false; 1944 1945 /* Copper options */ 1946 if (hw->phy.media_type == e1000_media_type_copper) { 1947 hw->phy.mdix = AUTO_ALL_MODES; 1948 hw->phy.disable_polarity_correction = false; 1949 hw->phy.ms_type = e1000_ms_hw_default; 1950 } 1951 1952 if (igb_check_reset_block(hw)) 1953 dev_info(&pdev->dev, 1954 "PHY reset is blocked due to SOL/IDER session.\n"); 1955 1956 /* 1957 * features is initialized to 0 in allocation, it might have bits 1958 * set by igb_sw_init so we should use an or instead of an 1959 * assignment. 1960 */ 1961 netdev->features |= NETIF_F_SG | 1962 NETIF_F_IP_CSUM | 1963 NETIF_F_IPV6_CSUM | 1964 NETIF_F_TSO | 1965 NETIF_F_TSO6 | 1966 NETIF_F_RXHASH | 1967 NETIF_F_RXCSUM | 1968 NETIF_F_HW_VLAN_RX | 1969 NETIF_F_HW_VLAN_TX; 1970 1971 /* copy netdev features into list of user selectable features */ 1972 netdev->hw_features |= netdev->features; 1973 netdev->hw_features |= NETIF_F_RXALL; 1974 1975 /* set this bit last since it cannot be part of hw_features */ 1976 netdev->features |= NETIF_F_HW_VLAN_FILTER; 1977 1978 netdev->vlan_features |= NETIF_F_TSO | 1979 NETIF_F_TSO6 | 1980 NETIF_F_IP_CSUM | 1981 NETIF_F_IPV6_CSUM | 1982 NETIF_F_SG; 1983 1984 netdev->priv_flags |= IFF_SUPP_NOFCS; 1985 1986 if (pci_using_dac) { 1987 netdev->features |= NETIF_F_HIGHDMA; 1988 netdev->vlan_features |= NETIF_F_HIGHDMA; 1989 } 1990 1991 if (hw->mac.type >= e1000_82576) { 1992 netdev->hw_features |= NETIF_F_SCTP_CSUM; 1993 netdev->features |= NETIF_F_SCTP_CSUM; 1994 } 1995 1996 netdev->priv_flags |= IFF_UNICAST_FLT; 1997 1998 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 1999 2000 /* before reading the NVM, reset the controller to put the device in a 2001 * known good starting state */ 2002 hw->mac.ops.reset_hw(hw); 2003 2004 /* 2005 * make sure the NVM is good , i211 parts have special NVM that 2006 * doesn't contain a checksum 2007 */ 2008 if (hw->mac.type != e1000_i211) { 2009 if (hw->nvm.ops.validate(hw) < 0) { 2010 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2011 err = -EIO; 2012 goto err_eeprom; 2013 } 2014 } 2015 2016 /* copy the MAC address out of the NVM */ 2017 if (hw->mac.ops.read_mac_addr(hw)) 2018 dev_err(&pdev->dev, "NVM Read Error\n"); 2019 2020 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2021 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); 2022 2023 if (!is_valid_ether_addr(netdev->perm_addr)) { 2024 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2025 err = -EIO; 2026 goto err_eeprom; 2027 } 2028 2029 /* get firmware version for ethtool -i */ 2030 igb_set_fw_version(adapter); 2031 2032 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2033 (unsigned long) adapter); 2034 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2035 (unsigned long) adapter); 2036 2037 INIT_WORK(&adapter->reset_task, igb_reset_task); 2038 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2039 2040 /* Initialize link properties that are user-changeable */ 2041 adapter->fc_autoneg = true; 2042 hw->mac.autoneg = true; 2043 hw->phy.autoneg_advertised = 0x2f; 2044 2045 hw->fc.requested_mode = e1000_fc_default; 2046 hw->fc.current_mode = e1000_fc_default; 2047 2048 igb_validate_mdi_setting(hw); 2049 2050 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, 2051 * enable the ACPI Magic Packet filter 2052 */ 2053 2054 if (hw->bus.func == 0) 2055 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 2056 else if (hw->mac.type >= e1000_82580) 2057 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2058 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2059 &eeprom_data); 2060 else if (hw->bus.func == 1) 2061 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2062 2063 if (eeprom_data & eeprom_apme_mask) 2064 adapter->eeprom_wol |= E1000_WUFC_MAG; 2065 2066 /* now that we have the eeprom settings, apply the special cases where 2067 * the eeprom may be wrong or the board simply won't support wake on 2068 * lan on a particular port */ 2069 switch (pdev->device) { 2070 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2071 adapter->eeprom_wol = 0; 2072 break; 2073 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2074 case E1000_DEV_ID_82576_FIBER: 2075 case E1000_DEV_ID_82576_SERDES: 2076 /* Wake events only supported on port A for dual fiber 2077 * regardless of eeprom setting */ 2078 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2079 adapter->eeprom_wol = 0; 2080 break; 2081 case E1000_DEV_ID_82576_QUAD_COPPER: 2082 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2083 /* if quad port adapter, disable WoL on all but port A */ 2084 if (global_quad_port_a != 0) 2085 adapter->eeprom_wol = 0; 2086 else 2087 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2088 /* Reset for multiple quad port adapters */ 2089 if (++global_quad_port_a == 4) 2090 global_quad_port_a = 0; 2091 break; 2092 } 2093 2094 /* initialize the wol settings based on the eeprom settings */ 2095 adapter->wol = adapter->eeprom_wol; 2096 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2097 2098 /* reset the hardware with the new settings */ 2099 igb_reset(adapter); 2100 2101 /* let the f/w know that the h/w is now under the control of the 2102 * driver. */ 2103 igb_get_hw_control(adapter); 2104 2105 strcpy(netdev->name, "eth%d"); 2106 err = register_netdev(netdev); 2107 if (err) 2108 goto err_register; 2109 2110 /* carrier off reporting is important to ethtool even BEFORE open */ 2111 netif_carrier_off(netdev); 2112 2113#ifdef CONFIG_IGB_DCA 2114 if (dca_add_requester(&pdev->dev) == 0) { 2115 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2116 dev_info(&pdev->dev, "DCA enabled\n"); 2117 igb_setup_dca(adapter); 2118 } 2119 2120#endif 2121 2122#ifdef CONFIG_IGB_PTP 2123 /* do hw tstamp init after resetting */ 2124 igb_ptp_init(adapter); 2125#endif /* CONFIG_IGB_PTP */ 2126 2127 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2128 /* print bus type/speed/width info */ 2129 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2130 netdev->name, 2131 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2132 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2133 "unknown"), 2134 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 2135 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" : 2136 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" : 2137 "unknown"), 2138 netdev->dev_addr); 2139 2140 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH); 2141 if (ret_val) 2142 strcpy(part_str, "Unknown"); 2143 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2144 dev_info(&pdev->dev, 2145 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2146 adapter->msix_entries ? "MSI-X" : 2147 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2148 adapter->num_rx_queues, adapter->num_tx_queues); 2149 switch (hw->mac.type) { 2150 case e1000_i350: 2151 case e1000_i210: 2152 case e1000_i211: 2153 igb_set_eee_i350(hw); 2154 break; 2155 default: 2156 break; 2157 } 2158 2159 pm_runtime_put_noidle(&pdev->dev); 2160 return 0; 2161 2162err_register: 2163 igb_release_hw_control(adapter); 2164err_eeprom: 2165 if (!igb_check_reset_block(hw)) 2166 igb_reset_phy(hw); 2167 2168 if (hw->flash_address) 2169 iounmap(hw->flash_address); 2170err_sw_init: 2171 igb_clear_interrupt_scheme(adapter); 2172 iounmap(hw->hw_addr); 2173err_ioremap: 2174 free_netdev(netdev); 2175err_alloc_etherdev: 2176 pci_release_selected_regions(pdev, 2177 pci_select_bars(pdev, IORESOURCE_MEM)); 2178err_pci_reg: 2179err_dma: 2180 pci_disable_device(pdev); 2181 return err; 2182} 2183 2184/** 2185 * igb_remove - Device Removal Routine 2186 * @pdev: PCI device information struct 2187 * 2188 * igb_remove is called by the PCI subsystem to alert the driver 2189 * that it should release a PCI device. The could be caused by a 2190 * Hot-Plug event, or because the driver is going to be removed from 2191 * memory. 2192 **/ 2193static void __devexit igb_remove(struct pci_dev *pdev) 2194{ 2195 struct net_device *netdev = pci_get_drvdata(pdev); 2196 struct igb_adapter *adapter = netdev_priv(netdev); 2197 struct e1000_hw *hw = &adapter->hw; 2198 2199 pm_runtime_get_noresume(&pdev->dev); 2200#ifdef CONFIG_IGB_PTP 2201 igb_ptp_stop(adapter); 2202#endif /* CONFIG_IGB_PTP */ 2203 2204 /* 2205 * The watchdog timer may be rescheduled, so explicitly 2206 * disable watchdog from being rescheduled. 2207 */ 2208 set_bit(__IGB_DOWN, &adapter->state); 2209 del_timer_sync(&adapter->watchdog_timer); 2210 del_timer_sync(&adapter->phy_info_timer); 2211 2212 cancel_work_sync(&adapter->reset_task); 2213 cancel_work_sync(&adapter->watchdog_task); 2214 2215#ifdef CONFIG_IGB_DCA 2216 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2217 dev_info(&pdev->dev, "DCA disabled\n"); 2218 dca_remove_requester(&pdev->dev); 2219 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2220 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2221 } 2222#endif 2223 2224 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2225 * would have already happened in close and is redundant. */ 2226 igb_release_hw_control(adapter); 2227 2228 unregister_netdev(netdev); 2229 2230 igb_clear_interrupt_scheme(adapter); 2231 2232#ifdef CONFIG_PCI_IOV 2233 /* reclaim resources allocated to VFs */ 2234 if (adapter->vf_data) { 2235 /* disable iov and allow time for transactions to clear */ 2236 if (igb_vfs_are_assigned(adapter)) { 2237 dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n"); 2238 } else { 2239 pci_disable_sriov(pdev); 2240 msleep(500); 2241 } 2242 2243 kfree(adapter->vf_data); 2244 adapter->vf_data = NULL; 2245 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2246 wrfl(); 2247 msleep(100); 2248 dev_info(&pdev->dev, "IOV Disabled\n"); 2249 } 2250#endif 2251 2252 iounmap(hw->hw_addr); 2253 if (hw->flash_address) 2254 iounmap(hw->flash_address); 2255 pci_release_selected_regions(pdev, 2256 pci_select_bars(pdev, IORESOURCE_MEM)); 2257 2258 kfree(adapter->shadow_vfta); 2259 free_netdev(netdev); 2260 2261 pci_disable_pcie_error_reporting(pdev); 2262 2263 pci_disable_device(pdev); 2264} 2265 2266/** 2267 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2268 * @adapter: board private structure to initialize 2269 * 2270 * This function initializes the vf specific data storage and then attempts to 2271 * allocate the VFs. The reason for ordering it this way is because it is much 2272 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2273 * the memory for the VFs. 2274 **/ 2275static void __devinit igb_probe_vfs(struct igb_adapter * adapter) 2276{ 2277#ifdef CONFIG_PCI_IOV 2278 struct pci_dev *pdev = adapter->pdev; 2279 struct e1000_hw *hw = &adapter->hw; 2280 int old_vfs = pci_num_vf(adapter->pdev); 2281 int i; 2282 2283 /* Virtualization features not supported on i210 family. */ 2284 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2285 return; 2286 2287 if (old_vfs) { 2288 dev_info(&pdev->dev, "%d pre-allocated VFs found - override " 2289 "max_vfs setting of %d\n", old_vfs, max_vfs); 2290 adapter->vfs_allocated_count = old_vfs; 2291 } 2292 2293 if (!adapter->vfs_allocated_count) 2294 return; 2295 2296 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2297 sizeof(struct vf_data_storage), GFP_KERNEL); 2298 2299 /* if allocation failed then we do not support SR-IOV */ 2300 if (!adapter->vf_data) { 2301 adapter->vfs_allocated_count = 0; 2302 dev_err(&pdev->dev, "Unable to allocate memory for VF " 2303 "Data Storage\n"); 2304 goto out; 2305 } 2306 2307 if (!old_vfs) { 2308 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) 2309 goto err_out; 2310 } 2311 dev_info(&pdev->dev, "%d VFs allocated\n", 2312 adapter->vfs_allocated_count); 2313 for (i = 0; i < adapter->vfs_allocated_count; i++) 2314 igb_vf_configure(adapter, i); 2315 2316 /* DMA Coalescing is not supported in IOV mode. */ 2317 adapter->flags &= ~IGB_FLAG_DMAC; 2318 goto out; 2319err_out: 2320 kfree(adapter->vf_data); 2321 adapter->vf_data = NULL; 2322 adapter->vfs_allocated_count = 0; 2323out: 2324 return; 2325#endif /* CONFIG_PCI_IOV */ 2326} 2327 2328/** 2329 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2330 * @adapter: board private structure to initialize 2331 * 2332 * igb_sw_init initializes the Adapter private data structure. 2333 * Fields are initialized based on PCI device information and 2334 * OS network device settings (MTU size). 2335 **/ 2336static int __devinit igb_sw_init(struct igb_adapter *adapter) 2337{ 2338 struct e1000_hw *hw = &adapter->hw; 2339 struct net_device *netdev = adapter->netdev; 2340 struct pci_dev *pdev = adapter->pdev; 2341 u32 max_rss_queues; 2342 2343 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2344 2345 /* set default ring sizes */ 2346 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2347 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2348 2349 /* set default ITR values */ 2350 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2351 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2352 2353 /* set default work limits */ 2354 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2355 2356 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2357 VLAN_HLEN; 2358 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2359 2360 spin_lock_init(&adapter->stats64_lock); 2361#ifdef CONFIG_PCI_IOV 2362 switch (hw->mac.type) { 2363 case e1000_82576: 2364 case e1000_i350: 2365 if (max_vfs > 7) { 2366 dev_warn(&pdev->dev, 2367 "Maximum of 7 VFs per PF, using max\n"); 2368 adapter->vfs_allocated_count = 7; 2369 } else 2370 adapter->vfs_allocated_count = max_vfs; 2371 break; 2372 default: 2373 break; 2374 } 2375#endif /* CONFIG_PCI_IOV */ 2376 2377 /* Determine the maximum number of RSS queues supported. */ 2378 switch (hw->mac.type) { 2379 case e1000_i211: 2380 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2381 break; 2382 case e1000_82575: 2383 case e1000_i210: 2384 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2385 break; 2386 case e1000_i350: 2387 /* I350 cannot do RSS and SR-IOV at the same time */ 2388 if (!!adapter->vfs_allocated_count) { 2389 max_rss_queues = 1; 2390 break; 2391 } 2392 /* fall through */ 2393 case e1000_82576: 2394 if (!!adapter->vfs_allocated_count) { 2395 max_rss_queues = 2; 2396 break; 2397 } 2398 /* fall through */ 2399 case e1000_82580: 2400 default: 2401 max_rss_queues = IGB_MAX_RX_QUEUES; 2402 break; 2403 } 2404 2405 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2406 2407 /* Determine if we need to pair queues. */ 2408 switch (hw->mac.type) { 2409 case e1000_82575: 2410 case e1000_i211: 2411 /* Device supports enough interrupts without queue pairing. */ 2412 break; 2413 case e1000_82576: 2414 /* 2415 * If VFs are going to be allocated with RSS queues then we 2416 * should pair the queues in order to conserve interrupts due 2417 * to limited supply. 2418 */ 2419 if ((adapter->rss_queues > 1) && 2420 (adapter->vfs_allocated_count > 6)) 2421 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2422 /* fall through */ 2423 case e1000_82580: 2424 case e1000_i350: 2425 case e1000_i210: 2426 default: 2427 /* 2428 * If rss_queues > half of max_rss_queues, pair the queues in 2429 * order to conserve interrupts due to limited supply. 2430 */ 2431 if (adapter->rss_queues > (max_rss_queues / 2)) 2432 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2433 break; 2434 } 2435 2436 /* Setup and initialize a copy of the hw vlan table array */ 2437 adapter->shadow_vfta = kzalloc(sizeof(u32) * 2438 E1000_VLAN_FILTER_TBL_SIZE, 2439 GFP_ATOMIC); 2440 2441 /* This call may decrease the number of queues */ 2442 if (igb_init_interrupt_scheme(adapter)) { 2443 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2444 return -ENOMEM; 2445 } 2446 2447 igb_probe_vfs(adapter); 2448 2449 /* Explicitly disable IRQ since the NIC can be in any state. */ 2450 igb_irq_disable(adapter); 2451 2452 if (hw->mac.type >= e1000_i350) 2453 adapter->flags &= ~IGB_FLAG_DMAC; 2454 2455 set_bit(__IGB_DOWN, &adapter->state); 2456 return 0; 2457} 2458 2459/** 2460 * igb_open - Called when a network interface is made active 2461 * @netdev: network interface device structure 2462 * 2463 * Returns 0 on success, negative value on failure 2464 * 2465 * The open entry point is called when a network interface is made 2466 * active by the system (IFF_UP). At this point all resources needed 2467 * for transmit and receive operations are allocated, the interrupt 2468 * handler is registered with the OS, the watchdog timer is started, 2469 * and the stack is notified that the interface is ready. 2470 **/ 2471static int __igb_open(struct net_device *netdev, bool resuming) 2472{ 2473 struct igb_adapter *adapter = netdev_priv(netdev); 2474 struct e1000_hw *hw = &adapter->hw; 2475 struct pci_dev *pdev = adapter->pdev; 2476 int err; 2477 int i; 2478 2479 /* disallow open during test */ 2480 if (test_bit(__IGB_TESTING, &adapter->state)) { 2481 WARN_ON(resuming); 2482 return -EBUSY; 2483 } 2484 2485 if (!resuming) 2486 pm_runtime_get_sync(&pdev->dev); 2487 2488 netif_carrier_off(netdev); 2489 2490 /* allocate transmit descriptors */ 2491 err = igb_setup_all_tx_resources(adapter); 2492 if (err) 2493 goto err_setup_tx; 2494 2495 /* allocate receive descriptors */ 2496 err = igb_setup_all_rx_resources(adapter); 2497 if (err) 2498 goto err_setup_rx; 2499 2500 igb_power_up_link(adapter); 2501 2502 /* before we allocate an interrupt, we must be ready to handle it. 2503 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 2504 * as soon as we call pci_request_irq, so we have to setup our 2505 * clean_rx handler before we do so. */ 2506 igb_configure(adapter); 2507 2508 err = igb_request_irq(adapter); 2509 if (err) 2510 goto err_req_irq; 2511 2512 /* Notify the stack of the actual queue counts. */ 2513 err = netif_set_real_num_tx_queues(adapter->netdev, 2514 adapter->num_tx_queues); 2515 if (err) 2516 goto err_set_queues; 2517 2518 err = netif_set_real_num_rx_queues(adapter->netdev, 2519 adapter->num_rx_queues); 2520 if (err) 2521 goto err_set_queues; 2522 2523 /* From here on the code is the same as igb_up() */ 2524 clear_bit(__IGB_DOWN, &adapter->state); 2525 2526 for (i = 0; i < adapter->num_q_vectors; i++) 2527 napi_enable(&(adapter->q_vector[i]->napi)); 2528 2529 /* Clear any pending interrupts. */ 2530 rd32(E1000_ICR); 2531 2532 igb_irq_enable(adapter); 2533 2534 /* notify VFs that reset has been completed */ 2535 if (adapter->vfs_allocated_count) { 2536 u32 reg_data = rd32(E1000_CTRL_EXT); 2537 reg_data |= E1000_CTRL_EXT_PFRSTD; 2538 wr32(E1000_CTRL_EXT, reg_data); 2539 } 2540 2541 netif_tx_start_all_queues(netdev); 2542 2543 if (!resuming) 2544 pm_runtime_put(&pdev->dev); 2545 2546 /* start the watchdog. */ 2547 hw->mac.get_link_status = 1; 2548 schedule_work(&adapter->watchdog_task); 2549 2550 return 0; 2551 2552err_set_queues: 2553 igb_free_irq(adapter); 2554err_req_irq: 2555 igb_release_hw_control(adapter); 2556 igb_power_down_link(adapter); 2557 igb_free_all_rx_resources(adapter); 2558err_setup_rx: 2559 igb_free_all_tx_resources(adapter); 2560err_setup_tx: 2561 igb_reset(adapter); 2562 if (!resuming) 2563 pm_runtime_put(&pdev->dev); 2564 2565 return err; 2566} 2567 2568static int igb_open(struct net_device *netdev) 2569{ 2570 return __igb_open(netdev, false); 2571} 2572 2573/** 2574 * igb_close - Disables a network interface 2575 * @netdev: network interface device structure 2576 * 2577 * Returns 0, this is not allowed to fail 2578 * 2579 * The close entry point is called when an interface is de-activated 2580 * by the OS. The hardware is still under the driver's control, but 2581 * needs to be disabled. A global MAC reset is issued to stop the 2582 * hardware, and all transmit and receive resources are freed. 2583 **/ 2584static int __igb_close(struct net_device *netdev, bool suspending) 2585{ 2586 struct igb_adapter *adapter = netdev_priv(netdev); 2587 struct pci_dev *pdev = adapter->pdev; 2588 2589 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 2590 2591 if (!suspending) 2592 pm_runtime_get_sync(&pdev->dev); 2593 2594 igb_down(adapter); 2595 igb_free_irq(adapter); 2596 2597 igb_free_all_tx_resources(adapter); 2598 igb_free_all_rx_resources(adapter); 2599 2600 if (!suspending) 2601 pm_runtime_put_sync(&pdev->dev); 2602 return 0; 2603} 2604 2605static int igb_close(struct net_device *netdev) 2606{ 2607 return __igb_close(netdev, false); 2608} 2609 2610/** 2611 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 2612 * @tx_ring: tx descriptor ring (for a specific queue) to setup 2613 * 2614 * Return 0 on success, negative on failure 2615 **/ 2616int igb_setup_tx_resources(struct igb_ring *tx_ring) 2617{ 2618 struct device *dev = tx_ring->dev; 2619 int size; 2620 2621 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 2622 2623 tx_ring->tx_buffer_info = vzalloc(size); 2624 if (!tx_ring->tx_buffer_info) 2625 goto err; 2626 2627 /* round up to nearest 4K */ 2628 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 2629 tx_ring->size = ALIGN(tx_ring->size, 4096); 2630 2631 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 2632 &tx_ring->dma, GFP_KERNEL); 2633 if (!tx_ring->desc) 2634 goto err; 2635 2636 tx_ring->next_to_use = 0; 2637 tx_ring->next_to_clean = 0; 2638 2639 return 0; 2640 2641err: 2642 vfree(tx_ring->tx_buffer_info); 2643 tx_ring->tx_buffer_info = NULL; 2644 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 2645 return -ENOMEM; 2646} 2647 2648/** 2649 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 2650 * (Descriptors) for all queues 2651 * @adapter: board private structure 2652 * 2653 * Return 0 on success, negative on failure 2654 **/ 2655static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 2656{ 2657 struct pci_dev *pdev = adapter->pdev; 2658 int i, err = 0; 2659 2660 for (i = 0; i < adapter->num_tx_queues; i++) { 2661 err = igb_setup_tx_resources(adapter->tx_ring[i]); 2662 if (err) { 2663 dev_err(&pdev->dev, 2664 "Allocation for Tx Queue %u failed\n", i); 2665 for (i--; i >= 0; i--) 2666 igb_free_tx_resources(adapter->tx_ring[i]); 2667 break; 2668 } 2669 } 2670 2671 return err; 2672} 2673 2674/** 2675 * igb_setup_tctl - configure the transmit control registers 2676 * @adapter: Board private structure 2677 **/ 2678void igb_setup_tctl(struct igb_adapter *adapter) 2679{ 2680 struct e1000_hw *hw = &adapter->hw; 2681 u32 tctl; 2682 2683 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 2684 wr32(E1000_TXDCTL(0), 0); 2685 2686 /* Program the Transmit Control Register */ 2687 tctl = rd32(E1000_TCTL); 2688 tctl &= ~E1000_TCTL_CT; 2689 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2690 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2691 2692 igb_config_collision_dist(hw); 2693 2694 /* Enable transmits */ 2695 tctl |= E1000_TCTL_EN; 2696 2697 wr32(E1000_TCTL, tctl); 2698} 2699 2700/** 2701 * igb_configure_tx_ring - Configure transmit ring after Reset 2702 * @adapter: board private structure 2703 * @ring: tx ring to configure 2704 * 2705 * Configure a transmit ring after a reset. 2706 **/ 2707void igb_configure_tx_ring(struct igb_adapter *adapter, 2708 struct igb_ring *ring) 2709{ 2710 struct e1000_hw *hw = &adapter->hw; 2711 u32 txdctl = 0; 2712 u64 tdba = ring->dma; 2713 int reg_idx = ring->reg_idx; 2714 2715 /* disable the queue */ 2716 wr32(E1000_TXDCTL(reg_idx), 0); 2717 wrfl(); 2718 mdelay(10); 2719 2720 wr32(E1000_TDLEN(reg_idx), 2721 ring->count * sizeof(union e1000_adv_tx_desc)); 2722 wr32(E1000_TDBAL(reg_idx), 2723 tdba & 0x00000000ffffffffULL); 2724 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 2725 2726 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 2727 wr32(E1000_TDH(reg_idx), 0); 2728 writel(0, ring->tail); 2729 2730 txdctl |= IGB_TX_PTHRESH; 2731 txdctl |= IGB_TX_HTHRESH << 8; 2732 txdctl |= IGB_TX_WTHRESH << 16; 2733 2734 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 2735 wr32(E1000_TXDCTL(reg_idx), txdctl); 2736} 2737 2738/** 2739 * igb_configure_tx - Configure transmit Unit after Reset 2740 * @adapter: board private structure 2741 * 2742 * Configure the Tx unit of the MAC after a reset. 2743 **/ 2744static void igb_configure_tx(struct igb_adapter *adapter) 2745{ 2746 int i; 2747 2748 for (i = 0; i < adapter->num_tx_queues; i++) 2749 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 2750} 2751 2752/** 2753 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 2754 * @rx_ring: rx descriptor ring (for a specific queue) to setup 2755 * 2756 * Returns 0 on success, negative on failure 2757 **/ 2758int igb_setup_rx_resources(struct igb_ring *rx_ring) 2759{ 2760 struct device *dev = rx_ring->dev; 2761 int size; 2762 2763 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 2764 2765 rx_ring->rx_buffer_info = vzalloc(size); 2766 if (!rx_ring->rx_buffer_info) 2767 goto err; 2768 2769 /* Round up to nearest 4K */ 2770 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 2771 rx_ring->size = ALIGN(rx_ring->size, 4096); 2772 2773 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 2774 &rx_ring->dma, GFP_KERNEL); 2775 if (!rx_ring->desc) 2776 goto err; 2777 2778 rx_ring->next_to_alloc = 0; 2779 rx_ring->next_to_clean = 0; 2780 rx_ring->next_to_use = 0; 2781 2782 return 0; 2783 2784err: 2785 vfree(rx_ring->rx_buffer_info); 2786 rx_ring->rx_buffer_info = NULL; 2787 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 2788 return -ENOMEM; 2789} 2790 2791/** 2792 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 2793 * (Descriptors) for all queues 2794 * @adapter: board private structure 2795 * 2796 * Return 0 on success, negative on failure 2797 **/ 2798static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 2799{ 2800 struct pci_dev *pdev = adapter->pdev; 2801 int i, err = 0; 2802 2803 for (i = 0; i < adapter->num_rx_queues; i++) { 2804 err = igb_setup_rx_resources(adapter->rx_ring[i]); 2805 if (err) { 2806 dev_err(&pdev->dev, 2807 "Allocation for Rx Queue %u failed\n", i); 2808 for (i--; i >= 0; i--) 2809 igb_free_rx_resources(adapter->rx_ring[i]); 2810 break; 2811 } 2812 } 2813 2814 return err; 2815} 2816 2817/** 2818 * igb_setup_mrqc - configure the multiple receive queue control registers 2819 * @adapter: Board private structure 2820 **/ 2821static void igb_setup_mrqc(struct igb_adapter *adapter) 2822{ 2823 struct e1000_hw *hw = &adapter->hw; 2824 u32 mrqc, rxcsum; 2825 u32 j, num_rx_queues, shift = 0; 2826 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, 2827 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, 2828 0xA32DCB77, 0x0CF23080, 0x3BB7426A, 2829 0xFA01ACBE }; 2830 2831 /* Fill out hash function seeds */ 2832 for (j = 0; j < 10; j++) 2833 wr32(E1000_RSSRK(j), rsskey[j]); 2834 2835 num_rx_queues = adapter->rss_queues; 2836 2837 switch (hw->mac.type) { 2838 case e1000_82575: 2839 shift = 6; 2840 break; 2841 case e1000_82576: 2842 /* 82576 supports 2 RSS queues for SR-IOV */ 2843 if (adapter->vfs_allocated_count) { 2844 shift = 3; 2845 num_rx_queues = 2; 2846 } 2847 break; 2848 default: 2849 break; 2850 } 2851 2852 /* 2853 * Populate the indirection table 4 entries at a time. To do this 2854 * we are generating the results for n and n+2 and then interleaving 2855 * those with the results with n+1 and n+3. 2856 */ 2857 for (j = 0; j < 32; j++) { 2858 /* first pass generates n and n+2 */ 2859 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues; 2860 u32 reta = (base & 0x07800780) >> (7 - shift); 2861 2862 /* second pass generates n+1 and n+3 */ 2863 base += 0x00010001 * num_rx_queues; 2864 reta |= (base & 0x07800780) << (1 + shift); 2865 2866 wr32(E1000_RETA(j), reta); 2867 } 2868 2869 /* 2870 * Disable raw packet checksumming so that RSS hash is placed in 2871 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 2872 * offloads as they are enabled by default 2873 */ 2874 rxcsum = rd32(E1000_RXCSUM); 2875 rxcsum |= E1000_RXCSUM_PCSD; 2876 2877 if (adapter->hw.mac.type >= e1000_82576) 2878 /* Enable Receive Checksum Offload for SCTP */ 2879 rxcsum |= E1000_RXCSUM_CRCOFL; 2880 2881 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 2882 wr32(E1000_RXCSUM, rxcsum); 2883 /* 2884 * Generate RSS hash based on TCP port numbers and/or 2885 * IPv4/v6 src and dst addresses since UDP cannot be 2886 * hashed reliably due to IP fragmentation 2887 */ 2888 2889 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 2890 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2891 E1000_MRQC_RSS_FIELD_IPV6 | 2892 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2893 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 2894 2895 /* If VMDq is enabled then we set the appropriate mode for that, else 2896 * we default to RSS so that an RSS hash is calculated per packet even 2897 * if we are only using one queue */ 2898 if (adapter->vfs_allocated_count) { 2899 if (hw->mac.type > e1000_82575) { 2900 /* Set the default pool for the PF's first queue */ 2901 u32 vtctl = rd32(E1000_VT_CTL); 2902 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 2903 E1000_VT_CTL_DISABLE_DEF_POOL); 2904 vtctl |= adapter->vfs_allocated_count << 2905 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 2906 wr32(E1000_VT_CTL, vtctl); 2907 } 2908 if (adapter->rss_queues > 1) 2909 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 2910 else 2911 mrqc |= E1000_MRQC_ENABLE_VMDQ; 2912 } else { 2913 if (hw->mac.type != e1000_i211) 2914 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 2915 } 2916 igb_vmm_control(adapter); 2917 2918 wr32(E1000_MRQC, mrqc); 2919} 2920 2921/** 2922 * igb_setup_rctl - configure the receive control registers 2923 * @adapter: Board private structure 2924 **/ 2925void igb_setup_rctl(struct igb_adapter *adapter) 2926{ 2927 struct e1000_hw *hw = &adapter->hw; 2928 u32 rctl; 2929 2930 rctl = rd32(E1000_RCTL); 2931 2932 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2933 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 2934 2935 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 2936 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2937 2938 /* 2939 * enable stripping of CRC. It's unlikely this will break BMC 2940 * redirection as it did with e1000. Newer features require 2941 * that the HW strips the CRC. 2942 */ 2943 rctl |= E1000_RCTL_SECRC; 2944 2945 /* disable store bad packets and clear size bits. */ 2946 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 2947 2948 /* enable LPE to prevent packets larger than max_frame_size */ 2949 rctl |= E1000_RCTL_LPE; 2950 2951 /* disable queue 0 to prevent tail write w/o re-config */ 2952 wr32(E1000_RXDCTL(0), 0); 2953 2954 /* Attention!!! For SR-IOV PF driver operations you must enable 2955 * queue drop for all VF and PF queues to prevent head of line blocking 2956 * if an un-trusted VF does not provide descriptors to hardware. 2957 */ 2958 if (adapter->vfs_allocated_count) { 2959 /* set all queue drop enable bits */ 2960 wr32(E1000_QDE, ALL_QUEUES); 2961 } 2962 2963 /* This is useful for sniffing bad packets. */ 2964 if (adapter->netdev->features & NETIF_F_RXALL) { 2965 /* UPE and MPE will be handled by normal PROMISC logic 2966 * in e1000e_set_rx_mode */ 2967 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 2968 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 2969 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 2970 2971 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 2972 E1000_RCTL_DPF | /* Allow filtered pause */ 2973 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 2974 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 2975 * and that breaks VLANs. 2976 */ 2977 } 2978 2979 wr32(E1000_RCTL, rctl); 2980} 2981 2982static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 2983 int vfn) 2984{ 2985 struct e1000_hw *hw = &adapter->hw; 2986 u32 vmolr; 2987 2988 /* if it isn't the PF check to see if VFs are enabled and 2989 * increase the size to support vlan tags */ 2990 if (vfn < adapter->vfs_allocated_count && 2991 adapter->vf_data[vfn].vlans_enabled) 2992 size += VLAN_TAG_SIZE; 2993 2994 vmolr = rd32(E1000_VMOLR(vfn)); 2995 vmolr &= ~E1000_VMOLR_RLPML_MASK; 2996 vmolr |= size | E1000_VMOLR_LPE; 2997 wr32(E1000_VMOLR(vfn), vmolr); 2998 2999 return 0; 3000} 3001 3002/** 3003 * igb_rlpml_set - set maximum receive packet size 3004 * @adapter: board private structure 3005 * 3006 * Configure maximum receivable packet size. 3007 **/ 3008static void igb_rlpml_set(struct igb_adapter *adapter) 3009{ 3010 u32 max_frame_size = adapter->max_frame_size; 3011 struct e1000_hw *hw = &adapter->hw; 3012 u16 pf_id = adapter->vfs_allocated_count; 3013 3014 if (pf_id) { 3015 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3016 /* 3017 * If we're in VMDQ or SR-IOV mode, then set global RLPML 3018 * to our max jumbo frame size, in case we need to enable 3019 * jumbo frames on one of the rings later. 3020 * This will not pass over-length frames into the default 3021 * queue because it's gated by the VMOLR.RLPML. 3022 */ 3023 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3024 } 3025 3026 wr32(E1000_RLPML, max_frame_size); 3027} 3028 3029static inline void igb_set_vmolr(struct igb_adapter *adapter, 3030 int vfn, bool aupe) 3031{ 3032 struct e1000_hw *hw = &adapter->hw; 3033 u32 vmolr; 3034 3035 /* 3036 * This register exists only on 82576 and newer so if we are older then 3037 * we should exit and do nothing 3038 */ 3039 if (hw->mac.type < e1000_82576) 3040 return; 3041 3042 vmolr = rd32(E1000_VMOLR(vfn)); 3043 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3044 if (aupe) 3045 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3046 else 3047 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3048 3049 /* clear all bits that might not be set */ 3050 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3051 3052 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3053 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3054 /* 3055 * for VMDq only allow the VFs and pool 0 to accept broadcast and 3056 * multicast packets 3057 */ 3058 if (vfn <= adapter->vfs_allocated_count) 3059 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3060 3061 wr32(E1000_VMOLR(vfn), vmolr); 3062} 3063 3064/** 3065 * igb_configure_rx_ring - Configure a receive ring after Reset 3066 * @adapter: board private structure 3067 * @ring: receive ring to be configured 3068 * 3069 * Configure the Rx unit of the MAC after a reset. 3070 **/ 3071void igb_configure_rx_ring(struct igb_adapter *adapter, 3072 struct igb_ring *ring) 3073{ 3074 struct e1000_hw *hw = &adapter->hw; 3075 u64 rdba = ring->dma; 3076 int reg_idx = ring->reg_idx; 3077 u32 srrctl = 0, rxdctl = 0; 3078 3079 /* disable the queue */ 3080 wr32(E1000_RXDCTL(reg_idx), 0); 3081 3082 /* Set DMA base address registers */ 3083 wr32(E1000_RDBAL(reg_idx), 3084 rdba & 0x00000000ffffffffULL); 3085 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3086 wr32(E1000_RDLEN(reg_idx), 3087 ring->count * sizeof(union e1000_adv_rx_desc)); 3088 3089 /* initialize head and tail */ 3090 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3091 wr32(E1000_RDH(reg_idx), 0); 3092 writel(0, ring->tail); 3093 3094 /* set descriptor configuration */ 3095 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3096 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3097 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3098#ifdef CONFIG_IGB_PTP 3099 if (hw->mac.type >= e1000_82580) 3100 srrctl |= E1000_SRRCTL_TIMESTAMP; 3101#endif /* CONFIG_IGB_PTP */ 3102 /* Only set Drop Enable if we are supporting multiple queues */ 3103 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3104 srrctl |= E1000_SRRCTL_DROP_EN; 3105 3106 wr32(E1000_SRRCTL(reg_idx), srrctl); 3107 3108 /* set filtering for VMDQ pools */ 3109 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3110 3111 rxdctl |= IGB_RX_PTHRESH; 3112 rxdctl |= IGB_RX_HTHRESH << 8; 3113 rxdctl |= IGB_RX_WTHRESH << 16; 3114 3115 /* enable receive descriptor fetching */ 3116 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3117 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3118} 3119 3120/** 3121 * igb_configure_rx - Configure receive Unit after Reset 3122 * @adapter: board private structure 3123 * 3124 * Configure the Rx unit of the MAC after a reset. 3125 **/ 3126static void igb_configure_rx(struct igb_adapter *adapter) 3127{ 3128 int i; 3129 3130 /* set UTA to appropriate mode */ 3131 igb_set_uta(adapter); 3132 3133 /* set the correct pool for the PF default MAC address in entry 0 */ 3134 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3135 adapter->vfs_allocated_count); 3136 3137 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3138 * the Base and Length of the Rx Descriptor Ring */ 3139 for (i = 0; i < adapter->num_rx_queues; i++) 3140 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3141} 3142 3143/** 3144 * igb_free_tx_resources - Free Tx Resources per Queue 3145 * @tx_ring: Tx descriptor ring for a specific queue 3146 * 3147 * Free all transmit software resources 3148 **/ 3149void igb_free_tx_resources(struct igb_ring *tx_ring) 3150{ 3151 igb_clean_tx_ring(tx_ring); 3152 3153 vfree(tx_ring->tx_buffer_info); 3154 tx_ring->tx_buffer_info = NULL; 3155 3156 /* if not set, then don't free */ 3157 if (!tx_ring->desc) 3158 return; 3159 3160 dma_free_coherent(tx_ring->dev, tx_ring->size, 3161 tx_ring->desc, tx_ring->dma); 3162 3163 tx_ring->desc = NULL; 3164} 3165 3166/** 3167 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3168 * @adapter: board private structure 3169 * 3170 * Free all transmit software resources 3171 **/ 3172static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3173{ 3174 int i; 3175 3176 for (i = 0; i < adapter->num_tx_queues; i++) 3177 igb_free_tx_resources(adapter->tx_ring[i]); 3178} 3179 3180void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3181 struct igb_tx_buffer *tx_buffer) 3182{ 3183 if (tx_buffer->skb) { 3184 dev_kfree_skb_any(tx_buffer->skb); 3185 if (dma_unmap_len(tx_buffer, len)) 3186 dma_unmap_single(ring->dev, 3187 dma_unmap_addr(tx_buffer, dma), 3188 dma_unmap_len(tx_buffer, len), 3189 DMA_TO_DEVICE); 3190 } else if (dma_unmap_len(tx_buffer, len)) { 3191 dma_unmap_page(ring->dev, 3192 dma_unmap_addr(tx_buffer, dma), 3193 dma_unmap_len(tx_buffer, len), 3194 DMA_TO_DEVICE); 3195 } 3196 tx_buffer->next_to_watch = NULL; 3197 tx_buffer->skb = NULL; 3198 dma_unmap_len_set(tx_buffer, len, 0); 3199 /* buffer_info must be completely set up in the transmit path */ 3200} 3201 3202/** 3203 * igb_clean_tx_ring - Free Tx Buffers 3204 * @tx_ring: ring to be cleaned 3205 **/ 3206static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3207{ 3208 struct igb_tx_buffer *buffer_info; 3209 unsigned long size; 3210 u16 i; 3211 3212 if (!tx_ring->tx_buffer_info) 3213 return; 3214 /* Free all the Tx ring sk_buffs */ 3215 3216 for (i = 0; i < tx_ring->count; i++) { 3217 buffer_info = &tx_ring->tx_buffer_info[i]; 3218 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3219 } 3220 3221 netdev_tx_reset_queue(txring_txq(tx_ring)); 3222 3223 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3224 memset(tx_ring->tx_buffer_info, 0, size); 3225 3226 /* Zero out the descriptor ring */ 3227 memset(tx_ring->desc, 0, tx_ring->size); 3228 3229 tx_ring->next_to_use = 0; 3230 tx_ring->next_to_clean = 0; 3231} 3232 3233/** 3234 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3235 * @adapter: board private structure 3236 **/ 3237static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3238{ 3239 int i; 3240 3241 for (i = 0; i < adapter->num_tx_queues; i++) 3242 igb_clean_tx_ring(adapter->tx_ring[i]); 3243} 3244 3245/** 3246 * igb_free_rx_resources - Free Rx Resources 3247 * @rx_ring: ring to clean the resources from 3248 * 3249 * Free all receive software resources 3250 **/ 3251void igb_free_rx_resources(struct igb_ring *rx_ring) 3252{ 3253 igb_clean_rx_ring(rx_ring); 3254 3255 vfree(rx_ring->rx_buffer_info); 3256 rx_ring->rx_buffer_info = NULL; 3257 3258 /* if not set, then don't free */ 3259 if (!rx_ring->desc) 3260 return; 3261 3262 dma_free_coherent(rx_ring->dev, rx_ring->size, 3263 rx_ring->desc, rx_ring->dma); 3264 3265 rx_ring->desc = NULL; 3266} 3267 3268/** 3269 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3270 * @adapter: board private structure 3271 * 3272 * Free all receive software resources 3273 **/ 3274static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3275{ 3276 int i; 3277 3278 for (i = 0; i < adapter->num_rx_queues; i++) 3279 igb_free_rx_resources(adapter->rx_ring[i]); 3280} 3281 3282/** 3283 * igb_clean_rx_ring - Free Rx Buffers per Queue 3284 * @rx_ring: ring to free buffers from 3285 **/ 3286static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3287{ 3288 unsigned long size; 3289 u16 i; 3290 3291 if (rx_ring->skb) 3292 dev_kfree_skb(rx_ring->skb); 3293 rx_ring->skb = NULL; 3294 3295 if (!rx_ring->rx_buffer_info) 3296 return; 3297 3298 /* Free all the Rx ring sk_buffs */ 3299 for (i = 0; i < rx_ring->count; i++) { 3300 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3301 3302 if (!buffer_info->page) 3303 continue; 3304 3305 dma_unmap_page(rx_ring->dev, 3306 buffer_info->dma, 3307 PAGE_SIZE, 3308 DMA_FROM_DEVICE); 3309 __free_page(buffer_info->page); 3310 3311 buffer_info->page = NULL; 3312 } 3313 3314 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3315 memset(rx_ring->rx_buffer_info, 0, size); 3316 3317 /* Zero out the descriptor ring */ 3318 memset(rx_ring->desc, 0, rx_ring->size); 3319 3320 rx_ring->next_to_alloc = 0; 3321 rx_ring->next_to_clean = 0; 3322 rx_ring->next_to_use = 0; 3323} 3324 3325/** 3326 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3327 * @adapter: board private structure 3328 **/ 3329static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3330{ 3331 int i; 3332 3333 for (i = 0; i < adapter->num_rx_queues; i++) 3334 igb_clean_rx_ring(adapter->rx_ring[i]); 3335} 3336 3337/** 3338 * igb_set_mac - Change the Ethernet Address of the NIC 3339 * @netdev: network interface device structure 3340 * @p: pointer to an address structure 3341 * 3342 * Returns 0 on success, negative on failure 3343 **/ 3344static int igb_set_mac(struct net_device *netdev, void *p) 3345{ 3346 struct igb_adapter *adapter = netdev_priv(netdev); 3347 struct e1000_hw *hw = &adapter->hw; 3348 struct sockaddr *addr = p; 3349 3350 if (!is_valid_ether_addr(addr->sa_data)) 3351 return -EADDRNOTAVAIL; 3352 3353 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3354 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3355 3356 /* set the correct pool for the new PF MAC address in entry 0 */ 3357 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3358 adapter->vfs_allocated_count); 3359 3360 return 0; 3361} 3362 3363/** 3364 * igb_write_mc_addr_list - write multicast addresses to MTA 3365 * @netdev: network interface device structure 3366 * 3367 * Writes multicast address list to the MTA hash table. 3368 * Returns: -ENOMEM on failure 3369 * 0 on no addresses written 3370 * X on writing X addresses to MTA 3371 **/ 3372static int igb_write_mc_addr_list(struct net_device *netdev) 3373{ 3374 struct igb_adapter *adapter = netdev_priv(netdev); 3375 struct e1000_hw *hw = &adapter->hw; 3376 struct netdev_hw_addr *ha; 3377 u8 *mta_list; 3378 int i; 3379 3380 if (netdev_mc_empty(netdev)) { 3381 /* nothing to program, so clear mc list */ 3382 igb_update_mc_addr_list(hw, NULL, 0); 3383 igb_restore_vf_multicasts(adapter); 3384 return 0; 3385 } 3386 3387 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3388 if (!mta_list) 3389 return -ENOMEM; 3390 3391 /* The shared function expects a packed array of only addresses. */ 3392 i = 0; 3393 netdev_for_each_mc_addr(ha, netdev) 3394 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3395 3396 igb_update_mc_addr_list(hw, mta_list, i); 3397 kfree(mta_list); 3398 3399 return netdev_mc_count(netdev); 3400} 3401 3402/** 3403 * igb_write_uc_addr_list - write unicast addresses to RAR table 3404 * @netdev: network interface device structure 3405 * 3406 * Writes unicast address list to the RAR table. 3407 * Returns: -ENOMEM on failure/insufficient address space 3408 * 0 on no addresses written 3409 * X on writing X addresses to the RAR table 3410 **/ 3411static int igb_write_uc_addr_list(struct net_device *netdev) 3412{ 3413 struct igb_adapter *adapter = netdev_priv(netdev); 3414 struct e1000_hw *hw = &adapter->hw; 3415 unsigned int vfn = adapter->vfs_allocated_count; 3416 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3417 int count = 0; 3418 3419 /* return ENOMEM indicating insufficient memory for addresses */ 3420 if (netdev_uc_count(netdev) > rar_entries) 3421 return -ENOMEM; 3422 3423 if (!netdev_uc_empty(netdev) && rar_entries) { 3424 struct netdev_hw_addr *ha; 3425 3426 netdev_for_each_uc_addr(ha, netdev) { 3427 if (!rar_entries) 3428 break; 3429 igb_rar_set_qsel(adapter, ha->addr, 3430 rar_entries--, 3431 vfn); 3432 count++; 3433 } 3434 } 3435 /* write the addresses in reverse order to avoid write combining */ 3436 for (; rar_entries > 0 ; rar_entries--) { 3437 wr32(E1000_RAH(rar_entries), 0); 3438 wr32(E1000_RAL(rar_entries), 0); 3439 } 3440 wrfl(); 3441 3442 return count; 3443} 3444 3445/** 3446 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3447 * @netdev: network interface device structure 3448 * 3449 * The set_rx_mode entry point is called whenever the unicast or multicast 3450 * address lists or the network interface flags are updated. This routine is 3451 * responsible for configuring the hardware for proper unicast, multicast, 3452 * promiscuous mode, and all-multi behavior. 3453 **/ 3454static void igb_set_rx_mode(struct net_device *netdev) 3455{ 3456 struct igb_adapter *adapter = netdev_priv(netdev); 3457 struct e1000_hw *hw = &adapter->hw; 3458 unsigned int vfn = adapter->vfs_allocated_count; 3459 u32 rctl, vmolr = 0; 3460 int count; 3461 3462 /* Check for Promiscuous and All Multicast modes */ 3463 rctl = rd32(E1000_RCTL); 3464 3465 /* clear the effected bits */ 3466 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 3467 3468 if (netdev->flags & IFF_PROMISC) { 3469 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3470 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 3471 } else { 3472 if (netdev->flags & IFF_ALLMULTI) { 3473 rctl |= E1000_RCTL_MPE; 3474 vmolr |= E1000_VMOLR_MPME; 3475 } else { 3476 /* 3477 * Write addresses to the MTA, if the attempt fails 3478 * then we should just turn on promiscuous mode so 3479 * that we can at least receive multicast traffic 3480 */ 3481 count = igb_write_mc_addr_list(netdev); 3482 if (count < 0) { 3483 rctl |= E1000_RCTL_MPE; 3484 vmolr |= E1000_VMOLR_MPME; 3485 } else if (count) { 3486 vmolr |= E1000_VMOLR_ROMPE; 3487 } 3488 } 3489 /* 3490 * Write addresses to available RAR registers, if there is not 3491 * sufficient space to store all the addresses then enable 3492 * unicast promiscuous mode 3493 */ 3494 count = igb_write_uc_addr_list(netdev); 3495 if (count < 0) { 3496 rctl |= E1000_RCTL_UPE; 3497 vmolr |= E1000_VMOLR_ROPE; 3498 } 3499 rctl |= E1000_RCTL_VFE; 3500 } 3501 wr32(E1000_RCTL, rctl); 3502 3503 /* 3504 * In order to support SR-IOV and eventually VMDq it is necessary to set 3505 * the VMOLR to enable the appropriate modes. Without this workaround 3506 * we will have issues with VLAN tag stripping not being done for frames 3507 * that are only arriving because we are the default pool 3508 */ 3509 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 3510 return; 3511 3512 vmolr |= rd32(E1000_VMOLR(vfn)) & 3513 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 3514 wr32(E1000_VMOLR(vfn), vmolr); 3515 igb_restore_vf_multicasts(adapter); 3516} 3517 3518static void igb_check_wvbr(struct igb_adapter *adapter) 3519{ 3520 struct e1000_hw *hw = &adapter->hw; 3521 u32 wvbr = 0; 3522 3523 switch (hw->mac.type) { 3524 case e1000_82576: 3525 case e1000_i350: 3526 if (!(wvbr = rd32(E1000_WVBR))) 3527 return; 3528 break; 3529 default: 3530 break; 3531 } 3532 3533 adapter->wvbr |= wvbr; 3534} 3535 3536#define IGB_STAGGERED_QUEUE_OFFSET 8 3537 3538static void igb_spoof_check(struct igb_adapter *adapter) 3539{ 3540 int j; 3541 3542 if (!adapter->wvbr) 3543 return; 3544 3545 for(j = 0; j < adapter->vfs_allocated_count; j++) { 3546 if (adapter->wvbr & (1 << j) || 3547 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 3548 dev_warn(&adapter->pdev->dev, 3549 "Spoof event(s) detected on VF %d\n", j); 3550 adapter->wvbr &= 3551 ~((1 << j) | 3552 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 3553 } 3554 } 3555} 3556 3557/* Need to wait a few seconds after link up to get diagnostic information from 3558 * the phy */ 3559static void igb_update_phy_info(unsigned long data) 3560{ 3561 struct igb_adapter *adapter = (struct igb_adapter *) data; 3562 igb_get_phy_info(&adapter->hw); 3563} 3564 3565/** 3566 * igb_has_link - check shared code for link and determine up/down 3567 * @adapter: pointer to driver private info 3568 **/ 3569bool igb_has_link(struct igb_adapter *adapter) 3570{ 3571 struct e1000_hw *hw = &adapter->hw; 3572 bool link_active = false; 3573 s32 ret_val = 0; 3574 3575 /* get_link_status is set on LSC (link status) interrupt or 3576 * rx sequence error interrupt. get_link_status will stay 3577 * false until the e1000_check_for_link establishes link 3578 * for copper adapters ONLY 3579 */ 3580 switch (hw->phy.media_type) { 3581 case e1000_media_type_copper: 3582 if (hw->mac.get_link_status) { 3583 ret_val = hw->mac.ops.check_for_link(hw); 3584 link_active = !hw->mac.get_link_status; 3585 } else { 3586 link_active = true; 3587 } 3588 break; 3589 case e1000_media_type_internal_serdes: 3590 ret_val = hw->mac.ops.check_for_link(hw); 3591 link_active = hw->mac.serdes_has_link; 3592 break; 3593 default: 3594 case e1000_media_type_unknown: 3595 break; 3596 } 3597 3598 return link_active; 3599} 3600 3601static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 3602{ 3603 bool ret = false; 3604 u32 ctrl_ext, thstat; 3605 3606 /* check for thermal sensor event on i350 copper only */ 3607 if (hw->mac.type == e1000_i350) { 3608 thstat = rd32(E1000_THSTAT); 3609 ctrl_ext = rd32(E1000_CTRL_EXT); 3610 3611 if ((hw->phy.media_type == e1000_media_type_copper) && 3612 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3613 ret = !!(thstat & event); 3614 } 3615 } 3616 3617 return ret; 3618} 3619 3620/** 3621 * igb_watchdog - Timer Call-back 3622 * @data: pointer to adapter cast into an unsigned long 3623 **/ 3624static void igb_watchdog(unsigned long data) 3625{ 3626 struct igb_adapter *adapter = (struct igb_adapter *)data; 3627 /* Do the rest outside of interrupt context */ 3628 schedule_work(&adapter->watchdog_task); 3629} 3630 3631static void igb_watchdog_task(struct work_struct *work) 3632{ 3633 struct igb_adapter *adapter = container_of(work, 3634 struct igb_adapter, 3635 watchdog_task); 3636 struct e1000_hw *hw = &adapter->hw; 3637 struct net_device *netdev = adapter->netdev; 3638 u32 link; 3639 int i; 3640 3641 link = igb_has_link(adapter); 3642 if (link) { 3643 /* Cancel scheduled suspend requests. */ 3644 pm_runtime_resume(netdev->dev.parent); 3645 3646 if (!netif_carrier_ok(netdev)) { 3647 u32 ctrl; 3648 hw->mac.ops.get_speed_and_duplex(hw, 3649 &adapter->link_speed, 3650 &adapter->link_duplex); 3651 3652 ctrl = rd32(E1000_CTRL); 3653 /* Links status message must follow this format */ 3654 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s " 3655 "Duplex, Flow Control: %s\n", 3656 netdev->name, 3657 adapter->link_speed, 3658 adapter->link_duplex == FULL_DUPLEX ? 3659 "Full" : "Half", 3660 (ctrl & E1000_CTRL_TFCE) && 3661 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 3662 (ctrl & E1000_CTRL_RFCE) ? "RX" : 3663 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 3664 3665 /* check for thermal sensor event */ 3666 if (igb_thermal_sensor_event(hw, 3667 E1000_THSTAT_LINK_THROTTLE)) { 3668 netdev_info(netdev, "The network adapter link " 3669 "speed was downshifted because it " 3670 "overheated\n"); 3671 } 3672 3673 /* adjust timeout factor according to speed/duplex */ 3674 adapter->tx_timeout_factor = 1; 3675 switch (adapter->link_speed) { 3676 case SPEED_10: 3677 adapter->tx_timeout_factor = 14; 3678 break; 3679 case SPEED_100: 3680 /* maybe add some timeout factor ? */ 3681 break; 3682 } 3683 3684 netif_carrier_on(netdev); 3685 3686 igb_ping_all_vfs(adapter); 3687 igb_check_vf_rate_limit(adapter); 3688 3689 /* link state has changed, schedule phy info update */ 3690 if (!test_bit(__IGB_DOWN, &adapter->state)) 3691 mod_timer(&adapter->phy_info_timer, 3692 round_jiffies(jiffies + 2 * HZ)); 3693 } 3694 } else { 3695 if (netif_carrier_ok(netdev)) { 3696 adapter->link_speed = 0; 3697 adapter->link_duplex = 0; 3698 3699 /* check for thermal sensor event */ 3700 if (igb_thermal_sensor_event(hw, 3701 E1000_THSTAT_PWR_DOWN)) { 3702 netdev_err(netdev, "The network adapter was " 3703 "stopped because it overheated\n"); 3704 } 3705 3706 /* Links status message must follow this format */ 3707 printk(KERN_INFO "igb: %s NIC Link is Down\n", 3708 netdev->name); 3709 netif_carrier_off(netdev); 3710 3711 igb_ping_all_vfs(adapter); 3712 3713 /* link state has changed, schedule phy info update */ 3714 if (!test_bit(__IGB_DOWN, &adapter->state)) 3715 mod_timer(&adapter->phy_info_timer, 3716 round_jiffies(jiffies + 2 * HZ)); 3717 3718 pm_schedule_suspend(netdev->dev.parent, 3719 MSEC_PER_SEC * 5); 3720 } 3721 } 3722 3723 spin_lock(&adapter->stats64_lock); 3724 igb_update_stats(adapter, &adapter->stats64); 3725 spin_unlock(&adapter->stats64_lock); 3726 3727 for (i = 0; i < adapter->num_tx_queues; i++) { 3728 struct igb_ring *tx_ring = adapter->tx_ring[i]; 3729 if (!netif_carrier_ok(netdev)) { 3730 /* We've lost link, so the controller stops DMA, 3731 * but we've got queued Tx work that's never going 3732 * to get done, so reset controller to flush Tx. 3733 * (Do the reset outside of interrupt context). */ 3734 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 3735 adapter->tx_timeout_count++; 3736 schedule_work(&adapter->reset_task); 3737 /* return immediately since reset is imminent */ 3738 return; 3739 } 3740 } 3741 3742 /* Force detection of hung controller every watchdog period */ 3743 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 3744 } 3745 3746 /* Cause software interrupt to ensure rx ring is cleaned */ 3747 if (adapter->msix_entries) { 3748 u32 eics = 0; 3749 for (i = 0; i < adapter->num_q_vectors; i++) 3750 eics |= adapter->q_vector[i]->eims_value; 3751 wr32(E1000_EICS, eics); 3752 } else { 3753 wr32(E1000_ICS, E1000_ICS_RXDMT0); 3754 } 3755 3756 igb_spoof_check(adapter); 3757 3758 /* Reset the timer */ 3759 if (!test_bit(__IGB_DOWN, &adapter->state)) 3760 mod_timer(&adapter->watchdog_timer, 3761 round_jiffies(jiffies + 2 * HZ)); 3762} 3763 3764enum latency_range { 3765 lowest_latency = 0, 3766 low_latency = 1, 3767 bulk_latency = 2, 3768 latency_invalid = 255 3769}; 3770 3771/** 3772 * igb_update_ring_itr - update the dynamic ITR value based on packet size 3773 * 3774 * Stores a new ITR value based on strictly on packet size. This 3775 * algorithm is less sophisticated than that used in igb_update_itr, 3776 * due to the difficulty of synchronizing statistics across multiple 3777 * receive rings. The divisors and thresholds used by this function 3778 * were determined based on theoretical maximum wire speed and testing 3779 * data, in order to minimize response time while increasing bulk 3780 * throughput. 3781 * This functionality is controlled by the InterruptThrottleRate module 3782 * parameter (see igb_param.c) 3783 * NOTE: This function is called only when operating in a multiqueue 3784 * receive environment. 3785 * @q_vector: pointer to q_vector 3786 **/ 3787static void igb_update_ring_itr(struct igb_q_vector *q_vector) 3788{ 3789 int new_val = q_vector->itr_val; 3790 int avg_wire_size = 0; 3791 struct igb_adapter *adapter = q_vector->adapter; 3792 unsigned int packets; 3793 3794 /* For non-gigabit speeds, just fix the interrupt rate at 4000 3795 * ints/sec - ITR timer value of 120 ticks. 3796 */ 3797 if (adapter->link_speed != SPEED_1000) { 3798 new_val = IGB_4K_ITR; 3799 goto set_itr_val; 3800 } 3801 3802 packets = q_vector->rx.total_packets; 3803 if (packets) 3804 avg_wire_size = q_vector->rx.total_bytes / packets; 3805 3806 packets = q_vector->tx.total_packets; 3807 if (packets) 3808 avg_wire_size = max_t(u32, avg_wire_size, 3809 q_vector->tx.total_bytes / packets); 3810 3811 /* if avg_wire_size isn't set no work was done */ 3812 if (!avg_wire_size) 3813 goto clear_counts; 3814 3815 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 3816 avg_wire_size += 24; 3817 3818 /* Don't starve jumbo frames */ 3819 avg_wire_size = min(avg_wire_size, 3000); 3820 3821 /* Give a little boost to mid-size frames */ 3822 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 3823 new_val = avg_wire_size / 3; 3824 else 3825 new_val = avg_wire_size / 2; 3826 3827 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 3828 if (new_val < IGB_20K_ITR && 3829 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 3830 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 3831 new_val = IGB_20K_ITR; 3832 3833set_itr_val: 3834 if (new_val != q_vector->itr_val) { 3835 q_vector->itr_val = new_val; 3836 q_vector->set_itr = 1; 3837 } 3838clear_counts: 3839 q_vector->rx.total_bytes = 0; 3840 q_vector->rx.total_packets = 0; 3841 q_vector->tx.total_bytes = 0; 3842 q_vector->tx.total_packets = 0; 3843} 3844 3845/** 3846 * igb_update_itr - update the dynamic ITR value based on statistics 3847 * Stores a new ITR value based on packets and byte 3848 * counts during the last interrupt. The advantage of per interrupt 3849 * computation is faster updates and more accurate ITR for the current 3850 * traffic pattern. Constants in this function were computed 3851 * based on theoretical maximum wire speed and thresholds were set based 3852 * on testing data as well as attempting to minimize response time 3853 * while increasing bulk throughput. 3854 * this functionality is controlled by the InterruptThrottleRate module 3855 * parameter (see igb_param.c) 3856 * NOTE: These calculations are only valid when operating in a single- 3857 * queue environment. 3858 * @q_vector: pointer to q_vector 3859 * @ring_container: ring info to update the itr for 3860 **/ 3861static void igb_update_itr(struct igb_q_vector *q_vector, 3862 struct igb_ring_container *ring_container) 3863{ 3864 unsigned int packets = ring_container->total_packets; 3865 unsigned int bytes = ring_container->total_bytes; 3866 u8 itrval = ring_container->itr; 3867 3868 /* no packets, exit with status unchanged */ 3869 if (packets == 0) 3870 return; 3871 3872 switch (itrval) { 3873 case lowest_latency: 3874 /* handle TSO and jumbo frames */ 3875 if (bytes/packets > 8000) 3876 itrval = bulk_latency; 3877 else if ((packets < 5) && (bytes > 512)) 3878 itrval = low_latency; 3879 break; 3880 case low_latency: /* 50 usec aka 20000 ints/s */ 3881 if (bytes > 10000) { 3882 /* this if handles the TSO accounting */ 3883 if (bytes/packets > 8000) { 3884 itrval = bulk_latency; 3885 } else if ((packets < 10) || ((bytes/packets) > 1200)) { 3886 itrval = bulk_latency; 3887 } else if ((packets > 35)) { 3888 itrval = lowest_latency; 3889 } 3890 } else if (bytes/packets > 2000) { 3891 itrval = bulk_latency; 3892 } else if (packets <= 2 && bytes < 512) { 3893 itrval = lowest_latency; 3894 } 3895 break; 3896 case bulk_latency: /* 250 usec aka 4000 ints/s */ 3897 if (bytes > 25000) { 3898 if (packets > 35) 3899 itrval = low_latency; 3900 } else if (bytes < 1500) { 3901 itrval = low_latency; 3902 } 3903 break; 3904 } 3905 3906 /* clear work counters since we have the values we need */ 3907 ring_container->total_bytes = 0; 3908 ring_container->total_packets = 0; 3909 3910 /* write updated itr to ring container */ 3911 ring_container->itr = itrval; 3912} 3913 3914static void igb_set_itr(struct igb_q_vector *q_vector) 3915{ 3916 struct igb_adapter *adapter = q_vector->adapter; 3917 u32 new_itr = q_vector->itr_val; 3918 u8 current_itr = 0; 3919 3920 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 3921 if (adapter->link_speed != SPEED_1000) { 3922 current_itr = 0; 3923 new_itr = IGB_4K_ITR; 3924 goto set_itr_now; 3925 } 3926 3927 igb_update_itr(q_vector, &q_vector->tx); 3928 igb_update_itr(q_vector, &q_vector->rx); 3929 3930 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 3931 3932 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 3933 if (current_itr == lowest_latency && 3934 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 3935 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 3936 current_itr = low_latency; 3937 3938 switch (current_itr) { 3939 /* counts and packets in update_itr are dependent on these numbers */ 3940 case lowest_latency: 3941 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 3942 break; 3943 case low_latency: 3944 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 3945 break; 3946 case bulk_latency: 3947 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 3948 break; 3949 default: 3950 break; 3951 } 3952 3953set_itr_now: 3954 if (new_itr != q_vector->itr_val) { 3955 /* this attempts to bias the interrupt rate towards Bulk 3956 * by adding intermediate steps when interrupt rate is 3957 * increasing */ 3958 new_itr = new_itr > q_vector->itr_val ? 3959 max((new_itr * q_vector->itr_val) / 3960 (new_itr + (q_vector->itr_val >> 2)), 3961 new_itr) : 3962 new_itr; 3963 /* Don't write the value here; it resets the adapter's 3964 * internal timer, and causes us to delay far longer than 3965 * we should between interrupts. Instead, we write the ITR 3966 * value at the beginning of the next interrupt so the timing 3967 * ends up being correct. 3968 */ 3969 q_vector->itr_val = new_itr; 3970 q_vector->set_itr = 1; 3971 } 3972} 3973 3974static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 3975 u32 type_tucmd, u32 mss_l4len_idx) 3976{ 3977 struct e1000_adv_tx_context_desc *context_desc; 3978 u16 i = tx_ring->next_to_use; 3979 3980 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 3981 3982 i++; 3983 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 3984 3985 /* set bits to identify this as an advanced context descriptor */ 3986 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 3987 3988 /* For 82575, context index must be unique per ring. */ 3989 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 3990 mss_l4len_idx |= tx_ring->reg_idx << 4; 3991 3992 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 3993 context_desc->seqnum_seed = 0; 3994 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 3995 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 3996} 3997 3998static int igb_tso(struct igb_ring *tx_ring, 3999 struct igb_tx_buffer *first, 4000 u8 *hdr_len) 4001{ 4002 struct sk_buff *skb = first->skb; 4003 u32 vlan_macip_lens, type_tucmd; 4004 u32 mss_l4len_idx, l4len; 4005 4006 if (!skb_is_gso(skb)) 4007 return 0; 4008 4009 if (skb_header_cloned(skb)) { 4010 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 4011 if (err) 4012 return err; 4013 } 4014 4015 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4016 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4017 4018 if (first->protocol == __constant_htons(ETH_P_IP)) { 4019 struct iphdr *iph = ip_hdr(skb); 4020 iph->tot_len = 0; 4021 iph->check = 0; 4022 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4023 iph->daddr, 0, 4024 IPPROTO_TCP, 4025 0); 4026 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4027 first->tx_flags |= IGB_TX_FLAGS_TSO | 4028 IGB_TX_FLAGS_CSUM | 4029 IGB_TX_FLAGS_IPV4; 4030 } else if (skb_is_gso_v6(skb)) { 4031 ipv6_hdr(skb)->payload_len = 0; 4032 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4033 &ipv6_hdr(skb)->daddr, 4034 0, IPPROTO_TCP, 0); 4035 first->tx_flags |= IGB_TX_FLAGS_TSO | 4036 IGB_TX_FLAGS_CSUM; 4037 } 4038 4039 /* compute header lengths */ 4040 l4len = tcp_hdrlen(skb); 4041 *hdr_len = skb_transport_offset(skb) + l4len; 4042 4043 /* update gso size and bytecount with header size */ 4044 first->gso_segs = skb_shinfo(skb)->gso_segs; 4045 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4046 4047 /* MSS L4LEN IDX */ 4048 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4049 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4050 4051 /* VLAN MACLEN IPLEN */ 4052 vlan_macip_lens = skb_network_header_len(skb); 4053 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4054 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4055 4056 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4057 4058 return 1; 4059} 4060 4061static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4062{ 4063 struct sk_buff *skb = first->skb; 4064 u32 vlan_macip_lens = 0; 4065 u32 mss_l4len_idx = 0; 4066 u32 type_tucmd = 0; 4067 4068 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4069 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4070 return; 4071 } else { 4072 u8 l4_hdr = 0; 4073 switch (first->protocol) { 4074 case __constant_htons(ETH_P_IP): 4075 vlan_macip_lens |= skb_network_header_len(skb); 4076 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4077 l4_hdr = ip_hdr(skb)->protocol; 4078 break; 4079 case __constant_htons(ETH_P_IPV6): 4080 vlan_macip_lens |= skb_network_header_len(skb); 4081 l4_hdr = ipv6_hdr(skb)->nexthdr; 4082 break; 4083 default: 4084 if (unlikely(net_ratelimit())) { 4085 dev_warn(tx_ring->dev, 4086 "partial checksum but proto=%x!\n", 4087 first->protocol); 4088 } 4089 break; 4090 } 4091 4092 switch (l4_hdr) { 4093 case IPPROTO_TCP: 4094 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4095 mss_l4len_idx = tcp_hdrlen(skb) << 4096 E1000_ADVTXD_L4LEN_SHIFT; 4097 break; 4098 case IPPROTO_SCTP: 4099 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4100 mss_l4len_idx = sizeof(struct sctphdr) << 4101 E1000_ADVTXD_L4LEN_SHIFT; 4102 break; 4103 case IPPROTO_UDP: 4104 mss_l4len_idx = sizeof(struct udphdr) << 4105 E1000_ADVTXD_L4LEN_SHIFT; 4106 break; 4107 default: 4108 if (unlikely(net_ratelimit())) { 4109 dev_warn(tx_ring->dev, 4110 "partial checksum but l4 proto=%x!\n", 4111 l4_hdr); 4112 } 4113 break; 4114 } 4115 4116 /* update TX checksum flag */ 4117 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4118 } 4119 4120 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4121 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4122 4123 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4124} 4125 4126static __le32 igb_tx_cmd_type(u32 tx_flags) 4127{ 4128 /* set type for advanced descriptor with frame checksum insertion */ 4129 __le32 cmd_type = cpu_to_le32(E1000_ADVTXD_DTYP_DATA | 4130 E1000_ADVTXD_DCMD_IFCS | 4131 E1000_ADVTXD_DCMD_DEXT); 4132 4133 /* set HW vlan bit if vlan is present */ 4134 if (tx_flags & IGB_TX_FLAGS_VLAN) 4135 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_VLE); 4136 4137#ifdef CONFIG_IGB_PTP 4138 /* set timestamp bit if present */ 4139 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) 4140 cmd_type |= cpu_to_le32(E1000_ADVTXD_MAC_TSTAMP); 4141#endif /* CONFIG_IGB_PTP */ 4142 4143 /* set segmentation bits for TSO */ 4144 if (tx_flags & IGB_TX_FLAGS_TSO) 4145 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_TSE); 4146 4147 return cmd_type; 4148} 4149 4150static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4151 union e1000_adv_tx_desc *tx_desc, 4152 u32 tx_flags, unsigned int paylen) 4153{ 4154 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4155 4156 /* 82575 requires a unique index per ring if any offload is enabled */ 4157 if ((tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_VLAN)) && 4158 test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4159 olinfo_status |= tx_ring->reg_idx << 4; 4160 4161 /* insert L4 checksum */ 4162 if (tx_flags & IGB_TX_FLAGS_CSUM) { 4163 olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 4164 4165 /* insert IPv4 checksum */ 4166 if (tx_flags & IGB_TX_FLAGS_IPV4) 4167 olinfo_status |= E1000_TXD_POPTS_IXSM << 8; 4168 } 4169 4170 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4171} 4172 4173/* 4174 * The largest size we can write to the descriptor is 65535. In order to 4175 * maintain a power of two alignment we have to limit ourselves to 32K. 4176 */ 4177#define IGB_MAX_TXD_PWR 15 4178#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) 4179 4180static void igb_tx_map(struct igb_ring *tx_ring, 4181 struct igb_tx_buffer *first, 4182 const u8 hdr_len) 4183{ 4184 struct sk_buff *skb = first->skb; 4185 struct igb_tx_buffer *tx_buffer; 4186 union e1000_adv_tx_desc *tx_desc; 4187 dma_addr_t dma; 4188 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 4189 unsigned int data_len = skb->data_len; 4190 unsigned int size = skb_headlen(skb); 4191 unsigned int paylen = skb->len - hdr_len; 4192 __le32 cmd_type; 4193 u32 tx_flags = first->tx_flags; 4194 u16 i = tx_ring->next_to_use; 4195 4196 tx_desc = IGB_TX_DESC(tx_ring, i); 4197 4198 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, paylen); 4199 cmd_type = igb_tx_cmd_type(tx_flags); 4200 4201 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4202 if (dma_mapping_error(tx_ring->dev, dma)) 4203 goto dma_error; 4204 4205 /* record length, and DMA address */ 4206 dma_unmap_len_set(first, len, size); 4207 dma_unmap_addr_set(first, dma, dma); 4208 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4209 4210 for (;;) { 4211 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4212 tx_desc->read.cmd_type_len = 4213 cmd_type | cpu_to_le32(IGB_MAX_DATA_PER_TXD); 4214 4215 i++; 4216 tx_desc++; 4217 if (i == tx_ring->count) { 4218 tx_desc = IGB_TX_DESC(tx_ring, 0); 4219 i = 0; 4220 } 4221 4222 dma += IGB_MAX_DATA_PER_TXD; 4223 size -= IGB_MAX_DATA_PER_TXD; 4224 4225 tx_desc->read.olinfo_status = 0; 4226 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4227 } 4228 4229 if (likely(!data_len)) 4230 break; 4231 4232 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); 4233 4234 i++; 4235 tx_desc++; 4236 if (i == tx_ring->count) { 4237 tx_desc = IGB_TX_DESC(tx_ring, 0); 4238 i = 0; 4239 } 4240 4241 size = skb_frag_size(frag); 4242 data_len -= size; 4243 4244 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4245 size, DMA_TO_DEVICE); 4246 if (dma_mapping_error(tx_ring->dev, dma)) 4247 goto dma_error; 4248 4249 tx_buffer = &tx_ring->tx_buffer_info[i]; 4250 dma_unmap_len_set(tx_buffer, len, size); 4251 dma_unmap_addr_set(tx_buffer, dma, dma); 4252 4253 tx_desc->read.olinfo_status = 0; 4254 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4255 4256 frag++; 4257 } 4258 4259 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4260 4261 /* write last descriptor with RS and EOP bits */ 4262 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IGB_TXD_DCMD); 4263 if (unlikely(skb->no_fcs)) 4264 cmd_type &= ~(cpu_to_le32(E1000_ADVTXD_DCMD_IFCS)); 4265 tx_desc->read.cmd_type_len = cmd_type; 4266 4267 /* set the timestamp */ 4268 first->time_stamp = jiffies; 4269 4270 /* 4271 * Force memory writes to complete before letting h/w know there 4272 * are new descriptors to fetch. (Only applicable for weak-ordered 4273 * memory model archs, such as IA-64). 4274 * 4275 * We also need this memory barrier to make certain all of the 4276 * status bits have been updated before next_to_watch is written. 4277 */ 4278 wmb(); 4279 4280 /* set next_to_watch value indicating a packet is present */ 4281 first->next_to_watch = tx_desc; 4282 4283 i++; 4284 if (i == tx_ring->count) 4285 i = 0; 4286 4287 tx_ring->next_to_use = i; 4288 4289 writel(i, tx_ring->tail); 4290 4291 /* we need this if more than one processor can write to our tail 4292 * at a time, it syncronizes IO on IA64/Altix systems */ 4293 mmiowb(); 4294 4295 return; 4296 4297dma_error: 4298 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4299 4300 /* clear dma mappings for failed tx_buffer_info map */ 4301 for (;;) { 4302 tx_buffer = &tx_ring->tx_buffer_info[i]; 4303 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4304 if (tx_buffer == first) 4305 break; 4306 if (i == 0) 4307 i = tx_ring->count; 4308 i--; 4309 } 4310 4311 tx_ring->next_to_use = i; 4312} 4313 4314static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4315{ 4316 struct net_device *netdev = tx_ring->netdev; 4317 4318 netif_stop_subqueue(netdev, tx_ring->queue_index); 4319 4320 /* Herbert's original patch had: 4321 * smp_mb__after_netif_stop_queue(); 4322 * but since that doesn't exist yet, just open code it. */ 4323 smp_mb(); 4324 4325 /* We need to check again in a case another CPU has just 4326 * made room available. */ 4327 if (igb_desc_unused(tx_ring) < size) 4328 return -EBUSY; 4329 4330 /* A reprieve! */ 4331 netif_wake_subqueue(netdev, tx_ring->queue_index); 4332 4333 u64_stats_update_begin(&tx_ring->tx_syncp2); 4334 tx_ring->tx_stats.restart_queue2++; 4335 u64_stats_update_end(&tx_ring->tx_syncp2); 4336 4337 return 0; 4338} 4339 4340static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4341{ 4342 if (igb_desc_unused(tx_ring) >= size) 4343 return 0; 4344 return __igb_maybe_stop_tx(tx_ring, size); 4345} 4346 4347netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4348 struct igb_ring *tx_ring) 4349{ 4350#ifdef CONFIG_IGB_PTP 4351 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 4352#endif /* CONFIG_IGB_PTP */ 4353 struct igb_tx_buffer *first; 4354 int tso; 4355 u32 tx_flags = 0; 4356 __be16 protocol = vlan_get_protocol(skb); 4357 u8 hdr_len = 0; 4358 4359 /* need: 1 descriptor per page, 4360 * + 2 desc gap to keep tail from touching head, 4361 * + 1 desc for skb->data, 4362 * + 1 desc for context descriptor, 4363 * otherwise try next time */ 4364 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) { 4365 /* this is a hard error */ 4366 return NETDEV_TX_BUSY; 4367 } 4368 4369 /* record the location of the first descriptor for this packet */ 4370 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 4371 first->skb = skb; 4372 first->bytecount = skb->len; 4373 first->gso_segs = 1; 4374 4375#ifdef CONFIG_IGB_PTP 4376 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4377 !(adapter->ptp_tx_skb))) { 4378 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4379 tx_flags |= IGB_TX_FLAGS_TSTAMP; 4380 4381 adapter->ptp_tx_skb = skb_get(skb); 4382 if (adapter->hw.mac.type == e1000_82576) 4383 schedule_work(&adapter->ptp_tx_work); 4384 } 4385#endif /* CONFIG_IGB_PTP */ 4386 4387 if (vlan_tx_tag_present(skb)) { 4388 tx_flags |= IGB_TX_FLAGS_VLAN; 4389 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 4390 } 4391 4392 /* record initial flags and protocol */ 4393 first->tx_flags = tx_flags; 4394 first->protocol = protocol; 4395 4396 tso = igb_tso(tx_ring, first, &hdr_len); 4397 if (tso < 0) 4398 goto out_drop; 4399 else if (!tso) 4400 igb_tx_csum(tx_ring, first); 4401 4402 igb_tx_map(tx_ring, first, hdr_len); 4403 4404 /* Make sure there is space in the ring for the next send. */ 4405 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4); 4406 4407 return NETDEV_TX_OK; 4408 4409out_drop: 4410 igb_unmap_and_free_tx_resource(tx_ring, first); 4411 4412 return NETDEV_TX_OK; 4413} 4414 4415static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 4416 struct sk_buff *skb) 4417{ 4418 unsigned int r_idx = skb->queue_mapping; 4419 4420 if (r_idx >= adapter->num_tx_queues) 4421 r_idx = r_idx % adapter->num_tx_queues; 4422 4423 return adapter->tx_ring[r_idx]; 4424} 4425 4426static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 4427 struct net_device *netdev) 4428{ 4429 struct igb_adapter *adapter = netdev_priv(netdev); 4430 4431 if (test_bit(__IGB_DOWN, &adapter->state)) { 4432 dev_kfree_skb_any(skb); 4433 return NETDEV_TX_OK; 4434 } 4435 4436 if (skb->len <= 0) { 4437 dev_kfree_skb_any(skb); 4438 return NETDEV_TX_OK; 4439 } 4440 4441 /* 4442 * The minimum packet size with TCTL.PSP set is 17 so pad the skb 4443 * in order to meet this minimum size requirement. 4444 */ 4445 if (unlikely(skb->len < 17)) { 4446 if (skb_pad(skb, 17 - skb->len)) 4447 return NETDEV_TX_OK; 4448 skb->len = 17; 4449 skb_set_tail_pointer(skb, 17); 4450 } 4451 4452 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 4453} 4454 4455/** 4456 * igb_tx_timeout - Respond to a Tx Hang 4457 * @netdev: network interface device structure 4458 **/ 4459static void igb_tx_timeout(struct net_device *netdev) 4460{ 4461 struct igb_adapter *adapter = netdev_priv(netdev); 4462 struct e1000_hw *hw = &adapter->hw; 4463 4464 /* Do the reset outside of interrupt context */ 4465 adapter->tx_timeout_count++; 4466 4467 if (hw->mac.type >= e1000_82580) 4468 hw->dev_spec._82575.global_device_reset = true; 4469 4470 schedule_work(&adapter->reset_task); 4471 wr32(E1000_EICS, 4472 (adapter->eims_enable_mask & ~adapter->eims_other)); 4473} 4474 4475static void igb_reset_task(struct work_struct *work) 4476{ 4477 struct igb_adapter *adapter; 4478 adapter = container_of(work, struct igb_adapter, reset_task); 4479 4480 igb_dump(adapter); 4481 netdev_err(adapter->netdev, "Reset adapter\n"); 4482 igb_reinit_locked(adapter); 4483} 4484 4485/** 4486 * igb_get_stats64 - Get System Network Statistics 4487 * @netdev: network interface device structure 4488 * @stats: rtnl_link_stats64 pointer 4489 * 4490 **/ 4491static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 4492 struct rtnl_link_stats64 *stats) 4493{ 4494 struct igb_adapter *adapter = netdev_priv(netdev); 4495 4496 spin_lock(&adapter->stats64_lock); 4497 igb_update_stats(adapter, &adapter->stats64); 4498 memcpy(stats, &adapter->stats64, sizeof(*stats)); 4499 spin_unlock(&adapter->stats64_lock); 4500 4501 return stats; 4502} 4503 4504/** 4505 * igb_change_mtu - Change the Maximum Transfer Unit 4506 * @netdev: network interface device structure 4507 * @new_mtu: new value for maximum frame size 4508 * 4509 * Returns 0 on success, negative on failure 4510 **/ 4511static int igb_change_mtu(struct net_device *netdev, int new_mtu) 4512{ 4513 struct igb_adapter *adapter = netdev_priv(netdev); 4514 struct pci_dev *pdev = adapter->pdev; 4515 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 4516 4517 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 4518 dev_err(&pdev->dev, "Invalid MTU setting\n"); 4519 return -EINVAL; 4520 } 4521 4522#define MAX_STD_JUMBO_FRAME_SIZE 9238 4523 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 4524 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 4525 return -EINVAL; 4526 } 4527 4528 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 4529 msleep(1); 4530 4531 /* igb_down has a dependency on max_frame_size */ 4532 adapter->max_frame_size = max_frame; 4533 4534 if (netif_running(netdev)) 4535 igb_down(adapter); 4536 4537 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 4538 netdev->mtu, new_mtu); 4539 netdev->mtu = new_mtu; 4540 4541 if (netif_running(netdev)) 4542 igb_up(adapter); 4543 else 4544 igb_reset(adapter); 4545 4546 clear_bit(__IGB_RESETTING, &adapter->state); 4547 4548 return 0; 4549} 4550 4551/** 4552 * igb_update_stats - Update the board statistics counters 4553 * @adapter: board private structure 4554 **/ 4555 4556void igb_update_stats(struct igb_adapter *adapter, 4557 struct rtnl_link_stats64 *net_stats) 4558{ 4559 struct e1000_hw *hw = &adapter->hw; 4560 struct pci_dev *pdev = adapter->pdev; 4561 u32 reg, mpc; 4562 u16 phy_tmp; 4563 int i; 4564 u64 bytes, packets; 4565 unsigned int start; 4566 u64 _bytes, _packets; 4567 4568#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF 4569 4570 /* 4571 * Prevent stats update while adapter is being reset, or if the pci 4572 * connection is down. 4573 */ 4574 if (adapter->link_speed == 0) 4575 return; 4576 if (pci_channel_offline(pdev)) 4577 return; 4578 4579 bytes = 0; 4580 packets = 0; 4581 for (i = 0; i < adapter->num_rx_queues; i++) { 4582 u32 rqdpc = rd32(E1000_RQDPC(i)); 4583 struct igb_ring *ring = adapter->rx_ring[i]; 4584 4585 if (rqdpc) { 4586 ring->rx_stats.drops += rqdpc; 4587 net_stats->rx_fifo_errors += rqdpc; 4588 } 4589 4590 do { 4591 start = u64_stats_fetch_begin_bh(&ring->rx_syncp); 4592 _bytes = ring->rx_stats.bytes; 4593 _packets = ring->rx_stats.packets; 4594 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); 4595 bytes += _bytes; 4596 packets += _packets; 4597 } 4598 4599 net_stats->rx_bytes = bytes; 4600 net_stats->rx_packets = packets; 4601 4602 bytes = 0; 4603 packets = 0; 4604 for (i = 0; i < adapter->num_tx_queues; i++) { 4605 struct igb_ring *ring = adapter->tx_ring[i]; 4606 do { 4607 start = u64_stats_fetch_begin_bh(&ring->tx_syncp); 4608 _bytes = ring->tx_stats.bytes; 4609 _packets = ring->tx_stats.packets; 4610 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); 4611 bytes += _bytes; 4612 packets += _packets; 4613 } 4614 net_stats->tx_bytes = bytes; 4615 net_stats->tx_packets = packets; 4616 4617 /* read stats registers */ 4618 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 4619 adapter->stats.gprc += rd32(E1000_GPRC); 4620 adapter->stats.gorc += rd32(E1000_GORCL); 4621 rd32(E1000_GORCH); /* clear GORCL */ 4622 adapter->stats.bprc += rd32(E1000_BPRC); 4623 adapter->stats.mprc += rd32(E1000_MPRC); 4624 adapter->stats.roc += rd32(E1000_ROC); 4625 4626 adapter->stats.prc64 += rd32(E1000_PRC64); 4627 adapter->stats.prc127 += rd32(E1000_PRC127); 4628 adapter->stats.prc255 += rd32(E1000_PRC255); 4629 adapter->stats.prc511 += rd32(E1000_PRC511); 4630 adapter->stats.prc1023 += rd32(E1000_PRC1023); 4631 adapter->stats.prc1522 += rd32(E1000_PRC1522); 4632 adapter->stats.symerrs += rd32(E1000_SYMERRS); 4633 adapter->stats.sec += rd32(E1000_SEC); 4634 4635 mpc = rd32(E1000_MPC); 4636 adapter->stats.mpc += mpc; 4637 net_stats->rx_fifo_errors += mpc; 4638 adapter->stats.scc += rd32(E1000_SCC); 4639 adapter->stats.ecol += rd32(E1000_ECOL); 4640 adapter->stats.mcc += rd32(E1000_MCC); 4641 adapter->stats.latecol += rd32(E1000_LATECOL); 4642 adapter->stats.dc += rd32(E1000_DC); 4643 adapter->stats.rlec += rd32(E1000_RLEC); 4644 adapter->stats.xonrxc += rd32(E1000_XONRXC); 4645 adapter->stats.xontxc += rd32(E1000_XONTXC); 4646 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 4647 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 4648 adapter->stats.fcruc += rd32(E1000_FCRUC); 4649 adapter->stats.gptc += rd32(E1000_GPTC); 4650 adapter->stats.gotc += rd32(E1000_GOTCL); 4651 rd32(E1000_GOTCH); /* clear GOTCL */ 4652 adapter->stats.rnbc += rd32(E1000_RNBC); 4653 adapter->stats.ruc += rd32(E1000_RUC); 4654 adapter->stats.rfc += rd32(E1000_RFC); 4655 adapter->stats.rjc += rd32(E1000_RJC); 4656 adapter->stats.tor += rd32(E1000_TORH); 4657 adapter->stats.tot += rd32(E1000_TOTH); 4658 adapter->stats.tpr += rd32(E1000_TPR); 4659 4660 adapter->stats.ptc64 += rd32(E1000_PTC64); 4661 adapter->stats.ptc127 += rd32(E1000_PTC127); 4662 adapter->stats.ptc255 += rd32(E1000_PTC255); 4663 adapter->stats.ptc511 += rd32(E1000_PTC511); 4664 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 4665 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 4666 4667 adapter->stats.mptc += rd32(E1000_MPTC); 4668 adapter->stats.bptc += rd32(E1000_BPTC); 4669 4670 adapter->stats.tpt += rd32(E1000_TPT); 4671 adapter->stats.colc += rd32(E1000_COLC); 4672 4673 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 4674 /* read internal phy specific stats */ 4675 reg = rd32(E1000_CTRL_EXT); 4676 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 4677 adapter->stats.rxerrc += rd32(E1000_RXERRC); 4678 4679 /* this stat has invalid values on i210/i211 */ 4680 if ((hw->mac.type != e1000_i210) && 4681 (hw->mac.type != e1000_i211)) 4682 adapter->stats.tncrs += rd32(E1000_TNCRS); 4683 } 4684 4685 adapter->stats.tsctc += rd32(E1000_TSCTC); 4686 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 4687 4688 adapter->stats.iac += rd32(E1000_IAC); 4689 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 4690 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 4691 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 4692 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 4693 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 4694 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 4695 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 4696 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 4697 4698 /* Fill out the OS statistics structure */ 4699 net_stats->multicast = adapter->stats.mprc; 4700 net_stats->collisions = adapter->stats.colc; 4701 4702 /* Rx Errors */ 4703 4704 /* RLEC on some newer hardware can be incorrect so build 4705 * our own version based on RUC and ROC */ 4706 net_stats->rx_errors = adapter->stats.rxerrc + 4707 adapter->stats.crcerrs + adapter->stats.algnerrc + 4708 adapter->stats.ruc + adapter->stats.roc + 4709 adapter->stats.cexterr; 4710 net_stats->rx_length_errors = adapter->stats.ruc + 4711 adapter->stats.roc; 4712 net_stats->rx_crc_errors = adapter->stats.crcerrs; 4713 net_stats->rx_frame_errors = adapter->stats.algnerrc; 4714 net_stats->rx_missed_errors = adapter->stats.mpc; 4715 4716 /* Tx Errors */ 4717 net_stats->tx_errors = adapter->stats.ecol + 4718 adapter->stats.latecol; 4719 net_stats->tx_aborted_errors = adapter->stats.ecol; 4720 net_stats->tx_window_errors = adapter->stats.latecol; 4721 net_stats->tx_carrier_errors = adapter->stats.tncrs; 4722 4723 /* Tx Dropped needs to be maintained elsewhere */ 4724 4725 /* Phy Stats */ 4726 if (hw->phy.media_type == e1000_media_type_copper) { 4727 if ((adapter->link_speed == SPEED_1000) && 4728 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 4729 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; 4730 adapter->phy_stats.idle_errors += phy_tmp; 4731 } 4732 } 4733 4734 /* Management Stats */ 4735 adapter->stats.mgptc += rd32(E1000_MGTPTC); 4736 adapter->stats.mgprc += rd32(E1000_MGTPRC); 4737 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 4738 4739 /* OS2BMC Stats */ 4740 reg = rd32(E1000_MANC); 4741 if (reg & E1000_MANC_EN_BMC2OS) { 4742 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 4743 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 4744 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 4745 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 4746 } 4747} 4748 4749static irqreturn_t igb_msix_other(int irq, void *data) 4750{ 4751 struct igb_adapter *adapter = data; 4752 struct e1000_hw *hw = &adapter->hw; 4753 u32 icr = rd32(E1000_ICR); 4754 /* reading ICR causes bit 31 of EICR to be cleared */ 4755 4756 if (icr & E1000_ICR_DRSTA) 4757 schedule_work(&adapter->reset_task); 4758 4759 if (icr & E1000_ICR_DOUTSYNC) { 4760 /* HW is reporting DMA is out of sync */ 4761 adapter->stats.doosync++; 4762 /* The DMA Out of Sync is also indication of a spoof event 4763 * in IOV mode. Check the Wrong VM Behavior register to 4764 * see if it is really a spoof event. */ 4765 igb_check_wvbr(adapter); 4766 } 4767 4768 /* Check for a mailbox event */ 4769 if (icr & E1000_ICR_VMMB) 4770 igb_msg_task(adapter); 4771 4772 if (icr & E1000_ICR_LSC) { 4773 hw->mac.get_link_status = 1; 4774 /* guard against interrupt when we're going down */ 4775 if (!test_bit(__IGB_DOWN, &adapter->state)) 4776 mod_timer(&adapter->watchdog_timer, jiffies + 1); 4777 } 4778 4779#ifdef CONFIG_IGB_PTP 4780 if (icr & E1000_ICR_TS) { 4781 u32 tsicr = rd32(E1000_TSICR); 4782 4783 if (tsicr & E1000_TSICR_TXTS) { 4784 /* acknowledge the interrupt */ 4785 wr32(E1000_TSICR, E1000_TSICR_TXTS); 4786 /* retrieve hardware timestamp */ 4787 schedule_work(&adapter->ptp_tx_work); 4788 } 4789 } 4790#endif /* CONFIG_IGB_PTP */ 4791 4792 wr32(E1000_EIMS, adapter->eims_other); 4793 4794 return IRQ_HANDLED; 4795} 4796 4797static void igb_write_itr(struct igb_q_vector *q_vector) 4798{ 4799 struct igb_adapter *adapter = q_vector->adapter; 4800 u32 itr_val = q_vector->itr_val & 0x7FFC; 4801 4802 if (!q_vector->set_itr) 4803 return; 4804 4805 if (!itr_val) 4806 itr_val = 0x4; 4807 4808 if (adapter->hw.mac.type == e1000_82575) 4809 itr_val |= itr_val << 16; 4810 else 4811 itr_val |= E1000_EITR_CNT_IGNR; 4812 4813 writel(itr_val, q_vector->itr_register); 4814 q_vector->set_itr = 0; 4815} 4816 4817static irqreturn_t igb_msix_ring(int irq, void *data) 4818{ 4819 struct igb_q_vector *q_vector = data; 4820 4821 /* Write the ITR value calculated from the previous interrupt. */ 4822 igb_write_itr(q_vector); 4823 4824 napi_schedule(&q_vector->napi); 4825 4826 return IRQ_HANDLED; 4827} 4828 4829#ifdef CONFIG_IGB_DCA 4830static void igb_update_tx_dca(struct igb_adapter *adapter, 4831 struct igb_ring *tx_ring, 4832 int cpu) 4833{ 4834 struct e1000_hw *hw = &adapter->hw; 4835 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 4836 4837 if (hw->mac.type != e1000_82575) 4838 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 4839 4840 /* 4841 * We can enable relaxed ordering for reads, but not writes when 4842 * DCA is enabled. This is due to a known issue in some chipsets 4843 * which will cause the DCA tag to be cleared. 4844 */ 4845 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 4846 E1000_DCA_TXCTRL_DATA_RRO_EN | 4847 E1000_DCA_TXCTRL_DESC_DCA_EN; 4848 4849 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 4850} 4851 4852static void igb_update_rx_dca(struct igb_adapter *adapter, 4853 struct igb_ring *rx_ring, 4854 int cpu) 4855{ 4856 struct e1000_hw *hw = &adapter->hw; 4857 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 4858 4859 if (hw->mac.type != e1000_82575) 4860 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 4861 4862 /* 4863 * We can enable relaxed ordering for reads, but not writes when 4864 * DCA is enabled. This is due to a known issue in some chipsets 4865 * which will cause the DCA tag to be cleared. 4866 */ 4867 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 4868 E1000_DCA_RXCTRL_DESC_DCA_EN; 4869 4870 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 4871} 4872 4873static void igb_update_dca(struct igb_q_vector *q_vector) 4874{ 4875 struct igb_adapter *adapter = q_vector->adapter; 4876 int cpu = get_cpu(); 4877 4878 if (q_vector->cpu == cpu) 4879 goto out_no_update; 4880 4881 if (q_vector->tx.ring) 4882 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 4883 4884 if (q_vector->rx.ring) 4885 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 4886 4887 q_vector->cpu = cpu; 4888out_no_update: 4889 put_cpu(); 4890} 4891 4892static void igb_setup_dca(struct igb_adapter *adapter) 4893{ 4894 struct e1000_hw *hw = &adapter->hw; 4895 int i; 4896 4897 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 4898 return; 4899 4900 /* Always use CB2 mode, difference is masked in the CB driver. */ 4901 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 4902 4903 for (i = 0; i < adapter->num_q_vectors; i++) { 4904 adapter->q_vector[i]->cpu = -1; 4905 igb_update_dca(adapter->q_vector[i]); 4906 } 4907} 4908 4909static int __igb_notify_dca(struct device *dev, void *data) 4910{ 4911 struct net_device *netdev = dev_get_drvdata(dev); 4912 struct igb_adapter *adapter = netdev_priv(netdev); 4913 struct pci_dev *pdev = adapter->pdev; 4914 struct e1000_hw *hw = &adapter->hw; 4915 unsigned long event = *(unsigned long *)data; 4916 4917 switch (event) { 4918 case DCA_PROVIDER_ADD: 4919 /* if already enabled, don't do it again */ 4920 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 4921 break; 4922 if (dca_add_requester(dev) == 0) { 4923 adapter->flags |= IGB_FLAG_DCA_ENABLED; 4924 dev_info(&pdev->dev, "DCA enabled\n"); 4925 igb_setup_dca(adapter); 4926 break; 4927 } 4928 /* Fall Through since DCA is disabled. */ 4929 case DCA_PROVIDER_REMOVE: 4930 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 4931 /* without this a class_device is left 4932 * hanging around in the sysfs model */ 4933 dca_remove_requester(dev); 4934 dev_info(&pdev->dev, "DCA disabled\n"); 4935 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 4936 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 4937 } 4938 break; 4939 } 4940 4941 return 0; 4942} 4943 4944static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 4945 void *p) 4946{ 4947 int ret_val; 4948 4949 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 4950 __igb_notify_dca); 4951 4952 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 4953} 4954#endif /* CONFIG_IGB_DCA */ 4955 4956#ifdef CONFIG_PCI_IOV 4957static int igb_vf_configure(struct igb_adapter *adapter, int vf) 4958{ 4959 unsigned char mac_addr[ETH_ALEN]; 4960 4961 eth_random_addr(mac_addr); 4962 igb_set_vf_mac(adapter, vf, mac_addr); 4963 4964 return 0; 4965} 4966 4967static bool igb_vfs_are_assigned(struct igb_adapter *adapter) 4968{ 4969 struct pci_dev *pdev = adapter->pdev; 4970 struct pci_dev *vfdev; 4971 int dev_id; 4972 4973 switch (adapter->hw.mac.type) { 4974 case e1000_82576: 4975 dev_id = IGB_82576_VF_DEV_ID; 4976 break; 4977 case e1000_i350: 4978 dev_id = IGB_I350_VF_DEV_ID; 4979 break; 4980 default: 4981 return false; 4982 } 4983 4984 /* loop through all the VFs to see if we own any that are assigned */ 4985 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL); 4986 while (vfdev) { 4987 /* if we don't own it we don't care */ 4988 if (vfdev->is_virtfn && vfdev->physfn == pdev) { 4989 /* if it is assigned we cannot release it */ 4990 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) 4991 return true; 4992 } 4993 4994 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev); 4995 } 4996 4997 return false; 4998} 4999 5000#endif 5001static void igb_ping_all_vfs(struct igb_adapter *adapter) 5002{ 5003 struct e1000_hw *hw = &adapter->hw; 5004 u32 ping; 5005 int i; 5006 5007 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5008 ping = E1000_PF_CONTROL_MSG; 5009 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5010 ping |= E1000_VT_MSGTYPE_CTS; 5011 igb_write_mbx(hw, &ping, 1, i); 5012 } 5013} 5014 5015static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5016{ 5017 struct e1000_hw *hw = &adapter->hw; 5018 u32 vmolr = rd32(E1000_VMOLR(vf)); 5019 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5020 5021 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5022 IGB_VF_FLAG_MULTI_PROMISC); 5023 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5024 5025 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5026 vmolr |= E1000_VMOLR_MPME; 5027 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5028 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5029 } else { 5030 /* 5031 * if we have hashes and we are clearing a multicast promisc 5032 * flag we need to write the hashes to the MTA as this step 5033 * was previously skipped 5034 */ 5035 if (vf_data->num_vf_mc_hashes > 30) { 5036 vmolr |= E1000_VMOLR_MPME; 5037 } else if (vf_data->num_vf_mc_hashes) { 5038 int j; 5039 vmolr |= E1000_VMOLR_ROMPE; 5040 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5041 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5042 } 5043 } 5044 5045 wr32(E1000_VMOLR(vf), vmolr); 5046 5047 /* there are flags left unprocessed, likely not supported */ 5048 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5049 return -EINVAL; 5050 5051 return 0; 5052 5053} 5054 5055static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5056 u32 *msgbuf, u32 vf) 5057{ 5058 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5059 u16 *hash_list = (u16 *)&msgbuf[1]; 5060 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5061 int i; 5062 5063 /* salt away the number of multicast addresses assigned 5064 * to this VF for later use to restore when the PF multi cast 5065 * list changes 5066 */ 5067 vf_data->num_vf_mc_hashes = n; 5068 5069 /* only up to 30 hash values supported */ 5070 if (n > 30) 5071 n = 30; 5072 5073 /* store the hashes for later use */ 5074 for (i = 0; i < n; i++) 5075 vf_data->vf_mc_hashes[i] = hash_list[i]; 5076 5077 /* Flush and reset the mta with the new values */ 5078 igb_set_rx_mode(adapter->netdev); 5079 5080 return 0; 5081} 5082 5083static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5084{ 5085 struct e1000_hw *hw = &adapter->hw; 5086 struct vf_data_storage *vf_data; 5087 int i, j; 5088 5089 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5090 u32 vmolr = rd32(E1000_VMOLR(i)); 5091 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5092 5093 vf_data = &adapter->vf_data[i]; 5094 5095 if ((vf_data->num_vf_mc_hashes > 30) || 5096 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5097 vmolr |= E1000_VMOLR_MPME; 5098 } else if (vf_data->num_vf_mc_hashes) { 5099 vmolr |= E1000_VMOLR_ROMPE; 5100 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5101 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5102 } 5103 wr32(E1000_VMOLR(i), vmolr); 5104 } 5105} 5106 5107static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5108{ 5109 struct e1000_hw *hw = &adapter->hw; 5110 u32 pool_mask, reg, vid; 5111 int i; 5112 5113 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5114 5115 /* Find the vlan filter for this id */ 5116 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5117 reg = rd32(E1000_VLVF(i)); 5118 5119 /* remove the vf from the pool */ 5120 reg &= ~pool_mask; 5121 5122 /* if pool is empty then remove entry from vfta */ 5123 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5124 (reg & E1000_VLVF_VLANID_ENABLE)) { 5125 reg = 0; 5126 vid = reg & E1000_VLVF_VLANID_MASK; 5127 igb_vfta_set(hw, vid, false); 5128 } 5129 5130 wr32(E1000_VLVF(i), reg); 5131 } 5132 5133 adapter->vf_data[vf].vlans_enabled = 0; 5134} 5135 5136static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5137{ 5138 struct e1000_hw *hw = &adapter->hw; 5139 u32 reg, i; 5140 5141 /* The vlvf table only exists on 82576 hardware and newer */ 5142 if (hw->mac.type < e1000_82576) 5143 return -1; 5144 5145 /* we only need to do this if VMDq is enabled */ 5146 if (!adapter->vfs_allocated_count) 5147 return -1; 5148 5149 /* Find the vlan filter for this id */ 5150 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5151 reg = rd32(E1000_VLVF(i)); 5152 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5153 vid == (reg & E1000_VLVF_VLANID_MASK)) 5154 break; 5155 } 5156 5157 if (add) { 5158 if (i == E1000_VLVF_ARRAY_SIZE) { 5159 /* Did not find a matching VLAN ID entry that was 5160 * enabled. Search for a free filter entry, i.e. 5161 * one without the enable bit set 5162 */ 5163 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5164 reg = rd32(E1000_VLVF(i)); 5165 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5166 break; 5167 } 5168 } 5169 if (i < E1000_VLVF_ARRAY_SIZE) { 5170 /* Found an enabled/available entry */ 5171 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5172 5173 /* if !enabled we need to set this up in vfta */ 5174 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5175 /* add VID to filter table */ 5176 igb_vfta_set(hw, vid, true); 5177 reg |= E1000_VLVF_VLANID_ENABLE; 5178 } 5179 reg &= ~E1000_VLVF_VLANID_MASK; 5180 reg |= vid; 5181 wr32(E1000_VLVF(i), reg); 5182 5183 /* do not modify RLPML for PF devices */ 5184 if (vf >= adapter->vfs_allocated_count) 5185 return 0; 5186 5187 if (!adapter->vf_data[vf].vlans_enabled) { 5188 u32 size; 5189 reg = rd32(E1000_VMOLR(vf)); 5190 size = reg & E1000_VMOLR_RLPML_MASK; 5191 size += 4; 5192 reg &= ~E1000_VMOLR_RLPML_MASK; 5193 reg |= size; 5194 wr32(E1000_VMOLR(vf), reg); 5195 } 5196 5197 adapter->vf_data[vf].vlans_enabled++; 5198 } 5199 } else { 5200 if (i < E1000_VLVF_ARRAY_SIZE) { 5201 /* remove vf from the pool */ 5202 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5203 /* if pool is empty then remove entry from vfta */ 5204 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5205 reg = 0; 5206 igb_vfta_set(hw, vid, false); 5207 } 5208 wr32(E1000_VLVF(i), reg); 5209 5210 /* do not modify RLPML for PF devices */ 5211 if (vf >= adapter->vfs_allocated_count) 5212 return 0; 5213 5214 adapter->vf_data[vf].vlans_enabled--; 5215 if (!adapter->vf_data[vf].vlans_enabled) { 5216 u32 size; 5217 reg = rd32(E1000_VMOLR(vf)); 5218 size = reg & E1000_VMOLR_RLPML_MASK; 5219 size -= 4; 5220 reg &= ~E1000_VMOLR_RLPML_MASK; 5221 reg |= size; 5222 wr32(E1000_VMOLR(vf), reg); 5223 } 5224 } 5225 } 5226 return 0; 5227} 5228 5229static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5230{ 5231 struct e1000_hw *hw = &adapter->hw; 5232 5233 if (vid) 5234 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5235 else 5236 wr32(E1000_VMVIR(vf), 0); 5237} 5238 5239static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5240 int vf, u16 vlan, u8 qos) 5241{ 5242 int err = 0; 5243 struct igb_adapter *adapter = netdev_priv(netdev); 5244 5245 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5246 return -EINVAL; 5247 if (vlan || qos) { 5248 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5249 if (err) 5250 goto out; 5251 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5252 igb_set_vmolr(adapter, vf, !vlan); 5253 adapter->vf_data[vf].pf_vlan = vlan; 5254 adapter->vf_data[vf].pf_qos = qos; 5255 dev_info(&adapter->pdev->dev, 5256 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5257 if (test_bit(__IGB_DOWN, &adapter->state)) { 5258 dev_warn(&adapter->pdev->dev, 5259 "The VF VLAN has been set," 5260 " but the PF device is not up.\n"); 5261 dev_warn(&adapter->pdev->dev, 5262 "Bring the PF device up before" 5263 " attempting to use the VF device.\n"); 5264 } 5265 } else { 5266 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5267 false, vf); 5268 igb_set_vmvir(adapter, vlan, vf); 5269 igb_set_vmolr(adapter, vf, true); 5270 adapter->vf_data[vf].pf_vlan = 0; 5271 adapter->vf_data[vf].pf_qos = 0; 5272 } 5273out: 5274 return err; 5275} 5276 5277static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5278{ 5279 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5280 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5281 5282 return igb_vlvf_set(adapter, vid, add, vf); 5283} 5284 5285static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 5286{ 5287 /* clear flags - except flag that indicates PF has set the MAC */ 5288 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 5289 adapter->vf_data[vf].last_nack = jiffies; 5290 5291 /* reset offloads to defaults */ 5292 igb_set_vmolr(adapter, vf, true); 5293 5294 /* reset vlans for device */ 5295 igb_clear_vf_vfta(adapter, vf); 5296 if (adapter->vf_data[vf].pf_vlan) 5297 igb_ndo_set_vf_vlan(adapter->netdev, vf, 5298 adapter->vf_data[vf].pf_vlan, 5299 adapter->vf_data[vf].pf_qos); 5300 else 5301 igb_clear_vf_vfta(adapter, vf); 5302 5303 /* reset multicast table array for vf */ 5304 adapter->vf_data[vf].num_vf_mc_hashes = 0; 5305 5306 /* Flush and reset the mta with the new values */ 5307 igb_set_rx_mode(adapter->netdev); 5308} 5309 5310static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 5311{ 5312 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5313 5314 /* generate a new mac address as we were hotplug removed/added */ 5315 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 5316 eth_random_addr(vf_mac); 5317 5318 /* process remaining reset events */ 5319 igb_vf_reset(adapter, vf); 5320} 5321 5322static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 5323{ 5324 struct e1000_hw *hw = &adapter->hw; 5325 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5326 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 5327 u32 reg, msgbuf[3]; 5328 u8 *addr = (u8 *)(&msgbuf[1]); 5329 5330 /* process all the same items cleared in a function level reset */ 5331 igb_vf_reset(adapter, vf); 5332 5333 /* set vf mac address */ 5334 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 5335 5336 /* enable transmit and receive for vf */ 5337 reg = rd32(E1000_VFTE); 5338 wr32(E1000_VFTE, reg | (1 << vf)); 5339 reg = rd32(E1000_VFRE); 5340 wr32(E1000_VFRE, reg | (1 << vf)); 5341 5342 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 5343 5344 /* reply to reset with ack and vf mac address */ 5345 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 5346 memcpy(addr, vf_mac, 6); 5347 igb_write_mbx(hw, msgbuf, 3, vf); 5348} 5349 5350static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 5351{ 5352 /* 5353 * The VF MAC Address is stored in a packed array of bytes 5354 * starting at the second 32 bit word of the msg array 5355 */ 5356 unsigned char *addr = (char *)&msg[1]; 5357 int err = -1; 5358 5359 if (is_valid_ether_addr(addr)) 5360 err = igb_set_vf_mac(adapter, vf, addr); 5361 5362 return err; 5363} 5364 5365static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 5366{ 5367 struct e1000_hw *hw = &adapter->hw; 5368 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5369 u32 msg = E1000_VT_MSGTYPE_NACK; 5370 5371 /* if device isn't clear to send it shouldn't be reading either */ 5372 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 5373 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 5374 igb_write_mbx(hw, &msg, 1, vf); 5375 vf_data->last_nack = jiffies; 5376 } 5377} 5378 5379static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 5380{ 5381 struct pci_dev *pdev = adapter->pdev; 5382 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 5383 struct e1000_hw *hw = &adapter->hw; 5384 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5385 s32 retval; 5386 5387 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 5388 5389 if (retval) { 5390 /* if receive failed revoke VF CTS stats and restart init */ 5391 dev_err(&pdev->dev, "Error receiving message from VF\n"); 5392 vf_data->flags &= ~IGB_VF_FLAG_CTS; 5393 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 5394 return; 5395 goto out; 5396 } 5397 5398 /* this is a message we already processed, do nothing */ 5399 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 5400 return; 5401 5402 /* 5403 * until the vf completes a reset it should not be 5404 * allowed to start any configuration. 5405 */ 5406 5407 if (msgbuf[0] == E1000_VF_RESET) { 5408 igb_vf_reset_msg(adapter, vf); 5409 return; 5410 } 5411 5412 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 5413 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 5414 return; 5415 retval = -1; 5416 goto out; 5417 } 5418 5419 switch ((msgbuf[0] & 0xFFFF)) { 5420 case E1000_VF_SET_MAC_ADDR: 5421 retval = -EINVAL; 5422 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 5423 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 5424 else 5425 dev_warn(&pdev->dev, 5426 "VF %d attempted to override administratively " 5427 "set MAC address\nReload the VF driver to " 5428 "resume operations\n", vf); 5429 break; 5430 case E1000_VF_SET_PROMISC: 5431 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 5432 break; 5433 case E1000_VF_SET_MULTICAST: 5434 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 5435 break; 5436 case E1000_VF_SET_LPE: 5437 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 5438 break; 5439 case E1000_VF_SET_VLAN: 5440 retval = -1; 5441 if (vf_data->pf_vlan) 5442 dev_warn(&pdev->dev, 5443 "VF %d attempted to override administratively " 5444 "set VLAN tag\nReload the VF driver to " 5445 "resume operations\n", vf); 5446 else 5447 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 5448 break; 5449 default: 5450 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 5451 retval = -1; 5452 break; 5453 } 5454 5455 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 5456out: 5457 /* notify the VF of the results of what it sent us */ 5458 if (retval) 5459 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 5460 else 5461 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 5462 5463 igb_write_mbx(hw, msgbuf, 1, vf); 5464} 5465 5466static void igb_msg_task(struct igb_adapter *adapter) 5467{ 5468 struct e1000_hw *hw = &adapter->hw; 5469 u32 vf; 5470 5471 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 5472 /* process any reset requests */ 5473 if (!igb_check_for_rst(hw, vf)) 5474 igb_vf_reset_event(adapter, vf); 5475 5476 /* process any messages pending */ 5477 if (!igb_check_for_msg(hw, vf)) 5478 igb_rcv_msg_from_vf(adapter, vf); 5479 5480 /* process any acks */ 5481 if (!igb_check_for_ack(hw, vf)) 5482 igb_rcv_ack_from_vf(adapter, vf); 5483 } 5484} 5485 5486/** 5487 * igb_set_uta - Set unicast filter table address 5488 * @adapter: board private structure 5489 * 5490 * The unicast table address is a register array of 32-bit registers. 5491 * The table is meant to be used in a way similar to how the MTA is used 5492 * however due to certain limitations in the hardware it is necessary to 5493 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 5494 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 5495 **/ 5496static void igb_set_uta(struct igb_adapter *adapter) 5497{ 5498 struct e1000_hw *hw = &adapter->hw; 5499 int i; 5500 5501 /* The UTA table only exists on 82576 hardware and newer */ 5502 if (hw->mac.type < e1000_82576) 5503 return; 5504 5505 /* we only need to do this if VMDq is enabled */ 5506 if (!adapter->vfs_allocated_count) 5507 return; 5508 5509 for (i = 0; i < hw->mac.uta_reg_count; i++) 5510 array_wr32(E1000_UTA, i, ~0); 5511} 5512 5513/** 5514 * igb_intr_msi - Interrupt Handler 5515 * @irq: interrupt number 5516 * @data: pointer to a network interface device structure 5517 **/ 5518static irqreturn_t igb_intr_msi(int irq, void *data) 5519{ 5520 struct igb_adapter *adapter = data; 5521 struct igb_q_vector *q_vector = adapter->q_vector[0]; 5522 struct e1000_hw *hw = &adapter->hw; 5523 /* read ICR disables interrupts using IAM */ 5524 u32 icr = rd32(E1000_ICR); 5525 5526 igb_write_itr(q_vector); 5527 5528 if (icr & E1000_ICR_DRSTA) 5529 schedule_work(&adapter->reset_task); 5530 5531 if (icr & E1000_ICR_DOUTSYNC) { 5532 /* HW is reporting DMA is out of sync */ 5533 adapter->stats.doosync++; 5534 } 5535 5536 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 5537 hw->mac.get_link_status = 1; 5538 if (!test_bit(__IGB_DOWN, &adapter->state)) 5539 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5540 } 5541 5542#ifdef CONFIG_IGB_PTP 5543 if (icr & E1000_ICR_TS) { 5544 u32 tsicr = rd32(E1000_TSICR); 5545 5546 if (tsicr & E1000_TSICR_TXTS) { 5547 /* acknowledge the interrupt */ 5548 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5549 /* retrieve hardware timestamp */ 5550 schedule_work(&adapter->ptp_tx_work); 5551 } 5552 } 5553#endif /* CONFIG_IGB_PTP */ 5554 5555 napi_schedule(&q_vector->napi); 5556 5557 return IRQ_HANDLED; 5558} 5559 5560/** 5561 * igb_intr - Legacy Interrupt Handler 5562 * @irq: interrupt number 5563 * @data: pointer to a network interface device structure 5564 **/ 5565static irqreturn_t igb_intr(int irq, void *data) 5566{ 5567 struct igb_adapter *adapter = data; 5568 struct igb_q_vector *q_vector = adapter->q_vector[0]; 5569 struct e1000_hw *hw = &adapter->hw; 5570 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 5571 * need for the IMC write */ 5572 u32 icr = rd32(E1000_ICR); 5573 5574 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 5575 * not set, then the adapter didn't send an interrupt */ 5576 if (!(icr & E1000_ICR_INT_ASSERTED)) 5577 return IRQ_NONE; 5578 5579 igb_write_itr(q_vector); 5580 5581 if (icr & E1000_ICR_DRSTA) 5582 schedule_work(&adapter->reset_task); 5583 5584 if (icr & E1000_ICR_DOUTSYNC) { 5585 /* HW is reporting DMA is out of sync */ 5586 adapter->stats.doosync++; 5587 } 5588 5589 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 5590 hw->mac.get_link_status = 1; 5591 /* guard against interrupt when we're going down */ 5592 if (!test_bit(__IGB_DOWN, &adapter->state)) 5593 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5594 } 5595 5596#ifdef CONFIG_IGB_PTP 5597 if (icr & E1000_ICR_TS) { 5598 u32 tsicr = rd32(E1000_TSICR); 5599 5600 if (tsicr & E1000_TSICR_TXTS) { 5601 /* acknowledge the interrupt */ 5602 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5603 /* retrieve hardware timestamp */ 5604 schedule_work(&adapter->ptp_tx_work); 5605 } 5606 } 5607#endif /* CONFIG_IGB_PTP */ 5608 5609 napi_schedule(&q_vector->napi); 5610 5611 return IRQ_HANDLED; 5612} 5613 5614static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 5615{ 5616 struct igb_adapter *adapter = q_vector->adapter; 5617 struct e1000_hw *hw = &adapter->hw; 5618 5619 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 5620 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 5621 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 5622 igb_set_itr(q_vector); 5623 else 5624 igb_update_ring_itr(q_vector); 5625 } 5626 5627 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5628 if (adapter->msix_entries) 5629 wr32(E1000_EIMS, q_vector->eims_value); 5630 else 5631 igb_irq_enable(adapter); 5632 } 5633} 5634 5635/** 5636 * igb_poll - NAPI Rx polling callback 5637 * @napi: napi polling structure 5638 * @budget: count of how many packets we should handle 5639 **/ 5640static int igb_poll(struct napi_struct *napi, int budget) 5641{ 5642 struct igb_q_vector *q_vector = container_of(napi, 5643 struct igb_q_vector, 5644 napi); 5645 bool clean_complete = true; 5646 5647#ifdef CONFIG_IGB_DCA 5648 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 5649 igb_update_dca(q_vector); 5650#endif 5651 if (q_vector->tx.ring) 5652 clean_complete = igb_clean_tx_irq(q_vector); 5653 5654 if (q_vector->rx.ring) 5655 clean_complete &= igb_clean_rx_irq(q_vector, budget); 5656 5657 /* If all work not completed, return budget and keep polling */ 5658 if (!clean_complete) 5659 return budget; 5660 5661 /* If not enough Rx work done, exit the polling mode */ 5662 napi_complete(napi); 5663 igb_ring_irq_enable(q_vector); 5664 5665 return 0; 5666} 5667 5668/** 5669 * igb_clean_tx_irq - Reclaim resources after transmit completes 5670 * @q_vector: pointer to q_vector containing needed info 5671 * 5672 * returns true if ring is completely cleaned 5673 **/ 5674static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 5675{ 5676 struct igb_adapter *adapter = q_vector->adapter; 5677 struct igb_ring *tx_ring = q_vector->tx.ring; 5678 struct igb_tx_buffer *tx_buffer; 5679 union e1000_adv_tx_desc *tx_desc; 5680 unsigned int total_bytes = 0, total_packets = 0; 5681 unsigned int budget = q_vector->tx.work_limit; 5682 unsigned int i = tx_ring->next_to_clean; 5683 5684 if (test_bit(__IGB_DOWN, &adapter->state)) 5685 return true; 5686 5687 tx_buffer = &tx_ring->tx_buffer_info[i]; 5688 tx_desc = IGB_TX_DESC(tx_ring, i); 5689 i -= tx_ring->count; 5690 5691 do { 5692 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 5693 5694 /* if next_to_watch is not set then there is no work pending */ 5695 if (!eop_desc) 5696 break; 5697 5698 /* prevent any other reads prior to eop_desc */ 5699 rmb(); 5700 5701 /* if DD is not set pending work has not been completed */ 5702 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 5703 break; 5704 5705 /* clear next_to_watch to prevent false hangs */ 5706 tx_buffer->next_to_watch = NULL; 5707 5708 /* update the statistics for this packet */ 5709 total_bytes += tx_buffer->bytecount; 5710 total_packets += tx_buffer->gso_segs; 5711 5712 /* free the skb */ 5713 dev_kfree_skb_any(tx_buffer->skb); 5714 5715 /* unmap skb header data */ 5716 dma_unmap_single(tx_ring->dev, 5717 dma_unmap_addr(tx_buffer, dma), 5718 dma_unmap_len(tx_buffer, len), 5719 DMA_TO_DEVICE); 5720 5721 /* clear tx_buffer data */ 5722 tx_buffer->skb = NULL; 5723 dma_unmap_len_set(tx_buffer, len, 0); 5724 5725 /* clear last DMA location and unmap remaining buffers */ 5726 while (tx_desc != eop_desc) { 5727 tx_buffer++; 5728 tx_desc++; 5729 i++; 5730 if (unlikely(!i)) { 5731 i -= tx_ring->count; 5732 tx_buffer = tx_ring->tx_buffer_info; 5733 tx_desc = IGB_TX_DESC(tx_ring, 0); 5734 } 5735 5736 /* unmap any remaining paged data */ 5737 if (dma_unmap_len(tx_buffer, len)) { 5738 dma_unmap_page(tx_ring->dev, 5739 dma_unmap_addr(tx_buffer, dma), 5740 dma_unmap_len(tx_buffer, len), 5741 DMA_TO_DEVICE); 5742 dma_unmap_len_set(tx_buffer, len, 0); 5743 } 5744 } 5745 5746 /* move us one more past the eop_desc for start of next pkt */ 5747 tx_buffer++; 5748 tx_desc++; 5749 i++; 5750 if (unlikely(!i)) { 5751 i -= tx_ring->count; 5752 tx_buffer = tx_ring->tx_buffer_info; 5753 tx_desc = IGB_TX_DESC(tx_ring, 0); 5754 } 5755 5756 /* issue prefetch for next Tx descriptor */ 5757 prefetch(tx_desc); 5758 5759 /* update budget accounting */ 5760 budget--; 5761 } while (likely(budget)); 5762 5763 netdev_tx_completed_queue(txring_txq(tx_ring), 5764 total_packets, total_bytes); 5765 i += tx_ring->count; 5766 tx_ring->next_to_clean = i; 5767 u64_stats_update_begin(&tx_ring->tx_syncp); 5768 tx_ring->tx_stats.bytes += total_bytes; 5769 tx_ring->tx_stats.packets += total_packets; 5770 u64_stats_update_end(&tx_ring->tx_syncp); 5771 q_vector->tx.total_bytes += total_bytes; 5772 q_vector->tx.total_packets += total_packets; 5773 5774 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 5775 struct e1000_hw *hw = &adapter->hw; 5776 5777 /* Detect a transmit hang in hardware, this serializes the 5778 * check with the clearing of time_stamp and movement of i */ 5779 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5780 if (tx_buffer->next_to_watch && 5781 time_after(jiffies, tx_buffer->time_stamp + 5782 (adapter->tx_timeout_factor * HZ)) && 5783 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 5784 5785 /* detected Tx unit hang */ 5786 dev_err(tx_ring->dev, 5787 "Detected Tx Unit Hang\n" 5788 " Tx Queue <%d>\n" 5789 " TDH <%x>\n" 5790 " TDT <%x>\n" 5791 " next_to_use <%x>\n" 5792 " next_to_clean <%x>\n" 5793 "buffer_info[next_to_clean]\n" 5794 " time_stamp <%lx>\n" 5795 " next_to_watch <%p>\n" 5796 " jiffies <%lx>\n" 5797 " desc.status <%x>\n", 5798 tx_ring->queue_index, 5799 rd32(E1000_TDH(tx_ring->reg_idx)), 5800 readl(tx_ring->tail), 5801 tx_ring->next_to_use, 5802 tx_ring->next_to_clean, 5803 tx_buffer->time_stamp, 5804 tx_buffer->next_to_watch, 5805 jiffies, 5806 tx_buffer->next_to_watch->wb.status); 5807 netif_stop_subqueue(tx_ring->netdev, 5808 tx_ring->queue_index); 5809 5810 /* we are about to reset, no point in enabling stuff */ 5811 return true; 5812 } 5813 } 5814 5815 if (unlikely(total_packets && 5816 netif_carrier_ok(tx_ring->netdev) && 5817 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) { 5818 /* Make sure that anybody stopping the queue after this 5819 * sees the new next_to_clean. 5820 */ 5821 smp_mb(); 5822 if (__netif_subqueue_stopped(tx_ring->netdev, 5823 tx_ring->queue_index) && 5824 !(test_bit(__IGB_DOWN, &adapter->state))) { 5825 netif_wake_subqueue(tx_ring->netdev, 5826 tx_ring->queue_index); 5827 5828 u64_stats_update_begin(&tx_ring->tx_syncp); 5829 tx_ring->tx_stats.restart_queue++; 5830 u64_stats_update_end(&tx_ring->tx_syncp); 5831 } 5832 } 5833 5834 return !!budget; 5835} 5836 5837/** 5838 * igb_reuse_rx_page - page flip buffer and store it back on the ring 5839 * @rx_ring: rx descriptor ring to store buffers on 5840 * @old_buff: donor buffer to have page reused 5841 * 5842 * Synchronizes page for reuse by the adapter 5843 **/ 5844static void igb_reuse_rx_page(struct igb_ring *rx_ring, 5845 struct igb_rx_buffer *old_buff) 5846{ 5847 struct igb_rx_buffer *new_buff; 5848 u16 nta = rx_ring->next_to_alloc; 5849 5850 new_buff = &rx_ring->rx_buffer_info[nta]; 5851 5852 /* update, and store next to alloc */ 5853 nta++; 5854 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 5855 5856 /* transfer page from old buffer to new buffer */ 5857 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); 5858 5859 /* sync the buffer for use by the device */ 5860 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 5861 old_buff->page_offset, 5862 IGB_RX_BUFSZ, 5863 DMA_FROM_DEVICE); 5864} 5865 5866/** 5867 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 5868 * @rx_ring: rx descriptor ring to transact packets on 5869 * @rx_buffer: buffer containing page to add 5870 * @rx_desc: descriptor containing length of buffer written by hardware 5871 * @skb: sk_buff to place the data into 5872 * 5873 * This function will add the data contained in rx_buffer->page to the skb. 5874 * This is done either through a direct copy if the data in the buffer is 5875 * less than the skb header size, otherwise it will just attach the page as 5876 * a frag to the skb. 5877 * 5878 * The function will then update the page offset if necessary and return 5879 * true if the buffer can be reused by the adapter. 5880 **/ 5881static bool igb_add_rx_frag(struct igb_ring *rx_ring, 5882 struct igb_rx_buffer *rx_buffer, 5883 union e1000_adv_rx_desc *rx_desc, 5884 struct sk_buff *skb) 5885{ 5886 struct page *page = rx_buffer->page; 5887 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 5888 5889 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { 5890 unsigned char *va = page_address(page) + rx_buffer->page_offset; 5891 5892#ifdef CONFIG_IGB_PTP 5893 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 5894 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 5895 va += IGB_TS_HDR_LEN; 5896 size -= IGB_TS_HDR_LEN; 5897 } 5898 5899#endif 5900 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 5901 5902 /* we can reuse buffer as-is, just make sure it is local */ 5903 if (likely(page_to_nid(page) == numa_node_id())) 5904 return true; 5905 5906 /* this page cannot be reused so discard it */ 5907 put_page(page); 5908 return false; 5909 } 5910 5911 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 5912 rx_buffer->page_offset, size, IGB_RX_BUFSZ); 5913 5914 /* avoid re-using remote pages */ 5915 if (unlikely(page_to_nid(page) != numa_node_id())) 5916 return false; 5917 5918#if (PAGE_SIZE < 8192) 5919 /* if we are only owner of page we can reuse it */ 5920 if (unlikely(page_count(page) != 1)) 5921 return false; 5922 5923 /* flip page offset to other buffer */ 5924 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 5925 5926 /* 5927 * since we are the only owner of the page and we need to 5928 * increment it, just set the value to 2 in order to avoid 5929 * an unnecessary locked operation 5930 */ 5931 atomic_set(&page->_count, 2); 5932#else 5933 /* move offset up to the next cache line */ 5934 rx_buffer->page_offset += SKB_DATA_ALIGN(size); 5935 5936 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 5937 return false; 5938 5939 /* bump ref count on page before it is given to the stack */ 5940 get_page(page); 5941#endif 5942 5943 return true; 5944} 5945 5946static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 5947 union e1000_adv_rx_desc *rx_desc, 5948 struct sk_buff *skb) 5949{ 5950 struct igb_rx_buffer *rx_buffer; 5951 struct page *page; 5952 5953 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 5954 5955 /* 5956 * This memory barrier is needed to keep us from reading 5957 * any other fields out of the rx_desc until we know the 5958 * RXD_STAT_DD bit is set 5959 */ 5960 rmb(); 5961 5962 page = rx_buffer->page; 5963 prefetchw(page); 5964 5965 if (likely(!skb)) { 5966 void *page_addr = page_address(page) + 5967 rx_buffer->page_offset; 5968 5969 /* prefetch first cache line of first page */ 5970 prefetch(page_addr); 5971#if L1_CACHE_BYTES < 128 5972 prefetch(page_addr + L1_CACHE_BYTES); 5973#endif 5974 5975 /* allocate a skb to store the frags */ 5976 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 5977 IGB_RX_HDR_LEN); 5978 if (unlikely(!skb)) { 5979 rx_ring->rx_stats.alloc_failed++; 5980 return NULL; 5981 } 5982 5983 /* 5984 * we will be copying header into skb->data in 5985 * pskb_may_pull so it is in our interest to prefetch 5986 * it now to avoid a possible cache miss 5987 */ 5988 prefetchw(skb->data); 5989 } 5990 5991 /* we are reusing so sync this buffer for CPU use */ 5992 dma_sync_single_range_for_cpu(rx_ring->dev, 5993 rx_buffer->dma, 5994 rx_buffer->page_offset, 5995 IGB_RX_BUFSZ, 5996 DMA_FROM_DEVICE); 5997 5998 /* pull page into skb */ 5999 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 6000 /* hand second half of page back to the ring */ 6001 igb_reuse_rx_page(rx_ring, rx_buffer); 6002 } else { 6003 /* we are not reusing the buffer so unmap it */ 6004 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6005 PAGE_SIZE, DMA_FROM_DEVICE); 6006 } 6007 6008 /* clear contents of rx_buffer */ 6009 rx_buffer->page = NULL; 6010 6011 return skb; 6012} 6013 6014static inline void igb_rx_checksum(struct igb_ring *ring, 6015 union e1000_adv_rx_desc *rx_desc, 6016 struct sk_buff *skb) 6017{ 6018 skb_checksum_none_assert(skb); 6019 6020 /* Ignore Checksum bit is set */ 6021 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6022 return; 6023 6024 /* Rx checksum disabled via ethtool */ 6025 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6026 return; 6027 6028 /* TCP/UDP checksum error bit is set */ 6029 if (igb_test_staterr(rx_desc, 6030 E1000_RXDEXT_STATERR_TCPE | 6031 E1000_RXDEXT_STATERR_IPE)) { 6032 /* 6033 * work around errata with sctp packets where the TCPE aka 6034 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6035 * packets, (aka let the stack check the crc32c) 6036 */ 6037 if (!((skb->len == 60) && 6038 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6039 u64_stats_update_begin(&ring->rx_syncp); 6040 ring->rx_stats.csum_err++; 6041 u64_stats_update_end(&ring->rx_syncp); 6042 } 6043 /* let the stack verify checksum errors */ 6044 return; 6045 } 6046 /* It must be a TCP or UDP packet with a valid checksum */ 6047 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 6048 E1000_RXD_STAT_UDPCS)) 6049 skb->ip_summed = CHECKSUM_UNNECESSARY; 6050 6051 dev_dbg(ring->dev, "cksum success: bits %08X\n", 6052 le32_to_cpu(rx_desc->wb.upper.status_error)); 6053} 6054 6055static inline void igb_rx_hash(struct igb_ring *ring, 6056 union e1000_adv_rx_desc *rx_desc, 6057 struct sk_buff *skb) 6058{ 6059 if (ring->netdev->features & NETIF_F_RXHASH) 6060 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); 6061} 6062 6063/** 6064 * igb_is_non_eop - process handling of non-EOP buffers 6065 * @rx_ring: Rx ring being processed 6066 * @rx_desc: Rx descriptor for current buffer 6067 * @skb: current socket buffer containing buffer in progress 6068 * 6069 * This function updates next to clean. If the buffer is an EOP buffer 6070 * this function exits returning false, otherwise it will place the 6071 * sk_buff in the next buffer to be chained and return true indicating 6072 * that this is in fact a non-EOP buffer. 6073 **/ 6074static bool igb_is_non_eop(struct igb_ring *rx_ring, 6075 union e1000_adv_rx_desc *rx_desc) 6076{ 6077 u32 ntc = rx_ring->next_to_clean + 1; 6078 6079 /* fetch, update, and store next to clean */ 6080 ntc = (ntc < rx_ring->count) ? ntc : 0; 6081 rx_ring->next_to_clean = ntc; 6082 6083 prefetch(IGB_RX_DESC(rx_ring, ntc)); 6084 6085 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 6086 return false; 6087 6088 return true; 6089} 6090 6091/** 6092 * igb_get_headlen - determine size of header for LRO/GRO 6093 * @data: pointer to the start of the headers 6094 * @max_len: total length of section to find headers in 6095 * 6096 * This function is meant to determine the length of headers that will 6097 * be recognized by hardware for LRO, and GRO offloads. The main 6098 * motivation of doing this is to only perform one pull for IPv4 TCP 6099 * packets so that we can do basic things like calculating the gso_size 6100 * based on the average data per packet. 6101 **/ 6102static unsigned int igb_get_headlen(unsigned char *data, 6103 unsigned int max_len) 6104{ 6105 union { 6106 unsigned char *network; 6107 /* l2 headers */ 6108 struct ethhdr *eth; 6109 struct vlan_hdr *vlan; 6110 /* l3 headers */ 6111 struct iphdr *ipv4; 6112 struct ipv6hdr *ipv6; 6113 } hdr; 6114 __be16 protocol; 6115 u8 nexthdr = 0; /* default to not TCP */ 6116 u8 hlen; 6117 6118 /* this should never happen, but better safe than sorry */ 6119 if (max_len < ETH_HLEN) 6120 return max_len; 6121 6122 /* initialize network frame pointer */ 6123 hdr.network = data; 6124 6125 /* set first protocol and move network header forward */ 6126 protocol = hdr.eth->h_proto; 6127 hdr.network += ETH_HLEN; 6128 6129 /* handle any vlan tag if present */ 6130 if (protocol == __constant_htons(ETH_P_8021Q)) { 6131 if ((hdr.network - data) > (max_len - VLAN_HLEN)) 6132 return max_len; 6133 6134 protocol = hdr.vlan->h_vlan_encapsulated_proto; 6135 hdr.network += VLAN_HLEN; 6136 } 6137 6138 /* handle L3 protocols */ 6139 if (protocol == __constant_htons(ETH_P_IP)) { 6140 if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) 6141 return max_len; 6142 6143 /* access ihl as a u8 to avoid unaligned access on ia64 */ 6144 hlen = (hdr.network[0] & 0x0F) << 2; 6145 6146 /* verify hlen meets minimum size requirements */ 6147 if (hlen < sizeof(struct iphdr)) 6148 return hdr.network - data; 6149 6150 /* record next protocol */ 6151 nexthdr = hdr.ipv4->protocol; 6152 hdr.network += hlen; 6153 } else if (protocol == __constant_htons(ETH_P_IPV6)) { 6154 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) 6155 return max_len; 6156 6157 /* record next protocol */ 6158 nexthdr = hdr.ipv6->nexthdr; 6159 hdr.network += sizeof(struct ipv6hdr); 6160 } else { 6161 return hdr.network - data; 6162 } 6163 6164 /* finally sort out TCP */ 6165 if (nexthdr == IPPROTO_TCP) { 6166 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) 6167 return max_len; 6168 6169 /* access doff as a u8 to avoid unaligned access on ia64 */ 6170 hlen = (hdr.network[12] & 0xF0) >> 2; 6171 6172 /* verify hlen meets minimum size requirements */ 6173 if (hlen < sizeof(struct tcphdr)) 6174 return hdr.network - data; 6175 6176 hdr.network += hlen; 6177 } else if (nexthdr == IPPROTO_UDP) { 6178 if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) 6179 return max_len; 6180 6181 hdr.network += sizeof(struct udphdr); 6182 } 6183 6184 /* 6185 * If everything has gone correctly hdr.network should be the 6186 * data section of the packet and will be the end of the header. 6187 * If not then it probably represents the end of the last recognized 6188 * header. 6189 */ 6190 if ((hdr.network - data) < max_len) 6191 return hdr.network - data; 6192 else 6193 return max_len; 6194} 6195 6196/** 6197 * igb_pull_tail - igb specific version of skb_pull_tail 6198 * @rx_ring: rx descriptor ring packet is being transacted on 6199 * @rx_desc: pointer to the EOP Rx descriptor 6200 * @skb: pointer to current skb being adjusted 6201 * 6202 * This function is an igb specific version of __pskb_pull_tail. The 6203 * main difference between this version and the original function is that 6204 * this function can make several assumptions about the state of things 6205 * that allow for significant optimizations versus the standard function. 6206 * As a result we can do things like drop a frag and maintain an accurate 6207 * truesize for the skb. 6208 */ 6209static void igb_pull_tail(struct igb_ring *rx_ring, 6210 union e1000_adv_rx_desc *rx_desc, 6211 struct sk_buff *skb) 6212{ 6213 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6214 unsigned char *va; 6215 unsigned int pull_len; 6216 6217 /* 6218 * it is valid to use page_address instead of kmap since we are 6219 * working with pages allocated out of the lomem pool per 6220 * alloc_page(GFP_ATOMIC) 6221 */ 6222 va = skb_frag_address(frag); 6223 6224#ifdef CONFIG_IGB_PTP 6225 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6226 /* retrieve timestamp from buffer */ 6227 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6228 6229 /* update pointers to remove timestamp header */ 6230 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); 6231 frag->page_offset += IGB_TS_HDR_LEN; 6232 skb->data_len -= IGB_TS_HDR_LEN; 6233 skb->len -= IGB_TS_HDR_LEN; 6234 6235 /* move va to start of packet data */ 6236 va += IGB_TS_HDR_LEN; 6237 } 6238 6239#endif 6240 /* 6241 * we need the header to contain the greater of either ETH_HLEN or 6242 * 60 bytes if the skb->len is less than 60 for skb_pad. 6243 */ 6244 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); 6245 6246 /* align pull length to size of long to optimize memcpy performance */ 6247 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 6248 6249 /* update all of the pointers */ 6250 skb_frag_size_sub(frag, pull_len); 6251 frag->page_offset += pull_len; 6252 skb->data_len -= pull_len; 6253 skb->tail += pull_len; 6254} 6255 6256/** 6257 * igb_cleanup_headers - Correct corrupted or empty headers 6258 * @rx_ring: rx descriptor ring packet is being transacted on 6259 * @rx_desc: pointer to the EOP Rx descriptor 6260 * @skb: pointer to current skb being fixed 6261 * 6262 * Address the case where we are pulling data in on pages only 6263 * and as such no data is present in the skb header. 6264 * 6265 * In addition if skb is not at least 60 bytes we need to pad it so that 6266 * it is large enough to qualify as a valid Ethernet frame. 6267 * 6268 * Returns true if an error was encountered and skb was freed. 6269 **/ 6270static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6271 union e1000_adv_rx_desc *rx_desc, 6272 struct sk_buff *skb) 6273{ 6274 6275 if (unlikely((igb_test_staterr(rx_desc, 6276 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6277 struct net_device *netdev = rx_ring->netdev; 6278 if (!(netdev->features & NETIF_F_RXALL)) { 6279 dev_kfree_skb_any(skb); 6280 return true; 6281 } 6282 } 6283 6284 /* place header in linear portion of buffer */ 6285 if (skb_is_nonlinear(skb)) 6286 igb_pull_tail(rx_ring, rx_desc, skb); 6287 6288 /* if skb_pad returns an error the skb was freed */ 6289 if (unlikely(skb->len < 60)) { 6290 int pad_len = 60 - skb->len; 6291 6292 if (skb_pad(skb, pad_len)) 6293 return true; 6294 __skb_put(skb, pad_len); 6295 } 6296 6297 return false; 6298} 6299 6300/** 6301 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6302 * @rx_ring: rx descriptor ring packet is being transacted on 6303 * @rx_desc: pointer to the EOP Rx descriptor 6304 * @skb: pointer to current skb being populated 6305 * 6306 * This function checks the ring, descriptor, and packet information in 6307 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6308 * other fields within the skb. 6309 **/ 6310static void igb_process_skb_fields(struct igb_ring *rx_ring, 6311 union e1000_adv_rx_desc *rx_desc, 6312 struct sk_buff *skb) 6313{ 6314 struct net_device *dev = rx_ring->netdev; 6315 6316 igb_rx_hash(rx_ring, rx_desc, skb); 6317 6318 igb_rx_checksum(rx_ring, rx_desc, skb); 6319 6320#ifdef CONFIG_IGB_PTP 6321 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb); 6322#endif /* CONFIG_IGB_PTP */ 6323 6324 if ((dev->features & NETIF_F_HW_VLAN_RX) && 6325 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6326 u16 vid; 6327 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6328 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6329 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6330 else 6331 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6332 6333 __vlan_hwaccel_put_tag(skb, vid); 6334 } 6335 6336 skb_record_rx_queue(skb, rx_ring->queue_index); 6337 6338 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6339} 6340 6341static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 6342{ 6343 struct igb_ring *rx_ring = q_vector->rx.ring; 6344 struct sk_buff *skb = rx_ring->skb; 6345 unsigned int total_bytes = 0, total_packets = 0; 6346 u16 cleaned_count = igb_desc_unused(rx_ring); 6347 6348 do { 6349 union e1000_adv_rx_desc *rx_desc; 6350 6351 /* return some buffers to hardware, one at a time is too slow */ 6352 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6353 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6354 cleaned_count = 0; 6355 } 6356 6357 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 6358 6359 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) 6360 break; 6361 6362 /* retrieve a buffer from the ring */ 6363 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 6364 6365 /* exit if we failed to retrieve a buffer */ 6366 if (!skb) 6367 break; 6368 6369 cleaned_count++; 6370 6371 /* fetch next buffer in frame if non-eop */ 6372 if (igb_is_non_eop(rx_ring, rx_desc)) 6373 continue; 6374 6375 /* verify the packet layout is correct */ 6376 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 6377 skb = NULL; 6378 continue; 6379 } 6380 6381 /* probably a little skewed due to removing CRC */ 6382 total_bytes += skb->len; 6383 6384 /* populate checksum, timestamp, VLAN, and protocol */ 6385 igb_process_skb_fields(rx_ring, rx_desc, skb); 6386 6387 napi_gro_receive(&q_vector->napi, skb); 6388 6389 /* reset skb pointer */ 6390 skb = NULL; 6391 6392 /* update budget accounting */ 6393 total_packets++; 6394 } while (likely(total_packets < budget)); 6395 6396 /* place incomplete frames back on ring for completion */ 6397 rx_ring->skb = skb; 6398 6399 u64_stats_update_begin(&rx_ring->rx_syncp); 6400 rx_ring->rx_stats.packets += total_packets; 6401 rx_ring->rx_stats.bytes += total_bytes; 6402 u64_stats_update_end(&rx_ring->rx_syncp); 6403 q_vector->rx.total_packets += total_packets; 6404 q_vector->rx.total_bytes += total_bytes; 6405 6406 if (cleaned_count) 6407 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6408 6409 return (total_packets < budget); 6410} 6411 6412static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 6413 struct igb_rx_buffer *bi) 6414{ 6415 struct page *page = bi->page; 6416 dma_addr_t dma; 6417 6418 /* since we are recycling buffers we should seldom need to alloc */ 6419 if (likely(page)) 6420 return true; 6421 6422 /* alloc new page for storage */ 6423 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); 6424 if (unlikely(!page)) { 6425 rx_ring->rx_stats.alloc_failed++; 6426 return false; 6427 } 6428 6429 /* map page for use */ 6430 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 6431 6432 /* 6433 * if mapping failed free memory back to system since 6434 * there isn't much point in holding memory we can't use 6435 */ 6436 if (dma_mapping_error(rx_ring->dev, dma)) { 6437 __free_page(page); 6438 6439 rx_ring->rx_stats.alloc_failed++; 6440 return false; 6441 } 6442 6443 bi->dma = dma; 6444 bi->page = page; 6445 bi->page_offset = 0; 6446 6447 return true; 6448} 6449 6450/** 6451 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 6452 * @adapter: address of board private structure 6453 **/ 6454void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 6455{ 6456 union e1000_adv_rx_desc *rx_desc; 6457 struct igb_rx_buffer *bi; 6458 u16 i = rx_ring->next_to_use; 6459 6460 /* nothing to do */ 6461 if (!cleaned_count) 6462 return; 6463 6464 rx_desc = IGB_RX_DESC(rx_ring, i); 6465 bi = &rx_ring->rx_buffer_info[i]; 6466 i -= rx_ring->count; 6467 6468 do { 6469 if (!igb_alloc_mapped_page(rx_ring, bi)) 6470 break; 6471 6472 /* 6473 * Refresh the desc even if buffer_addrs didn't change 6474 * because each write-back erases this info. 6475 */ 6476 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 6477 6478 rx_desc++; 6479 bi++; 6480 i++; 6481 if (unlikely(!i)) { 6482 rx_desc = IGB_RX_DESC(rx_ring, 0); 6483 bi = rx_ring->rx_buffer_info; 6484 i -= rx_ring->count; 6485 } 6486 6487 /* clear the hdr_addr for the next_to_use descriptor */ 6488 rx_desc->read.hdr_addr = 0; 6489 6490 cleaned_count--; 6491 } while (cleaned_count); 6492 6493 i += rx_ring->count; 6494 6495 if (rx_ring->next_to_use != i) { 6496 /* record the next descriptor to use */ 6497 rx_ring->next_to_use = i; 6498 6499 /* update next to alloc since we have filled the ring */ 6500 rx_ring->next_to_alloc = i; 6501 6502 /* 6503 * Force memory writes to complete before letting h/w 6504 * know there are new descriptors to fetch. (Only 6505 * applicable for weak-ordered memory model archs, 6506 * such as IA-64). 6507 */ 6508 wmb(); 6509 writel(i, rx_ring->tail); 6510 } 6511} 6512 6513/** 6514 * igb_mii_ioctl - 6515 * @netdev: 6516 * @ifreq: 6517 * @cmd: 6518 **/ 6519static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6520{ 6521 struct igb_adapter *adapter = netdev_priv(netdev); 6522 struct mii_ioctl_data *data = if_mii(ifr); 6523 6524 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6525 return -EOPNOTSUPP; 6526 6527 switch (cmd) { 6528 case SIOCGMIIPHY: 6529 data->phy_id = adapter->hw.phy.addr; 6530 break; 6531 case SIOCGMIIREG: 6532 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 6533 &data->val_out)) 6534 return -EIO; 6535 break; 6536 case SIOCSMIIREG: 6537 default: 6538 return -EOPNOTSUPP; 6539 } 6540 return 0; 6541} 6542 6543/** 6544 * igb_ioctl - 6545 * @netdev: 6546 * @ifreq: 6547 * @cmd: 6548 **/ 6549static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6550{ 6551 switch (cmd) { 6552 case SIOCGMIIPHY: 6553 case SIOCGMIIREG: 6554 case SIOCSMIIREG: 6555 return igb_mii_ioctl(netdev, ifr, cmd); 6556#ifdef CONFIG_IGB_PTP 6557 case SIOCSHWTSTAMP: 6558 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd); 6559#endif /* CONFIG_IGB_PTP */ 6560 default: 6561 return -EOPNOTSUPP; 6562 } 6563} 6564 6565s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 6566{ 6567 struct igb_adapter *adapter = hw->back; 6568 6569 if (pcie_capability_read_word(adapter->pdev, reg, value)) 6570 return -E1000_ERR_CONFIG; 6571 6572 return 0; 6573} 6574 6575s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 6576{ 6577 struct igb_adapter *adapter = hw->back; 6578 6579 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 6580 return -E1000_ERR_CONFIG; 6581 6582 return 0; 6583} 6584 6585static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 6586{ 6587 struct igb_adapter *adapter = netdev_priv(netdev); 6588 struct e1000_hw *hw = &adapter->hw; 6589 u32 ctrl, rctl; 6590 bool enable = !!(features & NETIF_F_HW_VLAN_RX); 6591 6592 if (enable) { 6593 /* enable VLAN tag insert/strip */ 6594 ctrl = rd32(E1000_CTRL); 6595 ctrl |= E1000_CTRL_VME; 6596 wr32(E1000_CTRL, ctrl); 6597 6598 /* Disable CFI check */ 6599 rctl = rd32(E1000_RCTL); 6600 rctl &= ~E1000_RCTL_CFIEN; 6601 wr32(E1000_RCTL, rctl); 6602 } else { 6603 /* disable VLAN tag insert/strip */ 6604 ctrl = rd32(E1000_CTRL); 6605 ctrl &= ~E1000_CTRL_VME; 6606 wr32(E1000_CTRL, ctrl); 6607 } 6608 6609 igb_rlpml_set(adapter); 6610} 6611 6612static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) 6613{ 6614 struct igb_adapter *adapter = netdev_priv(netdev); 6615 struct e1000_hw *hw = &adapter->hw; 6616 int pf_id = adapter->vfs_allocated_count; 6617 6618 /* attempt to add filter to vlvf array */ 6619 igb_vlvf_set(adapter, vid, true, pf_id); 6620 6621 /* add the filter since PF can receive vlans w/o entry in vlvf */ 6622 igb_vfta_set(hw, vid, true); 6623 6624 set_bit(vid, adapter->active_vlans); 6625 6626 return 0; 6627} 6628 6629static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) 6630{ 6631 struct igb_adapter *adapter = netdev_priv(netdev); 6632 struct e1000_hw *hw = &adapter->hw; 6633 int pf_id = adapter->vfs_allocated_count; 6634 s32 err; 6635 6636 /* remove vlan from VLVF table array */ 6637 err = igb_vlvf_set(adapter, vid, false, pf_id); 6638 6639 /* if vid was not present in VLVF just remove it from table */ 6640 if (err) 6641 igb_vfta_set(hw, vid, false); 6642 6643 clear_bit(vid, adapter->active_vlans); 6644 6645 return 0; 6646} 6647 6648static void igb_restore_vlan(struct igb_adapter *adapter) 6649{ 6650 u16 vid; 6651 6652 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 6653 6654 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 6655 igb_vlan_rx_add_vid(adapter->netdev, vid); 6656} 6657 6658int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 6659{ 6660 struct pci_dev *pdev = adapter->pdev; 6661 struct e1000_mac_info *mac = &adapter->hw.mac; 6662 6663 mac->autoneg = 0; 6664 6665 /* Make sure dplx is at most 1 bit and lsb of speed is not set 6666 * for the switch() below to work */ 6667 if ((spd & 1) || (dplx & ~1)) 6668 goto err_inval; 6669 6670 /* Fiber NIC's only allow 1000 Gbps Full duplex */ 6671 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) && 6672 spd != SPEED_1000 && 6673 dplx != DUPLEX_FULL) 6674 goto err_inval; 6675 6676 switch (spd + dplx) { 6677 case SPEED_10 + DUPLEX_HALF: 6678 mac->forced_speed_duplex = ADVERTISE_10_HALF; 6679 break; 6680 case SPEED_10 + DUPLEX_FULL: 6681 mac->forced_speed_duplex = ADVERTISE_10_FULL; 6682 break; 6683 case SPEED_100 + DUPLEX_HALF: 6684 mac->forced_speed_duplex = ADVERTISE_100_HALF; 6685 break; 6686 case SPEED_100 + DUPLEX_FULL: 6687 mac->forced_speed_duplex = ADVERTISE_100_FULL; 6688 break; 6689 case SPEED_1000 + DUPLEX_FULL: 6690 mac->autoneg = 1; 6691 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 6692 break; 6693 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 6694 default: 6695 goto err_inval; 6696 } 6697 6698 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 6699 adapter->hw.phy.mdix = AUTO_ALL_MODES; 6700 6701 return 0; 6702 6703err_inval: 6704 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 6705 return -EINVAL; 6706} 6707 6708static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 6709 bool runtime) 6710{ 6711 struct net_device *netdev = pci_get_drvdata(pdev); 6712 struct igb_adapter *adapter = netdev_priv(netdev); 6713 struct e1000_hw *hw = &adapter->hw; 6714 u32 ctrl, rctl, status; 6715 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 6716#ifdef CONFIG_PM 6717 int retval = 0; 6718#endif 6719 6720 netif_device_detach(netdev); 6721 6722 if (netif_running(netdev)) 6723 __igb_close(netdev, true); 6724 6725 igb_clear_interrupt_scheme(adapter); 6726 6727#ifdef CONFIG_PM 6728 retval = pci_save_state(pdev); 6729 if (retval) 6730 return retval; 6731#endif 6732 6733 status = rd32(E1000_STATUS); 6734 if (status & E1000_STATUS_LU) 6735 wufc &= ~E1000_WUFC_LNKC; 6736 6737 if (wufc) { 6738 igb_setup_rctl(adapter); 6739 igb_set_rx_mode(netdev); 6740 6741 /* turn on all-multi mode if wake on multicast is enabled */ 6742 if (wufc & E1000_WUFC_MC) { 6743 rctl = rd32(E1000_RCTL); 6744 rctl |= E1000_RCTL_MPE; 6745 wr32(E1000_RCTL, rctl); 6746 } 6747 6748 ctrl = rd32(E1000_CTRL); 6749 /* advertise wake from D3Cold */ 6750 #define E1000_CTRL_ADVD3WUC 0x00100000 6751 /* phy power management enable */ 6752 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 6753 ctrl |= E1000_CTRL_ADVD3WUC; 6754 wr32(E1000_CTRL, ctrl); 6755 6756 /* Allow time for pending master requests to run */ 6757 igb_disable_pcie_master(hw); 6758 6759 wr32(E1000_WUC, E1000_WUC_PME_EN); 6760 wr32(E1000_WUFC, wufc); 6761 } else { 6762 wr32(E1000_WUC, 0); 6763 wr32(E1000_WUFC, 0); 6764 } 6765 6766 *enable_wake = wufc || adapter->en_mng_pt; 6767 if (!*enable_wake) 6768 igb_power_down_link(adapter); 6769 else 6770 igb_power_up_link(adapter); 6771 6772 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6773 * would have already happened in close and is redundant. */ 6774 igb_release_hw_control(adapter); 6775 6776 pci_disable_device(pdev); 6777 6778 return 0; 6779} 6780 6781#ifdef CONFIG_PM 6782#ifdef CONFIG_PM_SLEEP 6783static int igb_suspend(struct device *dev) 6784{ 6785 int retval; 6786 bool wake; 6787 struct pci_dev *pdev = to_pci_dev(dev); 6788 6789 retval = __igb_shutdown(pdev, &wake, 0); 6790 if (retval) 6791 return retval; 6792 6793 if (wake) { 6794 pci_prepare_to_sleep(pdev); 6795 } else { 6796 pci_wake_from_d3(pdev, false); 6797 pci_set_power_state(pdev, PCI_D3hot); 6798 } 6799 6800 return 0; 6801} 6802#endif /* CONFIG_PM_SLEEP */ 6803 6804static int igb_resume(struct device *dev) 6805{ 6806 struct pci_dev *pdev = to_pci_dev(dev); 6807 struct net_device *netdev = pci_get_drvdata(pdev); 6808 struct igb_adapter *adapter = netdev_priv(netdev); 6809 struct e1000_hw *hw = &adapter->hw; 6810 u32 err; 6811 6812 pci_set_power_state(pdev, PCI_D0); 6813 pci_restore_state(pdev); 6814 pci_save_state(pdev); 6815 6816 err = pci_enable_device_mem(pdev); 6817 if (err) { 6818 dev_err(&pdev->dev, 6819 "igb: Cannot enable PCI device from suspend\n"); 6820 return err; 6821 } 6822 pci_set_master(pdev); 6823 6824 pci_enable_wake(pdev, PCI_D3hot, 0); 6825 pci_enable_wake(pdev, PCI_D3cold, 0); 6826 6827 if (igb_init_interrupt_scheme(adapter)) { 6828 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 6829 return -ENOMEM; 6830 } 6831 6832 igb_reset(adapter); 6833 6834 /* let the f/w know that the h/w is now under the control of the 6835 * driver. */ 6836 igb_get_hw_control(adapter); 6837 6838 wr32(E1000_WUS, ~0); 6839 6840 if (netdev->flags & IFF_UP) { 6841 rtnl_lock(); 6842 err = __igb_open(netdev, true); 6843 rtnl_unlock(); 6844 if (err) 6845 return err; 6846 } 6847 6848 netif_device_attach(netdev); 6849 return 0; 6850} 6851 6852#ifdef CONFIG_PM_RUNTIME 6853static int igb_runtime_idle(struct device *dev) 6854{ 6855 struct pci_dev *pdev = to_pci_dev(dev); 6856 struct net_device *netdev = pci_get_drvdata(pdev); 6857 struct igb_adapter *adapter = netdev_priv(netdev); 6858 6859 if (!igb_has_link(adapter)) 6860 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 6861 6862 return -EBUSY; 6863} 6864 6865static int igb_runtime_suspend(struct device *dev) 6866{ 6867 struct pci_dev *pdev = to_pci_dev(dev); 6868 int retval; 6869 bool wake; 6870 6871 retval = __igb_shutdown(pdev, &wake, 1); 6872 if (retval) 6873 return retval; 6874 6875 if (wake) { 6876 pci_prepare_to_sleep(pdev); 6877 } else { 6878 pci_wake_from_d3(pdev, false); 6879 pci_set_power_state(pdev, PCI_D3hot); 6880 } 6881 6882 return 0; 6883} 6884 6885static int igb_runtime_resume(struct device *dev) 6886{ 6887 return igb_resume(dev); 6888} 6889#endif /* CONFIG_PM_RUNTIME */ 6890#endif 6891 6892static void igb_shutdown(struct pci_dev *pdev) 6893{ 6894 bool wake; 6895 6896 __igb_shutdown(pdev, &wake, 0); 6897 6898 if (system_state == SYSTEM_POWER_OFF) { 6899 pci_wake_from_d3(pdev, wake); 6900 pci_set_power_state(pdev, PCI_D3hot); 6901 } 6902} 6903 6904#ifdef CONFIG_NET_POLL_CONTROLLER 6905/* 6906 * Polling 'interrupt' - used by things like netconsole to send skbs 6907 * without having to re-enable interrupts. It's not called while 6908 * the interrupt routine is executing. 6909 */ 6910static void igb_netpoll(struct net_device *netdev) 6911{ 6912 struct igb_adapter *adapter = netdev_priv(netdev); 6913 struct e1000_hw *hw = &adapter->hw; 6914 struct igb_q_vector *q_vector; 6915 int i; 6916 6917 for (i = 0; i < adapter->num_q_vectors; i++) { 6918 q_vector = adapter->q_vector[i]; 6919 if (adapter->msix_entries) 6920 wr32(E1000_EIMC, q_vector->eims_value); 6921 else 6922 igb_irq_disable(adapter); 6923 napi_schedule(&q_vector->napi); 6924 } 6925} 6926#endif /* CONFIG_NET_POLL_CONTROLLER */ 6927 6928/** 6929 * igb_io_error_detected - called when PCI error is detected 6930 * @pdev: Pointer to PCI device 6931 * @state: The current pci connection state 6932 * 6933 * This function is called after a PCI bus error affecting 6934 * this device has been detected. 6935 */ 6936static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 6937 pci_channel_state_t state) 6938{ 6939 struct net_device *netdev = pci_get_drvdata(pdev); 6940 struct igb_adapter *adapter = netdev_priv(netdev); 6941 6942 netif_device_detach(netdev); 6943 6944 if (state == pci_channel_io_perm_failure) 6945 return PCI_ERS_RESULT_DISCONNECT; 6946 6947 if (netif_running(netdev)) 6948 igb_down(adapter); 6949 pci_disable_device(pdev); 6950 6951 /* Request a slot slot reset. */ 6952 return PCI_ERS_RESULT_NEED_RESET; 6953} 6954 6955/** 6956 * igb_io_slot_reset - called after the pci bus has been reset. 6957 * @pdev: Pointer to PCI device 6958 * 6959 * Restart the card from scratch, as if from a cold-boot. Implementation 6960 * resembles the first-half of the igb_resume routine. 6961 */ 6962static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 6963{ 6964 struct net_device *netdev = pci_get_drvdata(pdev); 6965 struct igb_adapter *adapter = netdev_priv(netdev); 6966 struct e1000_hw *hw = &adapter->hw; 6967 pci_ers_result_t result; 6968 int err; 6969 6970 if (pci_enable_device_mem(pdev)) { 6971 dev_err(&pdev->dev, 6972 "Cannot re-enable PCI device after reset.\n"); 6973 result = PCI_ERS_RESULT_DISCONNECT; 6974 } else { 6975 pci_set_master(pdev); 6976 pci_restore_state(pdev); 6977 pci_save_state(pdev); 6978 6979 pci_enable_wake(pdev, PCI_D3hot, 0); 6980 pci_enable_wake(pdev, PCI_D3cold, 0); 6981 6982 igb_reset(adapter); 6983 wr32(E1000_WUS, ~0); 6984 result = PCI_ERS_RESULT_RECOVERED; 6985 } 6986 6987 err = pci_cleanup_aer_uncorrect_error_status(pdev); 6988 if (err) { 6989 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status " 6990 "failed 0x%0x\n", err); 6991 /* non-fatal, continue */ 6992 } 6993 6994 return result; 6995} 6996 6997/** 6998 * igb_io_resume - called when traffic can start flowing again. 6999 * @pdev: Pointer to PCI device 7000 * 7001 * This callback is called when the error recovery driver tells us that 7002 * its OK to resume normal operation. Implementation resembles the 7003 * second-half of the igb_resume routine. 7004 */ 7005static void igb_io_resume(struct pci_dev *pdev) 7006{ 7007 struct net_device *netdev = pci_get_drvdata(pdev); 7008 struct igb_adapter *adapter = netdev_priv(netdev); 7009 7010 if (netif_running(netdev)) { 7011 if (igb_up(adapter)) { 7012 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7013 return; 7014 } 7015 } 7016 7017 netif_device_attach(netdev); 7018 7019 /* let the f/w know that the h/w is now under the control of the 7020 * driver. */ 7021 igb_get_hw_control(adapter); 7022} 7023 7024static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7025 u8 qsel) 7026{ 7027 u32 rar_low, rar_high; 7028 struct e1000_hw *hw = &adapter->hw; 7029 7030 /* HW expects these in little endian so we reverse the byte order 7031 * from network order (big endian) to little endian 7032 */ 7033 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 7034 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 7035 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 7036 7037 /* Indicate to hardware the Address is Valid. */ 7038 rar_high |= E1000_RAH_AV; 7039 7040 if (hw->mac.type == e1000_82575) 7041 rar_high |= E1000_RAH_POOL_1 * qsel; 7042 else 7043 rar_high |= E1000_RAH_POOL_1 << qsel; 7044 7045 wr32(E1000_RAL(index), rar_low); 7046 wrfl(); 7047 wr32(E1000_RAH(index), rar_high); 7048 wrfl(); 7049} 7050 7051static int igb_set_vf_mac(struct igb_adapter *adapter, 7052 int vf, unsigned char *mac_addr) 7053{ 7054 struct e1000_hw *hw = &adapter->hw; 7055 /* VF MAC addresses start at end of receive addresses and moves 7056 * torwards the first, as a result a collision should not be possible */ 7057 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7058 7059 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7060 7061 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7062 7063 return 0; 7064} 7065 7066static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7067{ 7068 struct igb_adapter *adapter = netdev_priv(netdev); 7069 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7070 return -EINVAL; 7071 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7072 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7073 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this" 7074 " change effective."); 7075 if (test_bit(__IGB_DOWN, &adapter->state)) { 7076 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set," 7077 " but the PF device is not up.\n"); 7078 dev_warn(&adapter->pdev->dev, "Bring the PF device up before" 7079 " attempting to use the VF device.\n"); 7080 } 7081 return igb_set_vf_mac(adapter, vf, mac); 7082} 7083 7084static int igb_link_mbps(int internal_link_speed) 7085{ 7086 switch (internal_link_speed) { 7087 case SPEED_100: 7088 return 100; 7089 case SPEED_1000: 7090 return 1000; 7091 default: 7092 return 0; 7093 } 7094} 7095 7096static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7097 int link_speed) 7098{ 7099 int rf_dec, rf_int; 7100 u32 bcnrc_val; 7101 7102 if (tx_rate != 0) { 7103 /* Calculate the rate factor values to set */ 7104 rf_int = link_speed / tx_rate; 7105 rf_dec = (link_speed - (rf_int * tx_rate)); 7106 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate; 7107 7108 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7109 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) & 7110 E1000_RTTBCNRC_RF_INT_MASK); 7111 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7112 } else { 7113 bcnrc_val = 0; 7114 } 7115 7116 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7117 /* 7118 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7119 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7120 */ 7121 wr32(E1000_RTTBCNRM, 0x14); 7122 wr32(E1000_RTTBCNRC, bcnrc_val); 7123} 7124 7125static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7126{ 7127 int actual_link_speed, i; 7128 bool reset_rate = false; 7129 7130 /* VF TX rate limit was not set or not supported */ 7131 if ((adapter->vf_rate_link_speed == 0) || 7132 (adapter->hw.mac.type != e1000_82576)) 7133 return; 7134 7135 actual_link_speed = igb_link_mbps(adapter->link_speed); 7136 if (actual_link_speed != adapter->vf_rate_link_speed) { 7137 reset_rate = true; 7138 adapter->vf_rate_link_speed = 0; 7139 dev_info(&adapter->pdev->dev, 7140 "Link speed has been changed. VF Transmit " 7141 "rate is disabled\n"); 7142 } 7143 7144 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7145 if (reset_rate) 7146 adapter->vf_data[i].tx_rate = 0; 7147 7148 igb_set_vf_rate_limit(&adapter->hw, i, 7149 adapter->vf_data[i].tx_rate, 7150 actual_link_speed); 7151 } 7152} 7153 7154static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) 7155{ 7156 struct igb_adapter *adapter = netdev_priv(netdev); 7157 struct e1000_hw *hw = &adapter->hw; 7158 int actual_link_speed; 7159 7160 if (hw->mac.type != e1000_82576) 7161 return -EOPNOTSUPP; 7162 7163 actual_link_speed = igb_link_mbps(adapter->link_speed); 7164 if ((vf >= adapter->vfs_allocated_count) || 7165 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7166 (tx_rate < 0) || (tx_rate > actual_link_speed)) 7167 return -EINVAL; 7168 7169 adapter->vf_rate_link_speed = actual_link_speed; 7170 adapter->vf_data[vf].tx_rate = (u16)tx_rate; 7171 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); 7172 7173 return 0; 7174} 7175 7176static int igb_ndo_get_vf_config(struct net_device *netdev, 7177 int vf, struct ifla_vf_info *ivi) 7178{ 7179 struct igb_adapter *adapter = netdev_priv(netdev); 7180 if (vf >= adapter->vfs_allocated_count) 7181 return -EINVAL; 7182 ivi->vf = vf; 7183 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7184 ivi->tx_rate = adapter->vf_data[vf].tx_rate; 7185 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7186 ivi->qos = adapter->vf_data[vf].pf_qos; 7187 return 0; 7188} 7189 7190static void igb_vmm_control(struct igb_adapter *adapter) 7191{ 7192 struct e1000_hw *hw = &adapter->hw; 7193 u32 reg; 7194 7195 switch (hw->mac.type) { 7196 case e1000_82575: 7197 case e1000_i210: 7198 case e1000_i211: 7199 default: 7200 /* replication is not supported for 82575 */ 7201 return; 7202 case e1000_82576: 7203 /* notify HW that the MAC is adding vlan tags */ 7204 reg = rd32(E1000_DTXCTL); 7205 reg |= E1000_DTXCTL_VLAN_ADDED; 7206 wr32(E1000_DTXCTL, reg); 7207 case e1000_82580: 7208 /* enable replication vlan tag stripping */ 7209 reg = rd32(E1000_RPLOLR); 7210 reg |= E1000_RPLOLR_STRVLAN; 7211 wr32(E1000_RPLOLR, reg); 7212 case e1000_i350: 7213 /* none of the above registers are supported by i350 */ 7214 break; 7215 } 7216 7217 if (adapter->vfs_allocated_count) { 7218 igb_vmdq_set_loopback_pf(hw, true); 7219 igb_vmdq_set_replication_pf(hw, true); 7220 igb_vmdq_set_anti_spoofing_pf(hw, true, 7221 adapter->vfs_allocated_count); 7222 } else { 7223 igb_vmdq_set_loopback_pf(hw, false); 7224 igb_vmdq_set_replication_pf(hw, false); 7225 } 7226} 7227 7228static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7229{ 7230 struct e1000_hw *hw = &adapter->hw; 7231 u32 dmac_thr; 7232 u16 hwm; 7233 7234 if (hw->mac.type > e1000_82580) { 7235 if (adapter->flags & IGB_FLAG_DMAC) { 7236 u32 reg; 7237 7238 /* force threshold to 0. */ 7239 wr32(E1000_DMCTXTH, 0); 7240 7241 /* 7242 * DMA Coalescing high water mark needs to be greater 7243 * than the Rx threshold. Set hwm to PBA - max frame 7244 * size in 16B units, capping it at PBA - 6KB. 7245 */ 7246 hwm = 64 * pba - adapter->max_frame_size / 16; 7247 if (hwm < 64 * (pba - 6)) 7248 hwm = 64 * (pba - 6); 7249 reg = rd32(E1000_FCRTC); 7250 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 7251 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 7252 & E1000_FCRTC_RTH_COAL_MASK); 7253 wr32(E1000_FCRTC, reg); 7254 7255 /* 7256 * Set the DMA Coalescing Rx threshold to PBA - 2 * max 7257 * frame size, capping it at PBA - 10KB. 7258 */ 7259 dmac_thr = pba - adapter->max_frame_size / 512; 7260 if (dmac_thr < pba - 10) 7261 dmac_thr = pba - 10; 7262 reg = rd32(E1000_DMACR); 7263 reg &= ~E1000_DMACR_DMACTHR_MASK; 7264 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 7265 & E1000_DMACR_DMACTHR_MASK); 7266 7267 /* transition to L0x or L1 if available..*/ 7268 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 7269 7270 /* watchdog timer= +-1000 usec in 32usec intervals */ 7271 reg |= (1000 >> 5); 7272 7273 /* Disable BMC-to-OS Watchdog Enable */ 7274 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 7275 wr32(E1000_DMACR, reg); 7276 7277 /* 7278 * no lower threshold to disable 7279 * coalescing(smart fifb)-UTRESH=0 7280 */ 7281 wr32(E1000_DMCRTRH, 0); 7282 7283 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 7284 7285 wr32(E1000_DMCTLX, reg); 7286 7287 /* 7288 * free space in tx packet buffer to wake from 7289 * DMA coal 7290 */ 7291 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 7292 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 7293 7294 /* 7295 * make low power state decision controlled 7296 * by DMA coal 7297 */ 7298 reg = rd32(E1000_PCIEMISC); 7299 reg &= ~E1000_PCIEMISC_LX_DECISION; 7300 wr32(E1000_PCIEMISC, reg); 7301 } /* endif adapter->dmac is not disabled */ 7302 } else if (hw->mac.type == e1000_82580) { 7303 u32 reg = rd32(E1000_PCIEMISC); 7304 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 7305 wr32(E1000_DMACR, 0); 7306 } 7307} 7308 7309/* igb_main.c */ 7310