igb_main.c revision 22a8b2915998a5f35f659c1d419bd4bcbb1b6f41
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25*******************************************************************************/ 26 27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 28 29#include <linux/module.h> 30#include <linux/types.h> 31#include <linux/init.h> 32#include <linux/bitops.h> 33#include <linux/vmalloc.h> 34#include <linux/pagemap.h> 35#include <linux/netdevice.h> 36#include <linux/ipv6.h> 37#include <linux/slab.h> 38#include <net/checksum.h> 39#include <net/ip6_checksum.h> 40#include <linux/net_tstamp.h> 41#include <linux/mii.h> 42#include <linux/ethtool.h> 43#include <linux/if.h> 44#include <linux/if_vlan.h> 45#include <linux/pci.h> 46#include <linux/pci-aspm.h> 47#include <linux/delay.h> 48#include <linux/interrupt.h> 49#include <linux/ip.h> 50#include <linux/tcp.h> 51#include <linux/sctp.h> 52#include <linux/if_ether.h> 53#include <linux/aer.h> 54#include <linux/prefetch.h> 55#include <linux/pm_runtime.h> 56#ifdef CONFIG_IGB_DCA 57#include <linux/dca.h> 58#endif 59#include <linux/i2c.h> 60#include "igb.h" 61 62#define MAJ 5 63#define MIN 0 64#define BUILD 5 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 66__stringify(BUILD) "-k" 67char igb_driver_name[] = "igb"; 68char igb_driver_version[] = DRV_VERSION; 69static const char igb_driver_string[] = 70 "Intel(R) Gigabit Ethernet Network Driver"; 71static const char igb_copyright[] = 72 "Copyright (c) 2007-2014 Intel Corporation."; 73 74static const struct e1000_info *igb_info_tbl[] = { 75 [board_82575] = &e1000_82575_info, 76}; 77 78static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 114 /* required last entry */ 115 {0, } 116}; 117 118MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 119 120void igb_reset(struct igb_adapter *); 121static int igb_setup_all_tx_resources(struct igb_adapter *); 122static int igb_setup_all_rx_resources(struct igb_adapter *); 123static void igb_free_all_tx_resources(struct igb_adapter *); 124static void igb_free_all_rx_resources(struct igb_adapter *); 125static void igb_setup_mrqc(struct igb_adapter *); 126static int igb_probe(struct pci_dev *, const struct pci_device_id *); 127static void igb_remove(struct pci_dev *pdev); 128static int igb_sw_init(struct igb_adapter *); 129static int igb_open(struct net_device *); 130static int igb_close(struct net_device *); 131static void igb_configure(struct igb_adapter *); 132static void igb_configure_tx(struct igb_adapter *); 133static void igb_configure_rx(struct igb_adapter *); 134static void igb_clean_all_tx_rings(struct igb_adapter *); 135static void igb_clean_all_rx_rings(struct igb_adapter *); 136static void igb_clean_tx_ring(struct igb_ring *); 137static void igb_clean_rx_ring(struct igb_ring *); 138static void igb_set_rx_mode(struct net_device *); 139static void igb_update_phy_info(unsigned long); 140static void igb_watchdog(unsigned long); 141static void igb_watchdog_task(struct work_struct *); 142static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 143static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 144 struct rtnl_link_stats64 *stats); 145static int igb_change_mtu(struct net_device *, int); 146static int igb_set_mac(struct net_device *, void *); 147static void igb_set_uta(struct igb_adapter *adapter); 148static irqreturn_t igb_intr(int irq, void *); 149static irqreturn_t igb_intr_msi(int irq, void *); 150static irqreturn_t igb_msix_other(int irq, void *); 151static irqreturn_t igb_msix_ring(int irq, void *); 152#ifdef CONFIG_IGB_DCA 153static void igb_update_dca(struct igb_q_vector *); 154static void igb_setup_dca(struct igb_adapter *); 155#endif /* CONFIG_IGB_DCA */ 156static int igb_poll(struct napi_struct *, int); 157static bool igb_clean_tx_irq(struct igb_q_vector *); 158static bool igb_clean_rx_irq(struct igb_q_vector *, int); 159static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 160static void igb_tx_timeout(struct net_device *); 161static void igb_reset_task(struct work_struct *); 162static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); 163static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 164static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 165static void igb_restore_vlan(struct igb_adapter *); 166static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 167static void igb_ping_all_vfs(struct igb_adapter *); 168static void igb_msg_task(struct igb_adapter *); 169static void igb_vmm_control(struct igb_adapter *); 170static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 171static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 172static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 173static int igb_ndo_set_vf_vlan(struct net_device *netdev, 174 int vf, u16 vlan, u8 qos); 175static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 176static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 177 bool setting); 178static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 179 struct ifla_vf_info *ivi); 180static void igb_check_vf_rate_limit(struct igb_adapter *); 181 182#ifdef CONFIG_PCI_IOV 183static int igb_vf_configure(struct igb_adapter *adapter, int vf); 184static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 185#endif 186 187#ifdef CONFIG_PM 188#ifdef CONFIG_PM_SLEEP 189static int igb_suspend(struct device *); 190#endif 191static int igb_resume(struct device *); 192#ifdef CONFIG_PM_RUNTIME 193static int igb_runtime_suspend(struct device *dev); 194static int igb_runtime_resume(struct device *dev); 195static int igb_runtime_idle(struct device *dev); 196#endif 197static const struct dev_pm_ops igb_pm_ops = { 198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 200 igb_runtime_idle) 201}; 202#endif 203static void igb_shutdown(struct pci_dev *); 204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 205#ifdef CONFIG_IGB_DCA 206static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 207static struct notifier_block dca_notifier = { 208 .notifier_call = igb_notify_dca, 209 .next = NULL, 210 .priority = 0 211}; 212#endif 213#ifdef CONFIG_NET_POLL_CONTROLLER 214/* for netdump / net console */ 215static void igb_netpoll(struct net_device *); 216#endif 217#ifdef CONFIG_PCI_IOV 218static unsigned int max_vfs = 0; 219module_param(max_vfs, uint, 0); 220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " 221 "per physical function"); 222#endif /* CONFIG_PCI_IOV */ 223 224static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 225 pci_channel_state_t); 226static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 227static void igb_io_resume(struct pci_dev *); 228 229static const struct pci_error_handlers igb_err_handler = { 230 .error_detected = igb_io_error_detected, 231 .slot_reset = igb_io_slot_reset, 232 .resume = igb_io_resume, 233}; 234 235static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 236 237static struct pci_driver igb_driver = { 238 .name = igb_driver_name, 239 .id_table = igb_pci_tbl, 240 .probe = igb_probe, 241 .remove = igb_remove, 242#ifdef CONFIG_PM 243 .driver.pm = &igb_pm_ops, 244#endif 245 .shutdown = igb_shutdown, 246 .sriov_configure = igb_pci_sriov_configure, 247 .err_handler = &igb_err_handler 248}; 249 250MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 251MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 252MODULE_LICENSE("GPL"); 253MODULE_VERSION(DRV_VERSION); 254 255#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 256static int debug = -1; 257module_param(debug, int, 0); 258MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 259 260struct igb_reg_info { 261 u32 ofs; 262 char *name; 263}; 264 265static const struct igb_reg_info igb_reg_info_tbl[] = { 266 267 /* General Registers */ 268 {E1000_CTRL, "CTRL"}, 269 {E1000_STATUS, "STATUS"}, 270 {E1000_CTRL_EXT, "CTRL_EXT"}, 271 272 /* Interrupt Registers */ 273 {E1000_ICR, "ICR"}, 274 275 /* RX Registers */ 276 {E1000_RCTL, "RCTL"}, 277 {E1000_RDLEN(0), "RDLEN"}, 278 {E1000_RDH(0), "RDH"}, 279 {E1000_RDT(0), "RDT"}, 280 {E1000_RXDCTL(0), "RXDCTL"}, 281 {E1000_RDBAL(0), "RDBAL"}, 282 {E1000_RDBAH(0), "RDBAH"}, 283 284 /* TX Registers */ 285 {E1000_TCTL, "TCTL"}, 286 {E1000_TDBAL(0), "TDBAL"}, 287 {E1000_TDBAH(0), "TDBAH"}, 288 {E1000_TDLEN(0), "TDLEN"}, 289 {E1000_TDH(0), "TDH"}, 290 {E1000_TDT(0), "TDT"}, 291 {E1000_TXDCTL(0), "TXDCTL"}, 292 {E1000_TDFH, "TDFH"}, 293 {E1000_TDFT, "TDFT"}, 294 {E1000_TDFHS, "TDFHS"}, 295 {E1000_TDFPC, "TDFPC"}, 296 297 /* List Terminator */ 298 {} 299}; 300 301/* igb_regdump - register printout routine */ 302static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 303{ 304 int n = 0; 305 char rname[16]; 306 u32 regs[8]; 307 308 switch (reginfo->ofs) { 309 case E1000_RDLEN(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDLEN(n)); 312 break; 313 case E1000_RDH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDH(n)); 316 break; 317 case E1000_RDT(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_RDT(n)); 320 break; 321 case E1000_RXDCTL(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_RXDCTL(n)); 324 break; 325 case E1000_RDBAL(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_RDBAL(n)); 328 break; 329 case E1000_RDBAH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_RDBAH(n)); 332 break; 333 case E1000_TDBAL(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_RDBAL(n)); 336 break; 337 case E1000_TDBAH(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TDBAH(n)); 340 break; 341 case E1000_TDLEN(0): 342 for (n = 0; n < 4; n++) 343 regs[n] = rd32(E1000_TDLEN(n)); 344 break; 345 case E1000_TDH(0): 346 for (n = 0; n < 4; n++) 347 regs[n] = rd32(E1000_TDH(n)); 348 break; 349 case E1000_TDT(0): 350 for (n = 0; n < 4; n++) 351 regs[n] = rd32(E1000_TDT(n)); 352 break; 353 case E1000_TXDCTL(0): 354 for (n = 0; n < 4; n++) 355 regs[n] = rd32(E1000_TXDCTL(n)); 356 break; 357 default: 358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 359 return; 360 } 361 362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 364 regs[2], regs[3]); 365} 366 367/* igb_dump - Print registers, Tx-rings and Rx-rings */ 368static void igb_dump(struct igb_adapter *adapter) 369{ 370 struct net_device *netdev = adapter->netdev; 371 struct e1000_hw *hw = &adapter->hw; 372 struct igb_reg_info *reginfo; 373 struct igb_ring *tx_ring; 374 union e1000_adv_tx_desc *tx_desc; 375 struct my_u0 { u64 a; u64 b; } *u0; 376 struct igb_ring *rx_ring; 377 union e1000_adv_rx_desc *rx_desc; 378 u32 staterr; 379 u16 i, n; 380 381 if (!netif_msg_hw(adapter)) 382 return; 383 384 /* Print netdevice Info */ 385 if (netdev) { 386 dev_info(&adapter->pdev->dev, "Net device Info\n"); 387 pr_info("Device Name state trans_start " 388 "last_rx\n"); 389 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 390 netdev->state, netdev->trans_start, netdev->last_rx); 391 } 392 393 /* Print Registers */ 394 dev_info(&adapter->pdev->dev, "Register Dump\n"); 395 pr_info(" Register Name Value\n"); 396 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 397 reginfo->name; reginfo++) { 398 igb_regdump(hw, reginfo); 399 } 400 401 /* Print TX Ring Summary */ 402 if (!netdev || !netif_running(netdev)) 403 goto exit; 404 405 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 406 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 407 for (n = 0; n < adapter->num_tx_queues; n++) { 408 struct igb_tx_buffer *buffer_info; 409 tx_ring = adapter->tx_ring[n]; 410 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 411 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 412 n, tx_ring->next_to_use, tx_ring->next_to_clean, 413 (u64)dma_unmap_addr(buffer_info, dma), 414 dma_unmap_len(buffer_info, len), 415 buffer_info->next_to_watch, 416 (u64)buffer_info->time_stamp); 417 } 418 419 /* Print TX Rings */ 420 if (!netif_msg_tx_done(adapter)) 421 goto rx_ring_summary; 422 423 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 424 425 /* Transmit Descriptor Formats 426 * 427 * Advanced Transmit Descriptor 428 * +--------------------------------------------------------------+ 429 * 0 | Buffer Address [63:0] | 430 * +--------------------------------------------------------------+ 431 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 432 * +--------------------------------------------------------------+ 433 * 63 46 45 40 39 38 36 35 32 31 24 15 0 434 */ 435 436 for (n = 0; n < adapter->num_tx_queues; n++) { 437 tx_ring = adapter->tx_ring[n]; 438 pr_info("------------------------------------\n"); 439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 440 pr_info("------------------------------------\n"); 441 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] " 442 "[bi->dma ] leng ntw timestamp " 443 "bi->skb\n"); 444 445 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 446 const char *next_desc; 447 struct igb_tx_buffer *buffer_info; 448 tx_desc = IGB_TX_DESC(tx_ring, i); 449 buffer_info = &tx_ring->tx_buffer_info[i]; 450 u0 = (struct my_u0 *)tx_desc; 451 if (i == tx_ring->next_to_use && 452 i == tx_ring->next_to_clean) 453 next_desc = " NTC/U"; 454 else if (i == tx_ring->next_to_use) 455 next_desc = " NTU"; 456 else if (i == tx_ring->next_to_clean) 457 next_desc = " NTC"; 458 else 459 next_desc = ""; 460 461 pr_info("T [0x%03X] %016llX %016llX %016llX" 462 " %04X %p %016llX %p%s\n", i, 463 le64_to_cpu(u0->a), 464 le64_to_cpu(u0->b), 465 (u64)dma_unmap_addr(buffer_info, dma), 466 dma_unmap_len(buffer_info, len), 467 buffer_info->next_to_watch, 468 (u64)buffer_info->time_stamp, 469 buffer_info->skb, next_desc); 470 471 if (netif_msg_pktdata(adapter) && buffer_info->skb) 472 print_hex_dump(KERN_INFO, "", 473 DUMP_PREFIX_ADDRESS, 474 16, 1, buffer_info->skb->data, 475 dma_unmap_len(buffer_info, len), 476 true); 477 } 478 } 479 480 /* Print RX Rings Summary */ 481rx_ring_summary: 482 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 483 pr_info("Queue [NTU] [NTC]\n"); 484 for (n = 0; n < adapter->num_rx_queues; n++) { 485 rx_ring = adapter->rx_ring[n]; 486 pr_info(" %5d %5X %5X\n", 487 n, rx_ring->next_to_use, rx_ring->next_to_clean); 488 } 489 490 /* Print RX Rings */ 491 if (!netif_msg_rx_status(adapter)) 492 goto exit; 493 494 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 495 496 /* Advanced Receive Descriptor (Read) Format 497 * 63 1 0 498 * +-----------------------------------------------------+ 499 * 0 | Packet Buffer Address [63:1] |A0/NSE| 500 * +----------------------------------------------+------+ 501 * 8 | Header Buffer Address [63:1] | DD | 502 * +-----------------------------------------------------+ 503 * 504 * 505 * Advanced Receive Descriptor (Write-Back) Format 506 * 507 * 63 48 47 32 31 30 21 20 17 16 4 3 0 508 * +------------------------------------------------------+ 509 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 510 * | Checksum Ident | | | | Type | Type | 511 * +------------------------------------------------------+ 512 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 513 * +------------------------------------------------------+ 514 * 63 48 47 32 31 20 19 0 515 */ 516 517 for (n = 0; n < adapter->num_rx_queues; n++) { 518 rx_ring = adapter->rx_ring[n]; 519 pr_info("------------------------------------\n"); 520 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 521 pr_info("------------------------------------\n"); 522 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] " 523 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 524 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----" 525 "----------- [bi->skb] <-- Adv Rx Write-Back format\n"); 526 527 for (i = 0; i < rx_ring->count; i++) { 528 const char *next_desc; 529 struct igb_rx_buffer *buffer_info; 530 buffer_info = &rx_ring->rx_buffer_info[i]; 531 rx_desc = IGB_RX_DESC(rx_ring, i); 532 u0 = (struct my_u0 *)rx_desc; 533 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 534 535 if (i == rx_ring->next_to_use) 536 next_desc = " NTU"; 537 else if (i == rx_ring->next_to_clean) 538 next_desc = " NTC"; 539 else 540 next_desc = ""; 541 542 if (staterr & E1000_RXD_STAT_DD) { 543 /* Descriptor Done */ 544 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 545 "RWB", i, 546 le64_to_cpu(u0->a), 547 le64_to_cpu(u0->b), 548 next_desc); 549 } else { 550 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 551 "R ", i, 552 le64_to_cpu(u0->a), 553 le64_to_cpu(u0->b), 554 (u64)buffer_info->dma, 555 next_desc); 556 557 if (netif_msg_pktdata(adapter) && 558 buffer_info->dma && buffer_info->page) { 559 print_hex_dump(KERN_INFO, "", 560 DUMP_PREFIX_ADDRESS, 561 16, 1, 562 page_address(buffer_info->page) + 563 buffer_info->page_offset, 564 IGB_RX_BUFSZ, true); 565 } 566 } 567 } 568 } 569 570exit: 571 return; 572} 573 574/** 575 * igb_get_i2c_data - Reads the I2C SDA data bit 576 * @hw: pointer to hardware structure 577 * @i2cctl: Current value of I2CCTL register 578 * 579 * Returns the I2C data bit value 580 **/ 581static int igb_get_i2c_data(void *data) 582{ 583 struct igb_adapter *adapter = (struct igb_adapter *)data; 584 struct e1000_hw *hw = &adapter->hw; 585 s32 i2cctl = rd32(E1000_I2CPARAMS); 586 587 return ((i2cctl & E1000_I2C_DATA_IN) != 0); 588} 589 590/** 591 * igb_set_i2c_data - Sets the I2C data bit 592 * @data: pointer to hardware structure 593 * @state: I2C data value (0 or 1) to set 594 * 595 * Sets the I2C data bit 596 **/ 597static void igb_set_i2c_data(void *data, int state) 598{ 599 struct igb_adapter *adapter = (struct igb_adapter *)data; 600 struct e1000_hw *hw = &adapter->hw; 601 s32 i2cctl = rd32(E1000_I2CPARAMS); 602 603 if (state) 604 i2cctl |= E1000_I2C_DATA_OUT; 605 else 606 i2cctl &= ~E1000_I2C_DATA_OUT; 607 608 i2cctl &= ~E1000_I2C_DATA_OE_N; 609 i2cctl |= E1000_I2C_CLK_OE_N; 610 wr32(E1000_I2CPARAMS, i2cctl); 611 wrfl(); 612 613} 614 615/** 616 * igb_set_i2c_clk - Sets the I2C SCL clock 617 * @data: pointer to hardware structure 618 * @state: state to set clock 619 * 620 * Sets the I2C clock line to state 621 **/ 622static void igb_set_i2c_clk(void *data, int state) 623{ 624 struct igb_adapter *adapter = (struct igb_adapter *)data; 625 struct e1000_hw *hw = &adapter->hw; 626 s32 i2cctl = rd32(E1000_I2CPARAMS); 627 628 if (state) { 629 i2cctl |= E1000_I2C_CLK_OUT; 630 i2cctl &= ~E1000_I2C_CLK_OE_N; 631 } else { 632 i2cctl &= ~E1000_I2C_CLK_OUT; 633 i2cctl &= ~E1000_I2C_CLK_OE_N; 634 } 635 wr32(E1000_I2CPARAMS, i2cctl); 636 wrfl(); 637} 638 639/** 640 * igb_get_i2c_clk - Gets the I2C SCL clock state 641 * @data: pointer to hardware structure 642 * 643 * Gets the I2C clock state 644 **/ 645static int igb_get_i2c_clk(void *data) 646{ 647 struct igb_adapter *adapter = (struct igb_adapter *)data; 648 struct e1000_hw *hw = &adapter->hw; 649 s32 i2cctl = rd32(E1000_I2CPARAMS); 650 651 return ((i2cctl & E1000_I2C_CLK_IN) != 0); 652} 653 654static const struct i2c_algo_bit_data igb_i2c_algo = { 655 .setsda = igb_set_i2c_data, 656 .setscl = igb_set_i2c_clk, 657 .getsda = igb_get_i2c_data, 658 .getscl = igb_get_i2c_clk, 659 .udelay = 5, 660 .timeout = 20, 661}; 662 663/** 664 * igb_get_hw_dev - return device 665 * @hw: pointer to hardware structure 666 * 667 * used by hardware layer to print debugging information 668 **/ 669struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 670{ 671 struct igb_adapter *adapter = hw->back; 672 return adapter->netdev; 673} 674 675/** 676 * igb_init_module - Driver Registration Routine 677 * 678 * igb_init_module is the first routine called when the driver is 679 * loaded. All it does is register with the PCI subsystem. 680 **/ 681static int __init igb_init_module(void) 682{ 683 int ret; 684 pr_info("%s - version %s\n", 685 igb_driver_string, igb_driver_version); 686 687 pr_info("%s\n", igb_copyright); 688 689#ifdef CONFIG_IGB_DCA 690 dca_register_notify(&dca_notifier); 691#endif 692 ret = pci_register_driver(&igb_driver); 693 return ret; 694} 695 696module_init(igb_init_module); 697 698/** 699 * igb_exit_module - Driver Exit Cleanup Routine 700 * 701 * igb_exit_module is called just before the driver is removed 702 * from memory. 703 **/ 704static void __exit igb_exit_module(void) 705{ 706#ifdef CONFIG_IGB_DCA 707 dca_unregister_notify(&dca_notifier); 708#endif 709 pci_unregister_driver(&igb_driver); 710} 711 712module_exit(igb_exit_module); 713 714#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 715/** 716 * igb_cache_ring_register - Descriptor ring to register mapping 717 * @adapter: board private structure to initialize 718 * 719 * Once we know the feature-set enabled for the device, we'll cache 720 * the register offset the descriptor ring is assigned to. 721 **/ 722static void igb_cache_ring_register(struct igb_adapter *adapter) 723{ 724 int i = 0, j = 0; 725 u32 rbase_offset = adapter->vfs_allocated_count; 726 727 switch (adapter->hw.mac.type) { 728 case e1000_82576: 729 /* The queues are allocated for virtualization such that VF 0 730 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 731 * In order to avoid collision we start at the first free queue 732 * and continue consuming queues in the same sequence 733 */ 734 if (adapter->vfs_allocated_count) { 735 for (; i < adapter->rss_queues; i++) 736 adapter->rx_ring[i]->reg_idx = rbase_offset + 737 Q_IDX_82576(i); 738 } 739 case e1000_82575: 740 case e1000_82580: 741 case e1000_i350: 742 case e1000_i354: 743 case e1000_i210: 744 case e1000_i211: 745 default: 746 for (; i < adapter->num_rx_queues; i++) 747 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 748 for (; j < adapter->num_tx_queues; j++) 749 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 750 break; 751 } 752} 753 754u32 igb_rd32(struct e1000_hw *hw, u32 reg) 755{ 756 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 757 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 758 u32 value = 0; 759 760 if (E1000_REMOVED(hw_addr)) 761 return ~value; 762 763 value = readl(&hw_addr[reg]); 764 765 /* reads should not return all F's */ 766 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 767 struct net_device *netdev = igb->netdev; 768 hw->hw_addr = NULL; 769 netif_device_detach(netdev); 770 netdev_err(netdev, "PCIe link lost, device now detached\n"); 771 } 772 773 return value; 774} 775 776/** 777 * igb_write_ivar - configure ivar for given MSI-X vector 778 * @hw: pointer to the HW structure 779 * @msix_vector: vector number we are allocating to a given ring 780 * @index: row index of IVAR register to write within IVAR table 781 * @offset: column offset of in IVAR, should be multiple of 8 782 * 783 * This function is intended to handle the writing of the IVAR register 784 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 785 * each containing an cause allocation for an Rx and Tx ring, and a 786 * variable number of rows depending on the number of queues supported. 787 **/ 788static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 789 int index, int offset) 790{ 791 u32 ivar = array_rd32(E1000_IVAR0, index); 792 793 /* clear any bits that are currently set */ 794 ivar &= ~((u32)0xFF << offset); 795 796 /* write vector and valid bit */ 797 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 798 799 array_wr32(E1000_IVAR0, index, ivar); 800} 801 802#define IGB_N0_QUEUE -1 803static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 804{ 805 struct igb_adapter *adapter = q_vector->adapter; 806 struct e1000_hw *hw = &adapter->hw; 807 int rx_queue = IGB_N0_QUEUE; 808 int tx_queue = IGB_N0_QUEUE; 809 u32 msixbm = 0; 810 811 if (q_vector->rx.ring) 812 rx_queue = q_vector->rx.ring->reg_idx; 813 if (q_vector->tx.ring) 814 tx_queue = q_vector->tx.ring->reg_idx; 815 816 switch (hw->mac.type) { 817 case e1000_82575: 818 /* The 82575 assigns vectors using a bitmask, which matches the 819 * bitmask for the EICR/EIMS/EIMC registers. To assign one 820 * or more queues to a vector, we write the appropriate bits 821 * into the MSIXBM register for that vector. 822 */ 823 if (rx_queue > IGB_N0_QUEUE) 824 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 825 if (tx_queue > IGB_N0_QUEUE) 826 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 827 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 828 msixbm |= E1000_EIMS_OTHER; 829 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 830 q_vector->eims_value = msixbm; 831 break; 832 case e1000_82576: 833 /* 82576 uses a table that essentially consists of 2 columns 834 * with 8 rows. The ordering is column-major so we use the 835 * lower 3 bits as the row index, and the 4th bit as the 836 * column offset. 837 */ 838 if (rx_queue > IGB_N0_QUEUE) 839 igb_write_ivar(hw, msix_vector, 840 rx_queue & 0x7, 841 (rx_queue & 0x8) << 1); 842 if (tx_queue > IGB_N0_QUEUE) 843 igb_write_ivar(hw, msix_vector, 844 tx_queue & 0x7, 845 ((tx_queue & 0x8) << 1) + 8); 846 q_vector->eims_value = 1 << msix_vector; 847 break; 848 case e1000_82580: 849 case e1000_i350: 850 case e1000_i354: 851 case e1000_i210: 852 case e1000_i211: 853 /* On 82580 and newer adapters the scheme is similar to 82576 854 * however instead of ordering column-major we have things 855 * ordered row-major. So we traverse the table by using 856 * bit 0 as the column offset, and the remaining bits as the 857 * row index. 858 */ 859 if (rx_queue > IGB_N0_QUEUE) 860 igb_write_ivar(hw, msix_vector, 861 rx_queue >> 1, 862 (rx_queue & 0x1) << 4); 863 if (tx_queue > IGB_N0_QUEUE) 864 igb_write_ivar(hw, msix_vector, 865 tx_queue >> 1, 866 ((tx_queue & 0x1) << 4) + 8); 867 q_vector->eims_value = 1 << msix_vector; 868 break; 869 default: 870 BUG(); 871 break; 872 } 873 874 /* add q_vector eims value to global eims_enable_mask */ 875 adapter->eims_enable_mask |= q_vector->eims_value; 876 877 /* configure q_vector to set itr on first interrupt */ 878 q_vector->set_itr = 1; 879} 880 881/** 882 * igb_configure_msix - Configure MSI-X hardware 883 * @adapter: board private structure to initialize 884 * 885 * igb_configure_msix sets up the hardware to properly 886 * generate MSI-X interrupts. 887 **/ 888static void igb_configure_msix(struct igb_adapter *adapter) 889{ 890 u32 tmp; 891 int i, vector = 0; 892 struct e1000_hw *hw = &adapter->hw; 893 894 adapter->eims_enable_mask = 0; 895 896 /* set vector for other causes, i.e. link changes */ 897 switch (hw->mac.type) { 898 case e1000_82575: 899 tmp = rd32(E1000_CTRL_EXT); 900 /* enable MSI-X PBA support*/ 901 tmp |= E1000_CTRL_EXT_PBA_CLR; 902 903 /* Auto-Mask interrupts upon ICR read. */ 904 tmp |= E1000_CTRL_EXT_EIAME; 905 tmp |= E1000_CTRL_EXT_IRCA; 906 907 wr32(E1000_CTRL_EXT, tmp); 908 909 /* enable msix_other interrupt */ 910 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 911 adapter->eims_other = E1000_EIMS_OTHER; 912 913 break; 914 915 case e1000_82576: 916 case e1000_82580: 917 case e1000_i350: 918 case e1000_i354: 919 case e1000_i210: 920 case e1000_i211: 921 /* Turn on MSI-X capability first, or our settings 922 * won't stick. And it will take days to debug. 923 */ 924 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 925 E1000_GPIE_PBA | E1000_GPIE_EIAME | 926 E1000_GPIE_NSICR); 927 928 /* enable msix_other interrupt */ 929 adapter->eims_other = 1 << vector; 930 tmp = (vector++ | E1000_IVAR_VALID) << 8; 931 932 wr32(E1000_IVAR_MISC, tmp); 933 break; 934 default: 935 /* do nothing, since nothing else supports MSI-X */ 936 break; 937 } /* switch (hw->mac.type) */ 938 939 adapter->eims_enable_mask |= adapter->eims_other; 940 941 for (i = 0; i < adapter->num_q_vectors; i++) 942 igb_assign_vector(adapter->q_vector[i], vector++); 943 944 wrfl(); 945} 946 947/** 948 * igb_request_msix - Initialize MSI-X interrupts 949 * @adapter: board private structure to initialize 950 * 951 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 952 * kernel. 953 **/ 954static int igb_request_msix(struct igb_adapter *adapter) 955{ 956 struct net_device *netdev = adapter->netdev; 957 struct e1000_hw *hw = &adapter->hw; 958 int i, err = 0, vector = 0, free_vector = 0; 959 960 err = request_irq(adapter->msix_entries[vector].vector, 961 igb_msix_other, 0, netdev->name, adapter); 962 if (err) 963 goto err_out; 964 965 for (i = 0; i < adapter->num_q_vectors; i++) { 966 struct igb_q_vector *q_vector = adapter->q_vector[i]; 967 968 vector++; 969 970 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 971 972 if (q_vector->rx.ring && q_vector->tx.ring) 973 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 974 q_vector->rx.ring->queue_index); 975 else if (q_vector->tx.ring) 976 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 977 q_vector->tx.ring->queue_index); 978 else if (q_vector->rx.ring) 979 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 980 q_vector->rx.ring->queue_index); 981 else 982 sprintf(q_vector->name, "%s-unused", netdev->name); 983 984 err = request_irq(adapter->msix_entries[vector].vector, 985 igb_msix_ring, 0, q_vector->name, 986 q_vector); 987 if (err) 988 goto err_free; 989 } 990 991 igb_configure_msix(adapter); 992 return 0; 993 994err_free: 995 /* free already assigned IRQs */ 996 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 997 998 vector--; 999 for (i = 0; i < vector; i++) { 1000 free_irq(adapter->msix_entries[free_vector++].vector, 1001 adapter->q_vector[i]); 1002 } 1003err_out: 1004 return err; 1005} 1006 1007/** 1008 * igb_free_q_vector - Free memory allocated for specific interrupt vector 1009 * @adapter: board private structure to initialize 1010 * @v_idx: Index of vector to be freed 1011 * 1012 * This function frees the memory allocated to the q_vector. 1013 **/ 1014static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1015{ 1016 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1017 1018 adapter->q_vector[v_idx] = NULL; 1019 1020 /* igb_get_stats64() might access the rings on this vector, 1021 * we must wait a grace period before freeing it. 1022 */ 1023 kfree_rcu(q_vector, rcu); 1024} 1025 1026/** 1027 * igb_reset_q_vector - Reset config for interrupt vector 1028 * @adapter: board private structure to initialize 1029 * @v_idx: Index of vector to be reset 1030 * 1031 * If NAPI is enabled it will delete any references to the 1032 * NAPI struct. This is preparation for igb_free_q_vector. 1033 **/ 1034static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1035{ 1036 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1037 1038 if (q_vector->tx.ring) 1039 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1040 1041 if (q_vector->rx.ring) 1042 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; 1043 1044 netif_napi_del(&q_vector->napi); 1045 1046} 1047 1048static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1049{ 1050 int v_idx = adapter->num_q_vectors; 1051 1052 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1053 pci_disable_msix(adapter->pdev); 1054 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1055 pci_disable_msi(adapter->pdev); 1056 1057 while (v_idx--) 1058 igb_reset_q_vector(adapter, v_idx); 1059} 1060 1061/** 1062 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1063 * @adapter: board private structure to initialize 1064 * 1065 * This function frees the memory allocated to the q_vectors. In addition if 1066 * NAPI is enabled it will delete any references to the NAPI struct prior 1067 * to freeing the q_vector. 1068 **/ 1069static void igb_free_q_vectors(struct igb_adapter *adapter) 1070{ 1071 int v_idx = adapter->num_q_vectors; 1072 1073 adapter->num_tx_queues = 0; 1074 adapter->num_rx_queues = 0; 1075 adapter->num_q_vectors = 0; 1076 1077 while (v_idx--) { 1078 igb_reset_q_vector(adapter, v_idx); 1079 igb_free_q_vector(adapter, v_idx); 1080 } 1081} 1082 1083/** 1084 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1085 * @adapter: board private structure to initialize 1086 * 1087 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1088 * MSI-X interrupts allocated. 1089 */ 1090static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1091{ 1092 igb_free_q_vectors(adapter); 1093 igb_reset_interrupt_capability(adapter); 1094} 1095 1096/** 1097 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1098 * @adapter: board private structure to initialize 1099 * @msix: boolean value of MSIX capability 1100 * 1101 * Attempt to configure interrupts using the best available 1102 * capabilities of the hardware and kernel. 1103 **/ 1104static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1105{ 1106 int err; 1107 int numvecs, i; 1108 1109 if (!msix) 1110 goto msi_only; 1111 adapter->flags |= IGB_FLAG_HAS_MSIX; 1112 1113 /* Number of supported queues. */ 1114 adapter->num_rx_queues = adapter->rss_queues; 1115 if (adapter->vfs_allocated_count) 1116 adapter->num_tx_queues = 1; 1117 else 1118 adapter->num_tx_queues = adapter->rss_queues; 1119 1120 /* start with one vector for every Rx queue */ 1121 numvecs = adapter->num_rx_queues; 1122 1123 /* if Tx handler is separate add 1 for every Tx queue */ 1124 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1125 numvecs += adapter->num_tx_queues; 1126 1127 /* store the number of vectors reserved for queues */ 1128 adapter->num_q_vectors = numvecs; 1129 1130 /* add 1 vector for link status interrupts */ 1131 numvecs++; 1132 for (i = 0; i < numvecs; i++) 1133 adapter->msix_entries[i].entry = i; 1134 1135 err = pci_enable_msix_range(adapter->pdev, 1136 adapter->msix_entries, 1137 numvecs, 1138 numvecs); 1139 if (err > 0) 1140 return; 1141 1142 igb_reset_interrupt_capability(adapter); 1143 1144 /* If we can't do MSI-X, try MSI */ 1145msi_only: 1146#ifdef CONFIG_PCI_IOV 1147 /* disable SR-IOV for non MSI-X configurations */ 1148 if (adapter->vf_data) { 1149 struct e1000_hw *hw = &adapter->hw; 1150 /* disable iov and allow time for transactions to clear */ 1151 pci_disable_sriov(adapter->pdev); 1152 msleep(500); 1153 1154 kfree(adapter->vf_data); 1155 adapter->vf_data = NULL; 1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1157 wrfl(); 1158 msleep(100); 1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1160 } 1161#endif 1162 adapter->vfs_allocated_count = 0; 1163 adapter->rss_queues = 1; 1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1165 adapter->num_rx_queues = 1; 1166 adapter->num_tx_queues = 1; 1167 adapter->num_q_vectors = 1; 1168 if (!pci_enable_msi(adapter->pdev)) 1169 adapter->flags |= IGB_FLAG_HAS_MSI; 1170} 1171 1172static void igb_add_ring(struct igb_ring *ring, 1173 struct igb_ring_container *head) 1174{ 1175 head->ring = ring; 1176 head->count++; 1177} 1178 1179/** 1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1181 * @adapter: board private structure to initialize 1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1183 * @v_idx: index of vector in adapter struct 1184 * @txr_count: total number of Tx rings to allocate 1185 * @txr_idx: index of first Tx ring to allocate 1186 * @rxr_count: total number of Rx rings to allocate 1187 * @rxr_idx: index of first Rx ring to allocate 1188 * 1189 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1190 **/ 1191static int igb_alloc_q_vector(struct igb_adapter *adapter, 1192 int v_count, int v_idx, 1193 int txr_count, int txr_idx, 1194 int rxr_count, int rxr_idx) 1195{ 1196 struct igb_q_vector *q_vector; 1197 struct igb_ring *ring; 1198 int ring_count, size; 1199 1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1201 if (txr_count > 1 || rxr_count > 1) 1202 return -ENOMEM; 1203 1204 ring_count = txr_count + rxr_count; 1205 size = sizeof(struct igb_q_vector) + 1206 (sizeof(struct igb_ring) * ring_count); 1207 1208 /* allocate q_vector and rings */ 1209 q_vector = adapter->q_vector[v_idx]; 1210 if (!q_vector) 1211 q_vector = kzalloc(size, GFP_KERNEL); 1212 if (!q_vector) 1213 return -ENOMEM; 1214 1215 /* initialize NAPI */ 1216 netif_napi_add(adapter->netdev, &q_vector->napi, 1217 igb_poll, 64); 1218 1219 /* tie q_vector and adapter together */ 1220 adapter->q_vector[v_idx] = q_vector; 1221 q_vector->adapter = adapter; 1222 1223 /* initialize work limits */ 1224 q_vector->tx.work_limit = adapter->tx_work_limit; 1225 1226 /* initialize ITR configuration */ 1227 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); 1228 q_vector->itr_val = IGB_START_ITR; 1229 1230 /* initialize pointer to rings */ 1231 ring = q_vector->ring; 1232 1233 /* intialize ITR */ 1234 if (rxr_count) { 1235 /* rx or rx/tx vector */ 1236 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1237 q_vector->itr_val = adapter->rx_itr_setting; 1238 } else { 1239 /* tx only vector */ 1240 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1241 q_vector->itr_val = adapter->tx_itr_setting; 1242 } 1243 1244 if (txr_count) { 1245 /* assign generic ring traits */ 1246 ring->dev = &adapter->pdev->dev; 1247 ring->netdev = adapter->netdev; 1248 1249 /* configure backlink on ring */ 1250 ring->q_vector = q_vector; 1251 1252 /* update q_vector Tx values */ 1253 igb_add_ring(ring, &q_vector->tx); 1254 1255 /* For 82575, context index must be unique per ring. */ 1256 if (adapter->hw.mac.type == e1000_82575) 1257 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1258 1259 /* apply Tx specific ring traits */ 1260 ring->count = adapter->tx_ring_count; 1261 ring->queue_index = txr_idx; 1262 1263 u64_stats_init(&ring->tx_syncp); 1264 u64_stats_init(&ring->tx_syncp2); 1265 1266 /* assign ring to adapter */ 1267 adapter->tx_ring[txr_idx] = ring; 1268 1269 /* push pointer to next ring */ 1270 ring++; 1271 } 1272 1273 if (rxr_count) { 1274 /* assign generic ring traits */ 1275 ring->dev = &adapter->pdev->dev; 1276 ring->netdev = adapter->netdev; 1277 1278 /* configure backlink on ring */ 1279 ring->q_vector = q_vector; 1280 1281 /* update q_vector Rx values */ 1282 igb_add_ring(ring, &q_vector->rx); 1283 1284 /* set flag indicating ring supports SCTP checksum offload */ 1285 if (adapter->hw.mac.type >= e1000_82576) 1286 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1287 1288 /* 1289 * On i350, i354, i210, and i211, loopback VLAN packets 1290 * have the tag byte-swapped. 1291 */ 1292 if (adapter->hw.mac.type >= e1000_i350) 1293 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1294 1295 /* apply Rx specific ring traits */ 1296 ring->count = adapter->rx_ring_count; 1297 ring->queue_index = rxr_idx; 1298 1299 u64_stats_init(&ring->rx_syncp); 1300 1301 /* assign ring to adapter */ 1302 adapter->rx_ring[rxr_idx] = ring; 1303 } 1304 1305 return 0; 1306} 1307 1308 1309/** 1310 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1311 * @adapter: board private structure to initialize 1312 * 1313 * We allocate one q_vector per queue interrupt. If allocation fails we 1314 * return -ENOMEM. 1315 **/ 1316static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1317{ 1318 int q_vectors = adapter->num_q_vectors; 1319 int rxr_remaining = adapter->num_rx_queues; 1320 int txr_remaining = adapter->num_tx_queues; 1321 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1322 int err; 1323 1324 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1325 for (; rxr_remaining; v_idx++) { 1326 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1327 0, 0, 1, rxr_idx); 1328 1329 if (err) 1330 goto err_out; 1331 1332 /* update counts and index */ 1333 rxr_remaining--; 1334 rxr_idx++; 1335 } 1336 } 1337 1338 for (; v_idx < q_vectors; v_idx++) { 1339 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1340 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1341 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1342 tqpv, txr_idx, rqpv, rxr_idx); 1343 1344 if (err) 1345 goto err_out; 1346 1347 /* update counts and index */ 1348 rxr_remaining -= rqpv; 1349 txr_remaining -= tqpv; 1350 rxr_idx++; 1351 txr_idx++; 1352 } 1353 1354 return 0; 1355 1356err_out: 1357 adapter->num_tx_queues = 0; 1358 adapter->num_rx_queues = 0; 1359 adapter->num_q_vectors = 0; 1360 1361 while (v_idx--) 1362 igb_free_q_vector(adapter, v_idx); 1363 1364 return -ENOMEM; 1365} 1366 1367/** 1368 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1369 * @adapter: board private structure to initialize 1370 * @msix: boolean value of MSIX capability 1371 * 1372 * This function initializes the interrupts and allocates all of the queues. 1373 **/ 1374static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1375{ 1376 struct pci_dev *pdev = adapter->pdev; 1377 int err; 1378 1379 igb_set_interrupt_capability(adapter, msix); 1380 1381 err = igb_alloc_q_vectors(adapter); 1382 if (err) { 1383 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1384 goto err_alloc_q_vectors; 1385 } 1386 1387 igb_cache_ring_register(adapter); 1388 1389 return 0; 1390 1391err_alloc_q_vectors: 1392 igb_reset_interrupt_capability(adapter); 1393 return err; 1394} 1395 1396/** 1397 * igb_request_irq - initialize interrupts 1398 * @adapter: board private structure to initialize 1399 * 1400 * Attempts to configure interrupts using the best available 1401 * capabilities of the hardware and kernel. 1402 **/ 1403static int igb_request_irq(struct igb_adapter *adapter) 1404{ 1405 struct net_device *netdev = adapter->netdev; 1406 struct pci_dev *pdev = adapter->pdev; 1407 int err = 0; 1408 1409 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1410 err = igb_request_msix(adapter); 1411 if (!err) 1412 goto request_done; 1413 /* fall back to MSI */ 1414 igb_free_all_tx_resources(adapter); 1415 igb_free_all_rx_resources(adapter); 1416 1417 igb_clear_interrupt_scheme(adapter); 1418 err = igb_init_interrupt_scheme(adapter, false); 1419 if (err) 1420 goto request_done; 1421 1422 igb_setup_all_tx_resources(adapter); 1423 igb_setup_all_rx_resources(adapter); 1424 igb_configure(adapter); 1425 } 1426 1427 igb_assign_vector(adapter->q_vector[0], 0); 1428 1429 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1430 err = request_irq(pdev->irq, igb_intr_msi, 0, 1431 netdev->name, adapter); 1432 if (!err) 1433 goto request_done; 1434 1435 /* fall back to legacy interrupts */ 1436 igb_reset_interrupt_capability(adapter); 1437 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1438 } 1439 1440 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1441 netdev->name, adapter); 1442 1443 if (err) 1444 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1445 err); 1446 1447request_done: 1448 return err; 1449} 1450 1451static void igb_free_irq(struct igb_adapter *adapter) 1452{ 1453 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1454 int vector = 0, i; 1455 1456 free_irq(adapter->msix_entries[vector++].vector, adapter); 1457 1458 for (i = 0; i < adapter->num_q_vectors; i++) 1459 free_irq(adapter->msix_entries[vector++].vector, 1460 adapter->q_vector[i]); 1461 } else { 1462 free_irq(adapter->pdev->irq, adapter); 1463 } 1464} 1465 1466/** 1467 * igb_irq_disable - Mask off interrupt generation on the NIC 1468 * @adapter: board private structure 1469 **/ 1470static void igb_irq_disable(struct igb_adapter *adapter) 1471{ 1472 struct e1000_hw *hw = &adapter->hw; 1473 1474 /* we need to be careful when disabling interrupts. The VFs are also 1475 * mapped into these registers and so clearing the bits can cause 1476 * issues on the VF drivers so we only need to clear what we set 1477 */ 1478 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1479 u32 regval = rd32(E1000_EIAM); 1480 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1481 wr32(E1000_EIMC, adapter->eims_enable_mask); 1482 regval = rd32(E1000_EIAC); 1483 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1484 } 1485 1486 wr32(E1000_IAM, 0); 1487 wr32(E1000_IMC, ~0); 1488 wrfl(); 1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1490 int i; 1491 for (i = 0; i < adapter->num_q_vectors; i++) 1492 synchronize_irq(adapter->msix_entries[i].vector); 1493 } else { 1494 synchronize_irq(adapter->pdev->irq); 1495 } 1496} 1497 1498/** 1499 * igb_irq_enable - Enable default interrupt generation settings 1500 * @adapter: board private structure 1501 **/ 1502static void igb_irq_enable(struct igb_adapter *adapter) 1503{ 1504 struct e1000_hw *hw = &adapter->hw; 1505 1506 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1507 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1508 u32 regval = rd32(E1000_EIAC); 1509 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1510 regval = rd32(E1000_EIAM); 1511 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1512 wr32(E1000_EIMS, adapter->eims_enable_mask); 1513 if (adapter->vfs_allocated_count) { 1514 wr32(E1000_MBVFIMR, 0xFF); 1515 ims |= E1000_IMS_VMMB; 1516 } 1517 wr32(E1000_IMS, ims); 1518 } else { 1519 wr32(E1000_IMS, IMS_ENABLE_MASK | 1520 E1000_IMS_DRSTA); 1521 wr32(E1000_IAM, IMS_ENABLE_MASK | 1522 E1000_IMS_DRSTA); 1523 } 1524} 1525 1526static void igb_update_mng_vlan(struct igb_adapter *adapter) 1527{ 1528 struct e1000_hw *hw = &adapter->hw; 1529 u16 vid = adapter->hw.mng_cookie.vlan_id; 1530 u16 old_vid = adapter->mng_vlan_id; 1531 1532 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1533 /* add VID to filter table */ 1534 igb_vfta_set(hw, vid, true); 1535 adapter->mng_vlan_id = vid; 1536 } else { 1537 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1538 } 1539 1540 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1541 (vid != old_vid) && 1542 !test_bit(old_vid, adapter->active_vlans)) { 1543 /* remove VID from filter table */ 1544 igb_vfta_set(hw, old_vid, false); 1545 } 1546} 1547 1548/** 1549 * igb_release_hw_control - release control of the h/w to f/w 1550 * @adapter: address of board private structure 1551 * 1552 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1553 * For ASF and Pass Through versions of f/w this means that the 1554 * driver is no longer loaded. 1555 **/ 1556static void igb_release_hw_control(struct igb_adapter *adapter) 1557{ 1558 struct e1000_hw *hw = &adapter->hw; 1559 u32 ctrl_ext; 1560 1561 /* Let firmware take over control of h/w */ 1562 ctrl_ext = rd32(E1000_CTRL_EXT); 1563 wr32(E1000_CTRL_EXT, 1564 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1565} 1566 1567/** 1568 * igb_get_hw_control - get control of the h/w from f/w 1569 * @adapter: address of board private structure 1570 * 1571 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1572 * For ASF and Pass Through versions of f/w this means that 1573 * the driver is loaded. 1574 **/ 1575static void igb_get_hw_control(struct igb_adapter *adapter) 1576{ 1577 struct e1000_hw *hw = &adapter->hw; 1578 u32 ctrl_ext; 1579 1580 /* Let firmware know the driver has taken over */ 1581 ctrl_ext = rd32(E1000_CTRL_EXT); 1582 wr32(E1000_CTRL_EXT, 1583 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1584} 1585 1586/** 1587 * igb_configure - configure the hardware for RX and TX 1588 * @adapter: private board structure 1589 **/ 1590static void igb_configure(struct igb_adapter *adapter) 1591{ 1592 struct net_device *netdev = adapter->netdev; 1593 int i; 1594 1595 igb_get_hw_control(adapter); 1596 igb_set_rx_mode(netdev); 1597 1598 igb_restore_vlan(adapter); 1599 1600 igb_setup_tctl(adapter); 1601 igb_setup_mrqc(adapter); 1602 igb_setup_rctl(adapter); 1603 1604 igb_configure_tx(adapter); 1605 igb_configure_rx(adapter); 1606 1607 igb_rx_fifo_flush_82575(&adapter->hw); 1608 1609 /* call igb_desc_unused which always leaves 1610 * at least 1 descriptor unused to make sure 1611 * next_to_use != next_to_clean 1612 */ 1613 for (i = 0; i < adapter->num_rx_queues; i++) { 1614 struct igb_ring *ring = adapter->rx_ring[i]; 1615 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1616 } 1617} 1618 1619/** 1620 * igb_power_up_link - Power up the phy/serdes link 1621 * @adapter: address of board private structure 1622 **/ 1623void igb_power_up_link(struct igb_adapter *adapter) 1624{ 1625 igb_reset_phy(&adapter->hw); 1626 1627 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1628 igb_power_up_phy_copper(&adapter->hw); 1629 else 1630 igb_power_up_serdes_link_82575(&adapter->hw); 1631} 1632 1633/** 1634 * igb_power_down_link - Power down the phy/serdes link 1635 * @adapter: address of board private structure 1636 */ 1637static void igb_power_down_link(struct igb_adapter *adapter) 1638{ 1639 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1640 igb_power_down_phy_copper_82575(&adapter->hw); 1641 else 1642 igb_shutdown_serdes_link_82575(&adapter->hw); 1643} 1644 1645/** 1646 * Detect and switch function for Media Auto Sense 1647 * @adapter: address of the board private structure 1648 **/ 1649static void igb_check_swap_media(struct igb_adapter *adapter) 1650{ 1651 struct e1000_hw *hw = &adapter->hw; 1652 u32 ctrl_ext, connsw; 1653 bool swap_now = false; 1654 1655 ctrl_ext = rd32(E1000_CTRL_EXT); 1656 connsw = rd32(E1000_CONNSW); 1657 1658 /* need to live swap if current media is copper and we have fiber/serdes 1659 * to go to. 1660 */ 1661 1662 if ((hw->phy.media_type == e1000_media_type_copper) && 1663 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1664 swap_now = true; 1665 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1666 /* copper signal takes time to appear */ 1667 if (adapter->copper_tries < 4) { 1668 adapter->copper_tries++; 1669 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1670 wr32(E1000_CONNSW, connsw); 1671 return; 1672 } else { 1673 adapter->copper_tries = 0; 1674 if ((connsw & E1000_CONNSW_PHYSD) && 1675 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1676 swap_now = true; 1677 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1678 wr32(E1000_CONNSW, connsw); 1679 } 1680 } 1681 } 1682 1683 if (!swap_now) 1684 return; 1685 1686 switch (hw->phy.media_type) { 1687 case e1000_media_type_copper: 1688 netdev_info(adapter->netdev, 1689 "MAS: changing media to fiber/serdes\n"); 1690 ctrl_ext |= 1691 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1692 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1693 adapter->copper_tries = 0; 1694 break; 1695 case e1000_media_type_internal_serdes: 1696 case e1000_media_type_fiber: 1697 netdev_info(adapter->netdev, 1698 "MAS: changing media to copper\n"); 1699 ctrl_ext &= 1700 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1701 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1702 break; 1703 default: 1704 /* shouldn't get here during regular operation */ 1705 netdev_err(adapter->netdev, 1706 "AMS: Invalid media type found, returning\n"); 1707 break; 1708 } 1709 wr32(E1000_CTRL_EXT, ctrl_ext); 1710} 1711 1712/** 1713 * igb_up - Open the interface and prepare it to handle traffic 1714 * @adapter: board private structure 1715 **/ 1716int igb_up(struct igb_adapter *adapter) 1717{ 1718 struct e1000_hw *hw = &adapter->hw; 1719 int i; 1720 1721 /* hardware has been reset, we need to reload some things */ 1722 igb_configure(adapter); 1723 1724 clear_bit(__IGB_DOWN, &adapter->state); 1725 1726 for (i = 0; i < adapter->num_q_vectors; i++) 1727 napi_enable(&(adapter->q_vector[i]->napi)); 1728 1729 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1730 igb_configure_msix(adapter); 1731 else 1732 igb_assign_vector(adapter->q_vector[0], 0); 1733 1734 /* Clear any pending interrupts. */ 1735 rd32(E1000_ICR); 1736 igb_irq_enable(adapter); 1737 1738 /* notify VFs that reset has been completed */ 1739 if (adapter->vfs_allocated_count) { 1740 u32 reg_data = rd32(E1000_CTRL_EXT); 1741 reg_data |= E1000_CTRL_EXT_PFRSTD; 1742 wr32(E1000_CTRL_EXT, reg_data); 1743 } 1744 1745 netif_tx_start_all_queues(adapter->netdev); 1746 1747 /* start the watchdog. */ 1748 hw->mac.get_link_status = 1; 1749 schedule_work(&adapter->watchdog_task); 1750 1751 if ((adapter->flags & IGB_FLAG_EEE) && 1752 (!hw->dev_spec._82575.eee_disable)) 1753 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1754 1755 return 0; 1756} 1757 1758void igb_down(struct igb_adapter *adapter) 1759{ 1760 struct net_device *netdev = adapter->netdev; 1761 struct e1000_hw *hw = &adapter->hw; 1762 u32 tctl, rctl; 1763 int i; 1764 1765 /* signal that we're down so the interrupt handler does not 1766 * reschedule our watchdog timer 1767 */ 1768 set_bit(__IGB_DOWN, &adapter->state); 1769 1770 /* disable receives in the hardware */ 1771 rctl = rd32(E1000_RCTL); 1772 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1773 /* flush and sleep below */ 1774 1775 netif_tx_stop_all_queues(netdev); 1776 1777 /* disable transmits in the hardware */ 1778 tctl = rd32(E1000_TCTL); 1779 tctl &= ~E1000_TCTL_EN; 1780 wr32(E1000_TCTL, tctl); 1781 /* flush both disables and wait for them to finish */ 1782 wrfl(); 1783 msleep(10); 1784 1785 igb_irq_disable(adapter); 1786 1787 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1788 1789 for (i = 0; i < adapter->num_q_vectors; i++) { 1790 napi_synchronize(&(adapter->q_vector[i]->napi)); 1791 napi_disable(&(adapter->q_vector[i]->napi)); 1792 } 1793 1794 1795 del_timer_sync(&adapter->watchdog_timer); 1796 del_timer_sync(&adapter->phy_info_timer); 1797 1798 netif_carrier_off(netdev); 1799 1800 /* record the stats before reset*/ 1801 spin_lock(&adapter->stats64_lock); 1802 igb_update_stats(adapter, &adapter->stats64); 1803 spin_unlock(&adapter->stats64_lock); 1804 1805 adapter->link_speed = 0; 1806 adapter->link_duplex = 0; 1807 1808 if (!pci_channel_offline(adapter->pdev)) 1809 igb_reset(adapter); 1810 igb_clean_all_tx_rings(adapter); 1811 igb_clean_all_rx_rings(adapter); 1812#ifdef CONFIG_IGB_DCA 1813 1814 /* since we reset the hardware DCA settings were cleared */ 1815 igb_setup_dca(adapter); 1816#endif 1817} 1818 1819void igb_reinit_locked(struct igb_adapter *adapter) 1820{ 1821 WARN_ON(in_interrupt()); 1822 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1823 msleep(1); 1824 igb_down(adapter); 1825 igb_up(adapter); 1826 clear_bit(__IGB_RESETTING, &adapter->state); 1827} 1828 1829/** igb_enable_mas - Media Autosense re-enable after swap 1830 * 1831 * @adapter: adapter struct 1832 **/ 1833static s32 igb_enable_mas(struct igb_adapter *adapter) 1834{ 1835 struct e1000_hw *hw = &adapter->hw; 1836 u32 connsw; 1837 s32 ret_val = 0; 1838 1839 connsw = rd32(E1000_CONNSW); 1840 if (!(hw->phy.media_type == e1000_media_type_copper)) 1841 return ret_val; 1842 1843 /* configure for SerDes media detect */ 1844 if (!(connsw & E1000_CONNSW_SERDESD)) { 1845 connsw |= E1000_CONNSW_ENRGSRC; 1846 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1847 wr32(E1000_CONNSW, connsw); 1848 wrfl(); 1849 } else if (connsw & E1000_CONNSW_SERDESD) { 1850 /* already SerDes, no need to enable anything */ 1851 return ret_val; 1852 } else { 1853 netdev_info(adapter->netdev, 1854 "MAS: Unable to configure feature, disabling..\n"); 1855 adapter->flags &= ~IGB_FLAG_MAS_ENABLE; 1856 } 1857 return ret_val; 1858} 1859 1860void igb_reset(struct igb_adapter *adapter) 1861{ 1862 struct pci_dev *pdev = adapter->pdev; 1863 struct e1000_hw *hw = &adapter->hw; 1864 struct e1000_mac_info *mac = &hw->mac; 1865 struct e1000_fc_info *fc = &hw->fc; 1866 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; 1867 1868 /* Repartition Pba for greater than 9k mtu 1869 * To take effect CTRL.RST is required. 1870 */ 1871 switch (mac->type) { 1872 case e1000_i350: 1873 case e1000_i354: 1874 case e1000_82580: 1875 pba = rd32(E1000_RXPBS); 1876 pba = igb_rxpbs_adjust_82580(pba); 1877 break; 1878 case e1000_82576: 1879 pba = rd32(E1000_RXPBS); 1880 pba &= E1000_RXPBS_SIZE_MASK_82576; 1881 break; 1882 case e1000_82575: 1883 case e1000_i210: 1884 case e1000_i211: 1885 default: 1886 pba = E1000_PBA_34K; 1887 break; 1888 } 1889 1890 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1891 (mac->type < e1000_82576)) { 1892 /* adjust PBA for jumbo frames */ 1893 wr32(E1000_PBA, pba); 1894 1895 /* To maintain wire speed transmits, the Tx FIFO should be 1896 * large enough to accommodate two full transmit packets, 1897 * rounded up to the next 1KB and expressed in KB. Likewise, 1898 * the Rx FIFO should be large enough to accommodate at least 1899 * one full receive packet and is similarly rounded up and 1900 * expressed in KB. 1901 */ 1902 pba = rd32(E1000_PBA); 1903 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1904 tx_space = pba >> 16; 1905 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1906 pba &= 0xffff; 1907 /* the Tx fifo also stores 16 bytes of information about the Tx 1908 * but don't include ethernet FCS because hardware appends it 1909 */ 1910 min_tx_space = (adapter->max_frame_size + 1911 sizeof(union e1000_adv_tx_desc) - 1912 ETH_FCS_LEN) * 2; 1913 min_tx_space = ALIGN(min_tx_space, 1024); 1914 min_tx_space >>= 10; 1915 /* software strips receive CRC, so leave room for it */ 1916 min_rx_space = adapter->max_frame_size; 1917 min_rx_space = ALIGN(min_rx_space, 1024); 1918 min_rx_space >>= 10; 1919 1920 /* If current Tx allocation is less than the min Tx FIFO size, 1921 * and the min Tx FIFO size is less than the current Rx FIFO 1922 * allocation, take space away from current Rx allocation 1923 */ 1924 if (tx_space < min_tx_space && 1925 ((min_tx_space - tx_space) < pba)) { 1926 pba = pba - (min_tx_space - tx_space); 1927 1928 /* if short on Rx space, Rx wins and must trump Tx 1929 * adjustment 1930 */ 1931 if (pba < min_rx_space) 1932 pba = min_rx_space; 1933 } 1934 wr32(E1000_PBA, pba); 1935 } 1936 1937 /* flow control settings */ 1938 /* The high water mark must be low enough to fit one full frame 1939 * (or the size used for early receive) above it in the Rx FIFO. 1940 * Set it to the lower of: 1941 * - 90% of the Rx FIFO size, or 1942 * - the full Rx FIFO size minus one full frame 1943 */ 1944 hwm = min(((pba << 10) * 9 / 10), 1945 ((pba << 10) - 2 * adapter->max_frame_size)); 1946 1947 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1948 fc->low_water = fc->high_water - 16; 1949 fc->pause_time = 0xFFFF; 1950 fc->send_xon = 1; 1951 fc->current_mode = fc->requested_mode; 1952 1953 /* disable receive for all VFs and wait one second */ 1954 if (adapter->vfs_allocated_count) { 1955 int i; 1956 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1957 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1958 1959 /* ping all the active vfs to let them know we are going down */ 1960 igb_ping_all_vfs(adapter); 1961 1962 /* disable transmits and receives */ 1963 wr32(E1000_VFRE, 0); 1964 wr32(E1000_VFTE, 0); 1965 } 1966 1967 /* Allow time for pending master requests to run */ 1968 hw->mac.ops.reset_hw(hw); 1969 wr32(E1000_WUC, 0); 1970 1971 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1972 /* need to resetup here after media swap */ 1973 adapter->ei.get_invariants(hw); 1974 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1975 } 1976 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 1977 if (igb_enable_mas(adapter)) 1978 dev_err(&pdev->dev, 1979 "Error enabling Media Auto Sense\n"); 1980 } 1981 if (hw->mac.ops.init_hw(hw)) 1982 dev_err(&pdev->dev, "Hardware Error\n"); 1983 1984 /* Flow control settings reset on hardware reset, so guarantee flow 1985 * control is off when forcing speed. 1986 */ 1987 if (!hw->mac.autoneg) 1988 igb_force_mac_fc(hw); 1989 1990 igb_init_dmac(adapter, pba); 1991#ifdef CONFIG_IGB_HWMON 1992 /* Re-initialize the thermal sensor on i350 devices. */ 1993 if (!test_bit(__IGB_DOWN, &adapter->state)) { 1994 if (mac->type == e1000_i350 && hw->bus.func == 0) { 1995 /* If present, re-initialize the external thermal sensor 1996 * interface. 1997 */ 1998 if (adapter->ets) 1999 mac->ops.init_thermal_sensor_thresh(hw); 2000 } 2001 } 2002#endif 2003 /* Re-establish EEE setting */ 2004 if (hw->phy.media_type == e1000_media_type_copper) { 2005 switch (mac->type) { 2006 case e1000_i350: 2007 case e1000_i210: 2008 case e1000_i211: 2009 igb_set_eee_i350(hw); 2010 break; 2011 case e1000_i354: 2012 igb_set_eee_i354(hw); 2013 break; 2014 default: 2015 break; 2016 } 2017 } 2018 if (!netif_running(adapter->netdev)) 2019 igb_power_down_link(adapter); 2020 2021 igb_update_mng_vlan(adapter); 2022 2023 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2024 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2025 2026 /* Re-enable PTP, where applicable. */ 2027 igb_ptp_reset(adapter); 2028 2029 igb_get_phy_info(hw); 2030} 2031 2032static netdev_features_t igb_fix_features(struct net_device *netdev, 2033 netdev_features_t features) 2034{ 2035 /* Since there is no support for separate Rx/Tx vlan accel 2036 * enable/disable make sure Tx flag is always in same state as Rx. 2037 */ 2038 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2039 features |= NETIF_F_HW_VLAN_CTAG_TX; 2040 else 2041 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2042 2043 return features; 2044} 2045 2046static int igb_set_features(struct net_device *netdev, 2047 netdev_features_t features) 2048{ 2049 netdev_features_t changed = netdev->features ^ features; 2050 struct igb_adapter *adapter = netdev_priv(netdev); 2051 2052 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2053 igb_vlan_mode(netdev, features); 2054 2055 if (!(changed & NETIF_F_RXALL)) 2056 return 0; 2057 2058 netdev->features = features; 2059 2060 if (netif_running(netdev)) 2061 igb_reinit_locked(adapter); 2062 else 2063 igb_reset(adapter); 2064 2065 return 0; 2066} 2067 2068static const struct net_device_ops igb_netdev_ops = { 2069 .ndo_open = igb_open, 2070 .ndo_stop = igb_close, 2071 .ndo_start_xmit = igb_xmit_frame, 2072 .ndo_get_stats64 = igb_get_stats64, 2073 .ndo_set_rx_mode = igb_set_rx_mode, 2074 .ndo_set_mac_address = igb_set_mac, 2075 .ndo_change_mtu = igb_change_mtu, 2076 .ndo_do_ioctl = igb_ioctl, 2077 .ndo_tx_timeout = igb_tx_timeout, 2078 .ndo_validate_addr = eth_validate_addr, 2079 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2080 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2081 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2082 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2083 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, 2084 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2085 .ndo_get_vf_config = igb_ndo_get_vf_config, 2086#ifdef CONFIG_NET_POLL_CONTROLLER 2087 .ndo_poll_controller = igb_netpoll, 2088#endif 2089 .ndo_fix_features = igb_fix_features, 2090 .ndo_set_features = igb_set_features, 2091}; 2092 2093/** 2094 * igb_set_fw_version - Configure version string for ethtool 2095 * @adapter: adapter struct 2096 **/ 2097void igb_set_fw_version(struct igb_adapter *adapter) 2098{ 2099 struct e1000_hw *hw = &adapter->hw; 2100 struct e1000_fw_version fw; 2101 2102 igb_get_fw_version(hw, &fw); 2103 2104 switch (hw->mac.type) { 2105 case e1000_i210: 2106 case e1000_i211: 2107 if (!(igb_get_flash_presence_i210(hw))) { 2108 snprintf(adapter->fw_version, 2109 sizeof(adapter->fw_version), 2110 "%2d.%2d-%d", 2111 fw.invm_major, fw.invm_minor, 2112 fw.invm_img_type); 2113 break; 2114 } 2115 /* fall through */ 2116 default: 2117 /* if option is rom valid, display its version too */ 2118 if (fw.or_valid) { 2119 snprintf(adapter->fw_version, 2120 sizeof(adapter->fw_version), 2121 "%d.%d, 0x%08x, %d.%d.%d", 2122 fw.eep_major, fw.eep_minor, fw.etrack_id, 2123 fw.or_major, fw.or_build, fw.or_patch); 2124 /* no option rom */ 2125 } else if (fw.etrack_id != 0X0000) { 2126 snprintf(adapter->fw_version, 2127 sizeof(adapter->fw_version), 2128 "%d.%d, 0x%08x", 2129 fw.eep_major, fw.eep_minor, fw.etrack_id); 2130 } else { 2131 snprintf(adapter->fw_version, 2132 sizeof(adapter->fw_version), 2133 "%d.%d.%d", 2134 fw.eep_major, fw.eep_minor, fw.eep_build); 2135 } 2136 break; 2137 } 2138 return; 2139} 2140 2141/** 2142 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2143 * 2144 * @adapter: adapter struct 2145 **/ 2146static void igb_init_mas(struct igb_adapter *adapter) 2147{ 2148 struct e1000_hw *hw = &adapter->hw; 2149 u16 eeprom_data; 2150 2151 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2152 switch (hw->bus.func) { 2153 case E1000_FUNC_0: 2154 if (eeprom_data & IGB_MAS_ENABLE_0) { 2155 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2156 netdev_info(adapter->netdev, 2157 "MAS: Enabling Media Autosense for port %d\n", 2158 hw->bus.func); 2159 } 2160 break; 2161 case E1000_FUNC_1: 2162 if (eeprom_data & IGB_MAS_ENABLE_1) { 2163 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2164 netdev_info(adapter->netdev, 2165 "MAS: Enabling Media Autosense for port %d\n", 2166 hw->bus.func); 2167 } 2168 break; 2169 case E1000_FUNC_2: 2170 if (eeprom_data & IGB_MAS_ENABLE_2) { 2171 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2172 netdev_info(adapter->netdev, 2173 "MAS: Enabling Media Autosense for port %d\n", 2174 hw->bus.func); 2175 } 2176 break; 2177 case E1000_FUNC_3: 2178 if (eeprom_data & IGB_MAS_ENABLE_3) { 2179 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2180 netdev_info(adapter->netdev, 2181 "MAS: Enabling Media Autosense for port %d\n", 2182 hw->bus.func); 2183 } 2184 break; 2185 default: 2186 /* Shouldn't get here */ 2187 netdev_err(adapter->netdev, 2188 "MAS: Invalid port configuration, returning\n"); 2189 break; 2190 } 2191} 2192 2193/** 2194 * igb_init_i2c - Init I2C interface 2195 * @adapter: pointer to adapter structure 2196 **/ 2197static s32 igb_init_i2c(struct igb_adapter *adapter) 2198{ 2199 s32 status = E1000_SUCCESS; 2200 2201 /* I2C interface supported on i350 devices */ 2202 if (adapter->hw.mac.type != e1000_i350) 2203 return E1000_SUCCESS; 2204 2205 /* Initialize the i2c bus which is controlled by the registers. 2206 * This bus will use the i2c_algo_bit structue that implements 2207 * the protocol through toggling of the 4 bits in the register. 2208 */ 2209 adapter->i2c_adap.owner = THIS_MODULE; 2210 adapter->i2c_algo = igb_i2c_algo; 2211 adapter->i2c_algo.data = adapter; 2212 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2213 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2214 strlcpy(adapter->i2c_adap.name, "igb BB", 2215 sizeof(adapter->i2c_adap.name)); 2216 status = i2c_bit_add_bus(&adapter->i2c_adap); 2217 return status; 2218} 2219 2220/** 2221 * igb_probe - Device Initialization Routine 2222 * @pdev: PCI device information struct 2223 * @ent: entry in igb_pci_tbl 2224 * 2225 * Returns 0 on success, negative on failure 2226 * 2227 * igb_probe initializes an adapter identified by a pci_dev structure. 2228 * The OS initialization, configuring of the adapter private structure, 2229 * and a hardware reset occur. 2230 **/ 2231static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2232{ 2233 struct net_device *netdev; 2234 struct igb_adapter *adapter; 2235 struct e1000_hw *hw; 2236 u16 eeprom_data = 0; 2237 s32 ret_val; 2238 static int global_quad_port_a; /* global quad port a indication */ 2239 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2240 int err, pci_using_dac; 2241 u8 part_str[E1000_PBANUM_LENGTH]; 2242 2243 /* Catch broken hardware that put the wrong VF device ID in 2244 * the PCIe SR-IOV capability. 2245 */ 2246 if (pdev->is_virtfn) { 2247 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2248 pci_name(pdev), pdev->vendor, pdev->device); 2249 return -EINVAL; 2250 } 2251 2252 err = pci_enable_device_mem(pdev); 2253 if (err) 2254 return err; 2255 2256 pci_using_dac = 0; 2257 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2258 if (!err) { 2259 pci_using_dac = 1; 2260 } else { 2261 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2262 if (err) { 2263 dev_err(&pdev->dev, 2264 "No usable DMA configuration, aborting\n"); 2265 goto err_dma; 2266 } 2267 } 2268 2269 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 2270 IORESOURCE_MEM), 2271 igb_driver_name); 2272 if (err) 2273 goto err_pci_reg; 2274 2275 pci_enable_pcie_error_reporting(pdev); 2276 2277 pci_set_master(pdev); 2278 pci_save_state(pdev); 2279 2280 err = -ENOMEM; 2281 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2282 IGB_MAX_TX_QUEUES); 2283 if (!netdev) 2284 goto err_alloc_etherdev; 2285 2286 SET_NETDEV_DEV(netdev, &pdev->dev); 2287 2288 pci_set_drvdata(pdev, netdev); 2289 adapter = netdev_priv(netdev); 2290 adapter->netdev = netdev; 2291 adapter->pdev = pdev; 2292 hw = &adapter->hw; 2293 hw->back = adapter; 2294 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2295 2296 err = -EIO; 2297 hw->hw_addr = pci_iomap(pdev, 0, 0); 2298 if (!hw->hw_addr) 2299 goto err_ioremap; 2300 2301 netdev->netdev_ops = &igb_netdev_ops; 2302 igb_set_ethtool_ops(netdev); 2303 netdev->watchdog_timeo = 5 * HZ; 2304 2305 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2306 2307 netdev->mem_start = pci_resource_start(pdev, 0); 2308 netdev->mem_end = pci_resource_end(pdev, 0); 2309 2310 /* PCI config space info */ 2311 hw->vendor_id = pdev->vendor; 2312 hw->device_id = pdev->device; 2313 hw->revision_id = pdev->revision; 2314 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2315 hw->subsystem_device_id = pdev->subsystem_device; 2316 2317 /* Copy the default MAC, PHY and NVM function pointers */ 2318 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2319 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2320 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2321 /* Initialize skew-specific constants */ 2322 err = ei->get_invariants(hw); 2323 if (err) 2324 goto err_sw_init; 2325 2326 /* setup the private structure */ 2327 err = igb_sw_init(adapter); 2328 if (err) 2329 goto err_sw_init; 2330 2331 igb_get_bus_info_pcie(hw); 2332 2333 hw->phy.autoneg_wait_to_complete = false; 2334 2335 /* Copper options */ 2336 if (hw->phy.media_type == e1000_media_type_copper) { 2337 hw->phy.mdix = AUTO_ALL_MODES; 2338 hw->phy.disable_polarity_correction = false; 2339 hw->phy.ms_type = e1000_ms_hw_default; 2340 } 2341 2342 if (igb_check_reset_block(hw)) 2343 dev_info(&pdev->dev, 2344 "PHY reset is blocked due to SOL/IDER session.\n"); 2345 2346 /* features is initialized to 0 in allocation, it might have bits 2347 * set by igb_sw_init so we should use an or instead of an 2348 * assignment. 2349 */ 2350 netdev->features |= NETIF_F_SG | 2351 NETIF_F_IP_CSUM | 2352 NETIF_F_IPV6_CSUM | 2353 NETIF_F_TSO | 2354 NETIF_F_TSO6 | 2355 NETIF_F_RXHASH | 2356 NETIF_F_RXCSUM | 2357 NETIF_F_HW_VLAN_CTAG_RX | 2358 NETIF_F_HW_VLAN_CTAG_TX; 2359 2360 /* copy netdev features into list of user selectable features */ 2361 netdev->hw_features |= netdev->features; 2362 netdev->hw_features |= NETIF_F_RXALL; 2363 2364 /* set this bit last since it cannot be part of hw_features */ 2365 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2366 2367 netdev->vlan_features |= NETIF_F_TSO | 2368 NETIF_F_TSO6 | 2369 NETIF_F_IP_CSUM | 2370 NETIF_F_IPV6_CSUM | 2371 NETIF_F_SG; 2372 2373 netdev->priv_flags |= IFF_SUPP_NOFCS; 2374 2375 if (pci_using_dac) { 2376 netdev->features |= NETIF_F_HIGHDMA; 2377 netdev->vlan_features |= NETIF_F_HIGHDMA; 2378 } 2379 2380 if (hw->mac.type >= e1000_82576) { 2381 netdev->hw_features |= NETIF_F_SCTP_CSUM; 2382 netdev->features |= NETIF_F_SCTP_CSUM; 2383 } 2384 2385 netdev->priv_flags |= IFF_UNICAST_FLT; 2386 2387 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2388 2389 /* before reading the NVM, reset the controller to put the device in a 2390 * known good starting state 2391 */ 2392 hw->mac.ops.reset_hw(hw); 2393 2394 /* make sure the NVM is good , i211/i210 parts can have special NVM 2395 * that doesn't contain a checksum 2396 */ 2397 switch (hw->mac.type) { 2398 case e1000_i210: 2399 case e1000_i211: 2400 if (igb_get_flash_presence_i210(hw)) { 2401 if (hw->nvm.ops.validate(hw) < 0) { 2402 dev_err(&pdev->dev, 2403 "The NVM Checksum Is Not Valid\n"); 2404 err = -EIO; 2405 goto err_eeprom; 2406 } 2407 } 2408 break; 2409 default: 2410 if (hw->nvm.ops.validate(hw) < 0) { 2411 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2412 err = -EIO; 2413 goto err_eeprom; 2414 } 2415 break; 2416 } 2417 2418 /* copy the MAC address out of the NVM */ 2419 if (hw->mac.ops.read_mac_addr(hw)) 2420 dev_err(&pdev->dev, "NVM Read Error\n"); 2421 2422 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2423 2424 if (!is_valid_ether_addr(netdev->dev_addr)) { 2425 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2426 err = -EIO; 2427 goto err_eeprom; 2428 } 2429 2430 /* get firmware version for ethtool -i */ 2431 igb_set_fw_version(adapter); 2432 2433 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2434 (unsigned long) adapter); 2435 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2436 (unsigned long) adapter); 2437 2438 INIT_WORK(&adapter->reset_task, igb_reset_task); 2439 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2440 2441 /* Initialize link properties that are user-changeable */ 2442 adapter->fc_autoneg = true; 2443 hw->mac.autoneg = true; 2444 hw->phy.autoneg_advertised = 0x2f; 2445 2446 hw->fc.requested_mode = e1000_fc_default; 2447 hw->fc.current_mode = e1000_fc_default; 2448 2449 igb_validate_mdi_setting(hw); 2450 2451 /* By default, support wake on port A */ 2452 if (hw->bus.func == 0) 2453 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2454 2455 /* Check the NVM for wake support on non-port A ports */ 2456 if (hw->mac.type >= e1000_82580) 2457 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2458 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2459 &eeprom_data); 2460 else if (hw->bus.func == 1) 2461 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2462 2463 if (eeprom_data & IGB_EEPROM_APME) 2464 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2465 2466 /* now that we have the eeprom settings, apply the special cases where 2467 * the eeprom may be wrong or the board simply won't support wake on 2468 * lan on a particular port 2469 */ 2470 switch (pdev->device) { 2471 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2472 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2473 break; 2474 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2475 case E1000_DEV_ID_82576_FIBER: 2476 case E1000_DEV_ID_82576_SERDES: 2477 /* Wake events only supported on port A for dual fiber 2478 * regardless of eeprom setting 2479 */ 2480 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2481 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2482 break; 2483 case E1000_DEV_ID_82576_QUAD_COPPER: 2484 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2485 /* if quad port adapter, disable WoL on all but port A */ 2486 if (global_quad_port_a != 0) 2487 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2488 else 2489 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2490 /* Reset for multiple quad port adapters */ 2491 if (++global_quad_port_a == 4) 2492 global_quad_port_a = 0; 2493 break; 2494 default: 2495 /* If the device can't wake, don't set software support */ 2496 if (!device_can_wakeup(&adapter->pdev->dev)) 2497 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2498 } 2499 2500 /* initialize the wol settings based on the eeprom settings */ 2501 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2502 adapter->wol |= E1000_WUFC_MAG; 2503 2504 /* Some vendors want WoL disabled by default, but still supported */ 2505 if ((hw->mac.type == e1000_i350) && 2506 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2507 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2508 adapter->wol = 0; 2509 } 2510 2511 device_set_wakeup_enable(&adapter->pdev->dev, 2512 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2513 2514 /* reset the hardware with the new settings */ 2515 igb_reset(adapter); 2516 2517 /* Init the I2C interface */ 2518 err = igb_init_i2c(adapter); 2519 if (err) { 2520 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2521 goto err_eeprom; 2522 } 2523 2524 /* let the f/w know that the h/w is now under the control of the 2525 * driver. */ 2526 igb_get_hw_control(adapter); 2527 2528 strcpy(netdev->name, "eth%d"); 2529 err = register_netdev(netdev); 2530 if (err) 2531 goto err_register; 2532 2533 /* carrier off reporting is important to ethtool even BEFORE open */ 2534 netif_carrier_off(netdev); 2535 2536#ifdef CONFIG_IGB_DCA 2537 if (dca_add_requester(&pdev->dev) == 0) { 2538 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2539 dev_info(&pdev->dev, "DCA enabled\n"); 2540 igb_setup_dca(adapter); 2541 } 2542 2543#endif 2544#ifdef CONFIG_IGB_HWMON 2545 /* Initialize the thermal sensor on i350 devices. */ 2546 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2547 u16 ets_word; 2548 2549 /* Read the NVM to determine if this i350 device supports an 2550 * external thermal sensor. 2551 */ 2552 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2553 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2554 adapter->ets = true; 2555 else 2556 adapter->ets = false; 2557 if (igb_sysfs_init(adapter)) 2558 dev_err(&pdev->dev, 2559 "failed to allocate sysfs resources\n"); 2560 } else { 2561 adapter->ets = false; 2562 } 2563#endif 2564 /* Check if Media Autosense is enabled */ 2565 adapter->ei = *ei; 2566 if (hw->dev_spec._82575.mas_capable) 2567 igb_init_mas(adapter); 2568 2569 /* do hw tstamp init after resetting */ 2570 igb_ptp_init(adapter); 2571 2572 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2573 /* print bus type/speed/width info, not applicable to i354 */ 2574 if (hw->mac.type != e1000_i354) { 2575 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2576 netdev->name, 2577 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2578 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2579 "unknown"), 2580 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2581 "Width x4" : 2582 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2583 "Width x2" : 2584 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2585 "Width x1" : "unknown"), netdev->dev_addr); 2586 } 2587 2588 if ((hw->mac.type >= e1000_i210 || 2589 igb_get_flash_presence_i210(hw))) { 2590 ret_val = igb_read_part_string(hw, part_str, 2591 E1000_PBANUM_LENGTH); 2592 } else { 2593 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2594 } 2595 2596 if (ret_val) 2597 strcpy(part_str, "Unknown"); 2598 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2599 dev_info(&pdev->dev, 2600 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2601 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2602 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2603 adapter->num_rx_queues, adapter->num_tx_queues); 2604 if (hw->phy.media_type == e1000_media_type_copper) { 2605 switch (hw->mac.type) { 2606 case e1000_i350: 2607 case e1000_i210: 2608 case e1000_i211: 2609 /* Enable EEE for internal copper PHY devices */ 2610 err = igb_set_eee_i350(hw); 2611 if ((!err) && 2612 (!hw->dev_spec._82575.eee_disable)) { 2613 adapter->eee_advert = 2614 MDIO_EEE_100TX | MDIO_EEE_1000T; 2615 adapter->flags |= IGB_FLAG_EEE; 2616 } 2617 break; 2618 case e1000_i354: 2619 if ((rd32(E1000_CTRL_EXT) & 2620 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2621 err = igb_set_eee_i354(hw); 2622 if ((!err) && 2623 (!hw->dev_spec._82575.eee_disable)) { 2624 adapter->eee_advert = 2625 MDIO_EEE_100TX | MDIO_EEE_1000T; 2626 adapter->flags |= IGB_FLAG_EEE; 2627 } 2628 } 2629 break; 2630 default: 2631 break; 2632 } 2633 } 2634 pm_runtime_put_noidle(&pdev->dev); 2635 return 0; 2636 2637err_register: 2638 igb_release_hw_control(adapter); 2639 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2640err_eeprom: 2641 if (!igb_check_reset_block(hw)) 2642 igb_reset_phy(hw); 2643 2644 if (hw->flash_address) 2645 iounmap(hw->flash_address); 2646err_sw_init: 2647 igb_clear_interrupt_scheme(adapter); 2648 iounmap(hw->hw_addr); 2649err_ioremap: 2650 free_netdev(netdev); 2651err_alloc_etherdev: 2652 pci_release_selected_regions(pdev, 2653 pci_select_bars(pdev, IORESOURCE_MEM)); 2654err_pci_reg: 2655err_dma: 2656 pci_disable_device(pdev); 2657 return err; 2658} 2659 2660#ifdef CONFIG_PCI_IOV 2661static int igb_disable_sriov(struct pci_dev *pdev) 2662{ 2663 struct net_device *netdev = pci_get_drvdata(pdev); 2664 struct igb_adapter *adapter = netdev_priv(netdev); 2665 struct e1000_hw *hw = &adapter->hw; 2666 2667 /* reclaim resources allocated to VFs */ 2668 if (adapter->vf_data) { 2669 /* disable iov and allow time for transactions to clear */ 2670 if (pci_vfs_assigned(pdev)) { 2671 dev_warn(&pdev->dev, 2672 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2673 return -EPERM; 2674 } else { 2675 pci_disable_sriov(pdev); 2676 msleep(500); 2677 } 2678 2679 kfree(adapter->vf_data); 2680 adapter->vf_data = NULL; 2681 adapter->vfs_allocated_count = 0; 2682 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2683 wrfl(); 2684 msleep(100); 2685 dev_info(&pdev->dev, "IOV Disabled\n"); 2686 2687 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2688 adapter->flags |= IGB_FLAG_DMAC; 2689 } 2690 2691 return 0; 2692} 2693 2694static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2695{ 2696 struct net_device *netdev = pci_get_drvdata(pdev); 2697 struct igb_adapter *adapter = netdev_priv(netdev); 2698 int old_vfs = pci_num_vf(pdev); 2699 int err = 0; 2700 int i; 2701 2702 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2703 err = -EPERM; 2704 goto out; 2705 } 2706 if (!num_vfs) 2707 goto out; 2708 2709 if (old_vfs) { 2710 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2711 old_vfs, max_vfs); 2712 adapter->vfs_allocated_count = old_vfs; 2713 } else 2714 adapter->vfs_allocated_count = num_vfs; 2715 2716 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2717 sizeof(struct vf_data_storage), GFP_KERNEL); 2718 2719 /* if allocation failed then we do not support SR-IOV */ 2720 if (!adapter->vf_data) { 2721 adapter->vfs_allocated_count = 0; 2722 dev_err(&pdev->dev, 2723 "Unable to allocate memory for VF Data Storage\n"); 2724 err = -ENOMEM; 2725 goto out; 2726 } 2727 2728 /* only call pci_enable_sriov() if no VFs are allocated already */ 2729 if (!old_vfs) { 2730 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2731 if (err) 2732 goto err_out; 2733 } 2734 dev_info(&pdev->dev, "%d VFs allocated\n", 2735 adapter->vfs_allocated_count); 2736 for (i = 0; i < adapter->vfs_allocated_count; i++) 2737 igb_vf_configure(adapter, i); 2738 2739 /* DMA Coalescing is not supported in IOV mode. */ 2740 adapter->flags &= ~IGB_FLAG_DMAC; 2741 goto out; 2742 2743err_out: 2744 kfree(adapter->vf_data); 2745 adapter->vf_data = NULL; 2746 adapter->vfs_allocated_count = 0; 2747out: 2748 return err; 2749} 2750 2751#endif 2752/** 2753 * igb_remove_i2c - Cleanup I2C interface 2754 * @adapter: pointer to adapter structure 2755 **/ 2756static void igb_remove_i2c(struct igb_adapter *adapter) 2757{ 2758 /* free the adapter bus structure */ 2759 i2c_del_adapter(&adapter->i2c_adap); 2760} 2761 2762/** 2763 * igb_remove - Device Removal Routine 2764 * @pdev: PCI device information struct 2765 * 2766 * igb_remove is called by the PCI subsystem to alert the driver 2767 * that it should release a PCI device. The could be caused by a 2768 * Hot-Plug event, or because the driver is going to be removed from 2769 * memory. 2770 **/ 2771static void igb_remove(struct pci_dev *pdev) 2772{ 2773 struct net_device *netdev = pci_get_drvdata(pdev); 2774 struct igb_adapter *adapter = netdev_priv(netdev); 2775 struct e1000_hw *hw = &adapter->hw; 2776 2777 pm_runtime_get_noresume(&pdev->dev); 2778#ifdef CONFIG_IGB_HWMON 2779 igb_sysfs_exit(adapter); 2780#endif 2781 igb_remove_i2c(adapter); 2782 igb_ptp_stop(adapter); 2783 /* The watchdog timer may be rescheduled, so explicitly 2784 * disable watchdog from being rescheduled. 2785 */ 2786 set_bit(__IGB_DOWN, &adapter->state); 2787 del_timer_sync(&adapter->watchdog_timer); 2788 del_timer_sync(&adapter->phy_info_timer); 2789 2790 cancel_work_sync(&adapter->reset_task); 2791 cancel_work_sync(&adapter->watchdog_task); 2792 2793#ifdef CONFIG_IGB_DCA 2794 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2795 dev_info(&pdev->dev, "DCA disabled\n"); 2796 dca_remove_requester(&pdev->dev); 2797 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2798 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2799 } 2800#endif 2801 2802 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2803 * would have already happened in close and is redundant. 2804 */ 2805 igb_release_hw_control(adapter); 2806 2807 unregister_netdev(netdev); 2808 2809 igb_clear_interrupt_scheme(adapter); 2810 2811#ifdef CONFIG_PCI_IOV 2812 igb_disable_sriov(pdev); 2813#endif 2814 2815 iounmap(hw->hw_addr); 2816 if (hw->flash_address) 2817 iounmap(hw->flash_address); 2818 pci_release_selected_regions(pdev, 2819 pci_select_bars(pdev, IORESOURCE_MEM)); 2820 2821 kfree(adapter->shadow_vfta); 2822 free_netdev(netdev); 2823 2824 pci_disable_pcie_error_reporting(pdev); 2825 2826 pci_disable_device(pdev); 2827} 2828 2829/** 2830 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2831 * @adapter: board private structure to initialize 2832 * 2833 * This function initializes the vf specific data storage and then attempts to 2834 * allocate the VFs. The reason for ordering it this way is because it is much 2835 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2836 * the memory for the VFs. 2837 **/ 2838static void igb_probe_vfs(struct igb_adapter *adapter) 2839{ 2840#ifdef CONFIG_PCI_IOV 2841 struct pci_dev *pdev = adapter->pdev; 2842 struct e1000_hw *hw = &adapter->hw; 2843 2844 /* Virtualization features not supported on i210 family. */ 2845 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2846 return; 2847 2848 pci_sriov_set_totalvfs(pdev, 7); 2849 igb_pci_enable_sriov(pdev, max_vfs); 2850 2851#endif /* CONFIG_PCI_IOV */ 2852} 2853 2854static void igb_init_queue_configuration(struct igb_adapter *adapter) 2855{ 2856 struct e1000_hw *hw = &adapter->hw; 2857 u32 max_rss_queues; 2858 2859 /* Determine the maximum number of RSS queues supported. */ 2860 switch (hw->mac.type) { 2861 case e1000_i211: 2862 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2863 break; 2864 case e1000_82575: 2865 case e1000_i210: 2866 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2867 break; 2868 case e1000_i350: 2869 /* I350 cannot do RSS and SR-IOV at the same time */ 2870 if (!!adapter->vfs_allocated_count) { 2871 max_rss_queues = 1; 2872 break; 2873 } 2874 /* fall through */ 2875 case e1000_82576: 2876 if (!!adapter->vfs_allocated_count) { 2877 max_rss_queues = 2; 2878 break; 2879 } 2880 /* fall through */ 2881 case e1000_82580: 2882 case e1000_i354: 2883 default: 2884 max_rss_queues = IGB_MAX_RX_QUEUES; 2885 break; 2886 } 2887 2888 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2889 2890 /* Determine if we need to pair queues. */ 2891 switch (hw->mac.type) { 2892 case e1000_82575: 2893 case e1000_i211: 2894 /* Device supports enough interrupts without queue pairing. */ 2895 break; 2896 case e1000_82576: 2897 /* If VFs are going to be allocated with RSS queues then we 2898 * should pair the queues in order to conserve interrupts due 2899 * to limited supply. 2900 */ 2901 if ((adapter->rss_queues > 1) && 2902 (adapter->vfs_allocated_count > 6)) 2903 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2904 /* fall through */ 2905 case e1000_82580: 2906 case e1000_i350: 2907 case e1000_i354: 2908 case e1000_i210: 2909 default: 2910 /* If rss_queues > half of max_rss_queues, pair the queues in 2911 * order to conserve interrupts due to limited supply. 2912 */ 2913 if (adapter->rss_queues > (max_rss_queues / 2)) 2914 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2915 break; 2916 } 2917} 2918 2919/** 2920 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2921 * @adapter: board private structure to initialize 2922 * 2923 * igb_sw_init initializes the Adapter private data structure. 2924 * Fields are initialized based on PCI device information and 2925 * OS network device settings (MTU size). 2926 **/ 2927static int igb_sw_init(struct igb_adapter *adapter) 2928{ 2929 struct e1000_hw *hw = &adapter->hw; 2930 struct net_device *netdev = adapter->netdev; 2931 struct pci_dev *pdev = adapter->pdev; 2932 2933 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2934 2935 /* set default ring sizes */ 2936 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2937 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2938 2939 /* set default ITR values */ 2940 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2941 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2942 2943 /* set default work limits */ 2944 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2945 2946 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2947 VLAN_HLEN; 2948 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2949 2950 spin_lock_init(&adapter->stats64_lock); 2951#ifdef CONFIG_PCI_IOV 2952 switch (hw->mac.type) { 2953 case e1000_82576: 2954 case e1000_i350: 2955 if (max_vfs > 7) { 2956 dev_warn(&pdev->dev, 2957 "Maximum of 7 VFs per PF, using max\n"); 2958 max_vfs = adapter->vfs_allocated_count = 7; 2959 } else 2960 adapter->vfs_allocated_count = max_vfs; 2961 if (adapter->vfs_allocated_count) 2962 dev_warn(&pdev->dev, 2963 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 2964 break; 2965 default: 2966 break; 2967 } 2968#endif /* CONFIG_PCI_IOV */ 2969 2970 igb_init_queue_configuration(adapter); 2971 2972 /* Setup and initialize a copy of the hw vlan table array */ 2973 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 2974 GFP_ATOMIC); 2975 2976 /* This call may decrease the number of queues */ 2977 if (igb_init_interrupt_scheme(adapter, true)) { 2978 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2979 return -ENOMEM; 2980 } 2981 2982 igb_probe_vfs(adapter); 2983 2984 /* Explicitly disable IRQ since the NIC can be in any state. */ 2985 igb_irq_disable(adapter); 2986 2987 if (hw->mac.type >= e1000_i350) 2988 adapter->flags &= ~IGB_FLAG_DMAC; 2989 2990 set_bit(__IGB_DOWN, &adapter->state); 2991 return 0; 2992} 2993 2994/** 2995 * igb_open - Called when a network interface is made active 2996 * @netdev: network interface device structure 2997 * 2998 * Returns 0 on success, negative value on failure 2999 * 3000 * The open entry point is called when a network interface is made 3001 * active by the system (IFF_UP). At this point all resources needed 3002 * for transmit and receive operations are allocated, the interrupt 3003 * handler is registered with the OS, the watchdog timer is started, 3004 * and the stack is notified that the interface is ready. 3005 **/ 3006static int __igb_open(struct net_device *netdev, bool resuming) 3007{ 3008 struct igb_adapter *adapter = netdev_priv(netdev); 3009 struct e1000_hw *hw = &adapter->hw; 3010 struct pci_dev *pdev = adapter->pdev; 3011 int err; 3012 int i; 3013 3014 /* disallow open during test */ 3015 if (test_bit(__IGB_TESTING, &adapter->state)) { 3016 WARN_ON(resuming); 3017 return -EBUSY; 3018 } 3019 3020 if (!resuming) 3021 pm_runtime_get_sync(&pdev->dev); 3022 3023 netif_carrier_off(netdev); 3024 3025 /* allocate transmit descriptors */ 3026 err = igb_setup_all_tx_resources(adapter); 3027 if (err) 3028 goto err_setup_tx; 3029 3030 /* allocate receive descriptors */ 3031 err = igb_setup_all_rx_resources(adapter); 3032 if (err) 3033 goto err_setup_rx; 3034 3035 igb_power_up_link(adapter); 3036 3037 /* before we allocate an interrupt, we must be ready to handle it. 3038 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3039 * as soon as we call pci_request_irq, so we have to setup our 3040 * clean_rx handler before we do so. 3041 */ 3042 igb_configure(adapter); 3043 3044 err = igb_request_irq(adapter); 3045 if (err) 3046 goto err_req_irq; 3047 3048 /* Notify the stack of the actual queue counts. */ 3049 err = netif_set_real_num_tx_queues(adapter->netdev, 3050 adapter->num_tx_queues); 3051 if (err) 3052 goto err_set_queues; 3053 3054 err = netif_set_real_num_rx_queues(adapter->netdev, 3055 adapter->num_rx_queues); 3056 if (err) 3057 goto err_set_queues; 3058 3059 /* From here on the code is the same as igb_up() */ 3060 clear_bit(__IGB_DOWN, &adapter->state); 3061 3062 for (i = 0; i < adapter->num_q_vectors; i++) 3063 napi_enable(&(adapter->q_vector[i]->napi)); 3064 3065 /* Clear any pending interrupts. */ 3066 rd32(E1000_ICR); 3067 3068 igb_irq_enable(adapter); 3069 3070 /* notify VFs that reset has been completed */ 3071 if (adapter->vfs_allocated_count) { 3072 u32 reg_data = rd32(E1000_CTRL_EXT); 3073 reg_data |= E1000_CTRL_EXT_PFRSTD; 3074 wr32(E1000_CTRL_EXT, reg_data); 3075 } 3076 3077 netif_tx_start_all_queues(netdev); 3078 3079 if (!resuming) 3080 pm_runtime_put(&pdev->dev); 3081 3082 /* start the watchdog. */ 3083 hw->mac.get_link_status = 1; 3084 schedule_work(&adapter->watchdog_task); 3085 3086 return 0; 3087 3088err_set_queues: 3089 igb_free_irq(adapter); 3090err_req_irq: 3091 igb_release_hw_control(adapter); 3092 igb_power_down_link(adapter); 3093 igb_free_all_rx_resources(adapter); 3094err_setup_rx: 3095 igb_free_all_tx_resources(adapter); 3096err_setup_tx: 3097 igb_reset(adapter); 3098 if (!resuming) 3099 pm_runtime_put(&pdev->dev); 3100 3101 return err; 3102} 3103 3104static int igb_open(struct net_device *netdev) 3105{ 3106 return __igb_open(netdev, false); 3107} 3108 3109/** 3110 * igb_close - Disables a network interface 3111 * @netdev: network interface device structure 3112 * 3113 * Returns 0, this is not allowed to fail 3114 * 3115 * The close entry point is called when an interface is de-activated 3116 * by the OS. The hardware is still under the driver's control, but 3117 * needs to be disabled. A global MAC reset is issued to stop the 3118 * hardware, and all transmit and receive resources are freed. 3119 **/ 3120static int __igb_close(struct net_device *netdev, bool suspending) 3121{ 3122 struct igb_adapter *adapter = netdev_priv(netdev); 3123 struct pci_dev *pdev = adapter->pdev; 3124 3125 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3126 3127 if (!suspending) 3128 pm_runtime_get_sync(&pdev->dev); 3129 3130 igb_down(adapter); 3131 igb_free_irq(adapter); 3132 3133 igb_free_all_tx_resources(adapter); 3134 igb_free_all_rx_resources(adapter); 3135 3136 if (!suspending) 3137 pm_runtime_put_sync(&pdev->dev); 3138 return 0; 3139} 3140 3141static int igb_close(struct net_device *netdev) 3142{ 3143 return __igb_close(netdev, false); 3144} 3145 3146/** 3147 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3148 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3149 * 3150 * Return 0 on success, negative on failure 3151 **/ 3152int igb_setup_tx_resources(struct igb_ring *tx_ring) 3153{ 3154 struct device *dev = tx_ring->dev; 3155 int size; 3156 3157 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3158 3159 tx_ring->tx_buffer_info = vzalloc(size); 3160 if (!tx_ring->tx_buffer_info) 3161 goto err; 3162 3163 /* round up to nearest 4K */ 3164 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3165 tx_ring->size = ALIGN(tx_ring->size, 4096); 3166 3167 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3168 &tx_ring->dma, GFP_KERNEL); 3169 if (!tx_ring->desc) 3170 goto err; 3171 3172 tx_ring->next_to_use = 0; 3173 tx_ring->next_to_clean = 0; 3174 3175 return 0; 3176 3177err: 3178 vfree(tx_ring->tx_buffer_info); 3179 tx_ring->tx_buffer_info = NULL; 3180 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3181 return -ENOMEM; 3182} 3183 3184/** 3185 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3186 * (Descriptors) for all queues 3187 * @adapter: board private structure 3188 * 3189 * Return 0 on success, negative on failure 3190 **/ 3191static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3192{ 3193 struct pci_dev *pdev = adapter->pdev; 3194 int i, err = 0; 3195 3196 for (i = 0; i < adapter->num_tx_queues; i++) { 3197 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3198 if (err) { 3199 dev_err(&pdev->dev, 3200 "Allocation for Tx Queue %u failed\n", i); 3201 for (i--; i >= 0; i--) 3202 igb_free_tx_resources(adapter->tx_ring[i]); 3203 break; 3204 } 3205 } 3206 3207 return err; 3208} 3209 3210/** 3211 * igb_setup_tctl - configure the transmit control registers 3212 * @adapter: Board private structure 3213 **/ 3214void igb_setup_tctl(struct igb_adapter *adapter) 3215{ 3216 struct e1000_hw *hw = &adapter->hw; 3217 u32 tctl; 3218 3219 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3220 wr32(E1000_TXDCTL(0), 0); 3221 3222 /* Program the Transmit Control Register */ 3223 tctl = rd32(E1000_TCTL); 3224 tctl &= ~E1000_TCTL_CT; 3225 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3226 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3227 3228 igb_config_collision_dist(hw); 3229 3230 /* Enable transmits */ 3231 tctl |= E1000_TCTL_EN; 3232 3233 wr32(E1000_TCTL, tctl); 3234} 3235 3236/** 3237 * igb_configure_tx_ring - Configure transmit ring after Reset 3238 * @adapter: board private structure 3239 * @ring: tx ring to configure 3240 * 3241 * Configure a transmit ring after a reset. 3242 **/ 3243void igb_configure_tx_ring(struct igb_adapter *adapter, 3244 struct igb_ring *ring) 3245{ 3246 struct e1000_hw *hw = &adapter->hw; 3247 u32 txdctl = 0; 3248 u64 tdba = ring->dma; 3249 int reg_idx = ring->reg_idx; 3250 3251 /* disable the queue */ 3252 wr32(E1000_TXDCTL(reg_idx), 0); 3253 wrfl(); 3254 mdelay(10); 3255 3256 wr32(E1000_TDLEN(reg_idx), 3257 ring->count * sizeof(union e1000_adv_tx_desc)); 3258 wr32(E1000_TDBAL(reg_idx), 3259 tdba & 0x00000000ffffffffULL); 3260 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3261 3262 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 3263 wr32(E1000_TDH(reg_idx), 0); 3264 writel(0, ring->tail); 3265 3266 txdctl |= IGB_TX_PTHRESH; 3267 txdctl |= IGB_TX_HTHRESH << 8; 3268 txdctl |= IGB_TX_WTHRESH << 16; 3269 3270 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3271 wr32(E1000_TXDCTL(reg_idx), txdctl); 3272} 3273 3274/** 3275 * igb_configure_tx - Configure transmit Unit after Reset 3276 * @adapter: board private structure 3277 * 3278 * Configure the Tx unit of the MAC after a reset. 3279 **/ 3280static void igb_configure_tx(struct igb_adapter *adapter) 3281{ 3282 int i; 3283 3284 for (i = 0; i < adapter->num_tx_queues; i++) 3285 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3286} 3287 3288/** 3289 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3290 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3291 * 3292 * Returns 0 on success, negative on failure 3293 **/ 3294int igb_setup_rx_resources(struct igb_ring *rx_ring) 3295{ 3296 struct device *dev = rx_ring->dev; 3297 int size; 3298 3299 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3300 3301 rx_ring->rx_buffer_info = vzalloc(size); 3302 if (!rx_ring->rx_buffer_info) 3303 goto err; 3304 3305 /* Round up to nearest 4K */ 3306 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3307 rx_ring->size = ALIGN(rx_ring->size, 4096); 3308 3309 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3310 &rx_ring->dma, GFP_KERNEL); 3311 if (!rx_ring->desc) 3312 goto err; 3313 3314 rx_ring->next_to_alloc = 0; 3315 rx_ring->next_to_clean = 0; 3316 rx_ring->next_to_use = 0; 3317 3318 return 0; 3319 3320err: 3321 vfree(rx_ring->rx_buffer_info); 3322 rx_ring->rx_buffer_info = NULL; 3323 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3324 return -ENOMEM; 3325} 3326 3327/** 3328 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3329 * (Descriptors) for all queues 3330 * @adapter: board private structure 3331 * 3332 * Return 0 on success, negative on failure 3333 **/ 3334static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3335{ 3336 struct pci_dev *pdev = adapter->pdev; 3337 int i, err = 0; 3338 3339 for (i = 0; i < adapter->num_rx_queues; i++) { 3340 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3341 if (err) { 3342 dev_err(&pdev->dev, 3343 "Allocation for Rx Queue %u failed\n", i); 3344 for (i--; i >= 0; i--) 3345 igb_free_rx_resources(adapter->rx_ring[i]); 3346 break; 3347 } 3348 } 3349 3350 return err; 3351} 3352 3353/** 3354 * igb_setup_mrqc - configure the multiple receive queue control registers 3355 * @adapter: Board private structure 3356 **/ 3357static void igb_setup_mrqc(struct igb_adapter *adapter) 3358{ 3359 struct e1000_hw *hw = &adapter->hw; 3360 u32 mrqc, rxcsum; 3361 u32 j, num_rx_queues; 3362 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, 3363 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, 3364 0xA32DCB77, 0x0CF23080, 0x3BB7426A, 3365 0xFA01ACBE }; 3366 3367 /* Fill out hash function seeds */ 3368 for (j = 0; j < 10; j++) 3369 wr32(E1000_RSSRK(j), rsskey[j]); 3370 3371 num_rx_queues = adapter->rss_queues; 3372 3373 switch (hw->mac.type) { 3374 case e1000_82576: 3375 /* 82576 supports 2 RSS queues for SR-IOV */ 3376 if (adapter->vfs_allocated_count) 3377 num_rx_queues = 2; 3378 break; 3379 default: 3380 break; 3381 } 3382 3383 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3384 for (j = 0; j < IGB_RETA_SIZE; j++) 3385 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE; 3386 adapter->rss_indir_tbl_init = num_rx_queues; 3387 } 3388 igb_write_rss_indir_tbl(adapter); 3389 3390 /* Disable raw packet checksumming so that RSS hash is placed in 3391 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3392 * offloads as they are enabled by default 3393 */ 3394 rxcsum = rd32(E1000_RXCSUM); 3395 rxcsum |= E1000_RXCSUM_PCSD; 3396 3397 if (adapter->hw.mac.type >= e1000_82576) 3398 /* Enable Receive Checksum Offload for SCTP */ 3399 rxcsum |= E1000_RXCSUM_CRCOFL; 3400 3401 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3402 wr32(E1000_RXCSUM, rxcsum); 3403 3404 /* Generate RSS hash based on packet types, TCP/UDP 3405 * port numbers and/or IPv4/v6 src and dst addresses 3406 */ 3407 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3408 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3409 E1000_MRQC_RSS_FIELD_IPV6 | 3410 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3411 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3412 3413 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3414 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3415 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3416 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3417 3418 /* If VMDq is enabled then we set the appropriate mode for that, else 3419 * we default to RSS so that an RSS hash is calculated per packet even 3420 * if we are only using one queue 3421 */ 3422 if (adapter->vfs_allocated_count) { 3423 if (hw->mac.type > e1000_82575) { 3424 /* Set the default pool for the PF's first queue */ 3425 u32 vtctl = rd32(E1000_VT_CTL); 3426 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3427 E1000_VT_CTL_DISABLE_DEF_POOL); 3428 vtctl |= adapter->vfs_allocated_count << 3429 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3430 wr32(E1000_VT_CTL, vtctl); 3431 } 3432 if (adapter->rss_queues > 1) 3433 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 3434 else 3435 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3436 } else { 3437 if (hw->mac.type != e1000_i211) 3438 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 3439 } 3440 igb_vmm_control(adapter); 3441 3442 wr32(E1000_MRQC, mrqc); 3443} 3444 3445/** 3446 * igb_setup_rctl - configure the receive control registers 3447 * @adapter: Board private structure 3448 **/ 3449void igb_setup_rctl(struct igb_adapter *adapter) 3450{ 3451 struct e1000_hw *hw = &adapter->hw; 3452 u32 rctl; 3453 3454 rctl = rd32(E1000_RCTL); 3455 3456 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3457 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3458 3459 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3460 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3461 3462 /* enable stripping of CRC. It's unlikely this will break BMC 3463 * redirection as it did with e1000. Newer features require 3464 * that the HW strips the CRC. 3465 */ 3466 rctl |= E1000_RCTL_SECRC; 3467 3468 /* disable store bad packets and clear size bits. */ 3469 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3470 3471 /* enable LPE to prevent packets larger than max_frame_size */ 3472 rctl |= E1000_RCTL_LPE; 3473 3474 /* disable queue 0 to prevent tail write w/o re-config */ 3475 wr32(E1000_RXDCTL(0), 0); 3476 3477 /* Attention!!! For SR-IOV PF driver operations you must enable 3478 * queue drop for all VF and PF queues to prevent head of line blocking 3479 * if an un-trusted VF does not provide descriptors to hardware. 3480 */ 3481 if (adapter->vfs_allocated_count) { 3482 /* set all queue drop enable bits */ 3483 wr32(E1000_QDE, ALL_QUEUES); 3484 } 3485 3486 /* This is useful for sniffing bad packets. */ 3487 if (adapter->netdev->features & NETIF_F_RXALL) { 3488 /* UPE and MPE will be handled by normal PROMISC logic 3489 * in e1000e_set_rx_mode 3490 */ 3491 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3492 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3493 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3494 3495 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3496 E1000_RCTL_DPF | /* Allow filtered pause */ 3497 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3498 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3499 * and that breaks VLANs. 3500 */ 3501 } 3502 3503 wr32(E1000_RCTL, rctl); 3504} 3505 3506static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3507 int vfn) 3508{ 3509 struct e1000_hw *hw = &adapter->hw; 3510 u32 vmolr; 3511 3512 /* if it isn't the PF check to see if VFs are enabled and 3513 * increase the size to support vlan tags 3514 */ 3515 if (vfn < adapter->vfs_allocated_count && 3516 adapter->vf_data[vfn].vlans_enabled) 3517 size += VLAN_TAG_SIZE; 3518 3519 vmolr = rd32(E1000_VMOLR(vfn)); 3520 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3521 vmolr |= size | E1000_VMOLR_LPE; 3522 wr32(E1000_VMOLR(vfn), vmolr); 3523 3524 return 0; 3525} 3526 3527/** 3528 * igb_rlpml_set - set maximum receive packet size 3529 * @adapter: board private structure 3530 * 3531 * Configure maximum receivable packet size. 3532 **/ 3533static void igb_rlpml_set(struct igb_adapter *adapter) 3534{ 3535 u32 max_frame_size = adapter->max_frame_size; 3536 struct e1000_hw *hw = &adapter->hw; 3537 u16 pf_id = adapter->vfs_allocated_count; 3538 3539 if (pf_id) { 3540 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3541 /* If we're in VMDQ or SR-IOV mode, then set global RLPML 3542 * to our max jumbo frame size, in case we need to enable 3543 * jumbo frames on one of the rings later. 3544 * This will not pass over-length frames into the default 3545 * queue because it's gated by the VMOLR.RLPML. 3546 */ 3547 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3548 } 3549 3550 wr32(E1000_RLPML, max_frame_size); 3551} 3552 3553static inline void igb_set_vmolr(struct igb_adapter *adapter, 3554 int vfn, bool aupe) 3555{ 3556 struct e1000_hw *hw = &adapter->hw; 3557 u32 vmolr; 3558 3559 /* This register exists only on 82576 and newer so if we are older then 3560 * we should exit and do nothing 3561 */ 3562 if (hw->mac.type < e1000_82576) 3563 return; 3564 3565 vmolr = rd32(E1000_VMOLR(vfn)); 3566 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3567 if (hw->mac.type == e1000_i350) { 3568 u32 dvmolr; 3569 3570 dvmolr = rd32(E1000_DVMOLR(vfn)); 3571 dvmolr |= E1000_DVMOLR_STRVLAN; 3572 wr32(E1000_DVMOLR(vfn), dvmolr); 3573 } 3574 if (aupe) 3575 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3576 else 3577 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3578 3579 /* clear all bits that might not be set */ 3580 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3581 3582 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3583 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3584 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3585 * multicast packets 3586 */ 3587 if (vfn <= adapter->vfs_allocated_count) 3588 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3589 3590 wr32(E1000_VMOLR(vfn), vmolr); 3591} 3592 3593/** 3594 * igb_configure_rx_ring - Configure a receive ring after Reset 3595 * @adapter: board private structure 3596 * @ring: receive ring to be configured 3597 * 3598 * Configure the Rx unit of the MAC after a reset. 3599 **/ 3600void igb_configure_rx_ring(struct igb_adapter *adapter, 3601 struct igb_ring *ring) 3602{ 3603 struct e1000_hw *hw = &adapter->hw; 3604 u64 rdba = ring->dma; 3605 int reg_idx = ring->reg_idx; 3606 u32 srrctl = 0, rxdctl = 0; 3607 3608 /* disable the queue */ 3609 wr32(E1000_RXDCTL(reg_idx), 0); 3610 3611 /* Set DMA base address registers */ 3612 wr32(E1000_RDBAL(reg_idx), 3613 rdba & 0x00000000ffffffffULL); 3614 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3615 wr32(E1000_RDLEN(reg_idx), 3616 ring->count * sizeof(union e1000_adv_rx_desc)); 3617 3618 /* initialize head and tail */ 3619 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3620 wr32(E1000_RDH(reg_idx), 0); 3621 writel(0, ring->tail); 3622 3623 /* set descriptor configuration */ 3624 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3625 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3626 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3627 if (hw->mac.type >= e1000_82580) 3628 srrctl |= E1000_SRRCTL_TIMESTAMP; 3629 /* Only set Drop Enable if we are supporting multiple queues */ 3630 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3631 srrctl |= E1000_SRRCTL_DROP_EN; 3632 3633 wr32(E1000_SRRCTL(reg_idx), srrctl); 3634 3635 /* set filtering for VMDQ pools */ 3636 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3637 3638 rxdctl |= IGB_RX_PTHRESH; 3639 rxdctl |= IGB_RX_HTHRESH << 8; 3640 rxdctl |= IGB_RX_WTHRESH << 16; 3641 3642 /* enable receive descriptor fetching */ 3643 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3644 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3645} 3646 3647/** 3648 * igb_configure_rx - Configure receive Unit after Reset 3649 * @adapter: board private structure 3650 * 3651 * Configure the Rx unit of the MAC after a reset. 3652 **/ 3653static void igb_configure_rx(struct igb_adapter *adapter) 3654{ 3655 int i; 3656 3657 /* set UTA to appropriate mode */ 3658 igb_set_uta(adapter); 3659 3660 /* set the correct pool for the PF default MAC address in entry 0 */ 3661 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3662 adapter->vfs_allocated_count); 3663 3664 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3665 * the Base and Length of the Rx Descriptor Ring 3666 */ 3667 for (i = 0; i < adapter->num_rx_queues; i++) 3668 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3669} 3670 3671/** 3672 * igb_free_tx_resources - Free Tx Resources per Queue 3673 * @tx_ring: Tx descriptor ring for a specific queue 3674 * 3675 * Free all transmit software resources 3676 **/ 3677void igb_free_tx_resources(struct igb_ring *tx_ring) 3678{ 3679 igb_clean_tx_ring(tx_ring); 3680 3681 vfree(tx_ring->tx_buffer_info); 3682 tx_ring->tx_buffer_info = NULL; 3683 3684 /* if not set, then don't free */ 3685 if (!tx_ring->desc) 3686 return; 3687 3688 dma_free_coherent(tx_ring->dev, tx_ring->size, 3689 tx_ring->desc, tx_ring->dma); 3690 3691 tx_ring->desc = NULL; 3692} 3693 3694/** 3695 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3696 * @adapter: board private structure 3697 * 3698 * Free all transmit software resources 3699 **/ 3700static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3701{ 3702 int i; 3703 3704 for (i = 0; i < adapter->num_tx_queues; i++) 3705 igb_free_tx_resources(adapter->tx_ring[i]); 3706} 3707 3708void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3709 struct igb_tx_buffer *tx_buffer) 3710{ 3711 if (tx_buffer->skb) { 3712 dev_kfree_skb_any(tx_buffer->skb); 3713 if (dma_unmap_len(tx_buffer, len)) 3714 dma_unmap_single(ring->dev, 3715 dma_unmap_addr(tx_buffer, dma), 3716 dma_unmap_len(tx_buffer, len), 3717 DMA_TO_DEVICE); 3718 } else if (dma_unmap_len(tx_buffer, len)) { 3719 dma_unmap_page(ring->dev, 3720 dma_unmap_addr(tx_buffer, dma), 3721 dma_unmap_len(tx_buffer, len), 3722 DMA_TO_DEVICE); 3723 } 3724 tx_buffer->next_to_watch = NULL; 3725 tx_buffer->skb = NULL; 3726 dma_unmap_len_set(tx_buffer, len, 0); 3727 /* buffer_info must be completely set up in the transmit path */ 3728} 3729 3730/** 3731 * igb_clean_tx_ring - Free Tx Buffers 3732 * @tx_ring: ring to be cleaned 3733 **/ 3734static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3735{ 3736 struct igb_tx_buffer *buffer_info; 3737 unsigned long size; 3738 u16 i; 3739 3740 if (!tx_ring->tx_buffer_info) 3741 return; 3742 /* Free all the Tx ring sk_buffs */ 3743 3744 for (i = 0; i < tx_ring->count; i++) { 3745 buffer_info = &tx_ring->tx_buffer_info[i]; 3746 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3747 } 3748 3749 netdev_tx_reset_queue(txring_txq(tx_ring)); 3750 3751 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3752 memset(tx_ring->tx_buffer_info, 0, size); 3753 3754 /* Zero out the descriptor ring */ 3755 memset(tx_ring->desc, 0, tx_ring->size); 3756 3757 tx_ring->next_to_use = 0; 3758 tx_ring->next_to_clean = 0; 3759} 3760 3761/** 3762 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3763 * @adapter: board private structure 3764 **/ 3765static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3766{ 3767 int i; 3768 3769 for (i = 0; i < adapter->num_tx_queues; i++) 3770 igb_clean_tx_ring(adapter->tx_ring[i]); 3771} 3772 3773/** 3774 * igb_free_rx_resources - Free Rx Resources 3775 * @rx_ring: ring to clean the resources from 3776 * 3777 * Free all receive software resources 3778 **/ 3779void igb_free_rx_resources(struct igb_ring *rx_ring) 3780{ 3781 igb_clean_rx_ring(rx_ring); 3782 3783 vfree(rx_ring->rx_buffer_info); 3784 rx_ring->rx_buffer_info = NULL; 3785 3786 /* if not set, then don't free */ 3787 if (!rx_ring->desc) 3788 return; 3789 3790 dma_free_coherent(rx_ring->dev, rx_ring->size, 3791 rx_ring->desc, rx_ring->dma); 3792 3793 rx_ring->desc = NULL; 3794} 3795 3796/** 3797 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3798 * @adapter: board private structure 3799 * 3800 * Free all receive software resources 3801 **/ 3802static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3803{ 3804 int i; 3805 3806 for (i = 0; i < adapter->num_rx_queues; i++) 3807 igb_free_rx_resources(adapter->rx_ring[i]); 3808} 3809 3810/** 3811 * igb_clean_rx_ring - Free Rx Buffers per Queue 3812 * @rx_ring: ring to free buffers from 3813 **/ 3814static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3815{ 3816 unsigned long size; 3817 u16 i; 3818 3819 if (rx_ring->skb) 3820 dev_kfree_skb(rx_ring->skb); 3821 rx_ring->skb = NULL; 3822 3823 if (!rx_ring->rx_buffer_info) 3824 return; 3825 3826 /* Free all the Rx ring sk_buffs */ 3827 for (i = 0; i < rx_ring->count; i++) { 3828 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3829 3830 if (!buffer_info->page) 3831 continue; 3832 3833 dma_unmap_page(rx_ring->dev, 3834 buffer_info->dma, 3835 PAGE_SIZE, 3836 DMA_FROM_DEVICE); 3837 __free_page(buffer_info->page); 3838 3839 buffer_info->page = NULL; 3840 } 3841 3842 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3843 memset(rx_ring->rx_buffer_info, 0, size); 3844 3845 /* Zero out the descriptor ring */ 3846 memset(rx_ring->desc, 0, rx_ring->size); 3847 3848 rx_ring->next_to_alloc = 0; 3849 rx_ring->next_to_clean = 0; 3850 rx_ring->next_to_use = 0; 3851} 3852 3853/** 3854 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3855 * @adapter: board private structure 3856 **/ 3857static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3858{ 3859 int i; 3860 3861 for (i = 0; i < adapter->num_rx_queues; i++) 3862 igb_clean_rx_ring(adapter->rx_ring[i]); 3863} 3864 3865/** 3866 * igb_set_mac - Change the Ethernet Address of the NIC 3867 * @netdev: network interface device structure 3868 * @p: pointer to an address structure 3869 * 3870 * Returns 0 on success, negative on failure 3871 **/ 3872static int igb_set_mac(struct net_device *netdev, void *p) 3873{ 3874 struct igb_adapter *adapter = netdev_priv(netdev); 3875 struct e1000_hw *hw = &adapter->hw; 3876 struct sockaddr *addr = p; 3877 3878 if (!is_valid_ether_addr(addr->sa_data)) 3879 return -EADDRNOTAVAIL; 3880 3881 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3882 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3883 3884 /* set the correct pool for the new PF MAC address in entry 0 */ 3885 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3886 adapter->vfs_allocated_count); 3887 3888 return 0; 3889} 3890 3891/** 3892 * igb_write_mc_addr_list - write multicast addresses to MTA 3893 * @netdev: network interface device structure 3894 * 3895 * Writes multicast address list to the MTA hash table. 3896 * Returns: -ENOMEM on failure 3897 * 0 on no addresses written 3898 * X on writing X addresses to MTA 3899 **/ 3900static int igb_write_mc_addr_list(struct net_device *netdev) 3901{ 3902 struct igb_adapter *adapter = netdev_priv(netdev); 3903 struct e1000_hw *hw = &adapter->hw; 3904 struct netdev_hw_addr *ha; 3905 u8 *mta_list; 3906 int i; 3907 3908 if (netdev_mc_empty(netdev)) { 3909 /* nothing to program, so clear mc list */ 3910 igb_update_mc_addr_list(hw, NULL, 0); 3911 igb_restore_vf_multicasts(adapter); 3912 return 0; 3913 } 3914 3915 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3916 if (!mta_list) 3917 return -ENOMEM; 3918 3919 /* The shared function expects a packed array of only addresses. */ 3920 i = 0; 3921 netdev_for_each_mc_addr(ha, netdev) 3922 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3923 3924 igb_update_mc_addr_list(hw, mta_list, i); 3925 kfree(mta_list); 3926 3927 return netdev_mc_count(netdev); 3928} 3929 3930/** 3931 * igb_write_uc_addr_list - write unicast addresses to RAR table 3932 * @netdev: network interface device structure 3933 * 3934 * Writes unicast address list to the RAR table. 3935 * Returns: -ENOMEM on failure/insufficient address space 3936 * 0 on no addresses written 3937 * X on writing X addresses to the RAR table 3938 **/ 3939static int igb_write_uc_addr_list(struct net_device *netdev) 3940{ 3941 struct igb_adapter *adapter = netdev_priv(netdev); 3942 struct e1000_hw *hw = &adapter->hw; 3943 unsigned int vfn = adapter->vfs_allocated_count; 3944 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3945 int count = 0; 3946 3947 /* return ENOMEM indicating insufficient memory for addresses */ 3948 if (netdev_uc_count(netdev) > rar_entries) 3949 return -ENOMEM; 3950 3951 if (!netdev_uc_empty(netdev) && rar_entries) { 3952 struct netdev_hw_addr *ha; 3953 3954 netdev_for_each_uc_addr(ha, netdev) { 3955 if (!rar_entries) 3956 break; 3957 igb_rar_set_qsel(adapter, ha->addr, 3958 rar_entries--, 3959 vfn); 3960 count++; 3961 } 3962 } 3963 /* write the addresses in reverse order to avoid write combining */ 3964 for (; rar_entries > 0 ; rar_entries--) { 3965 wr32(E1000_RAH(rar_entries), 0); 3966 wr32(E1000_RAL(rar_entries), 0); 3967 } 3968 wrfl(); 3969 3970 return count; 3971} 3972 3973/** 3974 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3975 * @netdev: network interface device structure 3976 * 3977 * The set_rx_mode entry point is called whenever the unicast or multicast 3978 * address lists or the network interface flags are updated. This routine is 3979 * responsible for configuring the hardware for proper unicast, multicast, 3980 * promiscuous mode, and all-multi behavior. 3981 **/ 3982static void igb_set_rx_mode(struct net_device *netdev) 3983{ 3984 struct igb_adapter *adapter = netdev_priv(netdev); 3985 struct e1000_hw *hw = &adapter->hw; 3986 unsigned int vfn = adapter->vfs_allocated_count; 3987 u32 rctl, vmolr = 0; 3988 int count; 3989 3990 /* Check for Promiscuous and All Multicast modes */ 3991 rctl = rd32(E1000_RCTL); 3992 3993 /* clear the effected bits */ 3994 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 3995 3996 if (netdev->flags & IFF_PROMISC) { 3997 /* retain VLAN HW filtering if in VT mode */ 3998 if (adapter->vfs_allocated_count) 3999 rctl |= E1000_RCTL_VFE; 4000 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 4001 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 4002 } else { 4003 if (netdev->flags & IFF_ALLMULTI) { 4004 rctl |= E1000_RCTL_MPE; 4005 vmolr |= E1000_VMOLR_MPME; 4006 } else { 4007 /* Write addresses to the MTA, if the attempt fails 4008 * then we should just turn on promiscuous mode so 4009 * that we can at least receive multicast traffic 4010 */ 4011 count = igb_write_mc_addr_list(netdev); 4012 if (count < 0) { 4013 rctl |= E1000_RCTL_MPE; 4014 vmolr |= E1000_VMOLR_MPME; 4015 } else if (count) { 4016 vmolr |= E1000_VMOLR_ROMPE; 4017 } 4018 } 4019 /* Write addresses to available RAR registers, if there is not 4020 * sufficient space to store all the addresses then enable 4021 * unicast promiscuous mode 4022 */ 4023 count = igb_write_uc_addr_list(netdev); 4024 if (count < 0) { 4025 rctl |= E1000_RCTL_UPE; 4026 vmolr |= E1000_VMOLR_ROPE; 4027 } 4028 rctl |= E1000_RCTL_VFE; 4029 } 4030 wr32(E1000_RCTL, rctl); 4031 4032 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4033 * the VMOLR to enable the appropriate modes. Without this workaround 4034 * we will have issues with VLAN tag stripping not being done for frames 4035 * that are only arriving because we are the default pool 4036 */ 4037 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4038 return; 4039 4040 vmolr |= rd32(E1000_VMOLR(vfn)) & 4041 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4042 wr32(E1000_VMOLR(vfn), vmolr); 4043 igb_restore_vf_multicasts(adapter); 4044} 4045 4046static void igb_check_wvbr(struct igb_adapter *adapter) 4047{ 4048 struct e1000_hw *hw = &adapter->hw; 4049 u32 wvbr = 0; 4050 4051 switch (hw->mac.type) { 4052 case e1000_82576: 4053 case e1000_i350: 4054 if (!(wvbr = rd32(E1000_WVBR))) 4055 return; 4056 break; 4057 default: 4058 break; 4059 } 4060 4061 adapter->wvbr |= wvbr; 4062} 4063 4064#define IGB_STAGGERED_QUEUE_OFFSET 8 4065 4066static void igb_spoof_check(struct igb_adapter *adapter) 4067{ 4068 int j; 4069 4070 if (!adapter->wvbr) 4071 return; 4072 4073 for(j = 0; j < adapter->vfs_allocated_count; j++) { 4074 if (adapter->wvbr & (1 << j) || 4075 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 4076 dev_warn(&adapter->pdev->dev, 4077 "Spoof event(s) detected on VF %d\n", j); 4078 adapter->wvbr &= 4079 ~((1 << j) | 4080 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 4081 } 4082 } 4083} 4084 4085/* Need to wait a few seconds after link up to get diagnostic information from 4086 * the phy 4087 */ 4088static void igb_update_phy_info(unsigned long data) 4089{ 4090 struct igb_adapter *adapter = (struct igb_adapter *) data; 4091 igb_get_phy_info(&adapter->hw); 4092} 4093 4094/** 4095 * igb_has_link - check shared code for link and determine up/down 4096 * @adapter: pointer to driver private info 4097 **/ 4098bool igb_has_link(struct igb_adapter *adapter) 4099{ 4100 struct e1000_hw *hw = &adapter->hw; 4101 bool link_active = false; 4102 4103 /* get_link_status is set on LSC (link status) interrupt or 4104 * rx sequence error interrupt. get_link_status will stay 4105 * false until the e1000_check_for_link establishes link 4106 * for copper adapters ONLY 4107 */ 4108 switch (hw->phy.media_type) { 4109 case e1000_media_type_copper: 4110 if (!hw->mac.get_link_status) 4111 return true; 4112 case e1000_media_type_internal_serdes: 4113 hw->mac.ops.check_for_link(hw); 4114 link_active = !hw->mac.get_link_status; 4115 break; 4116 default: 4117 case e1000_media_type_unknown: 4118 break; 4119 } 4120 4121 if (((hw->mac.type == e1000_i210) || 4122 (hw->mac.type == e1000_i211)) && 4123 (hw->phy.id == I210_I_PHY_ID)) { 4124 if (!netif_carrier_ok(adapter->netdev)) { 4125 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4126 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4127 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4128 adapter->link_check_timeout = jiffies; 4129 } 4130 } 4131 4132 return link_active; 4133} 4134 4135static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4136{ 4137 bool ret = false; 4138 u32 ctrl_ext, thstat; 4139 4140 /* check for thermal sensor event on i350 copper only */ 4141 if (hw->mac.type == e1000_i350) { 4142 thstat = rd32(E1000_THSTAT); 4143 ctrl_ext = rd32(E1000_CTRL_EXT); 4144 4145 if ((hw->phy.media_type == e1000_media_type_copper) && 4146 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4147 ret = !!(thstat & event); 4148 } 4149 4150 return ret; 4151} 4152 4153/** 4154 * igb_watchdog - Timer Call-back 4155 * @data: pointer to adapter cast into an unsigned long 4156 **/ 4157static void igb_watchdog(unsigned long data) 4158{ 4159 struct igb_adapter *adapter = (struct igb_adapter *)data; 4160 /* Do the rest outside of interrupt context */ 4161 schedule_work(&adapter->watchdog_task); 4162} 4163 4164static void igb_watchdog_task(struct work_struct *work) 4165{ 4166 struct igb_adapter *adapter = container_of(work, 4167 struct igb_adapter, 4168 watchdog_task); 4169 struct e1000_hw *hw = &adapter->hw; 4170 struct e1000_phy_info *phy = &hw->phy; 4171 struct net_device *netdev = adapter->netdev; 4172 u32 link; 4173 int i; 4174 u32 connsw; 4175 4176 link = igb_has_link(adapter); 4177 4178 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4179 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4180 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4181 else 4182 link = false; 4183 } 4184 4185 /* Force link down if we have fiber to swap to */ 4186 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4187 if (hw->phy.media_type == e1000_media_type_copper) { 4188 connsw = rd32(E1000_CONNSW); 4189 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4190 link = 0; 4191 } 4192 } 4193 if (link) { 4194 /* Perform a reset if the media type changed. */ 4195 if (hw->dev_spec._82575.media_changed) { 4196 hw->dev_spec._82575.media_changed = false; 4197 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4198 igb_reset(adapter); 4199 } 4200 /* Cancel scheduled suspend requests. */ 4201 pm_runtime_resume(netdev->dev.parent); 4202 4203 if (!netif_carrier_ok(netdev)) { 4204 u32 ctrl; 4205 hw->mac.ops.get_speed_and_duplex(hw, 4206 &adapter->link_speed, 4207 &adapter->link_duplex); 4208 4209 ctrl = rd32(E1000_CTRL); 4210 /* Links status message must follow this format */ 4211 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s " 4212 "Duplex, Flow Control: %s\n", 4213 netdev->name, 4214 adapter->link_speed, 4215 adapter->link_duplex == FULL_DUPLEX ? 4216 "Full" : "Half", 4217 (ctrl & E1000_CTRL_TFCE) && 4218 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4219 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4220 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4221 4222 /* disable EEE if enabled */ 4223 if ((adapter->flags & IGB_FLAG_EEE) && 4224 (adapter->link_duplex == HALF_DUPLEX)) { 4225 dev_info(&adapter->pdev->dev, 4226 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4227 adapter->hw.dev_spec._82575.eee_disable = true; 4228 adapter->flags &= ~IGB_FLAG_EEE; 4229 } 4230 4231 /* check if SmartSpeed worked */ 4232 igb_check_downshift(hw); 4233 if (phy->speed_downgraded) 4234 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4235 4236 /* check for thermal sensor event */ 4237 if (igb_thermal_sensor_event(hw, 4238 E1000_THSTAT_LINK_THROTTLE)) { 4239 netdev_info(netdev, "The network adapter link " 4240 "speed was downshifted because it " 4241 "overheated\n"); 4242 } 4243 4244 /* adjust timeout factor according to speed/duplex */ 4245 adapter->tx_timeout_factor = 1; 4246 switch (adapter->link_speed) { 4247 case SPEED_10: 4248 adapter->tx_timeout_factor = 14; 4249 break; 4250 case SPEED_100: 4251 /* maybe add some timeout factor ? */ 4252 break; 4253 } 4254 4255 netif_carrier_on(netdev); 4256 4257 igb_ping_all_vfs(adapter); 4258 igb_check_vf_rate_limit(adapter); 4259 4260 /* link state has changed, schedule phy info update */ 4261 if (!test_bit(__IGB_DOWN, &adapter->state)) 4262 mod_timer(&adapter->phy_info_timer, 4263 round_jiffies(jiffies + 2 * HZ)); 4264 } 4265 } else { 4266 if (netif_carrier_ok(netdev)) { 4267 adapter->link_speed = 0; 4268 adapter->link_duplex = 0; 4269 4270 /* check for thermal sensor event */ 4271 if (igb_thermal_sensor_event(hw, 4272 E1000_THSTAT_PWR_DOWN)) { 4273 netdev_err(netdev, "The network adapter was " 4274 "stopped because it overheated\n"); 4275 } 4276 4277 /* Links status message must follow this format */ 4278 printk(KERN_INFO "igb: %s NIC Link is Down\n", 4279 netdev->name); 4280 netif_carrier_off(netdev); 4281 4282 igb_ping_all_vfs(adapter); 4283 4284 /* link state has changed, schedule phy info update */ 4285 if (!test_bit(__IGB_DOWN, &adapter->state)) 4286 mod_timer(&adapter->phy_info_timer, 4287 round_jiffies(jiffies + 2 * HZ)); 4288 4289 /* link is down, time to check for alternate media */ 4290 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4291 igb_check_swap_media(adapter); 4292 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4293 schedule_work(&adapter->reset_task); 4294 /* return immediately */ 4295 return; 4296 } 4297 } 4298 pm_schedule_suspend(netdev->dev.parent, 4299 MSEC_PER_SEC * 5); 4300 4301 /* also check for alternate media here */ 4302 } else if (!netif_carrier_ok(netdev) && 4303 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4304 igb_check_swap_media(adapter); 4305 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4306 schedule_work(&adapter->reset_task); 4307 /* return immediately */ 4308 return; 4309 } 4310 } 4311 } 4312 4313 spin_lock(&adapter->stats64_lock); 4314 igb_update_stats(adapter, &adapter->stats64); 4315 spin_unlock(&adapter->stats64_lock); 4316 4317 for (i = 0; i < adapter->num_tx_queues; i++) { 4318 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4319 if (!netif_carrier_ok(netdev)) { 4320 /* We've lost link, so the controller stops DMA, 4321 * but we've got queued Tx work that's never going 4322 * to get done, so reset controller to flush Tx. 4323 * (Do the reset outside of interrupt context). 4324 */ 4325 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4326 adapter->tx_timeout_count++; 4327 schedule_work(&adapter->reset_task); 4328 /* return immediately since reset is imminent */ 4329 return; 4330 } 4331 } 4332 4333 /* Force detection of hung controller every watchdog period */ 4334 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4335 } 4336 4337 /* Cause software interrupt to ensure Rx ring is cleaned */ 4338 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4339 u32 eics = 0; 4340 for (i = 0; i < adapter->num_q_vectors; i++) 4341 eics |= adapter->q_vector[i]->eims_value; 4342 wr32(E1000_EICS, eics); 4343 } else { 4344 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4345 } 4346 4347 igb_spoof_check(adapter); 4348 igb_ptp_rx_hang(adapter); 4349 4350 /* Reset the timer */ 4351 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4352 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4353 mod_timer(&adapter->watchdog_timer, 4354 round_jiffies(jiffies + HZ)); 4355 else 4356 mod_timer(&adapter->watchdog_timer, 4357 round_jiffies(jiffies + 2 * HZ)); 4358 } 4359} 4360 4361enum latency_range { 4362 lowest_latency = 0, 4363 low_latency = 1, 4364 bulk_latency = 2, 4365 latency_invalid = 255 4366}; 4367 4368/** 4369 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4370 * @q_vector: pointer to q_vector 4371 * 4372 * Stores a new ITR value based on strictly on packet size. This 4373 * algorithm is less sophisticated than that used in igb_update_itr, 4374 * due to the difficulty of synchronizing statistics across multiple 4375 * receive rings. The divisors and thresholds used by this function 4376 * were determined based on theoretical maximum wire speed and testing 4377 * data, in order to minimize response time while increasing bulk 4378 * throughput. 4379 * This functionality is controlled by ethtool's coalescing settings. 4380 * NOTE: This function is called only when operating in a multiqueue 4381 * receive environment. 4382 **/ 4383static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4384{ 4385 int new_val = q_vector->itr_val; 4386 int avg_wire_size = 0; 4387 struct igb_adapter *adapter = q_vector->adapter; 4388 unsigned int packets; 4389 4390 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4391 * ints/sec - ITR timer value of 120 ticks. 4392 */ 4393 if (adapter->link_speed != SPEED_1000) { 4394 new_val = IGB_4K_ITR; 4395 goto set_itr_val; 4396 } 4397 4398 packets = q_vector->rx.total_packets; 4399 if (packets) 4400 avg_wire_size = q_vector->rx.total_bytes / packets; 4401 4402 packets = q_vector->tx.total_packets; 4403 if (packets) 4404 avg_wire_size = max_t(u32, avg_wire_size, 4405 q_vector->tx.total_bytes / packets); 4406 4407 /* if avg_wire_size isn't set no work was done */ 4408 if (!avg_wire_size) 4409 goto clear_counts; 4410 4411 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4412 avg_wire_size += 24; 4413 4414 /* Don't starve jumbo frames */ 4415 avg_wire_size = min(avg_wire_size, 3000); 4416 4417 /* Give a little boost to mid-size frames */ 4418 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4419 new_val = avg_wire_size / 3; 4420 else 4421 new_val = avg_wire_size / 2; 4422 4423 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4424 if (new_val < IGB_20K_ITR && 4425 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4426 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4427 new_val = IGB_20K_ITR; 4428 4429set_itr_val: 4430 if (new_val != q_vector->itr_val) { 4431 q_vector->itr_val = new_val; 4432 q_vector->set_itr = 1; 4433 } 4434clear_counts: 4435 q_vector->rx.total_bytes = 0; 4436 q_vector->rx.total_packets = 0; 4437 q_vector->tx.total_bytes = 0; 4438 q_vector->tx.total_packets = 0; 4439} 4440 4441/** 4442 * igb_update_itr - update the dynamic ITR value based on statistics 4443 * @q_vector: pointer to q_vector 4444 * @ring_container: ring info to update the itr for 4445 * 4446 * Stores a new ITR value based on packets and byte 4447 * counts during the last interrupt. The advantage of per interrupt 4448 * computation is faster updates and more accurate ITR for the current 4449 * traffic pattern. Constants in this function were computed 4450 * based on theoretical maximum wire speed and thresholds were set based 4451 * on testing data as well as attempting to minimize response time 4452 * while increasing bulk throughput. 4453 * This functionality is controlled by ethtool's coalescing settings. 4454 * NOTE: These calculations are only valid when operating in a single- 4455 * queue environment. 4456 **/ 4457static void igb_update_itr(struct igb_q_vector *q_vector, 4458 struct igb_ring_container *ring_container) 4459{ 4460 unsigned int packets = ring_container->total_packets; 4461 unsigned int bytes = ring_container->total_bytes; 4462 u8 itrval = ring_container->itr; 4463 4464 /* no packets, exit with status unchanged */ 4465 if (packets == 0) 4466 return; 4467 4468 switch (itrval) { 4469 case lowest_latency: 4470 /* handle TSO and jumbo frames */ 4471 if (bytes/packets > 8000) 4472 itrval = bulk_latency; 4473 else if ((packets < 5) && (bytes > 512)) 4474 itrval = low_latency; 4475 break; 4476 case low_latency: /* 50 usec aka 20000 ints/s */ 4477 if (bytes > 10000) { 4478 /* this if handles the TSO accounting */ 4479 if (bytes/packets > 8000) { 4480 itrval = bulk_latency; 4481 } else if ((packets < 10) || ((bytes/packets) > 1200)) { 4482 itrval = bulk_latency; 4483 } else if ((packets > 35)) { 4484 itrval = lowest_latency; 4485 } 4486 } else if (bytes/packets > 2000) { 4487 itrval = bulk_latency; 4488 } else if (packets <= 2 && bytes < 512) { 4489 itrval = lowest_latency; 4490 } 4491 break; 4492 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4493 if (bytes > 25000) { 4494 if (packets > 35) 4495 itrval = low_latency; 4496 } else if (bytes < 1500) { 4497 itrval = low_latency; 4498 } 4499 break; 4500 } 4501 4502 /* clear work counters since we have the values we need */ 4503 ring_container->total_bytes = 0; 4504 ring_container->total_packets = 0; 4505 4506 /* write updated itr to ring container */ 4507 ring_container->itr = itrval; 4508} 4509 4510static void igb_set_itr(struct igb_q_vector *q_vector) 4511{ 4512 struct igb_adapter *adapter = q_vector->adapter; 4513 u32 new_itr = q_vector->itr_val; 4514 u8 current_itr = 0; 4515 4516 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4517 if (adapter->link_speed != SPEED_1000) { 4518 current_itr = 0; 4519 new_itr = IGB_4K_ITR; 4520 goto set_itr_now; 4521 } 4522 4523 igb_update_itr(q_vector, &q_vector->tx); 4524 igb_update_itr(q_vector, &q_vector->rx); 4525 4526 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4527 4528 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4529 if (current_itr == lowest_latency && 4530 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4531 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4532 current_itr = low_latency; 4533 4534 switch (current_itr) { 4535 /* counts and packets in update_itr are dependent on these numbers */ 4536 case lowest_latency: 4537 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4538 break; 4539 case low_latency: 4540 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4541 break; 4542 case bulk_latency: 4543 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4544 break; 4545 default: 4546 break; 4547 } 4548 4549set_itr_now: 4550 if (new_itr != q_vector->itr_val) { 4551 /* this attempts to bias the interrupt rate towards Bulk 4552 * by adding intermediate steps when interrupt rate is 4553 * increasing 4554 */ 4555 new_itr = new_itr > q_vector->itr_val ? 4556 max((new_itr * q_vector->itr_val) / 4557 (new_itr + (q_vector->itr_val >> 2)), 4558 new_itr) : new_itr; 4559 /* Don't write the value here; it resets the adapter's 4560 * internal timer, and causes us to delay far longer than 4561 * we should between interrupts. Instead, we write the ITR 4562 * value at the beginning of the next interrupt so the timing 4563 * ends up being correct. 4564 */ 4565 q_vector->itr_val = new_itr; 4566 q_vector->set_itr = 1; 4567 } 4568} 4569 4570static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4571 u32 type_tucmd, u32 mss_l4len_idx) 4572{ 4573 struct e1000_adv_tx_context_desc *context_desc; 4574 u16 i = tx_ring->next_to_use; 4575 4576 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4577 4578 i++; 4579 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4580 4581 /* set bits to identify this as an advanced context descriptor */ 4582 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4583 4584 /* For 82575, context index must be unique per ring. */ 4585 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4586 mss_l4len_idx |= tx_ring->reg_idx << 4; 4587 4588 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4589 context_desc->seqnum_seed = 0; 4590 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4591 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4592} 4593 4594static int igb_tso(struct igb_ring *tx_ring, 4595 struct igb_tx_buffer *first, 4596 u8 *hdr_len) 4597{ 4598 struct sk_buff *skb = first->skb; 4599 u32 vlan_macip_lens, type_tucmd; 4600 u32 mss_l4len_idx, l4len; 4601 4602 if (skb->ip_summed != CHECKSUM_PARTIAL) 4603 return 0; 4604 4605 if (!skb_is_gso(skb)) 4606 return 0; 4607 4608 if (skb_header_cloned(skb)) { 4609 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 4610 if (err) 4611 return err; 4612 } 4613 4614 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4615 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4616 4617 if (first->protocol == htons(ETH_P_IP)) { 4618 struct iphdr *iph = ip_hdr(skb); 4619 iph->tot_len = 0; 4620 iph->check = 0; 4621 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4622 iph->daddr, 0, 4623 IPPROTO_TCP, 4624 0); 4625 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4626 first->tx_flags |= IGB_TX_FLAGS_TSO | 4627 IGB_TX_FLAGS_CSUM | 4628 IGB_TX_FLAGS_IPV4; 4629 } else if (skb_is_gso_v6(skb)) { 4630 ipv6_hdr(skb)->payload_len = 0; 4631 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4632 &ipv6_hdr(skb)->daddr, 4633 0, IPPROTO_TCP, 0); 4634 first->tx_flags |= IGB_TX_FLAGS_TSO | 4635 IGB_TX_FLAGS_CSUM; 4636 } 4637 4638 /* compute header lengths */ 4639 l4len = tcp_hdrlen(skb); 4640 *hdr_len = skb_transport_offset(skb) + l4len; 4641 4642 /* update gso size and bytecount with header size */ 4643 first->gso_segs = skb_shinfo(skb)->gso_segs; 4644 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4645 4646 /* MSS L4LEN IDX */ 4647 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4648 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4649 4650 /* VLAN MACLEN IPLEN */ 4651 vlan_macip_lens = skb_network_header_len(skb); 4652 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4653 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4654 4655 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4656 4657 return 1; 4658} 4659 4660static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4661{ 4662 struct sk_buff *skb = first->skb; 4663 u32 vlan_macip_lens = 0; 4664 u32 mss_l4len_idx = 0; 4665 u32 type_tucmd = 0; 4666 4667 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4668 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4669 return; 4670 } else { 4671 u8 l4_hdr = 0; 4672 switch (first->protocol) { 4673 case htons(ETH_P_IP): 4674 vlan_macip_lens |= skb_network_header_len(skb); 4675 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4676 l4_hdr = ip_hdr(skb)->protocol; 4677 break; 4678 case htons(ETH_P_IPV6): 4679 vlan_macip_lens |= skb_network_header_len(skb); 4680 l4_hdr = ipv6_hdr(skb)->nexthdr; 4681 break; 4682 default: 4683 if (unlikely(net_ratelimit())) { 4684 dev_warn(tx_ring->dev, 4685 "partial checksum but proto=%x!\n", 4686 first->protocol); 4687 } 4688 break; 4689 } 4690 4691 switch (l4_hdr) { 4692 case IPPROTO_TCP: 4693 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4694 mss_l4len_idx = tcp_hdrlen(skb) << 4695 E1000_ADVTXD_L4LEN_SHIFT; 4696 break; 4697 case IPPROTO_SCTP: 4698 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4699 mss_l4len_idx = sizeof(struct sctphdr) << 4700 E1000_ADVTXD_L4LEN_SHIFT; 4701 break; 4702 case IPPROTO_UDP: 4703 mss_l4len_idx = sizeof(struct udphdr) << 4704 E1000_ADVTXD_L4LEN_SHIFT; 4705 break; 4706 default: 4707 if (unlikely(net_ratelimit())) { 4708 dev_warn(tx_ring->dev, 4709 "partial checksum but l4 proto=%x!\n", 4710 l4_hdr); 4711 } 4712 break; 4713 } 4714 4715 /* update TX checksum flag */ 4716 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4717 } 4718 4719 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4720 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4721 4722 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4723} 4724 4725#define IGB_SET_FLAG(_input, _flag, _result) \ 4726 ((_flag <= _result) ? \ 4727 ((u32)(_input & _flag) * (_result / _flag)) : \ 4728 ((u32)(_input & _flag) / (_flag / _result))) 4729 4730static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 4731{ 4732 /* set type for advanced descriptor with frame checksum insertion */ 4733 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 4734 E1000_ADVTXD_DCMD_DEXT | 4735 E1000_ADVTXD_DCMD_IFCS; 4736 4737 /* set HW vlan bit if vlan is present */ 4738 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 4739 (E1000_ADVTXD_DCMD_VLE)); 4740 4741 /* set segmentation bits for TSO */ 4742 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 4743 (E1000_ADVTXD_DCMD_TSE)); 4744 4745 /* set timestamp bit if present */ 4746 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 4747 (E1000_ADVTXD_MAC_TSTAMP)); 4748 4749 /* insert frame checksum */ 4750 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 4751 4752 return cmd_type; 4753} 4754 4755static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4756 union e1000_adv_tx_desc *tx_desc, 4757 u32 tx_flags, unsigned int paylen) 4758{ 4759 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4760 4761 /* 82575 requires a unique index per ring */ 4762 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4763 olinfo_status |= tx_ring->reg_idx << 4; 4764 4765 /* insert L4 checksum */ 4766 olinfo_status |= IGB_SET_FLAG(tx_flags, 4767 IGB_TX_FLAGS_CSUM, 4768 (E1000_TXD_POPTS_TXSM << 8)); 4769 4770 /* insert IPv4 checksum */ 4771 olinfo_status |= IGB_SET_FLAG(tx_flags, 4772 IGB_TX_FLAGS_IPV4, 4773 (E1000_TXD_POPTS_IXSM << 8)); 4774 4775 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4776} 4777 4778static void igb_tx_map(struct igb_ring *tx_ring, 4779 struct igb_tx_buffer *first, 4780 const u8 hdr_len) 4781{ 4782 struct sk_buff *skb = first->skb; 4783 struct igb_tx_buffer *tx_buffer; 4784 union e1000_adv_tx_desc *tx_desc; 4785 struct skb_frag_struct *frag; 4786 dma_addr_t dma; 4787 unsigned int data_len, size; 4788 u32 tx_flags = first->tx_flags; 4789 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 4790 u16 i = tx_ring->next_to_use; 4791 4792 tx_desc = IGB_TX_DESC(tx_ring, i); 4793 4794 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 4795 4796 size = skb_headlen(skb); 4797 data_len = skb->data_len; 4798 4799 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4800 4801 tx_buffer = first; 4802 4803 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 4804 if (dma_mapping_error(tx_ring->dev, dma)) 4805 goto dma_error; 4806 4807 /* record length, and DMA address */ 4808 dma_unmap_len_set(tx_buffer, len, size); 4809 dma_unmap_addr_set(tx_buffer, dma, dma); 4810 4811 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4812 4813 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4814 tx_desc->read.cmd_type_len = 4815 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 4816 4817 i++; 4818 tx_desc++; 4819 if (i == tx_ring->count) { 4820 tx_desc = IGB_TX_DESC(tx_ring, 0); 4821 i = 0; 4822 } 4823 tx_desc->read.olinfo_status = 0; 4824 4825 dma += IGB_MAX_DATA_PER_TXD; 4826 size -= IGB_MAX_DATA_PER_TXD; 4827 4828 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4829 } 4830 4831 if (likely(!data_len)) 4832 break; 4833 4834 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 4835 4836 i++; 4837 tx_desc++; 4838 if (i == tx_ring->count) { 4839 tx_desc = IGB_TX_DESC(tx_ring, 0); 4840 i = 0; 4841 } 4842 tx_desc->read.olinfo_status = 0; 4843 4844 size = skb_frag_size(frag); 4845 data_len -= size; 4846 4847 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4848 size, DMA_TO_DEVICE); 4849 4850 tx_buffer = &tx_ring->tx_buffer_info[i]; 4851 } 4852 4853 /* write last descriptor with RS and EOP bits */ 4854 cmd_type |= size | IGB_TXD_DCMD; 4855 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 4856 4857 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4858 4859 /* set the timestamp */ 4860 first->time_stamp = jiffies; 4861 4862 /* Force memory writes to complete before letting h/w know there 4863 * are new descriptors to fetch. (Only applicable for weak-ordered 4864 * memory model archs, such as IA-64). 4865 * 4866 * We also need this memory barrier to make certain all of the 4867 * status bits have been updated before next_to_watch is written. 4868 */ 4869 wmb(); 4870 4871 /* set next_to_watch value indicating a packet is present */ 4872 first->next_to_watch = tx_desc; 4873 4874 i++; 4875 if (i == tx_ring->count) 4876 i = 0; 4877 4878 tx_ring->next_to_use = i; 4879 4880 writel(i, tx_ring->tail); 4881 4882 /* we need this if more than one processor can write to our tail 4883 * at a time, it synchronizes IO on IA64/Altix systems 4884 */ 4885 mmiowb(); 4886 4887 return; 4888 4889dma_error: 4890 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4891 4892 /* clear dma mappings for failed tx_buffer_info map */ 4893 for (;;) { 4894 tx_buffer = &tx_ring->tx_buffer_info[i]; 4895 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4896 if (tx_buffer == first) 4897 break; 4898 if (i == 0) 4899 i = tx_ring->count; 4900 i--; 4901 } 4902 4903 tx_ring->next_to_use = i; 4904} 4905 4906static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4907{ 4908 struct net_device *netdev = tx_ring->netdev; 4909 4910 netif_stop_subqueue(netdev, tx_ring->queue_index); 4911 4912 /* Herbert's original patch had: 4913 * smp_mb__after_netif_stop_queue(); 4914 * but since that doesn't exist yet, just open code it. 4915 */ 4916 smp_mb(); 4917 4918 /* We need to check again in a case another CPU has just 4919 * made room available. 4920 */ 4921 if (igb_desc_unused(tx_ring) < size) 4922 return -EBUSY; 4923 4924 /* A reprieve! */ 4925 netif_wake_subqueue(netdev, tx_ring->queue_index); 4926 4927 u64_stats_update_begin(&tx_ring->tx_syncp2); 4928 tx_ring->tx_stats.restart_queue2++; 4929 u64_stats_update_end(&tx_ring->tx_syncp2); 4930 4931 return 0; 4932} 4933 4934static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4935{ 4936 if (igb_desc_unused(tx_ring) >= size) 4937 return 0; 4938 return __igb_maybe_stop_tx(tx_ring, size); 4939} 4940 4941netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4942 struct igb_ring *tx_ring) 4943{ 4944 struct igb_tx_buffer *first; 4945 int tso; 4946 u32 tx_flags = 0; 4947 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 4948 __be16 protocol = vlan_get_protocol(skb); 4949 u8 hdr_len = 0; 4950 4951 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 4952 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 4953 * + 2 desc gap to keep tail from touching head, 4954 * + 1 desc for context descriptor, 4955 * otherwise try next time 4956 */ 4957 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) { 4958 unsigned short f; 4959 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 4960 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 4961 } else { 4962 count += skb_shinfo(skb)->nr_frags; 4963 } 4964 4965 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 4966 /* this is a hard error */ 4967 return NETDEV_TX_BUSY; 4968 } 4969 4970 /* record the location of the first descriptor for this packet */ 4971 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 4972 first->skb = skb; 4973 first->bytecount = skb->len; 4974 first->gso_segs = 1; 4975 4976 skb_tx_timestamp(skb); 4977 4978 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 4979 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 4980 4981 if (!(adapter->ptp_tx_skb)) { 4982 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4983 tx_flags |= IGB_TX_FLAGS_TSTAMP; 4984 4985 adapter->ptp_tx_skb = skb_get(skb); 4986 adapter->ptp_tx_start = jiffies; 4987 if (adapter->hw.mac.type == e1000_82576) 4988 schedule_work(&adapter->ptp_tx_work); 4989 } 4990 } 4991 4992 if (vlan_tx_tag_present(skb)) { 4993 tx_flags |= IGB_TX_FLAGS_VLAN; 4994 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 4995 } 4996 4997 /* record initial flags and protocol */ 4998 first->tx_flags = tx_flags; 4999 first->protocol = protocol; 5000 5001 tso = igb_tso(tx_ring, first, &hdr_len); 5002 if (tso < 0) 5003 goto out_drop; 5004 else if (!tso) 5005 igb_tx_csum(tx_ring, first); 5006 5007 igb_tx_map(tx_ring, first, hdr_len); 5008 5009 /* Make sure there is space in the ring for the next send. */ 5010 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 5011 5012 return NETDEV_TX_OK; 5013 5014out_drop: 5015 igb_unmap_and_free_tx_resource(tx_ring, first); 5016 5017 return NETDEV_TX_OK; 5018} 5019 5020static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5021 struct sk_buff *skb) 5022{ 5023 unsigned int r_idx = skb->queue_mapping; 5024 5025 if (r_idx >= adapter->num_tx_queues) 5026 r_idx = r_idx % adapter->num_tx_queues; 5027 5028 return adapter->tx_ring[r_idx]; 5029} 5030 5031static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5032 struct net_device *netdev) 5033{ 5034 struct igb_adapter *adapter = netdev_priv(netdev); 5035 5036 if (test_bit(__IGB_DOWN, &adapter->state)) { 5037 dev_kfree_skb_any(skb); 5038 return NETDEV_TX_OK; 5039 } 5040 5041 if (skb->len <= 0) { 5042 dev_kfree_skb_any(skb); 5043 return NETDEV_TX_OK; 5044 } 5045 5046 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5047 * in order to meet this minimum size requirement. 5048 */ 5049 if (unlikely(skb->len < 17)) { 5050 if (skb_pad(skb, 17 - skb->len)) 5051 return NETDEV_TX_OK; 5052 skb->len = 17; 5053 skb_set_tail_pointer(skb, 17); 5054 } 5055 5056 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5057} 5058 5059/** 5060 * igb_tx_timeout - Respond to a Tx Hang 5061 * @netdev: network interface device structure 5062 **/ 5063static void igb_tx_timeout(struct net_device *netdev) 5064{ 5065 struct igb_adapter *adapter = netdev_priv(netdev); 5066 struct e1000_hw *hw = &adapter->hw; 5067 5068 /* Do the reset outside of interrupt context */ 5069 adapter->tx_timeout_count++; 5070 5071 if (hw->mac.type >= e1000_82580) 5072 hw->dev_spec._82575.global_device_reset = true; 5073 5074 schedule_work(&adapter->reset_task); 5075 wr32(E1000_EICS, 5076 (adapter->eims_enable_mask & ~adapter->eims_other)); 5077} 5078 5079static void igb_reset_task(struct work_struct *work) 5080{ 5081 struct igb_adapter *adapter; 5082 adapter = container_of(work, struct igb_adapter, reset_task); 5083 5084 igb_dump(adapter); 5085 netdev_err(adapter->netdev, "Reset adapter\n"); 5086 igb_reinit_locked(adapter); 5087} 5088 5089/** 5090 * igb_get_stats64 - Get System Network Statistics 5091 * @netdev: network interface device structure 5092 * @stats: rtnl_link_stats64 pointer 5093 **/ 5094static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 5095 struct rtnl_link_stats64 *stats) 5096{ 5097 struct igb_adapter *adapter = netdev_priv(netdev); 5098 5099 spin_lock(&adapter->stats64_lock); 5100 igb_update_stats(adapter, &adapter->stats64); 5101 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5102 spin_unlock(&adapter->stats64_lock); 5103 5104 return stats; 5105} 5106 5107/** 5108 * igb_change_mtu - Change the Maximum Transfer Unit 5109 * @netdev: network interface device structure 5110 * @new_mtu: new value for maximum frame size 5111 * 5112 * Returns 0 on success, negative on failure 5113 **/ 5114static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5115{ 5116 struct igb_adapter *adapter = netdev_priv(netdev); 5117 struct pci_dev *pdev = adapter->pdev; 5118 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5119 5120 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 5121 dev_err(&pdev->dev, "Invalid MTU setting\n"); 5122 return -EINVAL; 5123 } 5124 5125#define MAX_STD_JUMBO_FRAME_SIZE 9238 5126 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 5127 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 5128 return -EINVAL; 5129 } 5130 5131 /* adjust max frame to be at least the size of a standard frame */ 5132 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5133 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5134 5135 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5136 msleep(1); 5137 5138 /* igb_down has a dependency on max_frame_size */ 5139 adapter->max_frame_size = max_frame; 5140 5141 if (netif_running(netdev)) 5142 igb_down(adapter); 5143 5144 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5145 netdev->mtu, new_mtu); 5146 netdev->mtu = new_mtu; 5147 5148 if (netif_running(netdev)) 5149 igb_up(adapter); 5150 else 5151 igb_reset(adapter); 5152 5153 clear_bit(__IGB_RESETTING, &adapter->state); 5154 5155 return 0; 5156} 5157 5158/** 5159 * igb_update_stats - Update the board statistics counters 5160 * @adapter: board private structure 5161 **/ 5162void igb_update_stats(struct igb_adapter *adapter, 5163 struct rtnl_link_stats64 *net_stats) 5164{ 5165 struct e1000_hw *hw = &adapter->hw; 5166 struct pci_dev *pdev = adapter->pdev; 5167 u32 reg, mpc; 5168 u16 phy_tmp; 5169 int i; 5170 u64 bytes, packets; 5171 unsigned int start; 5172 u64 _bytes, _packets; 5173 5174#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF 5175 5176 /* Prevent stats update while adapter is being reset, or if the pci 5177 * connection is down. 5178 */ 5179 if (adapter->link_speed == 0) 5180 return; 5181 if (pci_channel_offline(pdev)) 5182 return; 5183 5184 bytes = 0; 5185 packets = 0; 5186 5187 rcu_read_lock(); 5188 for (i = 0; i < adapter->num_rx_queues; i++) { 5189 u32 rqdpc = rd32(E1000_RQDPC(i)); 5190 struct igb_ring *ring = adapter->rx_ring[i]; 5191 5192 if (rqdpc) { 5193 ring->rx_stats.drops += rqdpc; 5194 net_stats->rx_fifo_errors += rqdpc; 5195 } 5196 5197 do { 5198 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5199 _bytes = ring->rx_stats.bytes; 5200 _packets = ring->rx_stats.packets; 5201 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5202 bytes += _bytes; 5203 packets += _packets; 5204 } 5205 5206 net_stats->rx_bytes = bytes; 5207 net_stats->rx_packets = packets; 5208 5209 bytes = 0; 5210 packets = 0; 5211 for (i = 0; i < adapter->num_tx_queues; i++) { 5212 struct igb_ring *ring = adapter->tx_ring[i]; 5213 do { 5214 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5215 _bytes = ring->tx_stats.bytes; 5216 _packets = ring->tx_stats.packets; 5217 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5218 bytes += _bytes; 5219 packets += _packets; 5220 } 5221 net_stats->tx_bytes = bytes; 5222 net_stats->tx_packets = packets; 5223 rcu_read_unlock(); 5224 5225 /* read stats registers */ 5226 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5227 adapter->stats.gprc += rd32(E1000_GPRC); 5228 adapter->stats.gorc += rd32(E1000_GORCL); 5229 rd32(E1000_GORCH); /* clear GORCL */ 5230 adapter->stats.bprc += rd32(E1000_BPRC); 5231 adapter->stats.mprc += rd32(E1000_MPRC); 5232 adapter->stats.roc += rd32(E1000_ROC); 5233 5234 adapter->stats.prc64 += rd32(E1000_PRC64); 5235 adapter->stats.prc127 += rd32(E1000_PRC127); 5236 adapter->stats.prc255 += rd32(E1000_PRC255); 5237 adapter->stats.prc511 += rd32(E1000_PRC511); 5238 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5239 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5240 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5241 adapter->stats.sec += rd32(E1000_SEC); 5242 5243 mpc = rd32(E1000_MPC); 5244 adapter->stats.mpc += mpc; 5245 net_stats->rx_fifo_errors += mpc; 5246 adapter->stats.scc += rd32(E1000_SCC); 5247 adapter->stats.ecol += rd32(E1000_ECOL); 5248 adapter->stats.mcc += rd32(E1000_MCC); 5249 adapter->stats.latecol += rd32(E1000_LATECOL); 5250 adapter->stats.dc += rd32(E1000_DC); 5251 adapter->stats.rlec += rd32(E1000_RLEC); 5252 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5253 adapter->stats.xontxc += rd32(E1000_XONTXC); 5254 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5255 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5256 adapter->stats.fcruc += rd32(E1000_FCRUC); 5257 adapter->stats.gptc += rd32(E1000_GPTC); 5258 adapter->stats.gotc += rd32(E1000_GOTCL); 5259 rd32(E1000_GOTCH); /* clear GOTCL */ 5260 adapter->stats.rnbc += rd32(E1000_RNBC); 5261 adapter->stats.ruc += rd32(E1000_RUC); 5262 adapter->stats.rfc += rd32(E1000_RFC); 5263 adapter->stats.rjc += rd32(E1000_RJC); 5264 adapter->stats.tor += rd32(E1000_TORH); 5265 adapter->stats.tot += rd32(E1000_TOTH); 5266 adapter->stats.tpr += rd32(E1000_TPR); 5267 5268 adapter->stats.ptc64 += rd32(E1000_PTC64); 5269 adapter->stats.ptc127 += rd32(E1000_PTC127); 5270 adapter->stats.ptc255 += rd32(E1000_PTC255); 5271 adapter->stats.ptc511 += rd32(E1000_PTC511); 5272 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5273 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5274 5275 adapter->stats.mptc += rd32(E1000_MPTC); 5276 adapter->stats.bptc += rd32(E1000_BPTC); 5277 5278 adapter->stats.tpt += rd32(E1000_TPT); 5279 adapter->stats.colc += rd32(E1000_COLC); 5280 5281 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5282 /* read internal phy specific stats */ 5283 reg = rd32(E1000_CTRL_EXT); 5284 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5285 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5286 5287 /* this stat has invalid values on i210/i211 */ 5288 if ((hw->mac.type != e1000_i210) && 5289 (hw->mac.type != e1000_i211)) 5290 adapter->stats.tncrs += rd32(E1000_TNCRS); 5291 } 5292 5293 adapter->stats.tsctc += rd32(E1000_TSCTC); 5294 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5295 5296 adapter->stats.iac += rd32(E1000_IAC); 5297 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5298 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5299 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5300 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5301 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5302 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5303 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5304 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5305 5306 /* Fill out the OS statistics structure */ 5307 net_stats->multicast = adapter->stats.mprc; 5308 net_stats->collisions = adapter->stats.colc; 5309 5310 /* Rx Errors */ 5311 5312 /* RLEC on some newer hardware can be incorrect so build 5313 * our own version based on RUC and ROC 5314 */ 5315 net_stats->rx_errors = adapter->stats.rxerrc + 5316 adapter->stats.crcerrs + adapter->stats.algnerrc + 5317 adapter->stats.ruc + adapter->stats.roc + 5318 adapter->stats.cexterr; 5319 net_stats->rx_length_errors = adapter->stats.ruc + 5320 adapter->stats.roc; 5321 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5322 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5323 net_stats->rx_missed_errors = adapter->stats.mpc; 5324 5325 /* Tx Errors */ 5326 net_stats->tx_errors = adapter->stats.ecol + 5327 adapter->stats.latecol; 5328 net_stats->tx_aborted_errors = adapter->stats.ecol; 5329 net_stats->tx_window_errors = adapter->stats.latecol; 5330 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5331 5332 /* Tx Dropped needs to be maintained elsewhere */ 5333 5334 /* Phy Stats */ 5335 if (hw->phy.media_type == e1000_media_type_copper) { 5336 if ((adapter->link_speed == SPEED_1000) && 5337 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 5338 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; 5339 adapter->phy_stats.idle_errors += phy_tmp; 5340 } 5341 } 5342 5343 /* Management Stats */ 5344 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5345 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5346 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5347 5348 /* OS2BMC Stats */ 5349 reg = rd32(E1000_MANC); 5350 if (reg & E1000_MANC_EN_BMC2OS) { 5351 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5352 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5353 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5354 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5355 } 5356} 5357 5358static irqreturn_t igb_msix_other(int irq, void *data) 5359{ 5360 struct igb_adapter *adapter = data; 5361 struct e1000_hw *hw = &adapter->hw; 5362 u32 icr = rd32(E1000_ICR); 5363 /* reading ICR causes bit 31 of EICR to be cleared */ 5364 5365 if (icr & E1000_ICR_DRSTA) 5366 schedule_work(&adapter->reset_task); 5367 5368 if (icr & E1000_ICR_DOUTSYNC) { 5369 /* HW is reporting DMA is out of sync */ 5370 adapter->stats.doosync++; 5371 /* The DMA Out of Sync is also indication of a spoof event 5372 * in IOV mode. Check the Wrong VM Behavior register to 5373 * see if it is really a spoof event. 5374 */ 5375 igb_check_wvbr(adapter); 5376 } 5377 5378 /* Check for a mailbox event */ 5379 if (icr & E1000_ICR_VMMB) 5380 igb_msg_task(adapter); 5381 5382 if (icr & E1000_ICR_LSC) { 5383 hw->mac.get_link_status = 1; 5384 /* guard against interrupt when we're going down */ 5385 if (!test_bit(__IGB_DOWN, &adapter->state)) 5386 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5387 } 5388 5389 if (icr & E1000_ICR_TS) { 5390 u32 tsicr = rd32(E1000_TSICR); 5391 5392 if (tsicr & E1000_TSICR_TXTS) { 5393 /* acknowledge the interrupt */ 5394 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5395 /* retrieve hardware timestamp */ 5396 schedule_work(&adapter->ptp_tx_work); 5397 } 5398 } 5399 5400 wr32(E1000_EIMS, adapter->eims_other); 5401 5402 return IRQ_HANDLED; 5403} 5404 5405static void igb_write_itr(struct igb_q_vector *q_vector) 5406{ 5407 struct igb_adapter *adapter = q_vector->adapter; 5408 u32 itr_val = q_vector->itr_val & 0x7FFC; 5409 5410 if (!q_vector->set_itr) 5411 return; 5412 5413 if (!itr_val) 5414 itr_val = 0x4; 5415 5416 if (adapter->hw.mac.type == e1000_82575) 5417 itr_val |= itr_val << 16; 5418 else 5419 itr_val |= E1000_EITR_CNT_IGNR; 5420 5421 writel(itr_val, q_vector->itr_register); 5422 q_vector->set_itr = 0; 5423} 5424 5425static irqreturn_t igb_msix_ring(int irq, void *data) 5426{ 5427 struct igb_q_vector *q_vector = data; 5428 5429 /* Write the ITR value calculated from the previous interrupt. */ 5430 igb_write_itr(q_vector); 5431 5432 napi_schedule(&q_vector->napi); 5433 5434 return IRQ_HANDLED; 5435} 5436 5437#ifdef CONFIG_IGB_DCA 5438static void igb_update_tx_dca(struct igb_adapter *adapter, 5439 struct igb_ring *tx_ring, 5440 int cpu) 5441{ 5442 struct e1000_hw *hw = &adapter->hw; 5443 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5444 5445 if (hw->mac.type != e1000_82575) 5446 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5447 5448 /* We can enable relaxed ordering for reads, but not writes when 5449 * DCA is enabled. This is due to a known issue in some chipsets 5450 * which will cause the DCA tag to be cleared. 5451 */ 5452 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5453 E1000_DCA_TXCTRL_DATA_RRO_EN | 5454 E1000_DCA_TXCTRL_DESC_DCA_EN; 5455 5456 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5457} 5458 5459static void igb_update_rx_dca(struct igb_adapter *adapter, 5460 struct igb_ring *rx_ring, 5461 int cpu) 5462{ 5463 struct e1000_hw *hw = &adapter->hw; 5464 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5465 5466 if (hw->mac.type != e1000_82575) 5467 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5468 5469 /* We can enable relaxed ordering for reads, but not writes when 5470 * DCA is enabled. This is due to a known issue in some chipsets 5471 * which will cause the DCA tag to be cleared. 5472 */ 5473 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5474 E1000_DCA_RXCTRL_DESC_DCA_EN; 5475 5476 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5477} 5478 5479static void igb_update_dca(struct igb_q_vector *q_vector) 5480{ 5481 struct igb_adapter *adapter = q_vector->adapter; 5482 int cpu = get_cpu(); 5483 5484 if (q_vector->cpu == cpu) 5485 goto out_no_update; 5486 5487 if (q_vector->tx.ring) 5488 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5489 5490 if (q_vector->rx.ring) 5491 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5492 5493 q_vector->cpu = cpu; 5494out_no_update: 5495 put_cpu(); 5496} 5497 5498static void igb_setup_dca(struct igb_adapter *adapter) 5499{ 5500 struct e1000_hw *hw = &adapter->hw; 5501 int i; 5502 5503 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5504 return; 5505 5506 /* Always use CB2 mode, difference is masked in the CB driver. */ 5507 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5508 5509 for (i = 0; i < adapter->num_q_vectors; i++) { 5510 adapter->q_vector[i]->cpu = -1; 5511 igb_update_dca(adapter->q_vector[i]); 5512 } 5513} 5514 5515static int __igb_notify_dca(struct device *dev, void *data) 5516{ 5517 struct net_device *netdev = dev_get_drvdata(dev); 5518 struct igb_adapter *adapter = netdev_priv(netdev); 5519 struct pci_dev *pdev = adapter->pdev; 5520 struct e1000_hw *hw = &adapter->hw; 5521 unsigned long event = *(unsigned long *)data; 5522 5523 switch (event) { 5524 case DCA_PROVIDER_ADD: 5525 /* if already enabled, don't do it again */ 5526 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5527 break; 5528 if (dca_add_requester(dev) == 0) { 5529 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5530 dev_info(&pdev->dev, "DCA enabled\n"); 5531 igb_setup_dca(adapter); 5532 break; 5533 } 5534 /* Fall Through since DCA is disabled. */ 5535 case DCA_PROVIDER_REMOVE: 5536 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5537 /* without this a class_device is left 5538 * hanging around in the sysfs model 5539 */ 5540 dca_remove_requester(dev); 5541 dev_info(&pdev->dev, "DCA disabled\n"); 5542 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5543 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5544 } 5545 break; 5546 } 5547 5548 return 0; 5549} 5550 5551static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5552 void *p) 5553{ 5554 int ret_val; 5555 5556 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5557 __igb_notify_dca); 5558 5559 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5560} 5561#endif /* CONFIG_IGB_DCA */ 5562 5563#ifdef CONFIG_PCI_IOV 5564static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5565{ 5566 unsigned char mac_addr[ETH_ALEN]; 5567 5568 eth_zero_addr(mac_addr); 5569 igb_set_vf_mac(adapter, vf, mac_addr); 5570 5571 /* By default spoof check is enabled for all VFs */ 5572 adapter->vf_data[vf].spoofchk_enabled = true; 5573 5574 return 0; 5575} 5576 5577#endif 5578static void igb_ping_all_vfs(struct igb_adapter *adapter) 5579{ 5580 struct e1000_hw *hw = &adapter->hw; 5581 u32 ping; 5582 int i; 5583 5584 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5585 ping = E1000_PF_CONTROL_MSG; 5586 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5587 ping |= E1000_VT_MSGTYPE_CTS; 5588 igb_write_mbx(hw, &ping, 1, i); 5589 } 5590} 5591 5592static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5593{ 5594 struct e1000_hw *hw = &adapter->hw; 5595 u32 vmolr = rd32(E1000_VMOLR(vf)); 5596 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5597 5598 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5599 IGB_VF_FLAG_MULTI_PROMISC); 5600 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5601 5602 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5603 vmolr |= E1000_VMOLR_MPME; 5604 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5605 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5606 } else { 5607 /* if we have hashes and we are clearing a multicast promisc 5608 * flag we need to write the hashes to the MTA as this step 5609 * was previously skipped 5610 */ 5611 if (vf_data->num_vf_mc_hashes > 30) { 5612 vmolr |= E1000_VMOLR_MPME; 5613 } else if (vf_data->num_vf_mc_hashes) { 5614 int j; 5615 vmolr |= E1000_VMOLR_ROMPE; 5616 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5617 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5618 } 5619 } 5620 5621 wr32(E1000_VMOLR(vf), vmolr); 5622 5623 /* there are flags left unprocessed, likely not supported */ 5624 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5625 return -EINVAL; 5626 5627 return 0; 5628} 5629 5630static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5631 u32 *msgbuf, u32 vf) 5632{ 5633 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5634 u16 *hash_list = (u16 *)&msgbuf[1]; 5635 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5636 int i; 5637 5638 /* salt away the number of multicast addresses assigned 5639 * to this VF for later use to restore when the PF multi cast 5640 * list changes 5641 */ 5642 vf_data->num_vf_mc_hashes = n; 5643 5644 /* only up to 30 hash values supported */ 5645 if (n > 30) 5646 n = 30; 5647 5648 /* store the hashes for later use */ 5649 for (i = 0; i < n; i++) 5650 vf_data->vf_mc_hashes[i] = hash_list[i]; 5651 5652 /* Flush and reset the mta with the new values */ 5653 igb_set_rx_mode(adapter->netdev); 5654 5655 return 0; 5656} 5657 5658static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5659{ 5660 struct e1000_hw *hw = &adapter->hw; 5661 struct vf_data_storage *vf_data; 5662 int i, j; 5663 5664 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5665 u32 vmolr = rd32(E1000_VMOLR(i)); 5666 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5667 5668 vf_data = &adapter->vf_data[i]; 5669 5670 if ((vf_data->num_vf_mc_hashes > 30) || 5671 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5672 vmolr |= E1000_VMOLR_MPME; 5673 } else if (vf_data->num_vf_mc_hashes) { 5674 vmolr |= E1000_VMOLR_ROMPE; 5675 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5676 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5677 } 5678 wr32(E1000_VMOLR(i), vmolr); 5679 } 5680} 5681 5682static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5683{ 5684 struct e1000_hw *hw = &adapter->hw; 5685 u32 pool_mask, reg, vid; 5686 int i; 5687 5688 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5689 5690 /* Find the vlan filter for this id */ 5691 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5692 reg = rd32(E1000_VLVF(i)); 5693 5694 /* remove the vf from the pool */ 5695 reg &= ~pool_mask; 5696 5697 /* if pool is empty then remove entry from vfta */ 5698 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5699 (reg & E1000_VLVF_VLANID_ENABLE)) { 5700 reg = 0; 5701 vid = reg & E1000_VLVF_VLANID_MASK; 5702 igb_vfta_set(hw, vid, false); 5703 } 5704 5705 wr32(E1000_VLVF(i), reg); 5706 } 5707 5708 adapter->vf_data[vf].vlans_enabled = 0; 5709} 5710 5711static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5712{ 5713 struct e1000_hw *hw = &adapter->hw; 5714 u32 reg, i; 5715 5716 /* The vlvf table only exists on 82576 hardware and newer */ 5717 if (hw->mac.type < e1000_82576) 5718 return -1; 5719 5720 /* we only need to do this if VMDq is enabled */ 5721 if (!adapter->vfs_allocated_count) 5722 return -1; 5723 5724 /* Find the vlan filter for this id */ 5725 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5726 reg = rd32(E1000_VLVF(i)); 5727 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5728 vid == (reg & E1000_VLVF_VLANID_MASK)) 5729 break; 5730 } 5731 5732 if (add) { 5733 if (i == E1000_VLVF_ARRAY_SIZE) { 5734 /* Did not find a matching VLAN ID entry that was 5735 * enabled. Search for a free filter entry, i.e. 5736 * one without the enable bit set 5737 */ 5738 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5739 reg = rd32(E1000_VLVF(i)); 5740 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5741 break; 5742 } 5743 } 5744 if (i < E1000_VLVF_ARRAY_SIZE) { 5745 /* Found an enabled/available entry */ 5746 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5747 5748 /* if !enabled we need to set this up in vfta */ 5749 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5750 /* add VID to filter table */ 5751 igb_vfta_set(hw, vid, true); 5752 reg |= E1000_VLVF_VLANID_ENABLE; 5753 } 5754 reg &= ~E1000_VLVF_VLANID_MASK; 5755 reg |= vid; 5756 wr32(E1000_VLVF(i), reg); 5757 5758 /* do not modify RLPML for PF devices */ 5759 if (vf >= adapter->vfs_allocated_count) 5760 return 0; 5761 5762 if (!adapter->vf_data[vf].vlans_enabled) { 5763 u32 size; 5764 reg = rd32(E1000_VMOLR(vf)); 5765 size = reg & E1000_VMOLR_RLPML_MASK; 5766 size += 4; 5767 reg &= ~E1000_VMOLR_RLPML_MASK; 5768 reg |= size; 5769 wr32(E1000_VMOLR(vf), reg); 5770 } 5771 5772 adapter->vf_data[vf].vlans_enabled++; 5773 } 5774 } else { 5775 if (i < E1000_VLVF_ARRAY_SIZE) { 5776 /* remove vf from the pool */ 5777 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5778 /* if pool is empty then remove entry from vfta */ 5779 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5780 reg = 0; 5781 igb_vfta_set(hw, vid, false); 5782 } 5783 wr32(E1000_VLVF(i), reg); 5784 5785 /* do not modify RLPML for PF devices */ 5786 if (vf >= adapter->vfs_allocated_count) 5787 return 0; 5788 5789 adapter->vf_data[vf].vlans_enabled--; 5790 if (!adapter->vf_data[vf].vlans_enabled) { 5791 u32 size; 5792 reg = rd32(E1000_VMOLR(vf)); 5793 size = reg & E1000_VMOLR_RLPML_MASK; 5794 size -= 4; 5795 reg &= ~E1000_VMOLR_RLPML_MASK; 5796 reg |= size; 5797 wr32(E1000_VMOLR(vf), reg); 5798 } 5799 } 5800 } 5801 return 0; 5802} 5803 5804static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5805{ 5806 struct e1000_hw *hw = &adapter->hw; 5807 5808 if (vid) 5809 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5810 else 5811 wr32(E1000_VMVIR(vf), 0); 5812} 5813 5814static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5815 int vf, u16 vlan, u8 qos) 5816{ 5817 int err = 0; 5818 struct igb_adapter *adapter = netdev_priv(netdev); 5819 5820 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5821 return -EINVAL; 5822 if (vlan || qos) { 5823 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5824 if (err) 5825 goto out; 5826 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5827 igb_set_vmolr(adapter, vf, !vlan); 5828 adapter->vf_data[vf].pf_vlan = vlan; 5829 adapter->vf_data[vf].pf_qos = qos; 5830 dev_info(&adapter->pdev->dev, 5831 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5832 if (test_bit(__IGB_DOWN, &adapter->state)) { 5833 dev_warn(&adapter->pdev->dev, 5834 "The VF VLAN has been set, but the PF device is not up.\n"); 5835 dev_warn(&adapter->pdev->dev, 5836 "Bring the PF device up before attempting to use the VF device.\n"); 5837 } 5838 } else { 5839 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5840 false, vf); 5841 igb_set_vmvir(adapter, vlan, vf); 5842 igb_set_vmolr(adapter, vf, true); 5843 adapter->vf_data[vf].pf_vlan = 0; 5844 adapter->vf_data[vf].pf_qos = 0; 5845 } 5846out: 5847 return err; 5848} 5849 5850static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid) 5851{ 5852 struct e1000_hw *hw = &adapter->hw; 5853 int i; 5854 u32 reg; 5855 5856 /* Find the vlan filter for this id */ 5857 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5858 reg = rd32(E1000_VLVF(i)); 5859 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5860 vid == (reg & E1000_VLVF_VLANID_MASK)) 5861 break; 5862 } 5863 5864 if (i >= E1000_VLVF_ARRAY_SIZE) 5865 i = -1; 5866 5867 return i; 5868} 5869 5870static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5871{ 5872 struct e1000_hw *hw = &adapter->hw; 5873 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5874 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5875 int err = 0; 5876 5877 /* If in promiscuous mode we need to make sure the PF also has 5878 * the VLAN filter set. 5879 */ 5880 if (add && (adapter->netdev->flags & IFF_PROMISC)) 5881 err = igb_vlvf_set(adapter, vid, add, 5882 adapter->vfs_allocated_count); 5883 if (err) 5884 goto out; 5885 5886 err = igb_vlvf_set(adapter, vid, add, vf); 5887 5888 if (err) 5889 goto out; 5890 5891 /* Go through all the checks to see if the VLAN filter should 5892 * be wiped completely. 5893 */ 5894 if (!add && (adapter->netdev->flags & IFF_PROMISC)) { 5895 u32 vlvf, bits; 5896 5897 int regndx = igb_find_vlvf_entry(adapter, vid); 5898 if (regndx < 0) 5899 goto out; 5900 /* See if any other pools are set for this VLAN filter 5901 * entry other than the PF. 5902 */ 5903 vlvf = bits = rd32(E1000_VLVF(regndx)); 5904 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT + 5905 adapter->vfs_allocated_count); 5906 /* If the filter was removed then ensure PF pool bit 5907 * is cleared if the PF only added itself to the pool 5908 * because the PF is in promiscuous mode. 5909 */ 5910 if ((vlvf & VLAN_VID_MASK) == vid && 5911 !test_bit(vid, adapter->active_vlans) && 5912 !bits) 5913 igb_vlvf_set(adapter, vid, add, 5914 adapter->vfs_allocated_count); 5915 } 5916 5917out: 5918 return err; 5919} 5920 5921static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 5922{ 5923 /* clear flags - except flag that indicates PF has set the MAC */ 5924 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 5925 adapter->vf_data[vf].last_nack = jiffies; 5926 5927 /* reset offloads to defaults */ 5928 igb_set_vmolr(adapter, vf, true); 5929 5930 /* reset vlans for device */ 5931 igb_clear_vf_vfta(adapter, vf); 5932 if (adapter->vf_data[vf].pf_vlan) 5933 igb_ndo_set_vf_vlan(adapter->netdev, vf, 5934 adapter->vf_data[vf].pf_vlan, 5935 adapter->vf_data[vf].pf_qos); 5936 else 5937 igb_clear_vf_vfta(adapter, vf); 5938 5939 /* reset multicast table array for vf */ 5940 adapter->vf_data[vf].num_vf_mc_hashes = 0; 5941 5942 /* Flush and reset the mta with the new values */ 5943 igb_set_rx_mode(adapter->netdev); 5944} 5945 5946static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 5947{ 5948 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5949 5950 /* clear mac address as we were hotplug removed/added */ 5951 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 5952 eth_zero_addr(vf_mac); 5953 5954 /* process remaining reset events */ 5955 igb_vf_reset(adapter, vf); 5956} 5957 5958static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 5959{ 5960 struct e1000_hw *hw = &adapter->hw; 5961 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5962 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 5963 u32 reg, msgbuf[3]; 5964 u8 *addr = (u8 *)(&msgbuf[1]); 5965 5966 /* process all the same items cleared in a function level reset */ 5967 igb_vf_reset(adapter, vf); 5968 5969 /* set vf mac address */ 5970 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 5971 5972 /* enable transmit and receive for vf */ 5973 reg = rd32(E1000_VFTE); 5974 wr32(E1000_VFTE, reg | (1 << vf)); 5975 reg = rd32(E1000_VFRE); 5976 wr32(E1000_VFRE, reg | (1 << vf)); 5977 5978 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 5979 5980 /* reply to reset with ack and vf mac address */ 5981 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 5982 memcpy(addr, vf_mac, ETH_ALEN); 5983 igb_write_mbx(hw, msgbuf, 3, vf); 5984} 5985 5986static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 5987{ 5988 /* The VF MAC Address is stored in a packed array of bytes 5989 * starting at the second 32 bit word of the msg array 5990 */ 5991 unsigned char *addr = (char *)&msg[1]; 5992 int err = -1; 5993 5994 if (is_valid_ether_addr(addr)) 5995 err = igb_set_vf_mac(adapter, vf, addr); 5996 5997 return err; 5998} 5999 6000static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 6001{ 6002 struct e1000_hw *hw = &adapter->hw; 6003 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6004 u32 msg = E1000_VT_MSGTYPE_NACK; 6005 6006 /* if device isn't clear to send it shouldn't be reading either */ 6007 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6008 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6009 igb_write_mbx(hw, &msg, 1, vf); 6010 vf_data->last_nack = jiffies; 6011 } 6012} 6013 6014static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6015{ 6016 struct pci_dev *pdev = adapter->pdev; 6017 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6018 struct e1000_hw *hw = &adapter->hw; 6019 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6020 s32 retval; 6021 6022 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6023 6024 if (retval) { 6025 /* if receive failed revoke VF CTS stats and restart init */ 6026 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6027 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6028 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6029 return; 6030 goto out; 6031 } 6032 6033 /* this is a message we already processed, do nothing */ 6034 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6035 return; 6036 6037 /* until the vf completes a reset it should not be 6038 * allowed to start any configuration. 6039 */ 6040 if (msgbuf[0] == E1000_VF_RESET) { 6041 igb_vf_reset_msg(adapter, vf); 6042 return; 6043 } 6044 6045 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6046 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6047 return; 6048 retval = -1; 6049 goto out; 6050 } 6051 6052 switch ((msgbuf[0] & 0xFFFF)) { 6053 case E1000_VF_SET_MAC_ADDR: 6054 retval = -EINVAL; 6055 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 6056 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6057 else 6058 dev_warn(&pdev->dev, 6059 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6060 vf); 6061 break; 6062 case E1000_VF_SET_PROMISC: 6063 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6064 break; 6065 case E1000_VF_SET_MULTICAST: 6066 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6067 break; 6068 case E1000_VF_SET_LPE: 6069 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6070 break; 6071 case E1000_VF_SET_VLAN: 6072 retval = -1; 6073 if (vf_data->pf_vlan) 6074 dev_warn(&pdev->dev, 6075 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6076 vf); 6077 else 6078 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 6079 break; 6080 default: 6081 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6082 retval = -1; 6083 break; 6084 } 6085 6086 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6087out: 6088 /* notify the VF of the results of what it sent us */ 6089 if (retval) 6090 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6091 else 6092 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6093 6094 igb_write_mbx(hw, msgbuf, 1, vf); 6095} 6096 6097static void igb_msg_task(struct igb_adapter *adapter) 6098{ 6099 struct e1000_hw *hw = &adapter->hw; 6100 u32 vf; 6101 6102 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6103 /* process any reset requests */ 6104 if (!igb_check_for_rst(hw, vf)) 6105 igb_vf_reset_event(adapter, vf); 6106 6107 /* process any messages pending */ 6108 if (!igb_check_for_msg(hw, vf)) 6109 igb_rcv_msg_from_vf(adapter, vf); 6110 6111 /* process any acks */ 6112 if (!igb_check_for_ack(hw, vf)) 6113 igb_rcv_ack_from_vf(adapter, vf); 6114 } 6115} 6116 6117/** 6118 * igb_set_uta - Set unicast filter table address 6119 * @adapter: board private structure 6120 * 6121 * The unicast table address is a register array of 32-bit registers. 6122 * The table is meant to be used in a way similar to how the MTA is used 6123 * however due to certain limitations in the hardware it is necessary to 6124 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6125 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6126 **/ 6127static void igb_set_uta(struct igb_adapter *adapter) 6128{ 6129 struct e1000_hw *hw = &adapter->hw; 6130 int i; 6131 6132 /* The UTA table only exists on 82576 hardware and newer */ 6133 if (hw->mac.type < e1000_82576) 6134 return; 6135 6136 /* we only need to do this if VMDq is enabled */ 6137 if (!adapter->vfs_allocated_count) 6138 return; 6139 6140 for (i = 0; i < hw->mac.uta_reg_count; i++) 6141 array_wr32(E1000_UTA, i, ~0); 6142} 6143 6144/** 6145 * igb_intr_msi - Interrupt Handler 6146 * @irq: interrupt number 6147 * @data: pointer to a network interface device structure 6148 **/ 6149static irqreturn_t igb_intr_msi(int irq, void *data) 6150{ 6151 struct igb_adapter *adapter = data; 6152 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6153 struct e1000_hw *hw = &adapter->hw; 6154 /* read ICR disables interrupts using IAM */ 6155 u32 icr = rd32(E1000_ICR); 6156 6157 igb_write_itr(q_vector); 6158 6159 if (icr & E1000_ICR_DRSTA) 6160 schedule_work(&adapter->reset_task); 6161 6162 if (icr & E1000_ICR_DOUTSYNC) { 6163 /* HW is reporting DMA is out of sync */ 6164 adapter->stats.doosync++; 6165 } 6166 6167 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6168 hw->mac.get_link_status = 1; 6169 if (!test_bit(__IGB_DOWN, &adapter->state)) 6170 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6171 } 6172 6173 if (icr & E1000_ICR_TS) { 6174 u32 tsicr = rd32(E1000_TSICR); 6175 6176 if (tsicr & E1000_TSICR_TXTS) { 6177 /* acknowledge the interrupt */ 6178 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6179 /* retrieve hardware timestamp */ 6180 schedule_work(&adapter->ptp_tx_work); 6181 } 6182 } 6183 6184 napi_schedule(&q_vector->napi); 6185 6186 return IRQ_HANDLED; 6187} 6188 6189/** 6190 * igb_intr - Legacy Interrupt Handler 6191 * @irq: interrupt number 6192 * @data: pointer to a network interface device structure 6193 **/ 6194static irqreturn_t igb_intr(int irq, void *data) 6195{ 6196 struct igb_adapter *adapter = data; 6197 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6198 struct e1000_hw *hw = &adapter->hw; 6199 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6200 * need for the IMC write 6201 */ 6202 u32 icr = rd32(E1000_ICR); 6203 6204 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6205 * not set, then the adapter didn't send an interrupt 6206 */ 6207 if (!(icr & E1000_ICR_INT_ASSERTED)) 6208 return IRQ_NONE; 6209 6210 igb_write_itr(q_vector); 6211 6212 if (icr & E1000_ICR_DRSTA) 6213 schedule_work(&adapter->reset_task); 6214 6215 if (icr & E1000_ICR_DOUTSYNC) { 6216 /* HW is reporting DMA is out of sync */ 6217 adapter->stats.doosync++; 6218 } 6219 6220 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6221 hw->mac.get_link_status = 1; 6222 /* guard against interrupt when we're going down */ 6223 if (!test_bit(__IGB_DOWN, &adapter->state)) 6224 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6225 } 6226 6227 if (icr & E1000_ICR_TS) { 6228 u32 tsicr = rd32(E1000_TSICR); 6229 6230 if (tsicr & E1000_TSICR_TXTS) { 6231 /* acknowledge the interrupt */ 6232 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6233 /* retrieve hardware timestamp */ 6234 schedule_work(&adapter->ptp_tx_work); 6235 } 6236 } 6237 6238 napi_schedule(&q_vector->napi); 6239 6240 return IRQ_HANDLED; 6241} 6242 6243static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6244{ 6245 struct igb_adapter *adapter = q_vector->adapter; 6246 struct e1000_hw *hw = &adapter->hw; 6247 6248 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6249 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6250 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6251 igb_set_itr(q_vector); 6252 else 6253 igb_update_ring_itr(q_vector); 6254 } 6255 6256 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6257 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6258 wr32(E1000_EIMS, q_vector->eims_value); 6259 else 6260 igb_irq_enable(adapter); 6261 } 6262} 6263 6264/** 6265 * igb_poll - NAPI Rx polling callback 6266 * @napi: napi polling structure 6267 * @budget: count of how many packets we should handle 6268 **/ 6269static int igb_poll(struct napi_struct *napi, int budget) 6270{ 6271 struct igb_q_vector *q_vector = container_of(napi, 6272 struct igb_q_vector, 6273 napi); 6274 bool clean_complete = true; 6275 6276#ifdef CONFIG_IGB_DCA 6277 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6278 igb_update_dca(q_vector); 6279#endif 6280 if (q_vector->tx.ring) 6281 clean_complete = igb_clean_tx_irq(q_vector); 6282 6283 if (q_vector->rx.ring) 6284 clean_complete &= igb_clean_rx_irq(q_vector, budget); 6285 6286 /* If all work not completed, return budget and keep polling */ 6287 if (!clean_complete) 6288 return budget; 6289 6290 /* If not enough Rx work done, exit the polling mode */ 6291 napi_complete(napi); 6292 igb_ring_irq_enable(q_vector); 6293 6294 return 0; 6295} 6296 6297/** 6298 * igb_clean_tx_irq - Reclaim resources after transmit completes 6299 * @q_vector: pointer to q_vector containing needed info 6300 * 6301 * returns true if ring is completely cleaned 6302 **/ 6303static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 6304{ 6305 struct igb_adapter *adapter = q_vector->adapter; 6306 struct igb_ring *tx_ring = q_vector->tx.ring; 6307 struct igb_tx_buffer *tx_buffer; 6308 union e1000_adv_tx_desc *tx_desc; 6309 unsigned int total_bytes = 0, total_packets = 0; 6310 unsigned int budget = q_vector->tx.work_limit; 6311 unsigned int i = tx_ring->next_to_clean; 6312 6313 if (test_bit(__IGB_DOWN, &adapter->state)) 6314 return true; 6315 6316 tx_buffer = &tx_ring->tx_buffer_info[i]; 6317 tx_desc = IGB_TX_DESC(tx_ring, i); 6318 i -= tx_ring->count; 6319 6320 do { 6321 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6322 6323 /* if next_to_watch is not set then there is no work pending */ 6324 if (!eop_desc) 6325 break; 6326 6327 /* prevent any other reads prior to eop_desc */ 6328 read_barrier_depends(); 6329 6330 /* if DD is not set pending work has not been completed */ 6331 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6332 break; 6333 6334 /* clear next_to_watch to prevent false hangs */ 6335 tx_buffer->next_to_watch = NULL; 6336 6337 /* update the statistics for this packet */ 6338 total_bytes += tx_buffer->bytecount; 6339 total_packets += tx_buffer->gso_segs; 6340 6341 /* free the skb */ 6342 dev_kfree_skb_any(tx_buffer->skb); 6343 6344 /* unmap skb header data */ 6345 dma_unmap_single(tx_ring->dev, 6346 dma_unmap_addr(tx_buffer, dma), 6347 dma_unmap_len(tx_buffer, len), 6348 DMA_TO_DEVICE); 6349 6350 /* clear tx_buffer data */ 6351 tx_buffer->skb = NULL; 6352 dma_unmap_len_set(tx_buffer, len, 0); 6353 6354 /* clear last DMA location and unmap remaining buffers */ 6355 while (tx_desc != eop_desc) { 6356 tx_buffer++; 6357 tx_desc++; 6358 i++; 6359 if (unlikely(!i)) { 6360 i -= tx_ring->count; 6361 tx_buffer = tx_ring->tx_buffer_info; 6362 tx_desc = IGB_TX_DESC(tx_ring, 0); 6363 } 6364 6365 /* unmap any remaining paged data */ 6366 if (dma_unmap_len(tx_buffer, len)) { 6367 dma_unmap_page(tx_ring->dev, 6368 dma_unmap_addr(tx_buffer, dma), 6369 dma_unmap_len(tx_buffer, len), 6370 DMA_TO_DEVICE); 6371 dma_unmap_len_set(tx_buffer, len, 0); 6372 } 6373 } 6374 6375 /* move us one more past the eop_desc for start of next pkt */ 6376 tx_buffer++; 6377 tx_desc++; 6378 i++; 6379 if (unlikely(!i)) { 6380 i -= tx_ring->count; 6381 tx_buffer = tx_ring->tx_buffer_info; 6382 tx_desc = IGB_TX_DESC(tx_ring, 0); 6383 } 6384 6385 /* issue prefetch for next Tx descriptor */ 6386 prefetch(tx_desc); 6387 6388 /* update budget accounting */ 6389 budget--; 6390 } while (likely(budget)); 6391 6392 netdev_tx_completed_queue(txring_txq(tx_ring), 6393 total_packets, total_bytes); 6394 i += tx_ring->count; 6395 tx_ring->next_to_clean = i; 6396 u64_stats_update_begin(&tx_ring->tx_syncp); 6397 tx_ring->tx_stats.bytes += total_bytes; 6398 tx_ring->tx_stats.packets += total_packets; 6399 u64_stats_update_end(&tx_ring->tx_syncp); 6400 q_vector->tx.total_bytes += total_bytes; 6401 q_vector->tx.total_packets += total_packets; 6402 6403 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6404 struct e1000_hw *hw = &adapter->hw; 6405 6406 /* Detect a transmit hang in hardware, this serializes the 6407 * check with the clearing of time_stamp and movement of i 6408 */ 6409 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6410 if (tx_buffer->next_to_watch && 6411 time_after(jiffies, tx_buffer->time_stamp + 6412 (adapter->tx_timeout_factor * HZ)) && 6413 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6414 6415 /* detected Tx unit hang */ 6416 dev_err(tx_ring->dev, 6417 "Detected Tx Unit Hang\n" 6418 " Tx Queue <%d>\n" 6419 " TDH <%x>\n" 6420 " TDT <%x>\n" 6421 " next_to_use <%x>\n" 6422 " next_to_clean <%x>\n" 6423 "buffer_info[next_to_clean]\n" 6424 " time_stamp <%lx>\n" 6425 " next_to_watch <%p>\n" 6426 " jiffies <%lx>\n" 6427 " desc.status <%x>\n", 6428 tx_ring->queue_index, 6429 rd32(E1000_TDH(tx_ring->reg_idx)), 6430 readl(tx_ring->tail), 6431 tx_ring->next_to_use, 6432 tx_ring->next_to_clean, 6433 tx_buffer->time_stamp, 6434 tx_buffer->next_to_watch, 6435 jiffies, 6436 tx_buffer->next_to_watch->wb.status); 6437 netif_stop_subqueue(tx_ring->netdev, 6438 tx_ring->queue_index); 6439 6440 /* we are about to reset, no point in enabling stuff */ 6441 return true; 6442 } 6443 } 6444 6445#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6446 if (unlikely(total_packets && 6447 netif_carrier_ok(tx_ring->netdev) && 6448 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6449 /* Make sure that anybody stopping the queue after this 6450 * sees the new next_to_clean. 6451 */ 6452 smp_mb(); 6453 if (__netif_subqueue_stopped(tx_ring->netdev, 6454 tx_ring->queue_index) && 6455 !(test_bit(__IGB_DOWN, &adapter->state))) { 6456 netif_wake_subqueue(tx_ring->netdev, 6457 tx_ring->queue_index); 6458 6459 u64_stats_update_begin(&tx_ring->tx_syncp); 6460 tx_ring->tx_stats.restart_queue++; 6461 u64_stats_update_end(&tx_ring->tx_syncp); 6462 } 6463 } 6464 6465 return !!budget; 6466} 6467 6468/** 6469 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6470 * @rx_ring: rx descriptor ring to store buffers on 6471 * @old_buff: donor buffer to have page reused 6472 * 6473 * Synchronizes page for reuse by the adapter 6474 **/ 6475static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6476 struct igb_rx_buffer *old_buff) 6477{ 6478 struct igb_rx_buffer *new_buff; 6479 u16 nta = rx_ring->next_to_alloc; 6480 6481 new_buff = &rx_ring->rx_buffer_info[nta]; 6482 6483 /* update, and store next to alloc */ 6484 nta++; 6485 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6486 6487 /* transfer page from old buffer to new buffer */ 6488 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); 6489 6490 /* sync the buffer for use by the device */ 6491 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 6492 old_buff->page_offset, 6493 IGB_RX_BUFSZ, 6494 DMA_FROM_DEVICE); 6495} 6496 6497static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 6498 struct page *page, 6499 unsigned int truesize) 6500{ 6501 /* avoid re-using remote pages */ 6502 if (unlikely(page_to_nid(page) != numa_node_id())) 6503 return false; 6504 6505#if (PAGE_SIZE < 8192) 6506 /* if we are only owner of page we can reuse it */ 6507 if (unlikely(page_count(page) != 1)) 6508 return false; 6509 6510 /* flip page offset to other buffer */ 6511 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 6512 6513 /* since we are the only owner of the page and we need to 6514 * increment it, just set the value to 2 in order to avoid 6515 * an unnecessary locked operation 6516 */ 6517 atomic_set(&page->_count, 2); 6518#else 6519 /* move offset up to the next cache line */ 6520 rx_buffer->page_offset += truesize; 6521 6522 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 6523 return false; 6524 6525 /* bump ref count on page before it is given to the stack */ 6526 get_page(page); 6527#endif 6528 6529 return true; 6530} 6531 6532/** 6533 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6534 * @rx_ring: rx descriptor ring to transact packets on 6535 * @rx_buffer: buffer containing page to add 6536 * @rx_desc: descriptor containing length of buffer written by hardware 6537 * @skb: sk_buff to place the data into 6538 * 6539 * This function will add the data contained in rx_buffer->page to the skb. 6540 * This is done either through a direct copy if the data in the buffer is 6541 * less than the skb header size, otherwise it will just attach the page as 6542 * a frag to the skb. 6543 * 6544 * The function will then update the page offset if necessary and return 6545 * true if the buffer can be reused by the adapter. 6546 **/ 6547static bool igb_add_rx_frag(struct igb_ring *rx_ring, 6548 struct igb_rx_buffer *rx_buffer, 6549 union e1000_adv_rx_desc *rx_desc, 6550 struct sk_buff *skb) 6551{ 6552 struct page *page = rx_buffer->page; 6553 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 6554#if (PAGE_SIZE < 8192) 6555 unsigned int truesize = IGB_RX_BUFSZ; 6556#else 6557 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 6558#endif 6559 6560 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { 6561 unsigned char *va = page_address(page) + rx_buffer->page_offset; 6562 6563 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6564 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6565 va += IGB_TS_HDR_LEN; 6566 size -= IGB_TS_HDR_LEN; 6567 } 6568 6569 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 6570 6571 /* we can reuse buffer as-is, just make sure it is local */ 6572 if (likely(page_to_nid(page) == numa_node_id())) 6573 return true; 6574 6575 /* this page cannot be reused so discard it */ 6576 put_page(page); 6577 return false; 6578 } 6579 6580 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 6581 rx_buffer->page_offset, size, truesize); 6582 6583 return igb_can_reuse_rx_page(rx_buffer, page, truesize); 6584} 6585 6586static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 6587 union e1000_adv_rx_desc *rx_desc, 6588 struct sk_buff *skb) 6589{ 6590 struct igb_rx_buffer *rx_buffer; 6591 struct page *page; 6592 6593 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 6594 6595 page = rx_buffer->page; 6596 prefetchw(page); 6597 6598 if (likely(!skb)) { 6599 void *page_addr = page_address(page) + 6600 rx_buffer->page_offset; 6601 6602 /* prefetch first cache line of first page */ 6603 prefetch(page_addr); 6604#if L1_CACHE_BYTES < 128 6605 prefetch(page_addr + L1_CACHE_BYTES); 6606#endif 6607 6608 /* allocate a skb to store the frags */ 6609 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 6610 IGB_RX_HDR_LEN); 6611 if (unlikely(!skb)) { 6612 rx_ring->rx_stats.alloc_failed++; 6613 return NULL; 6614 } 6615 6616 /* we will be copying header into skb->data in 6617 * pskb_may_pull so it is in our interest to prefetch 6618 * it now to avoid a possible cache miss 6619 */ 6620 prefetchw(skb->data); 6621 } 6622 6623 /* we are reusing so sync this buffer for CPU use */ 6624 dma_sync_single_range_for_cpu(rx_ring->dev, 6625 rx_buffer->dma, 6626 rx_buffer->page_offset, 6627 IGB_RX_BUFSZ, 6628 DMA_FROM_DEVICE); 6629 6630 /* pull page into skb */ 6631 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 6632 /* hand second half of page back to the ring */ 6633 igb_reuse_rx_page(rx_ring, rx_buffer); 6634 } else { 6635 /* we are not reusing the buffer so unmap it */ 6636 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6637 PAGE_SIZE, DMA_FROM_DEVICE); 6638 } 6639 6640 /* clear contents of rx_buffer */ 6641 rx_buffer->page = NULL; 6642 6643 return skb; 6644} 6645 6646static inline void igb_rx_checksum(struct igb_ring *ring, 6647 union e1000_adv_rx_desc *rx_desc, 6648 struct sk_buff *skb) 6649{ 6650 skb_checksum_none_assert(skb); 6651 6652 /* Ignore Checksum bit is set */ 6653 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6654 return; 6655 6656 /* Rx checksum disabled via ethtool */ 6657 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6658 return; 6659 6660 /* TCP/UDP checksum error bit is set */ 6661 if (igb_test_staterr(rx_desc, 6662 E1000_RXDEXT_STATERR_TCPE | 6663 E1000_RXDEXT_STATERR_IPE)) { 6664 /* work around errata with sctp packets where the TCPE aka 6665 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6666 * packets, (aka let the stack check the crc32c) 6667 */ 6668 if (!((skb->len == 60) && 6669 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6670 u64_stats_update_begin(&ring->rx_syncp); 6671 ring->rx_stats.csum_err++; 6672 u64_stats_update_end(&ring->rx_syncp); 6673 } 6674 /* let the stack verify checksum errors */ 6675 return; 6676 } 6677 /* It must be a TCP or UDP packet with a valid checksum */ 6678 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 6679 E1000_RXD_STAT_UDPCS)) 6680 skb->ip_summed = CHECKSUM_UNNECESSARY; 6681 6682 dev_dbg(ring->dev, "cksum success: bits %08X\n", 6683 le32_to_cpu(rx_desc->wb.upper.status_error)); 6684} 6685 6686static inline void igb_rx_hash(struct igb_ring *ring, 6687 union e1000_adv_rx_desc *rx_desc, 6688 struct sk_buff *skb) 6689{ 6690 if (ring->netdev->features & NETIF_F_RXHASH) 6691 skb_set_hash(skb, 6692 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 6693 PKT_HASH_TYPE_L3); 6694} 6695 6696/** 6697 * igb_is_non_eop - process handling of non-EOP buffers 6698 * @rx_ring: Rx ring being processed 6699 * @rx_desc: Rx descriptor for current buffer 6700 * @skb: current socket buffer containing buffer in progress 6701 * 6702 * This function updates next to clean. If the buffer is an EOP buffer 6703 * this function exits returning false, otherwise it will place the 6704 * sk_buff in the next buffer to be chained and return true indicating 6705 * that this is in fact a non-EOP buffer. 6706 **/ 6707static bool igb_is_non_eop(struct igb_ring *rx_ring, 6708 union e1000_adv_rx_desc *rx_desc) 6709{ 6710 u32 ntc = rx_ring->next_to_clean + 1; 6711 6712 /* fetch, update, and store next to clean */ 6713 ntc = (ntc < rx_ring->count) ? ntc : 0; 6714 rx_ring->next_to_clean = ntc; 6715 6716 prefetch(IGB_RX_DESC(rx_ring, ntc)); 6717 6718 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 6719 return false; 6720 6721 return true; 6722} 6723 6724/** 6725 * igb_get_headlen - determine size of header for LRO/GRO 6726 * @data: pointer to the start of the headers 6727 * @max_len: total length of section to find headers in 6728 * 6729 * This function is meant to determine the length of headers that will 6730 * be recognized by hardware for LRO, and GRO offloads. The main 6731 * motivation of doing this is to only perform one pull for IPv4 TCP 6732 * packets so that we can do basic things like calculating the gso_size 6733 * based on the average data per packet. 6734 **/ 6735static unsigned int igb_get_headlen(unsigned char *data, 6736 unsigned int max_len) 6737{ 6738 union { 6739 unsigned char *network; 6740 /* l2 headers */ 6741 struct ethhdr *eth; 6742 struct vlan_hdr *vlan; 6743 /* l3 headers */ 6744 struct iphdr *ipv4; 6745 struct ipv6hdr *ipv6; 6746 } hdr; 6747 __be16 protocol; 6748 u8 nexthdr = 0; /* default to not TCP */ 6749 u8 hlen; 6750 6751 /* this should never happen, but better safe than sorry */ 6752 if (max_len < ETH_HLEN) 6753 return max_len; 6754 6755 /* initialize network frame pointer */ 6756 hdr.network = data; 6757 6758 /* set first protocol and move network header forward */ 6759 protocol = hdr.eth->h_proto; 6760 hdr.network += ETH_HLEN; 6761 6762 /* handle any vlan tag if present */ 6763 if (protocol == htons(ETH_P_8021Q)) { 6764 if ((hdr.network - data) > (max_len - VLAN_HLEN)) 6765 return max_len; 6766 6767 protocol = hdr.vlan->h_vlan_encapsulated_proto; 6768 hdr.network += VLAN_HLEN; 6769 } 6770 6771 /* handle L3 protocols */ 6772 if (protocol == htons(ETH_P_IP)) { 6773 if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) 6774 return max_len; 6775 6776 /* access ihl as a u8 to avoid unaligned access on ia64 */ 6777 hlen = (hdr.network[0] & 0x0F) << 2; 6778 6779 /* verify hlen meets minimum size requirements */ 6780 if (hlen < sizeof(struct iphdr)) 6781 return hdr.network - data; 6782 6783 /* record next protocol if header is present */ 6784 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET))) 6785 nexthdr = hdr.ipv4->protocol; 6786 } else if (protocol == htons(ETH_P_IPV6)) { 6787 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) 6788 return max_len; 6789 6790 /* record next protocol */ 6791 nexthdr = hdr.ipv6->nexthdr; 6792 hlen = sizeof(struct ipv6hdr); 6793 } else { 6794 return hdr.network - data; 6795 } 6796 6797 /* relocate pointer to start of L4 header */ 6798 hdr.network += hlen; 6799 6800 /* finally sort out TCP */ 6801 if (nexthdr == IPPROTO_TCP) { 6802 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) 6803 return max_len; 6804 6805 /* access doff as a u8 to avoid unaligned access on ia64 */ 6806 hlen = (hdr.network[12] & 0xF0) >> 2; 6807 6808 /* verify hlen meets minimum size requirements */ 6809 if (hlen < sizeof(struct tcphdr)) 6810 return hdr.network - data; 6811 6812 hdr.network += hlen; 6813 } else if (nexthdr == IPPROTO_UDP) { 6814 if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) 6815 return max_len; 6816 6817 hdr.network += sizeof(struct udphdr); 6818 } 6819 6820 /* If everything has gone correctly hdr.network should be the 6821 * data section of the packet and will be the end of the header. 6822 * If not then it probably represents the end of the last recognized 6823 * header. 6824 */ 6825 if ((hdr.network - data) < max_len) 6826 return hdr.network - data; 6827 else 6828 return max_len; 6829} 6830 6831/** 6832 * igb_pull_tail - igb specific version of skb_pull_tail 6833 * @rx_ring: rx descriptor ring packet is being transacted on 6834 * @rx_desc: pointer to the EOP Rx descriptor 6835 * @skb: pointer to current skb being adjusted 6836 * 6837 * This function is an igb specific version of __pskb_pull_tail. The 6838 * main difference between this version and the original function is that 6839 * this function can make several assumptions about the state of things 6840 * that allow for significant optimizations versus the standard function. 6841 * As a result we can do things like drop a frag and maintain an accurate 6842 * truesize for the skb. 6843 */ 6844static void igb_pull_tail(struct igb_ring *rx_ring, 6845 union e1000_adv_rx_desc *rx_desc, 6846 struct sk_buff *skb) 6847{ 6848 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6849 unsigned char *va; 6850 unsigned int pull_len; 6851 6852 /* it is valid to use page_address instead of kmap since we are 6853 * working with pages allocated out of the lomem pool per 6854 * alloc_page(GFP_ATOMIC) 6855 */ 6856 va = skb_frag_address(frag); 6857 6858 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6859 /* retrieve timestamp from buffer */ 6860 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6861 6862 /* update pointers to remove timestamp header */ 6863 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); 6864 frag->page_offset += IGB_TS_HDR_LEN; 6865 skb->data_len -= IGB_TS_HDR_LEN; 6866 skb->len -= IGB_TS_HDR_LEN; 6867 6868 /* move va to start of packet data */ 6869 va += IGB_TS_HDR_LEN; 6870 } 6871 6872 /* we need the header to contain the greater of either ETH_HLEN or 6873 * 60 bytes if the skb->len is less than 60 for skb_pad. 6874 */ 6875 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); 6876 6877 /* align pull length to size of long to optimize memcpy performance */ 6878 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 6879 6880 /* update all of the pointers */ 6881 skb_frag_size_sub(frag, pull_len); 6882 frag->page_offset += pull_len; 6883 skb->data_len -= pull_len; 6884 skb->tail += pull_len; 6885} 6886 6887/** 6888 * igb_cleanup_headers - Correct corrupted or empty headers 6889 * @rx_ring: rx descriptor ring packet is being transacted on 6890 * @rx_desc: pointer to the EOP Rx descriptor 6891 * @skb: pointer to current skb being fixed 6892 * 6893 * Address the case where we are pulling data in on pages only 6894 * and as such no data is present in the skb header. 6895 * 6896 * In addition if skb is not at least 60 bytes we need to pad it so that 6897 * it is large enough to qualify as a valid Ethernet frame. 6898 * 6899 * Returns true if an error was encountered and skb was freed. 6900 **/ 6901static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6902 union e1000_adv_rx_desc *rx_desc, 6903 struct sk_buff *skb) 6904{ 6905 if (unlikely((igb_test_staterr(rx_desc, 6906 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6907 struct net_device *netdev = rx_ring->netdev; 6908 if (!(netdev->features & NETIF_F_RXALL)) { 6909 dev_kfree_skb_any(skb); 6910 return true; 6911 } 6912 } 6913 6914 /* place header in linear portion of buffer */ 6915 if (skb_is_nonlinear(skb)) 6916 igb_pull_tail(rx_ring, rx_desc, skb); 6917 6918 /* if skb_pad returns an error the skb was freed */ 6919 if (unlikely(skb->len < 60)) { 6920 int pad_len = 60 - skb->len; 6921 6922 if (skb_pad(skb, pad_len)) 6923 return true; 6924 __skb_put(skb, pad_len); 6925 } 6926 6927 return false; 6928} 6929 6930/** 6931 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6932 * @rx_ring: rx descriptor ring packet is being transacted on 6933 * @rx_desc: pointer to the EOP Rx descriptor 6934 * @skb: pointer to current skb being populated 6935 * 6936 * This function checks the ring, descriptor, and packet information in 6937 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6938 * other fields within the skb. 6939 **/ 6940static void igb_process_skb_fields(struct igb_ring *rx_ring, 6941 union e1000_adv_rx_desc *rx_desc, 6942 struct sk_buff *skb) 6943{ 6944 struct net_device *dev = rx_ring->netdev; 6945 6946 igb_rx_hash(rx_ring, rx_desc, skb); 6947 6948 igb_rx_checksum(rx_ring, rx_desc, skb); 6949 6950 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 6951 6952 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 6953 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6954 u16 vid; 6955 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6956 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6957 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6958 else 6959 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6960 6961 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 6962 } 6963 6964 skb_record_rx_queue(skb, rx_ring->queue_index); 6965 6966 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6967} 6968 6969static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 6970{ 6971 struct igb_ring *rx_ring = q_vector->rx.ring; 6972 struct sk_buff *skb = rx_ring->skb; 6973 unsigned int total_bytes = 0, total_packets = 0; 6974 u16 cleaned_count = igb_desc_unused(rx_ring); 6975 6976 while (likely(total_packets < budget)) { 6977 union e1000_adv_rx_desc *rx_desc; 6978 6979 /* return some buffers to hardware, one at a time is too slow */ 6980 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6981 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6982 cleaned_count = 0; 6983 } 6984 6985 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 6986 6987 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) 6988 break; 6989 6990 /* This memory barrier is needed to keep us from reading 6991 * any other fields out of the rx_desc until we know the 6992 * RXD_STAT_DD bit is set 6993 */ 6994 rmb(); 6995 6996 /* retrieve a buffer from the ring */ 6997 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 6998 6999 /* exit if we failed to retrieve a buffer */ 7000 if (!skb) 7001 break; 7002 7003 cleaned_count++; 7004 7005 /* fetch next buffer in frame if non-eop */ 7006 if (igb_is_non_eop(rx_ring, rx_desc)) 7007 continue; 7008 7009 /* verify the packet layout is correct */ 7010 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 7011 skb = NULL; 7012 continue; 7013 } 7014 7015 /* probably a little skewed due to removing CRC */ 7016 total_bytes += skb->len; 7017 7018 /* populate checksum, timestamp, VLAN, and protocol */ 7019 igb_process_skb_fields(rx_ring, rx_desc, skb); 7020 7021 napi_gro_receive(&q_vector->napi, skb); 7022 7023 /* reset skb pointer */ 7024 skb = NULL; 7025 7026 /* update budget accounting */ 7027 total_packets++; 7028 } 7029 7030 /* place incomplete frames back on ring for completion */ 7031 rx_ring->skb = skb; 7032 7033 u64_stats_update_begin(&rx_ring->rx_syncp); 7034 rx_ring->rx_stats.packets += total_packets; 7035 rx_ring->rx_stats.bytes += total_bytes; 7036 u64_stats_update_end(&rx_ring->rx_syncp); 7037 q_vector->rx.total_packets += total_packets; 7038 q_vector->rx.total_bytes += total_bytes; 7039 7040 if (cleaned_count) 7041 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7042 7043 return (total_packets < budget); 7044} 7045 7046static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7047 struct igb_rx_buffer *bi) 7048{ 7049 struct page *page = bi->page; 7050 dma_addr_t dma; 7051 7052 /* since we are recycling buffers we should seldom need to alloc */ 7053 if (likely(page)) 7054 return true; 7055 7056 /* alloc new page for storage */ 7057 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); 7058 if (unlikely(!page)) { 7059 rx_ring->rx_stats.alloc_failed++; 7060 return false; 7061 } 7062 7063 /* map page for use */ 7064 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 7065 7066 /* if mapping failed free memory back to system since 7067 * there isn't much point in holding memory we can't use 7068 */ 7069 if (dma_mapping_error(rx_ring->dev, dma)) { 7070 __free_page(page); 7071 7072 rx_ring->rx_stats.alloc_failed++; 7073 return false; 7074 } 7075 7076 bi->dma = dma; 7077 bi->page = page; 7078 bi->page_offset = 0; 7079 7080 return true; 7081} 7082 7083/** 7084 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7085 * @adapter: address of board private structure 7086 **/ 7087void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7088{ 7089 union e1000_adv_rx_desc *rx_desc; 7090 struct igb_rx_buffer *bi; 7091 u16 i = rx_ring->next_to_use; 7092 7093 /* nothing to do */ 7094 if (!cleaned_count) 7095 return; 7096 7097 rx_desc = IGB_RX_DESC(rx_ring, i); 7098 bi = &rx_ring->rx_buffer_info[i]; 7099 i -= rx_ring->count; 7100 7101 do { 7102 if (!igb_alloc_mapped_page(rx_ring, bi)) 7103 break; 7104 7105 /* Refresh the desc even if buffer_addrs didn't change 7106 * because each write-back erases this info. 7107 */ 7108 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7109 7110 rx_desc++; 7111 bi++; 7112 i++; 7113 if (unlikely(!i)) { 7114 rx_desc = IGB_RX_DESC(rx_ring, 0); 7115 bi = rx_ring->rx_buffer_info; 7116 i -= rx_ring->count; 7117 } 7118 7119 /* clear the hdr_addr for the next_to_use descriptor */ 7120 rx_desc->read.hdr_addr = 0; 7121 7122 cleaned_count--; 7123 } while (cleaned_count); 7124 7125 i += rx_ring->count; 7126 7127 if (rx_ring->next_to_use != i) { 7128 /* record the next descriptor to use */ 7129 rx_ring->next_to_use = i; 7130 7131 /* update next to alloc since we have filled the ring */ 7132 rx_ring->next_to_alloc = i; 7133 7134 /* Force memory writes to complete before letting h/w 7135 * know there are new descriptors to fetch. (Only 7136 * applicable for weak-ordered memory model archs, 7137 * such as IA-64). 7138 */ 7139 wmb(); 7140 writel(i, rx_ring->tail); 7141 } 7142} 7143 7144/** 7145 * igb_mii_ioctl - 7146 * @netdev: 7147 * @ifreq: 7148 * @cmd: 7149 **/ 7150static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7151{ 7152 struct igb_adapter *adapter = netdev_priv(netdev); 7153 struct mii_ioctl_data *data = if_mii(ifr); 7154 7155 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7156 return -EOPNOTSUPP; 7157 7158 switch (cmd) { 7159 case SIOCGMIIPHY: 7160 data->phy_id = adapter->hw.phy.addr; 7161 break; 7162 case SIOCGMIIREG: 7163 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7164 &data->val_out)) 7165 return -EIO; 7166 break; 7167 case SIOCSMIIREG: 7168 default: 7169 return -EOPNOTSUPP; 7170 } 7171 return 0; 7172} 7173 7174/** 7175 * igb_ioctl - 7176 * @netdev: 7177 * @ifreq: 7178 * @cmd: 7179 **/ 7180static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7181{ 7182 switch (cmd) { 7183 case SIOCGMIIPHY: 7184 case SIOCGMIIREG: 7185 case SIOCSMIIREG: 7186 return igb_mii_ioctl(netdev, ifr, cmd); 7187 case SIOCGHWTSTAMP: 7188 return igb_ptp_get_ts_config(netdev, ifr); 7189 case SIOCSHWTSTAMP: 7190 return igb_ptp_set_ts_config(netdev, ifr); 7191 default: 7192 return -EOPNOTSUPP; 7193 } 7194} 7195 7196s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7197{ 7198 struct igb_adapter *adapter = hw->back; 7199 7200 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7201 return -E1000_ERR_CONFIG; 7202 7203 return 0; 7204} 7205 7206s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7207{ 7208 struct igb_adapter *adapter = hw->back; 7209 7210 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7211 return -E1000_ERR_CONFIG; 7212 7213 return 0; 7214} 7215 7216static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7217{ 7218 struct igb_adapter *adapter = netdev_priv(netdev); 7219 struct e1000_hw *hw = &adapter->hw; 7220 u32 ctrl, rctl; 7221 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7222 7223 if (enable) { 7224 /* enable VLAN tag insert/strip */ 7225 ctrl = rd32(E1000_CTRL); 7226 ctrl |= E1000_CTRL_VME; 7227 wr32(E1000_CTRL, ctrl); 7228 7229 /* Disable CFI check */ 7230 rctl = rd32(E1000_RCTL); 7231 rctl &= ~E1000_RCTL_CFIEN; 7232 wr32(E1000_RCTL, rctl); 7233 } else { 7234 /* disable VLAN tag insert/strip */ 7235 ctrl = rd32(E1000_CTRL); 7236 ctrl &= ~E1000_CTRL_VME; 7237 wr32(E1000_CTRL, ctrl); 7238 } 7239 7240 igb_rlpml_set(adapter); 7241} 7242 7243static int igb_vlan_rx_add_vid(struct net_device *netdev, 7244 __be16 proto, u16 vid) 7245{ 7246 struct igb_adapter *adapter = netdev_priv(netdev); 7247 struct e1000_hw *hw = &adapter->hw; 7248 int pf_id = adapter->vfs_allocated_count; 7249 7250 /* attempt to add filter to vlvf array */ 7251 igb_vlvf_set(adapter, vid, true, pf_id); 7252 7253 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7254 igb_vfta_set(hw, vid, true); 7255 7256 set_bit(vid, adapter->active_vlans); 7257 7258 return 0; 7259} 7260 7261static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7262 __be16 proto, u16 vid) 7263{ 7264 struct igb_adapter *adapter = netdev_priv(netdev); 7265 struct e1000_hw *hw = &adapter->hw; 7266 int pf_id = adapter->vfs_allocated_count; 7267 s32 err; 7268 7269 /* remove vlan from VLVF table array */ 7270 err = igb_vlvf_set(adapter, vid, false, pf_id); 7271 7272 /* if vid was not present in VLVF just remove it from table */ 7273 if (err) 7274 igb_vfta_set(hw, vid, false); 7275 7276 clear_bit(vid, adapter->active_vlans); 7277 7278 return 0; 7279} 7280 7281static void igb_restore_vlan(struct igb_adapter *adapter) 7282{ 7283 u16 vid; 7284 7285 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7286 7287 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 7288 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7289} 7290 7291int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7292{ 7293 struct pci_dev *pdev = adapter->pdev; 7294 struct e1000_mac_info *mac = &adapter->hw.mac; 7295 7296 mac->autoneg = 0; 7297 7298 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7299 * for the switch() below to work 7300 */ 7301 if ((spd & 1) || (dplx & ~1)) 7302 goto err_inval; 7303 7304 /* Fiber NIC's only allow 1000 gbps Full duplex 7305 * and 100Mbps Full duplex for 100baseFx sfp 7306 */ 7307 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7308 switch (spd + dplx) { 7309 case SPEED_10 + DUPLEX_HALF: 7310 case SPEED_10 + DUPLEX_FULL: 7311 case SPEED_100 + DUPLEX_HALF: 7312 goto err_inval; 7313 default: 7314 break; 7315 } 7316 } 7317 7318 switch (spd + dplx) { 7319 case SPEED_10 + DUPLEX_HALF: 7320 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7321 break; 7322 case SPEED_10 + DUPLEX_FULL: 7323 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7324 break; 7325 case SPEED_100 + DUPLEX_HALF: 7326 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7327 break; 7328 case SPEED_100 + DUPLEX_FULL: 7329 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7330 break; 7331 case SPEED_1000 + DUPLEX_FULL: 7332 mac->autoneg = 1; 7333 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7334 break; 7335 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7336 default: 7337 goto err_inval; 7338 } 7339 7340 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7341 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7342 7343 return 0; 7344 7345err_inval: 7346 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7347 return -EINVAL; 7348} 7349 7350static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7351 bool runtime) 7352{ 7353 struct net_device *netdev = pci_get_drvdata(pdev); 7354 struct igb_adapter *adapter = netdev_priv(netdev); 7355 struct e1000_hw *hw = &adapter->hw; 7356 u32 ctrl, rctl, status; 7357 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7358#ifdef CONFIG_PM 7359 int retval = 0; 7360#endif 7361 7362 netif_device_detach(netdev); 7363 7364 if (netif_running(netdev)) 7365 __igb_close(netdev, true); 7366 7367 igb_clear_interrupt_scheme(adapter); 7368 7369#ifdef CONFIG_PM 7370 retval = pci_save_state(pdev); 7371 if (retval) 7372 return retval; 7373#endif 7374 7375 status = rd32(E1000_STATUS); 7376 if (status & E1000_STATUS_LU) 7377 wufc &= ~E1000_WUFC_LNKC; 7378 7379 if (wufc) { 7380 igb_setup_rctl(adapter); 7381 igb_set_rx_mode(netdev); 7382 7383 /* turn on all-multi mode if wake on multicast is enabled */ 7384 if (wufc & E1000_WUFC_MC) { 7385 rctl = rd32(E1000_RCTL); 7386 rctl |= E1000_RCTL_MPE; 7387 wr32(E1000_RCTL, rctl); 7388 } 7389 7390 ctrl = rd32(E1000_CTRL); 7391 /* advertise wake from D3Cold */ 7392 #define E1000_CTRL_ADVD3WUC 0x00100000 7393 /* phy power management enable */ 7394 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7395 ctrl |= E1000_CTRL_ADVD3WUC; 7396 wr32(E1000_CTRL, ctrl); 7397 7398 /* Allow time for pending master requests to run */ 7399 igb_disable_pcie_master(hw); 7400 7401 wr32(E1000_WUC, E1000_WUC_PME_EN); 7402 wr32(E1000_WUFC, wufc); 7403 } else { 7404 wr32(E1000_WUC, 0); 7405 wr32(E1000_WUFC, 0); 7406 } 7407 7408 *enable_wake = wufc || adapter->en_mng_pt; 7409 if (!*enable_wake) 7410 igb_power_down_link(adapter); 7411 else 7412 igb_power_up_link(adapter); 7413 7414 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7415 * would have already happened in close and is redundant. 7416 */ 7417 igb_release_hw_control(adapter); 7418 7419 pci_disable_device(pdev); 7420 7421 return 0; 7422} 7423 7424#ifdef CONFIG_PM 7425#ifdef CONFIG_PM_SLEEP 7426static int igb_suspend(struct device *dev) 7427{ 7428 int retval; 7429 bool wake; 7430 struct pci_dev *pdev = to_pci_dev(dev); 7431 7432 retval = __igb_shutdown(pdev, &wake, 0); 7433 if (retval) 7434 return retval; 7435 7436 if (wake) { 7437 pci_prepare_to_sleep(pdev); 7438 } else { 7439 pci_wake_from_d3(pdev, false); 7440 pci_set_power_state(pdev, PCI_D3hot); 7441 } 7442 7443 return 0; 7444} 7445#endif /* CONFIG_PM_SLEEP */ 7446 7447static int igb_resume(struct device *dev) 7448{ 7449 struct pci_dev *pdev = to_pci_dev(dev); 7450 struct net_device *netdev = pci_get_drvdata(pdev); 7451 struct igb_adapter *adapter = netdev_priv(netdev); 7452 struct e1000_hw *hw = &adapter->hw; 7453 u32 err; 7454 7455 pci_set_power_state(pdev, PCI_D0); 7456 pci_restore_state(pdev); 7457 pci_save_state(pdev); 7458 7459 err = pci_enable_device_mem(pdev); 7460 if (err) { 7461 dev_err(&pdev->dev, 7462 "igb: Cannot enable PCI device from suspend\n"); 7463 return err; 7464 } 7465 pci_set_master(pdev); 7466 7467 pci_enable_wake(pdev, PCI_D3hot, 0); 7468 pci_enable_wake(pdev, PCI_D3cold, 0); 7469 7470 if (igb_init_interrupt_scheme(adapter, true)) { 7471 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7472 return -ENOMEM; 7473 } 7474 7475 igb_reset(adapter); 7476 7477 /* let the f/w know that the h/w is now under the control of the 7478 * driver. 7479 */ 7480 igb_get_hw_control(adapter); 7481 7482 wr32(E1000_WUS, ~0); 7483 7484 if (netdev->flags & IFF_UP) { 7485 rtnl_lock(); 7486 err = __igb_open(netdev, true); 7487 rtnl_unlock(); 7488 if (err) 7489 return err; 7490 } 7491 7492 netif_device_attach(netdev); 7493 return 0; 7494} 7495 7496#ifdef CONFIG_PM_RUNTIME 7497static int igb_runtime_idle(struct device *dev) 7498{ 7499 struct pci_dev *pdev = to_pci_dev(dev); 7500 struct net_device *netdev = pci_get_drvdata(pdev); 7501 struct igb_adapter *adapter = netdev_priv(netdev); 7502 7503 if (!igb_has_link(adapter)) 7504 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7505 7506 return -EBUSY; 7507} 7508 7509static int igb_runtime_suspend(struct device *dev) 7510{ 7511 struct pci_dev *pdev = to_pci_dev(dev); 7512 int retval; 7513 bool wake; 7514 7515 retval = __igb_shutdown(pdev, &wake, 1); 7516 if (retval) 7517 return retval; 7518 7519 if (wake) { 7520 pci_prepare_to_sleep(pdev); 7521 } else { 7522 pci_wake_from_d3(pdev, false); 7523 pci_set_power_state(pdev, PCI_D3hot); 7524 } 7525 7526 return 0; 7527} 7528 7529static int igb_runtime_resume(struct device *dev) 7530{ 7531 return igb_resume(dev); 7532} 7533#endif /* CONFIG_PM_RUNTIME */ 7534#endif 7535 7536static void igb_shutdown(struct pci_dev *pdev) 7537{ 7538 bool wake; 7539 7540 __igb_shutdown(pdev, &wake, 0); 7541 7542 if (system_state == SYSTEM_POWER_OFF) { 7543 pci_wake_from_d3(pdev, wake); 7544 pci_set_power_state(pdev, PCI_D3hot); 7545 } 7546} 7547 7548#ifdef CONFIG_PCI_IOV 7549static int igb_sriov_reinit(struct pci_dev *dev) 7550{ 7551 struct net_device *netdev = pci_get_drvdata(dev); 7552 struct igb_adapter *adapter = netdev_priv(netdev); 7553 struct pci_dev *pdev = adapter->pdev; 7554 7555 rtnl_lock(); 7556 7557 if (netif_running(netdev)) 7558 igb_close(netdev); 7559 7560 igb_clear_interrupt_scheme(adapter); 7561 7562 igb_init_queue_configuration(adapter); 7563 7564 if (igb_init_interrupt_scheme(adapter, true)) { 7565 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7566 return -ENOMEM; 7567 } 7568 7569 if (netif_running(netdev)) 7570 igb_open(netdev); 7571 7572 rtnl_unlock(); 7573 7574 return 0; 7575} 7576 7577static int igb_pci_disable_sriov(struct pci_dev *dev) 7578{ 7579 int err = igb_disable_sriov(dev); 7580 7581 if (!err) 7582 err = igb_sriov_reinit(dev); 7583 7584 return err; 7585} 7586 7587static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7588{ 7589 int err = igb_enable_sriov(dev, num_vfs); 7590 7591 if (err) 7592 goto out; 7593 7594 err = igb_sriov_reinit(dev); 7595 if (!err) 7596 return num_vfs; 7597 7598out: 7599 return err; 7600} 7601 7602#endif 7603static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7604{ 7605#ifdef CONFIG_PCI_IOV 7606 if (num_vfs == 0) 7607 return igb_pci_disable_sriov(dev); 7608 else 7609 return igb_pci_enable_sriov(dev, num_vfs); 7610#endif 7611 return 0; 7612} 7613 7614#ifdef CONFIG_NET_POLL_CONTROLLER 7615/* Polling 'interrupt' - used by things like netconsole to send skbs 7616 * without having to re-enable interrupts. It's not called while 7617 * the interrupt routine is executing. 7618 */ 7619static void igb_netpoll(struct net_device *netdev) 7620{ 7621 struct igb_adapter *adapter = netdev_priv(netdev); 7622 struct e1000_hw *hw = &adapter->hw; 7623 struct igb_q_vector *q_vector; 7624 int i; 7625 7626 for (i = 0; i < adapter->num_q_vectors; i++) { 7627 q_vector = adapter->q_vector[i]; 7628 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7629 wr32(E1000_EIMC, q_vector->eims_value); 7630 else 7631 igb_irq_disable(adapter); 7632 napi_schedule(&q_vector->napi); 7633 } 7634} 7635#endif /* CONFIG_NET_POLL_CONTROLLER */ 7636 7637/** 7638 * igb_io_error_detected - called when PCI error is detected 7639 * @pdev: Pointer to PCI device 7640 * @state: The current pci connection state 7641 * 7642 * This function is called after a PCI bus error affecting 7643 * this device has been detected. 7644 **/ 7645static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7646 pci_channel_state_t state) 7647{ 7648 struct net_device *netdev = pci_get_drvdata(pdev); 7649 struct igb_adapter *adapter = netdev_priv(netdev); 7650 7651 netif_device_detach(netdev); 7652 7653 if (state == pci_channel_io_perm_failure) 7654 return PCI_ERS_RESULT_DISCONNECT; 7655 7656 if (netif_running(netdev)) 7657 igb_down(adapter); 7658 pci_disable_device(pdev); 7659 7660 /* Request a slot slot reset. */ 7661 return PCI_ERS_RESULT_NEED_RESET; 7662} 7663 7664/** 7665 * igb_io_slot_reset - called after the pci bus has been reset. 7666 * @pdev: Pointer to PCI device 7667 * 7668 * Restart the card from scratch, as if from a cold-boot. Implementation 7669 * resembles the first-half of the igb_resume routine. 7670 **/ 7671static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 7672{ 7673 struct net_device *netdev = pci_get_drvdata(pdev); 7674 struct igb_adapter *adapter = netdev_priv(netdev); 7675 struct e1000_hw *hw = &adapter->hw; 7676 pci_ers_result_t result; 7677 int err; 7678 7679 if (pci_enable_device_mem(pdev)) { 7680 dev_err(&pdev->dev, 7681 "Cannot re-enable PCI device after reset.\n"); 7682 result = PCI_ERS_RESULT_DISCONNECT; 7683 } else { 7684 pci_set_master(pdev); 7685 pci_restore_state(pdev); 7686 pci_save_state(pdev); 7687 7688 pci_enable_wake(pdev, PCI_D3hot, 0); 7689 pci_enable_wake(pdev, PCI_D3cold, 0); 7690 7691 igb_reset(adapter); 7692 wr32(E1000_WUS, ~0); 7693 result = PCI_ERS_RESULT_RECOVERED; 7694 } 7695 7696 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7697 if (err) { 7698 dev_err(&pdev->dev, 7699 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7700 err); 7701 /* non-fatal, continue */ 7702 } 7703 7704 return result; 7705} 7706 7707/** 7708 * igb_io_resume - called when traffic can start flowing again. 7709 * @pdev: Pointer to PCI device 7710 * 7711 * This callback is called when the error recovery driver tells us that 7712 * its OK to resume normal operation. Implementation resembles the 7713 * second-half of the igb_resume routine. 7714 */ 7715static void igb_io_resume(struct pci_dev *pdev) 7716{ 7717 struct net_device *netdev = pci_get_drvdata(pdev); 7718 struct igb_adapter *adapter = netdev_priv(netdev); 7719 7720 if (netif_running(netdev)) { 7721 if (igb_up(adapter)) { 7722 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7723 return; 7724 } 7725 } 7726 7727 netif_device_attach(netdev); 7728 7729 /* let the f/w know that the h/w is now under the control of the 7730 * driver. 7731 */ 7732 igb_get_hw_control(adapter); 7733} 7734 7735static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7736 u8 qsel) 7737{ 7738 u32 rar_low, rar_high; 7739 struct e1000_hw *hw = &adapter->hw; 7740 7741 /* HW expects these in little endian so we reverse the byte order 7742 * from network order (big endian) to little endian 7743 */ 7744 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 7745 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 7746 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 7747 7748 /* Indicate to hardware the Address is Valid. */ 7749 rar_high |= E1000_RAH_AV; 7750 7751 if (hw->mac.type == e1000_82575) 7752 rar_high |= E1000_RAH_POOL_1 * qsel; 7753 else 7754 rar_high |= E1000_RAH_POOL_1 << qsel; 7755 7756 wr32(E1000_RAL(index), rar_low); 7757 wrfl(); 7758 wr32(E1000_RAH(index), rar_high); 7759 wrfl(); 7760} 7761 7762static int igb_set_vf_mac(struct igb_adapter *adapter, 7763 int vf, unsigned char *mac_addr) 7764{ 7765 struct e1000_hw *hw = &adapter->hw; 7766 /* VF MAC addresses start at end of receive addresses and moves 7767 * towards the first, as a result a collision should not be possible 7768 */ 7769 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7770 7771 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7772 7773 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7774 7775 return 0; 7776} 7777 7778static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7779{ 7780 struct igb_adapter *adapter = netdev_priv(netdev); 7781 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7782 return -EINVAL; 7783 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7784 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7785 dev_info(&adapter->pdev->dev, 7786 "Reload the VF driver to make this change effective."); 7787 if (test_bit(__IGB_DOWN, &adapter->state)) { 7788 dev_warn(&adapter->pdev->dev, 7789 "The VF MAC address has been set, but the PF device is not up.\n"); 7790 dev_warn(&adapter->pdev->dev, 7791 "Bring the PF device up before attempting to use the VF device.\n"); 7792 } 7793 return igb_set_vf_mac(adapter, vf, mac); 7794} 7795 7796static int igb_link_mbps(int internal_link_speed) 7797{ 7798 switch (internal_link_speed) { 7799 case SPEED_100: 7800 return 100; 7801 case SPEED_1000: 7802 return 1000; 7803 default: 7804 return 0; 7805 } 7806} 7807 7808static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7809 int link_speed) 7810{ 7811 int rf_dec, rf_int; 7812 u32 bcnrc_val; 7813 7814 if (tx_rate != 0) { 7815 /* Calculate the rate factor values to set */ 7816 rf_int = link_speed / tx_rate; 7817 rf_dec = (link_speed - (rf_int * tx_rate)); 7818 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / 7819 tx_rate; 7820 7821 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7822 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 7823 E1000_RTTBCNRC_RF_INT_MASK); 7824 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7825 } else { 7826 bcnrc_val = 0; 7827 } 7828 7829 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7830 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7831 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7832 */ 7833 wr32(E1000_RTTBCNRM, 0x14); 7834 wr32(E1000_RTTBCNRC, bcnrc_val); 7835} 7836 7837static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7838{ 7839 int actual_link_speed, i; 7840 bool reset_rate = false; 7841 7842 /* VF TX rate limit was not set or not supported */ 7843 if ((adapter->vf_rate_link_speed == 0) || 7844 (adapter->hw.mac.type != e1000_82576)) 7845 return; 7846 7847 actual_link_speed = igb_link_mbps(adapter->link_speed); 7848 if (actual_link_speed != adapter->vf_rate_link_speed) { 7849 reset_rate = true; 7850 adapter->vf_rate_link_speed = 0; 7851 dev_info(&adapter->pdev->dev, 7852 "Link speed has been changed. VF Transmit rate is disabled\n"); 7853 } 7854 7855 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7856 if (reset_rate) 7857 adapter->vf_data[i].tx_rate = 0; 7858 7859 igb_set_vf_rate_limit(&adapter->hw, i, 7860 adapter->vf_data[i].tx_rate, 7861 actual_link_speed); 7862 } 7863} 7864 7865static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) 7866{ 7867 struct igb_adapter *adapter = netdev_priv(netdev); 7868 struct e1000_hw *hw = &adapter->hw; 7869 int actual_link_speed; 7870 7871 if (hw->mac.type != e1000_82576) 7872 return -EOPNOTSUPP; 7873 7874 actual_link_speed = igb_link_mbps(adapter->link_speed); 7875 if ((vf >= adapter->vfs_allocated_count) || 7876 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7877 (tx_rate < 0) || (tx_rate > actual_link_speed)) 7878 return -EINVAL; 7879 7880 adapter->vf_rate_link_speed = actual_link_speed; 7881 adapter->vf_data[vf].tx_rate = (u16)tx_rate; 7882 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); 7883 7884 return 0; 7885} 7886 7887static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 7888 bool setting) 7889{ 7890 struct igb_adapter *adapter = netdev_priv(netdev); 7891 struct e1000_hw *hw = &adapter->hw; 7892 u32 reg_val, reg_offset; 7893 7894 if (!adapter->vfs_allocated_count) 7895 return -EOPNOTSUPP; 7896 7897 if (vf >= adapter->vfs_allocated_count) 7898 return -EINVAL; 7899 7900 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 7901 reg_val = rd32(reg_offset); 7902 if (setting) 7903 reg_val |= ((1 << vf) | 7904 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7905 else 7906 reg_val &= ~((1 << vf) | 7907 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7908 wr32(reg_offset, reg_val); 7909 7910 adapter->vf_data[vf].spoofchk_enabled = setting; 7911 return E1000_SUCCESS; 7912} 7913 7914static int igb_ndo_get_vf_config(struct net_device *netdev, 7915 int vf, struct ifla_vf_info *ivi) 7916{ 7917 struct igb_adapter *adapter = netdev_priv(netdev); 7918 if (vf >= adapter->vfs_allocated_count) 7919 return -EINVAL; 7920 ivi->vf = vf; 7921 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7922 ivi->tx_rate = adapter->vf_data[vf].tx_rate; 7923 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7924 ivi->qos = adapter->vf_data[vf].pf_qos; 7925 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 7926 return 0; 7927} 7928 7929static void igb_vmm_control(struct igb_adapter *adapter) 7930{ 7931 struct e1000_hw *hw = &adapter->hw; 7932 u32 reg; 7933 7934 switch (hw->mac.type) { 7935 case e1000_82575: 7936 case e1000_i210: 7937 case e1000_i211: 7938 case e1000_i354: 7939 default: 7940 /* replication is not supported for 82575 */ 7941 return; 7942 case e1000_82576: 7943 /* notify HW that the MAC is adding vlan tags */ 7944 reg = rd32(E1000_DTXCTL); 7945 reg |= E1000_DTXCTL_VLAN_ADDED; 7946 wr32(E1000_DTXCTL, reg); 7947 case e1000_82580: 7948 /* enable replication vlan tag stripping */ 7949 reg = rd32(E1000_RPLOLR); 7950 reg |= E1000_RPLOLR_STRVLAN; 7951 wr32(E1000_RPLOLR, reg); 7952 case e1000_i350: 7953 /* none of the above registers are supported by i350 */ 7954 break; 7955 } 7956 7957 if (adapter->vfs_allocated_count) { 7958 igb_vmdq_set_loopback_pf(hw, true); 7959 igb_vmdq_set_replication_pf(hw, true); 7960 igb_vmdq_set_anti_spoofing_pf(hw, true, 7961 adapter->vfs_allocated_count); 7962 } else { 7963 igb_vmdq_set_loopback_pf(hw, false); 7964 igb_vmdq_set_replication_pf(hw, false); 7965 } 7966} 7967 7968static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7969{ 7970 struct e1000_hw *hw = &adapter->hw; 7971 u32 dmac_thr; 7972 u16 hwm; 7973 7974 if (hw->mac.type > e1000_82580) { 7975 if (adapter->flags & IGB_FLAG_DMAC) { 7976 u32 reg; 7977 7978 /* force threshold to 0. */ 7979 wr32(E1000_DMCTXTH, 0); 7980 7981 /* DMA Coalescing high water mark needs to be greater 7982 * than the Rx threshold. Set hwm to PBA - max frame 7983 * size in 16B units, capping it at PBA - 6KB. 7984 */ 7985 hwm = 64 * pba - adapter->max_frame_size / 16; 7986 if (hwm < 64 * (pba - 6)) 7987 hwm = 64 * (pba - 6); 7988 reg = rd32(E1000_FCRTC); 7989 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 7990 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 7991 & E1000_FCRTC_RTH_COAL_MASK); 7992 wr32(E1000_FCRTC, reg); 7993 7994 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 7995 * frame size, capping it at PBA - 10KB. 7996 */ 7997 dmac_thr = pba - adapter->max_frame_size / 512; 7998 if (dmac_thr < pba - 10) 7999 dmac_thr = pba - 10; 8000 reg = rd32(E1000_DMACR); 8001 reg &= ~E1000_DMACR_DMACTHR_MASK; 8002 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 8003 & E1000_DMACR_DMACTHR_MASK); 8004 8005 /* transition to L0x or L1 if available..*/ 8006 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 8007 8008 /* watchdog timer= +-1000 usec in 32usec intervals */ 8009 reg |= (1000 >> 5); 8010 8011 /* Disable BMC-to-OS Watchdog Enable */ 8012 if (hw->mac.type != e1000_i354) 8013 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 8014 8015 wr32(E1000_DMACR, reg); 8016 8017 /* no lower threshold to disable 8018 * coalescing(smart fifb)-UTRESH=0 8019 */ 8020 wr32(E1000_DMCRTRH, 0); 8021 8022 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8023 8024 wr32(E1000_DMCTLX, reg); 8025 8026 /* free space in tx packet buffer to wake from 8027 * DMA coal 8028 */ 8029 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8030 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8031 8032 /* make low power state decision controlled 8033 * by DMA coal 8034 */ 8035 reg = rd32(E1000_PCIEMISC); 8036 reg &= ~E1000_PCIEMISC_LX_DECISION; 8037 wr32(E1000_PCIEMISC, reg); 8038 } /* endif adapter->dmac is not disabled */ 8039 } else if (hw->mac.type == e1000_82580) { 8040 u32 reg = rd32(E1000_PCIEMISC); 8041 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8042 wr32(E1000_DMACR, 0); 8043 } 8044} 8045 8046/** 8047 * igb_read_i2c_byte - Reads 8 bit word over I2C 8048 * @hw: pointer to hardware structure 8049 * @byte_offset: byte offset to read 8050 * @dev_addr: device address 8051 * @data: value read 8052 * 8053 * Performs byte read operation over I2C interface at 8054 * a specified device address. 8055 **/ 8056s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8057 u8 dev_addr, u8 *data) 8058{ 8059 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8060 struct i2c_client *this_client = adapter->i2c_client; 8061 s32 status; 8062 u16 swfw_mask = 0; 8063 8064 if (!this_client) 8065 return E1000_ERR_I2C; 8066 8067 swfw_mask = E1000_SWFW_PHY0_SM; 8068 8069 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 8070 != E1000_SUCCESS) 8071 return E1000_ERR_SWFW_SYNC; 8072 8073 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8074 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8075 8076 if (status < 0) 8077 return E1000_ERR_I2C; 8078 else { 8079 *data = status; 8080 return E1000_SUCCESS; 8081 } 8082} 8083 8084/** 8085 * igb_write_i2c_byte - Writes 8 bit word over I2C 8086 * @hw: pointer to hardware structure 8087 * @byte_offset: byte offset to write 8088 * @dev_addr: device address 8089 * @data: value to write 8090 * 8091 * Performs byte write operation over I2C interface at 8092 * a specified device address. 8093 **/ 8094s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8095 u8 dev_addr, u8 data) 8096{ 8097 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8098 struct i2c_client *this_client = adapter->i2c_client; 8099 s32 status; 8100 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8101 8102 if (!this_client) 8103 return E1000_ERR_I2C; 8104 8105 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) 8106 return E1000_ERR_SWFW_SYNC; 8107 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8108 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8109 8110 if (status) 8111 return E1000_ERR_I2C; 8112 else 8113 return E1000_SUCCESS; 8114 8115} 8116 8117int igb_reinit_queues(struct igb_adapter *adapter) 8118{ 8119 struct net_device *netdev = adapter->netdev; 8120 struct pci_dev *pdev = adapter->pdev; 8121 int err = 0; 8122 8123 if (netif_running(netdev)) 8124 igb_close(netdev); 8125 8126 igb_reset_interrupt_capability(adapter); 8127 8128 if (igb_init_interrupt_scheme(adapter, true)) { 8129 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8130 return -ENOMEM; 8131 } 8132 8133 if (netif_running(netdev)) 8134 err = igb_open(netdev); 8135 8136 return err; 8137} 8138/* igb_main.c */ 8139