igb_main.c revision 57ba34c9b068f314b219affafc19a39f8735d5e8
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25*******************************************************************************/ 26 27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 28 29#include <linux/module.h> 30#include <linux/types.h> 31#include <linux/init.h> 32#include <linux/bitops.h> 33#include <linux/vmalloc.h> 34#include <linux/pagemap.h> 35#include <linux/netdevice.h> 36#include <linux/ipv6.h> 37#include <linux/slab.h> 38#include <net/checksum.h> 39#include <net/ip6_checksum.h> 40#include <linux/net_tstamp.h> 41#include <linux/mii.h> 42#include <linux/ethtool.h> 43#include <linux/if.h> 44#include <linux/if_vlan.h> 45#include <linux/pci.h> 46#include <linux/pci-aspm.h> 47#include <linux/delay.h> 48#include <linux/interrupt.h> 49#include <linux/ip.h> 50#include <linux/tcp.h> 51#include <linux/sctp.h> 52#include <linux/if_ether.h> 53#include <linux/aer.h> 54#include <linux/prefetch.h> 55#include <linux/pm_runtime.h> 56#ifdef CONFIG_IGB_DCA 57#include <linux/dca.h> 58#endif 59#include <linux/i2c.h> 60#include "igb.h" 61 62#define MAJ 5 63#define MIN 0 64#define BUILD 5 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 66__stringify(BUILD) "-k" 67char igb_driver_name[] = "igb"; 68char igb_driver_version[] = DRV_VERSION; 69static const char igb_driver_string[] = 70 "Intel(R) Gigabit Ethernet Network Driver"; 71static const char igb_copyright[] = 72 "Copyright (c) 2007-2014 Intel Corporation."; 73 74static const struct e1000_info *igb_info_tbl[] = { 75 [board_82575] = &e1000_82575_info, 76}; 77 78static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 114 /* required last entry */ 115 {0, } 116}; 117 118MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 119 120void igb_reset(struct igb_adapter *); 121static int igb_setup_all_tx_resources(struct igb_adapter *); 122static int igb_setup_all_rx_resources(struct igb_adapter *); 123static void igb_free_all_tx_resources(struct igb_adapter *); 124static void igb_free_all_rx_resources(struct igb_adapter *); 125static void igb_setup_mrqc(struct igb_adapter *); 126static int igb_probe(struct pci_dev *, const struct pci_device_id *); 127static void igb_remove(struct pci_dev *pdev); 128static int igb_sw_init(struct igb_adapter *); 129static int igb_open(struct net_device *); 130static int igb_close(struct net_device *); 131static void igb_configure(struct igb_adapter *); 132static void igb_configure_tx(struct igb_adapter *); 133static void igb_configure_rx(struct igb_adapter *); 134static void igb_clean_all_tx_rings(struct igb_adapter *); 135static void igb_clean_all_rx_rings(struct igb_adapter *); 136static void igb_clean_tx_ring(struct igb_ring *); 137static void igb_clean_rx_ring(struct igb_ring *); 138static void igb_set_rx_mode(struct net_device *); 139static void igb_update_phy_info(unsigned long); 140static void igb_watchdog(unsigned long); 141static void igb_watchdog_task(struct work_struct *); 142static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 143static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 144 struct rtnl_link_stats64 *stats); 145static int igb_change_mtu(struct net_device *, int); 146static int igb_set_mac(struct net_device *, void *); 147static void igb_set_uta(struct igb_adapter *adapter); 148static irqreturn_t igb_intr(int irq, void *); 149static irqreturn_t igb_intr_msi(int irq, void *); 150static irqreturn_t igb_msix_other(int irq, void *); 151static irqreturn_t igb_msix_ring(int irq, void *); 152#ifdef CONFIG_IGB_DCA 153static void igb_update_dca(struct igb_q_vector *); 154static void igb_setup_dca(struct igb_adapter *); 155#endif /* CONFIG_IGB_DCA */ 156static int igb_poll(struct napi_struct *, int); 157static bool igb_clean_tx_irq(struct igb_q_vector *); 158static bool igb_clean_rx_irq(struct igb_q_vector *, int); 159static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 160static void igb_tx_timeout(struct net_device *); 161static void igb_reset_task(struct work_struct *); 162static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); 163static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 164static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 165static void igb_restore_vlan(struct igb_adapter *); 166static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 167static void igb_ping_all_vfs(struct igb_adapter *); 168static void igb_msg_task(struct igb_adapter *); 169static void igb_vmm_control(struct igb_adapter *); 170static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 171static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 172static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 173static int igb_ndo_set_vf_vlan(struct net_device *netdev, 174 int vf, u16 vlan, u8 qos); 175static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 176static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 177 bool setting); 178static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 179 struct ifla_vf_info *ivi); 180static void igb_check_vf_rate_limit(struct igb_adapter *); 181 182#ifdef CONFIG_PCI_IOV 183static int igb_vf_configure(struct igb_adapter *adapter, int vf); 184static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 185#endif 186 187#ifdef CONFIG_PM 188#ifdef CONFIG_PM_SLEEP 189static int igb_suspend(struct device *); 190#endif 191static int igb_resume(struct device *); 192#ifdef CONFIG_PM_RUNTIME 193static int igb_runtime_suspend(struct device *dev); 194static int igb_runtime_resume(struct device *dev); 195static int igb_runtime_idle(struct device *dev); 196#endif 197static const struct dev_pm_ops igb_pm_ops = { 198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 200 igb_runtime_idle) 201}; 202#endif 203static void igb_shutdown(struct pci_dev *); 204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 205#ifdef CONFIG_IGB_DCA 206static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 207static struct notifier_block dca_notifier = { 208 .notifier_call = igb_notify_dca, 209 .next = NULL, 210 .priority = 0 211}; 212#endif 213#ifdef CONFIG_NET_POLL_CONTROLLER 214/* for netdump / net console */ 215static void igb_netpoll(struct net_device *); 216#endif 217#ifdef CONFIG_PCI_IOV 218static unsigned int max_vfs = 0; 219module_param(max_vfs, uint, 0); 220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " 221 "per physical function"); 222#endif /* CONFIG_PCI_IOV */ 223 224static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 225 pci_channel_state_t); 226static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 227static void igb_io_resume(struct pci_dev *); 228 229static const struct pci_error_handlers igb_err_handler = { 230 .error_detected = igb_io_error_detected, 231 .slot_reset = igb_io_slot_reset, 232 .resume = igb_io_resume, 233}; 234 235static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 236 237static struct pci_driver igb_driver = { 238 .name = igb_driver_name, 239 .id_table = igb_pci_tbl, 240 .probe = igb_probe, 241 .remove = igb_remove, 242#ifdef CONFIG_PM 243 .driver.pm = &igb_pm_ops, 244#endif 245 .shutdown = igb_shutdown, 246 .sriov_configure = igb_pci_sriov_configure, 247 .err_handler = &igb_err_handler 248}; 249 250MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 251MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 252MODULE_LICENSE("GPL"); 253MODULE_VERSION(DRV_VERSION); 254 255#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 256static int debug = -1; 257module_param(debug, int, 0); 258MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 259 260struct igb_reg_info { 261 u32 ofs; 262 char *name; 263}; 264 265static const struct igb_reg_info igb_reg_info_tbl[] = { 266 267 /* General Registers */ 268 {E1000_CTRL, "CTRL"}, 269 {E1000_STATUS, "STATUS"}, 270 {E1000_CTRL_EXT, "CTRL_EXT"}, 271 272 /* Interrupt Registers */ 273 {E1000_ICR, "ICR"}, 274 275 /* RX Registers */ 276 {E1000_RCTL, "RCTL"}, 277 {E1000_RDLEN(0), "RDLEN"}, 278 {E1000_RDH(0), "RDH"}, 279 {E1000_RDT(0), "RDT"}, 280 {E1000_RXDCTL(0), "RXDCTL"}, 281 {E1000_RDBAL(0), "RDBAL"}, 282 {E1000_RDBAH(0), "RDBAH"}, 283 284 /* TX Registers */ 285 {E1000_TCTL, "TCTL"}, 286 {E1000_TDBAL(0), "TDBAL"}, 287 {E1000_TDBAH(0), "TDBAH"}, 288 {E1000_TDLEN(0), "TDLEN"}, 289 {E1000_TDH(0), "TDH"}, 290 {E1000_TDT(0), "TDT"}, 291 {E1000_TXDCTL(0), "TXDCTL"}, 292 {E1000_TDFH, "TDFH"}, 293 {E1000_TDFT, "TDFT"}, 294 {E1000_TDFHS, "TDFHS"}, 295 {E1000_TDFPC, "TDFPC"}, 296 297 /* List Terminator */ 298 {} 299}; 300 301/* igb_regdump - register printout routine */ 302static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 303{ 304 int n = 0; 305 char rname[16]; 306 u32 regs[8]; 307 308 switch (reginfo->ofs) { 309 case E1000_RDLEN(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDLEN(n)); 312 break; 313 case E1000_RDH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDH(n)); 316 break; 317 case E1000_RDT(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_RDT(n)); 320 break; 321 case E1000_RXDCTL(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_RXDCTL(n)); 324 break; 325 case E1000_RDBAL(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_RDBAL(n)); 328 break; 329 case E1000_RDBAH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_RDBAH(n)); 332 break; 333 case E1000_TDBAL(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_RDBAL(n)); 336 break; 337 case E1000_TDBAH(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TDBAH(n)); 340 break; 341 case E1000_TDLEN(0): 342 for (n = 0; n < 4; n++) 343 regs[n] = rd32(E1000_TDLEN(n)); 344 break; 345 case E1000_TDH(0): 346 for (n = 0; n < 4; n++) 347 regs[n] = rd32(E1000_TDH(n)); 348 break; 349 case E1000_TDT(0): 350 for (n = 0; n < 4; n++) 351 regs[n] = rd32(E1000_TDT(n)); 352 break; 353 case E1000_TXDCTL(0): 354 for (n = 0; n < 4; n++) 355 regs[n] = rd32(E1000_TXDCTL(n)); 356 break; 357 default: 358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 359 return; 360 } 361 362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 364 regs[2], regs[3]); 365} 366 367/* igb_dump - Print registers, Tx-rings and Rx-rings */ 368static void igb_dump(struct igb_adapter *adapter) 369{ 370 struct net_device *netdev = adapter->netdev; 371 struct e1000_hw *hw = &adapter->hw; 372 struct igb_reg_info *reginfo; 373 struct igb_ring *tx_ring; 374 union e1000_adv_tx_desc *tx_desc; 375 struct my_u0 { u64 a; u64 b; } *u0; 376 struct igb_ring *rx_ring; 377 union e1000_adv_rx_desc *rx_desc; 378 u32 staterr; 379 u16 i, n; 380 381 if (!netif_msg_hw(adapter)) 382 return; 383 384 /* Print netdevice Info */ 385 if (netdev) { 386 dev_info(&adapter->pdev->dev, "Net device Info\n"); 387 pr_info("Device Name state trans_start " 388 "last_rx\n"); 389 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 390 netdev->state, netdev->trans_start, netdev->last_rx); 391 } 392 393 /* Print Registers */ 394 dev_info(&adapter->pdev->dev, "Register Dump\n"); 395 pr_info(" Register Name Value\n"); 396 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 397 reginfo->name; reginfo++) { 398 igb_regdump(hw, reginfo); 399 } 400 401 /* Print TX Ring Summary */ 402 if (!netdev || !netif_running(netdev)) 403 goto exit; 404 405 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 406 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 407 for (n = 0; n < adapter->num_tx_queues; n++) { 408 struct igb_tx_buffer *buffer_info; 409 tx_ring = adapter->tx_ring[n]; 410 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 411 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 412 n, tx_ring->next_to_use, tx_ring->next_to_clean, 413 (u64)dma_unmap_addr(buffer_info, dma), 414 dma_unmap_len(buffer_info, len), 415 buffer_info->next_to_watch, 416 (u64)buffer_info->time_stamp); 417 } 418 419 /* Print TX Rings */ 420 if (!netif_msg_tx_done(adapter)) 421 goto rx_ring_summary; 422 423 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 424 425 /* Transmit Descriptor Formats 426 * 427 * Advanced Transmit Descriptor 428 * +--------------------------------------------------------------+ 429 * 0 | Buffer Address [63:0] | 430 * +--------------------------------------------------------------+ 431 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 432 * +--------------------------------------------------------------+ 433 * 63 46 45 40 39 38 36 35 32 31 24 15 0 434 */ 435 436 for (n = 0; n < adapter->num_tx_queues; n++) { 437 tx_ring = adapter->tx_ring[n]; 438 pr_info("------------------------------------\n"); 439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 440 pr_info("------------------------------------\n"); 441 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] " 442 "[bi->dma ] leng ntw timestamp " 443 "bi->skb\n"); 444 445 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 446 const char *next_desc; 447 struct igb_tx_buffer *buffer_info; 448 tx_desc = IGB_TX_DESC(tx_ring, i); 449 buffer_info = &tx_ring->tx_buffer_info[i]; 450 u0 = (struct my_u0 *)tx_desc; 451 if (i == tx_ring->next_to_use && 452 i == tx_ring->next_to_clean) 453 next_desc = " NTC/U"; 454 else if (i == tx_ring->next_to_use) 455 next_desc = " NTU"; 456 else if (i == tx_ring->next_to_clean) 457 next_desc = " NTC"; 458 else 459 next_desc = ""; 460 461 pr_info("T [0x%03X] %016llX %016llX %016llX" 462 " %04X %p %016llX %p%s\n", i, 463 le64_to_cpu(u0->a), 464 le64_to_cpu(u0->b), 465 (u64)dma_unmap_addr(buffer_info, dma), 466 dma_unmap_len(buffer_info, len), 467 buffer_info->next_to_watch, 468 (u64)buffer_info->time_stamp, 469 buffer_info->skb, next_desc); 470 471 if (netif_msg_pktdata(adapter) && buffer_info->skb) 472 print_hex_dump(KERN_INFO, "", 473 DUMP_PREFIX_ADDRESS, 474 16, 1, buffer_info->skb->data, 475 dma_unmap_len(buffer_info, len), 476 true); 477 } 478 } 479 480 /* Print RX Rings Summary */ 481rx_ring_summary: 482 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 483 pr_info("Queue [NTU] [NTC]\n"); 484 for (n = 0; n < adapter->num_rx_queues; n++) { 485 rx_ring = adapter->rx_ring[n]; 486 pr_info(" %5d %5X %5X\n", 487 n, rx_ring->next_to_use, rx_ring->next_to_clean); 488 } 489 490 /* Print RX Rings */ 491 if (!netif_msg_rx_status(adapter)) 492 goto exit; 493 494 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 495 496 /* Advanced Receive Descriptor (Read) Format 497 * 63 1 0 498 * +-----------------------------------------------------+ 499 * 0 | Packet Buffer Address [63:1] |A0/NSE| 500 * +----------------------------------------------+------+ 501 * 8 | Header Buffer Address [63:1] | DD | 502 * +-----------------------------------------------------+ 503 * 504 * 505 * Advanced Receive Descriptor (Write-Back) Format 506 * 507 * 63 48 47 32 31 30 21 20 17 16 4 3 0 508 * +------------------------------------------------------+ 509 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 510 * | Checksum Ident | | | | Type | Type | 511 * +------------------------------------------------------+ 512 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 513 * +------------------------------------------------------+ 514 * 63 48 47 32 31 20 19 0 515 */ 516 517 for (n = 0; n < adapter->num_rx_queues; n++) { 518 rx_ring = adapter->rx_ring[n]; 519 pr_info("------------------------------------\n"); 520 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 521 pr_info("------------------------------------\n"); 522 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] " 523 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 524 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----" 525 "----------- [bi->skb] <-- Adv Rx Write-Back format\n"); 526 527 for (i = 0; i < rx_ring->count; i++) { 528 const char *next_desc; 529 struct igb_rx_buffer *buffer_info; 530 buffer_info = &rx_ring->rx_buffer_info[i]; 531 rx_desc = IGB_RX_DESC(rx_ring, i); 532 u0 = (struct my_u0 *)rx_desc; 533 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 534 535 if (i == rx_ring->next_to_use) 536 next_desc = " NTU"; 537 else if (i == rx_ring->next_to_clean) 538 next_desc = " NTC"; 539 else 540 next_desc = ""; 541 542 if (staterr & E1000_RXD_STAT_DD) { 543 /* Descriptor Done */ 544 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 545 "RWB", i, 546 le64_to_cpu(u0->a), 547 le64_to_cpu(u0->b), 548 next_desc); 549 } else { 550 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 551 "R ", i, 552 le64_to_cpu(u0->a), 553 le64_to_cpu(u0->b), 554 (u64)buffer_info->dma, 555 next_desc); 556 557 if (netif_msg_pktdata(adapter) && 558 buffer_info->dma && buffer_info->page) { 559 print_hex_dump(KERN_INFO, "", 560 DUMP_PREFIX_ADDRESS, 561 16, 1, 562 page_address(buffer_info->page) + 563 buffer_info->page_offset, 564 IGB_RX_BUFSZ, true); 565 } 566 } 567 } 568 } 569 570exit: 571 return; 572} 573 574/** 575 * igb_get_i2c_data - Reads the I2C SDA data bit 576 * @hw: pointer to hardware structure 577 * @i2cctl: Current value of I2CCTL register 578 * 579 * Returns the I2C data bit value 580 **/ 581static int igb_get_i2c_data(void *data) 582{ 583 struct igb_adapter *adapter = (struct igb_adapter *)data; 584 struct e1000_hw *hw = &adapter->hw; 585 s32 i2cctl = rd32(E1000_I2CPARAMS); 586 587 return ((i2cctl & E1000_I2C_DATA_IN) != 0); 588} 589 590/** 591 * igb_set_i2c_data - Sets the I2C data bit 592 * @data: pointer to hardware structure 593 * @state: I2C data value (0 or 1) to set 594 * 595 * Sets the I2C data bit 596 **/ 597static void igb_set_i2c_data(void *data, int state) 598{ 599 struct igb_adapter *adapter = (struct igb_adapter *)data; 600 struct e1000_hw *hw = &adapter->hw; 601 s32 i2cctl = rd32(E1000_I2CPARAMS); 602 603 if (state) 604 i2cctl |= E1000_I2C_DATA_OUT; 605 else 606 i2cctl &= ~E1000_I2C_DATA_OUT; 607 608 i2cctl &= ~E1000_I2C_DATA_OE_N; 609 i2cctl |= E1000_I2C_CLK_OE_N; 610 wr32(E1000_I2CPARAMS, i2cctl); 611 wrfl(); 612 613} 614 615/** 616 * igb_set_i2c_clk - Sets the I2C SCL clock 617 * @data: pointer to hardware structure 618 * @state: state to set clock 619 * 620 * Sets the I2C clock line to state 621 **/ 622static void igb_set_i2c_clk(void *data, int state) 623{ 624 struct igb_adapter *adapter = (struct igb_adapter *)data; 625 struct e1000_hw *hw = &adapter->hw; 626 s32 i2cctl = rd32(E1000_I2CPARAMS); 627 628 if (state) { 629 i2cctl |= E1000_I2C_CLK_OUT; 630 i2cctl &= ~E1000_I2C_CLK_OE_N; 631 } else { 632 i2cctl &= ~E1000_I2C_CLK_OUT; 633 i2cctl &= ~E1000_I2C_CLK_OE_N; 634 } 635 wr32(E1000_I2CPARAMS, i2cctl); 636 wrfl(); 637} 638 639/** 640 * igb_get_i2c_clk - Gets the I2C SCL clock state 641 * @data: pointer to hardware structure 642 * 643 * Gets the I2C clock state 644 **/ 645static int igb_get_i2c_clk(void *data) 646{ 647 struct igb_adapter *adapter = (struct igb_adapter *)data; 648 struct e1000_hw *hw = &adapter->hw; 649 s32 i2cctl = rd32(E1000_I2CPARAMS); 650 651 return ((i2cctl & E1000_I2C_CLK_IN) != 0); 652} 653 654static const struct i2c_algo_bit_data igb_i2c_algo = { 655 .setsda = igb_set_i2c_data, 656 .setscl = igb_set_i2c_clk, 657 .getsda = igb_get_i2c_data, 658 .getscl = igb_get_i2c_clk, 659 .udelay = 5, 660 .timeout = 20, 661}; 662 663/** 664 * igb_get_hw_dev - return device 665 * @hw: pointer to hardware structure 666 * 667 * used by hardware layer to print debugging information 668 **/ 669struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 670{ 671 struct igb_adapter *adapter = hw->back; 672 return adapter->netdev; 673} 674 675/** 676 * igb_init_module - Driver Registration Routine 677 * 678 * igb_init_module is the first routine called when the driver is 679 * loaded. All it does is register with the PCI subsystem. 680 **/ 681static int __init igb_init_module(void) 682{ 683 int ret; 684 pr_info("%s - version %s\n", 685 igb_driver_string, igb_driver_version); 686 687 pr_info("%s\n", igb_copyright); 688 689#ifdef CONFIG_IGB_DCA 690 dca_register_notify(&dca_notifier); 691#endif 692 ret = pci_register_driver(&igb_driver); 693 return ret; 694} 695 696module_init(igb_init_module); 697 698/** 699 * igb_exit_module - Driver Exit Cleanup Routine 700 * 701 * igb_exit_module is called just before the driver is removed 702 * from memory. 703 **/ 704static void __exit igb_exit_module(void) 705{ 706#ifdef CONFIG_IGB_DCA 707 dca_unregister_notify(&dca_notifier); 708#endif 709 pci_unregister_driver(&igb_driver); 710} 711 712module_exit(igb_exit_module); 713 714#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 715/** 716 * igb_cache_ring_register - Descriptor ring to register mapping 717 * @adapter: board private structure to initialize 718 * 719 * Once we know the feature-set enabled for the device, we'll cache 720 * the register offset the descriptor ring is assigned to. 721 **/ 722static void igb_cache_ring_register(struct igb_adapter *adapter) 723{ 724 int i = 0, j = 0; 725 u32 rbase_offset = adapter->vfs_allocated_count; 726 727 switch (adapter->hw.mac.type) { 728 case e1000_82576: 729 /* The queues are allocated for virtualization such that VF 0 730 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 731 * In order to avoid collision we start at the first free queue 732 * and continue consuming queues in the same sequence 733 */ 734 if (adapter->vfs_allocated_count) { 735 for (; i < adapter->rss_queues; i++) 736 adapter->rx_ring[i]->reg_idx = rbase_offset + 737 Q_IDX_82576(i); 738 } 739 case e1000_82575: 740 case e1000_82580: 741 case e1000_i350: 742 case e1000_i354: 743 case e1000_i210: 744 case e1000_i211: 745 default: 746 for (; i < adapter->num_rx_queues; i++) 747 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 748 for (; j < adapter->num_tx_queues; j++) 749 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 750 break; 751 } 752} 753 754/** 755 * igb_write_ivar - configure ivar for given MSI-X vector 756 * @hw: pointer to the HW structure 757 * @msix_vector: vector number we are allocating to a given ring 758 * @index: row index of IVAR register to write within IVAR table 759 * @offset: column offset of in IVAR, should be multiple of 8 760 * 761 * This function is intended to handle the writing of the IVAR register 762 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 763 * each containing an cause allocation for an Rx and Tx ring, and a 764 * variable number of rows depending on the number of queues supported. 765 **/ 766static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 767 int index, int offset) 768{ 769 u32 ivar = array_rd32(E1000_IVAR0, index); 770 771 /* clear any bits that are currently set */ 772 ivar &= ~((u32)0xFF << offset); 773 774 /* write vector and valid bit */ 775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 776 777 array_wr32(E1000_IVAR0, index, ivar); 778} 779 780#define IGB_N0_QUEUE -1 781static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 782{ 783 struct igb_adapter *adapter = q_vector->adapter; 784 struct e1000_hw *hw = &adapter->hw; 785 int rx_queue = IGB_N0_QUEUE; 786 int tx_queue = IGB_N0_QUEUE; 787 u32 msixbm = 0; 788 789 if (q_vector->rx.ring) 790 rx_queue = q_vector->rx.ring->reg_idx; 791 if (q_vector->tx.ring) 792 tx_queue = q_vector->tx.ring->reg_idx; 793 794 switch (hw->mac.type) { 795 case e1000_82575: 796 /* The 82575 assigns vectors using a bitmask, which matches the 797 * bitmask for the EICR/EIMS/EIMC registers. To assign one 798 * or more queues to a vector, we write the appropriate bits 799 * into the MSIXBM register for that vector. 800 */ 801 if (rx_queue > IGB_N0_QUEUE) 802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 803 if (tx_queue > IGB_N0_QUEUE) 804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 805 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 806 msixbm |= E1000_EIMS_OTHER; 807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 808 q_vector->eims_value = msixbm; 809 break; 810 case e1000_82576: 811 /* 82576 uses a table that essentially consists of 2 columns 812 * with 8 rows. The ordering is column-major so we use the 813 * lower 3 bits as the row index, and the 4th bit as the 814 * column offset. 815 */ 816 if (rx_queue > IGB_N0_QUEUE) 817 igb_write_ivar(hw, msix_vector, 818 rx_queue & 0x7, 819 (rx_queue & 0x8) << 1); 820 if (tx_queue > IGB_N0_QUEUE) 821 igb_write_ivar(hw, msix_vector, 822 tx_queue & 0x7, 823 ((tx_queue & 0x8) << 1) + 8); 824 q_vector->eims_value = 1 << msix_vector; 825 break; 826 case e1000_82580: 827 case e1000_i350: 828 case e1000_i354: 829 case e1000_i210: 830 case e1000_i211: 831 /* On 82580 and newer adapters the scheme is similar to 82576 832 * however instead of ordering column-major we have things 833 * ordered row-major. So we traverse the table by using 834 * bit 0 as the column offset, and the remaining bits as the 835 * row index. 836 */ 837 if (rx_queue > IGB_N0_QUEUE) 838 igb_write_ivar(hw, msix_vector, 839 rx_queue >> 1, 840 (rx_queue & 0x1) << 4); 841 if (tx_queue > IGB_N0_QUEUE) 842 igb_write_ivar(hw, msix_vector, 843 tx_queue >> 1, 844 ((tx_queue & 0x1) << 4) + 8); 845 q_vector->eims_value = 1 << msix_vector; 846 break; 847 default: 848 BUG(); 849 break; 850 } 851 852 /* add q_vector eims value to global eims_enable_mask */ 853 adapter->eims_enable_mask |= q_vector->eims_value; 854 855 /* configure q_vector to set itr on first interrupt */ 856 q_vector->set_itr = 1; 857} 858 859/** 860 * igb_configure_msix - Configure MSI-X hardware 861 * @adapter: board private structure to initialize 862 * 863 * igb_configure_msix sets up the hardware to properly 864 * generate MSI-X interrupts. 865 **/ 866static void igb_configure_msix(struct igb_adapter *adapter) 867{ 868 u32 tmp; 869 int i, vector = 0; 870 struct e1000_hw *hw = &adapter->hw; 871 872 adapter->eims_enable_mask = 0; 873 874 /* set vector for other causes, i.e. link changes */ 875 switch (hw->mac.type) { 876 case e1000_82575: 877 tmp = rd32(E1000_CTRL_EXT); 878 /* enable MSI-X PBA support*/ 879 tmp |= E1000_CTRL_EXT_PBA_CLR; 880 881 /* Auto-Mask interrupts upon ICR read. */ 882 tmp |= E1000_CTRL_EXT_EIAME; 883 tmp |= E1000_CTRL_EXT_IRCA; 884 885 wr32(E1000_CTRL_EXT, tmp); 886 887 /* enable msix_other interrupt */ 888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 889 adapter->eims_other = E1000_EIMS_OTHER; 890 891 break; 892 893 case e1000_82576: 894 case e1000_82580: 895 case e1000_i350: 896 case e1000_i354: 897 case e1000_i210: 898 case e1000_i211: 899 /* Turn on MSI-X capability first, or our settings 900 * won't stick. And it will take days to debug. 901 */ 902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 903 E1000_GPIE_PBA | E1000_GPIE_EIAME | 904 E1000_GPIE_NSICR); 905 906 /* enable msix_other interrupt */ 907 adapter->eims_other = 1 << vector; 908 tmp = (vector++ | E1000_IVAR_VALID) << 8; 909 910 wr32(E1000_IVAR_MISC, tmp); 911 break; 912 default: 913 /* do nothing, since nothing else supports MSI-X */ 914 break; 915 } /* switch (hw->mac.type) */ 916 917 adapter->eims_enable_mask |= adapter->eims_other; 918 919 for (i = 0; i < adapter->num_q_vectors; i++) 920 igb_assign_vector(adapter->q_vector[i], vector++); 921 922 wrfl(); 923} 924 925/** 926 * igb_request_msix - Initialize MSI-X interrupts 927 * @adapter: board private structure to initialize 928 * 929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 930 * kernel. 931 **/ 932static int igb_request_msix(struct igb_adapter *adapter) 933{ 934 struct net_device *netdev = adapter->netdev; 935 struct e1000_hw *hw = &adapter->hw; 936 int i, err = 0, vector = 0, free_vector = 0; 937 938 err = request_irq(adapter->msix_entries[vector].vector, 939 igb_msix_other, 0, netdev->name, adapter); 940 if (err) 941 goto err_out; 942 943 for (i = 0; i < adapter->num_q_vectors; i++) { 944 struct igb_q_vector *q_vector = adapter->q_vector[i]; 945 946 vector++; 947 948 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 949 950 if (q_vector->rx.ring && q_vector->tx.ring) 951 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 952 q_vector->rx.ring->queue_index); 953 else if (q_vector->tx.ring) 954 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 955 q_vector->tx.ring->queue_index); 956 else if (q_vector->rx.ring) 957 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 958 q_vector->rx.ring->queue_index); 959 else 960 sprintf(q_vector->name, "%s-unused", netdev->name); 961 962 err = request_irq(adapter->msix_entries[vector].vector, 963 igb_msix_ring, 0, q_vector->name, 964 q_vector); 965 if (err) 966 goto err_free; 967 } 968 969 igb_configure_msix(adapter); 970 return 0; 971 972err_free: 973 /* free already assigned IRQs */ 974 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 975 976 vector--; 977 for (i = 0; i < vector; i++) { 978 free_irq(adapter->msix_entries[free_vector++].vector, 979 adapter->q_vector[i]); 980 } 981err_out: 982 return err; 983} 984 985/** 986 * igb_free_q_vector - Free memory allocated for specific interrupt vector 987 * @adapter: board private structure to initialize 988 * @v_idx: Index of vector to be freed 989 * 990 * This function frees the memory allocated to the q_vector. 991 **/ 992static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 993{ 994 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 995 996 adapter->q_vector[v_idx] = NULL; 997 998 /* igb_get_stats64() might access the rings on this vector, 999 * we must wait a grace period before freeing it. 1000 */ 1001 kfree_rcu(q_vector, rcu); 1002} 1003 1004/** 1005 * igb_reset_q_vector - Reset config for interrupt vector 1006 * @adapter: board private structure to initialize 1007 * @v_idx: Index of vector to be reset 1008 * 1009 * If NAPI is enabled it will delete any references to the 1010 * NAPI struct. This is preparation for igb_free_q_vector. 1011 **/ 1012static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1013{ 1014 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1015 1016 if (q_vector->tx.ring) 1017 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1018 1019 if (q_vector->rx.ring) 1020 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; 1021 1022 netif_napi_del(&q_vector->napi); 1023 1024} 1025 1026static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1027{ 1028 int v_idx = adapter->num_q_vectors; 1029 1030 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1031 pci_disable_msix(adapter->pdev); 1032 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1033 pci_disable_msi(adapter->pdev); 1034 1035 while (v_idx--) 1036 igb_reset_q_vector(adapter, v_idx); 1037} 1038 1039/** 1040 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1041 * @adapter: board private structure to initialize 1042 * 1043 * This function frees the memory allocated to the q_vectors. In addition if 1044 * NAPI is enabled it will delete any references to the NAPI struct prior 1045 * to freeing the q_vector. 1046 **/ 1047static void igb_free_q_vectors(struct igb_adapter *adapter) 1048{ 1049 int v_idx = adapter->num_q_vectors; 1050 1051 adapter->num_tx_queues = 0; 1052 adapter->num_rx_queues = 0; 1053 adapter->num_q_vectors = 0; 1054 1055 while (v_idx--) { 1056 igb_reset_q_vector(adapter, v_idx); 1057 igb_free_q_vector(adapter, v_idx); 1058 } 1059} 1060 1061/** 1062 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1063 * @adapter: board private structure to initialize 1064 * 1065 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1066 * MSI-X interrupts allocated. 1067 */ 1068static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1069{ 1070 igb_free_q_vectors(adapter); 1071 igb_reset_interrupt_capability(adapter); 1072} 1073 1074/** 1075 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1076 * @adapter: board private structure to initialize 1077 * @msix: boolean value of MSIX capability 1078 * 1079 * Attempt to configure interrupts using the best available 1080 * capabilities of the hardware and kernel. 1081 **/ 1082static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1083{ 1084 int err; 1085 int numvecs, i; 1086 1087 if (!msix) 1088 goto msi_only; 1089 adapter->flags |= IGB_FLAG_HAS_MSIX; 1090 1091 /* Number of supported queues. */ 1092 adapter->num_rx_queues = adapter->rss_queues; 1093 if (adapter->vfs_allocated_count) 1094 adapter->num_tx_queues = 1; 1095 else 1096 adapter->num_tx_queues = adapter->rss_queues; 1097 1098 /* start with one vector for every Rx queue */ 1099 numvecs = adapter->num_rx_queues; 1100 1101 /* if Tx handler is separate add 1 for every Tx queue */ 1102 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1103 numvecs += adapter->num_tx_queues; 1104 1105 /* store the number of vectors reserved for queues */ 1106 adapter->num_q_vectors = numvecs; 1107 1108 /* add 1 vector for link status interrupts */ 1109 numvecs++; 1110 for (i = 0; i < numvecs; i++) 1111 adapter->msix_entries[i].entry = i; 1112 1113 err = pci_enable_msix_range(adapter->pdev, 1114 adapter->msix_entries, 1115 numvecs, 1116 numvecs); 1117 if (err > 0) 1118 return; 1119 1120 igb_reset_interrupt_capability(adapter); 1121 1122 /* If we can't do MSI-X, try MSI */ 1123msi_only: 1124#ifdef CONFIG_PCI_IOV 1125 /* disable SR-IOV for non MSI-X configurations */ 1126 if (adapter->vf_data) { 1127 struct e1000_hw *hw = &adapter->hw; 1128 /* disable iov and allow time for transactions to clear */ 1129 pci_disable_sriov(adapter->pdev); 1130 msleep(500); 1131 1132 kfree(adapter->vf_data); 1133 adapter->vf_data = NULL; 1134 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1135 wrfl(); 1136 msleep(100); 1137 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1138 } 1139#endif 1140 adapter->vfs_allocated_count = 0; 1141 adapter->rss_queues = 1; 1142 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1143 adapter->num_rx_queues = 1; 1144 adapter->num_tx_queues = 1; 1145 adapter->num_q_vectors = 1; 1146 if (!pci_enable_msi(adapter->pdev)) 1147 adapter->flags |= IGB_FLAG_HAS_MSI; 1148} 1149 1150static void igb_add_ring(struct igb_ring *ring, 1151 struct igb_ring_container *head) 1152{ 1153 head->ring = ring; 1154 head->count++; 1155} 1156 1157/** 1158 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1159 * @adapter: board private structure to initialize 1160 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1161 * @v_idx: index of vector in adapter struct 1162 * @txr_count: total number of Tx rings to allocate 1163 * @txr_idx: index of first Tx ring to allocate 1164 * @rxr_count: total number of Rx rings to allocate 1165 * @rxr_idx: index of first Rx ring to allocate 1166 * 1167 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1168 **/ 1169static int igb_alloc_q_vector(struct igb_adapter *adapter, 1170 int v_count, int v_idx, 1171 int txr_count, int txr_idx, 1172 int rxr_count, int rxr_idx) 1173{ 1174 struct igb_q_vector *q_vector; 1175 struct igb_ring *ring; 1176 int ring_count, size; 1177 1178 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1179 if (txr_count > 1 || rxr_count > 1) 1180 return -ENOMEM; 1181 1182 ring_count = txr_count + rxr_count; 1183 size = sizeof(struct igb_q_vector) + 1184 (sizeof(struct igb_ring) * ring_count); 1185 1186 /* allocate q_vector and rings */ 1187 q_vector = adapter->q_vector[v_idx]; 1188 if (!q_vector) 1189 q_vector = kzalloc(size, GFP_KERNEL); 1190 if (!q_vector) 1191 return -ENOMEM; 1192 1193 /* initialize NAPI */ 1194 netif_napi_add(adapter->netdev, &q_vector->napi, 1195 igb_poll, 64); 1196 1197 /* tie q_vector and adapter together */ 1198 adapter->q_vector[v_idx] = q_vector; 1199 q_vector->adapter = adapter; 1200 1201 /* initialize work limits */ 1202 q_vector->tx.work_limit = adapter->tx_work_limit; 1203 1204 /* initialize ITR configuration */ 1205 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); 1206 q_vector->itr_val = IGB_START_ITR; 1207 1208 /* initialize pointer to rings */ 1209 ring = q_vector->ring; 1210 1211 /* intialize ITR */ 1212 if (rxr_count) { 1213 /* rx or rx/tx vector */ 1214 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1215 q_vector->itr_val = adapter->rx_itr_setting; 1216 } else { 1217 /* tx only vector */ 1218 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1219 q_vector->itr_val = adapter->tx_itr_setting; 1220 } 1221 1222 if (txr_count) { 1223 /* assign generic ring traits */ 1224 ring->dev = &adapter->pdev->dev; 1225 ring->netdev = adapter->netdev; 1226 1227 /* configure backlink on ring */ 1228 ring->q_vector = q_vector; 1229 1230 /* update q_vector Tx values */ 1231 igb_add_ring(ring, &q_vector->tx); 1232 1233 /* For 82575, context index must be unique per ring. */ 1234 if (adapter->hw.mac.type == e1000_82575) 1235 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1236 1237 /* apply Tx specific ring traits */ 1238 ring->count = adapter->tx_ring_count; 1239 ring->queue_index = txr_idx; 1240 1241 u64_stats_init(&ring->tx_syncp); 1242 u64_stats_init(&ring->tx_syncp2); 1243 1244 /* assign ring to adapter */ 1245 adapter->tx_ring[txr_idx] = ring; 1246 1247 /* push pointer to next ring */ 1248 ring++; 1249 } 1250 1251 if (rxr_count) { 1252 /* assign generic ring traits */ 1253 ring->dev = &adapter->pdev->dev; 1254 ring->netdev = adapter->netdev; 1255 1256 /* configure backlink on ring */ 1257 ring->q_vector = q_vector; 1258 1259 /* update q_vector Rx values */ 1260 igb_add_ring(ring, &q_vector->rx); 1261 1262 /* set flag indicating ring supports SCTP checksum offload */ 1263 if (adapter->hw.mac.type >= e1000_82576) 1264 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1265 1266 /* 1267 * On i350, i354, i210, and i211, loopback VLAN packets 1268 * have the tag byte-swapped. 1269 */ 1270 if (adapter->hw.mac.type >= e1000_i350) 1271 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1272 1273 /* apply Rx specific ring traits */ 1274 ring->count = adapter->rx_ring_count; 1275 ring->queue_index = rxr_idx; 1276 1277 u64_stats_init(&ring->rx_syncp); 1278 1279 /* assign ring to adapter */ 1280 adapter->rx_ring[rxr_idx] = ring; 1281 } 1282 1283 return 0; 1284} 1285 1286 1287/** 1288 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1289 * @adapter: board private structure to initialize 1290 * 1291 * We allocate one q_vector per queue interrupt. If allocation fails we 1292 * return -ENOMEM. 1293 **/ 1294static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1295{ 1296 int q_vectors = adapter->num_q_vectors; 1297 int rxr_remaining = adapter->num_rx_queues; 1298 int txr_remaining = adapter->num_tx_queues; 1299 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1300 int err; 1301 1302 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1303 for (; rxr_remaining; v_idx++) { 1304 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1305 0, 0, 1, rxr_idx); 1306 1307 if (err) 1308 goto err_out; 1309 1310 /* update counts and index */ 1311 rxr_remaining--; 1312 rxr_idx++; 1313 } 1314 } 1315 1316 for (; v_idx < q_vectors; v_idx++) { 1317 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1318 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1319 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1320 tqpv, txr_idx, rqpv, rxr_idx); 1321 1322 if (err) 1323 goto err_out; 1324 1325 /* update counts and index */ 1326 rxr_remaining -= rqpv; 1327 txr_remaining -= tqpv; 1328 rxr_idx++; 1329 txr_idx++; 1330 } 1331 1332 return 0; 1333 1334err_out: 1335 adapter->num_tx_queues = 0; 1336 adapter->num_rx_queues = 0; 1337 adapter->num_q_vectors = 0; 1338 1339 while (v_idx--) 1340 igb_free_q_vector(adapter, v_idx); 1341 1342 return -ENOMEM; 1343} 1344 1345/** 1346 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1347 * @adapter: board private structure to initialize 1348 * @msix: boolean value of MSIX capability 1349 * 1350 * This function initializes the interrupts and allocates all of the queues. 1351 **/ 1352static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1353{ 1354 struct pci_dev *pdev = adapter->pdev; 1355 int err; 1356 1357 igb_set_interrupt_capability(adapter, msix); 1358 1359 err = igb_alloc_q_vectors(adapter); 1360 if (err) { 1361 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1362 goto err_alloc_q_vectors; 1363 } 1364 1365 igb_cache_ring_register(adapter); 1366 1367 return 0; 1368 1369err_alloc_q_vectors: 1370 igb_reset_interrupt_capability(adapter); 1371 return err; 1372} 1373 1374/** 1375 * igb_request_irq - initialize interrupts 1376 * @adapter: board private structure to initialize 1377 * 1378 * Attempts to configure interrupts using the best available 1379 * capabilities of the hardware and kernel. 1380 **/ 1381static int igb_request_irq(struct igb_adapter *adapter) 1382{ 1383 struct net_device *netdev = adapter->netdev; 1384 struct pci_dev *pdev = adapter->pdev; 1385 int err = 0; 1386 1387 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1388 err = igb_request_msix(adapter); 1389 if (!err) 1390 goto request_done; 1391 /* fall back to MSI */ 1392 igb_free_all_tx_resources(adapter); 1393 igb_free_all_rx_resources(adapter); 1394 1395 igb_clear_interrupt_scheme(adapter); 1396 err = igb_init_interrupt_scheme(adapter, false); 1397 if (err) 1398 goto request_done; 1399 1400 igb_setup_all_tx_resources(adapter); 1401 igb_setup_all_rx_resources(adapter); 1402 igb_configure(adapter); 1403 } 1404 1405 igb_assign_vector(adapter->q_vector[0], 0); 1406 1407 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1408 err = request_irq(pdev->irq, igb_intr_msi, 0, 1409 netdev->name, adapter); 1410 if (!err) 1411 goto request_done; 1412 1413 /* fall back to legacy interrupts */ 1414 igb_reset_interrupt_capability(adapter); 1415 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1416 } 1417 1418 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1419 netdev->name, adapter); 1420 1421 if (err) 1422 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1423 err); 1424 1425request_done: 1426 return err; 1427} 1428 1429static void igb_free_irq(struct igb_adapter *adapter) 1430{ 1431 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1432 int vector = 0, i; 1433 1434 free_irq(adapter->msix_entries[vector++].vector, adapter); 1435 1436 for (i = 0; i < adapter->num_q_vectors; i++) 1437 free_irq(adapter->msix_entries[vector++].vector, 1438 adapter->q_vector[i]); 1439 } else { 1440 free_irq(adapter->pdev->irq, adapter); 1441 } 1442} 1443 1444/** 1445 * igb_irq_disable - Mask off interrupt generation on the NIC 1446 * @adapter: board private structure 1447 **/ 1448static void igb_irq_disable(struct igb_adapter *adapter) 1449{ 1450 struct e1000_hw *hw = &adapter->hw; 1451 1452 /* we need to be careful when disabling interrupts. The VFs are also 1453 * mapped into these registers and so clearing the bits can cause 1454 * issues on the VF drivers so we only need to clear what we set 1455 */ 1456 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1457 u32 regval = rd32(E1000_EIAM); 1458 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1459 wr32(E1000_EIMC, adapter->eims_enable_mask); 1460 regval = rd32(E1000_EIAC); 1461 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1462 } 1463 1464 wr32(E1000_IAM, 0); 1465 wr32(E1000_IMC, ~0); 1466 wrfl(); 1467 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1468 int i; 1469 for (i = 0; i < adapter->num_q_vectors; i++) 1470 synchronize_irq(adapter->msix_entries[i].vector); 1471 } else { 1472 synchronize_irq(adapter->pdev->irq); 1473 } 1474} 1475 1476/** 1477 * igb_irq_enable - Enable default interrupt generation settings 1478 * @adapter: board private structure 1479 **/ 1480static void igb_irq_enable(struct igb_adapter *adapter) 1481{ 1482 struct e1000_hw *hw = &adapter->hw; 1483 1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1485 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1486 u32 regval = rd32(E1000_EIAC); 1487 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1488 regval = rd32(E1000_EIAM); 1489 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1490 wr32(E1000_EIMS, adapter->eims_enable_mask); 1491 if (adapter->vfs_allocated_count) { 1492 wr32(E1000_MBVFIMR, 0xFF); 1493 ims |= E1000_IMS_VMMB; 1494 } 1495 wr32(E1000_IMS, ims); 1496 } else { 1497 wr32(E1000_IMS, IMS_ENABLE_MASK | 1498 E1000_IMS_DRSTA); 1499 wr32(E1000_IAM, IMS_ENABLE_MASK | 1500 E1000_IMS_DRSTA); 1501 } 1502} 1503 1504static void igb_update_mng_vlan(struct igb_adapter *adapter) 1505{ 1506 struct e1000_hw *hw = &adapter->hw; 1507 u16 vid = adapter->hw.mng_cookie.vlan_id; 1508 u16 old_vid = adapter->mng_vlan_id; 1509 1510 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1511 /* add VID to filter table */ 1512 igb_vfta_set(hw, vid, true); 1513 adapter->mng_vlan_id = vid; 1514 } else { 1515 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1516 } 1517 1518 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1519 (vid != old_vid) && 1520 !test_bit(old_vid, adapter->active_vlans)) { 1521 /* remove VID from filter table */ 1522 igb_vfta_set(hw, old_vid, false); 1523 } 1524} 1525 1526/** 1527 * igb_release_hw_control - release control of the h/w to f/w 1528 * @adapter: address of board private structure 1529 * 1530 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1531 * For ASF and Pass Through versions of f/w this means that the 1532 * driver is no longer loaded. 1533 **/ 1534static void igb_release_hw_control(struct igb_adapter *adapter) 1535{ 1536 struct e1000_hw *hw = &adapter->hw; 1537 u32 ctrl_ext; 1538 1539 /* Let firmware take over control of h/w */ 1540 ctrl_ext = rd32(E1000_CTRL_EXT); 1541 wr32(E1000_CTRL_EXT, 1542 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1543} 1544 1545/** 1546 * igb_get_hw_control - get control of the h/w from f/w 1547 * @adapter: address of board private structure 1548 * 1549 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1550 * For ASF and Pass Through versions of f/w this means that 1551 * the driver is loaded. 1552 **/ 1553static void igb_get_hw_control(struct igb_adapter *adapter) 1554{ 1555 struct e1000_hw *hw = &adapter->hw; 1556 u32 ctrl_ext; 1557 1558 /* Let firmware know the driver has taken over */ 1559 ctrl_ext = rd32(E1000_CTRL_EXT); 1560 wr32(E1000_CTRL_EXT, 1561 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1562} 1563 1564/** 1565 * igb_configure - configure the hardware for RX and TX 1566 * @adapter: private board structure 1567 **/ 1568static void igb_configure(struct igb_adapter *adapter) 1569{ 1570 struct net_device *netdev = adapter->netdev; 1571 int i; 1572 1573 igb_get_hw_control(adapter); 1574 igb_set_rx_mode(netdev); 1575 1576 igb_restore_vlan(adapter); 1577 1578 igb_setup_tctl(adapter); 1579 igb_setup_mrqc(adapter); 1580 igb_setup_rctl(adapter); 1581 1582 igb_configure_tx(adapter); 1583 igb_configure_rx(adapter); 1584 1585 igb_rx_fifo_flush_82575(&adapter->hw); 1586 1587 /* call igb_desc_unused which always leaves 1588 * at least 1 descriptor unused to make sure 1589 * next_to_use != next_to_clean 1590 */ 1591 for (i = 0; i < adapter->num_rx_queues; i++) { 1592 struct igb_ring *ring = adapter->rx_ring[i]; 1593 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1594 } 1595} 1596 1597/** 1598 * igb_power_up_link - Power up the phy/serdes link 1599 * @adapter: address of board private structure 1600 **/ 1601void igb_power_up_link(struct igb_adapter *adapter) 1602{ 1603 igb_reset_phy(&adapter->hw); 1604 1605 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1606 igb_power_up_phy_copper(&adapter->hw); 1607 else 1608 igb_power_up_serdes_link_82575(&adapter->hw); 1609} 1610 1611/** 1612 * igb_power_down_link - Power down the phy/serdes link 1613 * @adapter: address of board private structure 1614 */ 1615static void igb_power_down_link(struct igb_adapter *adapter) 1616{ 1617 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1618 igb_power_down_phy_copper_82575(&adapter->hw); 1619 else 1620 igb_shutdown_serdes_link_82575(&adapter->hw); 1621} 1622 1623/** 1624 * Detect and switch function for Media Auto Sense 1625 * @adapter: address of the board private structure 1626 **/ 1627static void igb_check_swap_media(struct igb_adapter *adapter) 1628{ 1629 struct e1000_hw *hw = &adapter->hw; 1630 u32 ctrl_ext, connsw; 1631 bool swap_now = false; 1632 1633 ctrl_ext = rd32(E1000_CTRL_EXT); 1634 connsw = rd32(E1000_CONNSW); 1635 1636 /* need to live swap if current media is copper and we have fiber/serdes 1637 * to go to. 1638 */ 1639 1640 if ((hw->phy.media_type == e1000_media_type_copper) && 1641 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1642 swap_now = true; 1643 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1644 /* copper signal takes time to appear */ 1645 if (adapter->copper_tries < 4) { 1646 adapter->copper_tries++; 1647 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1648 wr32(E1000_CONNSW, connsw); 1649 return; 1650 } else { 1651 adapter->copper_tries = 0; 1652 if ((connsw & E1000_CONNSW_PHYSD) && 1653 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1654 swap_now = true; 1655 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1656 wr32(E1000_CONNSW, connsw); 1657 } 1658 } 1659 } 1660 1661 if (!swap_now) 1662 return; 1663 1664 switch (hw->phy.media_type) { 1665 case e1000_media_type_copper: 1666 netdev_info(adapter->netdev, 1667 "MAS: changing media to fiber/serdes\n"); 1668 ctrl_ext |= 1669 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1670 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1671 adapter->copper_tries = 0; 1672 break; 1673 case e1000_media_type_internal_serdes: 1674 case e1000_media_type_fiber: 1675 netdev_info(adapter->netdev, 1676 "MAS: changing media to copper\n"); 1677 ctrl_ext &= 1678 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1679 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1680 break; 1681 default: 1682 /* shouldn't get here during regular operation */ 1683 netdev_err(adapter->netdev, 1684 "AMS: Invalid media type found, returning\n"); 1685 break; 1686 } 1687 wr32(E1000_CTRL_EXT, ctrl_ext); 1688} 1689 1690/** 1691 * igb_up - Open the interface and prepare it to handle traffic 1692 * @adapter: board private structure 1693 **/ 1694int igb_up(struct igb_adapter *adapter) 1695{ 1696 struct e1000_hw *hw = &adapter->hw; 1697 int i; 1698 1699 /* hardware has been reset, we need to reload some things */ 1700 igb_configure(adapter); 1701 1702 clear_bit(__IGB_DOWN, &adapter->state); 1703 1704 for (i = 0; i < adapter->num_q_vectors; i++) 1705 napi_enable(&(adapter->q_vector[i]->napi)); 1706 1707 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1708 igb_configure_msix(adapter); 1709 else 1710 igb_assign_vector(adapter->q_vector[0], 0); 1711 1712 /* Clear any pending interrupts. */ 1713 rd32(E1000_ICR); 1714 igb_irq_enable(adapter); 1715 1716 /* notify VFs that reset has been completed */ 1717 if (adapter->vfs_allocated_count) { 1718 u32 reg_data = rd32(E1000_CTRL_EXT); 1719 reg_data |= E1000_CTRL_EXT_PFRSTD; 1720 wr32(E1000_CTRL_EXT, reg_data); 1721 } 1722 1723 netif_tx_start_all_queues(adapter->netdev); 1724 1725 /* start the watchdog. */ 1726 hw->mac.get_link_status = 1; 1727 schedule_work(&adapter->watchdog_task); 1728 1729 if ((adapter->flags & IGB_FLAG_EEE) && 1730 (!hw->dev_spec._82575.eee_disable)) 1731 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1732 1733 return 0; 1734} 1735 1736void igb_down(struct igb_adapter *adapter) 1737{ 1738 struct net_device *netdev = adapter->netdev; 1739 struct e1000_hw *hw = &adapter->hw; 1740 u32 tctl, rctl; 1741 int i; 1742 1743 /* signal that we're down so the interrupt handler does not 1744 * reschedule our watchdog timer 1745 */ 1746 set_bit(__IGB_DOWN, &adapter->state); 1747 1748 /* disable receives in the hardware */ 1749 rctl = rd32(E1000_RCTL); 1750 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1751 /* flush and sleep below */ 1752 1753 netif_tx_stop_all_queues(netdev); 1754 1755 /* disable transmits in the hardware */ 1756 tctl = rd32(E1000_TCTL); 1757 tctl &= ~E1000_TCTL_EN; 1758 wr32(E1000_TCTL, tctl); 1759 /* flush both disables and wait for them to finish */ 1760 wrfl(); 1761 msleep(10); 1762 1763 igb_irq_disable(adapter); 1764 1765 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1766 1767 for (i = 0; i < adapter->num_q_vectors; i++) { 1768 napi_synchronize(&(adapter->q_vector[i]->napi)); 1769 napi_disable(&(adapter->q_vector[i]->napi)); 1770 } 1771 1772 1773 del_timer_sync(&adapter->watchdog_timer); 1774 del_timer_sync(&adapter->phy_info_timer); 1775 1776 netif_carrier_off(netdev); 1777 1778 /* record the stats before reset*/ 1779 spin_lock(&adapter->stats64_lock); 1780 igb_update_stats(adapter, &adapter->stats64); 1781 spin_unlock(&adapter->stats64_lock); 1782 1783 adapter->link_speed = 0; 1784 adapter->link_duplex = 0; 1785 1786 if (!pci_channel_offline(adapter->pdev)) 1787 igb_reset(adapter); 1788 igb_clean_all_tx_rings(adapter); 1789 igb_clean_all_rx_rings(adapter); 1790#ifdef CONFIG_IGB_DCA 1791 1792 /* since we reset the hardware DCA settings were cleared */ 1793 igb_setup_dca(adapter); 1794#endif 1795} 1796 1797void igb_reinit_locked(struct igb_adapter *adapter) 1798{ 1799 WARN_ON(in_interrupt()); 1800 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1801 msleep(1); 1802 igb_down(adapter); 1803 igb_up(adapter); 1804 clear_bit(__IGB_RESETTING, &adapter->state); 1805} 1806 1807/** igb_enable_mas - Media Autosense re-enable after swap 1808 * 1809 * @adapter: adapter struct 1810 **/ 1811static s32 igb_enable_mas(struct igb_adapter *adapter) 1812{ 1813 struct e1000_hw *hw = &adapter->hw; 1814 u32 connsw; 1815 s32 ret_val = 0; 1816 1817 connsw = rd32(E1000_CONNSW); 1818 if (!(hw->phy.media_type == e1000_media_type_copper)) 1819 return ret_val; 1820 1821 /* configure for SerDes media detect */ 1822 if (!(connsw & E1000_CONNSW_SERDESD)) { 1823 connsw |= E1000_CONNSW_ENRGSRC; 1824 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1825 wr32(E1000_CONNSW, connsw); 1826 wrfl(); 1827 } else if (connsw & E1000_CONNSW_SERDESD) { 1828 /* already SerDes, no need to enable anything */ 1829 return ret_val; 1830 } else { 1831 netdev_info(adapter->netdev, 1832 "MAS: Unable to configure feature, disabling..\n"); 1833 adapter->flags &= ~IGB_FLAG_MAS_ENABLE; 1834 } 1835 return ret_val; 1836} 1837 1838void igb_reset(struct igb_adapter *adapter) 1839{ 1840 struct pci_dev *pdev = adapter->pdev; 1841 struct e1000_hw *hw = &adapter->hw; 1842 struct e1000_mac_info *mac = &hw->mac; 1843 struct e1000_fc_info *fc = &hw->fc; 1844 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; 1845 1846 /* Repartition Pba for greater than 9k mtu 1847 * To take effect CTRL.RST is required. 1848 */ 1849 switch (mac->type) { 1850 case e1000_i350: 1851 case e1000_i354: 1852 case e1000_82580: 1853 pba = rd32(E1000_RXPBS); 1854 pba = igb_rxpbs_adjust_82580(pba); 1855 break; 1856 case e1000_82576: 1857 pba = rd32(E1000_RXPBS); 1858 pba &= E1000_RXPBS_SIZE_MASK_82576; 1859 break; 1860 case e1000_82575: 1861 case e1000_i210: 1862 case e1000_i211: 1863 default: 1864 pba = E1000_PBA_34K; 1865 break; 1866 } 1867 1868 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1869 (mac->type < e1000_82576)) { 1870 /* adjust PBA for jumbo frames */ 1871 wr32(E1000_PBA, pba); 1872 1873 /* To maintain wire speed transmits, the Tx FIFO should be 1874 * large enough to accommodate two full transmit packets, 1875 * rounded up to the next 1KB and expressed in KB. Likewise, 1876 * the Rx FIFO should be large enough to accommodate at least 1877 * one full receive packet and is similarly rounded up and 1878 * expressed in KB. 1879 */ 1880 pba = rd32(E1000_PBA); 1881 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1882 tx_space = pba >> 16; 1883 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1884 pba &= 0xffff; 1885 /* the Tx fifo also stores 16 bytes of information about the Tx 1886 * but don't include ethernet FCS because hardware appends it 1887 */ 1888 min_tx_space = (adapter->max_frame_size + 1889 sizeof(union e1000_adv_tx_desc) - 1890 ETH_FCS_LEN) * 2; 1891 min_tx_space = ALIGN(min_tx_space, 1024); 1892 min_tx_space >>= 10; 1893 /* software strips receive CRC, so leave room for it */ 1894 min_rx_space = adapter->max_frame_size; 1895 min_rx_space = ALIGN(min_rx_space, 1024); 1896 min_rx_space >>= 10; 1897 1898 /* If current Tx allocation is less than the min Tx FIFO size, 1899 * and the min Tx FIFO size is less than the current Rx FIFO 1900 * allocation, take space away from current Rx allocation 1901 */ 1902 if (tx_space < min_tx_space && 1903 ((min_tx_space - tx_space) < pba)) { 1904 pba = pba - (min_tx_space - tx_space); 1905 1906 /* if short on Rx space, Rx wins and must trump Tx 1907 * adjustment 1908 */ 1909 if (pba < min_rx_space) 1910 pba = min_rx_space; 1911 } 1912 wr32(E1000_PBA, pba); 1913 } 1914 1915 /* flow control settings */ 1916 /* The high water mark must be low enough to fit one full frame 1917 * (or the size used for early receive) above it in the Rx FIFO. 1918 * Set it to the lower of: 1919 * - 90% of the Rx FIFO size, or 1920 * - the full Rx FIFO size minus one full frame 1921 */ 1922 hwm = min(((pba << 10) * 9 / 10), 1923 ((pba << 10) - 2 * adapter->max_frame_size)); 1924 1925 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1926 fc->low_water = fc->high_water - 16; 1927 fc->pause_time = 0xFFFF; 1928 fc->send_xon = 1; 1929 fc->current_mode = fc->requested_mode; 1930 1931 /* disable receive for all VFs and wait one second */ 1932 if (adapter->vfs_allocated_count) { 1933 int i; 1934 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1935 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1936 1937 /* ping all the active vfs to let them know we are going down */ 1938 igb_ping_all_vfs(adapter); 1939 1940 /* disable transmits and receives */ 1941 wr32(E1000_VFRE, 0); 1942 wr32(E1000_VFTE, 0); 1943 } 1944 1945 /* Allow time for pending master requests to run */ 1946 hw->mac.ops.reset_hw(hw); 1947 wr32(E1000_WUC, 0); 1948 1949 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1950 /* need to resetup here after media swap */ 1951 adapter->ei.get_invariants(hw); 1952 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1953 } 1954 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 1955 if (igb_enable_mas(adapter)) 1956 dev_err(&pdev->dev, 1957 "Error enabling Media Auto Sense\n"); 1958 } 1959 if (hw->mac.ops.init_hw(hw)) 1960 dev_err(&pdev->dev, "Hardware Error\n"); 1961 1962 /* Flow control settings reset on hardware reset, so guarantee flow 1963 * control is off when forcing speed. 1964 */ 1965 if (!hw->mac.autoneg) 1966 igb_force_mac_fc(hw); 1967 1968 igb_init_dmac(adapter, pba); 1969#ifdef CONFIG_IGB_HWMON 1970 /* Re-initialize the thermal sensor on i350 devices. */ 1971 if (!test_bit(__IGB_DOWN, &adapter->state)) { 1972 if (mac->type == e1000_i350 && hw->bus.func == 0) { 1973 /* If present, re-initialize the external thermal sensor 1974 * interface. 1975 */ 1976 if (adapter->ets) 1977 mac->ops.init_thermal_sensor_thresh(hw); 1978 } 1979 } 1980#endif 1981 /* Re-establish EEE setting */ 1982 if (hw->phy.media_type == e1000_media_type_copper) { 1983 switch (mac->type) { 1984 case e1000_i350: 1985 case e1000_i210: 1986 case e1000_i211: 1987 igb_set_eee_i350(hw); 1988 break; 1989 case e1000_i354: 1990 igb_set_eee_i354(hw); 1991 break; 1992 default: 1993 break; 1994 } 1995 } 1996 if (!netif_running(adapter->netdev)) 1997 igb_power_down_link(adapter); 1998 1999 igb_update_mng_vlan(adapter); 2000 2001 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2002 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2003 2004 /* Re-enable PTP, where applicable. */ 2005 igb_ptp_reset(adapter); 2006 2007 igb_get_phy_info(hw); 2008} 2009 2010static netdev_features_t igb_fix_features(struct net_device *netdev, 2011 netdev_features_t features) 2012{ 2013 /* Since there is no support for separate Rx/Tx vlan accel 2014 * enable/disable make sure Tx flag is always in same state as Rx. 2015 */ 2016 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2017 features |= NETIF_F_HW_VLAN_CTAG_TX; 2018 else 2019 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2020 2021 return features; 2022} 2023 2024static int igb_set_features(struct net_device *netdev, 2025 netdev_features_t features) 2026{ 2027 netdev_features_t changed = netdev->features ^ features; 2028 struct igb_adapter *adapter = netdev_priv(netdev); 2029 2030 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2031 igb_vlan_mode(netdev, features); 2032 2033 if (!(changed & NETIF_F_RXALL)) 2034 return 0; 2035 2036 netdev->features = features; 2037 2038 if (netif_running(netdev)) 2039 igb_reinit_locked(adapter); 2040 else 2041 igb_reset(adapter); 2042 2043 return 0; 2044} 2045 2046static const struct net_device_ops igb_netdev_ops = { 2047 .ndo_open = igb_open, 2048 .ndo_stop = igb_close, 2049 .ndo_start_xmit = igb_xmit_frame, 2050 .ndo_get_stats64 = igb_get_stats64, 2051 .ndo_set_rx_mode = igb_set_rx_mode, 2052 .ndo_set_mac_address = igb_set_mac, 2053 .ndo_change_mtu = igb_change_mtu, 2054 .ndo_do_ioctl = igb_ioctl, 2055 .ndo_tx_timeout = igb_tx_timeout, 2056 .ndo_validate_addr = eth_validate_addr, 2057 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2058 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2059 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2060 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2061 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, 2062 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2063 .ndo_get_vf_config = igb_ndo_get_vf_config, 2064#ifdef CONFIG_NET_POLL_CONTROLLER 2065 .ndo_poll_controller = igb_netpoll, 2066#endif 2067 .ndo_fix_features = igb_fix_features, 2068 .ndo_set_features = igb_set_features, 2069}; 2070 2071/** 2072 * igb_set_fw_version - Configure version string for ethtool 2073 * @adapter: adapter struct 2074 **/ 2075void igb_set_fw_version(struct igb_adapter *adapter) 2076{ 2077 struct e1000_hw *hw = &adapter->hw; 2078 struct e1000_fw_version fw; 2079 2080 igb_get_fw_version(hw, &fw); 2081 2082 switch (hw->mac.type) { 2083 case e1000_i210: 2084 case e1000_i211: 2085 if (!(igb_get_flash_presence_i210(hw))) { 2086 snprintf(adapter->fw_version, 2087 sizeof(adapter->fw_version), 2088 "%2d.%2d-%d", 2089 fw.invm_major, fw.invm_minor, 2090 fw.invm_img_type); 2091 break; 2092 } 2093 /* fall through */ 2094 default: 2095 /* if option is rom valid, display its version too */ 2096 if (fw.or_valid) { 2097 snprintf(adapter->fw_version, 2098 sizeof(adapter->fw_version), 2099 "%d.%d, 0x%08x, %d.%d.%d", 2100 fw.eep_major, fw.eep_minor, fw.etrack_id, 2101 fw.or_major, fw.or_build, fw.or_patch); 2102 /* no option rom */ 2103 } else if (fw.etrack_id != 0X0000) { 2104 snprintf(adapter->fw_version, 2105 sizeof(adapter->fw_version), 2106 "%d.%d, 0x%08x", 2107 fw.eep_major, fw.eep_minor, fw.etrack_id); 2108 } else { 2109 snprintf(adapter->fw_version, 2110 sizeof(adapter->fw_version), 2111 "%d.%d.%d", 2112 fw.eep_major, fw.eep_minor, fw.eep_build); 2113 } 2114 break; 2115 } 2116 return; 2117} 2118 2119/** 2120 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2121 * 2122 * @adapter: adapter struct 2123 **/ 2124static void igb_init_mas(struct igb_adapter *adapter) 2125{ 2126 struct e1000_hw *hw = &adapter->hw; 2127 u16 eeprom_data; 2128 2129 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2130 switch (hw->bus.func) { 2131 case E1000_FUNC_0: 2132 if (eeprom_data & IGB_MAS_ENABLE_0) { 2133 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2134 netdev_info(adapter->netdev, 2135 "MAS: Enabling Media Autosense for port %d\n", 2136 hw->bus.func); 2137 } 2138 break; 2139 case E1000_FUNC_1: 2140 if (eeprom_data & IGB_MAS_ENABLE_1) { 2141 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2142 netdev_info(adapter->netdev, 2143 "MAS: Enabling Media Autosense for port %d\n", 2144 hw->bus.func); 2145 } 2146 break; 2147 case E1000_FUNC_2: 2148 if (eeprom_data & IGB_MAS_ENABLE_2) { 2149 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2150 netdev_info(adapter->netdev, 2151 "MAS: Enabling Media Autosense for port %d\n", 2152 hw->bus.func); 2153 } 2154 break; 2155 case E1000_FUNC_3: 2156 if (eeprom_data & IGB_MAS_ENABLE_3) { 2157 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2158 netdev_info(adapter->netdev, 2159 "MAS: Enabling Media Autosense for port %d\n", 2160 hw->bus.func); 2161 } 2162 break; 2163 default: 2164 /* Shouldn't get here */ 2165 netdev_err(adapter->netdev, 2166 "MAS: Invalid port configuration, returning\n"); 2167 break; 2168 } 2169} 2170 2171/** 2172 * igb_init_i2c - Init I2C interface 2173 * @adapter: pointer to adapter structure 2174 **/ 2175static s32 igb_init_i2c(struct igb_adapter *adapter) 2176{ 2177 s32 status = E1000_SUCCESS; 2178 2179 /* I2C interface supported on i350 devices */ 2180 if (adapter->hw.mac.type != e1000_i350) 2181 return E1000_SUCCESS; 2182 2183 /* Initialize the i2c bus which is controlled by the registers. 2184 * This bus will use the i2c_algo_bit structue that implements 2185 * the protocol through toggling of the 4 bits in the register. 2186 */ 2187 adapter->i2c_adap.owner = THIS_MODULE; 2188 adapter->i2c_algo = igb_i2c_algo; 2189 adapter->i2c_algo.data = adapter; 2190 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2191 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2192 strlcpy(adapter->i2c_adap.name, "igb BB", 2193 sizeof(adapter->i2c_adap.name)); 2194 status = i2c_bit_add_bus(&adapter->i2c_adap); 2195 return status; 2196} 2197 2198/** 2199 * igb_probe - Device Initialization Routine 2200 * @pdev: PCI device information struct 2201 * @ent: entry in igb_pci_tbl 2202 * 2203 * Returns 0 on success, negative on failure 2204 * 2205 * igb_probe initializes an adapter identified by a pci_dev structure. 2206 * The OS initialization, configuring of the adapter private structure, 2207 * and a hardware reset occur. 2208 **/ 2209static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2210{ 2211 struct net_device *netdev; 2212 struct igb_adapter *adapter; 2213 struct e1000_hw *hw; 2214 u16 eeprom_data = 0; 2215 s32 ret_val; 2216 static int global_quad_port_a; /* global quad port a indication */ 2217 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2218 int err, pci_using_dac; 2219 u8 part_str[E1000_PBANUM_LENGTH]; 2220 2221 /* Catch broken hardware that put the wrong VF device ID in 2222 * the PCIe SR-IOV capability. 2223 */ 2224 if (pdev->is_virtfn) { 2225 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2226 pci_name(pdev), pdev->vendor, pdev->device); 2227 return -EINVAL; 2228 } 2229 2230 err = pci_enable_device_mem(pdev); 2231 if (err) 2232 return err; 2233 2234 pci_using_dac = 0; 2235 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2236 if (!err) { 2237 pci_using_dac = 1; 2238 } else { 2239 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2240 if (err) { 2241 dev_err(&pdev->dev, 2242 "No usable DMA configuration, aborting\n"); 2243 goto err_dma; 2244 } 2245 } 2246 2247 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 2248 IORESOURCE_MEM), 2249 igb_driver_name); 2250 if (err) 2251 goto err_pci_reg; 2252 2253 pci_enable_pcie_error_reporting(pdev); 2254 2255 pci_set_master(pdev); 2256 pci_save_state(pdev); 2257 2258 err = -ENOMEM; 2259 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2260 IGB_MAX_TX_QUEUES); 2261 if (!netdev) 2262 goto err_alloc_etherdev; 2263 2264 SET_NETDEV_DEV(netdev, &pdev->dev); 2265 2266 pci_set_drvdata(pdev, netdev); 2267 adapter = netdev_priv(netdev); 2268 adapter->netdev = netdev; 2269 adapter->pdev = pdev; 2270 hw = &adapter->hw; 2271 hw->back = adapter; 2272 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2273 2274 err = -EIO; 2275 hw->hw_addr = pci_iomap(pdev, 0, 0); 2276 if (!hw->hw_addr) 2277 goto err_ioremap; 2278 2279 netdev->netdev_ops = &igb_netdev_ops; 2280 igb_set_ethtool_ops(netdev); 2281 netdev->watchdog_timeo = 5 * HZ; 2282 2283 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2284 2285 netdev->mem_start = pci_resource_start(pdev, 0); 2286 netdev->mem_end = pci_resource_end(pdev, 0); 2287 2288 /* PCI config space info */ 2289 hw->vendor_id = pdev->vendor; 2290 hw->device_id = pdev->device; 2291 hw->revision_id = pdev->revision; 2292 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2293 hw->subsystem_device_id = pdev->subsystem_device; 2294 2295 /* Copy the default MAC, PHY and NVM function pointers */ 2296 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2297 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2298 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2299 /* Initialize skew-specific constants */ 2300 err = ei->get_invariants(hw); 2301 if (err) 2302 goto err_sw_init; 2303 2304 /* setup the private structure */ 2305 err = igb_sw_init(adapter); 2306 if (err) 2307 goto err_sw_init; 2308 2309 igb_get_bus_info_pcie(hw); 2310 2311 hw->phy.autoneg_wait_to_complete = false; 2312 2313 /* Copper options */ 2314 if (hw->phy.media_type == e1000_media_type_copper) { 2315 hw->phy.mdix = AUTO_ALL_MODES; 2316 hw->phy.disable_polarity_correction = false; 2317 hw->phy.ms_type = e1000_ms_hw_default; 2318 } 2319 2320 if (igb_check_reset_block(hw)) 2321 dev_info(&pdev->dev, 2322 "PHY reset is blocked due to SOL/IDER session.\n"); 2323 2324 /* features is initialized to 0 in allocation, it might have bits 2325 * set by igb_sw_init so we should use an or instead of an 2326 * assignment. 2327 */ 2328 netdev->features |= NETIF_F_SG | 2329 NETIF_F_IP_CSUM | 2330 NETIF_F_IPV6_CSUM | 2331 NETIF_F_TSO | 2332 NETIF_F_TSO6 | 2333 NETIF_F_RXHASH | 2334 NETIF_F_RXCSUM | 2335 NETIF_F_HW_VLAN_CTAG_RX | 2336 NETIF_F_HW_VLAN_CTAG_TX; 2337 2338 /* copy netdev features into list of user selectable features */ 2339 netdev->hw_features |= netdev->features; 2340 netdev->hw_features |= NETIF_F_RXALL; 2341 2342 /* set this bit last since it cannot be part of hw_features */ 2343 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2344 2345 netdev->vlan_features |= NETIF_F_TSO | 2346 NETIF_F_TSO6 | 2347 NETIF_F_IP_CSUM | 2348 NETIF_F_IPV6_CSUM | 2349 NETIF_F_SG; 2350 2351 netdev->priv_flags |= IFF_SUPP_NOFCS; 2352 2353 if (pci_using_dac) { 2354 netdev->features |= NETIF_F_HIGHDMA; 2355 netdev->vlan_features |= NETIF_F_HIGHDMA; 2356 } 2357 2358 if (hw->mac.type >= e1000_82576) { 2359 netdev->hw_features |= NETIF_F_SCTP_CSUM; 2360 netdev->features |= NETIF_F_SCTP_CSUM; 2361 } 2362 2363 netdev->priv_flags |= IFF_UNICAST_FLT; 2364 2365 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2366 2367 /* before reading the NVM, reset the controller to put the device in a 2368 * known good starting state 2369 */ 2370 hw->mac.ops.reset_hw(hw); 2371 2372 /* make sure the NVM is good , i211/i210 parts can have special NVM 2373 * that doesn't contain a checksum 2374 */ 2375 switch (hw->mac.type) { 2376 case e1000_i210: 2377 case e1000_i211: 2378 if (igb_get_flash_presence_i210(hw)) { 2379 if (hw->nvm.ops.validate(hw) < 0) { 2380 dev_err(&pdev->dev, 2381 "The NVM Checksum Is Not Valid\n"); 2382 err = -EIO; 2383 goto err_eeprom; 2384 } 2385 } 2386 break; 2387 default: 2388 if (hw->nvm.ops.validate(hw) < 0) { 2389 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2390 err = -EIO; 2391 goto err_eeprom; 2392 } 2393 break; 2394 } 2395 2396 /* copy the MAC address out of the NVM */ 2397 if (hw->mac.ops.read_mac_addr(hw)) 2398 dev_err(&pdev->dev, "NVM Read Error\n"); 2399 2400 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2401 2402 if (!is_valid_ether_addr(netdev->dev_addr)) { 2403 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2404 err = -EIO; 2405 goto err_eeprom; 2406 } 2407 2408 /* get firmware version for ethtool -i */ 2409 igb_set_fw_version(adapter); 2410 2411 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2412 (unsigned long) adapter); 2413 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2414 (unsigned long) adapter); 2415 2416 INIT_WORK(&adapter->reset_task, igb_reset_task); 2417 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2418 2419 /* Initialize link properties that are user-changeable */ 2420 adapter->fc_autoneg = true; 2421 hw->mac.autoneg = true; 2422 hw->phy.autoneg_advertised = 0x2f; 2423 2424 hw->fc.requested_mode = e1000_fc_default; 2425 hw->fc.current_mode = e1000_fc_default; 2426 2427 igb_validate_mdi_setting(hw); 2428 2429 /* By default, support wake on port A */ 2430 if (hw->bus.func == 0) 2431 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2432 2433 /* Check the NVM for wake support on non-port A ports */ 2434 if (hw->mac.type >= e1000_82580) 2435 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2436 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2437 &eeprom_data); 2438 else if (hw->bus.func == 1) 2439 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2440 2441 if (eeprom_data & IGB_EEPROM_APME) 2442 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2443 2444 /* now that we have the eeprom settings, apply the special cases where 2445 * the eeprom may be wrong or the board simply won't support wake on 2446 * lan on a particular port 2447 */ 2448 switch (pdev->device) { 2449 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2450 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2451 break; 2452 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2453 case E1000_DEV_ID_82576_FIBER: 2454 case E1000_DEV_ID_82576_SERDES: 2455 /* Wake events only supported on port A for dual fiber 2456 * regardless of eeprom setting 2457 */ 2458 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2459 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2460 break; 2461 case E1000_DEV_ID_82576_QUAD_COPPER: 2462 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2463 /* if quad port adapter, disable WoL on all but port A */ 2464 if (global_quad_port_a != 0) 2465 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2466 else 2467 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2468 /* Reset for multiple quad port adapters */ 2469 if (++global_quad_port_a == 4) 2470 global_quad_port_a = 0; 2471 break; 2472 default: 2473 /* If the device can't wake, don't set software support */ 2474 if (!device_can_wakeup(&adapter->pdev->dev)) 2475 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2476 } 2477 2478 /* initialize the wol settings based on the eeprom settings */ 2479 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2480 adapter->wol |= E1000_WUFC_MAG; 2481 2482 /* Some vendors want WoL disabled by default, but still supported */ 2483 if ((hw->mac.type == e1000_i350) && 2484 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2485 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2486 adapter->wol = 0; 2487 } 2488 2489 device_set_wakeup_enable(&adapter->pdev->dev, 2490 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2491 2492 /* reset the hardware with the new settings */ 2493 igb_reset(adapter); 2494 2495 /* Init the I2C interface */ 2496 err = igb_init_i2c(adapter); 2497 if (err) { 2498 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2499 goto err_eeprom; 2500 } 2501 2502 /* let the f/w know that the h/w is now under the control of the 2503 * driver. */ 2504 igb_get_hw_control(adapter); 2505 2506 strcpy(netdev->name, "eth%d"); 2507 err = register_netdev(netdev); 2508 if (err) 2509 goto err_register; 2510 2511 /* carrier off reporting is important to ethtool even BEFORE open */ 2512 netif_carrier_off(netdev); 2513 2514#ifdef CONFIG_IGB_DCA 2515 if (dca_add_requester(&pdev->dev) == 0) { 2516 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2517 dev_info(&pdev->dev, "DCA enabled\n"); 2518 igb_setup_dca(adapter); 2519 } 2520 2521#endif 2522#ifdef CONFIG_IGB_HWMON 2523 /* Initialize the thermal sensor on i350 devices. */ 2524 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2525 u16 ets_word; 2526 2527 /* Read the NVM to determine if this i350 device supports an 2528 * external thermal sensor. 2529 */ 2530 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2531 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2532 adapter->ets = true; 2533 else 2534 adapter->ets = false; 2535 if (igb_sysfs_init(adapter)) 2536 dev_err(&pdev->dev, 2537 "failed to allocate sysfs resources\n"); 2538 } else { 2539 adapter->ets = false; 2540 } 2541#endif 2542 /* Check if Media Autosense is enabled */ 2543 adapter->ei = *ei; 2544 if (hw->dev_spec._82575.mas_capable) 2545 igb_init_mas(adapter); 2546 2547 /* do hw tstamp init after resetting */ 2548 igb_ptp_init(adapter); 2549 2550 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2551 /* print bus type/speed/width info, not applicable to i354 */ 2552 if (hw->mac.type != e1000_i354) { 2553 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2554 netdev->name, 2555 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2556 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2557 "unknown"), 2558 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2559 "Width x4" : 2560 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2561 "Width x2" : 2562 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2563 "Width x1" : "unknown"), netdev->dev_addr); 2564 } 2565 2566 if ((hw->mac.type >= e1000_i210 || 2567 igb_get_flash_presence_i210(hw))) { 2568 ret_val = igb_read_part_string(hw, part_str, 2569 E1000_PBANUM_LENGTH); 2570 } else { 2571 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2572 } 2573 2574 if (ret_val) 2575 strcpy(part_str, "Unknown"); 2576 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2577 dev_info(&pdev->dev, 2578 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2579 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2580 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2581 adapter->num_rx_queues, adapter->num_tx_queues); 2582 if (hw->phy.media_type == e1000_media_type_copper) { 2583 switch (hw->mac.type) { 2584 case e1000_i350: 2585 case e1000_i210: 2586 case e1000_i211: 2587 /* Enable EEE for internal copper PHY devices */ 2588 err = igb_set_eee_i350(hw); 2589 if ((!err) && 2590 (!hw->dev_spec._82575.eee_disable)) { 2591 adapter->eee_advert = 2592 MDIO_EEE_100TX | MDIO_EEE_1000T; 2593 adapter->flags |= IGB_FLAG_EEE; 2594 } 2595 break; 2596 case e1000_i354: 2597 if ((rd32(E1000_CTRL_EXT) & 2598 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2599 err = igb_set_eee_i354(hw); 2600 if ((!err) && 2601 (!hw->dev_spec._82575.eee_disable)) { 2602 adapter->eee_advert = 2603 MDIO_EEE_100TX | MDIO_EEE_1000T; 2604 adapter->flags |= IGB_FLAG_EEE; 2605 } 2606 } 2607 break; 2608 default: 2609 break; 2610 } 2611 } 2612 pm_runtime_put_noidle(&pdev->dev); 2613 return 0; 2614 2615err_register: 2616 igb_release_hw_control(adapter); 2617 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2618err_eeprom: 2619 if (!igb_check_reset_block(hw)) 2620 igb_reset_phy(hw); 2621 2622 if (hw->flash_address) 2623 iounmap(hw->flash_address); 2624err_sw_init: 2625 igb_clear_interrupt_scheme(adapter); 2626 iounmap(hw->hw_addr); 2627err_ioremap: 2628 free_netdev(netdev); 2629err_alloc_etherdev: 2630 pci_release_selected_regions(pdev, 2631 pci_select_bars(pdev, IORESOURCE_MEM)); 2632err_pci_reg: 2633err_dma: 2634 pci_disable_device(pdev); 2635 return err; 2636} 2637 2638#ifdef CONFIG_PCI_IOV 2639static int igb_disable_sriov(struct pci_dev *pdev) 2640{ 2641 struct net_device *netdev = pci_get_drvdata(pdev); 2642 struct igb_adapter *adapter = netdev_priv(netdev); 2643 struct e1000_hw *hw = &adapter->hw; 2644 2645 /* reclaim resources allocated to VFs */ 2646 if (adapter->vf_data) { 2647 /* disable iov and allow time for transactions to clear */ 2648 if (pci_vfs_assigned(pdev)) { 2649 dev_warn(&pdev->dev, 2650 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2651 return -EPERM; 2652 } else { 2653 pci_disable_sriov(pdev); 2654 msleep(500); 2655 } 2656 2657 kfree(adapter->vf_data); 2658 adapter->vf_data = NULL; 2659 adapter->vfs_allocated_count = 0; 2660 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2661 wrfl(); 2662 msleep(100); 2663 dev_info(&pdev->dev, "IOV Disabled\n"); 2664 2665 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2666 adapter->flags |= IGB_FLAG_DMAC; 2667 } 2668 2669 return 0; 2670} 2671 2672static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2673{ 2674 struct net_device *netdev = pci_get_drvdata(pdev); 2675 struct igb_adapter *adapter = netdev_priv(netdev); 2676 int old_vfs = pci_num_vf(pdev); 2677 int err = 0; 2678 int i; 2679 2680 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2681 err = -EPERM; 2682 goto out; 2683 } 2684 if (!num_vfs) 2685 goto out; 2686 2687 if (old_vfs) { 2688 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2689 old_vfs, max_vfs); 2690 adapter->vfs_allocated_count = old_vfs; 2691 } else 2692 adapter->vfs_allocated_count = num_vfs; 2693 2694 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2695 sizeof(struct vf_data_storage), GFP_KERNEL); 2696 2697 /* if allocation failed then we do not support SR-IOV */ 2698 if (!adapter->vf_data) { 2699 adapter->vfs_allocated_count = 0; 2700 dev_err(&pdev->dev, 2701 "Unable to allocate memory for VF Data Storage\n"); 2702 err = -ENOMEM; 2703 goto out; 2704 } 2705 2706 /* only call pci_enable_sriov() if no VFs are allocated already */ 2707 if (!old_vfs) { 2708 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2709 if (err) 2710 goto err_out; 2711 } 2712 dev_info(&pdev->dev, "%d VFs allocated\n", 2713 adapter->vfs_allocated_count); 2714 for (i = 0; i < adapter->vfs_allocated_count; i++) 2715 igb_vf_configure(adapter, i); 2716 2717 /* DMA Coalescing is not supported in IOV mode. */ 2718 adapter->flags &= ~IGB_FLAG_DMAC; 2719 goto out; 2720 2721err_out: 2722 kfree(adapter->vf_data); 2723 adapter->vf_data = NULL; 2724 adapter->vfs_allocated_count = 0; 2725out: 2726 return err; 2727} 2728 2729#endif 2730/** 2731 * igb_remove_i2c - Cleanup I2C interface 2732 * @adapter: pointer to adapter structure 2733 **/ 2734static void igb_remove_i2c(struct igb_adapter *adapter) 2735{ 2736 /* free the adapter bus structure */ 2737 i2c_del_adapter(&adapter->i2c_adap); 2738} 2739 2740/** 2741 * igb_remove - Device Removal Routine 2742 * @pdev: PCI device information struct 2743 * 2744 * igb_remove is called by the PCI subsystem to alert the driver 2745 * that it should release a PCI device. The could be caused by a 2746 * Hot-Plug event, or because the driver is going to be removed from 2747 * memory. 2748 **/ 2749static void igb_remove(struct pci_dev *pdev) 2750{ 2751 struct net_device *netdev = pci_get_drvdata(pdev); 2752 struct igb_adapter *adapter = netdev_priv(netdev); 2753 struct e1000_hw *hw = &adapter->hw; 2754 2755 pm_runtime_get_noresume(&pdev->dev); 2756#ifdef CONFIG_IGB_HWMON 2757 igb_sysfs_exit(adapter); 2758#endif 2759 igb_remove_i2c(adapter); 2760 igb_ptp_stop(adapter); 2761 /* The watchdog timer may be rescheduled, so explicitly 2762 * disable watchdog from being rescheduled. 2763 */ 2764 set_bit(__IGB_DOWN, &adapter->state); 2765 del_timer_sync(&adapter->watchdog_timer); 2766 del_timer_sync(&adapter->phy_info_timer); 2767 2768 cancel_work_sync(&adapter->reset_task); 2769 cancel_work_sync(&adapter->watchdog_task); 2770 2771#ifdef CONFIG_IGB_DCA 2772 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2773 dev_info(&pdev->dev, "DCA disabled\n"); 2774 dca_remove_requester(&pdev->dev); 2775 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2776 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2777 } 2778#endif 2779 2780 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2781 * would have already happened in close and is redundant. 2782 */ 2783 igb_release_hw_control(adapter); 2784 2785 unregister_netdev(netdev); 2786 2787 igb_clear_interrupt_scheme(adapter); 2788 2789#ifdef CONFIG_PCI_IOV 2790 igb_disable_sriov(pdev); 2791#endif 2792 2793 iounmap(hw->hw_addr); 2794 if (hw->flash_address) 2795 iounmap(hw->flash_address); 2796 pci_release_selected_regions(pdev, 2797 pci_select_bars(pdev, IORESOURCE_MEM)); 2798 2799 kfree(adapter->shadow_vfta); 2800 free_netdev(netdev); 2801 2802 pci_disable_pcie_error_reporting(pdev); 2803 2804 pci_disable_device(pdev); 2805} 2806 2807/** 2808 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2809 * @adapter: board private structure to initialize 2810 * 2811 * This function initializes the vf specific data storage and then attempts to 2812 * allocate the VFs. The reason for ordering it this way is because it is much 2813 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2814 * the memory for the VFs. 2815 **/ 2816static void igb_probe_vfs(struct igb_adapter *adapter) 2817{ 2818#ifdef CONFIG_PCI_IOV 2819 struct pci_dev *pdev = adapter->pdev; 2820 struct e1000_hw *hw = &adapter->hw; 2821 2822 /* Virtualization features not supported on i210 family. */ 2823 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2824 return; 2825 2826 pci_sriov_set_totalvfs(pdev, 7); 2827 igb_pci_enable_sriov(pdev, max_vfs); 2828 2829#endif /* CONFIG_PCI_IOV */ 2830} 2831 2832static void igb_init_queue_configuration(struct igb_adapter *adapter) 2833{ 2834 struct e1000_hw *hw = &adapter->hw; 2835 u32 max_rss_queues; 2836 2837 /* Determine the maximum number of RSS queues supported. */ 2838 switch (hw->mac.type) { 2839 case e1000_i211: 2840 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2841 break; 2842 case e1000_82575: 2843 case e1000_i210: 2844 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2845 break; 2846 case e1000_i350: 2847 /* I350 cannot do RSS and SR-IOV at the same time */ 2848 if (!!adapter->vfs_allocated_count) { 2849 max_rss_queues = 1; 2850 break; 2851 } 2852 /* fall through */ 2853 case e1000_82576: 2854 if (!!adapter->vfs_allocated_count) { 2855 max_rss_queues = 2; 2856 break; 2857 } 2858 /* fall through */ 2859 case e1000_82580: 2860 case e1000_i354: 2861 default: 2862 max_rss_queues = IGB_MAX_RX_QUEUES; 2863 break; 2864 } 2865 2866 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2867 2868 /* Determine if we need to pair queues. */ 2869 switch (hw->mac.type) { 2870 case e1000_82575: 2871 case e1000_i211: 2872 /* Device supports enough interrupts without queue pairing. */ 2873 break; 2874 case e1000_82576: 2875 /* If VFs are going to be allocated with RSS queues then we 2876 * should pair the queues in order to conserve interrupts due 2877 * to limited supply. 2878 */ 2879 if ((adapter->rss_queues > 1) && 2880 (adapter->vfs_allocated_count > 6)) 2881 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2882 /* fall through */ 2883 case e1000_82580: 2884 case e1000_i350: 2885 case e1000_i354: 2886 case e1000_i210: 2887 default: 2888 /* If rss_queues > half of max_rss_queues, pair the queues in 2889 * order to conserve interrupts due to limited supply. 2890 */ 2891 if (adapter->rss_queues > (max_rss_queues / 2)) 2892 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2893 break; 2894 } 2895} 2896 2897/** 2898 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2899 * @adapter: board private structure to initialize 2900 * 2901 * igb_sw_init initializes the Adapter private data structure. 2902 * Fields are initialized based on PCI device information and 2903 * OS network device settings (MTU size). 2904 **/ 2905static int igb_sw_init(struct igb_adapter *adapter) 2906{ 2907 struct e1000_hw *hw = &adapter->hw; 2908 struct net_device *netdev = adapter->netdev; 2909 struct pci_dev *pdev = adapter->pdev; 2910 2911 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2912 2913 /* set default ring sizes */ 2914 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2915 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2916 2917 /* set default ITR values */ 2918 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2919 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2920 2921 /* set default work limits */ 2922 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2923 2924 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2925 VLAN_HLEN; 2926 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2927 2928 spin_lock_init(&adapter->stats64_lock); 2929#ifdef CONFIG_PCI_IOV 2930 switch (hw->mac.type) { 2931 case e1000_82576: 2932 case e1000_i350: 2933 if (max_vfs > 7) { 2934 dev_warn(&pdev->dev, 2935 "Maximum of 7 VFs per PF, using max\n"); 2936 max_vfs = adapter->vfs_allocated_count = 7; 2937 } else 2938 adapter->vfs_allocated_count = max_vfs; 2939 if (adapter->vfs_allocated_count) 2940 dev_warn(&pdev->dev, 2941 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 2942 break; 2943 default: 2944 break; 2945 } 2946#endif /* CONFIG_PCI_IOV */ 2947 2948 igb_init_queue_configuration(adapter); 2949 2950 /* Setup and initialize a copy of the hw vlan table array */ 2951 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 2952 GFP_ATOMIC); 2953 2954 /* This call may decrease the number of queues */ 2955 if (igb_init_interrupt_scheme(adapter, true)) { 2956 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2957 return -ENOMEM; 2958 } 2959 2960 igb_probe_vfs(adapter); 2961 2962 /* Explicitly disable IRQ since the NIC can be in any state. */ 2963 igb_irq_disable(adapter); 2964 2965 if (hw->mac.type >= e1000_i350) 2966 adapter->flags &= ~IGB_FLAG_DMAC; 2967 2968 set_bit(__IGB_DOWN, &adapter->state); 2969 return 0; 2970} 2971 2972/** 2973 * igb_open - Called when a network interface is made active 2974 * @netdev: network interface device structure 2975 * 2976 * Returns 0 on success, negative value on failure 2977 * 2978 * The open entry point is called when a network interface is made 2979 * active by the system (IFF_UP). At this point all resources needed 2980 * for transmit and receive operations are allocated, the interrupt 2981 * handler is registered with the OS, the watchdog timer is started, 2982 * and the stack is notified that the interface is ready. 2983 **/ 2984static int __igb_open(struct net_device *netdev, bool resuming) 2985{ 2986 struct igb_adapter *adapter = netdev_priv(netdev); 2987 struct e1000_hw *hw = &adapter->hw; 2988 struct pci_dev *pdev = adapter->pdev; 2989 int err; 2990 int i; 2991 2992 /* disallow open during test */ 2993 if (test_bit(__IGB_TESTING, &adapter->state)) { 2994 WARN_ON(resuming); 2995 return -EBUSY; 2996 } 2997 2998 if (!resuming) 2999 pm_runtime_get_sync(&pdev->dev); 3000 3001 netif_carrier_off(netdev); 3002 3003 /* allocate transmit descriptors */ 3004 err = igb_setup_all_tx_resources(adapter); 3005 if (err) 3006 goto err_setup_tx; 3007 3008 /* allocate receive descriptors */ 3009 err = igb_setup_all_rx_resources(adapter); 3010 if (err) 3011 goto err_setup_rx; 3012 3013 igb_power_up_link(adapter); 3014 3015 /* before we allocate an interrupt, we must be ready to handle it. 3016 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3017 * as soon as we call pci_request_irq, so we have to setup our 3018 * clean_rx handler before we do so. 3019 */ 3020 igb_configure(adapter); 3021 3022 err = igb_request_irq(adapter); 3023 if (err) 3024 goto err_req_irq; 3025 3026 /* Notify the stack of the actual queue counts. */ 3027 err = netif_set_real_num_tx_queues(adapter->netdev, 3028 adapter->num_tx_queues); 3029 if (err) 3030 goto err_set_queues; 3031 3032 err = netif_set_real_num_rx_queues(adapter->netdev, 3033 adapter->num_rx_queues); 3034 if (err) 3035 goto err_set_queues; 3036 3037 /* From here on the code is the same as igb_up() */ 3038 clear_bit(__IGB_DOWN, &adapter->state); 3039 3040 for (i = 0; i < adapter->num_q_vectors; i++) 3041 napi_enable(&(adapter->q_vector[i]->napi)); 3042 3043 /* Clear any pending interrupts. */ 3044 rd32(E1000_ICR); 3045 3046 igb_irq_enable(adapter); 3047 3048 /* notify VFs that reset has been completed */ 3049 if (adapter->vfs_allocated_count) { 3050 u32 reg_data = rd32(E1000_CTRL_EXT); 3051 reg_data |= E1000_CTRL_EXT_PFRSTD; 3052 wr32(E1000_CTRL_EXT, reg_data); 3053 } 3054 3055 netif_tx_start_all_queues(netdev); 3056 3057 if (!resuming) 3058 pm_runtime_put(&pdev->dev); 3059 3060 /* start the watchdog. */ 3061 hw->mac.get_link_status = 1; 3062 schedule_work(&adapter->watchdog_task); 3063 3064 return 0; 3065 3066err_set_queues: 3067 igb_free_irq(adapter); 3068err_req_irq: 3069 igb_release_hw_control(adapter); 3070 igb_power_down_link(adapter); 3071 igb_free_all_rx_resources(adapter); 3072err_setup_rx: 3073 igb_free_all_tx_resources(adapter); 3074err_setup_tx: 3075 igb_reset(adapter); 3076 if (!resuming) 3077 pm_runtime_put(&pdev->dev); 3078 3079 return err; 3080} 3081 3082static int igb_open(struct net_device *netdev) 3083{ 3084 return __igb_open(netdev, false); 3085} 3086 3087/** 3088 * igb_close - Disables a network interface 3089 * @netdev: network interface device structure 3090 * 3091 * Returns 0, this is not allowed to fail 3092 * 3093 * The close entry point is called when an interface is de-activated 3094 * by the OS. The hardware is still under the driver's control, but 3095 * needs to be disabled. A global MAC reset is issued to stop the 3096 * hardware, and all transmit and receive resources are freed. 3097 **/ 3098static int __igb_close(struct net_device *netdev, bool suspending) 3099{ 3100 struct igb_adapter *adapter = netdev_priv(netdev); 3101 struct pci_dev *pdev = adapter->pdev; 3102 3103 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3104 3105 if (!suspending) 3106 pm_runtime_get_sync(&pdev->dev); 3107 3108 igb_down(adapter); 3109 igb_free_irq(adapter); 3110 3111 igb_free_all_tx_resources(adapter); 3112 igb_free_all_rx_resources(adapter); 3113 3114 if (!suspending) 3115 pm_runtime_put_sync(&pdev->dev); 3116 return 0; 3117} 3118 3119static int igb_close(struct net_device *netdev) 3120{ 3121 return __igb_close(netdev, false); 3122} 3123 3124/** 3125 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3126 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3127 * 3128 * Return 0 on success, negative on failure 3129 **/ 3130int igb_setup_tx_resources(struct igb_ring *tx_ring) 3131{ 3132 struct device *dev = tx_ring->dev; 3133 int size; 3134 3135 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3136 3137 tx_ring->tx_buffer_info = vzalloc(size); 3138 if (!tx_ring->tx_buffer_info) 3139 goto err; 3140 3141 /* round up to nearest 4K */ 3142 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3143 tx_ring->size = ALIGN(tx_ring->size, 4096); 3144 3145 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3146 &tx_ring->dma, GFP_KERNEL); 3147 if (!tx_ring->desc) 3148 goto err; 3149 3150 tx_ring->next_to_use = 0; 3151 tx_ring->next_to_clean = 0; 3152 3153 return 0; 3154 3155err: 3156 vfree(tx_ring->tx_buffer_info); 3157 tx_ring->tx_buffer_info = NULL; 3158 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3159 return -ENOMEM; 3160} 3161 3162/** 3163 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3164 * (Descriptors) for all queues 3165 * @adapter: board private structure 3166 * 3167 * Return 0 on success, negative on failure 3168 **/ 3169static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3170{ 3171 struct pci_dev *pdev = adapter->pdev; 3172 int i, err = 0; 3173 3174 for (i = 0; i < adapter->num_tx_queues; i++) { 3175 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3176 if (err) { 3177 dev_err(&pdev->dev, 3178 "Allocation for Tx Queue %u failed\n", i); 3179 for (i--; i >= 0; i--) 3180 igb_free_tx_resources(adapter->tx_ring[i]); 3181 break; 3182 } 3183 } 3184 3185 return err; 3186} 3187 3188/** 3189 * igb_setup_tctl - configure the transmit control registers 3190 * @adapter: Board private structure 3191 **/ 3192void igb_setup_tctl(struct igb_adapter *adapter) 3193{ 3194 struct e1000_hw *hw = &adapter->hw; 3195 u32 tctl; 3196 3197 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3198 wr32(E1000_TXDCTL(0), 0); 3199 3200 /* Program the Transmit Control Register */ 3201 tctl = rd32(E1000_TCTL); 3202 tctl &= ~E1000_TCTL_CT; 3203 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3204 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3205 3206 igb_config_collision_dist(hw); 3207 3208 /* Enable transmits */ 3209 tctl |= E1000_TCTL_EN; 3210 3211 wr32(E1000_TCTL, tctl); 3212} 3213 3214/** 3215 * igb_configure_tx_ring - Configure transmit ring after Reset 3216 * @adapter: board private structure 3217 * @ring: tx ring to configure 3218 * 3219 * Configure a transmit ring after a reset. 3220 **/ 3221void igb_configure_tx_ring(struct igb_adapter *adapter, 3222 struct igb_ring *ring) 3223{ 3224 struct e1000_hw *hw = &adapter->hw; 3225 u32 txdctl = 0; 3226 u64 tdba = ring->dma; 3227 int reg_idx = ring->reg_idx; 3228 3229 /* disable the queue */ 3230 wr32(E1000_TXDCTL(reg_idx), 0); 3231 wrfl(); 3232 mdelay(10); 3233 3234 wr32(E1000_TDLEN(reg_idx), 3235 ring->count * sizeof(union e1000_adv_tx_desc)); 3236 wr32(E1000_TDBAL(reg_idx), 3237 tdba & 0x00000000ffffffffULL); 3238 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3239 3240 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 3241 wr32(E1000_TDH(reg_idx), 0); 3242 writel(0, ring->tail); 3243 3244 txdctl |= IGB_TX_PTHRESH; 3245 txdctl |= IGB_TX_HTHRESH << 8; 3246 txdctl |= IGB_TX_WTHRESH << 16; 3247 3248 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3249 wr32(E1000_TXDCTL(reg_idx), txdctl); 3250} 3251 3252/** 3253 * igb_configure_tx - Configure transmit Unit after Reset 3254 * @adapter: board private structure 3255 * 3256 * Configure the Tx unit of the MAC after a reset. 3257 **/ 3258static void igb_configure_tx(struct igb_adapter *adapter) 3259{ 3260 int i; 3261 3262 for (i = 0; i < adapter->num_tx_queues; i++) 3263 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3264} 3265 3266/** 3267 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3268 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3269 * 3270 * Returns 0 on success, negative on failure 3271 **/ 3272int igb_setup_rx_resources(struct igb_ring *rx_ring) 3273{ 3274 struct device *dev = rx_ring->dev; 3275 int size; 3276 3277 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3278 3279 rx_ring->rx_buffer_info = vzalloc(size); 3280 if (!rx_ring->rx_buffer_info) 3281 goto err; 3282 3283 /* Round up to nearest 4K */ 3284 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3285 rx_ring->size = ALIGN(rx_ring->size, 4096); 3286 3287 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3288 &rx_ring->dma, GFP_KERNEL); 3289 if (!rx_ring->desc) 3290 goto err; 3291 3292 rx_ring->next_to_alloc = 0; 3293 rx_ring->next_to_clean = 0; 3294 rx_ring->next_to_use = 0; 3295 3296 return 0; 3297 3298err: 3299 vfree(rx_ring->rx_buffer_info); 3300 rx_ring->rx_buffer_info = NULL; 3301 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3302 return -ENOMEM; 3303} 3304 3305/** 3306 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3307 * (Descriptors) for all queues 3308 * @adapter: board private structure 3309 * 3310 * Return 0 on success, negative on failure 3311 **/ 3312static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3313{ 3314 struct pci_dev *pdev = adapter->pdev; 3315 int i, err = 0; 3316 3317 for (i = 0; i < adapter->num_rx_queues; i++) { 3318 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3319 if (err) { 3320 dev_err(&pdev->dev, 3321 "Allocation for Rx Queue %u failed\n", i); 3322 for (i--; i >= 0; i--) 3323 igb_free_rx_resources(adapter->rx_ring[i]); 3324 break; 3325 } 3326 } 3327 3328 return err; 3329} 3330 3331/** 3332 * igb_setup_mrqc - configure the multiple receive queue control registers 3333 * @adapter: Board private structure 3334 **/ 3335static void igb_setup_mrqc(struct igb_adapter *adapter) 3336{ 3337 struct e1000_hw *hw = &adapter->hw; 3338 u32 mrqc, rxcsum; 3339 u32 j, num_rx_queues; 3340 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, 3341 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, 3342 0xA32DCB77, 0x0CF23080, 0x3BB7426A, 3343 0xFA01ACBE }; 3344 3345 /* Fill out hash function seeds */ 3346 for (j = 0; j < 10; j++) 3347 wr32(E1000_RSSRK(j), rsskey[j]); 3348 3349 num_rx_queues = adapter->rss_queues; 3350 3351 switch (hw->mac.type) { 3352 case e1000_82576: 3353 /* 82576 supports 2 RSS queues for SR-IOV */ 3354 if (adapter->vfs_allocated_count) 3355 num_rx_queues = 2; 3356 break; 3357 default: 3358 break; 3359 } 3360 3361 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3362 for (j = 0; j < IGB_RETA_SIZE; j++) 3363 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE; 3364 adapter->rss_indir_tbl_init = num_rx_queues; 3365 } 3366 igb_write_rss_indir_tbl(adapter); 3367 3368 /* Disable raw packet checksumming so that RSS hash is placed in 3369 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3370 * offloads as they are enabled by default 3371 */ 3372 rxcsum = rd32(E1000_RXCSUM); 3373 rxcsum |= E1000_RXCSUM_PCSD; 3374 3375 if (adapter->hw.mac.type >= e1000_82576) 3376 /* Enable Receive Checksum Offload for SCTP */ 3377 rxcsum |= E1000_RXCSUM_CRCOFL; 3378 3379 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3380 wr32(E1000_RXCSUM, rxcsum); 3381 3382 /* Generate RSS hash based on packet types, TCP/UDP 3383 * port numbers and/or IPv4/v6 src and dst addresses 3384 */ 3385 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3386 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3387 E1000_MRQC_RSS_FIELD_IPV6 | 3388 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3389 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3390 3391 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3392 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3393 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3394 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3395 3396 /* If VMDq is enabled then we set the appropriate mode for that, else 3397 * we default to RSS so that an RSS hash is calculated per packet even 3398 * if we are only using one queue 3399 */ 3400 if (adapter->vfs_allocated_count) { 3401 if (hw->mac.type > e1000_82575) { 3402 /* Set the default pool for the PF's first queue */ 3403 u32 vtctl = rd32(E1000_VT_CTL); 3404 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3405 E1000_VT_CTL_DISABLE_DEF_POOL); 3406 vtctl |= adapter->vfs_allocated_count << 3407 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3408 wr32(E1000_VT_CTL, vtctl); 3409 } 3410 if (adapter->rss_queues > 1) 3411 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 3412 else 3413 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3414 } else { 3415 if (hw->mac.type != e1000_i211) 3416 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 3417 } 3418 igb_vmm_control(adapter); 3419 3420 wr32(E1000_MRQC, mrqc); 3421} 3422 3423/** 3424 * igb_setup_rctl - configure the receive control registers 3425 * @adapter: Board private structure 3426 **/ 3427void igb_setup_rctl(struct igb_adapter *adapter) 3428{ 3429 struct e1000_hw *hw = &adapter->hw; 3430 u32 rctl; 3431 3432 rctl = rd32(E1000_RCTL); 3433 3434 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3435 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3436 3437 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3438 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3439 3440 /* enable stripping of CRC. It's unlikely this will break BMC 3441 * redirection as it did with e1000. Newer features require 3442 * that the HW strips the CRC. 3443 */ 3444 rctl |= E1000_RCTL_SECRC; 3445 3446 /* disable store bad packets and clear size bits. */ 3447 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3448 3449 /* enable LPE to prevent packets larger than max_frame_size */ 3450 rctl |= E1000_RCTL_LPE; 3451 3452 /* disable queue 0 to prevent tail write w/o re-config */ 3453 wr32(E1000_RXDCTL(0), 0); 3454 3455 /* Attention!!! For SR-IOV PF driver operations you must enable 3456 * queue drop for all VF and PF queues to prevent head of line blocking 3457 * if an un-trusted VF does not provide descriptors to hardware. 3458 */ 3459 if (adapter->vfs_allocated_count) { 3460 /* set all queue drop enable bits */ 3461 wr32(E1000_QDE, ALL_QUEUES); 3462 } 3463 3464 /* This is useful for sniffing bad packets. */ 3465 if (adapter->netdev->features & NETIF_F_RXALL) { 3466 /* UPE and MPE will be handled by normal PROMISC logic 3467 * in e1000e_set_rx_mode 3468 */ 3469 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3470 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3471 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3472 3473 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3474 E1000_RCTL_DPF | /* Allow filtered pause */ 3475 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3476 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3477 * and that breaks VLANs. 3478 */ 3479 } 3480 3481 wr32(E1000_RCTL, rctl); 3482} 3483 3484static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3485 int vfn) 3486{ 3487 struct e1000_hw *hw = &adapter->hw; 3488 u32 vmolr; 3489 3490 /* if it isn't the PF check to see if VFs are enabled and 3491 * increase the size to support vlan tags 3492 */ 3493 if (vfn < adapter->vfs_allocated_count && 3494 adapter->vf_data[vfn].vlans_enabled) 3495 size += VLAN_TAG_SIZE; 3496 3497 vmolr = rd32(E1000_VMOLR(vfn)); 3498 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3499 vmolr |= size | E1000_VMOLR_LPE; 3500 wr32(E1000_VMOLR(vfn), vmolr); 3501 3502 return 0; 3503} 3504 3505/** 3506 * igb_rlpml_set - set maximum receive packet size 3507 * @adapter: board private structure 3508 * 3509 * Configure maximum receivable packet size. 3510 **/ 3511static void igb_rlpml_set(struct igb_adapter *adapter) 3512{ 3513 u32 max_frame_size = adapter->max_frame_size; 3514 struct e1000_hw *hw = &adapter->hw; 3515 u16 pf_id = adapter->vfs_allocated_count; 3516 3517 if (pf_id) { 3518 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3519 /* If we're in VMDQ or SR-IOV mode, then set global RLPML 3520 * to our max jumbo frame size, in case we need to enable 3521 * jumbo frames on one of the rings later. 3522 * This will not pass over-length frames into the default 3523 * queue because it's gated by the VMOLR.RLPML. 3524 */ 3525 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3526 } 3527 3528 wr32(E1000_RLPML, max_frame_size); 3529} 3530 3531static inline void igb_set_vmolr(struct igb_adapter *adapter, 3532 int vfn, bool aupe) 3533{ 3534 struct e1000_hw *hw = &adapter->hw; 3535 u32 vmolr; 3536 3537 /* This register exists only on 82576 and newer so if we are older then 3538 * we should exit and do nothing 3539 */ 3540 if (hw->mac.type < e1000_82576) 3541 return; 3542 3543 vmolr = rd32(E1000_VMOLR(vfn)); 3544 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3545 if (aupe) 3546 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3547 else 3548 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3549 3550 /* clear all bits that might not be set */ 3551 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3552 3553 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3554 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3555 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3556 * multicast packets 3557 */ 3558 if (vfn <= adapter->vfs_allocated_count) 3559 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3560 3561 wr32(E1000_VMOLR(vfn), vmolr); 3562} 3563 3564/** 3565 * igb_configure_rx_ring - Configure a receive ring after Reset 3566 * @adapter: board private structure 3567 * @ring: receive ring to be configured 3568 * 3569 * Configure the Rx unit of the MAC after a reset. 3570 **/ 3571void igb_configure_rx_ring(struct igb_adapter *adapter, 3572 struct igb_ring *ring) 3573{ 3574 struct e1000_hw *hw = &adapter->hw; 3575 u64 rdba = ring->dma; 3576 int reg_idx = ring->reg_idx; 3577 u32 srrctl = 0, rxdctl = 0; 3578 3579 /* disable the queue */ 3580 wr32(E1000_RXDCTL(reg_idx), 0); 3581 3582 /* Set DMA base address registers */ 3583 wr32(E1000_RDBAL(reg_idx), 3584 rdba & 0x00000000ffffffffULL); 3585 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3586 wr32(E1000_RDLEN(reg_idx), 3587 ring->count * sizeof(union e1000_adv_rx_desc)); 3588 3589 /* initialize head and tail */ 3590 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3591 wr32(E1000_RDH(reg_idx), 0); 3592 writel(0, ring->tail); 3593 3594 /* set descriptor configuration */ 3595 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3596 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3597 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3598 if (hw->mac.type >= e1000_82580) 3599 srrctl |= E1000_SRRCTL_TIMESTAMP; 3600 /* Only set Drop Enable if we are supporting multiple queues */ 3601 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3602 srrctl |= E1000_SRRCTL_DROP_EN; 3603 3604 wr32(E1000_SRRCTL(reg_idx), srrctl); 3605 3606 /* set filtering for VMDQ pools */ 3607 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3608 3609 rxdctl |= IGB_RX_PTHRESH; 3610 rxdctl |= IGB_RX_HTHRESH << 8; 3611 rxdctl |= IGB_RX_WTHRESH << 16; 3612 3613 /* enable receive descriptor fetching */ 3614 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3615 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3616} 3617 3618/** 3619 * igb_configure_rx - Configure receive Unit after Reset 3620 * @adapter: board private structure 3621 * 3622 * Configure the Rx unit of the MAC after a reset. 3623 **/ 3624static void igb_configure_rx(struct igb_adapter *adapter) 3625{ 3626 int i; 3627 3628 /* set UTA to appropriate mode */ 3629 igb_set_uta(adapter); 3630 3631 /* set the correct pool for the PF default MAC address in entry 0 */ 3632 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3633 adapter->vfs_allocated_count); 3634 3635 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3636 * the Base and Length of the Rx Descriptor Ring 3637 */ 3638 for (i = 0; i < adapter->num_rx_queues; i++) 3639 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3640} 3641 3642/** 3643 * igb_free_tx_resources - Free Tx Resources per Queue 3644 * @tx_ring: Tx descriptor ring for a specific queue 3645 * 3646 * Free all transmit software resources 3647 **/ 3648void igb_free_tx_resources(struct igb_ring *tx_ring) 3649{ 3650 igb_clean_tx_ring(tx_ring); 3651 3652 vfree(tx_ring->tx_buffer_info); 3653 tx_ring->tx_buffer_info = NULL; 3654 3655 /* if not set, then don't free */ 3656 if (!tx_ring->desc) 3657 return; 3658 3659 dma_free_coherent(tx_ring->dev, tx_ring->size, 3660 tx_ring->desc, tx_ring->dma); 3661 3662 tx_ring->desc = NULL; 3663} 3664 3665/** 3666 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3667 * @adapter: board private structure 3668 * 3669 * Free all transmit software resources 3670 **/ 3671static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3672{ 3673 int i; 3674 3675 for (i = 0; i < adapter->num_tx_queues; i++) 3676 igb_free_tx_resources(adapter->tx_ring[i]); 3677} 3678 3679void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3680 struct igb_tx_buffer *tx_buffer) 3681{ 3682 if (tx_buffer->skb) { 3683 dev_kfree_skb_any(tx_buffer->skb); 3684 if (dma_unmap_len(tx_buffer, len)) 3685 dma_unmap_single(ring->dev, 3686 dma_unmap_addr(tx_buffer, dma), 3687 dma_unmap_len(tx_buffer, len), 3688 DMA_TO_DEVICE); 3689 } else if (dma_unmap_len(tx_buffer, len)) { 3690 dma_unmap_page(ring->dev, 3691 dma_unmap_addr(tx_buffer, dma), 3692 dma_unmap_len(tx_buffer, len), 3693 DMA_TO_DEVICE); 3694 } 3695 tx_buffer->next_to_watch = NULL; 3696 tx_buffer->skb = NULL; 3697 dma_unmap_len_set(tx_buffer, len, 0); 3698 /* buffer_info must be completely set up in the transmit path */ 3699} 3700 3701/** 3702 * igb_clean_tx_ring - Free Tx Buffers 3703 * @tx_ring: ring to be cleaned 3704 **/ 3705static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3706{ 3707 struct igb_tx_buffer *buffer_info; 3708 unsigned long size; 3709 u16 i; 3710 3711 if (!tx_ring->tx_buffer_info) 3712 return; 3713 /* Free all the Tx ring sk_buffs */ 3714 3715 for (i = 0; i < tx_ring->count; i++) { 3716 buffer_info = &tx_ring->tx_buffer_info[i]; 3717 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3718 } 3719 3720 netdev_tx_reset_queue(txring_txq(tx_ring)); 3721 3722 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3723 memset(tx_ring->tx_buffer_info, 0, size); 3724 3725 /* Zero out the descriptor ring */ 3726 memset(tx_ring->desc, 0, tx_ring->size); 3727 3728 tx_ring->next_to_use = 0; 3729 tx_ring->next_to_clean = 0; 3730} 3731 3732/** 3733 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3734 * @adapter: board private structure 3735 **/ 3736static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3737{ 3738 int i; 3739 3740 for (i = 0; i < adapter->num_tx_queues; i++) 3741 igb_clean_tx_ring(adapter->tx_ring[i]); 3742} 3743 3744/** 3745 * igb_free_rx_resources - Free Rx Resources 3746 * @rx_ring: ring to clean the resources from 3747 * 3748 * Free all receive software resources 3749 **/ 3750void igb_free_rx_resources(struct igb_ring *rx_ring) 3751{ 3752 igb_clean_rx_ring(rx_ring); 3753 3754 vfree(rx_ring->rx_buffer_info); 3755 rx_ring->rx_buffer_info = NULL; 3756 3757 /* if not set, then don't free */ 3758 if (!rx_ring->desc) 3759 return; 3760 3761 dma_free_coherent(rx_ring->dev, rx_ring->size, 3762 rx_ring->desc, rx_ring->dma); 3763 3764 rx_ring->desc = NULL; 3765} 3766 3767/** 3768 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3769 * @adapter: board private structure 3770 * 3771 * Free all receive software resources 3772 **/ 3773static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3774{ 3775 int i; 3776 3777 for (i = 0; i < adapter->num_rx_queues; i++) 3778 igb_free_rx_resources(adapter->rx_ring[i]); 3779} 3780 3781/** 3782 * igb_clean_rx_ring - Free Rx Buffers per Queue 3783 * @rx_ring: ring to free buffers from 3784 **/ 3785static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3786{ 3787 unsigned long size; 3788 u16 i; 3789 3790 if (rx_ring->skb) 3791 dev_kfree_skb(rx_ring->skb); 3792 rx_ring->skb = NULL; 3793 3794 if (!rx_ring->rx_buffer_info) 3795 return; 3796 3797 /* Free all the Rx ring sk_buffs */ 3798 for (i = 0; i < rx_ring->count; i++) { 3799 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3800 3801 if (!buffer_info->page) 3802 continue; 3803 3804 dma_unmap_page(rx_ring->dev, 3805 buffer_info->dma, 3806 PAGE_SIZE, 3807 DMA_FROM_DEVICE); 3808 __free_page(buffer_info->page); 3809 3810 buffer_info->page = NULL; 3811 } 3812 3813 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3814 memset(rx_ring->rx_buffer_info, 0, size); 3815 3816 /* Zero out the descriptor ring */ 3817 memset(rx_ring->desc, 0, rx_ring->size); 3818 3819 rx_ring->next_to_alloc = 0; 3820 rx_ring->next_to_clean = 0; 3821 rx_ring->next_to_use = 0; 3822} 3823 3824/** 3825 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3826 * @adapter: board private structure 3827 **/ 3828static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3829{ 3830 int i; 3831 3832 for (i = 0; i < adapter->num_rx_queues; i++) 3833 igb_clean_rx_ring(adapter->rx_ring[i]); 3834} 3835 3836/** 3837 * igb_set_mac - Change the Ethernet Address of the NIC 3838 * @netdev: network interface device structure 3839 * @p: pointer to an address structure 3840 * 3841 * Returns 0 on success, negative on failure 3842 **/ 3843static int igb_set_mac(struct net_device *netdev, void *p) 3844{ 3845 struct igb_adapter *adapter = netdev_priv(netdev); 3846 struct e1000_hw *hw = &adapter->hw; 3847 struct sockaddr *addr = p; 3848 3849 if (!is_valid_ether_addr(addr->sa_data)) 3850 return -EADDRNOTAVAIL; 3851 3852 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3853 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3854 3855 /* set the correct pool for the new PF MAC address in entry 0 */ 3856 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3857 adapter->vfs_allocated_count); 3858 3859 return 0; 3860} 3861 3862/** 3863 * igb_write_mc_addr_list - write multicast addresses to MTA 3864 * @netdev: network interface device structure 3865 * 3866 * Writes multicast address list to the MTA hash table. 3867 * Returns: -ENOMEM on failure 3868 * 0 on no addresses written 3869 * X on writing X addresses to MTA 3870 **/ 3871static int igb_write_mc_addr_list(struct net_device *netdev) 3872{ 3873 struct igb_adapter *adapter = netdev_priv(netdev); 3874 struct e1000_hw *hw = &adapter->hw; 3875 struct netdev_hw_addr *ha; 3876 u8 *mta_list; 3877 int i; 3878 3879 if (netdev_mc_empty(netdev)) { 3880 /* nothing to program, so clear mc list */ 3881 igb_update_mc_addr_list(hw, NULL, 0); 3882 igb_restore_vf_multicasts(adapter); 3883 return 0; 3884 } 3885 3886 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3887 if (!mta_list) 3888 return -ENOMEM; 3889 3890 /* The shared function expects a packed array of only addresses. */ 3891 i = 0; 3892 netdev_for_each_mc_addr(ha, netdev) 3893 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3894 3895 igb_update_mc_addr_list(hw, mta_list, i); 3896 kfree(mta_list); 3897 3898 return netdev_mc_count(netdev); 3899} 3900 3901/** 3902 * igb_write_uc_addr_list - write unicast addresses to RAR table 3903 * @netdev: network interface device structure 3904 * 3905 * Writes unicast address list to the RAR table. 3906 * Returns: -ENOMEM on failure/insufficient address space 3907 * 0 on no addresses written 3908 * X on writing X addresses to the RAR table 3909 **/ 3910static int igb_write_uc_addr_list(struct net_device *netdev) 3911{ 3912 struct igb_adapter *adapter = netdev_priv(netdev); 3913 struct e1000_hw *hw = &adapter->hw; 3914 unsigned int vfn = adapter->vfs_allocated_count; 3915 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3916 int count = 0; 3917 3918 /* return ENOMEM indicating insufficient memory for addresses */ 3919 if (netdev_uc_count(netdev) > rar_entries) 3920 return -ENOMEM; 3921 3922 if (!netdev_uc_empty(netdev) && rar_entries) { 3923 struct netdev_hw_addr *ha; 3924 3925 netdev_for_each_uc_addr(ha, netdev) { 3926 if (!rar_entries) 3927 break; 3928 igb_rar_set_qsel(adapter, ha->addr, 3929 rar_entries--, 3930 vfn); 3931 count++; 3932 } 3933 } 3934 /* write the addresses in reverse order to avoid write combining */ 3935 for (; rar_entries > 0 ; rar_entries--) { 3936 wr32(E1000_RAH(rar_entries), 0); 3937 wr32(E1000_RAL(rar_entries), 0); 3938 } 3939 wrfl(); 3940 3941 return count; 3942} 3943 3944/** 3945 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3946 * @netdev: network interface device structure 3947 * 3948 * The set_rx_mode entry point is called whenever the unicast or multicast 3949 * address lists or the network interface flags are updated. This routine is 3950 * responsible for configuring the hardware for proper unicast, multicast, 3951 * promiscuous mode, and all-multi behavior. 3952 **/ 3953static void igb_set_rx_mode(struct net_device *netdev) 3954{ 3955 struct igb_adapter *adapter = netdev_priv(netdev); 3956 struct e1000_hw *hw = &adapter->hw; 3957 unsigned int vfn = adapter->vfs_allocated_count; 3958 u32 rctl, vmolr = 0; 3959 int count; 3960 3961 /* Check for Promiscuous and All Multicast modes */ 3962 rctl = rd32(E1000_RCTL); 3963 3964 /* clear the effected bits */ 3965 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 3966 3967 if (netdev->flags & IFF_PROMISC) { 3968 /* retain VLAN HW filtering if in VT mode */ 3969 if (adapter->vfs_allocated_count) 3970 rctl |= E1000_RCTL_VFE; 3971 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3972 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 3973 } else { 3974 if (netdev->flags & IFF_ALLMULTI) { 3975 rctl |= E1000_RCTL_MPE; 3976 vmolr |= E1000_VMOLR_MPME; 3977 } else { 3978 /* Write addresses to the MTA, if the attempt fails 3979 * then we should just turn on promiscuous mode so 3980 * that we can at least receive multicast traffic 3981 */ 3982 count = igb_write_mc_addr_list(netdev); 3983 if (count < 0) { 3984 rctl |= E1000_RCTL_MPE; 3985 vmolr |= E1000_VMOLR_MPME; 3986 } else if (count) { 3987 vmolr |= E1000_VMOLR_ROMPE; 3988 } 3989 } 3990 /* Write addresses to available RAR registers, if there is not 3991 * sufficient space to store all the addresses then enable 3992 * unicast promiscuous mode 3993 */ 3994 count = igb_write_uc_addr_list(netdev); 3995 if (count < 0) { 3996 rctl |= E1000_RCTL_UPE; 3997 vmolr |= E1000_VMOLR_ROPE; 3998 } 3999 rctl |= E1000_RCTL_VFE; 4000 } 4001 wr32(E1000_RCTL, rctl); 4002 4003 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4004 * the VMOLR to enable the appropriate modes. Without this workaround 4005 * we will have issues with VLAN tag stripping not being done for frames 4006 * that are only arriving because we are the default pool 4007 */ 4008 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4009 return; 4010 4011 vmolr |= rd32(E1000_VMOLR(vfn)) & 4012 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4013 wr32(E1000_VMOLR(vfn), vmolr); 4014 igb_restore_vf_multicasts(adapter); 4015} 4016 4017static void igb_check_wvbr(struct igb_adapter *adapter) 4018{ 4019 struct e1000_hw *hw = &adapter->hw; 4020 u32 wvbr = 0; 4021 4022 switch (hw->mac.type) { 4023 case e1000_82576: 4024 case e1000_i350: 4025 if (!(wvbr = rd32(E1000_WVBR))) 4026 return; 4027 break; 4028 default: 4029 break; 4030 } 4031 4032 adapter->wvbr |= wvbr; 4033} 4034 4035#define IGB_STAGGERED_QUEUE_OFFSET 8 4036 4037static void igb_spoof_check(struct igb_adapter *adapter) 4038{ 4039 int j; 4040 4041 if (!adapter->wvbr) 4042 return; 4043 4044 for(j = 0; j < adapter->vfs_allocated_count; j++) { 4045 if (adapter->wvbr & (1 << j) || 4046 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 4047 dev_warn(&adapter->pdev->dev, 4048 "Spoof event(s) detected on VF %d\n", j); 4049 adapter->wvbr &= 4050 ~((1 << j) | 4051 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 4052 } 4053 } 4054} 4055 4056/* Need to wait a few seconds after link up to get diagnostic information from 4057 * the phy 4058 */ 4059static void igb_update_phy_info(unsigned long data) 4060{ 4061 struct igb_adapter *adapter = (struct igb_adapter *) data; 4062 igb_get_phy_info(&adapter->hw); 4063} 4064 4065/** 4066 * igb_has_link - check shared code for link and determine up/down 4067 * @adapter: pointer to driver private info 4068 **/ 4069bool igb_has_link(struct igb_adapter *adapter) 4070{ 4071 struct e1000_hw *hw = &adapter->hw; 4072 bool link_active = false; 4073 4074 /* get_link_status is set on LSC (link status) interrupt or 4075 * rx sequence error interrupt. get_link_status will stay 4076 * false until the e1000_check_for_link establishes link 4077 * for copper adapters ONLY 4078 */ 4079 switch (hw->phy.media_type) { 4080 case e1000_media_type_copper: 4081 if (!hw->mac.get_link_status) 4082 return true; 4083 case e1000_media_type_internal_serdes: 4084 hw->mac.ops.check_for_link(hw); 4085 link_active = !hw->mac.get_link_status; 4086 break; 4087 default: 4088 case e1000_media_type_unknown: 4089 break; 4090 } 4091 4092 if (((hw->mac.type == e1000_i210) || 4093 (hw->mac.type == e1000_i211)) && 4094 (hw->phy.id == I210_I_PHY_ID)) { 4095 if (!netif_carrier_ok(adapter->netdev)) { 4096 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4097 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4098 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4099 adapter->link_check_timeout = jiffies; 4100 } 4101 } 4102 4103 return link_active; 4104} 4105 4106static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4107{ 4108 bool ret = false; 4109 u32 ctrl_ext, thstat; 4110 4111 /* check for thermal sensor event on i350 copper only */ 4112 if (hw->mac.type == e1000_i350) { 4113 thstat = rd32(E1000_THSTAT); 4114 ctrl_ext = rd32(E1000_CTRL_EXT); 4115 4116 if ((hw->phy.media_type == e1000_media_type_copper) && 4117 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4118 ret = !!(thstat & event); 4119 } 4120 4121 return ret; 4122} 4123 4124/** 4125 * igb_watchdog - Timer Call-back 4126 * @data: pointer to adapter cast into an unsigned long 4127 **/ 4128static void igb_watchdog(unsigned long data) 4129{ 4130 struct igb_adapter *adapter = (struct igb_adapter *)data; 4131 /* Do the rest outside of interrupt context */ 4132 schedule_work(&adapter->watchdog_task); 4133} 4134 4135static void igb_watchdog_task(struct work_struct *work) 4136{ 4137 struct igb_adapter *adapter = container_of(work, 4138 struct igb_adapter, 4139 watchdog_task); 4140 struct e1000_hw *hw = &adapter->hw; 4141 struct e1000_phy_info *phy = &hw->phy; 4142 struct net_device *netdev = adapter->netdev; 4143 u32 link; 4144 int i; 4145 u32 connsw; 4146 4147 link = igb_has_link(adapter); 4148 4149 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4150 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4151 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4152 else 4153 link = false; 4154 } 4155 4156 /* Force link down if we have fiber to swap to */ 4157 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4158 if (hw->phy.media_type == e1000_media_type_copper) { 4159 connsw = rd32(E1000_CONNSW); 4160 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4161 link = 0; 4162 } 4163 } 4164 if (link) { 4165 /* Perform a reset if the media type changed. */ 4166 if (hw->dev_spec._82575.media_changed) { 4167 hw->dev_spec._82575.media_changed = false; 4168 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4169 igb_reset(adapter); 4170 } 4171 /* Cancel scheduled suspend requests. */ 4172 pm_runtime_resume(netdev->dev.parent); 4173 4174 if (!netif_carrier_ok(netdev)) { 4175 u32 ctrl; 4176 hw->mac.ops.get_speed_and_duplex(hw, 4177 &adapter->link_speed, 4178 &adapter->link_duplex); 4179 4180 ctrl = rd32(E1000_CTRL); 4181 /* Links status message must follow this format */ 4182 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s " 4183 "Duplex, Flow Control: %s\n", 4184 netdev->name, 4185 adapter->link_speed, 4186 adapter->link_duplex == FULL_DUPLEX ? 4187 "Full" : "Half", 4188 (ctrl & E1000_CTRL_TFCE) && 4189 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4190 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4191 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4192 4193 /* disable EEE if enabled */ 4194 if ((adapter->flags & IGB_FLAG_EEE) && 4195 (adapter->link_duplex == HALF_DUPLEX)) { 4196 dev_info(&adapter->pdev->dev, 4197 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4198 adapter->hw.dev_spec._82575.eee_disable = true; 4199 adapter->flags &= ~IGB_FLAG_EEE; 4200 } 4201 4202 /* check if SmartSpeed worked */ 4203 igb_check_downshift(hw); 4204 if (phy->speed_downgraded) 4205 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4206 4207 /* check for thermal sensor event */ 4208 if (igb_thermal_sensor_event(hw, 4209 E1000_THSTAT_LINK_THROTTLE)) { 4210 netdev_info(netdev, "The network adapter link " 4211 "speed was downshifted because it " 4212 "overheated\n"); 4213 } 4214 4215 /* adjust timeout factor according to speed/duplex */ 4216 adapter->tx_timeout_factor = 1; 4217 switch (adapter->link_speed) { 4218 case SPEED_10: 4219 adapter->tx_timeout_factor = 14; 4220 break; 4221 case SPEED_100: 4222 /* maybe add some timeout factor ? */ 4223 break; 4224 } 4225 4226 netif_carrier_on(netdev); 4227 4228 igb_ping_all_vfs(adapter); 4229 igb_check_vf_rate_limit(adapter); 4230 4231 /* link state has changed, schedule phy info update */ 4232 if (!test_bit(__IGB_DOWN, &adapter->state)) 4233 mod_timer(&adapter->phy_info_timer, 4234 round_jiffies(jiffies + 2 * HZ)); 4235 } 4236 } else { 4237 if (netif_carrier_ok(netdev)) { 4238 adapter->link_speed = 0; 4239 adapter->link_duplex = 0; 4240 4241 /* check for thermal sensor event */ 4242 if (igb_thermal_sensor_event(hw, 4243 E1000_THSTAT_PWR_DOWN)) { 4244 netdev_err(netdev, "The network adapter was " 4245 "stopped because it overheated\n"); 4246 } 4247 4248 /* Links status message must follow this format */ 4249 printk(KERN_INFO "igb: %s NIC Link is Down\n", 4250 netdev->name); 4251 netif_carrier_off(netdev); 4252 4253 igb_ping_all_vfs(adapter); 4254 4255 /* link state has changed, schedule phy info update */ 4256 if (!test_bit(__IGB_DOWN, &adapter->state)) 4257 mod_timer(&adapter->phy_info_timer, 4258 round_jiffies(jiffies + 2 * HZ)); 4259 4260 /* link is down, time to check for alternate media */ 4261 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4262 igb_check_swap_media(adapter); 4263 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4264 schedule_work(&adapter->reset_task); 4265 /* return immediately */ 4266 return; 4267 } 4268 } 4269 pm_schedule_suspend(netdev->dev.parent, 4270 MSEC_PER_SEC * 5); 4271 4272 /* also check for alternate media here */ 4273 } else if (!netif_carrier_ok(netdev) && 4274 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4275 igb_check_swap_media(adapter); 4276 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4277 schedule_work(&adapter->reset_task); 4278 /* return immediately */ 4279 return; 4280 } 4281 } 4282 } 4283 4284 spin_lock(&adapter->stats64_lock); 4285 igb_update_stats(adapter, &adapter->stats64); 4286 spin_unlock(&adapter->stats64_lock); 4287 4288 for (i = 0; i < adapter->num_tx_queues; i++) { 4289 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4290 if (!netif_carrier_ok(netdev)) { 4291 /* We've lost link, so the controller stops DMA, 4292 * but we've got queued Tx work that's never going 4293 * to get done, so reset controller to flush Tx. 4294 * (Do the reset outside of interrupt context). 4295 */ 4296 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4297 adapter->tx_timeout_count++; 4298 schedule_work(&adapter->reset_task); 4299 /* return immediately since reset is imminent */ 4300 return; 4301 } 4302 } 4303 4304 /* Force detection of hung controller every watchdog period */ 4305 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4306 } 4307 4308 /* Cause software interrupt to ensure Rx ring is cleaned */ 4309 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4310 u32 eics = 0; 4311 for (i = 0; i < adapter->num_q_vectors; i++) 4312 eics |= adapter->q_vector[i]->eims_value; 4313 wr32(E1000_EICS, eics); 4314 } else { 4315 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4316 } 4317 4318 igb_spoof_check(adapter); 4319 igb_ptp_rx_hang(adapter); 4320 4321 /* Reset the timer */ 4322 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4323 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4324 mod_timer(&adapter->watchdog_timer, 4325 round_jiffies(jiffies + HZ)); 4326 else 4327 mod_timer(&adapter->watchdog_timer, 4328 round_jiffies(jiffies + 2 * HZ)); 4329 } 4330} 4331 4332enum latency_range { 4333 lowest_latency = 0, 4334 low_latency = 1, 4335 bulk_latency = 2, 4336 latency_invalid = 255 4337}; 4338 4339/** 4340 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4341 * @q_vector: pointer to q_vector 4342 * 4343 * Stores a new ITR value based on strictly on packet size. This 4344 * algorithm is less sophisticated than that used in igb_update_itr, 4345 * due to the difficulty of synchronizing statistics across multiple 4346 * receive rings. The divisors and thresholds used by this function 4347 * were determined based on theoretical maximum wire speed and testing 4348 * data, in order to minimize response time while increasing bulk 4349 * throughput. 4350 * This functionality is controlled by the InterruptThrottleRate module 4351 * parameter (see igb_param.c) 4352 * NOTE: This function is called only when operating in a multiqueue 4353 * receive environment. 4354 **/ 4355static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4356{ 4357 int new_val = q_vector->itr_val; 4358 int avg_wire_size = 0; 4359 struct igb_adapter *adapter = q_vector->adapter; 4360 unsigned int packets; 4361 4362 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4363 * ints/sec - ITR timer value of 120 ticks. 4364 */ 4365 if (adapter->link_speed != SPEED_1000) { 4366 new_val = IGB_4K_ITR; 4367 goto set_itr_val; 4368 } 4369 4370 packets = q_vector->rx.total_packets; 4371 if (packets) 4372 avg_wire_size = q_vector->rx.total_bytes / packets; 4373 4374 packets = q_vector->tx.total_packets; 4375 if (packets) 4376 avg_wire_size = max_t(u32, avg_wire_size, 4377 q_vector->tx.total_bytes / packets); 4378 4379 /* if avg_wire_size isn't set no work was done */ 4380 if (!avg_wire_size) 4381 goto clear_counts; 4382 4383 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4384 avg_wire_size += 24; 4385 4386 /* Don't starve jumbo frames */ 4387 avg_wire_size = min(avg_wire_size, 3000); 4388 4389 /* Give a little boost to mid-size frames */ 4390 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4391 new_val = avg_wire_size / 3; 4392 else 4393 new_val = avg_wire_size / 2; 4394 4395 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4396 if (new_val < IGB_20K_ITR && 4397 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4398 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4399 new_val = IGB_20K_ITR; 4400 4401set_itr_val: 4402 if (new_val != q_vector->itr_val) { 4403 q_vector->itr_val = new_val; 4404 q_vector->set_itr = 1; 4405 } 4406clear_counts: 4407 q_vector->rx.total_bytes = 0; 4408 q_vector->rx.total_packets = 0; 4409 q_vector->tx.total_bytes = 0; 4410 q_vector->tx.total_packets = 0; 4411} 4412 4413/** 4414 * igb_update_itr - update the dynamic ITR value based on statistics 4415 * @q_vector: pointer to q_vector 4416 * @ring_container: ring info to update the itr for 4417 * 4418 * Stores a new ITR value based on packets and byte 4419 * counts during the last interrupt. The advantage of per interrupt 4420 * computation is faster updates and more accurate ITR for the current 4421 * traffic pattern. Constants in this function were computed 4422 * based on theoretical maximum wire speed and thresholds were set based 4423 * on testing data as well as attempting to minimize response time 4424 * while increasing bulk throughput. 4425 * this functionality is controlled by the InterruptThrottleRate module 4426 * parameter (see igb_param.c) 4427 * NOTE: These calculations are only valid when operating in a single- 4428 * queue environment. 4429 **/ 4430static void igb_update_itr(struct igb_q_vector *q_vector, 4431 struct igb_ring_container *ring_container) 4432{ 4433 unsigned int packets = ring_container->total_packets; 4434 unsigned int bytes = ring_container->total_bytes; 4435 u8 itrval = ring_container->itr; 4436 4437 /* no packets, exit with status unchanged */ 4438 if (packets == 0) 4439 return; 4440 4441 switch (itrval) { 4442 case lowest_latency: 4443 /* handle TSO and jumbo frames */ 4444 if (bytes/packets > 8000) 4445 itrval = bulk_latency; 4446 else if ((packets < 5) && (bytes > 512)) 4447 itrval = low_latency; 4448 break; 4449 case low_latency: /* 50 usec aka 20000 ints/s */ 4450 if (bytes > 10000) { 4451 /* this if handles the TSO accounting */ 4452 if (bytes/packets > 8000) { 4453 itrval = bulk_latency; 4454 } else if ((packets < 10) || ((bytes/packets) > 1200)) { 4455 itrval = bulk_latency; 4456 } else if ((packets > 35)) { 4457 itrval = lowest_latency; 4458 } 4459 } else if (bytes/packets > 2000) { 4460 itrval = bulk_latency; 4461 } else if (packets <= 2 && bytes < 512) { 4462 itrval = lowest_latency; 4463 } 4464 break; 4465 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4466 if (bytes > 25000) { 4467 if (packets > 35) 4468 itrval = low_latency; 4469 } else if (bytes < 1500) { 4470 itrval = low_latency; 4471 } 4472 break; 4473 } 4474 4475 /* clear work counters since we have the values we need */ 4476 ring_container->total_bytes = 0; 4477 ring_container->total_packets = 0; 4478 4479 /* write updated itr to ring container */ 4480 ring_container->itr = itrval; 4481} 4482 4483static void igb_set_itr(struct igb_q_vector *q_vector) 4484{ 4485 struct igb_adapter *adapter = q_vector->adapter; 4486 u32 new_itr = q_vector->itr_val; 4487 u8 current_itr = 0; 4488 4489 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4490 if (adapter->link_speed != SPEED_1000) { 4491 current_itr = 0; 4492 new_itr = IGB_4K_ITR; 4493 goto set_itr_now; 4494 } 4495 4496 igb_update_itr(q_vector, &q_vector->tx); 4497 igb_update_itr(q_vector, &q_vector->rx); 4498 4499 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4500 4501 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4502 if (current_itr == lowest_latency && 4503 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4504 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4505 current_itr = low_latency; 4506 4507 switch (current_itr) { 4508 /* counts and packets in update_itr are dependent on these numbers */ 4509 case lowest_latency: 4510 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4511 break; 4512 case low_latency: 4513 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4514 break; 4515 case bulk_latency: 4516 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4517 break; 4518 default: 4519 break; 4520 } 4521 4522set_itr_now: 4523 if (new_itr != q_vector->itr_val) { 4524 /* this attempts to bias the interrupt rate towards Bulk 4525 * by adding intermediate steps when interrupt rate is 4526 * increasing 4527 */ 4528 new_itr = new_itr > q_vector->itr_val ? 4529 max((new_itr * q_vector->itr_val) / 4530 (new_itr + (q_vector->itr_val >> 2)), 4531 new_itr) : new_itr; 4532 /* Don't write the value here; it resets the adapter's 4533 * internal timer, and causes us to delay far longer than 4534 * we should between interrupts. Instead, we write the ITR 4535 * value at the beginning of the next interrupt so the timing 4536 * ends up being correct. 4537 */ 4538 q_vector->itr_val = new_itr; 4539 q_vector->set_itr = 1; 4540 } 4541} 4542 4543static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4544 u32 type_tucmd, u32 mss_l4len_idx) 4545{ 4546 struct e1000_adv_tx_context_desc *context_desc; 4547 u16 i = tx_ring->next_to_use; 4548 4549 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4550 4551 i++; 4552 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4553 4554 /* set bits to identify this as an advanced context descriptor */ 4555 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4556 4557 /* For 82575, context index must be unique per ring. */ 4558 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4559 mss_l4len_idx |= tx_ring->reg_idx << 4; 4560 4561 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4562 context_desc->seqnum_seed = 0; 4563 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4564 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4565} 4566 4567static int igb_tso(struct igb_ring *tx_ring, 4568 struct igb_tx_buffer *first, 4569 u8 *hdr_len) 4570{ 4571 struct sk_buff *skb = first->skb; 4572 u32 vlan_macip_lens, type_tucmd; 4573 u32 mss_l4len_idx, l4len; 4574 4575 if (skb->ip_summed != CHECKSUM_PARTIAL) 4576 return 0; 4577 4578 if (!skb_is_gso(skb)) 4579 return 0; 4580 4581 if (skb_header_cloned(skb)) { 4582 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 4583 if (err) 4584 return err; 4585 } 4586 4587 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4588 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4589 4590 if (first->protocol == __constant_htons(ETH_P_IP)) { 4591 struct iphdr *iph = ip_hdr(skb); 4592 iph->tot_len = 0; 4593 iph->check = 0; 4594 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4595 iph->daddr, 0, 4596 IPPROTO_TCP, 4597 0); 4598 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4599 first->tx_flags |= IGB_TX_FLAGS_TSO | 4600 IGB_TX_FLAGS_CSUM | 4601 IGB_TX_FLAGS_IPV4; 4602 } else if (skb_is_gso_v6(skb)) { 4603 ipv6_hdr(skb)->payload_len = 0; 4604 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4605 &ipv6_hdr(skb)->daddr, 4606 0, IPPROTO_TCP, 0); 4607 first->tx_flags |= IGB_TX_FLAGS_TSO | 4608 IGB_TX_FLAGS_CSUM; 4609 } 4610 4611 /* compute header lengths */ 4612 l4len = tcp_hdrlen(skb); 4613 *hdr_len = skb_transport_offset(skb) + l4len; 4614 4615 /* update gso size and bytecount with header size */ 4616 first->gso_segs = skb_shinfo(skb)->gso_segs; 4617 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4618 4619 /* MSS L4LEN IDX */ 4620 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4621 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4622 4623 /* VLAN MACLEN IPLEN */ 4624 vlan_macip_lens = skb_network_header_len(skb); 4625 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4626 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4627 4628 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4629 4630 return 1; 4631} 4632 4633static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4634{ 4635 struct sk_buff *skb = first->skb; 4636 u32 vlan_macip_lens = 0; 4637 u32 mss_l4len_idx = 0; 4638 u32 type_tucmd = 0; 4639 4640 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4641 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4642 return; 4643 } else { 4644 u8 l4_hdr = 0; 4645 switch (first->protocol) { 4646 case __constant_htons(ETH_P_IP): 4647 vlan_macip_lens |= skb_network_header_len(skb); 4648 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4649 l4_hdr = ip_hdr(skb)->protocol; 4650 break; 4651 case __constant_htons(ETH_P_IPV6): 4652 vlan_macip_lens |= skb_network_header_len(skb); 4653 l4_hdr = ipv6_hdr(skb)->nexthdr; 4654 break; 4655 default: 4656 if (unlikely(net_ratelimit())) { 4657 dev_warn(tx_ring->dev, 4658 "partial checksum but proto=%x!\n", 4659 first->protocol); 4660 } 4661 break; 4662 } 4663 4664 switch (l4_hdr) { 4665 case IPPROTO_TCP: 4666 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4667 mss_l4len_idx = tcp_hdrlen(skb) << 4668 E1000_ADVTXD_L4LEN_SHIFT; 4669 break; 4670 case IPPROTO_SCTP: 4671 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4672 mss_l4len_idx = sizeof(struct sctphdr) << 4673 E1000_ADVTXD_L4LEN_SHIFT; 4674 break; 4675 case IPPROTO_UDP: 4676 mss_l4len_idx = sizeof(struct udphdr) << 4677 E1000_ADVTXD_L4LEN_SHIFT; 4678 break; 4679 default: 4680 if (unlikely(net_ratelimit())) { 4681 dev_warn(tx_ring->dev, 4682 "partial checksum but l4 proto=%x!\n", 4683 l4_hdr); 4684 } 4685 break; 4686 } 4687 4688 /* update TX checksum flag */ 4689 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4690 } 4691 4692 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4693 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4694 4695 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4696} 4697 4698#define IGB_SET_FLAG(_input, _flag, _result) \ 4699 ((_flag <= _result) ? \ 4700 ((u32)(_input & _flag) * (_result / _flag)) : \ 4701 ((u32)(_input & _flag) / (_flag / _result))) 4702 4703static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 4704{ 4705 /* set type for advanced descriptor with frame checksum insertion */ 4706 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 4707 E1000_ADVTXD_DCMD_DEXT | 4708 E1000_ADVTXD_DCMD_IFCS; 4709 4710 /* set HW vlan bit if vlan is present */ 4711 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 4712 (E1000_ADVTXD_DCMD_VLE)); 4713 4714 /* set segmentation bits for TSO */ 4715 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 4716 (E1000_ADVTXD_DCMD_TSE)); 4717 4718 /* set timestamp bit if present */ 4719 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 4720 (E1000_ADVTXD_MAC_TSTAMP)); 4721 4722 /* insert frame checksum */ 4723 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 4724 4725 return cmd_type; 4726} 4727 4728static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4729 union e1000_adv_tx_desc *tx_desc, 4730 u32 tx_flags, unsigned int paylen) 4731{ 4732 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4733 4734 /* 82575 requires a unique index per ring */ 4735 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4736 olinfo_status |= tx_ring->reg_idx << 4; 4737 4738 /* insert L4 checksum */ 4739 olinfo_status |= IGB_SET_FLAG(tx_flags, 4740 IGB_TX_FLAGS_CSUM, 4741 (E1000_TXD_POPTS_TXSM << 8)); 4742 4743 /* insert IPv4 checksum */ 4744 olinfo_status |= IGB_SET_FLAG(tx_flags, 4745 IGB_TX_FLAGS_IPV4, 4746 (E1000_TXD_POPTS_IXSM << 8)); 4747 4748 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4749} 4750 4751static void igb_tx_map(struct igb_ring *tx_ring, 4752 struct igb_tx_buffer *first, 4753 const u8 hdr_len) 4754{ 4755 struct sk_buff *skb = first->skb; 4756 struct igb_tx_buffer *tx_buffer; 4757 union e1000_adv_tx_desc *tx_desc; 4758 struct skb_frag_struct *frag; 4759 dma_addr_t dma; 4760 unsigned int data_len, size; 4761 u32 tx_flags = first->tx_flags; 4762 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 4763 u16 i = tx_ring->next_to_use; 4764 4765 tx_desc = IGB_TX_DESC(tx_ring, i); 4766 4767 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 4768 4769 size = skb_headlen(skb); 4770 data_len = skb->data_len; 4771 4772 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4773 4774 tx_buffer = first; 4775 4776 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 4777 if (dma_mapping_error(tx_ring->dev, dma)) 4778 goto dma_error; 4779 4780 /* record length, and DMA address */ 4781 dma_unmap_len_set(tx_buffer, len, size); 4782 dma_unmap_addr_set(tx_buffer, dma, dma); 4783 4784 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4785 4786 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4787 tx_desc->read.cmd_type_len = 4788 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 4789 4790 i++; 4791 tx_desc++; 4792 if (i == tx_ring->count) { 4793 tx_desc = IGB_TX_DESC(tx_ring, 0); 4794 i = 0; 4795 } 4796 tx_desc->read.olinfo_status = 0; 4797 4798 dma += IGB_MAX_DATA_PER_TXD; 4799 size -= IGB_MAX_DATA_PER_TXD; 4800 4801 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4802 } 4803 4804 if (likely(!data_len)) 4805 break; 4806 4807 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 4808 4809 i++; 4810 tx_desc++; 4811 if (i == tx_ring->count) { 4812 tx_desc = IGB_TX_DESC(tx_ring, 0); 4813 i = 0; 4814 } 4815 tx_desc->read.olinfo_status = 0; 4816 4817 size = skb_frag_size(frag); 4818 data_len -= size; 4819 4820 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4821 size, DMA_TO_DEVICE); 4822 4823 tx_buffer = &tx_ring->tx_buffer_info[i]; 4824 } 4825 4826 /* write last descriptor with RS and EOP bits */ 4827 cmd_type |= size | IGB_TXD_DCMD; 4828 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 4829 4830 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4831 4832 /* set the timestamp */ 4833 first->time_stamp = jiffies; 4834 4835 /* Force memory writes to complete before letting h/w know there 4836 * are new descriptors to fetch. (Only applicable for weak-ordered 4837 * memory model archs, such as IA-64). 4838 * 4839 * We also need this memory barrier to make certain all of the 4840 * status bits have been updated before next_to_watch is written. 4841 */ 4842 wmb(); 4843 4844 /* set next_to_watch value indicating a packet is present */ 4845 first->next_to_watch = tx_desc; 4846 4847 i++; 4848 if (i == tx_ring->count) 4849 i = 0; 4850 4851 tx_ring->next_to_use = i; 4852 4853 writel(i, tx_ring->tail); 4854 4855 /* we need this if more than one processor can write to our tail 4856 * at a time, it synchronizes IO on IA64/Altix systems 4857 */ 4858 mmiowb(); 4859 4860 return; 4861 4862dma_error: 4863 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4864 4865 /* clear dma mappings for failed tx_buffer_info map */ 4866 for (;;) { 4867 tx_buffer = &tx_ring->tx_buffer_info[i]; 4868 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4869 if (tx_buffer == first) 4870 break; 4871 if (i == 0) 4872 i = tx_ring->count; 4873 i--; 4874 } 4875 4876 tx_ring->next_to_use = i; 4877} 4878 4879static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4880{ 4881 struct net_device *netdev = tx_ring->netdev; 4882 4883 netif_stop_subqueue(netdev, tx_ring->queue_index); 4884 4885 /* Herbert's original patch had: 4886 * smp_mb__after_netif_stop_queue(); 4887 * but since that doesn't exist yet, just open code it. 4888 */ 4889 smp_mb(); 4890 4891 /* We need to check again in a case another CPU has just 4892 * made room available. 4893 */ 4894 if (igb_desc_unused(tx_ring) < size) 4895 return -EBUSY; 4896 4897 /* A reprieve! */ 4898 netif_wake_subqueue(netdev, tx_ring->queue_index); 4899 4900 u64_stats_update_begin(&tx_ring->tx_syncp2); 4901 tx_ring->tx_stats.restart_queue2++; 4902 u64_stats_update_end(&tx_ring->tx_syncp2); 4903 4904 return 0; 4905} 4906 4907static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4908{ 4909 if (igb_desc_unused(tx_ring) >= size) 4910 return 0; 4911 return __igb_maybe_stop_tx(tx_ring, size); 4912} 4913 4914netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4915 struct igb_ring *tx_ring) 4916{ 4917 struct igb_tx_buffer *first; 4918 int tso; 4919 u32 tx_flags = 0; 4920 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 4921 __be16 protocol = vlan_get_protocol(skb); 4922 u8 hdr_len = 0; 4923 4924 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 4925 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 4926 * + 2 desc gap to keep tail from touching head, 4927 * + 1 desc for context descriptor, 4928 * otherwise try next time 4929 */ 4930 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) { 4931 unsigned short f; 4932 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 4933 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 4934 } else { 4935 count += skb_shinfo(skb)->nr_frags; 4936 } 4937 4938 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 4939 /* this is a hard error */ 4940 return NETDEV_TX_BUSY; 4941 } 4942 4943 /* record the location of the first descriptor for this packet */ 4944 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 4945 first->skb = skb; 4946 first->bytecount = skb->len; 4947 first->gso_segs = 1; 4948 4949 skb_tx_timestamp(skb); 4950 4951 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 4952 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 4953 4954 if (!(adapter->ptp_tx_skb)) { 4955 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4956 tx_flags |= IGB_TX_FLAGS_TSTAMP; 4957 4958 adapter->ptp_tx_skb = skb_get(skb); 4959 adapter->ptp_tx_start = jiffies; 4960 if (adapter->hw.mac.type == e1000_82576) 4961 schedule_work(&adapter->ptp_tx_work); 4962 } 4963 } 4964 4965 if (vlan_tx_tag_present(skb)) { 4966 tx_flags |= IGB_TX_FLAGS_VLAN; 4967 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 4968 } 4969 4970 /* record initial flags and protocol */ 4971 first->tx_flags = tx_flags; 4972 first->protocol = protocol; 4973 4974 tso = igb_tso(tx_ring, first, &hdr_len); 4975 if (tso < 0) 4976 goto out_drop; 4977 else if (!tso) 4978 igb_tx_csum(tx_ring, first); 4979 4980 igb_tx_map(tx_ring, first, hdr_len); 4981 4982 /* Make sure there is space in the ring for the next send. */ 4983 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 4984 4985 return NETDEV_TX_OK; 4986 4987out_drop: 4988 igb_unmap_and_free_tx_resource(tx_ring, first); 4989 4990 return NETDEV_TX_OK; 4991} 4992 4993static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 4994 struct sk_buff *skb) 4995{ 4996 unsigned int r_idx = skb->queue_mapping; 4997 4998 if (r_idx >= adapter->num_tx_queues) 4999 r_idx = r_idx % adapter->num_tx_queues; 5000 5001 return adapter->tx_ring[r_idx]; 5002} 5003 5004static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5005 struct net_device *netdev) 5006{ 5007 struct igb_adapter *adapter = netdev_priv(netdev); 5008 5009 if (test_bit(__IGB_DOWN, &adapter->state)) { 5010 dev_kfree_skb_any(skb); 5011 return NETDEV_TX_OK; 5012 } 5013 5014 if (skb->len <= 0) { 5015 dev_kfree_skb_any(skb); 5016 return NETDEV_TX_OK; 5017 } 5018 5019 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5020 * in order to meet this minimum size requirement. 5021 */ 5022 if (unlikely(skb->len < 17)) { 5023 if (skb_pad(skb, 17 - skb->len)) 5024 return NETDEV_TX_OK; 5025 skb->len = 17; 5026 skb_set_tail_pointer(skb, 17); 5027 } 5028 5029 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5030} 5031 5032/** 5033 * igb_tx_timeout - Respond to a Tx Hang 5034 * @netdev: network interface device structure 5035 **/ 5036static void igb_tx_timeout(struct net_device *netdev) 5037{ 5038 struct igb_adapter *adapter = netdev_priv(netdev); 5039 struct e1000_hw *hw = &adapter->hw; 5040 5041 /* Do the reset outside of interrupt context */ 5042 adapter->tx_timeout_count++; 5043 5044 if (hw->mac.type >= e1000_82580) 5045 hw->dev_spec._82575.global_device_reset = true; 5046 5047 schedule_work(&adapter->reset_task); 5048 wr32(E1000_EICS, 5049 (adapter->eims_enable_mask & ~adapter->eims_other)); 5050} 5051 5052static void igb_reset_task(struct work_struct *work) 5053{ 5054 struct igb_adapter *adapter; 5055 adapter = container_of(work, struct igb_adapter, reset_task); 5056 5057 igb_dump(adapter); 5058 netdev_err(adapter->netdev, "Reset adapter\n"); 5059 igb_reinit_locked(adapter); 5060} 5061 5062/** 5063 * igb_get_stats64 - Get System Network Statistics 5064 * @netdev: network interface device structure 5065 * @stats: rtnl_link_stats64 pointer 5066 **/ 5067static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 5068 struct rtnl_link_stats64 *stats) 5069{ 5070 struct igb_adapter *adapter = netdev_priv(netdev); 5071 5072 spin_lock(&adapter->stats64_lock); 5073 igb_update_stats(adapter, &adapter->stats64); 5074 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5075 spin_unlock(&adapter->stats64_lock); 5076 5077 return stats; 5078} 5079 5080/** 5081 * igb_change_mtu - Change the Maximum Transfer Unit 5082 * @netdev: network interface device structure 5083 * @new_mtu: new value for maximum frame size 5084 * 5085 * Returns 0 on success, negative on failure 5086 **/ 5087static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5088{ 5089 struct igb_adapter *adapter = netdev_priv(netdev); 5090 struct pci_dev *pdev = adapter->pdev; 5091 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5092 5093 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 5094 dev_err(&pdev->dev, "Invalid MTU setting\n"); 5095 return -EINVAL; 5096 } 5097 5098#define MAX_STD_JUMBO_FRAME_SIZE 9238 5099 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 5100 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 5101 return -EINVAL; 5102 } 5103 5104 /* adjust max frame to be at least the size of a standard frame */ 5105 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5106 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5107 5108 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5109 msleep(1); 5110 5111 /* igb_down has a dependency on max_frame_size */ 5112 adapter->max_frame_size = max_frame; 5113 5114 if (netif_running(netdev)) 5115 igb_down(adapter); 5116 5117 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5118 netdev->mtu, new_mtu); 5119 netdev->mtu = new_mtu; 5120 5121 if (netif_running(netdev)) 5122 igb_up(adapter); 5123 else 5124 igb_reset(adapter); 5125 5126 clear_bit(__IGB_RESETTING, &adapter->state); 5127 5128 return 0; 5129} 5130 5131/** 5132 * igb_update_stats - Update the board statistics counters 5133 * @adapter: board private structure 5134 **/ 5135void igb_update_stats(struct igb_adapter *adapter, 5136 struct rtnl_link_stats64 *net_stats) 5137{ 5138 struct e1000_hw *hw = &adapter->hw; 5139 struct pci_dev *pdev = adapter->pdev; 5140 u32 reg, mpc; 5141 u16 phy_tmp; 5142 int i; 5143 u64 bytes, packets; 5144 unsigned int start; 5145 u64 _bytes, _packets; 5146 5147#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF 5148 5149 /* Prevent stats update while adapter is being reset, or if the pci 5150 * connection is down. 5151 */ 5152 if (adapter->link_speed == 0) 5153 return; 5154 if (pci_channel_offline(pdev)) 5155 return; 5156 5157 bytes = 0; 5158 packets = 0; 5159 5160 rcu_read_lock(); 5161 for (i = 0; i < adapter->num_rx_queues; i++) { 5162 u32 rqdpc = rd32(E1000_RQDPC(i)); 5163 struct igb_ring *ring = adapter->rx_ring[i]; 5164 5165 if (rqdpc) { 5166 ring->rx_stats.drops += rqdpc; 5167 net_stats->rx_fifo_errors += rqdpc; 5168 } 5169 5170 do { 5171 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5172 _bytes = ring->rx_stats.bytes; 5173 _packets = ring->rx_stats.packets; 5174 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5175 bytes += _bytes; 5176 packets += _packets; 5177 } 5178 5179 net_stats->rx_bytes = bytes; 5180 net_stats->rx_packets = packets; 5181 5182 bytes = 0; 5183 packets = 0; 5184 for (i = 0; i < adapter->num_tx_queues; i++) { 5185 struct igb_ring *ring = adapter->tx_ring[i]; 5186 do { 5187 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5188 _bytes = ring->tx_stats.bytes; 5189 _packets = ring->tx_stats.packets; 5190 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5191 bytes += _bytes; 5192 packets += _packets; 5193 } 5194 net_stats->tx_bytes = bytes; 5195 net_stats->tx_packets = packets; 5196 rcu_read_unlock(); 5197 5198 /* read stats registers */ 5199 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5200 adapter->stats.gprc += rd32(E1000_GPRC); 5201 adapter->stats.gorc += rd32(E1000_GORCL); 5202 rd32(E1000_GORCH); /* clear GORCL */ 5203 adapter->stats.bprc += rd32(E1000_BPRC); 5204 adapter->stats.mprc += rd32(E1000_MPRC); 5205 adapter->stats.roc += rd32(E1000_ROC); 5206 5207 adapter->stats.prc64 += rd32(E1000_PRC64); 5208 adapter->stats.prc127 += rd32(E1000_PRC127); 5209 adapter->stats.prc255 += rd32(E1000_PRC255); 5210 adapter->stats.prc511 += rd32(E1000_PRC511); 5211 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5212 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5213 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5214 adapter->stats.sec += rd32(E1000_SEC); 5215 5216 mpc = rd32(E1000_MPC); 5217 adapter->stats.mpc += mpc; 5218 net_stats->rx_fifo_errors += mpc; 5219 adapter->stats.scc += rd32(E1000_SCC); 5220 adapter->stats.ecol += rd32(E1000_ECOL); 5221 adapter->stats.mcc += rd32(E1000_MCC); 5222 adapter->stats.latecol += rd32(E1000_LATECOL); 5223 adapter->stats.dc += rd32(E1000_DC); 5224 adapter->stats.rlec += rd32(E1000_RLEC); 5225 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5226 adapter->stats.xontxc += rd32(E1000_XONTXC); 5227 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5228 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5229 adapter->stats.fcruc += rd32(E1000_FCRUC); 5230 adapter->stats.gptc += rd32(E1000_GPTC); 5231 adapter->stats.gotc += rd32(E1000_GOTCL); 5232 rd32(E1000_GOTCH); /* clear GOTCL */ 5233 adapter->stats.rnbc += rd32(E1000_RNBC); 5234 adapter->stats.ruc += rd32(E1000_RUC); 5235 adapter->stats.rfc += rd32(E1000_RFC); 5236 adapter->stats.rjc += rd32(E1000_RJC); 5237 adapter->stats.tor += rd32(E1000_TORH); 5238 adapter->stats.tot += rd32(E1000_TOTH); 5239 adapter->stats.tpr += rd32(E1000_TPR); 5240 5241 adapter->stats.ptc64 += rd32(E1000_PTC64); 5242 adapter->stats.ptc127 += rd32(E1000_PTC127); 5243 adapter->stats.ptc255 += rd32(E1000_PTC255); 5244 adapter->stats.ptc511 += rd32(E1000_PTC511); 5245 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5246 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5247 5248 adapter->stats.mptc += rd32(E1000_MPTC); 5249 adapter->stats.bptc += rd32(E1000_BPTC); 5250 5251 adapter->stats.tpt += rd32(E1000_TPT); 5252 adapter->stats.colc += rd32(E1000_COLC); 5253 5254 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5255 /* read internal phy specific stats */ 5256 reg = rd32(E1000_CTRL_EXT); 5257 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5258 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5259 5260 /* this stat has invalid values on i210/i211 */ 5261 if ((hw->mac.type != e1000_i210) && 5262 (hw->mac.type != e1000_i211)) 5263 adapter->stats.tncrs += rd32(E1000_TNCRS); 5264 } 5265 5266 adapter->stats.tsctc += rd32(E1000_TSCTC); 5267 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5268 5269 adapter->stats.iac += rd32(E1000_IAC); 5270 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5271 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5272 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5273 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5274 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5275 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5276 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5277 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5278 5279 /* Fill out the OS statistics structure */ 5280 net_stats->multicast = adapter->stats.mprc; 5281 net_stats->collisions = adapter->stats.colc; 5282 5283 /* Rx Errors */ 5284 5285 /* RLEC on some newer hardware can be incorrect so build 5286 * our own version based on RUC and ROC 5287 */ 5288 net_stats->rx_errors = adapter->stats.rxerrc + 5289 adapter->stats.crcerrs + adapter->stats.algnerrc + 5290 adapter->stats.ruc + adapter->stats.roc + 5291 adapter->stats.cexterr; 5292 net_stats->rx_length_errors = adapter->stats.ruc + 5293 adapter->stats.roc; 5294 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5295 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5296 net_stats->rx_missed_errors = adapter->stats.mpc; 5297 5298 /* Tx Errors */ 5299 net_stats->tx_errors = adapter->stats.ecol + 5300 adapter->stats.latecol; 5301 net_stats->tx_aborted_errors = adapter->stats.ecol; 5302 net_stats->tx_window_errors = adapter->stats.latecol; 5303 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5304 5305 /* Tx Dropped needs to be maintained elsewhere */ 5306 5307 /* Phy Stats */ 5308 if (hw->phy.media_type == e1000_media_type_copper) { 5309 if ((adapter->link_speed == SPEED_1000) && 5310 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 5311 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; 5312 adapter->phy_stats.idle_errors += phy_tmp; 5313 } 5314 } 5315 5316 /* Management Stats */ 5317 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5318 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5319 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5320 5321 /* OS2BMC Stats */ 5322 reg = rd32(E1000_MANC); 5323 if (reg & E1000_MANC_EN_BMC2OS) { 5324 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5325 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5326 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5327 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5328 } 5329} 5330 5331static irqreturn_t igb_msix_other(int irq, void *data) 5332{ 5333 struct igb_adapter *adapter = data; 5334 struct e1000_hw *hw = &adapter->hw; 5335 u32 icr = rd32(E1000_ICR); 5336 /* reading ICR causes bit 31 of EICR to be cleared */ 5337 5338 if (icr & E1000_ICR_DRSTA) 5339 schedule_work(&adapter->reset_task); 5340 5341 if (icr & E1000_ICR_DOUTSYNC) { 5342 /* HW is reporting DMA is out of sync */ 5343 adapter->stats.doosync++; 5344 /* The DMA Out of Sync is also indication of a spoof event 5345 * in IOV mode. Check the Wrong VM Behavior register to 5346 * see if it is really a spoof event. 5347 */ 5348 igb_check_wvbr(adapter); 5349 } 5350 5351 /* Check for a mailbox event */ 5352 if (icr & E1000_ICR_VMMB) 5353 igb_msg_task(adapter); 5354 5355 if (icr & E1000_ICR_LSC) { 5356 hw->mac.get_link_status = 1; 5357 /* guard against interrupt when we're going down */ 5358 if (!test_bit(__IGB_DOWN, &adapter->state)) 5359 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5360 } 5361 5362 if (icr & E1000_ICR_TS) { 5363 u32 tsicr = rd32(E1000_TSICR); 5364 5365 if (tsicr & E1000_TSICR_TXTS) { 5366 /* acknowledge the interrupt */ 5367 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5368 /* retrieve hardware timestamp */ 5369 schedule_work(&adapter->ptp_tx_work); 5370 } 5371 } 5372 5373 wr32(E1000_EIMS, adapter->eims_other); 5374 5375 return IRQ_HANDLED; 5376} 5377 5378static void igb_write_itr(struct igb_q_vector *q_vector) 5379{ 5380 struct igb_adapter *adapter = q_vector->adapter; 5381 u32 itr_val = q_vector->itr_val & 0x7FFC; 5382 5383 if (!q_vector->set_itr) 5384 return; 5385 5386 if (!itr_val) 5387 itr_val = 0x4; 5388 5389 if (adapter->hw.mac.type == e1000_82575) 5390 itr_val |= itr_val << 16; 5391 else 5392 itr_val |= E1000_EITR_CNT_IGNR; 5393 5394 writel(itr_val, q_vector->itr_register); 5395 q_vector->set_itr = 0; 5396} 5397 5398static irqreturn_t igb_msix_ring(int irq, void *data) 5399{ 5400 struct igb_q_vector *q_vector = data; 5401 5402 /* Write the ITR value calculated from the previous interrupt. */ 5403 igb_write_itr(q_vector); 5404 5405 napi_schedule(&q_vector->napi); 5406 5407 return IRQ_HANDLED; 5408} 5409 5410#ifdef CONFIG_IGB_DCA 5411static void igb_update_tx_dca(struct igb_adapter *adapter, 5412 struct igb_ring *tx_ring, 5413 int cpu) 5414{ 5415 struct e1000_hw *hw = &adapter->hw; 5416 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5417 5418 if (hw->mac.type != e1000_82575) 5419 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5420 5421 /* We can enable relaxed ordering for reads, but not writes when 5422 * DCA is enabled. This is due to a known issue in some chipsets 5423 * which will cause the DCA tag to be cleared. 5424 */ 5425 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5426 E1000_DCA_TXCTRL_DATA_RRO_EN | 5427 E1000_DCA_TXCTRL_DESC_DCA_EN; 5428 5429 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5430} 5431 5432static void igb_update_rx_dca(struct igb_adapter *adapter, 5433 struct igb_ring *rx_ring, 5434 int cpu) 5435{ 5436 struct e1000_hw *hw = &adapter->hw; 5437 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5438 5439 if (hw->mac.type != e1000_82575) 5440 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5441 5442 /* We can enable relaxed ordering for reads, but not writes when 5443 * DCA is enabled. This is due to a known issue in some chipsets 5444 * which will cause the DCA tag to be cleared. 5445 */ 5446 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5447 E1000_DCA_RXCTRL_DESC_DCA_EN; 5448 5449 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5450} 5451 5452static void igb_update_dca(struct igb_q_vector *q_vector) 5453{ 5454 struct igb_adapter *adapter = q_vector->adapter; 5455 int cpu = get_cpu(); 5456 5457 if (q_vector->cpu == cpu) 5458 goto out_no_update; 5459 5460 if (q_vector->tx.ring) 5461 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5462 5463 if (q_vector->rx.ring) 5464 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5465 5466 q_vector->cpu = cpu; 5467out_no_update: 5468 put_cpu(); 5469} 5470 5471static void igb_setup_dca(struct igb_adapter *adapter) 5472{ 5473 struct e1000_hw *hw = &adapter->hw; 5474 int i; 5475 5476 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5477 return; 5478 5479 /* Always use CB2 mode, difference is masked in the CB driver. */ 5480 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5481 5482 for (i = 0; i < adapter->num_q_vectors; i++) { 5483 adapter->q_vector[i]->cpu = -1; 5484 igb_update_dca(adapter->q_vector[i]); 5485 } 5486} 5487 5488static int __igb_notify_dca(struct device *dev, void *data) 5489{ 5490 struct net_device *netdev = dev_get_drvdata(dev); 5491 struct igb_adapter *adapter = netdev_priv(netdev); 5492 struct pci_dev *pdev = adapter->pdev; 5493 struct e1000_hw *hw = &adapter->hw; 5494 unsigned long event = *(unsigned long *)data; 5495 5496 switch (event) { 5497 case DCA_PROVIDER_ADD: 5498 /* if already enabled, don't do it again */ 5499 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5500 break; 5501 if (dca_add_requester(dev) == 0) { 5502 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5503 dev_info(&pdev->dev, "DCA enabled\n"); 5504 igb_setup_dca(adapter); 5505 break; 5506 } 5507 /* Fall Through since DCA is disabled. */ 5508 case DCA_PROVIDER_REMOVE: 5509 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5510 /* without this a class_device is left 5511 * hanging around in the sysfs model 5512 */ 5513 dca_remove_requester(dev); 5514 dev_info(&pdev->dev, "DCA disabled\n"); 5515 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5516 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5517 } 5518 break; 5519 } 5520 5521 return 0; 5522} 5523 5524static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5525 void *p) 5526{ 5527 int ret_val; 5528 5529 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5530 __igb_notify_dca); 5531 5532 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5533} 5534#endif /* CONFIG_IGB_DCA */ 5535 5536#ifdef CONFIG_PCI_IOV 5537static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5538{ 5539 unsigned char mac_addr[ETH_ALEN]; 5540 5541 eth_zero_addr(mac_addr); 5542 igb_set_vf_mac(adapter, vf, mac_addr); 5543 5544 /* By default spoof check is enabled for all VFs */ 5545 adapter->vf_data[vf].spoofchk_enabled = true; 5546 5547 return 0; 5548} 5549 5550#endif 5551static void igb_ping_all_vfs(struct igb_adapter *adapter) 5552{ 5553 struct e1000_hw *hw = &adapter->hw; 5554 u32 ping; 5555 int i; 5556 5557 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5558 ping = E1000_PF_CONTROL_MSG; 5559 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5560 ping |= E1000_VT_MSGTYPE_CTS; 5561 igb_write_mbx(hw, &ping, 1, i); 5562 } 5563} 5564 5565static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5566{ 5567 struct e1000_hw *hw = &adapter->hw; 5568 u32 vmolr = rd32(E1000_VMOLR(vf)); 5569 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5570 5571 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5572 IGB_VF_FLAG_MULTI_PROMISC); 5573 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5574 5575 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5576 vmolr |= E1000_VMOLR_MPME; 5577 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5578 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5579 } else { 5580 /* if we have hashes and we are clearing a multicast promisc 5581 * flag we need to write the hashes to the MTA as this step 5582 * was previously skipped 5583 */ 5584 if (vf_data->num_vf_mc_hashes > 30) { 5585 vmolr |= E1000_VMOLR_MPME; 5586 } else if (vf_data->num_vf_mc_hashes) { 5587 int j; 5588 vmolr |= E1000_VMOLR_ROMPE; 5589 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5590 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5591 } 5592 } 5593 5594 wr32(E1000_VMOLR(vf), vmolr); 5595 5596 /* there are flags left unprocessed, likely not supported */ 5597 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5598 return -EINVAL; 5599 5600 return 0; 5601} 5602 5603static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5604 u32 *msgbuf, u32 vf) 5605{ 5606 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5607 u16 *hash_list = (u16 *)&msgbuf[1]; 5608 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5609 int i; 5610 5611 /* salt away the number of multicast addresses assigned 5612 * to this VF for later use to restore when the PF multi cast 5613 * list changes 5614 */ 5615 vf_data->num_vf_mc_hashes = n; 5616 5617 /* only up to 30 hash values supported */ 5618 if (n > 30) 5619 n = 30; 5620 5621 /* store the hashes for later use */ 5622 for (i = 0; i < n; i++) 5623 vf_data->vf_mc_hashes[i] = hash_list[i]; 5624 5625 /* Flush and reset the mta with the new values */ 5626 igb_set_rx_mode(adapter->netdev); 5627 5628 return 0; 5629} 5630 5631static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5632{ 5633 struct e1000_hw *hw = &adapter->hw; 5634 struct vf_data_storage *vf_data; 5635 int i, j; 5636 5637 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5638 u32 vmolr = rd32(E1000_VMOLR(i)); 5639 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5640 5641 vf_data = &adapter->vf_data[i]; 5642 5643 if ((vf_data->num_vf_mc_hashes > 30) || 5644 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5645 vmolr |= E1000_VMOLR_MPME; 5646 } else if (vf_data->num_vf_mc_hashes) { 5647 vmolr |= E1000_VMOLR_ROMPE; 5648 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5649 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5650 } 5651 wr32(E1000_VMOLR(i), vmolr); 5652 } 5653} 5654 5655static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5656{ 5657 struct e1000_hw *hw = &adapter->hw; 5658 u32 pool_mask, reg, vid; 5659 int i; 5660 5661 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5662 5663 /* Find the vlan filter for this id */ 5664 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5665 reg = rd32(E1000_VLVF(i)); 5666 5667 /* remove the vf from the pool */ 5668 reg &= ~pool_mask; 5669 5670 /* if pool is empty then remove entry from vfta */ 5671 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5672 (reg & E1000_VLVF_VLANID_ENABLE)) { 5673 reg = 0; 5674 vid = reg & E1000_VLVF_VLANID_MASK; 5675 igb_vfta_set(hw, vid, false); 5676 } 5677 5678 wr32(E1000_VLVF(i), reg); 5679 } 5680 5681 adapter->vf_data[vf].vlans_enabled = 0; 5682} 5683 5684static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5685{ 5686 struct e1000_hw *hw = &adapter->hw; 5687 u32 reg, i; 5688 5689 /* The vlvf table only exists on 82576 hardware and newer */ 5690 if (hw->mac.type < e1000_82576) 5691 return -1; 5692 5693 /* we only need to do this if VMDq is enabled */ 5694 if (!adapter->vfs_allocated_count) 5695 return -1; 5696 5697 /* Find the vlan filter for this id */ 5698 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5699 reg = rd32(E1000_VLVF(i)); 5700 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5701 vid == (reg & E1000_VLVF_VLANID_MASK)) 5702 break; 5703 } 5704 5705 if (add) { 5706 if (i == E1000_VLVF_ARRAY_SIZE) { 5707 /* Did not find a matching VLAN ID entry that was 5708 * enabled. Search for a free filter entry, i.e. 5709 * one without the enable bit set 5710 */ 5711 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5712 reg = rd32(E1000_VLVF(i)); 5713 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5714 break; 5715 } 5716 } 5717 if (i < E1000_VLVF_ARRAY_SIZE) { 5718 /* Found an enabled/available entry */ 5719 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5720 5721 /* if !enabled we need to set this up in vfta */ 5722 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5723 /* add VID to filter table */ 5724 igb_vfta_set(hw, vid, true); 5725 reg |= E1000_VLVF_VLANID_ENABLE; 5726 } 5727 reg &= ~E1000_VLVF_VLANID_MASK; 5728 reg |= vid; 5729 wr32(E1000_VLVF(i), reg); 5730 5731 /* do not modify RLPML for PF devices */ 5732 if (vf >= adapter->vfs_allocated_count) 5733 return 0; 5734 5735 if (!adapter->vf_data[vf].vlans_enabled) { 5736 u32 size; 5737 reg = rd32(E1000_VMOLR(vf)); 5738 size = reg & E1000_VMOLR_RLPML_MASK; 5739 size += 4; 5740 reg &= ~E1000_VMOLR_RLPML_MASK; 5741 reg |= size; 5742 wr32(E1000_VMOLR(vf), reg); 5743 } 5744 5745 adapter->vf_data[vf].vlans_enabled++; 5746 } 5747 } else { 5748 if (i < E1000_VLVF_ARRAY_SIZE) { 5749 /* remove vf from the pool */ 5750 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5751 /* if pool is empty then remove entry from vfta */ 5752 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5753 reg = 0; 5754 igb_vfta_set(hw, vid, false); 5755 } 5756 wr32(E1000_VLVF(i), reg); 5757 5758 /* do not modify RLPML for PF devices */ 5759 if (vf >= adapter->vfs_allocated_count) 5760 return 0; 5761 5762 adapter->vf_data[vf].vlans_enabled--; 5763 if (!adapter->vf_data[vf].vlans_enabled) { 5764 u32 size; 5765 reg = rd32(E1000_VMOLR(vf)); 5766 size = reg & E1000_VMOLR_RLPML_MASK; 5767 size -= 4; 5768 reg &= ~E1000_VMOLR_RLPML_MASK; 5769 reg |= size; 5770 wr32(E1000_VMOLR(vf), reg); 5771 } 5772 } 5773 } 5774 return 0; 5775} 5776 5777static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5778{ 5779 struct e1000_hw *hw = &adapter->hw; 5780 5781 if (vid) 5782 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5783 else 5784 wr32(E1000_VMVIR(vf), 0); 5785} 5786 5787static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5788 int vf, u16 vlan, u8 qos) 5789{ 5790 int err = 0; 5791 struct igb_adapter *adapter = netdev_priv(netdev); 5792 5793 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5794 return -EINVAL; 5795 if (vlan || qos) { 5796 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5797 if (err) 5798 goto out; 5799 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5800 igb_set_vmolr(adapter, vf, !vlan); 5801 adapter->vf_data[vf].pf_vlan = vlan; 5802 adapter->vf_data[vf].pf_qos = qos; 5803 dev_info(&adapter->pdev->dev, 5804 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5805 if (test_bit(__IGB_DOWN, &adapter->state)) { 5806 dev_warn(&adapter->pdev->dev, 5807 "The VF VLAN has been set, but the PF device is not up.\n"); 5808 dev_warn(&adapter->pdev->dev, 5809 "Bring the PF device up before attempting to use the VF device.\n"); 5810 } 5811 } else { 5812 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5813 false, vf); 5814 igb_set_vmvir(adapter, vlan, vf); 5815 igb_set_vmolr(adapter, vf, true); 5816 adapter->vf_data[vf].pf_vlan = 0; 5817 adapter->vf_data[vf].pf_qos = 0; 5818 } 5819out: 5820 return err; 5821} 5822 5823static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid) 5824{ 5825 struct e1000_hw *hw = &adapter->hw; 5826 int i; 5827 u32 reg; 5828 5829 /* Find the vlan filter for this id */ 5830 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5831 reg = rd32(E1000_VLVF(i)); 5832 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5833 vid == (reg & E1000_VLVF_VLANID_MASK)) 5834 break; 5835 } 5836 5837 if (i >= E1000_VLVF_ARRAY_SIZE) 5838 i = -1; 5839 5840 return i; 5841} 5842 5843static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5844{ 5845 struct e1000_hw *hw = &adapter->hw; 5846 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5847 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5848 int err = 0; 5849 5850 /* If in promiscuous mode we need to make sure the PF also has 5851 * the VLAN filter set. 5852 */ 5853 if (add && (adapter->netdev->flags & IFF_PROMISC)) 5854 err = igb_vlvf_set(adapter, vid, add, 5855 adapter->vfs_allocated_count); 5856 if (err) 5857 goto out; 5858 5859 err = igb_vlvf_set(adapter, vid, add, vf); 5860 5861 if (err) 5862 goto out; 5863 5864 /* Go through all the checks to see if the VLAN filter should 5865 * be wiped completely. 5866 */ 5867 if (!add && (adapter->netdev->flags & IFF_PROMISC)) { 5868 u32 vlvf, bits; 5869 5870 int regndx = igb_find_vlvf_entry(adapter, vid); 5871 if (regndx < 0) 5872 goto out; 5873 /* See if any other pools are set for this VLAN filter 5874 * entry other than the PF. 5875 */ 5876 vlvf = bits = rd32(E1000_VLVF(regndx)); 5877 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT + 5878 adapter->vfs_allocated_count); 5879 /* If the filter was removed then ensure PF pool bit 5880 * is cleared if the PF only added itself to the pool 5881 * because the PF is in promiscuous mode. 5882 */ 5883 if ((vlvf & VLAN_VID_MASK) == vid && 5884 !test_bit(vid, adapter->active_vlans) && 5885 !bits) 5886 igb_vlvf_set(adapter, vid, add, 5887 adapter->vfs_allocated_count); 5888 } 5889 5890out: 5891 return err; 5892} 5893 5894static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 5895{ 5896 /* clear flags - except flag that indicates PF has set the MAC */ 5897 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 5898 adapter->vf_data[vf].last_nack = jiffies; 5899 5900 /* reset offloads to defaults */ 5901 igb_set_vmolr(adapter, vf, true); 5902 5903 /* reset vlans for device */ 5904 igb_clear_vf_vfta(adapter, vf); 5905 if (adapter->vf_data[vf].pf_vlan) 5906 igb_ndo_set_vf_vlan(adapter->netdev, vf, 5907 adapter->vf_data[vf].pf_vlan, 5908 adapter->vf_data[vf].pf_qos); 5909 else 5910 igb_clear_vf_vfta(adapter, vf); 5911 5912 /* reset multicast table array for vf */ 5913 adapter->vf_data[vf].num_vf_mc_hashes = 0; 5914 5915 /* Flush and reset the mta with the new values */ 5916 igb_set_rx_mode(adapter->netdev); 5917} 5918 5919static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 5920{ 5921 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5922 5923 /* clear mac address as we were hotplug removed/added */ 5924 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 5925 eth_zero_addr(vf_mac); 5926 5927 /* process remaining reset events */ 5928 igb_vf_reset(adapter, vf); 5929} 5930 5931static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 5932{ 5933 struct e1000_hw *hw = &adapter->hw; 5934 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5935 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 5936 u32 reg, msgbuf[3]; 5937 u8 *addr = (u8 *)(&msgbuf[1]); 5938 5939 /* process all the same items cleared in a function level reset */ 5940 igb_vf_reset(adapter, vf); 5941 5942 /* set vf mac address */ 5943 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 5944 5945 /* enable transmit and receive for vf */ 5946 reg = rd32(E1000_VFTE); 5947 wr32(E1000_VFTE, reg | (1 << vf)); 5948 reg = rd32(E1000_VFRE); 5949 wr32(E1000_VFRE, reg | (1 << vf)); 5950 5951 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 5952 5953 /* reply to reset with ack and vf mac address */ 5954 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 5955 memcpy(addr, vf_mac, ETH_ALEN); 5956 igb_write_mbx(hw, msgbuf, 3, vf); 5957} 5958 5959static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 5960{ 5961 /* The VF MAC Address is stored in a packed array of bytes 5962 * starting at the second 32 bit word of the msg array 5963 */ 5964 unsigned char *addr = (char *)&msg[1]; 5965 int err = -1; 5966 5967 if (is_valid_ether_addr(addr)) 5968 err = igb_set_vf_mac(adapter, vf, addr); 5969 5970 return err; 5971} 5972 5973static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 5974{ 5975 struct e1000_hw *hw = &adapter->hw; 5976 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5977 u32 msg = E1000_VT_MSGTYPE_NACK; 5978 5979 /* if device isn't clear to send it shouldn't be reading either */ 5980 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 5981 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 5982 igb_write_mbx(hw, &msg, 1, vf); 5983 vf_data->last_nack = jiffies; 5984 } 5985} 5986 5987static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 5988{ 5989 struct pci_dev *pdev = adapter->pdev; 5990 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 5991 struct e1000_hw *hw = &adapter->hw; 5992 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5993 s32 retval; 5994 5995 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 5996 5997 if (retval) { 5998 /* if receive failed revoke VF CTS stats and restart init */ 5999 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6000 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6001 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6002 return; 6003 goto out; 6004 } 6005 6006 /* this is a message we already processed, do nothing */ 6007 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6008 return; 6009 6010 /* until the vf completes a reset it should not be 6011 * allowed to start any configuration. 6012 */ 6013 if (msgbuf[0] == E1000_VF_RESET) { 6014 igb_vf_reset_msg(adapter, vf); 6015 return; 6016 } 6017 6018 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6019 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6020 return; 6021 retval = -1; 6022 goto out; 6023 } 6024 6025 switch ((msgbuf[0] & 0xFFFF)) { 6026 case E1000_VF_SET_MAC_ADDR: 6027 retval = -EINVAL; 6028 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 6029 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6030 else 6031 dev_warn(&pdev->dev, 6032 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6033 vf); 6034 break; 6035 case E1000_VF_SET_PROMISC: 6036 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6037 break; 6038 case E1000_VF_SET_MULTICAST: 6039 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6040 break; 6041 case E1000_VF_SET_LPE: 6042 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6043 break; 6044 case E1000_VF_SET_VLAN: 6045 retval = -1; 6046 if (vf_data->pf_vlan) 6047 dev_warn(&pdev->dev, 6048 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6049 vf); 6050 else 6051 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 6052 break; 6053 default: 6054 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6055 retval = -1; 6056 break; 6057 } 6058 6059 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6060out: 6061 /* notify the VF of the results of what it sent us */ 6062 if (retval) 6063 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6064 else 6065 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6066 6067 igb_write_mbx(hw, msgbuf, 1, vf); 6068} 6069 6070static void igb_msg_task(struct igb_adapter *adapter) 6071{ 6072 struct e1000_hw *hw = &adapter->hw; 6073 u32 vf; 6074 6075 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6076 /* process any reset requests */ 6077 if (!igb_check_for_rst(hw, vf)) 6078 igb_vf_reset_event(adapter, vf); 6079 6080 /* process any messages pending */ 6081 if (!igb_check_for_msg(hw, vf)) 6082 igb_rcv_msg_from_vf(adapter, vf); 6083 6084 /* process any acks */ 6085 if (!igb_check_for_ack(hw, vf)) 6086 igb_rcv_ack_from_vf(adapter, vf); 6087 } 6088} 6089 6090/** 6091 * igb_set_uta - Set unicast filter table address 6092 * @adapter: board private structure 6093 * 6094 * The unicast table address is a register array of 32-bit registers. 6095 * The table is meant to be used in a way similar to how the MTA is used 6096 * however due to certain limitations in the hardware it is necessary to 6097 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6098 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6099 **/ 6100static void igb_set_uta(struct igb_adapter *adapter) 6101{ 6102 struct e1000_hw *hw = &adapter->hw; 6103 int i; 6104 6105 /* The UTA table only exists on 82576 hardware and newer */ 6106 if (hw->mac.type < e1000_82576) 6107 return; 6108 6109 /* we only need to do this if VMDq is enabled */ 6110 if (!adapter->vfs_allocated_count) 6111 return; 6112 6113 for (i = 0; i < hw->mac.uta_reg_count; i++) 6114 array_wr32(E1000_UTA, i, ~0); 6115} 6116 6117/** 6118 * igb_intr_msi - Interrupt Handler 6119 * @irq: interrupt number 6120 * @data: pointer to a network interface device structure 6121 **/ 6122static irqreturn_t igb_intr_msi(int irq, void *data) 6123{ 6124 struct igb_adapter *adapter = data; 6125 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6126 struct e1000_hw *hw = &adapter->hw; 6127 /* read ICR disables interrupts using IAM */ 6128 u32 icr = rd32(E1000_ICR); 6129 6130 igb_write_itr(q_vector); 6131 6132 if (icr & E1000_ICR_DRSTA) 6133 schedule_work(&adapter->reset_task); 6134 6135 if (icr & E1000_ICR_DOUTSYNC) { 6136 /* HW is reporting DMA is out of sync */ 6137 adapter->stats.doosync++; 6138 } 6139 6140 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6141 hw->mac.get_link_status = 1; 6142 if (!test_bit(__IGB_DOWN, &adapter->state)) 6143 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6144 } 6145 6146 if (icr & E1000_ICR_TS) { 6147 u32 tsicr = rd32(E1000_TSICR); 6148 6149 if (tsicr & E1000_TSICR_TXTS) { 6150 /* acknowledge the interrupt */ 6151 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6152 /* retrieve hardware timestamp */ 6153 schedule_work(&adapter->ptp_tx_work); 6154 } 6155 } 6156 6157 napi_schedule(&q_vector->napi); 6158 6159 return IRQ_HANDLED; 6160} 6161 6162/** 6163 * igb_intr - Legacy Interrupt Handler 6164 * @irq: interrupt number 6165 * @data: pointer to a network interface device structure 6166 **/ 6167static irqreturn_t igb_intr(int irq, void *data) 6168{ 6169 struct igb_adapter *adapter = data; 6170 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6171 struct e1000_hw *hw = &adapter->hw; 6172 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6173 * need for the IMC write 6174 */ 6175 u32 icr = rd32(E1000_ICR); 6176 6177 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6178 * not set, then the adapter didn't send an interrupt 6179 */ 6180 if (!(icr & E1000_ICR_INT_ASSERTED)) 6181 return IRQ_NONE; 6182 6183 igb_write_itr(q_vector); 6184 6185 if (icr & E1000_ICR_DRSTA) 6186 schedule_work(&adapter->reset_task); 6187 6188 if (icr & E1000_ICR_DOUTSYNC) { 6189 /* HW is reporting DMA is out of sync */ 6190 adapter->stats.doosync++; 6191 } 6192 6193 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6194 hw->mac.get_link_status = 1; 6195 /* guard against interrupt when we're going down */ 6196 if (!test_bit(__IGB_DOWN, &adapter->state)) 6197 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6198 } 6199 6200 if (icr & E1000_ICR_TS) { 6201 u32 tsicr = rd32(E1000_TSICR); 6202 6203 if (tsicr & E1000_TSICR_TXTS) { 6204 /* acknowledge the interrupt */ 6205 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6206 /* retrieve hardware timestamp */ 6207 schedule_work(&adapter->ptp_tx_work); 6208 } 6209 } 6210 6211 napi_schedule(&q_vector->napi); 6212 6213 return IRQ_HANDLED; 6214} 6215 6216static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6217{ 6218 struct igb_adapter *adapter = q_vector->adapter; 6219 struct e1000_hw *hw = &adapter->hw; 6220 6221 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6222 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6223 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6224 igb_set_itr(q_vector); 6225 else 6226 igb_update_ring_itr(q_vector); 6227 } 6228 6229 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6230 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6231 wr32(E1000_EIMS, q_vector->eims_value); 6232 else 6233 igb_irq_enable(adapter); 6234 } 6235} 6236 6237/** 6238 * igb_poll - NAPI Rx polling callback 6239 * @napi: napi polling structure 6240 * @budget: count of how many packets we should handle 6241 **/ 6242static int igb_poll(struct napi_struct *napi, int budget) 6243{ 6244 struct igb_q_vector *q_vector = container_of(napi, 6245 struct igb_q_vector, 6246 napi); 6247 bool clean_complete = true; 6248 6249#ifdef CONFIG_IGB_DCA 6250 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6251 igb_update_dca(q_vector); 6252#endif 6253 if (q_vector->tx.ring) 6254 clean_complete = igb_clean_tx_irq(q_vector); 6255 6256 if (q_vector->rx.ring) 6257 clean_complete &= igb_clean_rx_irq(q_vector, budget); 6258 6259 /* If all work not completed, return budget and keep polling */ 6260 if (!clean_complete) 6261 return budget; 6262 6263 /* If not enough Rx work done, exit the polling mode */ 6264 napi_complete(napi); 6265 igb_ring_irq_enable(q_vector); 6266 6267 return 0; 6268} 6269 6270/** 6271 * igb_clean_tx_irq - Reclaim resources after transmit completes 6272 * @q_vector: pointer to q_vector containing needed info 6273 * 6274 * returns true if ring is completely cleaned 6275 **/ 6276static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 6277{ 6278 struct igb_adapter *adapter = q_vector->adapter; 6279 struct igb_ring *tx_ring = q_vector->tx.ring; 6280 struct igb_tx_buffer *tx_buffer; 6281 union e1000_adv_tx_desc *tx_desc; 6282 unsigned int total_bytes = 0, total_packets = 0; 6283 unsigned int budget = q_vector->tx.work_limit; 6284 unsigned int i = tx_ring->next_to_clean; 6285 6286 if (test_bit(__IGB_DOWN, &adapter->state)) 6287 return true; 6288 6289 tx_buffer = &tx_ring->tx_buffer_info[i]; 6290 tx_desc = IGB_TX_DESC(tx_ring, i); 6291 i -= tx_ring->count; 6292 6293 do { 6294 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6295 6296 /* if next_to_watch is not set then there is no work pending */ 6297 if (!eop_desc) 6298 break; 6299 6300 /* prevent any other reads prior to eop_desc */ 6301 read_barrier_depends(); 6302 6303 /* if DD is not set pending work has not been completed */ 6304 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6305 break; 6306 6307 /* clear next_to_watch to prevent false hangs */ 6308 tx_buffer->next_to_watch = NULL; 6309 6310 /* update the statistics for this packet */ 6311 total_bytes += tx_buffer->bytecount; 6312 total_packets += tx_buffer->gso_segs; 6313 6314 /* free the skb */ 6315 dev_kfree_skb_any(tx_buffer->skb); 6316 6317 /* unmap skb header data */ 6318 dma_unmap_single(tx_ring->dev, 6319 dma_unmap_addr(tx_buffer, dma), 6320 dma_unmap_len(tx_buffer, len), 6321 DMA_TO_DEVICE); 6322 6323 /* clear tx_buffer data */ 6324 tx_buffer->skb = NULL; 6325 dma_unmap_len_set(tx_buffer, len, 0); 6326 6327 /* clear last DMA location and unmap remaining buffers */ 6328 while (tx_desc != eop_desc) { 6329 tx_buffer++; 6330 tx_desc++; 6331 i++; 6332 if (unlikely(!i)) { 6333 i -= tx_ring->count; 6334 tx_buffer = tx_ring->tx_buffer_info; 6335 tx_desc = IGB_TX_DESC(tx_ring, 0); 6336 } 6337 6338 /* unmap any remaining paged data */ 6339 if (dma_unmap_len(tx_buffer, len)) { 6340 dma_unmap_page(tx_ring->dev, 6341 dma_unmap_addr(tx_buffer, dma), 6342 dma_unmap_len(tx_buffer, len), 6343 DMA_TO_DEVICE); 6344 dma_unmap_len_set(tx_buffer, len, 0); 6345 } 6346 } 6347 6348 /* move us one more past the eop_desc for start of next pkt */ 6349 tx_buffer++; 6350 tx_desc++; 6351 i++; 6352 if (unlikely(!i)) { 6353 i -= tx_ring->count; 6354 tx_buffer = tx_ring->tx_buffer_info; 6355 tx_desc = IGB_TX_DESC(tx_ring, 0); 6356 } 6357 6358 /* issue prefetch for next Tx descriptor */ 6359 prefetch(tx_desc); 6360 6361 /* update budget accounting */ 6362 budget--; 6363 } while (likely(budget)); 6364 6365 netdev_tx_completed_queue(txring_txq(tx_ring), 6366 total_packets, total_bytes); 6367 i += tx_ring->count; 6368 tx_ring->next_to_clean = i; 6369 u64_stats_update_begin(&tx_ring->tx_syncp); 6370 tx_ring->tx_stats.bytes += total_bytes; 6371 tx_ring->tx_stats.packets += total_packets; 6372 u64_stats_update_end(&tx_ring->tx_syncp); 6373 q_vector->tx.total_bytes += total_bytes; 6374 q_vector->tx.total_packets += total_packets; 6375 6376 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6377 struct e1000_hw *hw = &adapter->hw; 6378 6379 /* Detect a transmit hang in hardware, this serializes the 6380 * check with the clearing of time_stamp and movement of i 6381 */ 6382 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6383 if (tx_buffer->next_to_watch && 6384 time_after(jiffies, tx_buffer->time_stamp + 6385 (adapter->tx_timeout_factor * HZ)) && 6386 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6387 6388 /* detected Tx unit hang */ 6389 dev_err(tx_ring->dev, 6390 "Detected Tx Unit Hang\n" 6391 " Tx Queue <%d>\n" 6392 " TDH <%x>\n" 6393 " TDT <%x>\n" 6394 " next_to_use <%x>\n" 6395 " next_to_clean <%x>\n" 6396 "buffer_info[next_to_clean]\n" 6397 " time_stamp <%lx>\n" 6398 " next_to_watch <%p>\n" 6399 " jiffies <%lx>\n" 6400 " desc.status <%x>\n", 6401 tx_ring->queue_index, 6402 rd32(E1000_TDH(tx_ring->reg_idx)), 6403 readl(tx_ring->tail), 6404 tx_ring->next_to_use, 6405 tx_ring->next_to_clean, 6406 tx_buffer->time_stamp, 6407 tx_buffer->next_to_watch, 6408 jiffies, 6409 tx_buffer->next_to_watch->wb.status); 6410 netif_stop_subqueue(tx_ring->netdev, 6411 tx_ring->queue_index); 6412 6413 /* we are about to reset, no point in enabling stuff */ 6414 return true; 6415 } 6416 } 6417 6418#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6419 if (unlikely(total_packets && 6420 netif_carrier_ok(tx_ring->netdev) && 6421 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6422 /* Make sure that anybody stopping the queue after this 6423 * sees the new next_to_clean. 6424 */ 6425 smp_mb(); 6426 if (__netif_subqueue_stopped(tx_ring->netdev, 6427 tx_ring->queue_index) && 6428 !(test_bit(__IGB_DOWN, &adapter->state))) { 6429 netif_wake_subqueue(tx_ring->netdev, 6430 tx_ring->queue_index); 6431 6432 u64_stats_update_begin(&tx_ring->tx_syncp); 6433 tx_ring->tx_stats.restart_queue++; 6434 u64_stats_update_end(&tx_ring->tx_syncp); 6435 } 6436 } 6437 6438 return !!budget; 6439} 6440 6441/** 6442 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6443 * @rx_ring: rx descriptor ring to store buffers on 6444 * @old_buff: donor buffer to have page reused 6445 * 6446 * Synchronizes page for reuse by the adapter 6447 **/ 6448static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6449 struct igb_rx_buffer *old_buff) 6450{ 6451 struct igb_rx_buffer *new_buff; 6452 u16 nta = rx_ring->next_to_alloc; 6453 6454 new_buff = &rx_ring->rx_buffer_info[nta]; 6455 6456 /* update, and store next to alloc */ 6457 nta++; 6458 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6459 6460 /* transfer page from old buffer to new buffer */ 6461 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); 6462 6463 /* sync the buffer for use by the device */ 6464 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 6465 old_buff->page_offset, 6466 IGB_RX_BUFSZ, 6467 DMA_FROM_DEVICE); 6468} 6469 6470static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 6471 struct page *page, 6472 unsigned int truesize) 6473{ 6474 /* avoid re-using remote pages */ 6475 if (unlikely(page_to_nid(page) != numa_node_id())) 6476 return false; 6477 6478#if (PAGE_SIZE < 8192) 6479 /* if we are only owner of page we can reuse it */ 6480 if (unlikely(page_count(page) != 1)) 6481 return false; 6482 6483 /* flip page offset to other buffer */ 6484 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 6485 6486 /* since we are the only owner of the page and we need to 6487 * increment it, just set the value to 2 in order to avoid 6488 * an unnecessary locked operation 6489 */ 6490 atomic_set(&page->_count, 2); 6491#else 6492 /* move offset up to the next cache line */ 6493 rx_buffer->page_offset += truesize; 6494 6495 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 6496 return false; 6497 6498 /* bump ref count on page before it is given to the stack */ 6499 get_page(page); 6500#endif 6501 6502 return true; 6503} 6504 6505/** 6506 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6507 * @rx_ring: rx descriptor ring to transact packets on 6508 * @rx_buffer: buffer containing page to add 6509 * @rx_desc: descriptor containing length of buffer written by hardware 6510 * @skb: sk_buff to place the data into 6511 * 6512 * This function will add the data contained in rx_buffer->page to the skb. 6513 * This is done either through a direct copy if the data in the buffer is 6514 * less than the skb header size, otherwise it will just attach the page as 6515 * a frag to the skb. 6516 * 6517 * The function will then update the page offset if necessary and return 6518 * true if the buffer can be reused by the adapter. 6519 **/ 6520static bool igb_add_rx_frag(struct igb_ring *rx_ring, 6521 struct igb_rx_buffer *rx_buffer, 6522 union e1000_adv_rx_desc *rx_desc, 6523 struct sk_buff *skb) 6524{ 6525 struct page *page = rx_buffer->page; 6526 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 6527#if (PAGE_SIZE < 8192) 6528 unsigned int truesize = IGB_RX_BUFSZ; 6529#else 6530 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 6531#endif 6532 6533 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { 6534 unsigned char *va = page_address(page) + rx_buffer->page_offset; 6535 6536 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6537 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6538 va += IGB_TS_HDR_LEN; 6539 size -= IGB_TS_HDR_LEN; 6540 } 6541 6542 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 6543 6544 /* we can reuse buffer as-is, just make sure it is local */ 6545 if (likely(page_to_nid(page) == numa_node_id())) 6546 return true; 6547 6548 /* this page cannot be reused so discard it */ 6549 put_page(page); 6550 return false; 6551 } 6552 6553 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 6554 rx_buffer->page_offset, size, truesize); 6555 6556 return igb_can_reuse_rx_page(rx_buffer, page, truesize); 6557} 6558 6559static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 6560 union e1000_adv_rx_desc *rx_desc, 6561 struct sk_buff *skb) 6562{ 6563 struct igb_rx_buffer *rx_buffer; 6564 struct page *page; 6565 6566 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 6567 6568 page = rx_buffer->page; 6569 prefetchw(page); 6570 6571 if (likely(!skb)) { 6572 void *page_addr = page_address(page) + 6573 rx_buffer->page_offset; 6574 6575 /* prefetch first cache line of first page */ 6576 prefetch(page_addr); 6577#if L1_CACHE_BYTES < 128 6578 prefetch(page_addr + L1_CACHE_BYTES); 6579#endif 6580 6581 /* allocate a skb to store the frags */ 6582 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 6583 IGB_RX_HDR_LEN); 6584 if (unlikely(!skb)) { 6585 rx_ring->rx_stats.alloc_failed++; 6586 return NULL; 6587 } 6588 6589 /* we will be copying header into skb->data in 6590 * pskb_may_pull so it is in our interest to prefetch 6591 * it now to avoid a possible cache miss 6592 */ 6593 prefetchw(skb->data); 6594 } 6595 6596 /* we are reusing so sync this buffer for CPU use */ 6597 dma_sync_single_range_for_cpu(rx_ring->dev, 6598 rx_buffer->dma, 6599 rx_buffer->page_offset, 6600 IGB_RX_BUFSZ, 6601 DMA_FROM_DEVICE); 6602 6603 /* pull page into skb */ 6604 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 6605 /* hand second half of page back to the ring */ 6606 igb_reuse_rx_page(rx_ring, rx_buffer); 6607 } else { 6608 /* we are not reusing the buffer so unmap it */ 6609 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6610 PAGE_SIZE, DMA_FROM_DEVICE); 6611 } 6612 6613 /* clear contents of rx_buffer */ 6614 rx_buffer->page = NULL; 6615 6616 return skb; 6617} 6618 6619static inline void igb_rx_checksum(struct igb_ring *ring, 6620 union e1000_adv_rx_desc *rx_desc, 6621 struct sk_buff *skb) 6622{ 6623 skb_checksum_none_assert(skb); 6624 6625 /* Ignore Checksum bit is set */ 6626 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6627 return; 6628 6629 /* Rx checksum disabled via ethtool */ 6630 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6631 return; 6632 6633 /* TCP/UDP checksum error bit is set */ 6634 if (igb_test_staterr(rx_desc, 6635 E1000_RXDEXT_STATERR_TCPE | 6636 E1000_RXDEXT_STATERR_IPE)) { 6637 /* work around errata with sctp packets where the TCPE aka 6638 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6639 * packets, (aka let the stack check the crc32c) 6640 */ 6641 if (!((skb->len == 60) && 6642 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6643 u64_stats_update_begin(&ring->rx_syncp); 6644 ring->rx_stats.csum_err++; 6645 u64_stats_update_end(&ring->rx_syncp); 6646 } 6647 /* let the stack verify checksum errors */ 6648 return; 6649 } 6650 /* It must be a TCP or UDP packet with a valid checksum */ 6651 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 6652 E1000_RXD_STAT_UDPCS)) 6653 skb->ip_summed = CHECKSUM_UNNECESSARY; 6654 6655 dev_dbg(ring->dev, "cksum success: bits %08X\n", 6656 le32_to_cpu(rx_desc->wb.upper.status_error)); 6657} 6658 6659static inline void igb_rx_hash(struct igb_ring *ring, 6660 union e1000_adv_rx_desc *rx_desc, 6661 struct sk_buff *skb) 6662{ 6663 if (ring->netdev->features & NETIF_F_RXHASH) 6664 skb_set_hash(skb, 6665 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 6666 PKT_HASH_TYPE_L3); 6667} 6668 6669/** 6670 * igb_is_non_eop - process handling of non-EOP buffers 6671 * @rx_ring: Rx ring being processed 6672 * @rx_desc: Rx descriptor for current buffer 6673 * @skb: current socket buffer containing buffer in progress 6674 * 6675 * This function updates next to clean. If the buffer is an EOP buffer 6676 * this function exits returning false, otherwise it will place the 6677 * sk_buff in the next buffer to be chained and return true indicating 6678 * that this is in fact a non-EOP buffer. 6679 **/ 6680static bool igb_is_non_eop(struct igb_ring *rx_ring, 6681 union e1000_adv_rx_desc *rx_desc) 6682{ 6683 u32 ntc = rx_ring->next_to_clean + 1; 6684 6685 /* fetch, update, and store next to clean */ 6686 ntc = (ntc < rx_ring->count) ? ntc : 0; 6687 rx_ring->next_to_clean = ntc; 6688 6689 prefetch(IGB_RX_DESC(rx_ring, ntc)); 6690 6691 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 6692 return false; 6693 6694 return true; 6695} 6696 6697/** 6698 * igb_get_headlen - determine size of header for LRO/GRO 6699 * @data: pointer to the start of the headers 6700 * @max_len: total length of section to find headers in 6701 * 6702 * This function is meant to determine the length of headers that will 6703 * be recognized by hardware for LRO, and GRO offloads. The main 6704 * motivation of doing this is to only perform one pull for IPv4 TCP 6705 * packets so that we can do basic things like calculating the gso_size 6706 * based on the average data per packet. 6707 **/ 6708static unsigned int igb_get_headlen(unsigned char *data, 6709 unsigned int max_len) 6710{ 6711 union { 6712 unsigned char *network; 6713 /* l2 headers */ 6714 struct ethhdr *eth; 6715 struct vlan_hdr *vlan; 6716 /* l3 headers */ 6717 struct iphdr *ipv4; 6718 struct ipv6hdr *ipv6; 6719 } hdr; 6720 __be16 protocol; 6721 u8 nexthdr = 0; /* default to not TCP */ 6722 u8 hlen; 6723 6724 /* this should never happen, but better safe than sorry */ 6725 if (max_len < ETH_HLEN) 6726 return max_len; 6727 6728 /* initialize network frame pointer */ 6729 hdr.network = data; 6730 6731 /* set first protocol and move network header forward */ 6732 protocol = hdr.eth->h_proto; 6733 hdr.network += ETH_HLEN; 6734 6735 /* handle any vlan tag if present */ 6736 if (protocol == __constant_htons(ETH_P_8021Q)) { 6737 if ((hdr.network - data) > (max_len - VLAN_HLEN)) 6738 return max_len; 6739 6740 protocol = hdr.vlan->h_vlan_encapsulated_proto; 6741 hdr.network += VLAN_HLEN; 6742 } 6743 6744 /* handle L3 protocols */ 6745 if (protocol == __constant_htons(ETH_P_IP)) { 6746 if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) 6747 return max_len; 6748 6749 /* access ihl as a u8 to avoid unaligned access on ia64 */ 6750 hlen = (hdr.network[0] & 0x0F) << 2; 6751 6752 /* verify hlen meets minimum size requirements */ 6753 if (hlen < sizeof(struct iphdr)) 6754 return hdr.network - data; 6755 6756 /* record next protocol if header is present */ 6757 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET))) 6758 nexthdr = hdr.ipv4->protocol; 6759 } else if (protocol == __constant_htons(ETH_P_IPV6)) { 6760 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) 6761 return max_len; 6762 6763 /* record next protocol */ 6764 nexthdr = hdr.ipv6->nexthdr; 6765 hlen = sizeof(struct ipv6hdr); 6766 } else { 6767 return hdr.network - data; 6768 } 6769 6770 /* relocate pointer to start of L4 header */ 6771 hdr.network += hlen; 6772 6773 /* finally sort out TCP */ 6774 if (nexthdr == IPPROTO_TCP) { 6775 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) 6776 return max_len; 6777 6778 /* access doff as a u8 to avoid unaligned access on ia64 */ 6779 hlen = (hdr.network[12] & 0xF0) >> 2; 6780 6781 /* verify hlen meets minimum size requirements */ 6782 if (hlen < sizeof(struct tcphdr)) 6783 return hdr.network - data; 6784 6785 hdr.network += hlen; 6786 } else if (nexthdr == IPPROTO_UDP) { 6787 if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) 6788 return max_len; 6789 6790 hdr.network += sizeof(struct udphdr); 6791 } 6792 6793 /* If everything has gone correctly hdr.network should be the 6794 * data section of the packet and will be the end of the header. 6795 * If not then it probably represents the end of the last recognized 6796 * header. 6797 */ 6798 if ((hdr.network - data) < max_len) 6799 return hdr.network - data; 6800 else 6801 return max_len; 6802} 6803 6804/** 6805 * igb_pull_tail - igb specific version of skb_pull_tail 6806 * @rx_ring: rx descriptor ring packet is being transacted on 6807 * @rx_desc: pointer to the EOP Rx descriptor 6808 * @skb: pointer to current skb being adjusted 6809 * 6810 * This function is an igb specific version of __pskb_pull_tail. The 6811 * main difference between this version and the original function is that 6812 * this function can make several assumptions about the state of things 6813 * that allow for significant optimizations versus the standard function. 6814 * As a result we can do things like drop a frag and maintain an accurate 6815 * truesize for the skb. 6816 */ 6817static void igb_pull_tail(struct igb_ring *rx_ring, 6818 union e1000_adv_rx_desc *rx_desc, 6819 struct sk_buff *skb) 6820{ 6821 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6822 unsigned char *va; 6823 unsigned int pull_len; 6824 6825 /* it is valid to use page_address instead of kmap since we are 6826 * working with pages allocated out of the lomem pool per 6827 * alloc_page(GFP_ATOMIC) 6828 */ 6829 va = skb_frag_address(frag); 6830 6831 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6832 /* retrieve timestamp from buffer */ 6833 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6834 6835 /* update pointers to remove timestamp header */ 6836 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); 6837 frag->page_offset += IGB_TS_HDR_LEN; 6838 skb->data_len -= IGB_TS_HDR_LEN; 6839 skb->len -= IGB_TS_HDR_LEN; 6840 6841 /* move va to start of packet data */ 6842 va += IGB_TS_HDR_LEN; 6843 } 6844 6845 /* we need the header to contain the greater of either ETH_HLEN or 6846 * 60 bytes if the skb->len is less than 60 for skb_pad. 6847 */ 6848 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); 6849 6850 /* align pull length to size of long to optimize memcpy performance */ 6851 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 6852 6853 /* update all of the pointers */ 6854 skb_frag_size_sub(frag, pull_len); 6855 frag->page_offset += pull_len; 6856 skb->data_len -= pull_len; 6857 skb->tail += pull_len; 6858} 6859 6860/** 6861 * igb_cleanup_headers - Correct corrupted or empty headers 6862 * @rx_ring: rx descriptor ring packet is being transacted on 6863 * @rx_desc: pointer to the EOP Rx descriptor 6864 * @skb: pointer to current skb being fixed 6865 * 6866 * Address the case where we are pulling data in on pages only 6867 * and as such no data is present in the skb header. 6868 * 6869 * In addition if skb is not at least 60 bytes we need to pad it so that 6870 * it is large enough to qualify as a valid Ethernet frame. 6871 * 6872 * Returns true if an error was encountered and skb was freed. 6873 **/ 6874static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6875 union e1000_adv_rx_desc *rx_desc, 6876 struct sk_buff *skb) 6877{ 6878 if (unlikely((igb_test_staterr(rx_desc, 6879 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6880 struct net_device *netdev = rx_ring->netdev; 6881 if (!(netdev->features & NETIF_F_RXALL)) { 6882 dev_kfree_skb_any(skb); 6883 return true; 6884 } 6885 } 6886 6887 /* place header in linear portion of buffer */ 6888 if (skb_is_nonlinear(skb)) 6889 igb_pull_tail(rx_ring, rx_desc, skb); 6890 6891 /* if skb_pad returns an error the skb was freed */ 6892 if (unlikely(skb->len < 60)) { 6893 int pad_len = 60 - skb->len; 6894 6895 if (skb_pad(skb, pad_len)) 6896 return true; 6897 __skb_put(skb, pad_len); 6898 } 6899 6900 return false; 6901} 6902 6903/** 6904 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6905 * @rx_ring: rx descriptor ring packet is being transacted on 6906 * @rx_desc: pointer to the EOP Rx descriptor 6907 * @skb: pointer to current skb being populated 6908 * 6909 * This function checks the ring, descriptor, and packet information in 6910 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6911 * other fields within the skb. 6912 **/ 6913static void igb_process_skb_fields(struct igb_ring *rx_ring, 6914 union e1000_adv_rx_desc *rx_desc, 6915 struct sk_buff *skb) 6916{ 6917 struct net_device *dev = rx_ring->netdev; 6918 6919 igb_rx_hash(rx_ring, rx_desc, skb); 6920 6921 igb_rx_checksum(rx_ring, rx_desc, skb); 6922 6923 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 6924 6925 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 6926 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6927 u16 vid; 6928 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6929 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6930 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6931 else 6932 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6933 6934 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 6935 } 6936 6937 skb_record_rx_queue(skb, rx_ring->queue_index); 6938 6939 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6940} 6941 6942static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 6943{ 6944 struct igb_ring *rx_ring = q_vector->rx.ring; 6945 struct sk_buff *skb = rx_ring->skb; 6946 unsigned int total_bytes = 0, total_packets = 0; 6947 u16 cleaned_count = igb_desc_unused(rx_ring); 6948 6949 while (likely(total_packets < budget)) { 6950 union e1000_adv_rx_desc *rx_desc; 6951 6952 /* return some buffers to hardware, one at a time is too slow */ 6953 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6954 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6955 cleaned_count = 0; 6956 } 6957 6958 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 6959 6960 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) 6961 break; 6962 6963 /* This memory barrier is needed to keep us from reading 6964 * any other fields out of the rx_desc until we know the 6965 * RXD_STAT_DD bit is set 6966 */ 6967 rmb(); 6968 6969 /* retrieve a buffer from the ring */ 6970 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 6971 6972 /* exit if we failed to retrieve a buffer */ 6973 if (!skb) 6974 break; 6975 6976 cleaned_count++; 6977 6978 /* fetch next buffer in frame if non-eop */ 6979 if (igb_is_non_eop(rx_ring, rx_desc)) 6980 continue; 6981 6982 /* verify the packet layout is correct */ 6983 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 6984 skb = NULL; 6985 continue; 6986 } 6987 6988 /* probably a little skewed due to removing CRC */ 6989 total_bytes += skb->len; 6990 6991 /* populate checksum, timestamp, VLAN, and protocol */ 6992 igb_process_skb_fields(rx_ring, rx_desc, skb); 6993 6994 napi_gro_receive(&q_vector->napi, skb); 6995 6996 /* reset skb pointer */ 6997 skb = NULL; 6998 6999 /* update budget accounting */ 7000 total_packets++; 7001 } 7002 7003 /* place incomplete frames back on ring for completion */ 7004 rx_ring->skb = skb; 7005 7006 u64_stats_update_begin(&rx_ring->rx_syncp); 7007 rx_ring->rx_stats.packets += total_packets; 7008 rx_ring->rx_stats.bytes += total_bytes; 7009 u64_stats_update_end(&rx_ring->rx_syncp); 7010 q_vector->rx.total_packets += total_packets; 7011 q_vector->rx.total_bytes += total_bytes; 7012 7013 if (cleaned_count) 7014 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7015 7016 return (total_packets < budget); 7017} 7018 7019static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7020 struct igb_rx_buffer *bi) 7021{ 7022 struct page *page = bi->page; 7023 dma_addr_t dma; 7024 7025 /* since we are recycling buffers we should seldom need to alloc */ 7026 if (likely(page)) 7027 return true; 7028 7029 /* alloc new page for storage */ 7030 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); 7031 if (unlikely(!page)) { 7032 rx_ring->rx_stats.alloc_failed++; 7033 return false; 7034 } 7035 7036 /* map page for use */ 7037 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 7038 7039 /* if mapping failed free memory back to system since 7040 * there isn't much point in holding memory we can't use 7041 */ 7042 if (dma_mapping_error(rx_ring->dev, dma)) { 7043 __free_page(page); 7044 7045 rx_ring->rx_stats.alloc_failed++; 7046 return false; 7047 } 7048 7049 bi->dma = dma; 7050 bi->page = page; 7051 bi->page_offset = 0; 7052 7053 return true; 7054} 7055 7056/** 7057 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7058 * @adapter: address of board private structure 7059 **/ 7060void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7061{ 7062 union e1000_adv_rx_desc *rx_desc; 7063 struct igb_rx_buffer *bi; 7064 u16 i = rx_ring->next_to_use; 7065 7066 /* nothing to do */ 7067 if (!cleaned_count) 7068 return; 7069 7070 rx_desc = IGB_RX_DESC(rx_ring, i); 7071 bi = &rx_ring->rx_buffer_info[i]; 7072 i -= rx_ring->count; 7073 7074 do { 7075 if (!igb_alloc_mapped_page(rx_ring, bi)) 7076 break; 7077 7078 /* Refresh the desc even if buffer_addrs didn't change 7079 * because each write-back erases this info. 7080 */ 7081 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7082 7083 rx_desc++; 7084 bi++; 7085 i++; 7086 if (unlikely(!i)) { 7087 rx_desc = IGB_RX_DESC(rx_ring, 0); 7088 bi = rx_ring->rx_buffer_info; 7089 i -= rx_ring->count; 7090 } 7091 7092 /* clear the hdr_addr for the next_to_use descriptor */ 7093 rx_desc->read.hdr_addr = 0; 7094 7095 cleaned_count--; 7096 } while (cleaned_count); 7097 7098 i += rx_ring->count; 7099 7100 if (rx_ring->next_to_use != i) { 7101 /* record the next descriptor to use */ 7102 rx_ring->next_to_use = i; 7103 7104 /* update next to alloc since we have filled the ring */ 7105 rx_ring->next_to_alloc = i; 7106 7107 /* Force memory writes to complete before letting h/w 7108 * know there are new descriptors to fetch. (Only 7109 * applicable for weak-ordered memory model archs, 7110 * such as IA-64). 7111 */ 7112 wmb(); 7113 writel(i, rx_ring->tail); 7114 } 7115} 7116 7117/** 7118 * igb_mii_ioctl - 7119 * @netdev: 7120 * @ifreq: 7121 * @cmd: 7122 **/ 7123static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7124{ 7125 struct igb_adapter *adapter = netdev_priv(netdev); 7126 struct mii_ioctl_data *data = if_mii(ifr); 7127 7128 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7129 return -EOPNOTSUPP; 7130 7131 switch (cmd) { 7132 case SIOCGMIIPHY: 7133 data->phy_id = adapter->hw.phy.addr; 7134 break; 7135 case SIOCGMIIREG: 7136 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7137 &data->val_out)) 7138 return -EIO; 7139 break; 7140 case SIOCSMIIREG: 7141 default: 7142 return -EOPNOTSUPP; 7143 } 7144 return 0; 7145} 7146 7147/** 7148 * igb_ioctl - 7149 * @netdev: 7150 * @ifreq: 7151 * @cmd: 7152 **/ 7153static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7154{ 7155 switch (cmd) { 7156 case SIOCGMIIPHY: 7157 case SIOCGMIIREG: 7158 case SIOCSMIIREG: 7159 return igb_mii_ioctl(netdev, ifr, cmd); 7160 case SIOCSHWTSTAMP: 7161 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd); 7162 default: 7163 return -EOPNOTSUPP; 7164 } 7165} 7166 7167s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7168{ 7169 struct igb_adapter *adapter = hw->back; 7170 7171 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7172 return -E1000_ERR_CONFIG; 7173 7174 return 0; 7175} 7176 7177s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7178{ 7179 struct igb_adapter *adapter = hw->back; 7180 7181 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7182 return -E1000_ERR_CONFIG; 7183 7184 return 0; 7185} 7186 7187static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7188{ 7189 struct igb_adapter *adapter = netdev_priv(netdev); 7190 struct e1000_hw *hw = &adapter->hw; 7191 u32 ctrl, rctl; 7192 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7193 7194 if (enable) { 7195 /* enable VLAN tag insert/strip */ 7196 ctrl = rd32(E1000_CTRL); 7197 ctrl |= E1000_CTRL_VME; 7198 wr32(E1000_CTRL, ctrl); 7199 7200 /* Disable CFI check */ 7201 rctl = rd32(E1000_RCTL); 7202 rctl &= ~E1000_RCTL_CFIEN; 7203 wr32(E1000_RCTL, rctl); 7204 } else { 7205 /* disable VLAN tag insert/strip */ 7206 ctrl = rd32(E1000_CTRL); 7207 ctrl &= ~E1000_CTRL_VME; 7208 wr32(E1000_CTRL, ctrl); 7209 } 7210 7211 igb_rlpml_set(adapter); 7212} 7213 7214static int igb_vlan_rx_add_vid(struct net_device *netdev, 7215 __be16 proto, u16 vid) 7216{ 7217 struct igb_adapter *adapter = netdev_priv(netdev); 7218 struct e1000_hw *hw = &adapter->hw; 7219 int pf_id = adapter->vfs_allocated_count; 7220 7221 /* attempt to add filter to vlvf array */ 7222 igb_vlvf_set(adapter, vid, true, pf_id); 7223 7224 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7225 igb_vfta_set(hw, vid, true); 7226 7227 set_bit(vid, adapter->active_vlans); 7228 7229 return 0; 7230} 7231 7232static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7233 __be16 proto, u16 vid) 7234{ 7235 struct igb_adapter *adapter = netdev_priv(netdev); 7236 struct e1000_hw *hw = &adapter->hw; 7237 int pf_id = adapter->vfs_allocated_count; 7238 s32 err; 7239 7240 /* remove vlan from VLVF table array */ 7241 err = igb_vlvf_set(adapter, vid, false, pf_id); 7242 7243 /* if vid was not present in VLVF just remove it from table */ 7244 if (err) 7245 igb_vfta_set(hw, vid, false); 7246 7247 clear_bit(vid, adapter->active_vlans); 7248 7249 return 0; 7250} 7251 7252static void igb_restore_vlan(struct igb_adapter *adapter) 7253{ 7254 u16 vid; 7255 7256 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7257 7258 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 7259 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7260} 7261 7262int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7263{ 7264 struct pci_dev *pdev = adapter->pdev; 7265 struct e1000_mac_info *mac = &adapter->hw.mac; 7266 7267 mac->autoneg = 0; 7268 7269 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7270 * for the switch() below to work 7271 */ 7272 if ((spd & 1) || (dplx & ~1)) 7273 goto err_inval; 7274 7275 /* Fiber NIC's only allow 1000 gbps Full duplex 7276 * and 100Mbps Full duplex for 100baseFx sfp 7277 */ 7278 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7279 switch (spd + dplx) { 7280 case SPEED_10 + DUPLEX_HALF: 7281 case SPEED_10 + DUPLEX_FULL: 7282 case SPEED_100 + DUPLEX_HALF: 7283 goto err_inval; 7284 default: 7285 break; 7286 } 7287 } 7288 7289 switch (spd + dplx) { 7290 case SPEED_10 + DUPLEX_HALF: 7291 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7292 break; 7293 case SPEED_10 + DUPLEX_FULL: 7294 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7295 break; 7296 case SPEED_100 + DUPLEX_HALF: 7297 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7298 break; 7299 case SPEED_100 + DUPLEX_FULL: 7300 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7301 break; 7302 case SPEED_1000 + DUPLEX_FULL: 7303 mac->autoneg = 1; 7304 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7305 break; 7306 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7307 default: 7308 goto err_inval; 7309 } 7310 7311 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7312 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7313 7314 return 0; 7315 7316err_inval: 7317 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7318 return -EINVAL; 7319} 7320 7321static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7322 bool runtime) 7323{ 7324 struct net_device *netdev = pci_get_drvdata(pdev); 7325 struct igb_adapter *adapter = netdev_priv(netdev); 7326 struct e1000_hw *hw = &adapter->hw; 7327 u32 ctrl, rctl, status; 7328 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7329#ifdef CONFIG_PM 7330 int retval = 0; 7331#endif 7332 7333 netif_device_detach(netdev); 7334 7335 if (netif_running(netdev)) 7336 __igb_close(netdev, true); 7337 7338 igb_clear_interrupt_scheme(adapter); 7339 7340#ifdef CONFIG_PM 7341 retval = pci_save_state(pdev); 7342 if (retval) 7343 return retval; 7344#endif 7345 7346 status = rd32(E1000_STATUS); 7347 if (status & E1000_STATUS_LU) 7348 wufc &= ~E1000_WUFC_LNKC; 7349 7350 if (wufc) { 7351 igb_setup_rctl(adapter); 7352 igb_set_rx_mode(netdev); 7353 7354 /* turn on all-multi mode if wake on multicast is enabled */ 7355 if (wufc & E1000_WUFC_MC) { 7356 rctl = rd32(E1000_RCTL); 7357 rctl |= E1000_RCTL_MPE; 7358 wr32(E1000_RCTL, rctl); 7359 } 7360 7361 ctrl = rd32(E1000_CTRL); 7362 /* advertise wake from D3Cold */ 7363 #define E1000_CTRL_ADVD3WUC 0x00100000 7364 /* phy power management enable */ 7365 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7366 ctrl |= E1000_CTRL_ADVD3WUC; 7367 wr32(E1000_CTRL, ctrl); 7368 7369 /* Allow time for pending master requests to run */ 7370 igb_disable_pcie_master(hw); 7371 7372 wr32(E1000_WUC, E1000_WUC_PME_EN); 7373 wr32(E1000_WUFC, wufc); 7374 } else { 7375 wr32(E1000_WUC, 0); 7376 wr32(E1000_WUFC, 0); 7377 } 7378 7379 *enable_wake = wufc || adapter->en_mng_pt; 7380 if (!*enable_wake) 7381 igb_power_down_link(adapter); 7382 else 7383 igb_power_up_link(adapter); 7384 7385 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7386 * would have already happened in close and is redundant. 7387 */ 7388 igb_release_hw_control(adapter); 7389 7390 pci_disable_device(pdev); 7391 7392 return 0; 7393} 7394 7395#ifdef CONFIG_PM 7396#ifdef CONFIG_PM_SLEEP 7397static int igb_suspend(struct device *dev) 7398{ 7399 int retval; 7400 bool wake; 7401 struct pci_dev *pdev = to_pci_dev(dev); 7402 7403 retval = __igb_shutdown(pdev, &wake, 0); 7404 if (retval) 7405 return retval; 7406 7407 if (wake) { 7408 pci_prepare_to_sleep(pdev); 7409 } else { 7410 pci_wake_from_d3(pdev, false); 7411 pci_set_power_state(pdev, PCI_D3hot); 7412 } 7413 7414 return 0; 7415} 7416#endif /* CONFIG_PM_SLEEP */ 7417 7418static int igb_resume(struct device *dev) 7419{ 7420 struct pci_dev *pdev = to_pci_dev(dev); 7421 struct net_device *netdev = pci_get_drvdata(pdev); 7422 struct igb_adapter *adapter = netdev_priv(netdev); 7423 struct e1000_hw *hw = &adapter->hw; 7424 u32 err; 7425 7426 pci_set_power_state(pdev, PCI_D0); 7427 pci_restore_state(pdev); 7428 pci_save_state(pdev); 7429 7430 err = pci_enable_device_mem(pdev); 7431 if (err) { 7432 dev_err(&pdev->dev, 7433 "igb: Cannot enable PCI device from suspend\n"); 7434 return err; 7435 } 7436 pci_set_master(pdev); 7437 7438 pci_enable_wake(pdev, PCI_D3hot, 0); 7439 pci_enable_wake(pdev, PCI_D3cold, 0); 7440 7441 if (igb_init_interrupt_scheme(adapter, true)) { 7442 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7443 return -ENOMEM; 7444 } 7445 7446 igb_reset(adapter); 7447 7448 /* let the f/w know that the h/w is now under the control of the 7449 * driver. 7450 */ 7451 igb_get_hw_control(adapter); 7452 7453 wr32(E1000_WUS, ~0); 7454 7455 if (netdev->flags & IFF_UP) { 7456 rtnl_lock(); 7457 err = __igb_open(netdev, true); 7458 rtnl_unlock(); 7459 if (err) 7460 return err; 7461 } 7462 7463 netif_device_attach(netdev); 7464 return 0; 7465} 7466 7467#ifdef CONFIG_PM_RUNTIME 7468static int igb_runtime_idle(struct device *dev) 7469{ 7470 struct pci_dev *pdev = to_pci_dev(dev); 7471 struct net_device *netdev = pci_get_drvdata(pdev); 7472 struct igb_adapter *adapter = netdev_priv(netdev); 7473 7474 if (!igb_has_link(adapter)) 7475 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7476 7477 return -EBUSY; 7478} 7479 7480static int igb_runtime_suspend(struct device *dev) 7481{ 7482 struct pci_dev *pdev = to_pci_dev(dev); 7483 int retval; 7484 bool wake; 7485 7486 retval = __igb_shutdown(pdev, &wake, 1); 7487 if (retval) 7488 return retval; 7489 7490 if (wake) { 7491 pci_prepare_to_sleep(pdev); 7492 } else { 7493 pci_wake_from_d3(pdev, false); 7494 pci_set_power_state(pdev, PCI_D3hot); 7495 } 7496 7497 return 0; 7498} 7499 7500static int igb_runtime_resume(struct device *dev) 7501{ 7502 return igb_resume(dev); 7503} 7504#endif /* CONFIG_PM_RUNTIME */ 7505#endif 7506 7507static void igb_shutdown(struct pci_dev *pdev) 7508{ 7509 bool wake; 7510 7511 __igb_shutdown(pdev, &wake, 0); 7512 7513 if (system_state == SYSTEM_POWER_OFF) { 7514 pci_wake_from_d3(pdev, wake); 7515 pci_set_power_state(pdev, PCI_D3hot); 7516 } 7517} 7518 7519#ifdef CONFIG_PCI_IOV 7520static int igb_sriov_reinit(struct pci_dev *dev) 7521{ 7522 struct net_device *netdev = pci_get_drvdata(dev); 7523 struct igb_adapter *adapter = netdev_priv(netdev); 7524 struct pci_dev *pdev = adapter->pdev; 7525 7526 rtnl_lock(); 7527 7528 if (netif_running(netdev)) 7529 igb_close(netdev); 7530 7531 igb_clear_interrupt_scheme(adapter); 7532 7533 igb_init_queue_configuration(adapter); 7534 7535 if (igb_init_interrupt_scheme(adapter, true)) { 7536 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7537 return -ENOMEM; 7538 } 7539 7540 if (netif_running(netdev)) 7541 igb_open(netdev); 7542 7543 rtnl_unlock(); 7544 7545 return 0; 7546} 7547 7548static int igb_pci_disable_sriov(struct pci_dev *dev) 7549{ 7550 int err = igb_disable_sriov(dev); 7551 7552 if (!err) 7553 err = igb_sriov_reinit(dev); 7554 7555 return err; 7556} 7557 7558static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7559{ 7560 int err = igb_enable_sriov(dev, num_vfs); 7561 7562 if (err) 7563 goto out; 7564 7565 err = igb_sriov_reinit(dev); 7566 if (!err) 7567 return num_vfs; 7568 7569out: 7570 return err; 7571} 7572 7573#endif 7574static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7575{ 7576#ifdef CONFIG_PCI_IOV 7577 if (num_vfs == 0) 7578 return igb_pci_disable_sriov(dev); 7579 else 7580 return igb_pci_enable_sriov(dev, num_vfs); 7581#endif 7582 return 0; 7583} 7584 7585#ifdef CONFIG_NET_POLL_CONTROLLER 7586/* Polling 'interrupt' - used by things like netconsole to send skbs 7587 * without having to re-enable interrupts. It's not called while 7588 * the interrupt routine is executing. 7589 */ 7590static void igb_netpoll(struct net_device *netdev) 7591{ 7592 struct igb_adapter *adapter = netdev_priv(netdev); 7593 struct e1000_hw *hw = &adapter->hw; 7594 struct igb_q_vector *q_vector; 7595 int i; 7596 7597 for (i = 0; i < adapter->num_q_vectors; i++) { 7598 q_vector = adapter->q_vector[i]; 7599 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7600 wr32(E1000_EIMC, q_vector->eims_value); 7601 else 7602 igb_irq_disable(adapter); 7603 napi_schedule(&q_vector->napi); 7604 } 7605} 7606#endif /* CONFIG_NET_POLL_CONTROLLER */ 7607 7608/** 7609 * igb_io_error_detected - called when PCI error is detected 7610 * @pdev: Pointer to PCI device 7611 * @state: The current pci connection state 7612 * 7613 * This function is called after a PCI bus error affecting 7614 * this device has been detected. 7615 **/ 7616static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7617 pci_channel_state_t state) 7618{ 7619 struct net_device *netdev = pci_get_drvdata(pdev); 7620 struct igb_adapter *adapter = netdev_priv(netdev); 7621 7622 netif_device_detach(netdev); 7623 7624 if (state == pci_channel_io_perm_failure) 7625 return PCI_ERS_RESULT_DISCONNECT; 7626 7627 if (netif_running(netdev)) 7628 igb_down(adapter); 7629 pci_disable_device(pdev); 7630 7631 /* Request a slot slot reset. */ 7632 return PCI_ERS_RESULT_NEED_RESET; 7633} 7634 7635/** 7636 * igb_io_slot_reset - called after the pci bus has been reset. 7637 * @pdev: Pointer to PCI device 7638 * 7639 * Restart the card from scratch, as if from a cold-boot. Implementation 7640 * resembles the first-half of the igb_resume routine. 7641 **/ 7642static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 7643{ 7644 struct net_device *netdev = pci_get_drvdata(pdev); 7645 struct igb_adapter *adapter = netdev_priv(netdev); 7646 struct e1000_hw *hw = &adapter->hw; 7647 pci_ers_result_t result; 7648 int err; 7649 7650 if (pci_enable_device_mem(pdev)) { 7651 dev_err(&pdev->dev, 7652 "Cannot re-enable PCI device after reset.\n"); 7653 result = PCI_ERS_RESULT_DISCONNECT; 7654 } else { 7655 pci_set_master(pdev); 7656 pci_restore_state(pdev); 7657 pci_save_state(pdev); 7658 7659 pci_enable_wake(pdev, PCI_D3hot, 0); 7660 pci_enable_wake(pdev, PCI_D3cold, 0); 7661 7662 igb_reset(adapter); 7663 wr32(E1000_WUS, ~0); 7664 result = PCI_ERS_RESULT_RECOVERED; 7665 } 7666 7667 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7668 if (err) { 7669 dev_err(&pdev->dev, 7670 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7671 err); 7672 /* non-fatal, continue */ 7673 } 7674 7675 return result; 7676} 7677 7678/** 7679 * igb_io_resume - called when traffic can start flowing again. 7680 * @pdev: Pointer to PCI device 7681 * 7682 * This callback is called when the error recovery driver tells us that 7683 * its OK to resume normal operation. Implementation resembles the 7684 * second-half of the igb_resume routine. 7685 */ 7686static void igb_io_resume(struct pci_dev *pdev) 7687{ 7688 struct net_device *netdev = pci_get_drvdata(pdev); 7689 struct igb_adapter *adapter = netdev_priv(netdev); 7690 7691 if (netif_running(netdev)) { 7692 if (igb_up(adapter)) { 7693 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7694 return; 7695 } 7696 } 7697 7698 netif_device_attach(netdev); 7699 7700 /* let the f/w know that the h/w is now under the control of the 7701 * driver. 7702 */ 7703 igb_get_hw_control(adapter); 7704} 7705 7706static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7707 u8 qsel) 7708{ 7709 u32 rar_low, rar_high; 7710 struct e1000_hw *hw = &adapter->hw; 7711 7712 /* HW expects these in little endian so we reverse the byte order 7713 * from network order (big endian) to little endian 7714 */ 7715 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 7716 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 7717 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 7718 7719 /* Indicate to hardware the Address is Valid. */ 7720 rar_high |= E1000_RAH_AV; 7721 7722 if (hw->mac.type == e1000_82575) 7723 rar_high |= E1000_RAH_POOL_1 * qsel; 7724 else 7725 rar_high |= E1000_RAH_POOL_1 << qsel; 7726 7727 wr32(E1000_RAL(index), rar_low); 7728 wrfl(); 7729 wr32(E1000_RAH(index), rar_high); 7730 wrfl(); 7731} 7732 7733static int igb_set_vf_mac(struct igb_adapter *adapter, 7734 int vf, unsigned char *mac_addr) 7735{ 7736 struct e1000_hw *hw = &adapter->hw; 7737 /* VF MAC addresses start at end of receive addresses and moves 7738 * towards the first, as a result a collision should not be possible 7739 */ 7740 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7741 7742 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7743 7744 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7745 7746 return 0; 7747} 7748 7749static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7750{ 7751 struct igb_adapter *adapter = netdev_priv(netdev); 7752 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7753 return -EINVAL; 7754 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7755 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7756 dev_info(&adapter->pdev->dev, 7757 "Reload the VF driver to make this change effective."); 7758 if (test_bit(__IGB_DOWN, &adapter->state)) { 7759 dev_warn(&adapter->pdev->dev, 7760 "The VF MAC address has been set, but the PF device is not up.\n"); 7761 dev_warn(&adapter->pdev->dev, 7762 "Bring the PF device up before attempting to use the VF device.\n"); 7763 } 7764 return igb_set_vf_mac(adapter, vf, mac); 7765} 7766 7767static int igb_link_mbps(int internal_link_speed) 7768{ 7769 switch (internal_link_speed) { 7770 case SPEED_100: 7771 return 100; 7772 case SPEED_1000: 7773 return 1000; 7774 default: 7775 return 0; 7776 } 7777} 7778 7779static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7780 int link_speed) 7781{ 7782 int rf_dec, rf_int; 7783 u32 bcnrc_val; 7784 7785 if (tx_rate != 0) { 7786 /* Calculate the rate factor values to set */ 7787 rf_int = link_speed / tx_rate; 7788 rf_dec = (link_speed - (rf_int * tx_rate)); 7789 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / 7790 tx_rate; 7791 7792 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7793 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 7794 E1000_RTTBCNRC_RF_INT_MASK); 7795 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7796 } else { 7797 bcnrc_val = 0; 7798 } 7799 7800 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7801 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7802 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7803 */ 7804 wr32(E1000_RTTBCNRM, 0x14); 7805 wr32(E1000_RTTBCNRC, bcnrc_val); 7806} 7807 7808static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7809{ 7810 int actual_link_speed, i; 7811 bool reset_rate = false; 7812 7813 /* VF TX rate limit was not set or not supported */ 7814 if ((adapter->vf_rate_link_speed == 0) || 7815 (adapter->hw.mac.type != e1000_82576)) 7816 return; 7817 7818 actual_link_speed = igb_link_mbps(adapter->link_speed); 7819 if (actual_link_speed != adapter->vf_rate_link_speed) { 7820 reset_rate = true; 7821 adapter->vf_rate_link_speed = 0; 7822 dev_info(&adapter->pdev->dev, 7823 "Link speed has been changed. VF Transmit rate is disabled\n"); 7824 } 7825 7826 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7827 if (reset_rate) 7828 adapter->vf_data[i].tx_rate = 0; 7829 7830 igb_set_vf_rate_limit(&adapter->hw, i, 7831 adapter->vf_data[i].tx_rate, 7832 actual_link_speed); 7833 } 7834} 7835 7836static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) 7837{ 7838 struct igb_adapter *adapter = netdev_priv(netdev); 7839 struct e1000_hw *hw = &adapter->hw; 7840 int actual_link_speed; 7841 7842 if (hw->mac.type != e1000_82576) 7843 return -EOPNOTSUPP; 7844 7845 actual_link_speed = igb_link_mbps(adapter->link_speed); 7846 if ((vf >= adapter->vfs_allocated_count) || 7847 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7848 (tx_rate < 0) || (tx_rate > actual_link_speed)) 7849 return -EINVAL; 7850 7851 adapter->vf_rate_link_speed = actual_link_speed; 7852 adapter->vf_data[vf].tx_rate = (u16)tx_rate; 7853 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); 7854 7855 return 0; 7856} 7857 7858static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 7859 bool setting) 7860{ 7861 struct igb_adapter *adapter = netdev_priv(netdev); 7862 struct e1000_hw *hw = &adapter->hw; 7863 u32 reg_val, reg_offset; 7864 7865 if (!adapter->vfs_allocated_count) 7866 return -EOPNOTSUPP; 7867 7868 if (vf >= adapter->vfs_allocated_count) 7869 return -EINVAL; 7870 7871 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 7872 reg_val = rd32(reg_offset); 7873 if (setting) 7874 reg_val |= ((1 << vf) | 7875 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7876 else 7877 reg_val &= ~((1 << vf) | 7878 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7879 wr32(reg_offset, reg_val); 7880 7881 adapter->vf_data[vf].spoofchk_enabled = setting; 7882 return E1000_SUCCESS; 7883} 7884 7885static int igb_ndo_get_vf_config(struct net_device *netdev, 7886 int vf, struct ifla_vf_info *ivi) 7887{ 7888 struct igb_adapter *adapter = netdev_priv(netdev); 7889 if (vf >= adapter->vfs_allocated_count) 7890 return -EINVAL; 7891 ivi->vf = vf; 7892 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7893 ivi->tx_rate = adapter->vf_data[vf].tx_rate; 7894 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7895 ivi->qos = adapter->vf_data[vf].pf_qos; 7896 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 7897 return 0; 7898} 7899 7900static void igb_vmm_control(struct igb_adapter *adapter) 7901{ 7902 struct e1000_hw *hw = &adapter->hw; 7903 u32 reg; 7904 7905 switch (hw->mac.type) { 7906 case e1000_82575: 7907 case e1000_i210: 7908 case e1000_i211: 7909 case e1000_i354: 7910 default: 7911 /* replication is not supported for 82575 */ 7912 return; 7913 case e1000_82576: 7914 /* notify HW that the MAC is adding vlan tags */ 7915 reg = rd32(E1000_DTXCTL); 7916 reg |= E1000_DTXCTL_VLAN_ADDED; 7917 wr32(E1000_DTXCTL, reg); 7918 case e1000_82580: 7919 /* enable replication vlan tag stripping */ 7920 reg = rd32(E1000_RPLOLR); 7921 reg |= E1000_RPLOLR_STRVLAN; 7922 wr32(E1000_RPLOLR, reg); 7923 case e1000_i350: 7924 /* none of the above registers are supported by i350 */ 7925 break; 7926 } 7927 7928 if (adapter->vfs_allocated_count) { 7929 igb_vmdq_set_loopback_pf(hw, true); 7930 igb_vmdq_set_replication_pf(hw, true); 7931 igb_vmdq_set_anti_spoofing_pf(hw, true, 7932 adapter->vfs_allocated_count); 7933 } else { 7934 igb_vmdq_set_loopback_pf(hw, false); 7935 igb_vmdq_set_replication_pf(hw, false); 7936 } 7937} 7938 7939static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7940{ 7941 struct e1000_hw *hw = &adapter->hw; 7942 u32 dmac_thr; 7943 u16 hwm; 7944 7945 if (hw->mac.type > e1000_82580) { 7946 if (adapter->flags & IGB_FLAG_DMAC) { 7947 u32 reg; 7948 7949 /* force threshold to 0. */ 7950 wr32(E1000_DMCTXTH, 0); 7951 7952 /* DMA Coalescing high water mark needs to be greater 7953 * than the Rx threshold. Set hwm to PBA - max frame 7954 * size in 16B units, capping it at PBA - 6KB. 7955 */ 7956 hwm = 64 * pba - adapter->max_frame_size / 16; 7957 if (hwm < 64 * (pba - 6)) 7958 hwm = 64 * (pba - 6); 7959 reg = rd32(E1000_FCRTC); 7960 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 7961 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 7962 & E1000_FCRTC_RTH_COAL_MASK); 7963 wr32(E1000_FCRTC, reg); 7964 7965 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 7966 * frame size, capping it at PBA - 10KB. 7967 */ 7968 dmac_thr = pba - adapter->max_frame_size / 512; 7969 if (dmac_thr < pba - 10) 7970 dmac_thr = pba - 10; 7971 reg = rd32(E1000_DMACR); 7972 reg &= ~E1000_DMACR_DMACTHR_MASK; 7973 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 7974 & E1000_DMACR_DMACTHR_MASK); 7975 7976 /* transition to L0x or L1 if available..*/ 7977 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 7978 7979 /* watchdog timer= +-1000 usec in 32usec intervals */ 7980 reg |= (1000 >> 5); 7981 7982 /* Disable BMC-to-OS Watchdog Enable */ 7983 if (hw->mac.type != e1000_i354) 7984 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 7985 7986 wr32(E1000_DMACR, reg); 7987 7988 /* no lower threshold to disable 7989 * coalescing(smart fifb)-UTRESH=0 7990 */ 7991 wr32(E1000_DMCRTRH, 0); 7992 7993 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 7994 7995 wr32(E1000_DMCTLX, reg); 7996 7997 /* free space in tx packet buffer to wake from 7998 * DMA coal 7999 */ 8000 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8001 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8002 8003 /* make low power state decision controlled 8004 * by DMA coal 8005 */ 8006 reg = rd32(E1000_PCIEMISC); 8007 reg &= ~E1000_PCIEMISC_LX_DECISION; 8008 wr32(E1000_PCIEMISC, reg); 8009 } /* endif adapter->dmac is not disabled */ 8010 } else if (hw->mac.type == e1000_82580) { 8011 u32 reg = rd32(E1000_PCIEMISC); 8012 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8013 wr32(E1000_DMACR, 0); 8014 } 8015} 8016 8017/** 8018 * igb_read_i2c_byte - Reads 8 bit word over I2C 8019 * @hw: pointer to hardware structure 8020 * @byte_offset: byte offset to read 8021 * @dev_addr: device address 8022 * @data: value read 8023 * 8024 * Performs byte read operation over I2C interface at 8025 * a specified device address. 8026 **/ 8027s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8028 u8 dev_addr, u8 *data) 8029{ 8030 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8031 struct i2c_client *this_client = adapter->i2c_client; 8032 s32 status; 8033 u16 swfw_mask = 0; 8034 8035 if (!this_client) 8036 return E1000_ERR_I2C; 8037 8038 swfw_mask = E1000_SWFW_PHY0_SM; 8039 8040 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 8041 != E1000_SUCCESS) 8042 return E1000_ERR_SWFW_SYNC; 8043 8044 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8045 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8046 8047 if (status < 0) 8048 return E1000_ERR_I2C; 8049 else { 8050 *data = status; 8051 return E1000_SUCCESS; 8052 } 8053} 8054 8055/** 8056 * igb_write_i2c_byte - Writes 8 bit word over I2C 8057 * @hw: pointer to hardware structure 8058 * @byte_offset: byte offset to write 8059 * @dev_addr: device address 8060 * @data: value to write 8061 * 8062 * Performs byte write operation over I2C interface at 8063 * a specified device address. 8064 **/ 8065s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8066 u8 dev_addr, u8 data) 8067{ 8068 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8069 struct i2c_client *this_client = adapter->i2c_client; 8070 s32 status; 8071 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8072 8073 if (!this_client) 8074 return E1000_ERR_I2C; 8075 8076 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) 8077 return E1000_ERR_SWFW_SYNC; 8078 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8079 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8080 8081 if (status) 8082 return E1000_ERR_I2C; 8083 else 8084 return E1000_SUCCESS; 8085 8086} 8087 8088int igb_reinit_queues(struct igb_adapter *adapter) 8089{ 8090 struct net_device *netdev = adapter->netdev; 8091 struct pci_dev *pdev = adapter->pdev; 8092 int err = 0; 8093 8094 if (netif_running(netdev)) 8095 igb_close(netdev); 8096 8097 igb_reset_interrupt_capability(adapter); 8098 8099 if (igb_init_interrupt_scheme(adapter, true)) { 8100 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8101 return -ENOMEM; 8102 } 8103 8104 if (netif_running(netdev)) 8105 err = igb_open(netdev); 8106 8107 return err; 8108} 8109/* igb_main.c */ 8110