igb_main.c revision 6ab5f7b2981e842e318ff48c708aaaa2a5a6a43e
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25*******************************************************************************/ 26 27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 28 29#include <linux/module.h> 30#include <linux/types.h> 31#include <linux/init.h> 32#include <linux/bitops.h> 33#include <linux/vmalloc.h> 34#include <linux/pagemap.h> 35#include <linux/netdevice.h> 36#include <linux/ipv6.h> 37#include <linux/slab.h> 38#include <net/checksum.h> 39#include <net/ip6_checksum.h> 40#include <linux/net_tstamp.h> 41#include <linux/mii.h> 42#include <linux/ethtool.h> 43#include <linux/if.h> 44#include <linux/if_vlan.h> 45#include <linux/pci.h> 46#include <linux/pci-aspm.h> 47#include <linux/delay.h> 48#include <linux/interrupt.h> 49#include <linux/ip.h> 50#include <linux/tcp.h> 51#include <linux/sctp.h> 52#include <linux/if_ether.h> 53#include <linux/aer.h> 54#include <linux/prefetch.h> 55#include <linux/pm_runtime.h> 56#ifdef CONFIG_IGB_DCA 57#include <linux/dca.h> 58#endif 59#include <linux/i2c.h> 60#include "igb.h" 61 62#define MAJ 5 63#define MIN 0 64#define BUILD 5 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 66__stringify(BUILD) "-k" 67char igb_driver_name[] = "igb"; 68char igb_driver_version[] = DRV_VERSION; 69static const char igb_driver_string[] = 70 "Intel(R) Gigabit Ethernet Network Driver"; 71static const char igb_copyright[] = 72 "Copyright (c) 2007-2014 Intel Corporation."; 73 74static const struct e1000_info *igb_info_tbl[] = { 75 [board_82575] = &e1000_82575_info, 76}; 77 78static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 114 /* required last entry */ 115 {0, } 116}; 117 118MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 119 120void igb_reset(struct igb_adapter *); 121static int igb_setup_all_tx_resources(struct igb_adapter *); 122static int igb_setup_all_rx_resources(struct igb_adapter *); 123static void igb_free_all_tx_resources(struct igb_adapter *); 124static void igb_free_all_rx_resources(struct igb_adapter *); 125static void igb_setup_mrqc(struct igb_adapter *); 126static int igb_probe(struct pci_dev *, const struct pci_device_id *); 127static void igb_remove(struct pci_dev *pdev); 128static int igb_sw_init(struct igb_adapter *); 129static int igb_open(struct net_device *); 130static int igb_close(struct net_device *); 131static void igb_configure(struct igb_adapter *); 132static void igb_configure_tx(struct igb_adapter *); 133static void igb_configure_rx(struct igb_adapter *); 134static void igb_clean_all_tx_rings(struct igb_adapter *); 135static void igb_clean_all_rx_rings(struct igb_adapter *); 136static void igb_clean_tx_ring(struct igb_ring *); 137static void igb_clean_rx_ring(struct igb_ring *); 138static void igb_set_rx_mode(struct net_device *); 139static void igb_update_phy_info(unsigned long); 140static void igb_watchdog(unsigned long); 141static void igb_watchdog_task(struct work_struct *); 142static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 143static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 144 struct rtnl_link_stats64 *stats); 145static int igb_change_mtu(struct net_device *, int); 146static int igb_set_mac(struct net_device *, void *); 147static void igb_set_uta(struct igb_adapter *adapter); 148static irqreturn_t igb_intr(int irq, void *); 149static irqreturn_t igb_intr_msi(int irq, void *); 150static irqreturn_t igb_msix_other(int irq, void *); 151static irqreturn_t igb_msix_ring(int irq, void *); 152#ifdef CONFIG_IGB_DCA 153static void igb_update_dca(struct igb_q_vector *); 154static void igb_setup_dca(struct igb_adapter *); 155#endif /* CONFIG_IGB_DCA */ 156static int igb_poll(struct napi_struct *, int); 157static bool igb_clean_tx_irq(struct igb_q_vector *); 158static bool igb_clean_rx_irq(struct igb_q_vector *, int); 159static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 160static void igb_tx_timeout(struct net_device *); 161static void igb_reset_task(struct work_struct *); 162static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); 163static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 164static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 165static void igb_restore_vlan(struct igb_adapter *); 166static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 167static void igb_ping_all_vfs(struct igb_adapter *); 168static void igb_msg_task(struct igb_adapter *); 169static void igb_vmm_control(struct igb_adapter *); 170static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 171static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 172static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 173static int igb_ndo_set_vf_vlan(struct net_device *netdev, 174 int vf, u16 vlan, u8 qos); 175static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 176static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 177 bool setting); 178static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 179 struct ifla_vf_info *ivi); 180static void igb_check_vf_rate_limit(struct igb_adapter *); 181 182#ifdef CONFIG_PCI_IOV 183static int igb_vf_configure(struct igb_adapter *adapter, int vf); 184static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 185#endif 186 187#ifdef CONFIG_PM 188#ifdef CONFIG_PM_SLEEP 189static int igb_suspend(struct device *); 190#endif 191static int igb_resume(struct device *); 192#ifdef CONFIG_PM_RUNTIME 193static int igb_runtime_suspend(struct device *dev); 194static int igb_runtime_resume(struct device *dev); 195static int igb_runtime_idle(struct device *dev); 196#endif 197static const struct dev_pm_ops igb_pm_ops = { 198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 200 igb_runtime_idle) 201}; 202#endif 203static void igb_shutdown(struct pci_dev *); 204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 205#ifdef CONFIG_IGB_DCA 206static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 207static struct notifier_block dca_notifier = { 208 .notifier_call = igb_notify_dca, 209 .next = NULL, 210 .priority = 0 211}; 212#endif 213#ifdef CONFIG_NET_POLL_CONTROLLER 214/* for netdump / net console */ 215static void igb_netpoll(struct net_device *); 216#endif 217#ifdef CONFIG_PCI_IOV 218static unsigned int max_vfs = 0; 219module_param(max_vfs, uint, 0); 220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " 221 "per physical function"); 222#endif /* CONFIG_PCI_IOV */ 223 224static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 225 pci_channel_state_t); 226static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 227static void igb_io_resume(struct pci_dev *); 228 229static const struct pci_error_handlers igb_err_handler = { 230 .error_detected = igb_io_error_detected, 231 .slot_reset = igb_io_slot_reset, 232 .resume = igb_io_resume, 233}; 234 235static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 236 237static struct pci_driver igb_driver = { 238 .name = igb_driver_name, 239 .id_table = igb_pci_tbl, 240 .probe = igb_probe, 241 .remove = igb_remove, 242#ifdef CONFIG_PM 243 .driver.pm = &igb_pm_ops, 244#endif 245 .shutdown = igb_shutdown, 246 .sriov_configure = igb_pci_sriov_configure, 247 .err_handler = &igb_err_handler 248}; 249 250MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 251MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 252MODULE_LICENSE("GPL"); 253MODULE_VERSION(DRV_VERSION); 254 255#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 256static int debug = -1; 257module_param(debug, int, 0); 258MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 259 260struct igb_reg_info { 261 u32 ofs; 262 char *name; 263}; 264 265static const struct igb_reg_info igb_reg_info_tbl[] = { 266 267 /* General Registers */ 268 {E1000_CTRL, "CTRL"}, 269 {E1000_STATUS, "STATUS"}, 270 {E1000_CTRL_EXT, "CTRL_EXT"}, 271 272 /* Interrupt Registers */ 273 {E1000_ICR, "ICR"}, 274 275 /* RX Registers */ 276 {E1000_RCTL, "RCTL"}, 277 {E1000_RDLEN(0), "RDLEN"}, 278 {E1000_RDH(0), "RDH"}, 279 {E1000_RDT(0), "RDT"}, 280 {E1000_RXDCTL(0), "RXDCTL"}, 281 {E1000_RDBAL(0), "RDBAL"}, 282 {E1000_RDBAH(0), "RDBAH"}, 283 284 /* TX Registers */ 285 {E1000_TCTL, "TCTL"}, 286 {E1000_TDBAL(0), "TDBAL"}, 287 {E1000_TDBAH(0), "TDBAH"}, 288 {E1000_TDLEN(0), "TDLEN"}, 289 {E1000_TDH(0), "TDH"}, 290 {E1000_TDT(0), "TDT"}, 291 {E1000_TXDCTL(0), "TXDCTL"}, 292 {E1000_TDFH, "TDFH"}, 293 {E1000_TDFT, "TDFT"}, 294 {E1000_TDFHS, "TDFHS"}, 295 {E1000_TDFPC, "TDFPC"}, 296 297 /* List Terminator */ 298 {} 299}; 300 301/* igb_regdump - register printout routine */ 302static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 303{ 304 int n = 0; 305 char rname[16]; 306 u32 regs[8]; 307 308 switch (reginfo->ofs) { 309 case E1000_RDLEN(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDLEN(n)); 312 break; 313 case E1000_RDH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDH(n)); 316 break; 317 case E1000_RDT(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_RDT(n)); 320 break; 321 case E1000_RXDCTL(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_RXDCTL(n)); 324 break; 325 case E1000_RDBAL(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_RDBAL(n)); 328 break; 329 case E1000_RDBAH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_RDBAH(n)); 332 break; 333 case E1000_TDBAL(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_RDBAL(n)); 336 break; 337 case E1000_TDBAH(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TDBAH(n)); 340 break; 341 case E1000_TDLEN(0): 342 for (n = 0; n < 4; n++) 343 regs[n] = rd32(E1000_TDLEN(n)); 344 break; 345 case E1000_TDH(0): 346 for (n = 0; n < 4; n++) 347 regs[n] = rd32(E1000_TDH(n)); 348 break; 349 case E1000_TDT(0): 350 for (n = 0; n < 4; n++) 351 regs[n] = rd32(E1000_TDT(n)); 352 break; 353 case E1000_TXDCTL(0): 354 for (n = 0; n < 4; n++) 355 regs[n] = rd32(E1000_TXDCTL(n)); 356 break; 357 default: 358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 359 return; 360 } 361 362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 364 regs[2], regs[3]); 365} 366 367/* igb_dump - Print registers, Tx-rings and Rx-rings */ 368static void igb_dump(struct igb_adapter *adapter) 369{ 370 struct net_device *netdev = adapter->netdev; 371 struct e1000_hw *hw = &adapter->hw; 372 struct igb_reg_info *reginfo; 373 struct igb_ring *tx_ring; 374 union e1000_adv_tx_desc *tx_desc; 375 struct my_u0 { u64 a; u64 b; } *u0; 376 struct igb_ring *rx_ring; 377 union e1000_adv_rx_desc *rx_desc; 378 u32 staterr; 379 u16 i, n; 380 381 if (!netif_msg_hw(adapter)) 382 return; 383 384 /* Print netdevice Info */ 385 if (netdev) { 386 dev_info(&adapter->pdev->dev, "Net device Info\n"); 387 pr_info("Device Name state trans_start " 388 "last_rx\n"); 389 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 390 netdev->state, netdev->trans_start, netdev->last_rx); 391 } 392 393 /* Print Registers */ 394 dev_info(&adapter->pdev->dev, "Register Dump\n"); 395 pr_info(" Register Name Value\n"); 396 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 397 reginfo->name; reginfo++) { 398 igb_regdump(hw, reginfo); 399 } 400 401 /* Print TX Ring Summary */ 402 if (!netdev || !netif_running(netdev)) 403 goto exit; 404 405 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 406 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 407 for (n = 0; n < adapter->num_tx_queues; n++) { 408 struct igb_tx_buffer *buffer_info; 409 tx_ring = adapter->tx_ring[n]; 410 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 411 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 412 n, tx_ring->next_to_use, tx_ring->next_to_clean, 413 (u64)dma_unmap_addr(buffer_info, dma), 414 dma_unmap_len(buffer_info, len), 415 buffer_info->next_to_watch, 416 (u64)buffer_info->time_stamp); 417 } 418 419 /* Print TX Rings */ 420 if (!netif_msg_tx_done(adapter)) 421 goto rx_ring_summary; 422 423 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 424 425 /* Transmit Descriptor Formats 426 * 427 * Advanced Transmit Descriptor 428 * +--------------------------------------------------------------+ 429 * 0 | Buffer Address [63:0] | 430 * +--------------------------------------------------------------+ 431 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 432 * +--------------------------------------------------------------+ 433 * 63 46 45 40 39 38 36 35 32 31 24 15 0 434 */ 435 436 for (n = 0; n < adapter->num_tx_queues; n++) { 437 tx_ring = adapter->tx_ring[n]; 438 pr_info("------------------------------------\n"); 439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 440 pr_info("------------------------------------\n"); 441 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] " 442 "[bi->dma ] leng ntw timestamp " 443 "bi->skb\n"); 444 445 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 446 const char *next_desc; 447 struct igb_tx_buffer *buffer_info; 448 tx_desc = IGB_TX_DESC(tx_ring, i); 449 buffer_info = &tx_ring->tx_buffer_info[i]; 450 u0 = (struct my_u0 *)tx_desc; 451 if (i == tx_ring->next_to_use && 452 i == tx_ring->next_to_clean) 453 next_desc = " NTC/U"; 454 else if (i == tx_ring->next_to_use) 455 next_desc = " NTU"; 456 else if (i == tx_ring->next_to_clean) 457 next_desc = " NTC"; 458 else 459 next_desc = ""; 460 461 pr_info("T [0x%03X] %016llX %016llX %016llX" 462 " %04X %p %016llX %p%s\n", i, 463 le64_to_cpu(u0->a), 464 le64_to_cpu(u0->b), 465 (u64)dma_unmap_addr(buffer_info, dma), 466 dma_unmap_len(buffer_info, len), 467 buffer_info->next_to_watch, 468 (u64)buffer_info->time_stamp, 469 buffer_info->skb, next_desc); 470 471 if (netif_msg_pktdata(adapter) && buffer_info->skb) 472 print_hex_dump(KERN_INFO, "", 473 DUMP_PREFIX_ADDRESS, 474 16, 1, buffer_info->skb->data, 475 dma_unmap_len(buffer_info, len), 476 true); 477 } 478 } 479 480 /* Print RX Rings Summary */ 481rx_ring_summary: 482 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 483 pr_info("Queue [NTU] [NTC]\n"); 484 for (n = 0; n < adapter->num_rx_queues; n++) { 485 rx_ring = adapter->rx_ring[n]; 486 pr_info(" %5d %5X %5X\n", 487 n, rx_ring->next_to_use, rx_ring->next_to_clean); 488 } 489 490 /* Print RX Rings */ 491 if (!netif_msg_rx_status(adapter)) 492 goto exit; 493 494 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 495 496 /* Advanced Receive Descriptor (Read) Format 497 * 63 1 0 498 * +-----------------------------------------------------+ 499 * 0 | Packet Buffer Address [63:1] |A0/NSE| 500 * +----------------------------------------------+------+ 501 * 8 | Header Buffer Address [63:1] | DD | 502 * +-----------------------------------------------------+ 503 * 504 * 505 * Advanced Receive Descriptor (Write-Back) Format 506 * 507 * 63 48 47 32 31 30 21 20 17 16 4 3 0 508 * +------------------------------------------------------+ 509 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 510 * | Checksum Ident | | | | Type | Type | 511 * +------------------------------------------------------+ 512 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 513 * +------------------------------------------------------+ 514 * 63 48 47 32 31 20 19 0 515 */ 516 517 for (n = 0; n < adapter->num_rx_queues; n++) { 518 rx_ring = adapter->rx_ring[n]; 519 pr_info("------------------------------------\n"); 520 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 521 pr_info("------------------------------------\n"); 522 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] " 523 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 524 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----" 525 "----------- [bi->skb] <-- Adv Rx Write-Back format\n"); 526 527 for (i = 0; i < rx_ring->count; i++) { 528 const char *next_desc; 529 struct igb_rx_buffer *buffer_info; 530 buffer_info = &rx_ring->rx_buffer_info[i]; 531 rx_desc = IGB_RX_DESC(rx_ring, i); 532 u0 = (struct my_u0 *)rx_desc; 533 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 534 535 if (i == rx_ring->next_to_use) 536 next_desc = " NTU"; 537 else if (i == rx_ring->next_to_clean) 538 next_desc = " NTC"; 539 else 540 next_desc = ""; 541 542 if (staterr & E1000_RXD_STAT_DD) { 543 /* Descriptor Done */ 544 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 545 "RWB", i, 546 le64_to_cpu(u0->a), 547 le64_to_cpu(u0->b), 548 next_desc); 549 } else { 550 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 551 "R ", i, 552 le64_to_cpu(u0->a), 553 le64_to_cpu(u0->b), 554 (u64)buffer_info->dma, 555 next_desc); 556 557 if (netif_msg_pktdata(adapter) && 558 buffer_info->dma && buffer_info->page) { 559 print_hex_dump(KERN_INFO, "", 560 DUMP_PREFIX_ADDRESS, 561 16, 1, 562 page_address(buffer_info->page) + 563 buffer_info->page_offset, 564 IGB_RX_BUFSZ, true); 565 } 566 } 567 } 568 } 569 570exit: 571 return; 572} 573 574/** 575 * igb_get_i2c_data - Reads the I2C SDA data bit 576 * @hw: pointer to hardware structure 577 * @i2cctl: Current value of I2CCTL register 578 * 579 * Returns the I2C data bit value 580 **/ 581static int igb_get_i2c_data(void *data) 582{ 583 struct igb_adapter *adapter = (struct igb_adapter *)data; 584 struct e1000_hw *hw = &adapter->hw; 585 s32 i2cctl = rd32(E1000_I2CPARAMS); 586 587 return ((i2cctl & E1000_I2C_DATA_IN) != 0); 588} 589 590/** 591 * igb_set_i2c_data - Sets the I2C data bit 592 * @data: pointer to hardware structure 593 * @state: I2C data value (0 or 1) to set 594 * 595 * Sets the I2C data bit 596 **/ 597static void igb_set_i2c_data(void *data, int state) 598{ 599 struct igb_adapter *adapter = (struct igb_adapter *)data; 600 struct e1000_hw *hw = &adapter->hw; 601 s32 i2cctl = rd32(E1000_I2CPARAMS); 602 603 if (state) 604 i2cctl |= E1000_I2C_DATA_OUT; 605 else 606 i2cctl &= ~E1000_I2C_DATA_OUT; 607 608 i2cctl &= ~E1000_I2C_DATA_OE_N; 609 i2cctl |= E1000_I2C_CLK_OE_N; 610 wr32(E1000_I2CPARAMS, i2cctl); 611 wrfl(); 612 613} 614 615/** 616 * igb_set_i2c_clk - Sets the I2C SCL clock 617 * @data: pointer to hardware structure 618 * @state: state to set clock 619 * 620 * Sets the I2C clock line to state 621 **/ 622static void igb_set_i2c_clk(void *data, int state) 623{ 624 struct igb_adapter *adapter = (struct igb_adapter *)data; 625 struct e1000_hw *hw = &adapter->hw; 626 s32 i2cctl = rd32(E1000_I2CPARAMS); 627 628 if (state) { 629 i2cctl |= E1000_I2C_CLK_OUT; 630 i2cctl &= ~E1000_I2C_CLK_OE_N; 631 } else { 632 i2cctl &= ~E1000_I2C_CLK_OUT; 633 i2cctl &= ~E1000_I2C_CLK_OE_N; 634 } 635 wr32(E1000_I2CPARAMS, i2cctl); 636 wrfl(); 637} 638 639/** 640 * igb_get_i2c_clk - Gets the I2C SCL clock state 641 * @data: pointer to hardware structure 642 * 643 * Gets the I2C clock state 644 **/ 645static int igb_get_i2c_clk(void *data) 646{ 647 struct igb_adapter *adapter = (struct igb_adapter *)data; 648 struct e1000_hw *hw = &adapter->hw; 649 s32 i2cctl = rd32(E1000_I2CPARAMS); 650 651 return ((i2cctl & E1000_I2C_CLK_IN) != 0); 652} 653 654static const struct i2c_algo_bit_data igb_i2c_algo = { 655 .setsda = igb_set_i2c_data, 656 .setscl = igb_set_i2c_clk, 657 .getsda = igb_get_i2c_data, 658 .getscl = igb_get_i2c_clk, 659 .udelay = 5, 660 .timeout = 20, 661}; 662 663/** 664 * igb_get_hw_dev - return device 665 * @hw: pointer to hardware structure 666 * 667 * used by hardware layer to print debugging information 668 **/ 669struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 670{ 671 struct igb_adapter *adapter = hw->back; 672 return adapter->netdev; 673} 674 675/** 676 * igb_init_module - Driver Registration Routine 677 * 678 * igb_init_module is the first routine called when the driver is 679 * loaded. All it does is register with the PCI subsystem. 680 **/ 681static int __init igb_init_module(void) 682{ 683 int ret; 684 pr_info("%s - version %s\n", 685 igb_driver_string, igb_driver_version); 686 687 pr_info("%s\n", igb_copyright); 688 689#ifdef CONFIG_IGB_DCA 690 dca_register_notify(&dca_notifier); 691#endif 692 ret = pci_register_driver(&igb_driver); 693 return ret; 694} 695 696module_init(igb_init_module); 697 698/** 699 * igb_exit_module - Driver Exit Cleanup Routine 700 * 701 * igb_exit_module is called just before the driver is removed 702 * from memory. 703 **/ 704static void __exit igb_exit_module(void) 705{ 706#ifdef CONFIG_IGB_DCA 707 dca_unregister_notify(&dca_notifier); 708#endif 709 pci_unregister_driver(&igb_driver); 710} 711 712module_exit(igb_exit_module); 713 714#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 715/** 716 * igb_cache_ring_register - Descriptor ring to register mapping 717 * @adapter: board private structure to initialize 718 * 719 * Once we know the feature-set enabled for the device, we'll cache 720 * the register offset the descriptor ring is assigned to. 721 **/ 722static void igb_cache_ring_register(struct igb_adapter *adapter) 723{ 724 int i = 0, j = 0; 725 u32 rbase_offset = adapter->vfs_allocated_count; 726 727 switch (adapter->hw.mac.type) { 728 case e1000_82576: 729 /* The queues are allocated for virtualization such that VF 0 730 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 731 * In order to avoid collision we start at the first free queue 732 * and continue consuming queues in the same sequence 733 */ 734 if (adapter->vfs_allocated_count) { 735 for (; i < adapter->rss_queues; i++) 736 adapter->rx_ring[i]->reg_idx = rbase_offset + 737 Q_IDX_82576(i); 738 } 739 case e1000_82575: 740 case e1000_82580: 741 case e1000_i350: 742 case e1000_i354: 743 case e1000_i210: 744 case e1000_i211: 745 default: 746 for (; i < adapter->num_rx_queues; i++) 747 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 748 for (; j < adapter->num_tx_queues; j++) 749 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 750 break; 751 } 752} 753 754/** 755 * igb_write_ivar - configure ivar for given MSI-X vector 756 * @hw: pointer to the HW structure 757 * @msix_vector: vector number we are allocating to a given ring 758 * @index: row index of IVAR register to write within IVAR table 759 * @offset: column offset of in IVAR, should be multiple of 8 760 * 761 * This function is intended to handle the writing of the IVAR register 762 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 763 * each containing an cause allocation for an Rx and Tx ring, and a 764 * variable number of rows depending on the number of queues supported. 765 **/ 766static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 767 int index, int offset) 768{ 769 u32 ivar = array_rd32(E1000_IVAR0, index); 770 771 /* clear any bits that are currently set */ 772 ivar &= ~((u32)0xFF << offset); 773 774 /* write vector and valid bit */ 775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 776 777 array_wr32(E1000_IVAR0, index, ivar); 778} 779 780#define IGB_N0_QUEUE -1 781static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 782{ 783 struct igb_adapter *adapter = q_vector->adapter; 784 struct e1000_hw *hw = &adapter->hw; 785 int rx_queue = IGB_N0_QUEUE; 786 int tx_queue = IGB_N0_QUEUE; 787 u32 msixbm = 0; 788 789 if (q_vector->rx.ring) 790 rx_queue = q_vector->rx.ring->reg_idx; 791 if (q_vector->tx.ring) 792 tx_queue = q_vector->tx.ring->reg_idx; 793 794 switch (hw->mac.type) { 795 case e1000_82575: 796 /* The 82575 assigns vectors using a bitmask, which matches the 797 * bitmask for the EICR/EIMS/EIMC registers. To assign one 798 * or more queues to a vector, we write the appropriate bits 799 * into the MSIXBM register for that vector. 800 */ 801 if (rx_queue > IGB_N0_QUEUE) 802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 803 if (tx_queue > IGB_N0_QUEUE) 804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 805 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 806 msixbm |= E1000_EIMS_OTHER; 807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 808 q_vector->eims_value = msixbm; 809 break; 810 case e1000_82576: 811 /* 82576 uses a table that essentially consists of 2 columns 812 * with 8 rows. The ordering is column-major so we use the 813 * lower 3 bits as the row index, and the 4th bit as the 814 * column offset. 815 */ 816 if (rx_queue > IGB_N0_QUEUE) 817 igb_write_ivar(hw, msix_vector, 818 rx_queue & 0x7, 819 (rx_queue & 0x8) << 1); 820 if (tx_queue > IGB_N0_QUEUE) 821 igb_write_ivar(hw, msix_vector, 822 tx_queue & 0x7, 823 ((tx_queue & 0x8) << 1) + 8); 824 q_vector->eims_value = 1 << msix_vector; 825 break; 826 case e1000_82580: 827 case e1000_i350: 828 case e1000_i354: 829 case e1000_i210: 830 case e1000_i211: 831 /* On 82580 and newer adapters the scheme is similar to 82576 832 * however instead of ordering column-major we have things 833 * ordered row-major. So we traverse the table by using 834 * bit 0 as the column offset, and the remaining bits as the 835 * row index. 836 */ 837 if (rx_queue > IGB_N0_QUEUE) 838 igb_write_ivar(hw, msix_vector, 839 rx_queue >> 1, 840 (rx_queue & 0x1) << 4); 841 if (tx_queue > IGB_N0_QUEUE) 842 igb_write_ivar(hw, msix_vector, 843 tx_queue >> 1, 844 ((tx_queue & 0x1) << 4) + 8); 845 q_vector->eims_value = 1 << msix_vector; 846 break; 847 default: 848 BUG(); 849 break; 850 } 851 852 /* add q_vector eims value to global eims_enable_mask */ 853 adapter->eims_enable_mask |= q_vector->eims_value; 854 855 /* configure q_vector to set itr on first interrupt */ 856 q_vector->set_itr = 1; 857} 858 859/** 860 * igb_configure_msix - Configure MSI-X hardware 861 * @adapter: board private structure to initialize 862 * 863 * igb_configure_msix sets up the hardware to properly 864 * generate MSI-X interrupts. 865 **/ 866static void igb_configure_msix(struct igb_adapter *adapter) 867{ 868 u32 tmp; 869 int i, vector = 0; 870 struct e1000_hw *hw = &adapter->hw; 871 872 adapter->eims_enable_mask = 0; 873 874 /* set vector for other causes, i.e. link changes */ 875 switch (hw->mac.type) { 876 case e1000_82575: 877 tmp = rd32(E1000_CTRL_EXT); 878 /* enable MSI-X PBA support*/ 879 tmp |= E1000_CTRL_EXT_PBA_CLR; 880 881 /* Auto-Mask interrupts upon ICR read. */ 882 tmp |= E1000_CTRL_EXT_EIAME; 883 tmp |= E1000_CTRL_EXT_IRCA; 884 885 wr32(E1000_CTRL_EXT, tmp); 886 887 /* enable msix_other interrupt */ 888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 889 adapter->eims_other = E1000_EIMS_OTHER; 890 891 break; 892 893 case e1000_82576: 894 case e1000_82580: 895 case e1000_i350: 896 case e1000_i354: 897 case e1000_i210: 898 case e1000_i211: 899 /* Turn on MSI-X capability first, or our settings 900 * won't stick. And it will take days to debug. 901 */ 902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 903 E1000_GPIE_PBA | E1000_GPIE_EIAME | 904 E1000_GPIE_NSICR); 905 906 /* enable msix_other interrupt */ 907 adapter->eims_other = 1 << vector; 908 tmp = (vector++ | E1000_IVAR_VALID) << 8; 909 910 wr32(E1000_IVAR_MISC, tmp); 911 break; 912 default: 913 /* do nothing, since nothing else supports MSI-X */ 914 break; 915 } /* switch (hw->mac.type) */ 916 917 adapter->eims_enable_mask |= adapter->eims_other; 918 919 for (i = 0; i < adapter->num_q_vectors; i++) 920 igb_assign_vector(adapter->q_vector[i], vector++); 921 922 wrfl(); 923} 924 925/** 926 * igb_request_msix - Initialize MSI-X interrupts 927 * @adapter: board private structure to initialize 928 * 929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 930 * kernel. 931 **/ 932static int igb_request_msix(struct igb_adapter *adapter) 933{ 934 struct net_device *netdev = adapter->netdev; 935 struct e1000_hw *hw = &adapter->hw; 936 int i, err = 0, vector = 0, free_vector = 0; 937 938 err = request_irq(adapter->msix_entries[vector].vector, 939 igb_msix_other, 0, netdev->name, adapter); 940 if (err) 941 goto err_out; 942 943 for (i = 0; i < adapter->num_q_vectors; i++) { 944 struct igb_q_vector *q_vector = adapter->q_vector[i]; 945 946 vector++; 947 948 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 949 950 if (q_vector->rx.ring && q_vector->tx.ring) 951 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 952 q_vector->rx.ring->queue_index); 953 else if (q_vector->tx.ring) 954 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 955 q_vector->tx.ring->queue_index); 956 else if (q_vector->rx.ring) 957 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 958 q_vector->rx.ring->queue_index); 959 else 960 sprintf(q_vector->name, "%s-unused", netdev->name); 961 962 err = request_irq(adapter->msix_entries[vector].vector, 963 igb_msix_ring, 0, q_vector->name, 964 q_vector); 965 if (err) 966 goto err_free; 967 } 968 969 igb_configure_msix(adapter); 970 return 0; 971 972err_free: 973 /* free already assigned IRQs */ 974 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 975 976 vector--; 977 for (i = 0; i < vector; i++) { 978 free_irq(adapter->msix_entries[free_vector++].vector, 979 adapter->q_vector[i]); 980 } 981err_out: 982 return err; 983} 984 985/** 986 * igb_free_q_vector - Free memory allocated for specific interrupt vector 987 * @adapter: board private structure to initialize 988 * @v_idx: Index of vector to be freed 989 * 990 * This function frees the memory allocated to the q_vector. 991 **/ 992static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 993{ 994 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 995 996 adapter->q_vector[v_idx] = NULL; 997 998 /* igb_get_stats64() might access the rings on this vector, 999 * we must wait a grace period before freeing it. 1000 */ 1001 kfree_rcu(q_vector, rcu); 1002} 1003 1004/** 1005 * igb_reset_q_vector - Reset config for interrupt vector 1006 * @adapter: board private structure to initialize 1007 * @v_idx: Index of vector to be reset 1008 * 1009 * If NAPI is enabled it will delete any references to the 1010 * NAPI struct. This is preparation for igb_free_q_vector. 1011 **/ 1012static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1013{ 1014 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1015 1016 if (q_vector->tx.ring) 1017 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1018 1019 if (q_vector->rx.ring) 1020 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; 1021 1022 netif_napi_del(&q_vector->napi); 1023 1024} 1025 1026static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1027{ 1028 int v_idx = adapter->num_q_vectors; 1029 1030 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1031 pci_disable_msix(adapter->pdev); 1032 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1033 pci_disable_msi(adapter->pdev); 1034 1035 while (v_idx--) 1036 igb_reset_q_vector(adapter, v_idx); 1037} 1038 1039/** 1040 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1041 * @adapter: board private structure to initialize 1042 * 1043 * This function frees the memory allocated to the q_vectors. In addition if 1044 * NAPI is enabled it will delete any references to the NAPI struct prior 1045 * to freeing the q_vector. 1046 **/ 1047static void igb_free_q_vectors(struct igb_adapter *adapter) 1048{ 1049 int v_idx = adapter->num_q_vectors; 1050 1051 adapter->num_tx_queues = 0; 1052 adapter->num_rx_queues = 0; 1053 adapter->num_q_vectors = 0; 1054 1055 while (v_idx--) { 1056 igb_reset_q_vector(adapter, v_idx); 1057 igb_free_q_vector(adapter, v_idx); 1058 } 1059} 1060 1061/** 1062 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1063 * @adapter: board private structure to initialize 1064 * 1065 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1066 * MSI-X interrupts allocated. 1067 */ 1068static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1069{ 1070 igb_free_q_vectors(adapter); 1071 igb_reset_interrupt_capability(adapter); 1072} 1073 1074/** 1075 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1076 * @adapter: board private structure to initialize 1077 * @msix: boolean value of MSIX capability 1078 * 1079 * Attempt to configure interrupts using the best available 1080 * capabilities of the hardware and kernel. 1081 **/ 1082static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1083{ 1084 int err; 1085 int numvecs, i; 1086 1087 if (!msix) 1088 goto msi_only; 1089 adapter->flags |= IGB_FLAG_HAS_MSIX; 1090 1091 /* Number of supported queues. */ 1092 adapter->num_rx_queues = adapter->rss_queues; 1093 if (adapter->vfs_allocated_count) 1094 adapter->num_tx_queues = 1; 1095 else 1096 adapter->num_tx_queues = adapter->rss_queues; 1097 1098 /* start with one vector for every Rx queue */ 1099 numvecs = adapter->num_rx_queues; 1100 1101 /* if Tx handler is separate add 1 for every Tx queue */ 1102 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1103 numvecs += adapter->num_tx_queues; 1104 1105 /* store the number of vectors reserved for queues */ 1106 adapter->num_q_vectors = numvecs; 1107 1108 /* add 1 vector for link status interrupts */ 1109 numvecs++; 1110 for (i = 0; i < numvecs; i++) 1111 adapter->msix_entries[i].entry = i; 1112 1113 err = pci_enable_msix_range(adapter->pdev, 1114 adapter->msix_entries, 1115 numvecs, 1116 numvecs); 1117 if (err > 0) 1118 return; 1119 1120 igb_reset_interrupt_capability(adapter); 1121 1122 /* If we can't do MSI-X, try MSI */ 1123msi_only: 1124#ifdef CONFIG_PCI_IOV 1125 /* disable SR-IOV for non MSI-X configurations */ 1126 if (adapter->vf_data) { 1127 struct e1000_hw *hw = &adapter->hw; 1128 /* disable iov and allow time for transactions to clear */ 1129 pci_disable_sriov(adapter->pdev); 1130 msleep(500); 1131 1132 kfree(adapter->vf_data); 1133 adapter->vf_data = NULL; 1134 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1135 wrfl(); 1136 msleep(100); 1137 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1138 } 1139#endif 1140 adapter->vfs_allocated_count = 0; 1141 adapter->rss_queues = 1; 1142 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1143 adapter->num_rx_queues = 1; 1144 adapter->num_tx_queues = 1; 1145 adapter->num_q_vectors = 1; 1146 if (!pci_enable_msi(adapter->pdev)) 1147 adapter->flags |= IGB_FLAG_HAS_MSI; 1148} 1149 1150static void igb_add_ring(struct igb_ring *ring, 1151 struct igb_ring_container *head) 1152{ 1153 head->ring = ring; 1154 head->count++; 1155} 1156 1157/** 1158 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1159 * @adapter: board private structure to initialize 1160 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1161 * @v_idx: index of vector in adapter struct 1162 * @txr_count: total number of Tx rings to allocate 1163 * @txr_idx: index of first Tx ring to allocate 1164 * @rxr_count: total number of Rx rings to allocate 1165 * @rxr_idx: index of first Rx ring to allocate 1166 * 1167 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1168 **/ 1169static int igb_alloc_q_vector(struct igb_adapter *adapter, 1170 int v_count, int v_idx, 1171 int txr_count, int txr_idx, 1172 int rxr_count, int rxr_idx) 1173{ 1174 struct igb_q_vector *q_vector; 1175 struct igb_ring *ring; 1176 int ring_count, size; 1177 1178 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1179 if (txr_count > 1 || rxr_count > 1) 1180 return -ENOMEM; 1181 1182 ring_count = txr_count + rxr_count; 1183 size = sizeof(struct igb_q_vector) + 1184 (sizeof(struct igb_ring) * ring_count); 1185 1186 /* allocate q_vector and rings */ 1187 q_vector = adapter->q_vector[v_idx]; 1188 if (!q_vector) 1189 q_vector = kzalloc(size, GFP_KERNEL); 1190 if (!q_vector) 1191 return -ENOMEM; 1192 1193 /* initialize NAPI */ 1194 netif_napi_add(adapter->netdev, &q_vector->napi, 1195 igb_poll, 64); 1196 1197 /* tie q_vector and adapter together */ 1198 adapter->q_vector[v_idx] = q_vector; 1199 q_vector->adapter = adapter; 1200 1201 /* initialize work limits */ 1202 q_vector->tx.work_limit = adapter->tx_work_limit; 1203 1204 /* initialize ITR configuration */ 1205 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); 1206 q_vector->itr_val = IGB_START_ITR; 1207 1208 /* initialize pointer to rings */ 1209 ring = q_vector->ring; 1210 1211 /* intialize ITR */ 1212 if (rxr_count) { 1213 /* rx or rx/tx vector */ 1214 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1215 q_vector->itr_val = adapter->rx_itr_setting; 1216 } else { 1217 /* tx only vector */ 1218 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1219 q_vector->itr_val = adapter->tx_itr_setting; 1220 } 1221 1222 if (txr_count) { 1223 /* assign generic ring traits */ 1224 ring->dev = &adapter->pdev->dev; 1225 ring->netdev = adapter->netdev; 1226 1227 /* configure backlink on ring */ 1228 ring->q_vector = q_vector; 1229 1230 /* update q_vector Tx values */ 1231 igb_add_ring(ring, &q_vector->tx); 1232 1233 /* For 82575, context index must be unique per ring. */ 1234 if (adapter->hw.mac.type == e1000_82575) 1235 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1236 1237 /* apply Tx specific ring traits */ 1238 ring->count = adapter->tx_ring_count; 1239 ring->queue_index = txr_idx; 1240 1241 u64_stats_init(&ring->tx_syncp); 1242 u64_stats_init(&ring->tx_syncp2); 1243 1244 /* assign ring to adapter */ 1245 adapter->tx_ring[txr_idx] = ring; 1246 1247 /* push pointer to next ring */ 1248 ring++; 1249 } 1250 1251 if (rxr_count) { 1252 /* assign generic ring traits */ 1253 ring->dev = &adapter->pdev->dev; 1254 ring->netdev = adapter->netdev; 1255 1256 /* configure backlink on ring */ 1257 ring->q_vector = q_vector; 1258 1259 /* update q_vector Rx values */ 1260 igb_add_ring(ring, &q_vector->rx); 1261 1262 /* set flag indicating ring supports SCTP checksum offload */ 1263 if (adapter->hw.mac.type >= e1000_82576) 1264 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1265 1266 /* 1267 * On i350, i354, i210, and i211, loopback VLAN packets 1268 * have the tag byte-swapped. 1269 */ 1270 if (adapter->hw.mac.type >= e1000_i350) 1271 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1272 1273 /* apply Rx specific ring traits */ 1274 ring->count = adapter->rx_ring_count; 1275 ring->queue_index = rxr_idx; 1276 1277 u64_stats_init(&ring->rx_syncp); 1278 1279 /* assign ring to adapter */ 1280 adapter->rx_ring[rxr_idx] = ring; 1281 } 1282 1283 return 0; 1284} 1285 1286 1287/** 1288 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1289 * @adapter: board private structure to initialize 1290 * 1291 * We allocate one q_vector per queue interrupt. If allocation fails we 1292 * return -ENOMEM. 1293 **/ 1294static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1295{ 1296 int q_vectors = adapter->num_q_vectors; 1297 int rxr_remaining = adapter->num_rx_queues; 1298 int txr_remaining = adapter->num_tx_queues; 1299 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1300 int err; 1301 1302 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1303 for (; rxr_remaining; v_idx++) { 1304 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1305 0, 0, 1, rxr_idx); 1306 1307 if (err) 1308 goto err_out; 1309 1310 /* update counts and index */ 1311 rxr_remaining--; 1312 rxr_idx++; 1313 } 1314 } 1315 1316 for (; v_idx < q_vectors; v_idx++) { 1317 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1318 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1319 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1320 tqpv, txr_idx, rqpv, rxr_idx); 1321 1322 if (err) 1323 goto err_out; 1324 1325 /* update counts and index */ 1326 rxr_remaining -= rqpv; 1327 txr_remaining -= tqpv; 1328 rxr_idx++; 1329 txr_idx++; 1330 } 1331 1332 return 0; 1333 1334err_out: 1335 adapter->num_tx_queues = 0; 1336 adapter->num_rx_queues = 0; 1337 adapter->num_q_vectors = 0; 1338 1339 while (v_idx--) 1340 igb_free_q_vector(adapter, v_idx); 1341 1342 return -ENOMEM; 1343} 1344 1345/** 1346 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1347 * @adapter: board private structure to initialize 1348 * @msix: boolean value of MSIX capability 1349 * 1350 * This function initializes the interrupts and allocates all of the queues. 1351 **/ 1352static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1353{ 1354 struct pci_dev *pdev = adapter->pdev; 1355 int err; 1356 1357 igb_set_interrupt_capability(adapter, msix); 1358 1359 err = igb_alloc_q_vectors(adapter); 1360 if (err) { 1361 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1362 goto err_alloc_q_vectors; 1363 } 1364 1365 igb_cache_ring_register(adapter); 1366 1367 return 0; 1368 1369err_alloc_q_vectors: 1370 igb_reset_interrupt_capability(adapter); 1371 return err; 1372} 1373 1374/** 1375 * igb_request_irq - initialize interrupts 1376 * @adapter: board private structure to initialize 1377 * 1378 * Attempts to configure interrupts using the best available 1379 * capabilities of the hardware and kernel. 1380 **/ 1381static int igb_request_irq(struct igb_adapter *adapter) 1382{ 1383 struct net_device *netdev = adapter->netdev; 1384 struct pci_dev *pdev = adapter->pdev; 1385 int err = 0; 1386 1387 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1388 err = igb_request_msix(adapter); 1389 if (!err) 1390 goto request_done; 1391 /* fall back to MSI */ 1392 igb_free_all_tx_resources(adapter); 1393 igb_free_all_rx_resources(adapter); 1394 1395 igb_clear_interrupt_scheme(adapter); 1396 err = igb_init_interrupt_scheme(adapter, false); 1397 if (err) 1398 goto request_done; 1399 1400 igb_setup_all_tx_resources(adapter); 1401 igb_setup_all_rx_resources(adapter); 1402 igb_configure(adapter); 1403 } 1404 1405 igb_assign_vector(adapter->q_vector[0], 0); 1406 1407 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1408 err = request_irq(pdev->irq, igb_intr_msi, 0, 1409 netdev->name, adapter); 1410 if (!err) 1411 goto request_done; 1412 1413 /* fall back to legacy interrupts */ 1414 igb_reset_interrupt_capability(adapter); 1415 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1416 } 1417 1418 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1419 netdev->name, adapter); 1420 1421 if (err) 1422 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1423 err); 1424 1425request_done: 1426 return err; 1427} 1428 1429static void igb_free_irq(struct igb_adapter *adapter) 1430{ 1431 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1432 int vector = 0, i; 1433 1434 free_irq(adapter->msix_entries[vector++].vector, adapter); 1435 1436 for (i = 0; i < adapter->num_q_vectors; i++) 1437 free_irq(adapter->msix_entries[vector++].vector, 1438 adapter->q_vector[i]); 1439 } else { 1440 free_irq(adapter->pdev->irq, adapter); 1441 } 1442} 1443 1444/** 1445 * igb_irq_disable - Mask off interrupt generation on the NIC 1446 * @adapter: board private structure 1447 **/ 1448static void igb_irq_disable(struct igb_adapter *adapter) 1449{ 1450 struct e1000_hw *hw = &adapter->hw; 1451 1452 /* we need to be careful when disabling interrupts. The VFs are also 1453 * mapped into these registers and so clearing the bits can cause 1454 * issues on the VF drivers so we only need to clear what we set 1455 */ 1456 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1457 u32 regval = rd32(E1000_EIAM); 1458 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1459 wr32(E1000_EIMC, adapter->eims_enable_mask); 1460 regval = rd32(E1000_EIAC); 1461 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1462 } 1463 1464 wr32(E1000_IAM, 0); 1465 wr32(E1000_IMC, ~0); 1466 wrfl(); 1467 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1468 int i; 1469 for (i = 0; i < adapter->num_q_vectors; i++) 1470 synchronize_irq(adapter->msix_entries[i].vector); 1471 } else { 1472 synchronize_irq(adapter->pdev->irq); 1473 } 1474} 1475 1476/** 1477 * igb_irq_enable - Enable default interrupt generation settings 1478 * @adapter: board private structure 1479 **/ 1480static void igb_irq_enable(struct igb_adapter *adapter) 1481{ 1482 struct e1000_hw *hw = &adapter->hw; 1483 1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1485 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1486 u32 regval = rd32(E1000_EIAC); 1487 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1488 regval = rd32(E1000_EIAM); 1489 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1490 wr32(E1000_EIMS, adapter->eims_enable_mask); 1491 if (adapter->vfs_allocated_count) { 1492 wr32(E1000_MBVFIMR, 0xFF); 1493 ims |= E1000_IMS_VMMB; 1494 } 1495 wr32(E1000_IMS, ims); 1496 } else { 1497 wr32(E1000_IMS, IMS_ENABLE_MASK | 1498 E1000_IMS_DRSTA); 1499 wr32(E1000_IAM, IMS_ENABLE_MASK | 1500 E1000_IMS_DRSTA); 1501 } 1502} 1503 1504static void igb_update_mng_vlan(struct igb_adapter *adapter) 1505{ 1506 struct e1000_hw *hw = &adapter->hw; 1507 u16 vid = adapter->hw.mng_cookie.vlan_id; 1508 u16 old_vid = adapter->mng_vlan_id; 1509 1510 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1511 /* add VID to filter table */ 1512 igb_vfta_set(hw, vid, true); 1513 adapter->mng_vlan_id = vid; 1514 } else { 1515 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1516 } 1517 1518 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1519 (vid != old_vid) && 1520 !test_bit(old_vid, adapter->active_vlans)) { 1521 /* remove VID from filter table */ 1522 igb_vfta_set(hw, old_vid, false); 1523 } 1524} 1525 1526/** 1527 * igb_release_hw_control - release control of the h/w to f/w 1528 * @adapter: address of board private structure 1529 * 1530 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1531 * For ASF and Pass Through versions of f/w this means that the 1532 * driver is no longer loaded. 1533 **/ 1534static void igb_release_hw_control(struct igb_adapter *adapter) 1535{ 1536 struct e1000_hw *hw = &adapter->hw; 1537 u32 ctrl_ext; 1538 1539 /* Let firmware take over control of h/w */ 1540 ctrl_ext = rd32(E1000_CTRL_EXT); 1541 wr32(E1000_CTRL_EXT, 1542 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1543} 1544 1545/** 1546 * igb_get_hw_control - get control of the h/w from f/w 1547 * @adapter: address of board private structure 1548 * 1549 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1550 * For ASF and Pass Through versions of f/w this means that 1551 * the driver is loaded. 1552 **/ 1553static void igb_get_hw_control(struct igb_adapter *adapter) 1554{ 1555 struct e1000_hw *hw = &adapter->hw; 1556 u32 ctrl_ext; 1557 1558 /* Let firmware know the driver has taken over */ 1559 ctrl_ext = rd32(E1000_CTRL_EXT); 1560 wr32(E1000_CTRL_EXT, 1561 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1562} 1563 1564/** 1565 * igb_configure - configure the hardware for RX and TX 1566 * @adapter: private board structure 1567 **/ 1568static void igb_configure(struct igb_adapter *adapter) 1569{ 1570 struct net_device *netdev = adapter->netdev; 1571 int i; 1572 1573 igb_get_hw_control(adapter); 1574 igb_set_rx_mode(netdev); 1575 1576 igb_restore_vlan(adapter); 1577 1578 igb_setup_tctl(adapter); 1579 igb_setup_mrqc(adapter); 1580 igb_setup_rctl(adapter); 1581 1582 igb_configure_tx(adapter); 1583 igb_configure_rx(adapter); 1584 1585 igb_rx_fifo_flush_82575(&adapter->hw); 1586 1587 /* call igb_desc_unused which always leaves 1588 * at least 1 descriptor unused to make sure 1589 * next_to_use != next_to_clean 1590 */ 1591 for (i = 0; i < adapter->num_rx_queues; i++) { 1592 struct igb_ring *ring = adapter->rx_ring[i]; 1593 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1594 } 1595} 1596 1597/** 1598 * igb_power_up_link - Power up the phy/serdes link 1599 * @adapter: address of board private structure 1600 **/ 1601void igb_power_up_link(struct igb_adapter *adapter) 1602{ 1603 igb_reset_phy(&adapter->hw); 1604 1605 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1606 igb_power_up_phy_copper(&adapter->hw); 1607 else 1608 igb_power_up_serdes_link_82575(&adapter->hw); 1609} 1610 1611/** 1612 * igb_power_down_link - Power down the phy/serdes link 1613 * @adapter: address of board private structure 1614 */ 1615static void igb_power_down_link(struct igb_adapter *adapter) 1616{ 1617 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1618 igb_power_down_phy_copper_82575(&adapter->hw); 1619 else 1620 igb_shutdown_serdes_link_82575(&adapter->hw); 1621} 1622 1623/** 1624 * Detect and switch function for Media Auto Sense 1625 * @adapter: address of the board private structure 1626 **/ 1627static void igb_check_swap_media(struct igb_adapter *adapter) 1628{ 1629 struct e1000_hw *hw = &adapter->hw; 1630 u32 ctrl_ext, connsw; 1631 bool swap_now = false; 1632 1633 ctrl_ext = rd32(E1000_CTRL_EXT); 1634 connsw = rd32(E1000_CONNSW); 1635 1636 /* need to live swap if current media is copper and we have fiber/serdes 1637 * to go to. 1638 */ 1639 1640 if ((hw->phy.media_type == e1000_media_type_copper) && 1641 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1642 swap_now = true; 1643 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1644 /* copper signal takes time to appear */ 1645 if (adapter->copper_tries < 4) { 1646 adapter->copper_tries++; 1647 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1648 wr32(E1000_CONNSW, connsw); 1649 return; 1650 } else { 1651 adapter->copper_tries = 0; 1652 if ((connsw & E1000_CONNSW_PHYSD) && 1653 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1654 swap_now = true; 1655 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1656 wr32(E1000_CONNSW, connsw); 1657 } 1658 } 1659 } 1660 1661 if (!swap_now) 1662 return; 1663 1664 switch (hw->phy.media_type) { 1665 case e1000_media_type_copper: 1666 netdev_info(adapter->netdev, 1667 "MAS: changing media to fiber/serdes\n"); 1668 ctrl_ext |= 1669 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1670 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1671 adapter->copper_tries = 0; 1672 break; 1673 case e1000_media_type_internal_serdes: 1674 case e1000_media_type_fiber: 1675 netdev_info(adapter->netdev, 1676 "MAS: changing media to copper\n"); 1677 ctrl_ext &= 1678 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1679 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1680 break; 1681 default: 1682 /* shouldn't get here during regular operation */ 1683 netdev_err(adapter->netdev, 1684 "AMS: Invalid media type found, returning\n"); 1685 break; 1686 } 1687 wr32(E1000_CTRL_EXT, ctrl_ext); 1688} 1689 1690/** 1691 * igb_up - Open the interface and prepare it to handle traffic 1692 * @adapter: board private structure 1693 **/ 1694int igb_up(struct igb_adapter *adapter) 1695{ 1696 struct e1000_hw *hw = &adapter->hw; 1697 int i; 1698 1699 /* hardware has been reset, we need to reload some things */ 1700 igb_configure(adapter); 1701 1702 clear_bit(__IGB_DOWN, &adapter->state); 1703 1704 for (i = 0; i < adapter->num_q_vectors; i++) 1705 napi_enable(&(adapter->q_vector[i]->napi)); 1706 1707 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1708 igb_configure_msix(adapter); 1709 else 1710 igb_assign_vector(adapter->q_vector[0], 0); 1711 1712 /* Clear any pending interrupts. */ 1713 rd32(E1000_ICR); 1714 igb_irq_enable(adapter); 1715 1716 /* notify VFs that reset has been completed */ 1717 if (adapter->vfs_allocated_count) { 1718 u32 reg_data = rd32(E1000_CTRL_EXT); 1719 reg_data |= E1000_CTRL_EXT_PFRSTD; 1720 wr32(E1000_CTRL_EXT, reg_data); 1721 } 1722 1723 netif_tx_start_all_queues(adapter->netdev); 1724 1725 /* start the watchdog. */ 1726 hw->mac.get_link_status = 1; 1727 schedule_work(&adapter->watchdog_task); 1728 1729 if ((adapter->flags & IGB_FLAG_EEE) && 1730 (!hw->dev_spec._82575.eee_disable)) 1731 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1732 1733 return 0; 1734} 1735 1736void igb_down(struct igb_adapter *adapter) 1737{ 1738 struct net_device *netdev = adapter->netdev; 1739 struct e1000_hw *hw = &adapter->hw; 1740 u32 tctl, rctl; 1741 int i; 1742 1743 /* signal that we're down so the interrupt handler does not 1744 * reschedule our watchdog timer 1745 */ 1746 set_bit(__IGB_DOWN, &adapter->state); 1747 1748 /* disable receives in the hardware */ 1749 rctl = rd32(E1000_RCTL); 1750 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1751 /* flush and sleep below */ 1752 1753 netif_tx_stop_all_queues(netdev); 1754 1755 /* disable transmits in the hardware */ 1756 tctl = rd32(E1000_TCTL); 1757 tctl &= ~E1000_TCTL_EN; 1758 wr32(E1000_TCTL, tctl); 1759 /* flush both disables and wait for them to finish */ 1760 wrfl(); 1761 msleep(10); 1762 1763 igb_irq_disable(adapter); 1764 1765 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1766 1767 for (i = 0; i < adapter->num_q_vectors; i++) { 1768 napi_synchronize(&(adapter->q_vector[i]->napi)); 1769 napi_disable(&(adapter->q_vector[i]->napi)); 1770 } 1771 1772 1773 del_timer_sync(&adapter->watchdog_timer); 1774 del_timer_sync(&adapter->phy_info_timer); 1775 1776 netif_carrier_off(netdev); 1777 1778 /* record the stats before reset*/ 1779 spin_lock(&adapter->stats64_lock); 1780 igb_update_stats(adapter, &adapter->stats64); 1781 spin_unlock(&adapter->stats64_lock); 1782 1783 adapter->link_speed = 0; 1784 adapter->link_duplex = 0; 1785 1786 if (!pci_channel_offline(adapter->pdev)) 1787 igb_reset(adapter); 1788 igb_clean_all_tx_rings(adapter); 1789 igb_clean_all_rx_rings(adapter); 1790#ifdef CONFIG_IGB_DCA 1791 1792 /* since we reset the hardware DCA settings were cleared */ 1793 igb_setup_dca(adapter); 1794#endif 1795} 1796 1797void igb_reinit_locked(struct igb_adapter *adapter) 1798{ 1799 WARN_ON(in_interrupt()); 1800 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1801 msleep(1); 1802 igb_down(adapter); 1803 igb_up(adapter); 1804 clear_bit(__IGB_RESETTING, &adapter->state); 1805} 1806 1807/** igb_enable_mas - Media Autosense re-enable after swap 1808 * 1809 * @adapter: adapter struct 1810 **/ 1811static s32 igb_enable_mas(struct igb_adapter *adapter) 1812{ 1813 struct e1000_hw *hw = &adapter->hw; 1814 u32 connsw; 1815 s32 ret_val = 0; 1816 1817 connsw = rd32(E1000_CONNSW); 1818 if (!(hw->phy.media_type == e1000_media_type_copper)) 1819 return ret_val; 1820 1821 /* configure for SerDes media detect */ 1822 if (!(connsw & E1000_CONNSW_SERDESD)) { 1823 connsw |= E1000_CONNSW_ENRGSRC; 1824 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1825 wr32(E1000_CONNSW, connsw); 1826 wrfl(); 1827 } else if (connsw & E1000_CONNSW_SERDESD) { 1828 /* already SerDes, no need to enable anything */ 1829 return ret_val; 1830 } else { 1831 netdev_info(adapter->netdev, 1832 "MAS: Unable to configure feature, disabling..\n"); 1833 adapter->flags &= ~IGB_FLAG_MAS_ENABLE; 1834 } 1835 return ret_val; 1836} 1837 1838void igb_reset(struct igb_adapter *adapter) 1839{ 1840 struct pci_dev *pdev = adapter->pdev; 1841 struct e1000_hw *hw = &adapter->hw; 1842 struct e1000_mac_info *mac = &hw->mac; 1843 struct e1000_fc_info *fc = &hw->fc; 1844 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; 1845 1846 /* Repartition Pba for greater than 9k mtu 1847 * To take effect CTRL.RST is required. 1848 */ 1849 switch (mac->type) { 1850 case e1000_i350: 1851 case e1000_i354: 1852 case e1000_82580: 1853 pba = rd32(E1000_RXPBS); 1854 pba = igb_rxpbs_adjust_82580(pba); 1855 break; 1856 case e1000_82576: 1857 pba = rd32(E1000_RXPBS); 1858 pba &= E1000_RXPBS_SIZE_MASK_82576; 1859 break; 1860 case e1000_82575: 1861 case e1000_i210: 1862 case e1000_i211: 1863 default: 1864 pba = E1000_PBA_34K; 1865 break; 1866 } 1867 1868 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1869 (mac->type < e1000_82576)) { 1870 /* adjust PBA for jumbo frames */ 1871 wr32(E1000_PBA, pba); 1872 1873 /* To maintain wire speed transmits, the Tx FIFO should be 1874 * large enough to accommodate two full transmit packets, 1875 * rounded up to the next 1KB and expressed in KB. Likewise, 1876 * the Rx FIFO should be large enough to accommodate at least 1877 * one full receive packet and is similarly rounded up and 1878 * expressed in KB. 1879 */ 1880 pba = rd32(E1000_PBA); 1881 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1882 tx_space = pba >> 16; 1883 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1884 pba &= 0xffff; 1885 /* the Tx fifo also stores 16 bytes of information about the Tx 1886 * but don't include ethernet FCS because hardware appends it 1887 */ 1888 min_tx_space = (adapter->max_frame_size + 1889 sizeof(union e1000_adv_tx_desc) - 1890 ETH_FCS_LEN) * 2; 1891 min_tx_space = ALIGN(min_tx_space, 1024); 1892 min_tx_space >>= 10; 1893 /* software strips receive CRC, so leave room for it */ 1894 min_rx_space = adapter->max_frame_size; 1895 min_rx_space = ALIGN(min_rx_space, 1024); 1896 min_rx_space >>= 10; 1897 1898 /* If current Tx allocation is less than the min Tx FIFO size, 1899 * and the min Tx FIFO size is less than the current Rx FIFO 1900 * allocation, take space away from current Rx allocation 1901 */ 1902 if (tx_space < min_tx_space && 1903 ((min_tx_space - tx_space) < pba)) { 1904 pba = pba - (min_tx_space - tx_space); 1905 1906 /* if short on Rx space, Rx wins and must trump Tx 1907 * adjustment 1908 */ 1909 if (pba < min_rx_space) 1910 pba = min_rx_space; 1911 } 1912 wr32(E1000_PBA, pba); 1913 } 1914 1915 /* flow control settings */ 1916 /* The high water mark must be low enough to fit one full frame 1917 * (or the size used for early receive) above it in the Rx FIFO. 1918 * Set it to the lower of: 1919 * - 90% of the Rx FIFO size, or 1920 * - the full Rx FIFO size minus one full frame 1921 */ 1922 hwm = min(((pba << 10) * 9 / 10), 1923 ((pba << 10) - 2 * adapter->max_frame_size)); 1924 1925 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1926 fc->low_water = fc->high_water - 16; 1927 fc->pause_time = 0xFFFF; 1928 fc->send_xon = 1; 1929 fc->current_mode = fc->requested_mode; 1930 1931 /* disable receive for all VFs and wait one second */ 1932 if (adapter->vfs_allocated_count) { 1933 int i; 1934 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1935 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1936 1937 /* ping all the active vfs to let them know we are going down */ 1938 igb_ping_all_vfs(adapter); 1939 1940 /* disable transmits and receives */ 1941 wr32(E1000_VFRE, 0); 1942 wr32(E1000_VFTE, 0); 1943 } 1944 1945 /* Allow time for pending master requests to run */ 1946 hw->mac.ops.reset_hw(hw); 1947 wr32(E1000_WUC, 0); 1948 1949 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1950 /* need to resetup here after media swap */ 1951 adapter->ei.get_invariants(hw); 1952 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1953 } 1954 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 1955 if (igb_enable_mas(adapter)) 1956 dev_err(&pdev->dev, 1957 "Error enabling Media Auto Sense\n"); 1958 } 1959 if (hw->mac.ops.init_hw(hw)) 1960 dev_err(&pdev->dev, "Hardware Error\n"); 1961 1962 /* Flow control settings reset on hardware reset, so guarantee flow 1963 * control is off when forcing speed. 1964 */ 1965 if (!hw->mac.autoneg) 1966 igb_force_mac_fc(hw); 1967 1968 igb_init_dmac(adapter, pba); 1969#ifdef CONFIG_IGB_HWMON 1970 /* Re-initialize the thermal sensor on i350 devices. */ 1971 if (!test_bit(__IGB_DOWN, &adapter->state)) { 1972 if (mac->type == e1000_i350 && hw->bus.func == 0) { 1973 /* If present, re-initialize the external thermal sensor 1974 * interface. 1975 */ 1976 if (adapter->ets) 1977 mac->ops.init_thermal_sensor_thresh(hw); 1978 } 1979 } 1980#endif 1981 /* Re-establish EEE setting */ 1982 if (hw->phy.media_type == e1000_media_type_copper) { 1983 switch (mac->type) { 1984 case e1000_i350: 1985 case e1000_i210: 1986 case e1000_i211: 1987 igb_set_eee_i350(hw); 1988 break; 1989 case e1000_i354: 1990 igb_set_eee_i354(hw); 1991 break; 1992 default: 1993 break; 1994 } 1995 } 1996 if (!netif_running(adapter->netdev)) 1997 igb_power_down_link(adapter); 1998 1999 igb_update_mng_vlan(adapter); 2000 2001 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2002 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2003 2004 /* Re-enable PTP, where applicable. */ 2005 igb_ptp_reset(adapter); 2006 2007 igb_get_phy_info(hw); 2008} 2009 2010static netdev_features_t igb_fix_features(struct net_device *netdev, 2011 netdev_features_t features) 2012{ 2013 /* Since there is no support for separate Rx/Tx vlan accel 2014 * enable/disable make sure Tx flag is always in same state as Rx. 2015 */ 2016 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2017 features |= NETIF_F_HW_VLAN_CTAG_TX; 2018 else 2019 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2020 2021 return features; 2022} 2023 2024static int igb_set_features(struct net_device *netdev, 2025 netdev_features_t features) 2026{ 2027 netdev_features_t changed = netdev->features ^ features; 2028 struct igb_adapter *adapter = netdev_priv(netdev); 2029 2030 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2031 igb_vlan_mode(netdev, features); 2032 2033 if (!(changed & NETIF_F_RXALL)) 2034 return 0; 2035 2036 netdev->features = features; 2037 2038 if (netif_running(netdev)) 2039 igb_reinit_locked(adapter); 2040 else 2041 igb_reset(adapter); 2042 2043 return 0; 2044} 2045 2046static const struct net_device_ops igb_netdev_ops = { 2047 .ndo_open = igb_open, 2048 .ndo_stop = igb_close, 2049 .ndo_start_xmit = igb_xmit_frame, 2050 .ndo_get_stats64 = igb_get_stats64, 2051 .ndo_set_rx_mode = igb_set_rx_mode, 2052 .ndo_set_mac_address = igb_set_mac, 2053 .ndo_change_mtu = igb_change_mtu, 2054 .ndo_do_ioctl = igb_ioctl, 2055 .ndo_tx_timeout = igb_tx_timeout, 2056 .ndo_validate_addr = eth_validate_addr, 2057 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2058 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2059 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2060 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2061 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, 2062 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2063 .ndo_get_vf_config = igb_ndo_get_vf_config, 2064#ifdef CONFIG_NET_POLL_CONTROLLER 2065 .ndo_poll_controller = igb_netpoll, 2066#endif 2067 .ndo_fix_features = igb_fix_features, 2068 .ndo_set_features = igb_set_features, 2069}; 2070 2071/** 2072 * igb_set_fw_version - Configure version string for ethtool 2073 * @adapter: adapter struct 2074 **/ 2075void igb_set_fw_version(struct igb_adapter *adapter) 2076{ 2077 struct e1000_hw *hw = &adapter->hw; 2078 struct e1000_fw_version fw; 2079 2080 igb_get_fw_version(hw, &fw); 2081 2082 switch (hw->mac.type) { 2083 case e1000_i210: 2084 case e1000_i211: 2085 if (!(igb_get_flash_presence_i210(hw))) { 2086 snprintf(adapter->fw_version, 2087 sizeof(adapter->fw_version), 2088 "%2d.%2d-%d", 2089 fw.invm_major, fw.invm_minor, 2090 fw.invm_img_type); 2091 break; 2092 } 2093 /* fall through */ 2094 default: 2095 /* if option is rom valid, display its version too */ 2096 if (fw.or_valid) { 2097 snprintf(adapter->fw_version, 2098 sizeof(adapter->fw_version), 2099 "%d.%d, 0x%08x, %d.%d.%d", 2100 fw.eep_major, fw.eep_minor, fw.etrack_id, 2101 fw.or_major, fw.or_build, fw.or_patch); 2102 /* no option rom */ 2103 } else if (fw.etrack_id != 0X0000) { 2104 snprintf(adapter->fw_version, 2105 sizeof(adapter->fw_version), 2106 "%d.%d, 0x%08x", 2107 fw.eep_major, fw.eep_minor, fw.etrack_id); 2108 } else { 2109 snprintf(adapter->fw_version, 2110 sizeof(adapter->fw_version), 2111 "%d.%d.%d", 2112 fw.eep_major, fw.eep_minor, fw.eep_build); 2113 } 2114 break; 2115 } 2116 return; 2117} 2118 2119/** 2120 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2121 * 2122 * @adapter: adapter struct 2123 **/ 2124static void igb_init_mas(struct igb_adapter *adapter) 2125{ 2126 struct e1000_hw *hw = &adapter->hw; 2127 u16 eeprom_data; 2128 2129 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2130 switch (hw->bus.func) { 2131 case E1000_FUNC_0: 2132 if (eeprom_data & IGB_MAS_ENABLE_0) { 2133 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2134 netdev_info(adapter->netdev, 2135 "MAS: Enabling Media Autosense for port %d\n", 2136 hw->bus.func); 2137 } 2138 break; 2139 case E1000_FUNC_1: 2140 if (eeprom_data & IGB_MAS_ENABLE_1) { 2141 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2142 netdev_info(adapter->netdev, 2143 "MAS: Enabling Media Autosense for port %d\n", 2144 hw->bus.func); 2145 } 2146 break; 2147 case E1000_FUNC_2: 2148 if (eeprom_data & IGB_MAS_ENABLE_2) { 2149 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2150 netdev_info(adapter->netdev, 2151 "MAS: Enabling Media Autosense for port %d\n", 2152 hw->bus.func); 2153 } 2154 break; 2155 case E1000_FUNC_3: 2156 if (eeprom_data & IGB_MAS_ENABLE_3) { 2157 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2158 netdev_info(adapter->netdev, 2159 "MAS: Enabling Media Autosense for port %d\n", 2160 hw->bus.func); 2161 } 2162 break; 2163 default: 2164 /* Shouldn't get here */ 2165 netdev_err(adapter->netdev, 2166 "MAS: Invalid port configuration, returning\n"); 2167 break; 2168 } 2169} 2170 2171/** 2172 * igb_init_i2c - Init I2C interface 2173 * @adapter: pointer to adapter structure 2174 **/ 2175static s32 igb_init_i2c(struct igb_adapter *adapter) 2176{ 2177 s32 status = E1000_SUCCESS; 2178 2179 /* I2C interface supported on i350 devices */ 2180 if (adapter->hw.mac.type != e1000_i350) 2181 return E1000_SUCCESS; 2182 2183 /* Initialize the i2c bus which is controlled by the registers. 2184 * This bus will use the i2c_algo_bit structue that implements 2185 * the protocol through toggling of the 4 bits in the register. 2186 */ 2187 adapter->i2c_adap.owner = THIS_MODULE; 2188 adapter->i2c_algo = igb_i2c_algo; 2189 adapter->i2c_algo.data = adapter; 2190 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2191 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2192 strlcpy(adapter->i2c_adap.name, "igb BB", 2193 sizeof(adapter->i2c_adap.name)); 2194 status = i2c_bit_add_bus(&adapter->i2c_adap); 2195 return status; 2196} 2197 2198/** 2199 * igb_probe - Device Initialization Routine 2200 * @pdev: PCI device information struct 2201 * @ent: entry in igb_pci_tbl 2202 * 2203 * Returns 0 on success, negative on failure 2204 * 2205 * igb_probe initializes an adapter identified by a pci_dev structure. 2206 * The OS initialization, configuring of the adapter private structure, 2207 * and a hardware reset occur. 2208 **/ 2209static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2210{ 2211 struct net_device *netdev; 2212 struct igb_adapter *adapter; 2213 struct e1000_hw *hw; 2214 u16 eeprom_data = 0; 2215 s32 ret_val; 2216 static int global_quad_port_a; /* global quad port a indication */ 2217 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2218 int err, pci_using_dac; 2219 u8 part_str[E1000_PBANUM_LENGTH]; 2220 2221 /* Catch broken hardware that put the wrong VF device ID in 2222 * the PCIe SR-IOV capability. 2223 */ 2224 if (pdev->is_virtfn) { 2225 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2226 pci_name(pdev), pdev->vendor, pdev->device); 2227 return -EINVAL; 2228 } 2229 2230 err = pci_enable_device_mem(pdev); 2231 if (err) 2232 return err; 2233 2234 pci_using_dac = 0; 2235 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2236 if (!err) { 2237 pci_using_dac = 1; 2238 } else { 2239 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2240 if (err) { 2241 dev_err(&pdev->dev, 2242 "No usable DMA configuration, aborting\n"); 2243 goto err_dma; 2244 } 2245 } 2246 2247 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 2248 IORESOURCE_MEM), 2249 igb_driver_name); 2250 if (err) 2251 goto err_pci_reg; 2252 2253 pci_enable_pcie_error_reporting(pdev); 2254 2255 pci_set_master(pdev); 2256 pci_save_state(pdev); 2257 2258 err = -ENOMEM; 2259 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2260 IGB_MAX_TX_QUEUES); 2261 if (!netdev) 2262 goto err_alloc_etherdev; 2263 2264 SET_NETDEV_DEV(netdev, &pdev->dev); 2265 2266 pci_set_drvdata(pdev, netdev); 2267 adapter = netdev_priv(netdev); 2268 adapter->netdev = netdev; 2269 adapter->pdev = pdev; 2270 hw = &adapter->hw; 2271 hw->back = adapter; 2272 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2273 2274 err = -EIO; 2275 hw->hw_addr = pci_iomap(pdev, 0, 0); 2276 if (!hw->hw_addr) 2277 goto err_ioremap; 2278 2279 netdev->netdev_ops = &igb_netdev_ops; 2280 igb_set_ethtool_ops(netdev); 2281 netdev->watchdog_timeo = 5 * HZ; 2282 2283 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2284 2285 netdev->mem_start = pci_resource_start(pdev, 0); 2286 netdev->mem_end = pci_resource_end(pdev, 0); 2287 2288 /* PCI config space info */ 2289 hw->vendor_id = pdev->vendor; 2290 hw->device_id = pdev->device; 2291 hw->revision_id = pdev->revision; 2292 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2293 hw->subsystem_device_id = pdev->subsystem_device; 2294 2295 /* Copy the default MAC, PHY and NVM function pointers */ 2296 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2297 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2298 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2299 /* Initialize skew-specific constants */ 2300 err = ei->get_invariants(hw); 2301 if (err) 2302 goto err_sw_init; 2303 2304 /* setup the private structure */ 2305 err = igb_sw_init(adapter); 2306 if (err) 2307 goto err_sw_init; 2308 2309 igb_get_bus_info_pcie(hw); 2310 2311 hw->phy.autoneg_wait_to_complete = false; 2312 2313 /* Copper options */ 2314 if (hw->phy.media_type == e1000_media_type_copper) { 2315 hw->phy.mdix = AUTO_ALL_MODES; 2316 hw->phy.disable_polarity_correction = false; 2317 hw->phy.ms_type = e1000_ms_hw_default; 2318 } 2319 2320 if (igb_check_reset_block(hw)) 2321 dev_info(&pdev->dev, 2322 "PHY reset is blocked due to SOL/IDER session.\n"); 2323 2324 /* features is initialized to 0 in allocation, it might have bits 2325 * set by igb_sw_init so we should use an or instead of an 2326 * assignment. 2327 */ 2328 netdev->features |= NETIF_F_SG | 2329 NETIF_F_IP_CSUM | 2330 NETIF_F_IPV6_CSUM | 2331 NETIF_F_TSO | 2332 NETIF_F_TSO6 | 2333 NETIF_F_RXHASH | 2334 NETIF_F_RXCSUM | 2335 NETIF_F_HW_VLAN_CTAG_RX | 2336 NETIF_F_HW_VLAN_CTAG_TX; 2337 2338 /* copy netdev features into list of user selectable features */ 2339 netdev->hw_features |= netdev->features; 2340 netdev->hw_features |= NETIF_F_RXALL; 2341 2342 /* set this bit last since it cannot be part of hw_features */ 2343 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2344 2345 netdev->vlan_features |= NETIF_F_TSO | 2346 NETIF_F_TSO6 | 2347 NETIF_F_IP_CSUM | 2348 NETIF_F_IPV6_CSUM | 2349 NETIF_F_SG; 2350 2351 netdev->priv_flags |= IFF_SUPP_NOFCS; 2352 2353 if (pci_using_dac) { 2354 netdev->features |= NETIF_F_HIGHDMA; 2355 netdev->vlan_features |= NETIF_F_HIGHDMA; 2356 } 2357 2358 if (hw->mac.type >= e1000_82576) { 2359 netdev->hw_features |= NETIF_F_SCTP_CSUM; 2360 netdev->features |= NETIF_F_SCTP_CSUM; 2361 } 2362 2363 netdev->priv_flags |= IFF_UNICAST_FLT; 2364 2365 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2366 2367 /* before reading the NVM, reset the controller to put the device in a 2368 * known good starting state 2369 */ 2370 hw->mac.ops.reset_hw(hw); 2371 2372 /* make sure the NVM is good , i211/i210 parts can have special NVM 2373 * that doesn't contain a checksum 2374 */ 2375 switch (hw->mac.type) { 2376 case e1000_i210: 2377 case e1000_i211: 2378 if (igb_get_flash_presence_i210(hw)) { 2379 if (hw->nvm.ops.validate(hw) < 0) { 2380 dev_err(&pdev->dev, 2381 "The NVM Checksum Is Not Valid\n"); 2382 err = -EIO; 2383 goto err_eeprom; 2384 } 2385 } 2386 break; 2387 default: 2388 if (hw->nvm.ops.validate(hw) < 0) { 2389 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2390 err = -EIO; 2391 goto err_eeprom; 2392 } 2393 break; 2394 } 2395 2396 /* copy the MAC address out of the NVM */ 2397 if (hw->mac.ops.read_mac_addr(hw)) 2398 dev_err(&pdev->dev, "NVM Read Error\n"); 2399 2400 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2401 2402 if (!is_valid_ether_addr(netdev->dev_addr)) { 2403 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2404 err = -EIO; 2405 goto err_eeprom; 2406 } 2407 2408 /* get firmware version for ethtool -i */ 2409 igb_set_fw_version(adapter); 2410 2411 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2412 (unsigned long) adapter); 2413 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2414 (unsigned long) adapter); 2415 2416 INIT_WORK(&adapter->reset_task, igb_reset_task); 2417 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2418 2419 /* Initialize link properties that are user-changeable */ 2420 adapter->fc_autoneg = true; 2421 hw->mac.autoneg = true; 2422 hw->phy.autoneg_advertised = 0x2f; 2423 2424 hw->fc.requested_mode = e1000_fc_default; 2425 hw->fc.current_mode = e1000_fc_default; 2426 2427 igb_validate_mdi_setting(hw); 2428 2429 /* By default, support wake on port A */ 2430 if (hw->bus.func == 0) 2431 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2432 2433 /* Check the NVM for wake support on non-port A ports */ 2434 if (hw->mac.type >= e1000_82580) 2435 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2436 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2437 &eeprom_data); 2438 else if (hw->bus.func == 1) 2439 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2440 2441 if (eeprom_data & IGB_EEPROM_APME) 2442 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2443 2444 /* now that we have the eeprom settings, apply the special cases where 2445 * the eeprom may be wrong or the board simply won't support wake on 2446 * lan on a particular port 2447 */ 2448 switch (pdev->device) { 2449 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2450 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2451 break; 2452 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2453 case E1000_DEV_ID_82576_FIBER: 2454 case E1000_DEV_ID_82576_SERDES: 2455 /* Wake events only supported on port A for dual fiber 2456 * regardless of eeprom setting 2457 */ 2458 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2459 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2460 break; 2461 case E1000_DEV_ID_82576_QUAD_COPPER: 2462 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2463 /* if quad port adapter, disable WoL on all but port A */ 2464 if (global_quad_port_a != 0) 2465 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2466 else 2467 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2468 /* Reset for multiple quad port adapters */ 2469 if (++global_quad_port_a == 4) 2470 global_quad_port_a = 0; 2471 break; 2472 default: 2473 /* If the device can't wake, don't set software support */ 2474 if (!device_can_wakeup(&adapter->pdev->dev)) 2475 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2476 } 2477 2478 /* initialize the wol settings based on the eeprom settings */ 2479 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2480 adapter->wol |= E1000_WUFC_MAG; 2481 2482 /* Some vendors want WoL disabled by default, but still supported */ 2483 if ((hw->mac.type == e1000_i350) && 2484 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2485 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2486 adapter->wol = 0; 2487 } 2488 2489 device_set_wakeup_enable(&adapter->pdev->dev, 2490 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2491 2492 /* reset the hardware with the new settings */ 2493 igb_reset(adapter); 2494 2495 /* Init the I2C interface */ 2496 err = igb_init_i2c(adapter); 2497 if (err) { 2498 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2499 goto err_eeprom; 2500 } 2501 2502 /* let the f/w know that the h/w is now under the control of the 2503 * driver. */ 2504 igb_get_hw_control(adapter); 2505 2506 strcpy(netdev->name, "eth%d"); 2507 err = register_netdev(netdev); 2508 if (err) 2509 goto err_register; 2510 2511 /* carrier off reporting is important to ethtool even BEFORE open */ 2512 netif_carrier_off(netdev); 2513 2514#ifdef CONFIG_IGB_DCA 2515 if (dca_add_requester(&pdev->dev) == 0) { 2516 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2517 dev_info(&pdev->dev, "DCA enabled\n"); 2518 igb_setup_dca(adapter); 2519 } 2520 2521#endif 2522#ifdef CONFIG_IGB_HWMON 2523 /* Initialize the thermal sensor on i350 devices. */ 2524 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2525 u16 ets_word; 2526 2527 /* Read the NVM to determine if this i350 device supports an 2528 * external thermal sensor. 2529 */ 2530 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2531 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2532 adapter->ets = true; 2533 else 2534 adapter->ets = false; 2535 if (igb_sysfs_init(adapter)) 2536 dev_err(&pdev->dev, 2537 "failed to allocate sysfs resources\n"); 2538 } else { 2539 adapter->ets = false; 2540 } 2541#endif 2542 /* Check if Media Autosense is enabled */ 2543 adapter->ei = *ei; 2544 if (hw->dev_spec._82575.mas_capable) 2545 igb_init_mas(adapter); 2546 2547 /* do hw tstamp init after resetting */ 2548 igb_ptp_init(adapter); 2549 2550 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2551 /* print bus type/speed/width info, not applicable to i354 */ 2552 if (hw->mac.type != e1000_i354) { 2553 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2554 netdev->name, 2555 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2556 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2557 "unknown"), 2558 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2559 "Width x4" : 2560 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2561 "Width x2" : 2562 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2563 "Width x1" : "unknown"), netdev->dev_addr); 2564 } 2565 2566 if ((hw->mac.type >= e1000_i210 || 2567 igb_get_flash_presence_i210(hw))) { 2568 ret_val = igb_read_part_string(hw, part_str, 2569 E1000_PBANUM_LENGTH); 2570 } else { 2571 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2572 } 2573 2574 if (ret_val) 2575 strcpy(part_str, "Unknown"); 2576 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2577 dev_info(&pdev->dev, 2578 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2579 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2580 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2581 adapter->num_rx_queues, adapter->num_tx_queues); 2582 if (hw->phy.media_type == e1000_media_type_copper) { 2583 switch (hw->mac.type) { 2584 case e1000_i350: 2585 case e1000_i210: 2586 case e1000_i211: 2587 /* Enable EEE for internal copper PHY devices */ 2588 err = igb_set_eee_i350(hw); 2589 if ((!err) && 2590 (!hw->dev_spec._82575.eee_disable)) { 2591 adapter->eee_advert = 2592 MDIO_EEE_100TX | MDIO_EEE_1000T; 2593 adapter->flags |= IGB_FLAG_EEE; 2594 } 2595 break; 2596 case e1000_i354: 2597 if ((rd32(E1000_CTRL_EXT) & 2598 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2599 err = igb_set_eee_i354(hw); 2600 if ((!err) && 2601 (!hw->dev_spec._82575.eee_disable)) { 2602 adapter->eee_advert = 2603 MDIO_EEE_100TX | MDIO_EEE_1000T; 2604 adapter->flags |= IGB_FLAG_EEE; 2605 } 2606 } 2607 break; 2608 default: 2609 break; 2610 } 2611 } 2612 pm_runtime_put_noidle(&pdev->dev); 2613 return 0; 2614 2615err_register: 2616 igb_release_hw_control(adapter); 2617 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2618err_eeprom: 2619 if (!igb_check_reset_block(hw)) 2620 igb_reset_phy(hw); 2621 2622 if (hw->flash_address) 2623 iounmap(hw->flash_address); 2624err_sw_init: 2625 igb_clear_interrupt_scheme(adapter); 2626 iounmap(hw->hw_addr); 2627err_ioremap: 2628 free_netdev(netdev); 2629err_alloc_etherdev: 2630 pci_release_selected_regions(pdev, 2631 pci_select_bars(pdev, IORESOURCE_MEM)); 2632err_pci_reg: 2633err_dma: 2634 pci_disable_device(pdev); 2635 return err; 2636} 2637 2638#ifdef CONFIG_PCI_IOV 2639static int igb_disable_sriov(struct pci_dev *pdev) 2640{ 2641 struct net_device *netdev = pci_get_drvdata(pdev); 2642 struct igb_adapter *adapter = netdev_priv(netdev); 2643 struct e1000_hw *hw = &adapter->hw; 2644 2645 /* reclaim resources allocated to VFs */ 2646 if (adapter->vf_data) { 2647 /* disable iov and allow time for transactions to clear */ 2648 if (pci_vfs_assigned(pdev)) { 2649 dev_warn(&pdev->dev, 2650 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2651 return -EPERM; 2652 } else { 2653 pci_disable_sriov(pdev); 2654 msleep(500); 2655 } 2656 2657 kfree(adapter->vf_data); 2658 adapter->vf_data = NULL; 2659 adapter->vfs_allocated_count = 0; 2660 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2661 wrfl(); 2662 msleep(100); 2663 dev_info(&pdev->dev, "IOV Disabled\n"); 2664 2665 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2666 adapter->flags |= IGB_FLAG_DMAC; 2667 } 2668 2669 return 0; 2670} 2671 2672static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2673{ 2674 struct net_device *netdev = pci_get_drvdata(pdev); 2675 struct igb_adapter *adapter = netdev_priv(netdev); 2676 int old_vfs = pci_num_vf(pdev); 2677 int err = 0; 2678 int i; 2679 2680 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2681 err = -EPERM; 2682 goto out; 2683 } 2684 if (!num_vfs) 2685 goto out; 2686 2687 if (old_vfs) { 2688 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2689 old_vfs, max_vfs); 2690 adapter->vfs_allocated_count = old_vfs; 2691 } else 2692 adapter->vfs_allocated_count = num_vfs; 2693 2694 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2695 sizeof(struct vf_data_storage), GFP_KERNEL); 2696 2697 /* if allocation failed then we do not support SR-IOV */ 2698 if (!adapter->vf_data) { 2699 adapter->vfs_allocated_count = 0; 2700 dev_err(&pdev->dev, 2701 "Unable to allocate memory for VF Data Storage\n"); 2702 err = -ENOMEM; 2703 goto out; 2704 } 2705 2706 /* only call pci_enable_sriov() if no VFs are allocated already */ 2707 if (!old_vfs) { 2708 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2709 if (err) 2710 goto err_out; 2711 } 2712 dev_info(&pdev->dev, "%d VFs allocated\n", 2713 adapter->vfs_allocated_count); 2714 for (i = 0; i < adapter->vfs_allocated_count; i++) 2715 igb_vf_configure(adapter, i); 2716 2717 /* DMA Coalescing is not supported in IOV mode. */ 2718 adapter->flags &= ~IGB_FLAG_DMAC; 2719 goto out; 2720 2721err_out: 2722 kfree(adapter->vf_data); 2723 adapter->vf_data = NULL; 2724 adapter->vfs_allocated_count = 0; 2725out: 2726 return err; 2727} 2728 2729#endif 2730/** 2731 * igb_remove_i2c - Cleanup I2C interface 2732 * @adapter: pointer to adapter structure 2733 **/ 2734static void igb_remove_i2c(struct igb_adapter *adapter) 2735{ 2736 /* free the adapter bus structure */ 2737 i2c_del_adapter(&adapter->i2c_adap); 2738} 2739 2740/** 2741 * igb_remove - Device Removal Routine 2742 * @pdev: PCI device information struct 2743 * 2744 * igb_remove is called by the PCI subsystem to alert the driver 2745 * that it should release a PCI device. The could be caused by a 2746 * Hot-Plug event, or because the driver is going to be removed from 2747 * memory. 2748 **/ 2749static void igb_remove(struct pci_dev *pdev) 2750{ 2751 struct net_device *netdev = pci_get_drvdata(pdev); 2752 struct igb_adapter *adapter = netdev_priv(netdev); 2753 struct e1000_hw *hw = &adapter->hw; 2754 2755 pm_runtime_get_noresume(&pdev->dev); 2756#ifdef CONFIG_IGB_HWMON 2757 igb_sysfs_exit(adapter); 2758#endif 2759 igb_remove_i2c(adapter); 2760 igb_ptp_stop(adapter); 2761 /* The watchdog timer may be rescheduled, so explicitly 2762 * disable watchdog from being rescheduled. 2763 */ 2764 set_bit(__IGB_DOWN, &adapter->state); 2765 del_timer_sync(&adapter->watchdog_timer); 2766 del_timer_sync(&adapter->phy_info_timer); 2767 2768 cancel_work_sync(&adapter->reset_task); 2769 cancel_work_sync(&adapter->watchdog_task); 2770 2771#ifdef CONFIG_IGB_DCA 2772 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2773 dev_info(&pdev->dev, "DCA disabled\n"); 2774 dca_remove_requester(&pdev->dev); 2775 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2776 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2777 } 2778#endif 2779 2780 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2781 * would have already happened in close and is redundant. 2782 */ 2783 igb_release_hw_control(adapter); 2784 2785 unregister_netdev(netdev); 2786 2787 igb_clear_interrupt_scheme(adapter); 2788 2789#ifdef CONFIG_PCI_IOV 2790 igb_disable_sriov(pdev); 2791#endif 2792 2793 iounmap(hw->hw_addr); 2794 if (hw->flash_address) 2795 iounmap(hw->flash_address); 2796 pci_release_selected_regions(pdev, 2797 pci_select_bars(pdev, IORESOURCE_MEM)); 2798 2799 kfree(adapter->shadow_vfta); 2800 free_netdev(netdev); 2801 2802 pci_disable_pcie_error_reporting(pdev); 2803 2804 pci_disable_device(pdev); 2805} 2806 2807/** 2808 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2809 * @adapter: board private structure to initialize 2810 * 2811 * This function initializes the vf specific data storage and then attempts to 2812 * allocate the VFs. The reason for ordering it this way is because it is much 2813 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2814 * the memory for the VFs. 2815 **/ 2816static void igb_probe_vfs(struct igb_adapter *adapter) 2817{ 2818#ifdef CONFIG_PCI_IOV 2819 struct pci_dev *pdev = adapter->pdev; 2820 struct e1000_hw *hw = &adapter->hw; 2821 2822 /* Virtualization features not supported on i210 family. */ 2823 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2824 return; 2825 2826 pci_sriov_set_totalvfs(pdev, 7); 2827 igb_pci_enable_sriov(pdev, max_vfs); 2828 2829#endif /* CONFIG_PCI_IOV */ 2830} 2831 2832static void igb_init_queue_configuration(struct igb_adapter *adapter) 2833{ 2834 struct e1000_hw *hw = &adapter->hw; 2835 u32 max_rss_queues; 2836 2837 /* Determine the maximum number of RSS queues supported. */ 2838 switch (hw->mac.type) { 2839 case e1000_i211: 2840 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2841 break; 2842 case e1000_82575: 2843 case e1000_i210: 2844 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2845 break; 2846 case e1000_i350: 2847 /* I350 cannot do RSS and SR-IOV at the same time */ 2848 if (!!adapter->vfs_allocated_count) { 2849 max_rss_queues = 1; 2850 break; 2851 } 2852 /* fall through */ 2853 case e1000_82576: 2854 if (!!adapter->vfs_allocated_count) { 2855 max_rss_queues = 2; 2856 break; 2857 } 2858 /* fall through */ 2859 case e1000_82580: 2860 case e1000_i354: 2861 default: 2862 max_rss_queues = IGB_MAX_RX_QUEUES; 2863 break; 2864 } 2865 2866 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2867 2868 /* Determine if we need to pair queues. */ 2869 switch (hw->mac.type) { 2870 case e1000_82575: 2871 case e1000_i211: 2872 /* Device supports enough interrupts without queue pairing. */ 2873 break; 2874 case e1000_82576: 2875 /* If VFs are going to be allocated with RSS queues then we 2876 * should pair the queues in order to conserve interrupts due 2877 * to limited supply. 2878 */ 2879 if ((adapter->rss_queues > 1) && 2880 (adapter->vfs_allocated_count > 6)) 2881 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2882 /* fall through */ 2883 case e1000_82580: 2884 case e1000_i350: 2885 case e1000_i354: 2886 case e1000_i210: 2887 default: 2888 /* If rss_queues > half of max_rss_queues, pair the queues in 2889 * order to conserve interrupts due to limited supply. 2890 */ 2891 if (adapter->rss_queues > (max_rss_queues / 2)) 2892 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2893 break; 2894 } 2895} 2896 2897/** 2898 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2899 * @adapter: board private structure to initialize 2900 * 2901 * igb_sw_init initializes the Adapter private data structure. 2902 * Fields are initialized based on PCI device information and 2903 * OS network device settings (MTU size). 2904 **/ 2905static int igb_sw_init(struct igb_adapter *adapter) 2906{ 2907 struct e1000_hw *hw = &adapter->hw; 2908 struct net_device *netdev = adapter->netdev; 2909 struct pci_dev *pdev = adapter->pdev; 2910 2911 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2912 2913 /* set default ring sizes */ 2914 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2915 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2916 2917 /* set default ITR values */ 2918 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2919 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2920 2921 /* set default work limits */ 2922 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2923 2924 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2925 VLAN_HLEN; 2926 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2927 2928 spin_lock_init(&adapter->stats64_lock); 2929#ifdef CONFIG_PCI_IOV 2930 switch (hw->mac.type) { 2931 case e1000_82576: 2932 case e1000_i350: 2933 if (max_vfs > 7) { 2934 dev_warn(&pdev->dev, 2935 "Maximum of 7 VFs per PF, using max\n"); 2936 max_vfs = adapter->vfs_allocated_count = 7; 2937 } else 2938 adapter->vfs_allocated_count = max_vfs; 2939 if (adapter->vfs_allocated_count) 2940 dev_warn(&pdev->dev, 2941 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 2942 break; 2943 default: 2944 break; 2945 } 2946#endif /* CONFIG_PCI_IOV */ 2947 2948 igb_init_queue_configuration(adapter); 2949 2950 /* Setup and initialize a copy of the hw vlan table array */ 2951 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 2952 GFP_ATOMIC); 2953 2954 /* This call may decrease the number of queues */ 2955 if (igb_init_interrupt_scheme(adapter, true)) { 2956 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2957 return -ENOMEM; 2958 } 2959 2960 igb_probe_vfs(adapter); 2961 2962 /* Explicitly disable IRQ since the NIC can be in any state. */ 2963 igb_irq_disable(adapter); 2964 2965 if (hw->mac.type >= e1000_i350) 2966 adapter->flags &= ~IGB_FLAG_DMAC; 2967 2968 set_bit(__IGB_DOWN, &adapter->state); 2969 return 0; 2970} 2971 2972/** 2973 * igb_open - Called when a network interface is made active 2974 * @netdev: network interface device structure 2975 * 2976 * Returns 0 on success, negative value on failure 2977 * 2978 * The open entry point is called when a network interface is made 2979 * active by the system (IFF_UP). At this point all resources needed 2980 * for transmit and receive operations are allocated, the interrupt 2981 * handler is registered with the OS, the watchdog timer is started, 2982 * and the stack is notified that the interface is ready. 2983 **/ 2984static int __igb_open(struct net_device *netdev, bool resuming) 2985{ 2986 struct igb_adapter *adapter = netdev_priv(netdev); 2987 struct e1000_hw *hw = &adapter->hw; 2988 struct pci_dev *pdev = adapter->pdev; 2989 int err; 2990 int i; 2991 2992 /* disallow open during test */ 2993 if (test_bit(__IGB_TESTING, &adapter->state)) { 2994 WARN_ON(resuming); 2995 return -EBUSY; 2996 } 2997 2998 if (!resuming) 2999 pm_runtime_get_sync(&pdev->dev); 3000 3001 netif_carrier_off(netdev); 3002 3003 /* allocate transmit descriptors */ 3004 err = igb_setup_all_tx_resources(adapter); 3005 if (err) 3006 goto err_setup_tx; 3007 3008 /* allocate receive descriptors */ 3009 err = igb_setup_all_rx_resources(adapter); 3010 if (err) 3011 goto err_setup_rx; 3012 3013 igb_power_up_link(adapter); 3014 3015 /* before we allocate an interrupt, we must be ready to handle it. 3016 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3017 * as soon as we call pci_request_irq, so we have to setup our 3018 * clean_rx handler before we do so. 3019 */ 3020 igb_configure(adapter); 3021 3022 err = igb_request_irq(adapter); 3023 if (err) 3024 goto err_req_irq; 3025 3026 /* Notify the stack of the actual queue counts. */ 3027 err = netif_set_real_num_tx_queues(adapter->netdev, 3028 adapter->num_tx_queues); 3029 if (err) 3030 goto err_set_queues; 3031 3032 err = netif_set_real_num_rx_queues(adapter->netdev, 3033 adapter->num_rx_queues); 3034 if (err) 3035 goto err_set_queues; 3036 3037 /* From here on the code is the same as igb_up() */ 3038 clear_bit(__IGB_DOWN, &adapter->state); 3039 3040 for (i = 0; i < adapter->num_q_vectors; i++) 3041 napi_enable(&(adapter->q_vector[i]->napi)); 3042 3043 /* Clear any pending interrupts. */ 3044 rd32(E1000_ICR); 3045 3046 igb_irq_enable(adapter); 3047 3048 /* notify VFs that reset has been completed */ 3049 if (adapter->vfs_allocated_count) { 3050 u32 reg_data = rd32(E1000_CTRL_EXT); 3051 reg_data |= E1000_CTRL_EXT_PFRSTD; 3052 wr32(E1000_CTRL_EXT, reg_data); 3053 } 3054 3055 netif_tx_start_all_queues(netdev); 3056 3057 if (!resuming) 3058 pm_runtime_put(&pdev->dev); 3059 3060 /* start the watchdog. */ 3061 hw->mac.get_link_status = 1; 3062 schedule_work(&adapter->watchdog_task); 3063 3064 return 0; 3065 3066err_set_queues: 3067 igb_free_irq(adapter); 3068err_req_irq: 3069 igb_release_hw_control(adapter); 3070 igb_power_down_link(adapter); 3071 igb_free_all_rx_resources(adapter); 3072err_setup_rx: 3073 igb_free_all_tx_resources(adapter); 3074err_setup_tx: 3075 igb_reset(adapter); 3076 if (!resuming) 3077 pm_runtime_put(&pdev->dev); 3078 3079 return err; 3080} 3081 3082static int igb_open(struct net_device *netdev) 3083{ 3084 return __igb_open(netdev, false); 3085} 3086 3087/** 3088 * igb_close - Disables a network interface 3089 * @netdev: network interface device structure 3090 * 3091 * Returns 0, this is not allowed to fail 3092 * 3093 * The close entry point is called when an interface is de-activated 3094 * by the OS. The hardware is still under the driver's control, but 3095 * needs to be disabled. A global MAC reset is issued to stop the 3096 * hardware, and all transmit and receive resources are freed. 3097 **/ 3098static int __igb_close(struct net_device *netdev, bool suspending) 3099{ 3100 struct igb_adapter *adapter = netdev_priv(netdev); 3101 struct pci_dev *pdev = adapter->pdev; 3102 3103 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3104 3105 if (!suspending) 3106 pm_runtime_get_sync(&pdev->dev); 3107 3108 igb_down(adapter); 3109 igb_free_irq(adapter); 3110 3111 igb_free_all_tx_resources(adapter); 3112 igb_free_all_rx_resources(adapter); 3113 3114 if (!suspending) 3115 pm_runtime_put_sync(&pdev->dev); 3116 return 0; 3117} 3118 3119static int igb_close(struct net_device *netdev) 3120{ 3121 return __igb_close(netdev, false); 3122} 3123 3124/** 3125 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3126 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3127 * 3128 * Return 0 on success, negative on failure 3129 **/ 3130int igb_setup_tx_resources(struct igb_ring *tx_ring) 3131{ 3132 struct device *dev = tx_ring->dev; 3133 int size; 3134 3135 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3136 3137 tx_ring->tx_buffer_info = vzalloc(size); 3138 if (!tx_ring->tx_buffer_info) 3139 goto err; 3140 3141 /* round up to nearest 4K */ 3142 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3143 tx_ring->size = ALIGN(tx_ring->size, 4096); 3144 3145 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3146 &tx_ring->dma, GFP_KERNEL); 3147 if (!tx_ring->desc) 3148 goto err; 3149 3150 tx_ring->next_to_use = 0; 3151 tx_ring->next_to_clean = 0; 3152 3153 return 0; 3154 3155err: 3156 vfree(tx_ring->tx_buffer_info); 3157 tx_ring->tx_buffer_info = NULL; 3158 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3159 return -ENOMEM; 3160} 3161 3162/** 3163 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3164 * (Descriptors) for all queues 3165 * @adapter: board private structure 3166 * 3167 * Return 0 on success, negative on failure 3168 **/ 3169static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3170{ 3171 struct pci_dev *pdev = adapter->pdev; 3172 int i, err = 0; 3173 3174 for (i = 0; i < adapter->num_tx_queues; i++) { 3175 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3176 if (err) { 3177 dev_err(&pdev->dev, 3178 "Allocation for Tx Queue %u failed\n", i); 3179 for (i--; i >= 0; i--) 3180 igb_free_tx_resources(adapter->tx_ring[i]); 3181 break; 3182 } 3183 } 3184 3185 return err; 3186} 3187 3188/** 3189 * igb_setup_tctl - configure the transmit control registers 3190 * @adapter: Board private structure 3191 **/ 3192void igb_setup_tctl(struct igb_adapter *adapter) 3193{ 3194 struct e1000_hw *hw = &adapter->hw; 3195 u32 tctl; 3196 3197 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3198 wr32(E1000_TXDCTL(0), 0); 3199 3200 /* Program the Transmit Control Register */ 3201 tctl = rd32(E1000_TCTL); 3202 tctl &= ~E1000_TCTL_CT; 3203 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3204 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3205 3206 igb_config_collision_dist(hw); 3207 3208 /* Enable transmits */ 3209 tctl |= E1000_TCTL_EN; 3210 3211 wr32(E1000_TCTL, tctl); 3212} 3213 3214/** 3215 * igb_configure_tx_ring - Configure transmit ring after Reset 3216 * @adapter: board private structure 3217 * @ring: tx ring to configure 3218 * 3219 * Configure a transmit ring after a reset. 3220 **/ 3221void igb_configure_tx_ring(struct igb_adapter *adapter, 3222 struct igb_ring *ring) 3223{ 3224 struct e1000_hw *hw = &adapter->hw; 3225 u32 txdctl = 0; 3226 u64 tdba = ring->dma; 3227 int reg_idx = ring->reg_idx; 3228 3229 /* disable the queue */ 3230 wr32(E1000_TXDCTL(reg_idx), 0); 3231 wrfl(); 3232 mdelay(10); 3233 3234 wr32(E1000_TDLEN(reg_idx), 3235 ring->count * sizeof(union e1000_adv_tx_desc)); 3236 wr32(E1000_TDBAL(reg_idx), 3237 tdba & 0x00000000ffffffffULL); 3238 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3239 3240 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 3241 wr32(E1000_TDH(reg_idx), 0); 3242 writel(0, ring->tail); 3243 3244 txdctl |= IGB_TX_PTHRESH; 3245 txdctl |= IGB_TX_HTHRESH << 8; 3246 txdctl |= IGB_TX_WTHRESH << 16; 3247 3248 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3249 wr32(E1000_TXDCTL(reg_idx), txdctl); 3250} 3251 3252/** 3253 * igb_configure_tx - Configure transmit Unit after Reset 3254 * @adapter: board private structure 3255 * 3256 * Configure the Tx unit of the MAC after a reset. 3257 **/ 3258static void igb_configure_tx(struct igb_adapter *adapter) 3259{ 3260 int i; 3261 3262 for (i = 0; i < adapter->num_tx_queues; i++) 3263 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3264} 3265 3266/** 3267 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3268 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3269 * 3270 * Returns 0 on success, negative on failure 3271 **/ 3272int igb_setup_rx_resources(struct igb_ring *rx_ring) 3273{ 3274 struct device *dev = rx_ring->dev; 3275 int size; 3276 3277 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3278 3279 rx_ring->rx_buffer_info = vzalloc(size); 3280 if (!rx_ring->rx_buffer_info) 3281 goto err; 3282 3283 /* Round up to nearest 4K */ 3284 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3285 rx_ring->size = ALIGN(rx_ring->size, 4096); 3286 3287 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3288 &rx_ring->dma, GFP_KERNEL); 3289 if (!rx_ring->desc) 3290 goto err; 3291 3292 rx_ring->next_to_alloc = 0; 3293 rx_ring->next_to_clean = 0; 3294 rx_ring->next_to_use = 0; 3295 3296 return 0; 3297 3298err: 3299 vfree(rx_ring->rx_buffer_info); 3300 rx_ring->rx_buffer_info = NULL; 3301 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3302 return -ENOMEM; 3303} 3304 3305/** 3306 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3307 * (Descriptors) for all queues 3308 * @adapter: board private structure 3309 * 3310 * Return 0 on success, negative on failure 3311 **/ 3312static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3313{ 3314 struct pci_dev *pdev = adapter->pdev; 3315 int i, err = 0; 3316 3317 for (i = 0; i < adapter->num_rx_queues; i++) { 3318 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3319 if (err) { 3320 dev_err(&pdev->dev, 3321 "Allocation for Rx Queue %u failed\n", i); 3322 for (i--; i >= 0; i--) 3323 igb_free_rx_resources(adapter->rx_ring[i]); 3324 break; 3325 } 3326 } 3327 3328 return err; 3329} 3330 3331/** 3332 * igb_setup_mrqc - configure the multiple receive queue control registers 3333 * @adapter: Board private structure 3334 **/ 3335static void igb_setup_mrqc(struct igb_adapter *adapter) 3336{ 3337 struct e1000_hw *hw = &adapter->hw; 3338 u32 mrqc, rxcsum; 3339 u32 j, num_rx_queues; 3340 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, 3341 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, 3342 0xA32DCB77, 0x0CF23080, 0x3BB7426A, 3343 0xFA01ACBE }; 3344 3345 /* Fill out hash function seeds */ 3346 for (j = 0; j < 10; j++) 3347 wr32(E1000_RSSRK(j), rsskey[j]); 3348 3349 num_rx_queues = adapter->rss_queues; 3350 3351 switch (hw->mac.type) { 3352 case e1000_82576: 3353 /* 82576 supports 2 RSS queues for SR-IOV */ 3354 if (adapter->vfs_allocated_count) 3355 num_rx_queues = 2; 3356 break; 3357 default: 3358 break; 3359 } 3360 3361 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3362 for (j = 0; j < IGB_RETA_SIZE; j++) 3363 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE; 3364 adapter->rss_indir_tbl_init = num_rx_queues; 3365 } 3366 igb_write_rss_indir_tbl(adapter); 3367 3368 /* Disable raw packet checksumming so that RSS hash is placed in 3369 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3370 * offloads as they are enabled by default 3371 */ 3372 rxcsum = rd32(E1000_RXCSUM); 3373 rxcsum |= E1000_RXCSUM_PCSD; 3374 3375 if (adapter->hw.mac.type >= e1000_82576) 3376 /* Enable Receive Checksum Offload for SCTP */ 3377 rxcsum |= E1000_RXCSUM_CRCOFL; 3378 3379 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3380 wr32(E1000_RXCSUM, rxcsum); 3381 3382 /* Generate RSS hash based on packet types, TCP/UDP 3383 * port numbers and/or IPv4/v6 src and dst addresses 3384 */ 3385 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3386 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3387 E1000_MRQC_RSS_FIELD_IPV6 | 3388 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3389 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3390 3391 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3392 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3393 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3394 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3395 3396 /* If VMDq is enabled then we set the appropriate mode for that, else 3397 * we default to RSS so that an RSS hash is calculated per packet even 3398 * if we are only using one queue 3399 */ 3400 if (adapter->vfs_allocated_count) { 3401 if (hw->mac.type > e1000_82575) { 3402 /* Set the default pool for the PF's first queue */ 3403 u32 vtctl = rd32(E1000_VT_CTL); 3404 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3405 E1000_VT_CTL_DISABLE_DEF_POOL); 3406 vtctl |= adapter->vfs_allocated_count << 3407 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3408 wr32(E1000_VT_CTL, vtctl); 3409 } 3410 if (adapter->rss_queues > 1) 3411 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 3412 else 3413 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3414 } else { 3415 if (hw->mac.type != e1000_i211) 3416 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 3417 } 3418 igb_vmm_control(adapter); 3419 3420 wr32(E1000_MRQC, mrqc); 3421} 3422 3423/** 3424 * igb_setup_rctl - configure the receive control registers 3425 * @adapter: Board private structure 3426 **/ 3427void igb_setup_rctl(struct igb_adapter *adapter) 3428{ 3429 struct e1000_hw *hw = &adapter->hw; 3430 u32 rctl; 3431 3432 rctl = rd32(E1000_RCTL); 3433 3434 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3435 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3436 3437 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3438 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3439 3440 /* enable stripping of CRC. It's unlikely this will break BMC 3441 * redirection as it did with e1000. Newer features require 3442 * that the HW strips the CRC. 3443 */ 3444 rctl |= E1000_RCTL_SECRC; 3445 3446 /* disable store bad packets and clear size bits. */ 3447 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3448 3449 /* enable LPE to prevent packets larger than max_frame_size */ 3450 rctl |= E1000_RCTL_LPE; 3451 3452 /* disable queue 0 to prevent tail write w/o re-config */ 3453 wr32(E1000_RXDCTL(0), 0); 3454 3455 /* Attention!!! For SR-IOV PF driver operations you must enable 3456 * queue drop for all VF and PF queues to prevent head of line blocking 3457 * if an un-trusted VF does not provide descriptors to hardware. 3458 */ 3459 if (adapter->vfs_allocated_count) { 3460 /* set all queue drop enable bits */ 3461 wr32(E1000_QDE, ALL_QUEUES); 3462 } 3463 3464 /* This is useful for sniffing bad packets. */ 3465 if (adapter->netdev->features & NETIF_F_RXALL) { 3466 /* UPE and MPE will be handled by normal PROMISC logic 3467 * in e1000e_set_rx_mode 3468 */ 3469 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3470 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3471 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3472 3473 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3474 E1000_RCTL_DPF | /* Allow filtered pause */ 3475 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3476 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3477 * and that breaks VLANs. 3478 */ 3479 } 3480 3481 wr32(E1000_RCTL, rctl); 3482} 3483 3484static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3485 int vfn) 3486{ 3487 struct e1000_hw *hw = &adapter->hw; 3488 u32 vmolr; 3489 3490 /* if it isn't the PF check to see if VFs are enabled and 3491 * increase the size to support vlan tags 3492 */ 3493 if (vfn < adapter->vfs_allocated_count && 3494 adapter->vf_data[vfn].vlans_enabled) 3495 size += VLAN_TAG_SIZE; 3496 3497 vmolr = rd32(E1000_VMOLR(vfn)); 3498 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3499 vmolr |= size | E1000_VMOLR_LPE; 3500 wr32(E1000_VMOLR(vfn), vmolr); 3501 3502 return 0; 3503} 3504 3505/** 3506 * igb_rlpml_set - set maximum receive packet size 3507 * @adapter: board private structure 3508 * 3509 * Configure maximum receivable packet size. 3510 **/ 3511static void igb_rlpml_set(struct igb_adapter *adapter) 3512{ 3513 u32 max_frame_size = adapter->max_frame_size; 3514 struct e1000_hw *hw = &adapter->hw; 3515 u16 pf_id = adapter->vfs_allocated_count; 3516 3517 if (pf_id) { 3518 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3519 /* If we're in VMDQ or SR-IOV mode, then set global RLPML 3520 * to our max jumbo frame size, in case we need to enable 3521 * jumbo frames on one of the rings later. 3522 * This will not pass over-length frames into the default 3523 * queue because it's gated by the VMOLR.RLPML. 3524 */ 3525 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3526 } 3527 3528 wr32(E1000_RLPML, max_frame_size); 3529} 3530 3531static inline void igb_set_vmolr(struct igb_adapter *adapter, 3532 int vfn, bool aupe) 3533{ 3534 struct e1000_hw *hw = &adapter->hw; 3535 u32 vmolr; 3536 3537 /* This register exists only on 82576 and newer so if we are older then 3538 * we should exit and do nothing 3539 */ 3540 if (hw->mac.type < e1000_82576) 3541 return; 3542 3543 vmolr = rd32(E1000_VMOLR(vfn)); 3544 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3545 if (hw->mac.type == e1000_i350) { 3546 u32 dvmolr; 3547 3548 dvmolr = rd32(E1000_DVMOLR(vfn)); 3549 dvmolr |= E1000_DVMOLR_STRVLAN; 3550 wr32(E1000_DVMOLR(vfn), dvmolr); 3551 } 3552 if (aupe) 3553 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3554 else 3555 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3556 3557 /* clear all bits that might not be set */ 3558 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3559 3560 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3561 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3562 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3563 * multicast packets 3564 */ 3565 if (vfn <= adapter->vfs_allocated_count) 3566 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3567 3568 wr32(E1000_VMOLR(vfn), vmolr); 3569} 3570 3571/** 3572 * igb_configure_rx_ring - Configure a receive ring after Reset 3573 * @adapter: board private structure 3574 * @ring: receive ring to be configured 3575 * 3576 * Configure the Rx unit of the MAC after a reset. 3577 **/ 3578void igb_configure_rx_ring(struct igb_adapter *adapter, 3579 struct igb_ring *ring) 3580{ 3581 struct e1000_hw *hw = &adapter->hw; 3582 u64 rdba = ring->dma; 3583 int reg_idx = ring->reg_idx; 3584 u32 srrctl = 0, rxdctl = 0; 3585 3586 /* disable the queue */ 3587 wr32(E1000_RXDCTL(reg_idx), 0); 3588 3589 /* Set DMA base address registers */ 3590 wr32(E1000_RDBAL(reg_idx), 3591 rdba & 0x00000000ffffffffULL); 3592 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3593 wr32(E1000_RDLEN(reg_idx), 3594 ring->count * sizeof(union e1000_adv_rx_desc)); 3595 3596 /* initialize head and tail */ 3597 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3598 wr32(E1000_RDH(reg_idx), 0); 3599 writel(0, ring->tail); 3600 3601 /* set descriptor configuration */ 3602 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3603 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3604 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3605 if (hw->mac.type >= e1000_82580) 3606 srrctl |= E1000_SRRCTL_TIMESTAMP; 3607 /* Only set Drop Enable if we are supporting multiple queues */ 3608 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3609 srrctl |= E1000_SRRCTL_DROP_EN; 3610 3611 wr32(E1000_SRRCTL(reg_idx), srrctl); 3612 3613 /* set filtering for VMDQ pools */ 3614 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3615 3616 rxdctl |= IGB_RX_PTHRESH; 3617 rxdctl |= IGB_RX_HTHRESH << 8; 3618 rxdctl |= IGB_RX_WTHRESH << 16; 3619 3620 /* enable receive descriptor fetching */ 3621 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3622 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3623} 3624 3625/** 3626 * igb_configure_rx - Configure receive Unit after Reset 3627 * @adapter: board private structure 3628 * 3629 * Configure the Rx unit of the MAC after a reset. 3630 **/ 3631static void igb_configure_rx(struct igb_adapter *adapter) 3632{ 3633 int i; 3634 3635 /* set UTA to appropriate mode */ 3636 igb_set_uta(adapter); 3637 3638 /* set the correct pool for the PF default MAC address in entry 0 */ 3639 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3640 adapter->vfs_allocated_count); 3641 3642 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3643 * the Base and Length of the Rx Descriptor Ring 3644 */ 3645 for (i = 0; i < adapter->num_rx_queues; i++) 3646 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3647} 3648 3649/** 3650 * igb_free_tx_resources - Free Tx Resources per Queue 3651 * @tx_ring: Tx descriptor ring for a specific queue 3652 * 3653 * Free all transmit software resources 3654 **/ 3655void igb_free_tx_resources(struct igb_ring *tx_ring) 3656{ 3657 igb_clean_tx_ring(tx_ring); 3658 3659 vfree(tx_ring->tx_buffer_info); 3660 tx_ring->tx_buffer_info = NULL; 3661 3662 /* if not set, then don't free */ 3663 if (!tx_ring->desc) 3664 return; 3665 3666 dma_free_coherent(tx_ring->dev, tx_ring->size, 3667 tx_ring->desc, tx_ring->dma); 3668 3669 tx_ring->desc = NULL; 3670} 3671 3672/** 3673 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3674 * @adapter: board private structure 3675 * 3676 * Free all transmit software resources 3677 **/ 3678static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3679{ 3680 int i; 3681 3682 for (i = 0; i < adapter->num_tx_queues; i++) 3683 igb_free_tx_resources(adapter->tx_ring[i]); 3684} 3685 3686void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3687 struct igb_tx_buffer *tx_buffer) 3688{ 3689 if (tx_buffer->skb) { 3690 dev_kfree_skb_any(tx_buffer->skb); 3691 if (dma_unmap_len(tx_buffer, len)) 3692 dma_unmap_single(ring->dev, 3693 dma_unmap_addr(tx_buffer, dma), 3694 dma_unmap_len(tx_buffer, len), 3695 DMA_TO_DEVICE); 3696 } else if (dma_unmap_len(tx_buffer, len)) { 3697 dma_unmap_page(ring->dev, 3698 dma_unmap_addr(tx_buffer, dma), 3699 dma_unmap_len(tx_buffer, len), 3700 DMA_TO_DEVICE); 3701 } 3702 tx_buffer->next_to_watch = NULL; 3703 tx_buffer->skb = NULL; 3704 dma_unmap_len_set(tx_buffer, len, 0); 3705 /* buffer_info must be completely set up in the transmit path */ 3706} 3707 3708/** 3709 * igb_clean_tx_ring - Free Tx Buffers 3710 * @tx_ring: ring to be cleaned 3711 **/ 3712static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3713{ 3714 struct igb_tx_buffer *buffer_info; 3715 unsigned long size; 3716 u16 i; 3717 3718 if (!tx_ring->tx_buffer_info) 3719 return; 3720 /* Free all the Tx ring sk_buffs */ 3721 3722 for (i = 0; i < tx_ring->count; i++) { 3723 buffer_info = &tx_ring->tx_buffer_info[i]; 3724 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3725 } 3726 3727 netdev_tx_reset_queue(txring_txq(tx_ring)); 3728 3729 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3730 memset(tx_ring->tx_buffer_info, 0, size); 3731 3732 /* Zero out the descriptor ring */ 3733 memset(tx_ring->desc, 0, tx_ring->size); 3734 3735 tx_ring->next_to_use = 0; 3736 tx_ring->next_to_clean = 0; 3737} 3738 3739/** 3740 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3741 * @adapter: board private structure 3742 **/ 3743static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3744{ 3745 int i; 3746 3747 for (i = 0; i < adapter->num_tx_queues; i++) 3748 igb_clean_tx_ring(adapter->tx_ring[i]); 3749} 3750 3751/** 3752 * igb_free_rx_resources - Free Rx Resources 3753 * @rx_ring: ring to clean the resources from 3754 * 3755 * Free all receive software resources 3756 **/ 3757void igb_free_rx_resources(struct igb_ring *rx_ring) 3758{ 3759 igb_clean_rx_ring(rx_ring); 3760 3761 vfree(rx_ring->rx_buffer_info); 3762 rx_ring->rx_buffer_info = NULL; 3763 3764 /* if not set, then don't free */ 3765 if (!rx_ring->desc) 3766 return; 3767 3768 dma_free_coherent(rx_ring->dev, rx_ring->size, 3769 rx_ring->desc, rx_ring->dma); 3770 3771 rx_ring->desc = NULL; 3772} 3773 3774/** 3775 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3776 * @adapter: board private structure 3777 * 3778 * Free all receive software resources 3779 **/ 3780static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3781{ 3782 int i; 3783 3784 for (i = 0; i < adapter->num_rx_queues; i++) 3785 igb_free_rx_resources(adapter->rx_ring[i]); 3786} 3787 3788/** 3789 * igb_clean_rx_ring - Free Rx Buffers per Queue 3790 * @rx_ring: ring to free buffers from 3791 **/ 3792static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3793{ 3794 unsigned long size; 3795 u16 i; 3796 3797 if (rx_ring->skb) 3798 dev_kfree_skb(rx_ring->skb); 3799 rx_ring->skb = NULL; 3800 3801 if (!rx_ring->rx_buffer_info) 3802 return; 3803 3804 /* Free all the Rx ring sk_buffs */ 3805 for (i = 0; i < rx_ring->count; i++) { 3806 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3807 3808 if (!buffer_info->page) 3809 continue; 3810 3811 dma_unmap_page(rx_ring->dev, 3812 buffer_info->dma, 3813 PAGE_SIZE, 3814 DMA_FROM_DEVICE); 3815 __free_page(buffer_info->page); 3816 3817 buffer_info->page = NULL; 3818 } 3819 3820 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3821 memset(rx_ring->rx_buffer_info, 0, size); 3822 3823 /* Zero out the descriptor ring */ 3824 memset(rx_ring->desc, 0, rx_ring->size); 3825 3826 rx_ring->next_to_alloc = 0; 3827 rx_ring->next_to_clean = 0; 3828 rx_ring->next_to_use = 0; 3829} 3830 3831/** 3832 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3833 * @adapter: board private structure 3834 **/ 3835static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3836{ 3837 int i; 3838 3839 for (i = 0; i < adapter->num_rx_queues; i++) 3840 igb_clean_rx_ring(adapter->rx_ring[i]); 3841} 3842 3843/** 3844 * igb_set_mac - Change the Ethernet Address of the NIC 3845 * @netdev: network interface device structure 3846 * @p: pointer to an address structure 3847 * 3848 * Returns 0 on success, negative on failure 3849 **/ 3850static int igb_set_mac(struct net_device *netdev, void *p) 3851{ 3852 struct igb_adapter *adapter = netdev_priv(netdev); 3853 struct e1000_hw *hw = &adapter->hw; 3854 struct sockaddr *addr = p; 3855 3856 if (!is_valid_ether_addr(addr->sa_data)) 3857 return -EADDRNOTAVAIL; 3858 3859 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3860 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3861 3862 /* set the correct pool for the new PF MAC address in entry 0 */ 3863 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3864 adapter->vfs_allocated_count); 3865 3866 return 0; 3867} 3868 3869/** 3870 * igb_write_mc_addr_list - write multicast addresses to MTA 3871 * @netdev: network interface device structure 3872 * 3873 * Writes multicast address list to the MTA hash table. 3874 * Returns: -ENOMEM on failure 3875 * 0 on no addresses written 3876 * X on writing X addresses to MTA 3877 **/ 3878static int igb_write_mc_addr_list(struct net_device *netdev) 3879{ 3880 struct igb_adapter *adapter = netdev_priv(netdev); 3881 struct e1000_hw *hw = &adapter->hw; 3882 struct netdev_hw_addr *ha; 3883 u8 *mta_list; 3884 int i; 3885 3886 if (netdev_mc_empty(netdev)) { 3887 /* nothing to program, so clear mc list */ 3888 igb_update_mc_addr_list(hw, NULL, 0); 3889 igb_restore_vf_multicasts(adapter); 3890 return 0; 3891 } 3892 3893 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3894 if (!mta_list) 3895 return -ENOMEM; 3896 3897 /* The shared function expects a packed array of only addresses. */ 3898 i = 0; 3899 netdev_for_each_mc_addr(ha, netdev) 3900 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3901 3902 igb_update_mc_addr_list(hw, mta_list, i); 3903 kfree(mta_list); 3904 3905 return netdev_mc_count(netdev); 3906} 3907 3908/** 3909 * igb_write_uc_addr_list - write unicast addresses to RAR table 3910 * @netdev: network interface device structure 3911 * 3912 * Writes unicast address list to the RAR table. 3913 * Returns: -ENOMEM on failure/insufficient address space 3914 * 0 on no addresses written 3915 * X on writing X addresses to the RAR table 3916 **/ 3917static int igb_write_uc_addr_list(struct net_device *netdev) 3918{ 3919 struct igb_adapter *adapter = netdev_priv(netdev); 3920 struct e1000_hw *hw = &adapter->hw; 3921 unsigned int vfn = adapter->vfs_allocated_count; 3922 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3923 int count = 0; 3924 3925 /* return ENOMEM indicating insufficient memory for addresses */ 3926 if (netdev_uc_count(netdev) > rar_entries) 3927 return -ENOMEM; 3928 3929 if (!netdev_uc_empty(netdev) && rar_entries) { 3930 struct netdev_hw_addr *ha; 3931 3932 netdev_for_each_uc_addr(ha, netdev) { 3933 if (!rar_entries) 3934 break; 3935 igb_rar_set_qsel(adapter, ha->addr, 3936 rar_entries--, 3937 vfn); 3938 count++; 3939 } 3940 } 3941 /* write the addresses in reverse order to avoid write combining */ 3942 for (; rar_entries > 0 ; rar_entries--) { 3943 wr32(E1000_RAH(rar_entries), 0); 3944 wr32(E1000_RAL(rar_entries), 0); 3945 } 3946 wrfl(); 3947 3948 return count; 3949} 3950 3951/** 3952 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3953 * @netdev: network interface device structure 3954 * 3955 * The set_rx_mode entry point is called whenever the unicast or multicast 3956 * address lists or the network interface flags are updated. This routine is 3957 * responsible for configuring the hardware for proper unicast, multicast, 3958 * promiscuous mode, and all-multi behavior. 3959 **/ 3960static void igb_set_rx_mode(struct net_device *netdev) 3961{ 3962 struct igb_adapter *adapter = netdev_priv(netdev); 3963 struct e1000_hw *hw = &adapter->hw; 3964 unsigned int vfn = adapter->vfs_allocated_count; 3965 u32 rctl, vmolr = 0; 3966 int count; 3967 3968 /* Check for Promiscuous and All Multicast modes */ 3969 rctl = rd32(E1000_RCTL); 3970 3971 /* clear the effected bits */ 3972 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 3973 3974 if (netdev->flags & IFF_PROMISC) { 3975 /* retain VLAN HW filtering if in VT mode */ 3976 if (adapter->vfs_allocated_count) 3977 rctl |= E1000_RCTL_VFE; 3978 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3979 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 3980 } else { 3981 if (netdev->flags & IFF_ALLMULTI) { 3982 rctl |= E1000_RCTL_MPE; 3983 vmolr |= E1000_VMOLR_MPME; 3984 } else { 3985 /* Write addresses to the MTA, if the attempt fails 3986 * then we should just turn on promiscuous mode so 3987 * that we can at least receive multicast traffic 3988 */ 3989 count = igb_write_mc_addr_list(netdev); 3990 if (count < 0) { 3991 rctl |= E1000_RCTL_MPE; 3992 vmolr |= E1000_VMOLR_MPME; 3993 } else if (count) { 3994 vmolr |= E1000_VMOLR_ROMPE; 3995 } 3996 } 3997 /* Write addresses to available RAR registers, if there is not 3998 * sufficient space to store all the addresses then enable 3999 * unicast promiscuous mode 4000 */ 4001 count = igb_write_uc_addr_list(netdev); 4002 if (count < 0) { 4003 rctl |= E1000_RCTL_UPE; 4004 vmolr |= E1000_VMOLR_ROPE; 4005 } 4006 rctl |= E1000_RCTL_VFE; 4007 } 4008 wr32(E1000_RCTL, rctl); 4009 4010 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4011 * the VMOLR to enable the appropriate modes. Without this workaround 4012 * we will have issues with VLAN tag stripping not being done for frames 4013 * that are only arriving because we are the default pool 4014 */ 4015 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4016 return; 4017 4018 vmolr |= rd32(E1000_VMOLR(vfn)) & 4019 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4020 wr32(E1000_VMOLR(vfn), vmolr); 4021 igb_restore_vf_multicasts(adapter); 4022} 4023 4024static void igb_check_wvbr(struct igb_adapter *adapter) 4025{ 4026 struct e1000_hw *hw = &adapter->hw; 4027 u32 wvbr = 0; 4028 4029 switch (hw->mac.type) { 4030 case e1000_82576: 4031 case e1000_i350: 4032 if (!(wvbr = rd32(E1000_WVBR))) 4033 return; 4034 break; 4035 default: 4036 break; 4037 } 4038 4039 adapter->wvbr |= wvbr; 4040} 4041 4042#define IGB_STAGGERED_QUEUE_OFFSET 8 4043 4044static void igb_spoof_check(struct igb_adapter *adapter) 4045{ 4046 int j; 4047 4048 if (!adapter->wvbr) 4049 return; 4050 4051 for(j = 0; j < adapter->vfs_allocated_count; j++) { 4052 if (adapter->wvbr & (1 << j) || 4053 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 4054 dev_warn(&adapter->pdev->dev, 4055 "Spoof event(s) detected on VF %d\n", j); 4056 adapter->wvbr &= 4057 ~((1 << j) | 4058 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 4059 } 4060 } 4061} 4062 4063/* Need to wait a few seconds after link up to get diagnostic information from 4064 * the phy 4065 */ 4066static void igb_update_phy_info(unsigned long data) 4067{ 4068 struct igb_adapter *adapter = (struct igb_adapter *) data; 4069 igb_get_phy_info(&adapter->hw); 4070} 4071 4072/** 4073 * igb_has_link - check shared code for link and determine up/down 4074 * @adapter: pointer to driver private info 4075 **/ 4076bool igb_has_link(struct igb_adapter *adapter) 4077{ 4078 struct e1000_hw *hw = &adapter->hw; 4079 bool link_active = false; 4080 4081 /* get_link_status is set on LSC (link status) interrupt or 4082 * rx sequence error interrupt. get_link_status will stay 4083 * false until the e1000_check_for_link establishes link 4084 * for copper adapters ONLY 4085 */ 4086 switch (hw->phy.media_type) { 4087 case e1000_media_type_copper: 4088 if (!hw->mac.get_link_status) 4089 return true; 4090 case e1000_media_type_internal_serdes: 4091 hw->mac.ops.check_for_link(hw); 4092 link_active = !hw->mac.get_link_status; 4093 break; 4094 default: 4095 case e1000_media_type_unknown: 4096 break; 4097 } 4098 4099 if (((hw->mac.type == e1000_i210) || 4100 (hw->mac.type == e1000_i211)) && 4101 (hw->phy.id == I210_I_PHY_ID)) { 4102 if (!netif_carrier_ok(adapter->netdev)) { 4103 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4104 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4105 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4106 adapter->link_check_timeout = jiffies; 4107 } 4108 } 4109 4110 return link_active; 4111} 4112 4113static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4114{ 4115 bool ret = false; 4116 u32 ctrl_ext, thstat; 4117 4118 /* check for thermal sensor event on i350 copper only */ 4119 if (hw->mac.type == e1000_i350) { 4120 thstat = rd32(E1000_THSTAT); 4121 ctrl_ext = rd32(E1000_CTRL_EXT); 4122 4123 if ((hw->phy.media_type == e1000_media_type_copper) && 4124 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4125 ret = !!(thstat & event); 4126 } 4127 4128 return ret; 4129} 4130 4131/** 4132 * igb_watchdog - Timer Call-back 4133 * @data: pointer to adapter cast into an unsigned long 4134 **/ 4135static void igb_watchdog(unsigned long data) 4136{ 4137 struct igb_adapter *adapter = (struct igb_adapter *)data; 4138 /* Do the rest outside of interrupt context */ 4139 schedule_work(&adapter->watchdog_task); 4140} 4141 4142static void igb_watchdog_task(struct work_struct *work) 4143{ 4144 struct igb_adapter *adapter = container_of(work, 4145 struct igb_adapter, 4146 watchdog_task); 4147 struct e1000_hw *hw = &adapter->hw; 4148 struct e1000_phy_info *phy = &hw->phy; 4149 struct net_device *netdev = adapter->netdev; 4150 u32 link; 4151 int i; 4152 u32 connsw; 4153 4154 link = igb_has_link(adapter); 4155 4156 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4157 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4158 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4159 else 4160 link = false; 4161 } 4162 4163 /* Force link down if we have fiber to swap to */ 4164 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4165 if (hw->phy.media_type == e1000_media_type_copper) { 4166 connsw = rd32(E1000_CONNSW); 4167 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4168 link = 0; 4169 } 4170 } 4171 if (link) { 4172 /* Perform a reset if the media type changed. */ 4173 if (hw->dev_spec._82575.media_changed) { 4174 hw->dev_spec._82575.media_changed = false; 4175 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4176 igb_reset(adapter); 4177 } 4178 /* Cancel scheduled suspend requests. */ 4179 pm_runtime_resume(netdev->dev.parent); 4180 4181 if (!netif_carrier_ok(netdev)) { 4182 u32 ctrl; 4183 hw->mac.ops.get_speed_and_duplex(hw, 4184 &adapter->link_speed, 4185 &adapter->link_duplex); 4186 4187 ctrl = rd32(E1000_CTRL); 4188 /* Links status message must follow this format */ 4189 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s " 4190 "Duplex, Flow Control: %s\n", 4191 netdev->name, 4192 adapter->link_speed, 4193 adapter->link_duplex == FULL_DUPLEX ? 4194 "Full" : "Half", 4195 (ctrl & E1000_CTRL_TFCE) && 4196 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4197 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4198 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4199 4200 /* disable EEE if enabled */ 4201 if ((adapter->flags & IGB_FLAG_EEE) && 4202 (adapter->link_duplex == HALF_DUPLEX)) { 4203 dev_info(&adapter->pdev->dev, 4204 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4205 adapter->hw.dev_spec._82575.eee_disable = true; 4206 adapter->flags &= ~IGB_FLAG_EEE; 4207 } 4208 4209 /* check if SmartSpeed worked */ 4210 igb_check_downshift(hw); 4211 if (phy->speed_downgraded) 4212 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4213 4214 /* check for thermal sensor event */ 4215 if (igb_thermal_sensor_event(hw, 4216 E1000_THSTAT_LINK_THROTTLE)) { 4217 netdev_info(netdev, "The network adapter link " 4218 "speed was downshifted because it " 4219 "overheated\n"); 4220 } 4221 4222 /* adjust timeout factor according to speed/duplex */ 4223 adapter->tx_timeout_factor = 1; 4224 switch (adapter->link_speed) { 4225 case SPEED_10: 4226 adapter->tx_timeout_factor = 14; 4227 break; 4228 case SPEED_100: 4229 /* maybe add some timeout factor ? */ 4230 break; 4231 } 4232 4233 netif_carrier_on(netdev); 4234 4235 igb_ping_all_vfs(adapter); 4236 igb_check_vf_rate_limit(adapter); 4237 4238 /* link state has changed, schedule phy info update */ 4239 if (!test_bit(__IGB_DOWN, &adapter->state)) 4240 mod_timer(&adapter->phy_info_timer, 4241 round_jiffies(jiffies + 2 * HZ)); 4242 } 4243 } else { 4244 if (netif_carrier_ok(netdev)) { 4245 adapter->link_speed = 0; 4246 adapter->link_duplex = 0; 4247 4248 /* check for thermal sensor event */ 4249 if (igb_thermal_sensor_event(hw, 4250 E1000_THSTAT_PWR_DOWN)) { 4251 netdev_err(netdev, "The network adapter was " 4252 "stopped because it overheated\n"); 4253 } 4254 4255 /* Links status message must follow this format */ 4256 printk(KERN_INFO "igb: %s NIC Link is Down\n", 4257 netdev->name); 4258 netif_carrier_off(netdev); 4259 4260 igb_ping_all_vfs(adapter); 4261 4262 /* link state has changed, schedule phy info update */ 4263 if (!test_bit(__IGB_DOWN, &adapter->state)) 4264 mod_timer(&adapter->phy_info_timer, 4265 round_jiffies(jiffies + 2 * HZ)); 4266 4267 /* link is down, time to check for alternate media */ 4268 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4269 igb_check_swap_media(adapter); 4270 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4271 schedule_work(&adapter->reset_task); 4272 /* return immediately */ 4273 return; 4274 } 4275 } 4276 pm_schedule_suspend(netdev->dev.parent, 4277 MSEC_PER_SEC * 5); 4278 4279 /* also check for alternate media here */ 4280 } else if (!netif_carrier_ok(netdev) && 4281 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4282 igb_check_swap_media(adapter); 4283 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4284 schedule_work(&adapter->reset_task); 4285 /* return immediately */ 4286 return; 4287 } 4288 } 4289 } 4290 4291 spin_lock(&adapter->stats64_lock); 4292 igb_update_stats(adapter, &adapter->stats64); 4293 spin_unlock(&adapter->stats64_lock); 4294 4295 for (i = 0; i < adapter->num_tx_queues; i++) { 4296 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4297 if (!netif_carrier_ok(netdev)) { 4298 /* We've lost link, so the controller stops DMA, 4299 * but we've got queued Tx work that's never going 4300 * to get done, so reset controller to flush Tx. 4301 * (Do the reset outside of interrupt context). 4302 */ 4303 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4304 adapter->tx_timeout_count++; 4305 schedule_work(&adapter->reset_task); 4306 /* return immediately since reset is imminent */ 4307 return; 4308 } 4309 } 4310 4311 /* Force detection of hung controller every watchdog period */ 4312 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4313 } 4314 4315 /* Cause software interrupt to ensure Rx ring is cleaned */ 4316 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4317 u32 eics = 0; 4318 for (i = 0; i < adapter->num_q_vectors; i++) 4319 eics |= adapter->q_vector[i]->eims_value; 4320 wr32(E1000_EICS, eics); 4321 } else { 4322 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4323 } 4324 4325 igb_spoof_check(adapter); 4326 igb_ptp_rx_hang(adapter); 4327 4328 /* Reset the timer */ 4329 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4330 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4331 mod_timer(&adapter->watchdog_timer, 4332 round_jiffies(jiffies + HZ)); 4333 else 4334 mod_timer(&adapter->watchdog_timer, 4335 round_jiffies(jiffies + 2 * HZ)); 4336 } 4337} 4338 4339enum latency_range { 4340 lowest_latency = 0, 4341 low_latency = 1, 4342 bulk_latency = 2, 4343 latency_invalid = 255 4344}; 4345 4346/** 4347 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4348 * @q_vector: pointer to q_vector 4349 * 4350 * Stores a new ITR value based on strictly on packet size. This 4351 * algorithm is less sophisticated than that used in igb_update_itr, 4352 * due to the difficulty of synchronizing statistics across multiple 4353 * receive rings. The divisors and thresholds used by this function 4354 * were determined based on theoretical maximum wire speed and testing 4355 * data, in order to minimize response time while increasing bulk 4356 * throughput. 4357 * This functionality is controlled by ethtool's coalescing settings. 4358 * NOTE: This function is called only when operating in a multiqueue 4359 * receive environment. 4360 **/ 4361static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4362{ 4363 int new_val = q_vector->itr_val; 4364 int avg_wire_size = 0; 4365 struct igb_adapter *adapter = q_vector->adapter; 4366 unsigned int packets; 4367 4368 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4369 * ints/sec - ITR timer value of 120 ticks. 4370 */ 4371 if (adapter->link_speed != SPEED_1000) { 4372 new_val = IGB_4K_ITR; 4373 goto set_itr_val; 4374 } 4375 4376 packets = q_vector->rx.total_packets; 4377 if (packets) 4378 avg_wire_size = q_vector->rx.total_bytes / packets; 4379 4380 packets = q_vector->tx.total_packets; 4381 if (packets) 4382 avg_wire_size = max_t(u32, avg_wire_size, 4383 q_vector->tx.total_bytes / packets); 4384 4385 /* if avg_wire_size isn't set no work was done */ 4386 if (!avg_wire_size) 4387 goto clear_counts; 4388 4389 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4390 avg_wire_size += 24; 4391 4392 /* Don't starve jumbo frames */ 4393 avg_wire_size = min(avg_wire_size, 3000); 4394 4395 /* Give a little boost to mid-size frames */ 4396 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4397 new_val = avg_wire_size / 3; 4398 else 4399 new_val = avg_wire_size / 2; 4400 4401 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4402 if (new_val < IGB_20K_ITR && 4403 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4404 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4405 new_val = IGB_20K_ITR; 4406 4407set_itr_val: 4408 if (new_val != q_vector->itr_val) { 4409 q_vector->itr_val = new_val; 4410 q_vector->set_itr = 1; 4411 } 4412clear_counts: 4413 q_vector->rx.total_bytes = 0; 4414 q_vector->rx.total_packets = 0; 4415 q_vector->tx.total_bytes = 0; 4416 q_vector->tx.total_packets = 0; 4417} 4418 4419/** 4420 * igb_update_itr - update the dynamic ITR value based on statistics 4421 * @q_vector: pointer to q_vector 4422 * @ring_container: ring info to update the itr for 4423 * 4424 * Stores a new ITR value based on packets and byte 4425 * counts during the last interrupt. The advantage of per interrupt 4426 * computation is faster updates and more accurate ITR for the current 4427 * traffic pattern. Constants in this function were computed 4428 * based on theoretical maximum wire speed and thresholds were set based 4429 * on testing data as well as attempting to minimize response time 4430 * while increasing bulk throughput. 4431 * This functionality is controlled by ethtool's coalescing settings. 4432 * NOTE: These calculations are only valid when operating in a single- 4433 * queue environment. 4434 **/ 4435static void igb_update_itr(struct igb_q_vector *q_vector, 4436 struct igb_ring_container *ring_container) 4437{ 4438 unsigned int packets = ring_container->total_packets; 4439 unsigned int bytes = ring_container->total_bytes; 4440 u8 itrval = ring_container->itr; 4441 4442 /* no packets, exit with status unchanged */ 4443 if (packets == 0) 4444 return; 4445 4446 switch (itrval) { 4447 case lowest_latency: 4448 /* handle TSO and jumbo frames */ 4449 if (bytes/packets > 8000) 4450 itrval = bulk_latency; 4451 else if ((packets < 5) && (bytes > 512)) 4452 itrval = low_latency; 4453 break; 4454 case low_latency: /* 50 usec aka 20000 ints/s */ 4455 if (bytes > 10000) { 4456 /* this if handles the TSO accounting */ 4457 if (bytes/packets > 8000) { 4458 itrval = bulk_latency; 4459 } else if ((packets < 10) || ((bytes/packets) > 1200)) { 4460 itrval = bulk_latency; 4461 } else if ((packets > 35)) { 4462 itrval = lowest_latency; 4463 } 4464 } else if (bytes/packets > 2000) { 4465 itrval = bulk_latency; 4466 } else if (packets <= 2 && bytes < 512) { 4467 itrval = lowest_latency; 4468 } 4469 break; 4470 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4471 if (bytes > 25000) { 4472 if (packets > 35) 4473 itrval = low_latency; 4474 } else if (bytes < 1500) { 4475 itrval = low_latency; 4476 } 4477 break; 4478 } 4479 4480 /* clear work counters since we have the values we need */ 4481 ring_container->total_bytes = 0; 4482 ring_container->total_packets = 0; 4483 4484 /* write updated itr to ring container */ 4485 ring_container->itr = itrval; 4486} 4487 4488static void igb_set_itr(struct igb_q_vector *q_vector) 4489{ 4490 struct igb_adapter *adapter = q_vector->adapter; 4491 u32 new_itr = q_vector->itr_val; 4492 u8 current_itr = 0; 4493 4494 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4495 if (adapter->link_speed != SPEED_1000) { 4496 current_itr = 0; 4497 new_itr = IGB_4K_ITR; 4498 goto set_itr_now; 4499 } 4500 4501 igb_update_itr(q_vector, &q_vector->tx); 4502 igb_update_itr(q_vector, &q_vector->rx); 4503 4504 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4505 4506 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4507 if (current_itr == lowest_latency && 4508 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4509 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4510 current_itr = low_latency; 4511 4512 switch (current_itr) { 4513 /* counts and packets in update_itr are dependent on these numbers */ 4514 case lowest_latency: 4515 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4516 break; 4517 case low_latency: 4518 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4519 break; 4520 case bulk_latency: 4521 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4522 break; 4523 default: 4524 break; 4525 } 4526 4527set_itr_now: 4528 if (new_itr != q_vector->itr_val) { 4529 /* this attempts to bias the interrupt rate towards Bulk 4530 * by adding intermediate steps when interrupt rate is 4531 * increasing 4532 */ 4533 new_itr = new_itr > q_vector->itr_val ? 4534 max((new_itr * q_vector->itr_val) / 4535 (new_itr + (q_vector->itr_val >> 2)), 4536 new_itr) : new_itr; 4537 /* Don't write the value here; it resets the adapter's 4538 * internal timer, and causes us to delay far longer than 4539 * we should between interrupts. Instead, we write the ITR 4540 * value at the beginning of the next interrupt so the timing 4541 * ends up being correct. 4542 */ 4543 q_vector->itr_val = new_itr; 4544 q_vector->set_itr = 1; 4545 } 4546} 4547 4548static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4549 u32 type_tucmd, u32 mss_l4len_idx) 4550{ 4551 struct e1000_adv_tx_context_desc *context_desc; 4552 u16 i = tx_ring->next_to_use; 4553 4554 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4555 4556 i++; 4557 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4558 4559 /* set bits to identify this as an advanced context descriptor */ 4560 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4561 4562 /* For 82575, context index must be unique per ring. */ 4563 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4564 mss_l4len_idx |= tx_ring->reg_idx << 4; 4565 4566 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4567 context_desc->seqnum_seed = 0; 4568 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4569 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4570} 4571 4572static int igb_tso(struct igb_ring *tx_ring, 4573 struct igb_tx_buffer *first, 4574 u8 *hdr_len) 4575{ 4576 struct sk_buff *skb = first->skb; 4577 u32 vlan_macip_lens, type_tucmd; 4578 u32 mss_l4len_idx, l4len; 4579 4580 if (skb->ip_summed != CHECKSUM_PARTIAL) 4581 return 0; 4582 4583 if (!skb_is_gso(skb)) 4584 return 0; 4585 4586 if (skb_header_cloned(skb)) { 4587 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 4588 if (err) 4589 return err; 4590 } 4591 4592 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4593 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4594 4595 if (first->protocol == htons(ETH_P_IP)) { 4596 struct iphdr *iph = ip_hdr(skb); 4597 iph->tot_len = 0; 4598 iph->check = 0; 4599 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4600 iph->daddr, 0, 4601 IPPROTO_TCP, 4602 0); 4603 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4604 first->tx_flags |= IGB_TX_FLAGS_TSO | 4605 IGB_TX_FLAGS_CSUM | 4606 IGB_TX_FLAGS_IPV4; 4607 } else if (skb_is_gso_v6(skb)) { 4608 ipv6_hdr(skb)->payload_len = 0; 4609 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4610 &ipv6_hdr(skb)->daddr, 4611 0, IPPROTO_TCP, 0); 4612 first->tx_flags |= IGB_TX_FLAGS_TSO | 4613 IGB_TX_FLAGS_CSUM; 4614 } 4615 4616 /* compute header lengths */ 4617 l4len = tcp_hdrlen(skb); 4618 *hdr_len = skb_transport_offset(skb) + l4len; 4619 4620 /* update gso size and bytecount with header size */ 4621 first->gso_segs = skb_shinfo(skb)->gso_segs; 4622 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4623 4624 /* MSS L4LEN IDX */ 4625 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4626 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4627 4628 /* VLAN MACLEN IPLEN */ 4629 vlan_macip_lens = skb_network_header_len(skb); 4630 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4631 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4632 4633 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4634 4635 return 1; 4636} 4637 4638static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4639{ 4640 struct sk_buff *skb = first->skb; 4641 u32 vlan_macip_lens = 0; 4642 u32 mss_l4len_idx = 0; 4643 u32 type_tucmd = 0; 4644 4645 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4646 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4647 return; 4648 } else { 4649 u8 l4_hdr = 0; 4650 switch (first->protocol) { 4651 case htons(ETH_P_IP): 4652 vlan_macip_lens |= skb_network_header_len(skb); 4653 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4654 l4_hdr = ip_hdr(skb)->protocol; 4655 break; 4656 case htons(ETH_P_IPV6): 4657 vlan_macip_lens |= skb_network_header_len(skb); 4658 l4_hdr = ipv6_hdr(skb)->nexthdr; 4659 break; 4660 default: 4661 if (unlikely(net_ratelimit())) { 4662 dev_warn(tx_ring->dev, 4663 "partial checksum but proto=%x!\n", 4664 first->protocol); 4665 } 4666 break; 4667 } 4668 4669 switch (l4_hdr) { 4670 case IPPROTO_TCP: 4671 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4672 mss_l4len_idx = tcp_hdrlen(skb) << 4673 E1000_ADVTXD_L4LEN_SHIFT; 4674 break; 4675 case IPPROTO_SCTP: 4676 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4677 mss_l4len_idx = sizeof(struct sctphdr) << 4678 E1000_ADVTXD_L4LEN_SHIFT; 4679 break; 4680 case IPPROTO_UDP: 4681 mss_l4len_idx = sizeof(struct udphdr) << 4682 E1000_ADVTXD_L4LEN_SHIFT; 4683 break; 4684 default: 4685 if (unlikely(net_ratelimit())) { 4686 dev_warn(tx_ring->dev, 4687 "partial checksum but l4 proto=%x!\n", 4688 l4_hdr); 4689 } 4690 break; 4691 } 4692 4693 /* update TX checksum flag */ 4694 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4695 } 4696 4697 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4698 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4699 4700 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4701} 4702 4703#define IGB_SET_FLAG(_input, _flag, _result) \ 4704 ((_flag <= _result) ? \ 4705 ((u32)(_input & _flag) * (_result / _flag)) : \ 4706 ((u32)(_input & _flag) / (_flag / _result))) 4707 4708static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 4709{ 4710 /* set type for advanced descriptor with frame checksum insertion */ 4711 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 4712 E1000_ADVTXD_DCMD_DEXT | 4713 E1000_ADVTXD_DCMD_IFCS; 4714 4715 /* set HW vlan bit if vlan is present */ 4716 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 4717 (E1000_ADVTXD_DCMD_VLE)); 4718 4719 /* set segmentation bits for TSO */ 4720 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 4721 (E1000_ADVTXD_DCMD_TSE)); 4722 4723 /* set timestamp bit if present */ 4724 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 4725 (E1000_ADVTXD_MAC_TSTAMP)); 4726 4727 /* insert frame checksum */ 4728 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 4729 4730 return cmd_type; 4731} 4732 4733static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4734 union e1000_adv_tx_desc *tx_desc, 4735 u32 tx_flags, unsigned int paylen) 4736{ 4737 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4738 4739 /* 82575 requires a unique index per ring */ 4740 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4741 olinfo_status |= tx_ring->reg_idx << 4; 4742 4743 /* insert L4 checksum */ 4744 olinfo_status |= IGB_SET_FLAG(tx_flags, 4745 IGB_TX_FLAGS_CSUM, 4746 (E1000_TXD_POPTS_TXSM << 8)); 4747 4748 /* insert IPv4 checksum */ 4749 olinfo_status |= IGB_SET_FLAG(tx_flags, 4750 IGB_TX_FLAGS_IPV4, 4751 (E1000_TXD_POPTS_IXSM << 8)); 4752 4753 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4754} 4755 4756static void igb_tx_map(struct igb_ring *tx_ring, 4757 struct igb_tx_buffer *first, 4758 const u8 hdr_len) 4759{ 4760 struct sk_buff *skb = first->skb; 4761 struct igb_tx_buffer *tx_buffer; 4762 union e1000_adv_tx_desc *tx_desc; 4763 struct skb_frag_struct *frag; 4764 dma_addr_t dma; 4765 unsigned int data_len, size; 4766 u32 tx_flags = first->tx_flags; 4767 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 4768 u16 i = tx_ring->next_to_use; 4769 4770 tx_desc = IGB_TX_DESC(tx_ring, i); 4771 4772 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 4773 4774 size = skb_headlen(skb); 4775 data_len = skb->data_len; 4776 4777 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4778 4779 tx_buffer = first; 4780 4781 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 4782 if (dma_mapping_error(tx_ring->dev, dma)) 4783 goto dma_error; 4784 4785 /* record length, and DMA address */ 4786 dma_unmap_len_set(tx_buffer, len, size); 4787 dma_unmap_addr_set(tx_buffer, dma, dma); 4788 4789 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4790 4791 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4792 tx_desc->read.cmd_type_len = 4793 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 4794 4795 i++; 4796 tx_desc++; 4797 if (i == tx_ring->count) { 4798 tx_desc = IGB_TX_DESC(tx_ring, 0); 4799 i = 0; 4800 } 4801 tx_desc->read.olinfo_status = 0; 4802 4803 dma += IGB_MAX_DATA_PER_TXD; 4804 size -= IGB_MAX_DATA_PER_TXD; 4805 4806 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4807 } 4808 4809 if (likely(!data_len)) 4810 break; 4811 4812 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 4813 4814 i++; 4815 tx_desc++; 4816 if (i == tx_ring->count) { 4817 tx_desc = IGB_TX_DESC(tx_ring, 0); 4818 i = 0; 4819 } 4820 tx_desc->read.olinfo_status = 0; 4821 4822 size = skb_frag_size(frag); 4823 data_len -= size; 4824 4825 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4826 size, DMA_TO_DEVICE); 4827 4828 tx_buffer = &tx_ring->tx_buffer_info[i]; 4829 } 4830 4831 /* write last descriptor with RS and EOP bits */ 4832 cmd_type |= size | IGB_TXD_DCMD; 4833 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 4834 4835 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4836 4837 /* set the timestamp */ 4838 first->time_stamp = jiffies; 4839 4840 /* Force memory writes to complete before letting h/w know there 4841 * are new descriptors to fetch. (Only applicable for weak-ordered 4842 * memory model archs, such as IA-64). 4843 * 4844 * We also need this memory barrier to make certain all of the 4845 * status bits have been updated before next_to_watch is written. 4846 */ 4847 wmb(); 4848 4849 /* set next_to_watch value indicating a packet is present */ 4850 first->next_to_watch = tx_desc; 4851 4852 i++; 4853 if (i == tx_ring->count) 4854 i = 0; 4855 4856 tx_ring->next_to_use = i; 4857 4858 writel(i, tx_ring->tail); 4859 4860 /* we need this if more than one processor can write to our tail 4861 * at a time, it synchronizes IO on IA64/Altix systems 4862 */ 4863 mmiowb(); 4864 4865 return; 4866 4867dma_error: 4868 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4869 4870 /* clear dma mappings for failed tx_buffer_info map */ 4871 for (;;) { 4872 tx_buffer = &tx_ring->tx_buffer_info[i]; 4873 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4874 if (tx_buffer == first) 4875 break; 4876 if (i == 0) 4877 i = tx_ring->count; 4878 i--; 4879 } 4880 4881 tx_ring->next_to_use = i; 4882} 4883 4884static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4885{ 4886 struct net_device *netdev = tx_ring->netdev; 4887 4888 netif_stop_subqueue(netdev, tx_ring->queue_index); 4889 4890 /* Herbert's original patch had: 4891 * smp_mb__after_netif_stop_queue(); 4892 * but since that doesn't exist yet, just open code it. 4893 */ 4894 smp_mb(); 4895 4896 /* We need to check again in a case another CPU has just 4897 * made room available. 4898 */ 4899 if (igb_desc_unused(tx_ring) < size) 4900 return -EBUSY; 4901 4902 /* A reprieve! */ 4903 netif_wake_subqueue(netdev, tx_ring->queue_index); 4904 4905 u64_stats_update_begin(&tx_ring->tx_syncp2); 4906 tx_ring->tx_stats.restart_queue2++; 4907 u64_stats_update_end(&tx_ring->tx_syncp2); 4908 4909 return 0; 4910} 4911 4912static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4913{ 4914 if (igb_desc_unused(tx_ring) >= size) 4915 return 0; 4916 return __igb_maybe_stop_tx(tx_ring, size); 4917} 4918 4919netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4920 struct igb_ring *tx_ring) 4921{ 4922 struct igb_tx_buffer *first; 4923 int tso; 4924 u32 tx_flags = 0; 4925 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 4926 __be16 protocol = vlan_get_protocol(skb); 4927 u8 hdr_len = 0; 4928 4929 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 4930 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 4931 * + 2 desc gap to keep tail from touching head, 4932 * + 1 desc for context descriptor, 4933 * otherwise try next time 4934 */ 4935 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) { 4936 unsigned short f; 4937 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 4938 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 4939 } else { 4940 count += skb_shinfo(skb)->nr_frags; 4941 } 4942 4943 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 4944 /* this is a hard error */ 4945 return NETDEV_TX_BUSY; 4946 } 4947 4948 /* record the location of the first descriptor for this packet */ 4949 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 4950 first->skb = skb; 4951 first->bytecount = skb->len; 4952 first->gso_segs = 1; 4953 4954 skb_tx_timestamp(skb); 4955 4956 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 4957 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 4958 4959 if (!(adapter->ptp_tx_skb)) { 4960 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4961 tx_flags |= IGB_TX_FLAGS_TSTAMP; 4962 4963 adapter->ptp_tx_skb = skb_get(skb); 4964 adapter->ptp_tx_start = jiffies; 4965 if (adapter->hw.mac.type == e1000_82576) 4966 schedule_work(&adapter->ptp_tx_work); 4967 } 4968 } 4969 4970 if (vlan_tx_tag_present(skb)) { 4971 tx_flags |= IGB_TX_FLAGS_VLAN; 4972 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 4973 } 4974 4975 /* record initial flags and protocol */ 4976 first->tx_flags = tx_flags; 4977 first->protocol = protocol; 4978 4979 tso = igb_tso(tx_ring, first, &hdr_len); 4980 if (tso < 0) 4981 goto out_drop; 4982 else if (!tso) 4983 igb_tx_csum(tx_ring, first); 4984 4985 igb_tx_map(tx_ring, first, hdr_len); 4986 4987 /* Make sure there is space in the ring for the next send. */ 4988 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 4989 4990 return NETDEV_TX_OK; 4991 4992out_drop: 4993 igb_unmap_and_free_tx_resource(tx_ring, first); 4994 4995 return NETDEV_TX_OK; 4996} 4997 4998static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 4999 struct sk_buff *skb) 5000{ 5001 unsigned int r_idx = skb->queue_mapping; 5002 5003 if (r_idx >= adapter->num_tx_queues) 5004 r_idx = r_idx % adapter->num_tx_queues; 5005 5006 return adapter->tx_ring[r_idx]; 5007} 5008 5009static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5010 struct net_device *netdev) 5011{ 5012 struct igb_adapter *adapter = netdev_priv(netdev); 5013 5014 if (test_bit(__IGB_DOWN, &adapter->state)) { 5015 dev_kfree_skb_any(skb); 5016 return NETDEV_TX_OK; 5017 } 5018 5019 if (skb->len <= 0) { 5020 dev_kfree_skb_any(skb); 5021 return NETDEV_TX_OK; 5022 } 5023 5024 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5025 * in order to meet this minimum size requirement. 5026 */ 5027 if (unlikely(skb->len < 17)) { 5028 if (skb_pad(skb, 17 - skb->len)) 5029 return NETDEV_TX_OK; 5030 skb->len = 17; 5031 skb_set_tail_pointer(skb, 17); 5032 } 5033 5034 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5035} 5036 5037/** 5038 * igb_tx_timeout - Respond to a Tx Hang 5039 * @netdev: network interface device structure 5040 **/ 5041static void igb_tx_timeout(struct net_device *netdev) 5042{ 5043 struct igb_adapter *adapter = netdev_priv(netdev); 5044 struct e1000_hw *hw = &adapter->hw; 5045 5046 /* Do the reset outside of interrupt context */ 5047 adapter->tx_timeout_count++; 5048 5049 if (hw->mac.type >= e1000_82580) 5050 hw->dev_spec._82575.global_device_reset = true; 5051 5052 schedule_work(&adapter->reset_task); 5053 wr32(E1000_EICS, 5054 (adapter->eims_enable_mask & ~adapter->eims_other)); 5055} 5056 5057static void igb_reset_task(struct work_struct *work) 5058{ 5059 struct igb_adapter *adapter; 5060 adapter = container_of(work, struct igb_adapter, reset_task); 5061 5062 igb_dump(adapter); 5063 netdev_err(adapter->netdev, "Reset adapter\n"); 5064 igb_reinit_locked(adapter); 5065} 5066 5067/** 5068 * igb_get_stats64 - Get System Network Statistics 5069 * @netdev: network interface device structure 5070 * @stats: rtnl_link_stats64 pointer 5071 **/ 5072static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 5073 struct rtnl_link_stats64 *stats) 5074{ 5075 struct igb_adapter *adapter = netdev_priv(netdev); 5076 5077 spin_lock(&adapter->stats64_lock); 5078 igb_update_stats(adapter, &adapter->stats64); 5079 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5080 spin_unlock(&adapter->stats64_lock); 5081 5082 return stats; 5083} 5084 5085/** 5086 * igb_change_mtu - Change the Maximum Transfer Unit 5087 * @netdev: network interface device structure 5088 * @new_mtu: new value for maximum frame size 5089 * 5090 * Returns 0 on success, negative on failure 5091 **/ 5092static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5093{ 5094 struct igb_adapter *adapter = netdev_priv(netdev); 5095 struct pci_dev *pdev = adapter->pdev; 5096 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5097 5098 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 5099 dev_err(&pdev->dev, "Invalid MTU setting\n"); 5100 return -EINVAL; 5101 } 5102 5103#define MAX_STD_JUMBO_FRAME_SIZE 9238 5104 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 5105 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 5106 return -EINVAL; 5107 } 5108 5109 /* adjust max frame to be at least the size of a standard frame */ 5110 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5111 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5112 5113 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5114 msleep(1); 5115 5116 /* igb_down has a dependency on max_frame_size */ 5117 adapter->max_frame_size = max_frame; 5118 5119 if (netif_running(netdev)) 5120 igb_down(adapter); 5121 5122 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5123 netdev->mtu, new_mtu); 5124 netdev->mtu = new_mtu; 5125 5126 if (netif_running(netdev)) 5127 igb_up(adapter); 5128 else 5129 igb_reset(adapter); 5130 5131 clear_bit(__IGB_RESETTING, &adapter->state); 5132 5133 return 0; 5134} 5135 5136/** 5137 * igb_update_stats - Update the board statistics counters 5138 * @adapter: board private structure 5139 **/ 5140void igb_update_stats(struct igb_adapter *adapter, 5141 struct rtnl_link_stats64 *net_stats) 5142{ 5143 struct e1000_hw *hw = &adapter->hw; 5144 struct pci_dev *pdev = adapter->pdev; 5145 u32 reg, mpc; 5146 u16 phy_tmp; 5147 int i; 5148 u64 bytes, packets; 5149 unsigned int start; 5150 u64 _bytes, _packets; 5151 5152#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF 5153 5154 /* Prevent stats update while adapter is being reset, or if the pci 5155 * connection is down. 5156 */ 5157 if (adapter->link_speed == 0) 5158 return; 5159 if (pci_channel_offline(pdev)) 5160 return; 5161 5162 bytes = 0; 5163 packets = 0; 5164 5165 rcu_read_lock(); 5166 for (i = 0; i < adapter->num_rx_queues; i++) { 5167 u32 rqdpc = rd32(E1000_RQDPC(i)); 5168 struct igb_ring *ring = adapter->rx_ring[i]; 5169 5170 if (rqdpc) { 5171 ring->rx_stats.drops += rqdpc; 5172 net_stats->rx_fifo_errors += rqdpc; 5173 } 5174 5175 do { 5176 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5177 _bytes = ring->rx_stats.bytes; 5178 _packets = ring->rx_stats.packets; 5179 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5180 bytes += _bytes; 5181 packets += _packets; 5182 } 5183 5184 net_stats->rx_bytes = bytes; 5185 net_stats->rx_packets = packets; 5186 5187 bytes = 0; 5188 packets = 0; 5189 for (i = 0; i < adapter->num_tx_queues; i++) { 5190 struct igb_ring *ring = adapter->tx_ring[i]; 5191 do { 5192 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5193 _bytes = ring->tx_stats.bytes; 5194 _packets = ring->tx_stats.packets; 5195 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5196 bytes += _bytes; 5197 packets += _packets; 5198 } 5199 net_stats->tx_bytes = bytes; 5200 net_stats->tx_packets = packets; 5201 rcu_read_unlock(); 5202 5203 /* read stats registers */ 5204 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5205 adapter->stats.gprc += rd32(E1000_GPRC); 5206 adapter->stats.gorc += rd32(E1000_GORCL); 5207 rd32(E1000_GORCH); /* clear GORCL */ 5208 adapter->stats.bprc += rd32(E1000_BPRC); 5209 adapter->stats.mprc += rd32(E1000_MPRC); 5210 adapter->stats.roc += rd32(E1000_ROC); 5211 5212 adapter->stats.prc64 += rd32(E1000_PRC64); 5213 adapter->stats.prc127 += rd32(E1000_PRC127); 5214 adapter->stats.prc255 += rd32(E1000_PRC255); 5215 adapter->stats.prc511 += rd32(E1000_PRC511); 5216 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5217 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5218 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5219 adapter->stats.sec += rd32(E1000_SEC); 5220 5221 mpc = rd32(E1000_MPC); 5222 adapter->stats.mpc += mpc; 5223 net_stats->rx_fifo_errors += mpc; 5224 adapter->stats.scc += rd32(E1000_SCC); 5225 adapter->stats.ecol += rd32(E1000_ECOL); 5226 adapter->stats.mcc += rd32(E1000_MCC); 5227 adapter->stats.latecol += rd32(E1000_LATECOL); 5228 adapter->stats.dc += rd32(E1000_DC); 5229 adapter->stats.rlec += rd32(E1000_RLEC); 5230 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5231 adapter->stats.xontxc += rd32(E1000_XONTXC); 5232 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5233 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5234 adapter->stats.fcruc += rd32(E1000_FCRUC); 5235 adapter->stats.gptc += rd32(E1000_GPTC); 5236 adapter->stats.gotc += rd32(E1000_GOTCL); 5237 rd32(E1000_GOTCH); /* clear GOTCL */ 5238 adapter->stats.rnbc += rd32(E1000_RNBC); 5239 adapter->stats.ruc += rd32(E1000_RUC); 5240 adapter->stats.rfc += rd32(E1000_RFC); 5241 adapter->stats.rjc += rd32(E1000_RJC); 5242 adapter->stats.tor += rd32(E1000_TORH); 5243 adapter->stats.tot += rd32(E1000_TOTH); 5244 adapter->stats.tpr += rd32(E1000_TPR); 5245 5246 adapter->stats.ptc64 += rd32(E1000_PTC64); 5247 adapter->stats.ptc127 += rd32(E1000_PTC127); 5248 adapter->stats.ptc255 += rd32(E1000_PTC255); 5249 adapter->stats.ptc511 += rd32(E1000_PTC511); 5250 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5251 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5252 5253 adapter->stats.mptc += rd32(E1000_MPTC); 5254 adapter->stats.bptc += rd32(E1000_BPTC); 5255 5256 adapter->stats.tpt += rd32(E1000_TPT); 5257 adapter->stats.colc += rd32(E1000_COLC); 5258 5259 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5260 /* read internal phy specific stats */ 5261 reg = rd32(E1000_CTRL_EXT); 5262 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5263 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5264 5265 /* this stat has invalid values on i210/i211 */ 5266 if ((hw->mac.type != e1000_i210) && 5267 (hw->mac.type != e1000_i211)) 5268 adapter->stats.tncrs += rd32(E1000_TNCRS); 5269 } 5270 5271 adapter->stats.tsctc += rd32(E1000_TSCTC); 5272 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5273 5274 adapter->stats.iac += rd32(E1000_IAC); 5275 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5276 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5277 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5278 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5279 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5280 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5281 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5282 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5283 5284 /* Fill out the OS statistics structure */ 5285 net_stats->multicast = adapter->stats.mprc; 5286 net_stats->collisions = adapter->stats.colc; 5287 5288 /* Rx Errors */ 5289 5290 /* RLEC on some newer hardware can be incorrect so build 5291 * our own version based on RUC and ROC 5292 */ 5293 net_stats->rx_errors = adapter->stats.rxerrc + 5294 adapter->stats.crcerrs + adapter->stats.algnerrc + 5295 adapter->stats.ruc + adapter->stats.roc + 5296 adapter->stats.cexterr; 5297 net_stats->rx_length_errors = adapter->stats.ruc + 5298 adapter->stats.roc; 5299 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5300 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5301 net_stats->rx_missed_errors = adapter->stats.mpc; 5302 5303 /* Tx Errors */ 5304 net_stats->tx_errors = adapter->stats.ecol + 5305 adapter->stats.latecol; 5306 net_stats->tx_aborted_errors = adapter->stats.ecol; 5307 net_stats->tx_window_errors = adapter->stats.latecol; 5308 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5309 5310 /* Tx Dropped needs to be maintained elsewhere */ 5311 5312 /* Phy Stats */ 5313 if (hw->phy.media_type == e1000_media_type_copper) { 5314 if ((adapter->link_speed == SPEED_1000) && 5315 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 5316 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; 5317 adapter->phy_stats.idle_errors += phy_tmp; 5318 } 5319 } 5320 5321 /* Management Stats */ 5322 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5323 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5324 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5325 5326 /* OS2BMC Stats */ 5327 reg = rd32(E1000_MANC); 5328 if (reg & E1000_MANC_EN_BMC2OS) { 5329 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5330 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5331 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5332 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5333 } 5334} 5335 5336static irqreturn_t igb_msix_other(int irq, void *data) 5337{ 5338 struct igb_adapter *adapter = data; 5339 struct e1000_hw *hw = &adapter->hw; 5340 u32 icr = rd32(E1000_ICR); 5341 /* reading ICR causes bit 31 of EICR to be cleared */ 5342 5343 if (icr & E1000_ICR_DRSTA) 5344 schedule_work(&adapter->reset_task); 5345 5346 if (icr & E1000_ICR_DOUTSYNC) { 5347 /* HW is reporting DMA is out of sync */ 5348 adapter->stats.doosync++; 5349 /* The DMA Out of Sync is also indication of a spoof event 5350 * in IOV mode. Check the Wrong VM Behavior register to 5351 * see if it is really a spoof event. 5352 */ 5353 igb_check_wvbr(adapter); 5354 } 5355 5356 /* Check for a mailbox event */ 5357 if (icr & E1000_ICR_VMMB) 5358 igb_msg_task(adapter); 5359 5360 if (icr & E1000_ICR_LSC) { 5361 hw->mac.get_link_status = 1; 5362 /* guard against interrupt when we're going down */ 5363 if (!test_bit(__IGB_DOWN, &adapter->state)) 5364 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5365 } 5366 5367 if (icr & E1000_ICR_TS) { 5368 u32 tsicr = rd32(E1000_TSICR); 5369 5370 if (tsicr & E1000_TSICR_TXTS) { 5371 /* acknowledge the interrupt */ 5372 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5373 /* retrieve hardware timestamp */ 5374 schedule_work(&adapter->ptp_tx_work); 5375 } 5376 } 5377 5378 wr32(E1000_EIMS, adapter->eims_other); 5379 5380 return IRQ_HANDLED; 5381} 5382 5383static void igb_write_itr(struct igb_q_vector *q_vector) 5384{ 5385 struct igb_adapter *adapter = q_vector->adapter; 5386 u32 itr_val = q_vector->itr_val & 0x7FFC; 5387 5388 if (!q_vector->set_itr) 5389 return; 5390 5391 if (!itr_val) 5392 itr_val = 0x4; 5393 5394 if (adapter->hw.mac.type == e1000_82575) 5395 itr_val |= itr_val << 16; 5396 else 5397 itr_val |= E1000_EITR_CNT_IGNR; 5398 5399 writel(itr_val, q_vector->itr_register); 5400 q_vector->set_itr = 0; 5401} 5402 5403static irqreturn_t igb_msix_ring(int irq, void *data) 5404{ 5405 struct igb_q_vector *q_vector = data; 5406 5407 /* Write the ITR value calculated from the previous interrupt. */ 5408 igb_write_itr(q_vector); 5409 5410 napi_schedule(&q_vector->napi); 5411 5412 return IRQ_HANDLED; 5413} 5414 5415#ifdef CONFIG_IGB_DCA 5416static void igb_update_tx_dca(struct igb_adapter *adapter, 5417 struct igb_ring *tx_ring, 5418 int cpu) 5419{ 5420 struct e1000_hw *hw = &adapter->hw; 5421 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5422 5423 if (hw->mac.type != e1000_82575) 5424 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5425 5426 /* We can enable relaxed ordering for reads, but not writes when 5427 * DCA is enabled. This is due to a known issue in some chipsets 5428 * which will cause the DCA tag to be cleared. 5429 */ 5430 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5431 E1000_DCA_TXCTRL_DATA_RRO_EN | 5432 E1000_DCA_TXCTRL_DESC_DCA_EN; 5433 5434 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5435} 5436 5437static void igb_update_rx_dca(struct igb_adapter *adapter, 5438 struct igb_ring *rx_ring, 5439 int cpu) 5440{ 5441 struct e1000_hw *hw = &adapter->hw; 5442 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5443 5444 if (hw->mac.type != e1000_82575) 5445 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5446 5447 /* We can enable relaxed ordering for reads, but not writes when 5448 * DCA is enabled. This is due to a known issue in some chipsets 5449 * which will cause the DCA tag to be cleared. 5450 */ 5451 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5452 E1000_DCA_RXCTRL_DESC_DCA_EN; 5453 5454 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5455} 5456 5457static void igb_update_dca(struct igb_q_vector *q_vector) 5458{ 5459 struct igb_adapter *adapter = q_vector->adapter; 5460 int cpu = get_cpu(); 5461 5462 if (q_vector->cpu == cpu) 5463 goto out_no_update; 5464 5465 if (q_vector->tx.ring) 5466 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5467 5468 if (q_vector->rx.ring) 5469 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5470 5471 q_vector->cpu = cpu; 5472out_no_update: 5473 put_cpu(); 5474} 5475 5476static void igb_setup_dca(struct igb_adapter *adapter) 5477{ 5478 struct e1000_hw *hw = &adapter->hw; 5479 int i; 5480 5481 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5482 return; 5483 5484 /* Always use CB2 mode, difference is masked in the CB driver. */ 5485 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5486 5487 for (i = 0; i < adapter->num_q_vectors; i++) { 5488 adapter->q_vector[i]->cpu = -1; 5489 igb_update_dca(adapter->q_vector[i]); 5490 } 5491} 5492 5493static int __igb_notify_dca(struct device *dev, void *data) 5494{ 5495 struct net_device *netdev = dev_get_drvdata(dev); 5496 struct igb_adapter *adapter = netdev_priv(netdev); 5497 struct pci_dev *pdev = adapter->pdev; 5498 struct e1000_hw *hw = &adapter->hw; 5499 unsigned long event = *(unsigned long *)data; 5500 5501 switch (event) { 5502 case DCA_PROVIDER_ADD: 5503 /* if already enabled, don't do it again */ 5504 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5505 break; 5506 if (dca_add_requester(dev) == 0) { 5507 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5508 dev_info(&pdev->dev, "DCA enabled\n"); 5509 igb_setup_dca(adapter); 5510 break; 5511 } 5512 /* Fall Through since DCA is disabled. */ 5513 case DCA_PROVIDER_REMOVE: 5514 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5515 /* without this a class_device is left 5516 * hanging around in the sysfs model 5517 */ 5518 dca_remove_requester(dev); 5519 dev_info(&pdev->dev, "DCA disabled\n"); 5520 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5521 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5522 } 5523 break; 5524 } 5525 5526 return 0; 5527} 5528 5529static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5530 void *p) 5531{ 5532 int ret_val; 5533 5534 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5535 __igb_notify_dca); 5536 5537 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5538} 5539#endif /* CONFIG_IGB_DCA */ 5540 5541#ifdef CONFIG_PCI_IOV 5542static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5543{ 5544 unsigned char mac_addr[ETH_ALEN]; 5545 5546 eth_zero_addr(mac_addr); 5547 igb_set_vf_mac(adapter, vf, mac_addr); 5548 5549 /* By default spoof check is enabled for all VFs */ 5550 adapter->vf_data[vf].spoofchk_enabled = true; 5551 5552 return 0; 5553} 5554 5555#endif 5556static void igb_ping_all_vfs(struct igb_adapter *adapter) 5557{ 5558 struct e1000_hw *hw = &adapter->hw; 5559 u32 ping; 5560 int i; 5561 5562 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5563 ping = E1000_PF_CONTROL_MSG; 5564 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5565 ping |= E1000_VT_MSGTYPE_CTS; 5566 igb_write_mbx(hw, &ping, 1, i); 5567 } 5568} 5569 5570static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5571{ 5572 struct e1000_hw *hw = &adapter->hw; 5573 u32 vmolr = rd32(E1000_VMOLR(vf)); 5574 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5575 5576 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5577 IGB_VF_FLAG_MULTI_PROMISC); 5578 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5579 5580 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5581 vmolr |= E1000_VMOLR_MPME; 5582 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5583 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5584 } else { 5585 /* if we have hashes and we are clearing a multicast promisc 5586 * flag we need to write the hashes to the MTA as this step 5587 * was previously skipped 5588 */ 5589 if (vf_data->num_vf_mc_hashes > 30) { 5590 vmolr |= E1000_VMOLR_MPME; 5591 } else if (vf_data->num_vf_mc_hashes) { 5592 int j; 5593 vmolr |= E1000_VMOLR_ROMPE; 5594 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5595 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5596 } 5597 } 5598 5599 wr32(E1000_VMOLR(vf), vmolr); 5600 5601 /* there are flags left unprocessed, likely not supported */ 5602 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5603 return -EINVAL; 5604 5605 return 0; 5606} 5607 5608static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5609 u32 *msgbuf, u32 vf) 5610{ 5611 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5612 u16 *hash_list = (u16 *)&msgbuf[1]; 5613 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5614 int i; 5615 5616 /* salt away the number of multicast addresses assigned 5617 * to this VF for later use to restore when the PF multi cast 5618 * list changes 5619 */ 5620 vf_data->num_vf_mc_hashes = n; 5621 5622 /* only up to 30 hash values supported */ 5623 if (n > 30) 5624 n = 30; 5625 5626 /* store the hashes for later use */ 5627 for (i = 0; i < n; i++) 5628 vf_data->vf_mc_hashes[i] = hash_list[i]; 5629 5630 /* Flush and reset the mta with the new values */ 5631 igb_set_rx_mode(adapter->netdev); 5632 5633 return 0; 5634} 5635 5636static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5637{ 5638 struct e1000_hw *hw = &adapter->hw; 5639 struct vf_data_storage *vf_data; 5640 int i, j; 5641 5642 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5643 u32 vmolr = rd32(E1000_VMOLR(i)); 5644 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5645 5646 vf_data = &adapter->vf_data[i]; 5647 5648 if ((vf_data->num_vf_mc_hashes > 30) || 5649 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5650 vmolr |= E1000_VMOLR_MPME; 5651 } else if (vf_data->num_vf_mc_hashes) { 5652 vmolr |= E1000_VMOLR_ROMPE; 5653 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5654 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5655 } 5656 wr32(E1000_VMOLR(i), vmolr); 5657 } 5658} 5659 5660static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5661{ 5662 struct e1000_hw *hw = &adapter->hw; 5663 u32 pool_mask, reg, vid; 5664 int i; 5665 5666 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5667 5668 /* Find the vlan filter for this id */ 5669 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5670 reg = rd32(E1000_VLVF(i)); 5671 5672 /* remove the vf from the pool */ 5673 reg &= ~pool_mask; 5674 5675 /* if pool is empty then remove entry from vfta */ 5676 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5677 (reg & E1000_VLVF_VLANID_ENABLE)) { 5678 reg = 0; 5679 vid = reg & E1000_VLVF_VLANID_MASK; 5680 igb_vfta_set(hw, vid, false); 5681 } 5682 5683 wr32(E1000_VLVF(i), reg); 5684 } 5685 5686 adapter->vf_data[vf].vlans_enabled = 0; 5687} 5688 5689static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5690{ 5691 struct e1000_hw *hw = &adapter->hw; 5692 u32 reg, i; 5693 5694 /* The vlvf table only exists on 82576 hardware and newer */ 5695 if (hw->mac.type < e1000_82576) 5696 return -1; 5697 5698 /* we only need to do this if VMDq is enabled */ 5699 if (!adapter->vfs_allocated_count) 5700 return -1; 5701 5702 /* Find the vlan filter for this id */ 5703 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5704 reg = rd32(E1000_VLVF(i)); 5705 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5706 vid == (reg & E1000_VLVF_VLANID_MASK)) 5707 break; 5708 } 5709 5710 if (add) { 5711 if (i == E1000_VLVF_ARRAY_SIZE) { 5712 /* Did not find a matching VLAN ID entry that was 5713 * enabled. Search for a free filter entry, i.e. 5714 * one without the enable bit set 5715 */ 5716 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5717 reg = rd32(E1000_VLVF(i)); 5718 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5719 break; 5720 } 5721 } 5722 if (i < E1000_VLVF_ARRAY_SIZE) { 5723 /* Found an enabled/available entry */ 5724 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5725 5726 /* if !enabled we need to set this up in vfta */ 5727 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5728 /* add VID to filter table */ 5729 igb_vfta_set(hw, vid, true); 5730 reg |= E1000_VLVF_VLANID_ENABLE; 5731 } 5732 reg &= ~E1000_VLVF_VLANID_MASK; 5733 reg |= vid; 5734 wr32(E1000_VLVF(i), reg); 5735 5736 /* do not modify RLPML for PF devices */ 5737 if (vf >= adapter->vfs_allocated_count) 5738 return 0; 5739 5740 if (!adapter->vf_data[vf].vlans_enabled) { 5741 u32 size; 5742 reg = rd32(E1000_VMOLR(vf)); 5743 size = reg & E1000_VMOLR_RLPML_MASK; 5744 size += 4; 5745 reg &= ~E1000_VMOLR_RLPML_MASK; 5746 reg |= size; 5747 wr32(E1000_VMOLR(vf), reg); 5748 } 5749 5750 adapter->vf_data[vf].vlans_enabled++; 5751 } 5752 } else { 5753 if (i < E1000_VLVF_ARRAY_SIZE) { 5754 /* remove vf from the pool */ 5755 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5756 /* if pool is empty then remove entry from vfta */ 5757 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5758 reg = 0; 5759 igb_vfta_set(hw, vid, false); 5760 } 5761 wr32(E1000_VLVF(i), reg); 5762 5763 /* do not modify RLPML for PF devices */ 5764 if (vf >= adapter->vfs_allocated_count) 5765 return 0; 5766 5767 adapter->vf_data[vf].vlans_enabled--; 5768 if (!adapter->vf_data[vf].vlans_enabled) { 5769 u32 size; 5770 reg = rd32(E1000_VMOLR(vf)); 5771 size = reg & E1000_VMOLR_RLPML_MASK; 5772 size -= 4; 5773 reg &= ~E1000_VMOLR_RLPML_MASK; 5774 reg |= size; 5775 wr32(E1000_VMOLR(vf), reg); 5776 } 5777 } 5778 } 5779 return 0; 5780} 5781 5782static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5783{ 5784 struct e1000_hw *hw = &adapter->hw; 5785 5786 if (vid) 5787 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5788 else 5789 wr32(E1000_VMVIR(vf), 0); 5790} 5791 5792static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5793 int vf, u16 vlan, u8 qos) 5794{ 5795 int err = 0; 5796 struct igb_adapter *adapter = netdev_priv(netdev); 5797 5798 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5799 return -EINVAL; 5800 if (vlan || qos) { 5801 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5802 if (err) 5803 goto out; 5804 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5805 igb_set_vmolr(adapter, vf, !vlan); 5806 adapter->vf_data[vf].pf_vlan = vlan; 5807 adapter->vf_data[vf].pf_qos = qos; 5808 dev_info(&adapter->pdev->dev, 5809 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5810 if (test_bit(__IGB_DOWN, &adapter->state)) { 5811 dev_warn(&adapter->pdev->dev, 5812 "The VF VLAN has been set, but the PF device is not up.\n"); 5813 dev_warn(&adapter->pdev->dev, 5814 "Bring the PF device up before attempting to use the VF device.\n"); 5815 } 5816 } else { 5817 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5818 false, vf); 5819 igb_set_vmvir(adapter, vlan, vf); 5820 igb_set_vmolr(adapter, vf, true); 5821 adapter->vf_data[vf].pf_vlan = 0; 5822 adapter->vf_data[vf].pf_qos = 0; 5823 } 5824out: 5825 return err; 5826} 5827 5828static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid) 5829{ 5830 struct e1000_hw *hw = &adapter->hw; 5831 int i; 5832 u32 reg; 5833 5834 /* Find the vlan filter for this id */ 5835 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5836 reg = rd32(E1000_VLVF(i)); 5837 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5838 vid == (reg & E1000_VLVF_VLANID_MASK)) 5839 break; 5840 } 5841 5842 if (i >= E1000_VLVF_ARRAY_SIZE) 5843 i = -1; 5844 5845 return i; 5846} 5847 5848static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5849{ 5850 struct e1000_hw *hw = &adapter->hw; 5851 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5852 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5853 int err = 0; 5854 5855 /* If in promiscuous mode we need to make sure the PF also has 5856 * the VLAN filter set. 5857 */ 5858 if (add && (adapter->netdev->flags & IFF_PROMISC)) 5859 err = igb_vlvf_set(adapter, vid, add, 5860 adapter->vfs_allocated_count); 5861 if (err) 5862 goto out; 5863 5864 err = igb_vlvf_set(adapter, vid, add, vf); 5865 5866 if (err) 5867 goto out; 5868 5869 /* Go through all the checks to see if the VLAN filter should 5870 * be wiped completely. 5871 */ 5872 if (!add && (adapter->netdev->flags & IFF_PROMISC)) { 5873 u32 vlvf, bits; 5874 5875 int regndx = igb_find_vlvf_entry(adapter, vid); 5876 if (regndx < 0) 5877 goto out; 5878 /* See if any other pools are set for this VLAN filter 5879 * entry other than the PF. 5880 */ 5881 vlvf = bits = rd32(E1000_VLVF(regndx)); 5882 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT + 5883 adapter->vfs_allocated_count); 5884 /* If the filter was removed then ensure PF pool bit 5885 * is cleared if the PF only added itself to the pool 5886 * because the PF is in promiscuous mode. 5887 */ 5888 if ((vlvf & VLAN_VID_MASK) == vid && 5889 !test_bit(vid, adapter->active_vlans) && 5890 !bits) 5891 igb_vlvf_set(adapter, vid, add, 5892 adapter->vfs_allocated_count); 5893 } 5894 5895out: 5896 return err; 5897} 5898 5899static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 5900{ 5901 /* clear flags - except flag that indicates PF has set the MAC */ 5902 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 5903 adapter->vf_data[vf].last_nack = jiffies; 5904 5905 /* reset offloads to defaults */ 5906 igb_set_vmolr(adapter, vf, true); 5907 5908 /* reset vlans for device */ 5909 igb_clear_vf_vfta(adapter, vf); 5910 if (adapter->vf_data[vf].pf_vlan) 5911 igb_ndo_set_vf_vlan(adapter->netdev, vf, 5912 adapter->vf_data[vf].pf_vlan, 5913 adapter->vf_data[vf].pf_qos); 5914 else 5915 igb_clear_vf_vfta(adapter, vf); 5916 5917 /* reset multicast table array for vf */ 5918 adapter->vf_data[vf].num_vf_mc_hashes = 0; 5919 5920 /* Flush and reset the mta with the new values */ 5921 igb_set_rx_mode(adapter->netdev); 5922} 5923 5924static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 5925{ 5926 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5927 5928 /* clear mac address as we were hotplug removed/added */ 5929 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 5930 eth_zero_addr(vf_mac); 5931 5932 /* process remaining reset events */ 5933 igb_vf_reset(adapter, vf); 5934} 5935 5936static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 5937{ 5938 struct e1000_hw *hw = &adapter->hw; 5939 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5940 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 5941 u32 reg, msgbuf[3]; 5942 u8 *addr = (u8 *)(&msgbuf[1]); 5943 5944 /* process all the same items cleared in a function level reset */ 5945 igb_vf_reset(adapter, vf); 5946 5947 /* set vf mac address */ 5948 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 5949 5950 /* enable transmit and receive for vf */ 5951 reg = rd32(E1000_VFTE); 5952 wr32(E1000_VFTE, reg | (1 << vf)); 5953 reg = rd32(E1000_VFRE); 5954 wr32(E1000_VFRE, reg | (1 << vf)); 5955 5956 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 5957 5958 /* reply to reset with ack and vf mac address */ 5959 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 5960 memcpy(addr, vf_mac, ETH_ALEN); 5961 igb_write_mbx(hw, msgbuf, 3, vf); 5962} 5963 5964static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 5965{ 5966 /* The VF MAC Address is stored in a packed array of bytes 5967 * starting at the second 32 bit word of the msg array 5968 */ 5969 unsigned char *addr = (char *)&msg[1]; 5970 int err = -1; 5971 5972 if (is_valid_ether_addr(addr)) 5973 err = igb_set_vf_mac(adapter, vf, addr); 5974 5975 return err; 5976} 5977 5978static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 5979{ 5980 struct e1000_hw *hw = &adapter->hw; 5981 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5982 u32 msg = E1000_VT_MSGTYPE_NACK; 5983 5984 /* if device isn't clear to send it shouldn't be reading either */ 5985 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 5986 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 5987 igb_write_mbx(hw, &msg, 1, vf); 5988 vf_data->last_nack = jiffies; 5989 } 5990} 5991 5992static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 5993{ 5994 struct pci_dev *pdev = adapter->pdev; 5995 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 5996 struct e1000_hw *hw = &adapter->hw; 5997 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5998 s32 retval; 5999 6000 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6001 6002 if (retval) { 6003 /* if receive failed revoke VF CTS stats and restart init */ 6004 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6005 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6006 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6007 return; 6008 goto out; 6009 } 6010 6011 /* this is a message we already processed, do nothing */ 6012 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6013 return; 6014 6015 /* until the vf completes a reset it should not be 6016 * allowed to start any configuration. 6017 */ 6018 if (msgbuf[0] == E1000_VF_RESET) { 6019 igb_vf_reset_msg(adapter, vf); 6020 return; 6021 } 6022 6023 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6024 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6025 return; 6026 retval = -1; 6027 goto out; 6028 } 6029 6030 switch ((msgbuf[0] & 0xFFFF)) { 6031 case E1000_VF_SET_MAC_ADDR: 6032 retval = -EINVAL; 6033 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 6034 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6035 else 6036 dev_warn(&pdev->dev, 6037 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6038 vf); 6039 break; 6040 case E1000_VF_SET_PROMISC: 6041 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6042 break; 6043 case E1000_VF_SET_MULTICAST: 6044 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6045 break; 6046 case E1000_VF_SET_LPE: 6047 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6048 break; 6049 case E1000_VF_SET_VLAN: 6050 retval = -1; 6051 if (vf_data->pf_vlan) 6052 dev_warn(&pdev->dev, 6053 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6054 vf); 6055 else 6056 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 6057 break; 6058 default: 6059 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6060 retval = -1; 6061 break; 6062 } 6063 6064 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6065out: 6066 /* notify the VF of the results of what it sent us */ 6067 if (retval) 6068 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6069 else 6070 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6071 6072 igb_write_mbx(hw, msgbuf, 1, vf); 6073} 6074 6075static void igb_msg_task(struct igb_adapter *adapter) 6076{ 6077 struct e1000_hw *hw = &adapter->hw; 6078 u32 vf; 6079 6080 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6081 /* process any reset requests */ 6082 if (!igb_check_for_rst(hw, vf)) 6083 igb_vf_reset_event(adapter, vf); 6084 6085 /* process any messages pending */ 6086 if (!igb_check_for_msg(hw, vf)) 6087 igb_rcv_msg_from_vf(adapter, vf); 6088 6089 /* process any acks */ 6090 if (!igb_check_for_ack(hw, vf)) 6091 igb_rcv_ack_from_vf(adapter, vf); 6092 } 6093} 6094 6095/** 6096 * igb_set_uta - Set unicast filter table address 6097 * @adapter: board private structure 6098 * 6099 * The unicast table address is a register array of 32-bit registers. 6100 * The table is meant to be used in a way similar to how the MTA is used 6101 * however due to certain limitations in the hardware it is necessary to 6102 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6103 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6104 **/ 6105static void igb_set_uta(struct igb_adapter *adapter) 6106{ 6107 struct e1000_hw *hw = &adapter->hw; 6108 int i; 6109 6110 /* The UTA table only exists on 82576 hardware and newer */ 6111 if (hw->mac.type < e1000_82576) 6112 return; 6113 6114 /* we only need to do this if VMDq is enabled */ 6115 if (!adapter->vfs_allocated_count) 6116 return; 6117 6118 for (i = 0; i < hw->mac.uta_reg_count; i++) 6119 array_wr32(E1000_UTA, i, ~0); 6120} 6121 6122/** 6123 * igb_intr_msi - Interrupt Handler 6124 * @irq: interrupt number 6125 * @data: pointer to a network interface device structure 6126 **/ 6127static irqreturn_t igb_intr_msi(int irq, void *data) 6128{ 6129 struct igb_adapter *adapter = data; 6130 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6131 struct e1000_hw *hw = &adapter->hw; 6132 /* read ICR disables interrupts using IAM */ 6133 u32 icr = rd32(E1000_ICR); 6134 6135 igb_write_itr(q_vector); 6136 6137 if (icr & E1000_ICR_DRSTA) 6138 schedule_work(&adapter->reset_task); 6139 6140 if (icr & E1000_ICR_DOUTSYNC) { 6141 /* HW is reporting DMA is out of sync */ 6142 adapter->stats.doosync++; 6143 } 6144 6145 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6146 hw->mac.get_link_status = 1; 6147 if (!test_bit(__IGB_DOWN, &adapter->state)) 6148 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6149 } 6150 6151 if (icr & E1000_ICR_TS) { 6152 u32 tsicr = rd32(E1000_TSICR); 6153 6154 if (tsicr & E1000_TSICR_TXTS) { 6155 /* acknowledge the interrupt */ 6156 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6157 /* retrieve hardware timestamp */ 6158 schedule_work(&adapter->ptp_tx_work); 6159 } 6160 } 6161 6162 napi_schedule(&q_vector->napi); 6163 6164 return IRQ_HANDLED; 6165} 6166 6167/** 6168 * igb_intr - Legacy Interrupt Handler 6169 * @irq: interrupt number 6170 * @data: pointer to a network interface device structure 6171 **/ 6172static irqreturn_t igb_intr(int irq, void *data) 6173{ 6174 struct igb_adapter *adapter = data; 6175 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6176 struct e1000_hw *hw = &adapter->hw; 6177 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6178 * need for the IMC write 6179 */ 6180 u32 icr = rd32(E1000_ICR); 6181 6182 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6183 * not set, then the adapter didn't send an interrupt 6184 */ 6185 if (!(icr & E1000_ICR_INT_ASSERTED)) 6186 return IRQ_NONE; 6187 6188 igb_write_itr(q_vector); 6189 6190 if (icr & E1000_ICR_DRSTA) 6191 schedule_work(&adapter->reset_task); 6192 6193 if (icr & E1000_ICR_DOUTSYNC) { 6194 /* HW is reporting DMA is out of sync */ 6195 adapter->stats.doosync++; 6196 } 6197 6198 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6199 hw->mac.get_link_status = 1; 6200 /* guard against interrupt when we're going down */ 6201 if (!test_bit(__IGB_DOWN, &adapter->state)) 6202 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6203 } 6204 6205 if (icr & E1000_ICR_TS) { 6206 u32 tsicr = rd32(E1000_TSICR); 6207 6208 if (tsicr & E1000_TSICR_TXTS) { 6209 /* acknowledge the interrupt */ 6210 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6211 /* retrieve hardware timestamp */ 6212 schedule_work(&adapter->ptp_tx_work); 6213 } 6214 } 6215 6216 napi_schedule(&q_vector->napi); 6217 6218 return IRQ_HANDLED; 6219} 6220 6221static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6222{ 6223 struct igb_adapter *adapter = q_vector->adapter; 6224 struct e1000_hw *hw = &adapter->hw; 6225 6226 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6227 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6228 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6229 igb_set_itr(q_vector); 6230 else 6231 igb_update_ring_itr(q_vector); 6232 } 6233 6234 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6235 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6236 wr32(E1000_EIMS, q_vector->eims_value); 6237 else 6238 igb_irq_enable(adapter); 6239 } 6240} 6241 6242/** 6243 * igb_poll - NAPI Rx polling callback 6244 * @napi: napi polling structure 6245 * @budget: count of how many packets we should handle 6246 **/ 6247static int igb_poll(struct napi_struct *napi, int budget) 6248{ 6249 struct igb_q_vector *q_vector = container_of(napi, 6250 struct igb_q_vector, 6251 napi); 6252 bool clean_complete = true; 6253 6254#ifdef CONFIG_IGB_DCA 6255 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6256 igb_update_dca(q_vector); 6257#endif 6258 if (q_vector->tx.ring) 6259 clean_complete = igb_clean_tx_irq(q_vector); 6260 6261 if (q_vector->rx.ring) 6262 clean_complete &= igb_clean_rx_irq(q_vector, budget); 6263 6264 /* If all work not completed, return budget and keep polling */ 6265 if (!clean_complete) 6266 return budget; 6267 6268 /* If not enough Rx work done, exit the polling mode */ 6269 napi_complete(napi); 6270 igb_ring_irq_enable(q_vector); 6271 6272 return 0; 6273} 6274 6275/** 6276 * igb_clean_tx_irq - Reclaim resources after transmit completes 6277 * @q_vector: pointer to q_vector containing needed info 6278 * 6279 * returns true if ring is completely cleaned 6280 **/ 6281static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 6282{ 6283 struct igb_adapter *adapter = q_vector->adapter; 6284 struct igb_ring *tx_ring = q_vector->tx.ring; 6285 struct igb_tx_buffer *tx_buffer; 6286 union e1000_adv_tx_desc *tx_desc; 6287 unsigned int total_bytes = 0, total_packets = 0; 6288 unsigned int budget = q_vector->tx.work_limit; 6289 unsigned int i = tx_ring->next_to_clean; 6290 6291 if (test_bit(__IGB_DOWN, &adapter->state)) 6292 return true; 6293 6294 tx_buffer = &tx_ring->tx_buffer_info[i]; 6295 tx_desc = IGB_TX_DESC(tx_ring, i); 6296 i -= tx_ring->count; 6297 6298 do { 6299 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6300 6301 /* if next_to_watch is not set then there is no work pending */ 6302 if (!eop_desc) 6303 break; 6304 6305 /* prevent any other reads prior to eop_desc */ 6306 read_barrier_depends(); 6307 6308 /* if DD is not set pending work has not been completed */ 6309 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6310 break; 6311 6312 /* clear next_to_watch to prevent false hangs */ 6313 tx_buffer->next_to_watch = NULL; 6314 6315 /* update the statistics for this packet */ 6316 total_bytes += tx_buffer->bytecount; 6317 total_packets += tx_buffer->gso_segs; 6318 6319 /* free the skb */ 6320 dev_kfree_skb_any(tx_buffer->skb); 6321 6322 /* unmap skb header data */ 6323 dma_unmap_single(tx_ring->dev, 6324 dma_unmap_addr(tx_buffer, dma), 6325 dma_unmap_len(tx_buffer, len), 6326 DMA_TO_DEVICE); 6327 6328 /* clear tx_buffer data */ 6329 tx_buffer->skb = NULL; 6330 dma_unmap_len_set(tx_buffer, len, 0); 6331 6332 /* clear last DMA location and unmap remaining buffers */ 6333 while (tx_desc != eop_desc) { 6334 tx_buffer++; 6335 tx_desc++; 6336 i++; 6337 if (unlikely(!i)) { 6338 i -= tx_ring->count; 6339 tx_buffer = tx_ring->tx_buffer_info; 6340 tx_desc = IGB_TX_DESC(tx_ring, 0); 6341 } 6342 6343 /* unmap any remaining paged data */ 6344 if (dma_unmap_len(tx_buffer, len)) { 6345 dma_unmap_page(tx_ring->dev, 6346 dma_unmap_addr(tx_buffer, dma), 6347 dma_unmap_len(tx_buffer, len), 6348 DMA_TO_DEVICE); 6349 dma_unmap_len_set(tx_buffer, len, 0); 6350 } 6351 } 6352 6353 /* move us one more past the eop_desc for start of next pkt */ 6354 tx_buffer++; 6355 tx_desc++; 6356 i++; 6357 if (unlikely(!i)) { 6358 i -= tx_ring->count; 6359 tx_buffer = tx_ring->tx_buffer_info; 6360 tx_desc = IGB_TX_DESC(tx_ring, 0); 6361 } 6362 6363 /* issue prefetch for next Tx descriptor */ 6364 prefetch(tx_desc); 6365 6366 /* update budget accounting */ 6367 budget--; 6368 } while (likely(budget)); 6369 6370 netdev_tx_completed_queue(txring_txq(tx_ring), 6371 total_packets, total_bytes); 6372 i += tx_ring->count; 6373 tx_ring->next_to_clean = i; 6374 u64_stats_update_begin(&tx_ring->tx_syncp); 6375 tx_ring->tx_stats.bytes += total_bytes; 6376 tx_ring->tx_stats.packets += total_packets; 6377 u64_stats_update_end(&tx_ring->tx_syncp); 6378 q_vector->tx.total_bytes += total_bytes; 6379 q_vector->tx.total_packets += total_packets; 6380 6381 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6382 struct e1000_hw *hw = &adapter->hw; 6383 6384 /* Detect a transmit hang in hardware, this serializes the 6385 * check with the clearing of time_stamp and movement of i 6386 */ 6387 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6388 if (tx_buffer->next_to_watch && 6389 time_after(jiffies, tx_buffer->time_stamp + 6390 (adapter->tx_timeout_factor * HZ)) && 6391 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6392 6393 /* detected Tx unit hang */ 6394 dev_err(tx_ring->dev, 6395 "Detected Tx Unit Hang\n" 6396 " Tx Queue <%d>\n" 6397 " TDH <%x>\n" 6398 " TDT <%x>\n" 6399 " next_to_use <%x>\n" 6400 " next_to_clean <%x>\n" 6401 "buffer_info[next_to_clean]\n" 6402 " time_stamp <%lx>\n" 6403 " next_to_watch <%p>\n" 6404 " jiffies <%lx>\n" 6405 " desc.status <%x>\n", 6406 tx_ring->queue_index, 6407 rd32(E1000_TDH(tx_ring->reg_idx)), 6408 readl(tx_ring->tail), 6409 tx_ring->next_to_use, 6410 tx_ring->next_to_clean, 6411 tx_buffer->time_stamp, 6412 tx_buffer->next_to_watch, 6413 jiffies, 6414 tx_buffer->next_to_watch->wb.status); 6415 netif_stop_subqueue(tx_ring->netdev, 6416 tx_ring->queue_index); 6417 6418 /* we are about to reset, no point in enabling stuff */ 6419 return true; 6420 } 6421 } 6422 6423#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6424 if (unlikely(total_packets && 6425 netif_carrier_ok(tx_ring->netdev) && 6426 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6427 /* Make sure that anybody stopping the queue after this 6428 * sees the new next_to_clean. 6429 */ 6430 smp_mb(); 6431 if (__netif_subqueue_stopped(tx_ring->netdev, 6432 tx_ring->queue_index) && 6433 !(test_bit(__IGB_DOWN, &adapter->state))) { 6434 netif_wake_subqueue(tx_ring->netdev, 6435 tx_ring->queue_index); 6436 6437 u64_stats_update_begin(&tx_ring->tx_syncp); 6438 tx_ring->tx_stats.restart_queue++; 6439 u64_stats_update_end(&tx_ring->tx_syncp); 6440 } 6441 } 6442 6443 return !!budget; 6444} 6445 6446/** 6447 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6448 * @rx_ring: rx descriptor ring to store buffers on 6449 * @old_buff: donor buffer to have page reused 6450 * 6451 * Synchronizes page for reuse by the adapter 6452 **/ 6453static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6454 struct igb_rx_buffer *old_buff) 6455{ 6456 struct igb_rx_buffer *new_buff; 6457 u16 nta = rx_ring->next_to_alloc; 6458 6459 new_buff = &rx_ring->rx_buffer_info[nta]; 6460 6461 /* update, and store next to alloc */ 6462 nta++; 6463 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6464 6465 /* transfer page from old buffer to new buffer */ 6466 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); 6467 6468 /* sync the buffer for use by the device */ 6469 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 6470 old_buff->page_offset, 6471 IGB_RX_BUFSZ, 6472 DMA_FROM_DEVICE); 6473} 6474 6475static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 6476 struct page *page, 6477 unsigned int truesize) 6478{ 6479 /* avoid re-using remote pages */ 6480 if (unlikely(page_to_nid(page) != numa_node_id())) 6481 return false; 6482 6483#if (PAGE_SIZE < 8192) 6484 /* if we are only owner of page we can reuse it */ 6485 if (unlikely(page_count(page) != 1)) 6486 return false; 6487 6488 /* flip page offset to other buffer */ 6489 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 6490 6491 /* since we are the only owner of the page and we need to 6492 * increment it, just set the value to 2 in order to avoid 6493 * an unnecessary locked operation 6494 */ 6495 atomic_set(&page->_count, 2); 6496#else 6497 /* move offset up to the next cache line */ 6498 rx_buffer->page_offset += truesize; 6499 6500 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 6501 return false; 6502 6503 /* bump ref count on page before it is given to the stack */ 6504 get_page(page); 6505#endif 6506 6507 return true; 6508} 6509 6510/** 6511 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6512 * @rx_ring: rx descriptor ring to transact packets on 6513 * @rx_buffer: buffer containing page to add 6514 * @rx_desc: descriptor containing length of buffer written by hardware 6515 * @skb: sk_buff to place the data into 6516 * 6517 * This function will add the data contained in rx_buffer->page to the skb. 6518 * This is done either through a direct copy if the data in the buffer is 6519 * less than the skb header size, otherwise it will just attach the page as 6520 * a frag to the skb. 6521 * 6522 * The function will then update the page offset if necessary and return 6523 * true if the buffer can be reused by the adapter. 6524 **/ 6525static bool igb_add_rx_frag(struct igb_ring *rx_ring, 6526 struct igb_rx_buffer *rx_buffer, 6527 union e1000_adv_rx_desc *rx_desc, 6528 struct sk_buff *skb) 6529{ 6530 struct page *page = rx_buffer->page; 6531 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 6532#if (PAGE_SIZE < 8192) 6533 unsigned int truesize = IGB_RX_BUFSZ; 6534#else 6535 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 6536#endif 6537 6538 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { 6539 unsigned char *va = page_address(page) + rx_buffer->page_offset; 6540 6541 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6542 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6543 va += IGB_TS_HDR_LEN; 6544 size -= IGB_TS_HDR_LEN; 6545 } 6546 6547 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 6548 6549 /* we can reuse buffer as-is, just make sure it is local */ 6550 if (likely(page_to_nid(page) == numa_node_id())) 6551 return true; 6552 6553 /* this page cannot be reused so discard it */ 6554 put_page(page); 6555 return false; 6556 } 6557 6558 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 6559 rx_buffer->page_offset, size, truesize); 6560 6561 return igb_can_reuse_rx_page(rx_buffer, page, truesize); 6562} 6563 6564static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 6565 union e1000_adv_rx_desc *rx_desc, 6566 struct sk_buff *skb) 6567{ 6568 struct igb_rx_buffer *rx_buffer; 6569 struct page *page; 6570 6571 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 6572 6573 page = rx_buffer->page; 6574 prefetchw(page); 6575 6576 if (likely(!skb)) { 6577 void *page_addr = page_address(page) + 6578 rx_buffer->page_offset; 6579 6580 /* prefetch first cache line of first page */ 6581 prefetch(page_addr); 6582#if L1_CACHE_BYTES < 128 6583 prefetch(page_addr + L1_CACHE_BYTES); 6584#endif 6585 6586 /* allocate a skb to store the frags */ 6587 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 6588 IGB_RX_HDR_LEN); 6589 if (unlikely(!skb)) { 6590 rx_ring->rx_stats.alloc_failed++; 6591 return NULL; 6592 } 6593 6594 /* we will be copying header into skb->data in 6595 * pskb_may_pull so it is in our interest to prefetch 6596 * it now to avoid a possible cache miss 6597 */ 6598 prefetchw(skb->data); 6599 } 6600 6601 /* we are reusing so sync this buffer for CPU use */ 6602 dma_sync_single_range_for_cpu(rx_ring->dev, 6603 rx_buffer->dma, 6604 rx_buffer->page_offset, 6605 IGB_RX_BUFSZ, 6606 DMA_FROM_DEVICE); 6607 6608 /* pull page into skb */ 6609 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 6610 /* hand second half of page back to the ring */ 6611 igb_reuse_rx_page(rx_ring, rx_buffer); 6612 } else { 6613 /* we are not reusing the buffer so unmap it */ 6614 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6615 PAGE_SIZE, DMA_FROM_DEVICE); 6616 } 6617 6618 /* clear contents of rx_buffer */ 6619 rx_buffer->page = NULL; 6620 6621 return skb; 6622} 6623 6624static inline void igb_rx_checksum(struct igb_ring *ring, 6625 union e1000_adv_rx_desc *rx_desc, 6626 struct sk_buff *skb) 6627{ 6628 skb_checksum_none_assert(skb); 6629 6630 /* Ignore Checksum bit is set */ 6631 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6632 return; 6633 6634 /* Rx checksum disabled via ethtool */ 6635 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6636 return; 6637 6638 /* TCP/UDP checksum error bit is set */ 6639 if (igb_test_staterr(rx_desc, 6640 E1000_RXDEXT_STATERR_TCPE | 6641 E1000_RXDEXT_STATERR_IPE)) { 6642 /* work around errata with sctp packets where the TCPE aka 6643 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6644 * packets, (aka let the stack check the crc32c) 6645 */ 6646 if (!((skb->len == 60) && 6647 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6648 u64_stats_update_begin(&ring->rx_syncp); 6649 ring->rx_stats.csum_err++; 6650 u64_stats_update_end(&ring->rx_syncp); 6651 } 6652 /* let the stack verify checksum errors */ 6653 return; 6654 } 6655 /* It must be a TCP or UDP packet with a valid checksum */ 6656 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 6657 E1000_RXD_STAT_UDPCS)) 6658 skb->ip_summed = CHECKSUM_UNNECESSARY; 6659 6660 dev_dbg(ring->dev, "cksum success: bits %08X\n", 6661 le32_to_cpu(rx_desc->wb.upper.status_error)); 6662} 6663 6664static inline void igb_rx_hash(struct igb_ring *ring, 6665 union e1000_adv_rx_desc *rx_desc, 6666 struct sk_buff *skb) 6667{ 6668 if (ring->netdev->features & NETIF_F_RXHASH) 6669 skb_set_hash(skb, 6670 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 6671 PKT_HASH_TYPE_L3); 6672} 6673 6674/** 6675 * igb_is_non_eop - process handling of non-EOP buffers 6676 * @rx_ring: Rx ring being processed 6677 * @rx_desc: Rx descriptor for current buffer 6678 * @skb: current socket buffer containing buffer in progress 6679 * 6680 * This function updates next to clean. If the buffer is an EOP buffer 6681 * this function exits returning false, otherwise it will place the 6682 * sk_buff in the next buffer to be chained and return true indicating 6683 * that this is in fact a non-EOP buffer. 6684 **/ 6685static bool igb_is_non_eop(struct igb_ring *rx_ring, 6686 union e1000_adv_rx_desc *rx_desc) 6687{ 6688 u32 ntc = rx_ring->next_to_clean + 1; 6689 6690 /* fetch, update, and store next to clean */ 6691 ntc = (ntc < rx_ring->count) ? ntc : 0; 6692 rx_ring->next_to_clean = ntc; 6693 6694 prefetch(IGB_RX_DESC(rx_ring, ntc)); 6695 6696 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 6697 return false; 6698 6699 return true; 6700} 6701 6702/** 6703 * igb_get_headlen - determine size of header for LRO/GRO 6704 * @data: pointer to the start of the headers 6705 * @max_len: total length of section to find headers in 6706 * 6707 * This function is meant to determine the length of headers that will 6708 * be recognized by hardware for LRO, and GRO offloads. The main 6709 * motivation of doing this is to only perform one pull for IPv4 TCP 6710 * packets so that we can do basic things like calculating the gso_size 6711 * based on the average data per packet. 6712 **/ 6713static unsigned int igb_get_headlen(unsigned char *data, 6714 unsigned int max_len) 6715{ 6716 union { 6717 unsigned char *network; 6718 /* l2 headers */ 6719 struct ethhdr *eth; 6720 struct vlan_hdr *vlan; 6721 /* l3 headers */ 6722 struct iphdr *ipv4; 6723 struct ipv6hdr *ipv6; 6724 } hdr; 6725 __be16 protocol; 6726 u8 nexthdr = 0; /* default to not TCP */ 6727 u8 hlen; 6728 6729 /* this should never happen, but better safe than sorry */ 6730 if (max_len < ETH_HLEN) 6731 return max_len; 6732 6733 /* initialize network frame pointer */ 6734 hdr.network = data; 6735 6736 /* set first protocol and move network header forward */ 6737 protocol = hdr.eth->h_proto; 6738 hdr.network += ETH_HLEN; 6739 6740 /* handle any vlan tag if present */ 6741 if (protocol == htons(ETH_P_8021Q)) { 6742 if ((hdr.network - data) > (max_len - VLAN_HLEN)) 6743 return max_len; 6744 6745 protocol = hdr.vlan->h_vlan_encapsulated_proto; 6746 hdr.network += VLAN_HLEN; 6747 } 6748 6749 /* handle L3 protocols */ 6750 if (protocol == htons(ETH_P_IP)) { 6751 if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) 6752 return max_len; 6753 6754 /* access ihl as a u8 to avoid unaligned access on ia64 */ 6755 hlen = (hdr.network[0] & 0x0F) << 2; 6756 6757 /* verify hlen meets minimum size requirements */ 6758 if (hlen < sizeof(struct iphdr)) 6759 return hdr.network - data; 6760 6761 /* record next protocol if header is present */ 6762 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET))) 6763 nexthdr = hdr.ipv4->protocol; 6764 } else if (protocol == htons(ETH_P_IPV6)) { 6765 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) 6766 return max_len; 6767 6768 /* record next protocol */ 6769 nexthdr = hdr.ipv6->nexthdr; 6770 hlen = sizeof(struct ipv6hdr); 6771 } else { 6772 return hdr.network - data; 6773 } 6774 6775 /* relocate pointer to start of L4 header */ 6776 hdr.network += hlen; 6777 6778 /* finally sort out TCP */ 6779 if (nexthdr == IPPROTO_TCP) { 6780 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) 6781 return max_len; 6782 6783 /* access doff as a u8 to avoid unaligned access on ia64 */ 6784 hlen = (hdr.network[12] & 0xF0) >> 2; 6785 6786 /* verify hlen meets minimum size requirements */ 6787 if (hlen < sizeof(struct tcphdr)) 6788 return hdr.network - data; 6789 6790 hdr.network += hlen; 6791 } else if (nexthdr == IPPROTO_UDP) { 6792 if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) 6793 return max_len; 6794 6795 hdr.network += sizeof(struct udphdr); 6796 } 6797 6798 /* If everything has gone correctly hdr.network should be the 6799 * data section of the packet and will be the end of the header. 6800 * If not then it probably represents the end of the last recognized 6801 * header. 6802 */ 6803 if ((hdr.network - data) < max_len) 6804 return hdr.network - data; 6805 else 6806 return max_len; 6807} 6808 6809/** 6810 * igb_pull_tail - igb specific version of skb_pull_tail 6811 * @rx_ring: rx descriptor ring packet is being transacted on 6812 * @rx_desc: pointer to the EOP Rx descriptor 6813 * @skb: pointer to current skb being adjusted 6814 * 6815 * This function is an igb specific version of __pskb_pull_tail. The 6816 * main difference between this version and the original function is that 6817 * this function can make several assumptions about the state of things 6818 * that allow for significant optimizations versus the standard function. 6819 * As a result we can do things like drop a frag and maintain an accurate 6820 * truesize for the skb. 6821 */ 6822static void igb_pull_tail(struct igb_ring *rx_ring, 6823 union e1000_adv_rx_desc *rx_desc, 6824 struct sk_buff *skb) 6825{ 6826 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6827 unsigned char *va; 6828 unsigned int pull_len; 6829 6830 /* it is valid to use page_address instead of kmap since we are 6831 * working with pages allocated out of the lomem pool per 6832 * alloc_page(GFP_ATOMIC) 6833 */ 6834 va = skb_frag_address(frag); 6835 6836 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6837 /* retrieve timestamp from buffer */ 6838 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6839 6840 /* update pointers to remove timestamp header */ 6841 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); 6842 frag->page_offset += IGB_TS_HDR_LEN; 6843 skb->data_len -= IGB_TS_HDR_LEN; 6844 skb->len -= IGB_TS_HDR_LEN; 6845 6846 /* move va to start of packet data */ 6847 va += IGB_TS_HDR_LEN; 6848 } 6849 6850 /* we need the header to contain the greater of either ETH_HLEN or 6851 * 60 bytes if the skb->len is less than 60 for skb_pad. 6852 */ 6853 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); 6854 6855 /* align pull length to size of long to optimize memcpy performance */ 6856 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 6857 6858 /* update all of the pointers */ 6859 skb_frag_size_sub(frag, pull_len); 6860 frag->page_offset += pull_len; 6861 skb->data_len -= pull_len; 6862 skb->tail += pull_len; 6863} 6864 6865/** 6866 * igb_cleanup_headers - Correct corrupted or empty headers 6867 * @rx_ring: rx descriptor ring packet is being transacted on 6868 * @rx_desc: pointer to the EOP Rx descriptor 6869 * @skb: pointer to current skb being fixed 6870 * 6871 * Address the case where we are pulling data in on pages only 6872 * and as such no data is present in the skb header. 6873 * 6874 * In addition if skb is not at least 60 bytes we need to pad it so that 6875 * it is large enough to qualify as a valid Ethernet frame. 6876 * 6877 * Returns true if an error was encountered and skb was freed. 6878 **/ 6879static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6880 union e1000_adv_rx_desc *rx_desc, 6881 struct sk_buff *skb) 6882{ 6883 if (unlikely((igb_test_staterr(rx_desc, 6884 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6885 struct net_device *netdev = rx_ring->netdev; 6886 if (!(netdev->features & NETIF_F_RXALL)) { 6887 dev_kfree_skb_any(skb); 6888 return true; 6889 } 6890 } 6891 6892 /* place header in linear portion of buffer */ 6893 if (skb_is_nonlinear(skb)) 6894 igb_pull_tail(rx_ring, rx_desc, skb); 6895 6896 /* if skb_pad returns an error the skb was freed */ 6897 if (unlikely(skb->len < 60)) { 6898 int pad_len = 60 - skb->len; 6899 6900 if (skb_pad(skb, pad_len)) 6901 return true; 6902 __skb_put(skb, pad_len); 6903 } 6904 6905 return false; 6906} 6907 6908/** 6909 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6910 * @rx_ring: rx descriptor ring packet is being transacted on 6911 * @rx_desc: pointer to the EOP Rx descriptor 6912 * @skb: pointer to current skb being populated 6913 * 6914 * This function checks the ring, descriptor, and packet information in 6915 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6916 * other fields within the skb. 6917 **/ 6918static void igb_process_skb_fields(struct igb_ring *rx_ring, 6919 union e1000_adv_rx_desc *rx_desc, 6920 struct sk_buff *skb) 6921{ 6922 struct net_device *dev = rx_ring->netdev; 6923 6924 igb_rx_hash(rx_ring, rx_desc, skb); 6925 6926 igb_rx_checksum(rx_ring, rx_desc, skb); 6927 6928 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 6929 6930 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 6931 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6932 u16 vid; 6933 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6934 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6935 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6936 else 6937 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6938 6939 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 6940 } 6941 6942 skb_record_rx_queue(skb, rx_ring->queue_index); 6943 6944 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6945} 6946 6947static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 6948{ 6949 struct igb_ring *rx_ring = q_vector->rx.ring; 6950 struct sk_buff *skb = rx_ring->skb; 6951 unsigned int total_bytes = 0, total_packets = 0; 6952 u16 cleaned_count = igb_desc_unused(rx_ring); 6953 6954 while (likely(total_packets < budget)) { 6955 union e1000_adv_rx_desc *rx_desc; 6956 6957 /* return some buffers to hardware, one at a time is too slow */ 6958 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6959 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6960 cleaned_count = 0; 6961 } 6962 6963 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 6964 6965 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) 6966 break; 6967 6968 /* This memory barrier is needed to keep us from reading 6969 * any other fields out of the rx_desc until we know the 6970 * RXD_STAT_DD bit is set 6971 */ 6972 rmb(); 6973 6974 /* retrieve a buffer from the ring */ 6975 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 6976 6977 /* exit if we failed to retrieve a buffer */ 6978 if (!skb) 6979 break; 6980 6981 cleaned_count++; 6982 6983 /* fetch next buffer in frame if non-eop */ 6984 if (igb_is_non_eop(rx_ring, rx_desc)) 6985 continue; 6986 6987 /* verify the packet layout is correct */ 6988 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 6989 skb = NULL; 6990 continue; 6991 } 6992 6993 /* probably a little skewed due to removing CRC */ 6994 total_bytes += skb->len; 6995 6996 /* populate checksum, timestamp, VLAN, and protocol */ 6997 igb_process_skb_fields(rx_ring, rx_desc, skb); 6998 6999 napi_gro_receive(&q_vector->napi, skb); 7000 7001 /* reset skb pointer */ 7002 skb = NULL; 7003 7004 /* update budget accounting */ 7005 total_packets++; 7006 } 7007 7008 /* place incomplete frames back on ring for completion */ 7009 rx_ring->skb = skb; 7010 7011 u64_stats_update_begin(&rx_ring->rx_syncp); 7012 rx_ring->rx_stats.packets += total_packets; 7013 rx_ring->rx_stats.bytes += total_bytes; 7014 u64_stats_update_end(&rx_ring->rx_syncp); 7015 q_vector->rx.total_packets += total_packets; 7016 q_vector->rx.total_bytes += total_bytes; 7017 7018 if (cleaned_count) 7019 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7020 7021 return (total_packets < budget); 7022} 7023 7024static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7025 struct igb_rx_buffer *bi) 7026{ 7027 struct page *page = bi->page; 7028 dma_addr_t dma; 7029 7030 /* since we are recycling buffers we should seldom need to alloc */ 7031 if (likely(page)) 7032 return true; 7033 7034 /* alloc new page for storage */ 7035 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); 7036 if (unlikely(!page)) { 7037 rx_ring->rx_stats.alloc_failed++; 7038 return false; 7039 } 7040 7041 /* map page for use */ 7042 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 7043 7044 /* if mapping failed free memory back to system since 7045 * there isn't much point in holding memory we can't use 7046 */ 7047 if (dma_mapping_error(rx_ring->dev, dma)) { 7048 __free_page(page); 7049 7050 rx_ring->rx_stats.alloc_failed++; 7051 return false; 7052 } 7053 7054 bi->dma = dma; 7055 bi->page = page; 7056 bi->page_offset = 0; 7057 7058 return true; 7059} 7060 7061/** 7062 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7063 * @adapter: address of board private structure 7064 **/ 7065void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7066{ 7067 union e1000_adv_rx_desc *rx_desc; 7068 struct igb_rx_buffer *bi; 7069 u16 i = rx_ring->next_to_use; 7070 7071 /* nothing to do */ 7072 if (!cleaned_count) 7073 return; 7074 7075 rx_desc = IGB_RX_DESC(rx_ring, i); 7076 bi = &rx_ring->rx_buffer_info[i]; 7077 i -= rx_ring->count; 7078 7079 do { 7080 if (!igb_alloc_mapped_page(rx_ring, bi)) 7081 break; 7082 7083 /* Refresh the desc even if buffer_addrs didn't change 7084 * because each write-back erases this info. 7085 */ 7086 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7087 7088 rx_desc++; 7089 bi++; 7090 i++; 7091 if (unlikely(!i)) { 7092 rx_desc = IGB_RX_DESC(rx_ring, 0); 7093 bi = rx_ring->rx_buffer_info; 7094 i -= rx_ring->count; 7095 } 7096 7097 /* clear the hdr_addr for the next_to_use descriptor */ 7098 rx_desc->read.hdr_addr = 0; 7099 7100 cleaned_count--; 7101 } while (cleaned_count); 7102 7103 i += rx_ring->count; 7104 7105 if (rx_ring->next_to_use != i) { 7106 /* record the next descriptor to use */ 7107 rx_ring->next_to_use = i; 7108 7109 /* update next to alloc since we have filled the ring */ 7110 rx_ring->next_to_alloc = i; 7111 7112 /* Force memory writes to complete before letting h/w 7113 * know there are new descriptors to fetch. (Only 7114 * applicable for weak-ordered memory model archs, 7115 * such as IA-64). 7116 */ 7117 wmb(); 7118 writel(i, rx_ring->tail); 7119 } 7120} 7121 7122/** 7123 * igb_mii_ioctl - 7124 * @netdev: 7125 * @ifreq: 7126 * @cmd: 7127 **/ 7128static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7129{ 7130 struct igb_adapter *adapter = netdev_priv(netdev); 7131 struct mii_ioctl_data *data = if_mii(ifr); 7132 7133 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7134 return -EOPNOTSUPP; 7135 7136 switch (cmd) { 7137 case SIOCGMIIPHY: 7138 data->phy_id = adapter->hw.phy.addr; 7139 break; 7140 case SIOCGMIIREG: 7141 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7142 &data->val_out)) 7143 return -EIO; 7144 break; 7145 case SIOCSMIIREG: 7146 default: 7147 return -EOPNOTSUPP; 7148 } 7149 return 0; 7150} 7151 7152/** 7153 * igb_ioctl - 7154 * @netdev: 7155 * @ifreq: 7156 * @cmd: 7157 **/ 7158static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7159{ 7160 switch (cmd) { 7161 case SIOCGMIIPHY: 7162 case SIOCGMIIREG: 7163 case SIOCSMIIREG: 7164 return igb_mii_ioctl(netdev, ifr, cmd); 7165 case SIOCGHWTSTAMP: 7166 return igb_ptp_get_ts_config(netdev, ifr); 7167 case SIOCSHWTSTAMP: 7168 return igb_ptp_set_ts_config(netdev, ifr); 7169 default: 7170 return -EOPNOTSUPP; 7171 } 7172} 7173 7174s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7175{ 7176 struct igb_adapter *adapter = hw->back; 7177 7178 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7179 return -E1000_ERR_CONFIG; 7180 7181 return 0; 7182} 7183 7184s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7185{ 7186 struct igb_adapter *adapter = hw->back; 7187 7188 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7189 return -E1000_ERR_CONFIG; 7190 7191 return 0; 7192} 7193 7194static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7195{ 7196 struct igb_adapter *adapter = netdev_priv(netdev); 7197 struct e1000_hw *hw = &adapter->hw; 7198 u32 ctrl, rctl; 7199 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7200 7201 if (enable) { 7202 /* enable VLAN tag insert/strip */ 7203 ctrl = rd32(E1000_CTRL); 7204 ctrl |= E1000_CTRL_VME; 7205 wr32(E1000_CTRL, ctrl); 7206 7207 /* Disable CFI check */ 7208 rctl = rd32(E1000_RCTL); 7209 rctl &= ~E1000_RCTL_CFIEN; 7210 wr32(E1000_RCTL, rctl); 7211 } else { 7212 /* disable VLAN tag insert/strip */ 7213 ctrl = rd32(E1000_CTRL); 7214 ctrl &= ~E1000_CTRL_VME; 7215 wr32(E1000_CTRL, ctrl); 7216 } 7217 7218 igb_rlpml_set(adapter); 7219} 7220 7221static int igb_vlan_rx_add_vid(struct net_device *netdev, 7222 __be16 proto, u16 vid) 7223{ 7224 struct igb_adapter *adapter = netdev_priv(netdev); 7225 struct e1000_hw *hw = &adapter->hw; 7226 int pf_id = adapter->vfs_allocated_count; 7227 7228 /* attempt to add filter to vlvf array */ 7229 igb_vlvf_set(adapter, vid, true, pf_id); 7230 7231 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7232 igb_vfta_set(hw, vid, true); 7233 7234 set_bit(vid, adapter->active_vlans); 7235 7236 return 0; 7237} 7238 7239static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7240 __be16 proto, u16 vid) 7241{ 7242 struct igb_adapter *adapter = netdev_priv(netdev); 7243 struct e1000_hw *hw = &adapter->hw; 7244 int pf_id = adapter->vfs_allocated_count; 7245 s32 err; 7246 7247 /* remove vlan from VLVF table array */ 7248 err = igb_vlvf_set(adapter, vid, false, pf_id); 7249 7250 /* if vid was not present in VLVF just remove it from table */ 7251 if (err) 7252 igb_vfta_set(hw, vid, false); 7253 7254 clear_bit(vid, adapter->active_vlans); 7255 7256 return 0; 7257} 7258 7259static void igb_restore_vlan(struct igb_adapter *adapter) 7260{ 7261 u16 vid; 7262 7263 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7264 7265 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 7266 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7267} 7268 7269int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7270{ 7271 struct pci_dev *pdev = adapter->pdev; 7272 struct e1000_mac_info *mac = &adapter->hw.mac; 7273 7274 mac->autoneg = 0; 7275 7276 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7277 * for the switch() below to work 7278 */ 7279 if ((spd & 1) || (dplx & ~1)) 7280 goto err_inval; 7281 7282 /* Fiber NIC's only allow 1000 gbps Full duplex 7283 * and 100Mbps Full duplex for 100baseFx sfp 7284 */ 7285 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7286 switch (spd + dplx) { 7287 case SPEED_10 + DUPLEX_HALF: 7288 case SPEED_10 + DUPLEX_FULL: 7289 case SPEED_100 + DUPLEX_HALF: 7290 goto err_inval; 7291 default: 7292 break; 7293 } 7294 } 7295 7296 switch (spd + dplx) { 7297 case SPEED_10 + DUPLEX_HALF: 7298 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7299 break; 7300 case SPEED_10 + DUPLEX_FULL: 7301 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7302 break; 7303 case SPEED_100 + DUPLEX_HALF: 7304 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7305 break; 7306 case SPEED_100 + DUPLEX_FULL: 7307 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7308 break; 7309 case SPEED_1000 + DUPLEX_FULL: 7310 mac->autoneg = 1; 7311 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7312 break; 7313 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7314 default: 7315 goto err_inval; 7316 } 7317 7318 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7319 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7320 7321 return 0; 7322 7323err_inval: 7324 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7325 return -EINVAL; 7326} 7327 7328static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7329 bool runtime) 7330{ 7331 struct net_device *netdev = pci_get_drvdata(pdev); 7332 struct igb_adapter *adapter = netdev_priv(netdev); 7333 struct e1000_hw *hw = &adapter->hw; 7334 u32 ctrl, rctl, status; 7335 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7336#ifdef CONFIG_PM 7337 int retval = 0; 7338#endif 7339 7340 netif_device_detach(netdev); 7341 7342 if (netif_running(netdev)) 7343 __igb_close(netdev, true); 7344 7345 igb_clear_interrupt_scheme(adapter); 7346 7347#ifdef CONFIG_PM 7348 retval = pci_save_state(pdev); 7349 if (retval) 7350 return retval; 7351#endif 7352 7353 status = rd32(E1000_STATUS); 7354 if (status & E1000_STATUS_LU) 7355 wufc &= ~E1000_WUFC_LNKC; 7356 7357 if (wufc) { 7358 igb_setup_rctl(adapter); 7359 igb_set_rx_mode(netdev); 7360 7361 /* turn on all-multi mode if wake on multicast is enabled */ 7362 if (wufc & E1000_WUFC_MC) { 7363 rctl = rd32(E1000_RCTL); 7364 rctl |= E1000_RCTL_MPE; 7365 wr32(E1000_RCTL, rctl); 7366 } 7367 7368 ctrl = rd32(E1000_CTRL); 7369 /* advertise wake from D3Cold */ 7370 #define E1000_CTRL_ADVD3WUC 0x00100000 7371 /* phy power management enable */ 7372 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7373 ctrl |= E1000_CTRL_ADVD3WUC; 7374 wr32(E1000_CTRL, ctrl); 7375 7376 /* Allow time for pending master requests to run */ 7377 igb_disable_pcie_master(hw); 7378 7379 wr32(E1000_WUC, E1000_WUC_PME_EN); 7380 wr32(E1000_WUFC, wufc); 7381 } else { 7382 wr32(E1000_WUC, 0); 7383 wr32(E1000_WUFC, 0); 7384 } 7385 7386 *enable_wake = wufc || adapter->en_mng_pt; 7387 if (!*enable_wake) 7388 igb_power_down_link(adapter); 7389 else 7390 igb_power_up_link(adapter); 7391 7392 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7393 * would have already happened in close and is redundant. 7394 */ 7395 igb_release_hw_control(adapter); 7396 7397 pci_disable_device(pdev); 7398 7399 return 0; 7400} 7401 7402#ifdef CONFIG_PM 7403#ifdef CONFIG_PM_SLEEP 7404static int igb_suspend(struct device *dev) 7405{ 7406 int retval; 7407 bool wake; 7408 struct pci_dev *pdev = to_pci_dev(dev); 7409 7410 retval = __igb_shutdown(pdev, &wake, 0); 7411 if (retval) 7412 return retval; 7413 7414 if (wake) { 7415 pci_prepare_to_sleep(pdev); 7416 } else { 7417 pci_wake_from_d3(pdev, false); 7418 pci_set_power_state(pdev, PCI_D3hot); 7419 } 7420 7421 return 0; 7422} 7423#endif /* CONFIG_PM_SLEEP */ 7424 7425static int igb_resume(struct device *dev) 7426{ 7427 struct pci_dev *pdev = to_pci_dev(dev); 7428 struct net_device *netdev = pci_get_drvdata(pdev); 7429 struct igb_adapter *adapter = netdev_priv(netdev); 7430 struct e1000_hw *hw = &adapter->hw; 7431 u32 err; 7432 7433 pci_set_power_state(pdev, PCI_D0); 7434 pci_restore_state(pdev); 7435 pci_save_state(pdev); 7436 7437 err = pci_enable_device_mem(pdev); 7438 if (err) { 7439 dev_err(&pdev->dev, 7440 "igb: Cannot enable PCI device from suspend\n"); 7441 return err; 7442 } 7443 pci_set_master(pdev); 7444 7445 pci_enable_wake(pdev, PCI_D3hot, 0); 7446 pci_enable_wake(pdev, PCI_D3cold, 0); 7447 7448 if (igb_init_interrupt_scheme(adapter, true)) { 7449 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7450 return -ENOMEM; 7451 } 7452 7453 igb_reset(adapter); 7454 7455 /* let the f/w know that the h/w is now under the control of the 7456 * driver. 7457 */ 7458 igb_get_hw_control(adapter); 7459 7460 wr32(E1000_WUS, ~0); 7461 7462 if (netdev->flags & IFF_UP) { 7463 rtnl_lock(); 7464 err = __igb_open(netdev, true); 7465 rtnl_unlock(); 7466 if (err) 7467 return err; 7468 } 7469 7470 netif_device_attach(netdev); 7471 return 0; 7472} 7473 7474#ifdef CONFIG_PM_RUNTIME 7475static int igb_runtime_idle(struct device *dev) 7476{ 7477 struct pci_dev *pdev = to_pci_dev(dev); 7478 struct net_device *netdev = pci_get_drvdata(pdev); 7479 struct igb_adapter *adapter = netdev_priv(netdev); 7480 7481 if (!igb_has_link(adapter)) 7482 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7483 7484 return -EBUSY; 7485} 7486 7487static int igb_runtime_suspend(struct device *dev) 7488{ 7489 struct pci_dev *pdev = to_pci_dev(dev); 7490 int retval; 7491 bool wake; 7492 7493 retval = __igb_shutdown(pdev, &wake, 1); 7494 if (retval) 7495 return retval; 7496 7497 if (wake) { 7498 pci_prepare_to_sleep(pdev); 7499 } else { 7500 pci_wake_from_d3(pdev, false); 7501 pci_set_power_state(pdev, PCI_D3hot); 7502 } 7503 7504 return 0; 7505} 7506 7507static int igb_runtime_resume(struct device *dev) 7508{ 7509 return igb_resume(dev); 7510} 7511#endif /* CONFIG_PM_RUNTIME */ 7512#endif 7513 7514static void igb_shutdown(struct pci_dev *pdev) 7515{ 7516 bool wake; 7517 7518 __igb_shutdown(pdev, &wake, 0); 7519 7520 if (system_state == SYSTEM_POWER_OFF) { 7521 pci_wake_from_d3(pdev, wake); 7522 pci_set_power_state(pdev, PCI_D3hot); 7523 } 7524} 7525 7526#ifdef CONFIG_PCI_IOV 7527static int igb_sriov_reinit(struct pci_dev *dev) 7528{ 7529 struct net_device *netdev = pci_get_drvdata(dev); 7530 struct igb_adapter *adapter = netdev_priv(netdev); 7531 struct pci_dev *pdev = adapter->pdev; 7532 7533 rtnl_lock(); 7534 7535 if (netif_running(netdev)) 7536 igb_close(netdev); 7537 7538 igb_clear_interrupt_scheme(adapter); 7539 7540 igb_init_queue_configuration(adapter); 7541 7542 if (igb_init_interrupt_scheme(adapter, true)) { 7543 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7544 return -ENOMEM; 7545 } 7546 7547 if (netif_running(netdev)) 7548 igb_open(netdev); 7549 7550 rtnl_unlock(); 7551 7552 return 0; 7553} 7554 7555static int igb_pci_disable_sriov(struct pci_dev *dev) 7556{ 7557 int err = igb_disable_sriov(dev); 7558 7559 if (!err) 7560 err = igb_sriov_reinit(dev); 7561 7562 return err; 7563} 7564 7565static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7566{ 7567 int err = igb_enable_sriov(dev, num_vfs); 7568 7569 if (err) 7570 goto out; 7571 7572 err = igb_sriov_reinit(dev); 7573 if (!err) 7574 return num_vfs; 7575 7576out: 7577 return err; 7578} 7579 7580#endif 7581static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7582{ 7583#ifdef CONFIG_PCI_IOV 7584 if (num_vfs == 0) 7585 return igb_pci_disable_sriov(dev); 7586 else 7587 return igb_pci_enable_sriov(dev, num_vfs); 7588#endif 7589 return 0; 7590} 7591 7592#ifdef CONFIG_NET_POLL_CONTROLLER 7593/* Polling 'interrupt' - used by things like netconsole to send skbs 7594 * without having to re-enable interrupts. It's not called while 7595 * the interrupt routine is executing. 7596 */ 7597static void igb_netpoll(struct net_device *netdev) 7598{ 7599 struct igb_adapter *adapter = netdev_priv(netdev); 7600 struct e1000_hw *hw = &adapter->hw; 7601 struct igb_q_vector *q_vector; 7602 int i; 7603 7604 for (i = 0; i < adapter->num_q_vectors; i++) { 7605 q_vector = adapter->q_vector[i]; 7606 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7607 wr32(E1000_EIMC, q_vector->eims_value); 7608 else 7609 igb_irq_disable(adapter); 7610 napi_schedule(&q_vector->napi); 7611 } 7612} 7613#endif /* CONFIG_NET_POLL_CONTROLLER */ 7614 7615/** 7616 * igb_io_error_detected - called when PCI error is detected 7617 * @pdev: Pointer to PCI device 7618 * @state: The current pci connection state 7619 * 7620 * This function is called after a PCI bus error affecting 7621 * this device has been detected. 7622 **/ 7623static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7624 pci_channel_state_t state) 7625{ 7626 struct net_device *netdev = pci_get_drvdata(pdev); 7627 struct igb_adapter *adapter = netdev_priv(netdev); 7628 7629 netif_device_detach(netdev); 7630 7631 if (state == pci_channel_io_perm_failure) 7632 return PCI_ERS_RESULT_DISCONNECT; 7633 7634 if (netif_running(netdev)) 7635 igb_down(adapter); 7636 pci_disable_device(pdev); 7637 7638 /* Request a slot slot reset. */ 7639 return PCI_ERS_RESULT_NEED_RESET; 7640} 7641 7642/** 7643 * igb_io_slot_reset - called after the pci bus has been reset. 7644 * @pdev: Pointer to PCI device 7645 * 7646 * Restart the card from scratch, as if from a cold-boot. Implementation 7647 * resembles the first-half of the igb_resume routine. 7648 **/ 7649static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 7650{ 7651 struct net_device *netdev = pci_get_drvdata(pdev); 7652 struct igb_adapter *adapter = netdev_priv(netdev); 7653 struct e1000_hw *hw = &adapter->hw; 7654 pci_ers_result_t result; 7655 int err; 7656 7657 if (pci_enable_device_mem(pdev)) { 7658 dev_err(&pdev->dev, 7659 "Cannot re-enable PCI device after reset.\n"); 7660 result = PCI_ERS_RESULT_DISCONNECT; 7661 } else { 7662 pci_set_master(pdev); 7663 pci_restore_state(pdev); 7664 pci_save_state(pdev); 7665 7666 pci_enable_wake(pdev, PCI_D3hot, 0); 7667 pci_enable_wake(pdev, PCI_D3cold, 0); 7668 7669 igb_reset(adapter); 7670 wr32(E1000_WUS, ~0); 7671 result = PCI_ERS_RESULT_RECOVERED; 7672 } 7673 7674 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7675 if (err) { 7676 dev_err(&pdev->dev, 7677 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7678 err); 7679 /* non-fatal, continue */ 7680 } 7681 7682 return result; 7683} 7684 7685/** 7686 * igb_io_resume - called when traffic can start flowing again. 7687 * @pdev: Pointer to PCI device 7688 * 7689 * This callback is called when the error recovery driver tells us that 7690 * its OK to resume normal operation. Implementation resembles the 7691 * second-half of the igb_resume routine. 7692 */ 7693static void igb_io_resume(struct pci_dev *pdev) 7694{ 7695 struct net_device *netdev = pci_get_drvdata(pdev); 7696 struct igb_adapter *adapter = netdev_priv(netdev); 7697 7698 if (netif_running(netdev)) { 7699 if (igb_up(adapter)) { 7700 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7701 return; 7702 } 7703 } 7704 7705 netif_device_attach(netdev); 7706 7707 /* let the f/w know that the h/w is now under the control of the 7708 * driver. 7709 */ 7710 igb_get_hw_control(adapter); 7711} 7712 7713static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7714 u8 qsel) 7715{ 7716 u32 rar_low, rar_high; 7717 struct e1000_hw *hw = &adapter->hw; 7718 7719 /* HW expects these in little endian so we reverse the byte order 7720 * from network order (big endian) to little endian 7721 */ 7722 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 7723 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 7724 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 7725 7726 /* Indicate to hardware the Address is Valid. */ 7727 rar_high |= E1000_RAH_AV; 7728 7729 if (hw->mac.type == e1000_82575) 7730 rar_high |= E1000_RAH_POOL_1 * qsel; 7731 else 7732 rar_high |= E1000_RAH_POOL_1 << qsel; 7733 7734 wr32(E1000_RAL(index), rar_low); 7735 wrfl(); 7736 wr32(E1000_RAH(index), rar_high); 7737 wrfl(); 7738} 7739 7740static int igb_set_vf_mac(struct igb_adapter *adapter, 7741 int vf, unsigned char *mac_addr) 7742{ 7743 struct e1000_hw *hw = &adapter->hw; 7744 /* VF MAC addresses start at end of receive addresses and moves 7745 * towards the first, as a result a collision should not be possible 7746 */ 7747 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7748 7749 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7750 7751 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7752 7753 return 0; 7754} 7755 7756static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7757{ 7758 struct igb_adapter *adapter = netdev_priv(netdev); 7759 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7760 return -EINVAL; 7761 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7762 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7763 dev_info(&adapter->pdev->dev, 7764 "Reload the VF driver to make this change effective."); 7765 if (test_bit(__IGB_DOWN, &adapter->state)) { 7766 dev_warn(&adapter->pdev->dev, 7767 "The VF MAC address has been set, but the PF device is not up.\n"); 7768 dev_warn(&adapter->pdev->dev, 7769 "Bring the PF device up before attempting to use the VF device.\n"); 7770 } 7771 return igb_set_vf_mac(adapter, vf, mac); 7772} 7773 7774static int igb_link_mbps(int internal_link_speed) 7775{ 7776 switch (internal_link_speed) { 7777 case SPEED_100: 7778 return 100; 7779 case SPEED_1000: 7780 return 1000; 7781 default: 7782 return 0; 7783 } 7784} 7785 7786static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7787 int link_speed) 7788{ 7789 int rf_dec, rf_int; 7790 u32 bcnrc_val; 7791 7792 if (tx_rate != 0) { 7793 /* Calculate the rate factor values to set */ 7794 rf_int = link_speed / tx_rate; 7795 rf_dec = (link_speed - (rf_int * tx_rate)); 7796 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / 7797 tx_rate; 7798 7799 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7800 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 7801 E1000_RTTBCNRC_RF_INT_MASK); 7802 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7803 } else { 7804 bcnrc_val = 0; 7805 } 7806 7807 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7808 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7809 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7810 */ 7811 wr32(E1000_RTTBCNRM, 0x14); 7812 wr32(E1000_RTTBCNRC, bcnrc_val); 7813} 7814 7815static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7816{ 7817 int actual_link_speed, i; 7818 bool reset_rate = false; 7819 7820 /* VF TX rate limit was not set or not supported */ 7821 if ((adapter->vf_rate_link_speed == 0) || 7822 (adapter->hw.mac.type != e1000_82576)) 7823 return; 7824 7825 actual_link_speed = igb_link_mbps(adapter->link_speed); 7826 if (actual_link_speed != adapter->vf_rate_link_speed) { 7827 reset_rate = true; 7828 adapter->vf_rate_link_speed = 0; 7829 dev_info(&adapter->pdev->dev, 7830 "Link speed has been changed. VF Transmit rate is disabled\n"); 7831 } 7832 7833 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7834 if (reset_rate) 7835 adapter->vf_data[i].tx_rate = 0; 7836 7837 igb_set_vf_rate_limit(&adapter->hw, i, 7838 adapter->vf_data[i].tx_rate, 7839 actual_link_speed); 7840 } 7841} 7842 7843static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) 7844{ 7845 struct igb_adapter *adapter = netdev_priv(netdev); 7846 struct e1000_hw *hw = &adapter->hw; 7847 int actual_link_speed; 7848 7849 if (hw->mac.type != e1000_82576) 7850 return -EOPNOTSUPP; 7851 7852 actual_link_speed = igb_link_mbps(adapter->link_speed); 7853 if ((vf >= adapter->vfs_allocated_count) || 7854 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7855 (tx_rate < 0) || (tx_rate > actual_link_speed)) 7856 return -EINVAL; 7857 7858 adapter->vf_rate_link_speed = actual_link_speed; 7859 adapter->vf_data[vf].tx_rate = (u16)tx_rate; 7860 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); 7861 7862 return 0; 7863} 7864 7865static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 7866 bool setting) 7867{ 7868 struct igb_adapter *adapter = netdev_priv(netdev); 7869 struct e1000_hw *hw = &adapter->hw; 7870 u32 reg_val, reg_offset; 7871 7872 if (!adapter->vfs_allocated_count) 7873 return -EOPNOTSUPP; 7874 7875 if (vf >= adapter->vfs_allocated_count) 7876 return -EINVAL; 7877 7878 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 7879 reg_val = rd32(reg_offset); 7880 if (setting) 7881 reg_val |= ((1 << vf) | 7882 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7883 else 7884 reg_val &= ~((1 << vf) | 7885 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7886 wr32(reg_offset, reg_val); 7887 7888 adapter->vf_data[vf].spoofchk_enabled = setting; 7889 return E1000_SUCCESS; 7890} 7891 7892static int igb_ndo_get_vf_config(struct net_device *netdev, 7893 int vf, struct ifla_vf_info *ivi) 7894{ 7895 struct igb_adapter *adapter = netdev_priv(netdev); 7896 if (vf >= adapter->vfs_allocated_count) 7897 return -EINVAL; 7898 ivi->vf = vf; 7899 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7900 ivi->tx_rate = adapter->vf_data[vf].tx_rate; 7901 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7902 ivi->qos = adapter->vf_data[vf].pf_qos; 7903 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 7904 return 0; 7905} 7906 7907static void igb_vmm_control(struct igb_adapter *adapter) 7908{ 7909 struct e1000_hw *hw = &adapter->hw; 7910 u32 reg; 7911 7912 switch (hw->mac.type) { 7913 case e1000_82575: 7914 case e1000_i210: 7915 case e1000_i211: 7916 case e1000_i354: 7917 default: 7918 /* replication is not supported for 82575 */ 7919 return; 7920 case e1000_82576: 7921 /* notify HW that the MAC is adding vlan tags */ 7922 reg = rd32(E1000_DTXCTL); 7923 reg |= E1000_DTXCTL_VLAN_ADDED; 7924 wr32(E1000_DTXCTL, reg); 7925 case e1000_82580: 7926 /* enable replication vlan tag stripping */ 7927 reg = rd32(E1000_RPLOLR); 7928 reg |= E1000_RPLOLR_STRVLAN; 7929 wr32(E1000_RPLOLR, reg); 7930 case e1000_i350: 7931 /* none of the above registers are supported by i350 */ 7932 break; 7933 } 7934 7935 if (adapter->vfs_allocated_count) { 7936 igb_vmdq_set_loopback_pf(hw, true); 7937 igb_vmdq_set_replication_pf(hw, true); 7938 igb_vmdq_set_anti_spoofing_pf(hw, true, 7939 adapter->vfs_allocated_count); 7940 } else { 7941 igb_vmdq_set_loopback_pf(hw, false); 7942 igb_vmdq_set_replication_pf(hw, false); 7943 } 7944} 7945 7946static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7947{ 7948 struct e1000_hw *hw = &adapter->hw; 7949 u32 dmac_thr; 7950 u16 hwm; 7951 7952 if (hw->mac.type > e1000_82580) { 7953 if (adapter->flags & IGB_FLAG_DMAC) { 7954 u32 reg; 7955 7956 /* force threshold to 0. */ 7957 wr32(E1000_DMCTXTH, 0); 7958 7959 /* DMA Coalescing high water mark needs to be greater 7960 * than the Rx threshold. Set hwm to PBA - max frame 7961 * size in 16B units, capping it at PBA - 6KB. 7962 */ 7963 hwm = 64 * pba - adapter->max_frame_size / 16; 7964 if (hwm < 64 * (pba - 6)) 7965 hwm = 64 * (pba - 6); 7966 reg = rd32(E1000_FCRTC); 7967 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 7968 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 7969 & E1000_FCRTC_RTH_COAL_MASK); 7970 wr32(E1000_FCRTC, reg); 7971 7972 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 7973 * frame size, capping it at PBA - 10KB. 7974 */ 7975 dmac_thr = pba - adapter->max_frame_size / 512; 7976 if (dmac_thr < pba - 10) 7977 dmac_thr = pba - 10; 7978 reg = rd32(E1000_DMACR); 7979 reg &= ~E1000_DMACR_DMACTHR_MASK; 7980 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 7981 & E1000_DMACR_DMACTHR_MASK); 7982 7983 /* transition to L0x or L1 if available..*/ 7984 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 7985 7986 /* watchdog timer= +-1000 usec in 32usec intervals */ 7987 reg |= (1000 >> 5); 7988 7989 /* Disable BMC-to-OS Watchdog Enable */ 7990 if (hw->mac.type != e1000_i354) 7991 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 7992 7993 wr32(E1000_DMACR, reg); 7994 7995 /* no lower threshold to disable 7996 * coalescing(smart fifb)-UTRESH=0 7997 */ 7998 wr32(E1000_DMCRTRH, 0); 7999 8000 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8001 8002 wr32(E1000_DMCTLX, reg); 8003 8004 /* free space in tx packet buffer to wake from 8005 * DMA coal 8006 */ 8007 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8008 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8009 8010 /* make low power state decision controlled 8011 * by DMA coal 8012 */ 8013 reg = rd32(E1000_PCIEMISC); 8014 reg &= ~E1000_PCIEMISC_LX_DECISION; 8015 wr32(E1000_PCIEMISC, reg); 8016 } /* endif adapter->dmac is not disabled */ 8017 } else if (hw->mac.type == e1000_82580) { 8018 u32 reg = rd32(E1000_PCIEMISC); 8019 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8020 wr32(E1000_DMACR, 0); 8021 } 8022} 8023 8024/** 8025 * igb_read_i2c_byte - Reads 8 bit word over I2C 8026 * @hw: pointer to hardware structure 8027 * @byte_offset: byte offset to read 8028 * @dev_addr: device address 8029 * @data: value read 8030 * 8031 * Performs byte read operation over I2C interface at 8032 * a specified device address. 8033 **/ 8034s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8035 u8 dev_addr, u8 *data) 8036{ 8037 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8038 struct i2c_client *this_client = adapter->i2c_client; 8039 s32 status; 8040 u16 swfw_mask = 0; 8041 8042 if (!this_client) 8043 return E1000_ERR_I2C; 8044 8045 swfw_mask = E1000_SWFW_PHY0_SM; 8046 8047 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 8048 != E1000_SUCCESS) 8049 return E1000_ERR_SWFW_SYNC; 8050 8051 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8052 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8053 8054 if (status < 0) 8055 return E1000_ERR_I2C; 8056 else { 8057 *data = status; 8058 return E1000_SUCCESS; 8059 } 8060} 8061 8062/** 8063 * igb_write_i2c_byte - Writes 8 bit word over I2C 8064 * @hw: pointer to hardware structure 8065 * @byte_offset: byte offset to write 8066 * @dev_addr: device address 8067 * @data: value to write 8068 * 8069 * Performs byte write operation over I2C interface at 8070 * a specified device address. 8071 **/ 8072s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8073 u8 dev_addr, u8 data) 8074{ 8075 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8076 struct i2c_client *this_client = adapter->i2c_client; 8077 s32 status; 8078 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8079 8080 if (!this_client) 8081 return E1000_ERR_I2C; 8082 8083 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) 8084 return E1000_ERR_SWFW_SYNC; 8085 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8086 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8087 8088 if (status) 8089 return E1000_ERR_I2C; 8090 else 8091 return E1000_SUCCESS; 8092 8093} 8094 8095int igb_reinit_queues(struct igb_adapter *adapter) 8096{ 8097 struct net_device *netdev = adapter->netdev; 8098 struct pci_dev *pdev = adapter->pdev; 8099 int err = 0; 8100 8101 if (netif_running(netdev)) 8102 igb_close(netdev); 8103 8104 igb_reset_interrupt_capability(adapter); 8105 8106 if (igb_init_interrupt_scheme(adapter, true)) { 8107 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8108 return -ENOMEM; 8109 } 8110 8111 if (netif_running(netdev)) 8112 err = igb_open(netdev); 8113 8114 return err; 8115} 8116/* igb_main.c */ 8117