igb_main.c revision 74cfb2e1f296b3f962016adf41b316b8cf7d4ed4
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25*******************************************************************************/ 26 27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 28 29#include <linux/module.h> 30#include <linux/types.h> 31#include <linux/init.h> 32#include <linux/bitops.h> 33#include <linux/vmalloc.h> 34#include <linux/pagemap.h> 35#include <linux/netdevice.h> 36#include <linux/ipv6.h> 37#include <linux/slab.h> 38#include <net/checksum.h> 39#include <net/ip6_checksum.h> 40#include <linux/net_tstamp.h> 41#include <linux/mii.h> 42#include <linux/ethtool.h> 43#include <linux/if.h> 44#include <linux/if_vlan.h> 45#include <linux/pci.h> 46#include <linux/pci-aspm.h> 47#include <linux/delay.h> 48#include <linux/interrupt.h> 49#include <linux/ip.h> 50#include <linux/tcp.h> 51#include <linux/sctp.h> 52#include <linux/if_ether.h> 53#include <linux/aer.h> 54#include <linux/prefetch.h> 55#include <linux/pm_runtime.h> 56#ifdef CONFIG_IGB_DCA 57#include <linux/dca.h> 58#endif 59#include <linux/i2c.h> 60#include "igb.h" 61 62#define MAJ 5 63#define MIN 0 64#define BUILD 5 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 66__stringify(BUILD) "-k" 67char igb_driver_name[] = "igb"; 68char igb_driver_version[] = DRV_VERSION; 69static const char igb_driver_string[] = 70 "Intel(R) Gigabit Ethernet Network Driver"; 71static const char igb_copyright[] = 72 "Copyright (c) 2007-2014 Intel Corporation."; 73 74static const struct e1000_info *igb_info_tbl[] = { 75 [board_82575] = &e1000_82575_info, 76}; 77 78static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 114 /* required last entry */ 115 {0, } 116}; 117 118MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 119 120void igb_reset(struct igb_adapter *); 121static int igb_setup_all_tx_resources(struct igb_adapter *); 122static int igb_setup_all_rx_resources(struct igb_adapter *); 123static void igb_free_all_tx_resources(struct igb_adapter *); 124static void igb_free_all_rx_resources(struct igb_adapter *); 125static void igb_setup_mrqc(struct igb_adapter *); 126static int igb_probe(struct pci_dev *, const struct pci_device_id *); 127static void igb_remove(struct pci_dev *pdev); 128static int igb_sw_init(struct igb_adapter *); 129static int igb_open(struct net_device *); 130static int igb_close(struct net_device *); 131static void igb_configure(struct igb_adapter *); 132static void igb_configure_tx(struct igb_adapter *); 133static void igb_configure_rx(struct igb_adapter *); 134static void igb_clean_all_tx_rings(struct igb_adapter *); 135static void igb_clean_all_rx_rings(struct igb_adapter *); 136static void igb_clean_tx_ring(struct igb_ring *); 137static void igb_clean_rx_ring(struct igb_ring *); 138static void igb_set_rx_mode(struct net_device *); 139static void igb_update_phy_info(unsigned long); 140static void igb_watchdog(unsigned long); 141static void igb_watchdog_task(struct work_struct *); 142static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 143static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 144 struct rtnl_link_stats64 *stats); 145static int igb_change_mtu(struct net_device *, int); 146static int igb_set_mac(struct net_device *, void *); 147static void igb_set_uta(struct igb_adapter *adapter); 148static irqreturn_t igb_intr(int irq, void *); 149static irqreturn_t igb_intr_msi(int irq, void *); 150static irqreturn_t igb_msix_other(int irq, void *); 151static irqreturn_t igb_msix_ring(int irq, void *); 152#ifdef CONFIG_IGB_DCA 153static void igb_update_dca(struct igb_q_vector *); 154static void igb_setup_dca(struct igb_adapter *); 155#endif /* CONFIG_IGB_DCA */ 156static int igb_poll(struct napi_struct *, int); 157static bool igb_clean_tx_irq(struct igb_q_vector *); 158static bool igb_clean_rx_irq(struct igb_q_vector *, int); 159static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 160static void igb_tx_timeout(struct net_device *); 161static void igb_reset_task(struct work_struct *); 162static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); 163static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 164static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 165static void igb_restore_vlan(struct igb_adapter *); 166static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 167static void igb_ping_all_vfs(struct igb_adapter *); 168static void igb_msg_task(struct igb_adapter *); 169static void igb_vmm_control(struct igb_adapter *); 170static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 171static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 172static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 173static int igb_ndo_set_vf_vlan(struct net_device *netdev, 174 int vf, u16 vlan, u8 qos); 175static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 176static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 177 bool setting); 178static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 179 struct ifla_vf_info *ivi); 180static void igb_check_vf_rate_limit(struct igb_adapter *); 181 182#ifdef CONFIG_PCI_IOV 183static int igb_vf_configure(struct igb_adapter *adapter, int vf); 184static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 185#endif 186 187#ifdef CONFIG_PM 188#ifdef CONFIG_PM_SLEEP 189static int igb_suspend(struct device *); 190#endif 191static int igb_resume(struct device *); 192#ifdef CONFIG_PM_RUNTIME 193static int igb_runtime_suspend(struct device *dev); 194static int igb_runtime_resume(struct device *dev); 195static int igb_runtime_idle(struct device *dev); 196#endif 197static const struct dev_pm_ops igb_pm_ops = { 198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 200 igb_runtime_idle) 201}; 202#endif 203static void igb_shutdown(struct pci_dev *); 204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 205#ifdef CONFIG_IGB_DCA 206static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 207static struct notifier_block dca_notifier = { 208 .notifier_call = igb_notify_dca, 209 .next = NULL, 210 .priority = 0 211}; 212#endif 213#ifdef CONFIG_NET_POLL_CONTROLLER 214/* for netdump / net console */ 215static void igb_netpoll(struct net_device *); 216#endif 217#ifdef CONFIG_PCI_IOV 218static unsigned int max_vfs = 0; 219module_param(max_vfs, uint, 0); 220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " 221 "per physical function"); 222#endif /* CONFIG_PCI_IOV */ 223 224static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 225 pci_channel_state_t); 226static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 227static void igb_io_resume(struct pci_dev *); 228 229static const struct pci_error_handlers igb_err_handler = { 230 .error_detected = igb_io_error_detected, 231 .slot_reset = igb_io_slot_reset, 232 .resume = igb_io_resume, 233}; 234 235static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 236 237static struct pci_driver igb_driver = { 238 .name = igb_driver_name, 239 .id_table = igb_pci_tbl, 240 .probe = igb_probe, 241 .remove = igb_remove, 242#ifdef CONFIG_PM 243 .driver.pm = &igb_pm_ops, 244#endif 245 .shutdown = igb_shutdown, 246 .sriov_configure = igb_pci_sriov_configure, 247 .err_handler = &igb_err_handler 248}; 249 250MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 251MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 252MODULE_LICENSE("GPL"); 253MODULE_VERSION(DRV_VERSION); 254 255#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 256static int debug = -1; 257module_param(debug, int, 0); 258MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 259 260struct igb_reg_info { 261 u32 ofs; 262 char *name; 263}; 264 265static const struct igb_reg_info igb_reg_info_tbl[] = { 266 267 /* General Registers */ 268 {E1000_CTRL, "CTRL"}, 269 {E1000_STATUS, "STATUS"}, 270 {E1000_CTRL_EXT, "CTRL_EXT"}, 271 272 /* Interrupt Registers */ 273 {E1000_ICR, "ICR"}, 274 275 /* RX Registers */ 276 {E1000_RCTL, "RCTL"}, 277 {E1000_RDLEN(0), "RDLEN"}, 278 {E1000_RDH(0), "RDH"}, 279 {E1000_RDT(0), "RDT"}, 280 {E1000_RXDCTL(0), "RXDCTL"}, 281 {E1000_RDBAL(0), "RDBAL"}, 282 {E1000_RDBAH(0), "RDBAH"}, 283 284 /* TX Registers */ 285 {E1000_TCTL, "TCTL"}, 286 {E1000_TDBAL(0), "TDBAL"}, 287 {E1000_TDBAH(0), "TDBAH"}, 288 {E1000_TDLEN(0), "TDLEN"}, 289 {E1000_TDH(0), "TDH"}, 290 {E1000_TDT(0), "TDT"}, 291 {E1000_TXDCTL(0), "TXDCTL"}, 292 {E1000_TDFH, "TDFH"}, 293 {E1000_TDFT, "TDFT"}, 294 {E1000_TDFHS, "TDFHS"}, 295 {E1000_TDFPC, "TDFPC"}, 296 297 /* List Terminator */ 298 {} 299}; 300 301/* igb_regdump - register printout routine */ 302static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 303{ 304 int n = 0; 305 char rname[16]; 306 u32 regs[8]; 307 308 switch (reginfo->ofs) { 309 case E1000_RDLEN(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDLEN(n)); 312 break; 313 case E1000_RDH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDH(n)); 316 break; 317 case E1000_RDT(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_RDT(n)); 320 break; 321 case E1000_RXDCTL(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_RXDCTL(n)); 324 break; 325 case E1000_RDBAL(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_RDBAL(n)); 328 break; 329 case E1000_RDBAH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_RDBAH(n)); 332 break; 333 case E1000_TDBAL(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_RDBAL(n)); 336 break; 337 case E1000_TDBAH(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TDBAH(n)); 340 break; 341 case E1000_TDLEN(0): 342 for (n = 0; n < 4; n++) 343 regs[n] = rd32(E1000_TDLEN(n)); 344 break; 345 case E1000_TDH(0): 346 for (n = 0; n < 4; n++) 347 regs[n] = rd32(E1000_TDH(n)); 348 break; 349 case E1000_TDT(0): 350 for (n = 0; n < 4; n++) 351 regs[n] = rd32(E1000_TDT(n)); 352 break; 353 case E1000_TXDCTL(0): 354 for (n = 0; n < 4; n++) 355 regs[n] = rd32(E1000_TXDCTL(n)); 356 break; 357 default: 358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 359 return; 360 } 361 362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 364 regs[2], regs[3]); 365} 366 367/* igb_dump - Print registers, Tx-rings and Rx-rings */ 368static void igb_dump(struct igb_adapter *adapter) 369{ 370 struct net_device *netdev = adapter->netdev; 371 struct e1000_hw *hw = &adapter->hw; 372 struct igb_reg_info *reginfo; 373 struct igb_ring *tx_ring; 374 union e1000_adv_tx_desc *tx_desc; 375 struct my_u0 { u64 a; u64 b; } *u0; 376 struct igb_ring *rx_ring; 377 union e1000_adv_rx_desc *rx_desc; 378 u32 staterr; 379 u16 i, n; 380 381 if (!netif_msg_hw(adapter)) 382 return; 383 384 /* Print netdevice Info */ 385 if (netdev) { 386 dev_info(&adapter->pdev->dev, "Net device Info\n"); 387 pr_info("Device Name state trans_start " 388 "last_rx\n"); 389 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 390 netdev->state, netdev->trans_start, netdev->last_rx); 391 } 392 393 /* Print Registers */ 394 dev_info(&adapter->pdev->dev, "Register Dump\n"); 395 pr_info(" Register Name Value\n"); 396 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 397 reginfo->name; reginfo++) { 398 igb_regdump(hw, reginfo); 399 } 400 401 /* Print TX Ring Summary */ 402 if (!netdev || !netif_running(netdev)) 403 goto exit; 404 405 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 406 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 407 for (n = 0; n < adapter->num_tx_queues; n++) { 408 struct igb_tx_buffer *buffer_info; 409 tx_ring = adapter->tx_ring[n]; 410 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 411 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 412 n, tx_ring->next_to_use, tx_ring->next_to_clean, 413 (u64)dma_unmap_addr(buffer_info, dma), 414 dma_unmap_len(buffer_info, len), 415 buffer_info->next_to_watch, 416 (u64)buffer_info->time_stamp); 417 } 418 419 /* Print TX Rings */ 420 if (!netif_msg_tx_done(adapter)) 421 goto rx_ring_summary; 422 423 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 424 425 /* Transmit Descriptor Formats 426 * 427 * Advanced Transmit Descriptor 428 * +--------------------------------------------------------------+ 429 * 0 | Buffer Address [63:0] | 430 * +--------------------------------------------------------------+ 431 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 432 * +--------------------------------------------------------------+ 433 * 63 46 45 40 39 38 36 35 32 31 24 15 0 434 */ 435 436 for (n = 0; n < adapter->num_tx_queues; n++) { 437 tx_ring = adapter->tx_ring[n]; 438 pr_info("------------------------------------\n"); 439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 440 pr_info("------------------------------------\n"); 441 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] " 442 "[bi->dma ] leng ntw timestamp " 443 "bi->skb\n"); 444 445 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 446 const char *next_desc; 447 struct igb_tx_buffer *buffer_info; 448 tx_desc = IGB_TX_DESC(tx_ring, i); 449 buffer_info = &tx_ring->tx_buffer_info[i]; 450 u0 = (struct my_u0 *)tx_desc; 451 if (i == tx_ring->next_to_use && 452 i == tx_ring->next_to_clean) 453 next_desc = " NTC/U"; 454 else if (i == tx_ring->next_to_use) 455 next_desc = " NTU"; 456 else if (i == tx_ring->next_to_clean) 457 next_desc = " NTC"; 458 else 459 next_desc = ""; 460 461 pr_info("T [0x%03X] %016llX %016llX %016llX" 462 " %04X %p %016llX %p%s\n", i, 463 le64_to_cpu(u0->a), 464 le64_to_cpu(u0->b), 465 (u64)dma_unmap_addr(buffer_info, dma), 466 dma_unmap_len(buffer_info, len), 467 buffer_info->next_to_watch, 468 (u64)buffer_info->time_stamp, 469 buffer_info->skb, next_desc); 470 471 if (netif_msg_pktdata(adapter) && buffer_info->skb) 472 print_hex_dump(KERN_INFO, "", 473 DUMP_PREFIX_ADDRESS, 474 16, 1, buffer_info->skb->data, 475 dma_unmap_len(buffer_info, len), 476 true); 477 } 478 } 479 480 /* Print RX Rings Summary */ 481rx_ring_summary: 482 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 483 pr_info("Queue [NTU] [NTC]\n"); 484 for (n = 0; n < adapter->num_rx_queues; n++) { 485 rx_ring = adapter->rx_ring[n]; 486 pr_info(" %5d %5X %5X\n", 487 n, rx_ring->next_to_use, rx_ring->next_to_clean); 488 } 489 490 /* Print RX Rings */ 491 if (!netif_msg_rx_status(adapter)) 492 goto exit; 493 494 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 495 496 /* Advanced Receive Descriptor (Read) Format 497 * 63 1 0 498 * +-----------------------------------------------------+ 499 * 0 | Packet Buffer Address [63:1] |A0/NSE| 500 * +----------------------------------------------+------+ 501 * 8 | Header Buffer Address [63:1] | DD | 502 * +-----------------------------------------------------+ 503 * 504 * 505 * Advanced Receive Descriptor (Write-Back) Format 506 * 507 * 63 48 47 32 31 30 21 20 17 16 4 3 0 508 * +------------------------------------------------------+ 509 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 510 * | Checksum Ident | | | | Type | Type | 511 * +------------------------------------------------------+ 512 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 513 * +------------------------------------------------------+ 514 * 63 48 47 32 31 20 19 0 515 */ 516 517 for (n = 0; n < adapter->num_rx_queues; n++) { 518 rx_ring = adapter->rx_ring[n]; 519 pr_info("------------------------------------\n"); 520 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 521 pr_info("------------------------------------\n"); 522 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] " 523 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 524 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----" 525 "----------- [bi->skb] <-- Adv Rx Write-Back format\n"); 526 527 for (i = 0; i < rx_ring->count; i++) { 528 const char *next_desc; 529 struct igb_rx_buffer *buffer_info; 530 buffer_info = &rx_ring->rx_buffer_info[i]; 531 rx_desc = IGB_RX_DESC(rx_ring, i); 532 u0 = (struct my_u0 *)rx_desc; 533 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 534 535 if (i == rx_ring->next_to_use) 536 next_desc = " NTU"; 537 else if (i == rx_ring->next_to_clean) 538 next_desc = " NTC"; 539 else 540 next_desc = ""; 541 542 if (staterr & E1000_RXD_STAT_DD) { 543 /* Descriptor Done */ 544 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 545 "RWB", i, 546 le64_to_cpu(u0->a), 547 le64_to_cpu(u0->b), 548 next_desc); 549 } else { 550 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 551 "R ", i, 552 le64_to_cpu(u0->a), 553 le64_to_cpu(u0->b), 554 (u64)buffer_info->dma, 555 next_desc); 556 557 if (netif_msg_pktdata(adapter) && 558 buffer_info->dma && buffer_info->page) { 559 print_hex_dump(KERN_INFO, "", 560 DUMP_PREFIX_ADDRESS, 561 16, 1, 562 page_address(buffer_info->page) + 563 buffer_info->page_offset, 564 IGB_RX_BUFSZ, true); 565 } 566 } 567 } 568 } 569 570exit: 571 return; 572} 573 574/** 575 * igb_get_i2c_data - Reads the I2C SDA data bit 576 * @hw: pointer to hardware structure 577 * @i2cctl: Current value of I2CCTL register 578 * 579 * Returns the I2C data bit value 580 **/ 581static int igb_get_i2c_data(void *data) 582{ 583 struct igb_adapter *adapter = (struct igb_adapter *)data; 584 struct e1000_hw *hw = &adapter->hw; 585 s32 i2cctl = rd32(E1000_I2CPARAMS); 586 587 return ((i2cctl & E1000_I2C_DATA_IN) != 0); 588} 589 590/** 591 * igb_set_i2c_data - Sets the I2C data bit 592 * @data: pointer to hardware structure 593 * @state: I2C data value (0 or 1) to set 594 * 595 * Sets the I2C data bit 596 **/ 597static void igb_set_i2c_data(void *data, int state) 598{ 599 struct igb_adapter *adapter = (struct igb_adapter *)data; 600 struct e1000_hw *hw = &adapter->hw; 601 s32 i2cctl = rd32(E1000_I2CPARAMS); 602 603 if (state) 604 i2cctl |= E1000_I2C_DATA_OUT; 605 else 606 i2cctl &= ~E1000_I2C_DATA_OUT; 607 608 i2cctl &= ~E1000_I2C_DATA_OE_N; 609 i2cctl |= E1000_I2C_CLK_OE_N; 610 wr32(E1000_I2CPARAMS, i2cctl); 611 wrfl(); 612 613} 614 615/** 616 * igb_set_i2c_clk - Sets the I2C SCL clock 617 * @data: pointer to hardware structure 618 * @state: state to set clock 619 * 620 * Sets the I2C clock line to state 621 **/ 622static void igb_set_i2c_clk(void *data, int state) 623{ 624 struct igb_adapter *adapter = (struct igb_adapter *)data; 625 struct e1000_hw *hw = &adapter->hw; 626 s32 i2cctl = rd32(E1000_I2CPARAMS); 627 628 if (state) { 629 i2cctl |= E1000_I2C_CLK_OUT; 630 i2cctl &= ~E1000_I2C_CLK_OE_N; 631 } else { 632 i2cctl &= ~E1000_I2C_CLK_OUT; 633 i2cctl &= ~E1000_I2C_CLK_OE_N; 634 } 635 wr32(E1000_I2CPARAMS, i2cctl); 636 wrfl(); 637} 638 639/** 640 * igb_get_i2c_clk - Gets the I2C SCL clock state 641 * @data: pointer to hardware structure 642 * 643 * Gets the I2C clock state 644 **/ 645static int igb_get_i2c_clk(void *data) 646{ 647 struct igb_adapter *adapter = (struct igb_adapter *)data; 648 struct e1000_hw *hw = &adapter->hw; 649 s32 i2cctl = rd32(E1000_I2CPARAMS); 650 651 return ((i2cctl & E1000_I2C_CLK_IN) != 0); 652} 653 654static const struct i2c_algo_bit_data igb_i2c_algo = { 655 .setsda = igb_set_i2c_data, 656 .setscl = igb_set_i2c_clk, 657 .getsda = igb_get_i2c_data, 658 .getscl = igb_get_i2c_clk, 659 .udelay = 5, 660 .timeout = 20, 661}; 662 663/** 664 * igb_get_hw_dev - return device 665 * @hw: pointer to hardware structure 666 * 667 * used by hardware layer to print debugging information 668 **/ 669struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 670{ 671 struct igb_adapter *adapter = hw->back; 672 return adapter->netdev; 673} 674 675/** 676 * igb_init_module - Driver Registration Routine 677 * 678 * igb_init_module is the first routine called when the driver is 679 * loaded. All it does is register with the PCI subsystem. 680 **/ 681static int __init igb_init_module(void) 682{ 683 int ret; 684 pr_info("%s - version %s\n", 685 igb_driver_string, igb_driver_version); 686 687 pr_info("%s\n", igb_copyright); 688 689#ifdef CONFIG_IGB_DCA 690 dca_register_notify(&dca_notifier); 691#endif 692 ret = pci_register_driver(&igb_driver); 693 return ret; 694} 695 696module_init(igb_init_module); 697 698/** 699 * igb_exit_module - Driver Exit Cleanup Routine 700 * 701 * igb_exit_module is called just before the driver is removed 702 * from memory. 703 **/ 704static void __exit igb_exit_module(void) 705{ 706#ifdef CONFIG_IGB_DCA 707 dca_unregister_notify(&dca_notifier); 708#endif 709 pci_unregister_driver(&igb_driver); 710} 711 712module_exit(igb_exit_module); 713 714#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 715/** 716 * igb_cache_ring_register - Descriptor ring to register mapping 717 * @adapter: board private structure to initialize 718 * 719 * Once we know the feature-set enabled for the device, we'll cache 720 * the register offset the descriptor ring is assigned to. 721 **/ 722static void igb_cache_ring_register(struct igb_adapter *adapter) 723{ 724 int i = 0, j = 0; 725 u32 rbase_offset = adapter->vfs_allocated_count; 726 727 switch (adapter->hw.mac.type) { 728 case e1000_82576: 729 /* The queues are allocated for virtualization such that VF 0 730 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 731 * In order to avoid collision we start at the first free queue 732 * and continue consuming queues in the same sequence 733 */ 734 if (adapter->vfs_allocated_count) { 735 for (; i < adapter->rss_queues; i++) 736 adapter->rx_ring[i]->reg_idx = rbase_offset + 737 Q_IDX_82576(i); 738 } 739 case e1000_82575: 740 case e1000_82580: 741 case e1000_i350: 742 case e1000_i354: 743 case e1000_i210: 744 case e1000_i211: 745 default: 746 for (; i < adapter->num_rx_queues; i++) 747 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 748 for (; j < adapter->num_tx_queues; j++) 749 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 750 break; 751 } 752} 753 754/** 755 * igb_write_ivar - configure ivar for given MSI-X vector 756 * @hw: pointer to the HW structure 757 * @msix_vector: vector number we are allocating to a given ring 758 * @index: row index of IVAR register to write within IVAR table 759 * @offset: column offset of in IVAR, should be multiple of 8 760 * 761 * This function is intended to handle the writing of the IVAR register 762 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 763 * each containing an cause allocation for an Rx and Tx ring, and a 764 * variable number of rows depending on the number of queues supported. 765 **/ 766static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 767 int index, int offset) 768{ 769 u32 ivar = array_rd32(E1000_IVAR0, index); 770 771 /* clear any bits that are currently set */ 772 ivar &= ~((u32)0xFF << offset); 773 774 /* write vector and valid bit */ 775 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 776 777 array_wr32(E1000_IVAR0, index, ivar); 778} 779 780#define IGB_N0_QUEUE -1 781static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 782{ 783 struct igb_adapter *adapter = q_vector->adapter; 784 struct e1000_hw *hw = &adapter->hw; 785 int rx_queue = IGB_N0_QUEUE; 786 int tx_queue = IGB_N0_QUEUE; 787 u32 msixbm = 0; 788 789 if (q_vector->rx.ring) 790 rx_queue = q_vector->rx.ring->reg_idx; 791 if (q_vector->tx.ring) 792 tx_queue = q_vector->tx.ring->reg_idx; 793 794 switch (hw->mac.type) { 795 case e1000_82575: 796 /* The 82575 assigns vectors using a bitmask, which matches the 797 * bitmask for the EICR/EIMS/EIMC registers. To assign one 798 * or more queues to a vector, we write the appropriate bits 799 * into the MSIXBM register for that vector. 800 */ 801 if (rx_queue > IGB_N0_QUEUE) 802 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 803 if (tx_queue > IGB_N0_QUEUE) 804 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 805 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 806 msixbm |= E1000_EIMS_OTHER; 807 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 808 q_vector->eims_value = msixbm; 809 break; 810 case e1000_82576: 811 /* 82576 uses a table that essentially consists of 2 columns 812 * with 8 rows. The ordering is column-major so we use the 813 * lower 3 bits as the row index, and the 4th bit as the 814 * column offset. 815 */ 816 if (rx_queue > IGB_N0_QUEUE) 817 igb_write_ivar(hw, msix_vector, 818 rx_queue & 0x7, 819 (rx_queue & 0x8) << 1); 820 if (tx_queue > IGB_N0_QUEUE) 821 igb_write_ivar(hw, msix_vector, 822 tx_queue & 0x7, 823 ((tx_queue & 0x8) << 1) + 8); 824 q_vector->eims_value = 1 << msix_vector; 825 break; 826 case e1000_82580: 827 case e1000_i350: 828 case e1000_i354: 829 case e1000_i210: 830 case e1000_i211: 831 /* On 82580 and newer adapters the scheme is similar to 82576 832 * however instead of ordering column-major we have things 833 * ordered row-major. So we traverse the table by using 834 * bit 0 as the column offset, and the remaining bits as the 835 * row index. 836 */ 837 if (rx_queue > IGB_N0_QUEUE) 838 igb_write_ivar(hw, msix_vector, 839 rx_queue >> 1, 840 (rx_queue & 0x1) << 4); 841 if (tx_queue > IGB_N0_QUEUE) 842 igb_write_ivar(hw, msix_vector, 843 tx_queue >> 1, 844 ((tx_queue & 0x1) << 4) + 8); 845 q_vector->eims_value = 1 << msix_vector; 846 break; 847 default: 848 BUG(); 849 break; 850 } 851 852 /* add q_vector eims value to global eims_enable_mask */ 853 adapter->eims_enable_mask |= q_vector->eims_value; 854 855 /* configure q_vector to set itr on first interrupt */ 856 q_vector->set_itr = 1; 857} 858 859/** 860 * igb_configure_msix - Configure MSI-X hardware 861 * @adapter: board private structure to initialize 862 * 863 * igb_configure_msix sets up the hardware to properly 864 * generate MSI-X interrupts. 865 **/ 866static void igb_configure_msix(struct igb_adapter *adapter) 867{ 868 u32 tmp; 869 int i, vector = 0; 870 struct e1000_hw *hw = &adapter->hw; 871 872 adapter->eims_enable_mask = 0; 873 874 /* set vector for other causes, i.e. link changes */ 875 switch (hw->mac.type) { 876 case e1000_82575: 877 tmp = rd32(E1000_CTRL_EXT); 878 /* enable MSI-X PBA support*/ 879 tmp |= E1000_CTRL_EXT_PBA_CLR; 880 881 /* Auto-Mask interrupts upon ICR read. */ 882 tmp |= E1000_CTRL_EXT_EIAME; 883 tmp |= E1000_CTRL_EXT_IRCA; 884 885 wr32(E1000_CTRL_EXT, tmp); 886 887 /* enable msix_other interrupt */ 888 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 889 adapter->eims_other = E1000_EIMS_OTHER; 890 891 break; 892 893 case e1000_82576: 894 case e1000_82580: 895 case e1000_i350: 896 case e1000_i354: 897 case e1000_i210: 898 case e1000_i211: 899 /* Turn on MSI-X capability first, or our settings 900 * won't stick. And it will take days to debug. 901 */ 902 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 903 E1000_GPIE_PBA | E1000_GPIE_EIAME | 904 E1000_GPIE_NSICR); 905 906 /* enable msix_other interrupt */ 907 adapter->eims_other = 1 << vector; 908 tmp = (vector++ | E1000_IVAR_VALID) << 8; 909 910 wr32(E1000_IVAR_MISC, tmp); 911 break; 912 default: 913 /* do nothing, since nothing else supports MSI-X */ 914 break; 915 } /* switch (hw->mac.type) */ 916 917 adapter->eims_enable_mask |= adapter->eims_other; 918 919 for (i = 0; i < adapter->num_q_vectors; i++) 920 igb_assign_vector(adapter->q_vector[i], vector++); 921 922 wrfl(); 923} 924 925/** 926 * igb_request_msix - Initialize MSI-X interrupts 927 * @adapter: board private structure to initialize 928 * 929 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 930 * kernel. 931 **/ 932static int igb_request_msix(struct igb_adapter *adapter) 933{ 934 struct net_device *netdev = adapter->netdev; 935 struct e1000_hw *hw = &adapter->hw; 936 int i, err = 0, vector = 0, free_vector = 0; 937 938 err = request_irq(adapter->msix_entries[vector].vector, 939 igb_msix_other, 0, netdev->name, adapter); 940 if (err) 941 goto err_out; 942 943 for (i = 0; i < adapter->num_q_vectors; i++) { 944 struct igb_q_vector *q_vector = adapter->q_vector[i]; 945 946 vector++; 947 948 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 949 950 if (q_vector->rx.ring && q_vector->tx.ring) 951 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 952 q_vector->rx.ring->queue_index); 953 else if (q_vector->tx.ring) 954 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 955 q_vector->tx.ring->queue_index); 956 else if (q_vector->rx.ring) 957 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 958 q_vector->rx.ring->queue_index); 959 else 960 sprintf(q_vector->name, "%s-unused", netdev->name); 961 962 err = request_irq(adapter->msix_entries[vector].vector, 963 igb_msix_ring, 0, q_vector->name, 964 q_vector); 965 if (err) 966 goto err_free; 967 } 968 969 igb_configure_msix(adapter); 970 return 0; 971 972err_free: 973 /* free already assigned IRQs */ 974 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 975 976 vector--; 977 for (i = 0; i < vector; i++) { 978 free_irq(adapter->msix_entries[free_vector++].vector, 979 adapter->q_vector[i]); 980 } 981err_out: 982 return err; 983} 984 985/** 986 * igb_free_q_vector - Free memory allocated for specific interrupt vector 987 * @adapter: board private structure to initialize 988 * @v_idx: Index of vector to be freed 989 * 990 * This function frees the memory allocated to the q_vector. 991 **/ 992static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 993{ 994 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 995 996 adapter->q_vector[v_idx] = NULL; 997 998 /* igb_get_stats64() might access the rings on this vector, 999 * we must wait a grace period before freeing it. 1000 */ 1001 kfree_rcu(q_vector, rcu); 1002} 1003 1004/** 1005 * igb_reset_q_vector - Reset config for interrupt vector 1006 * @adapter: board private structure to initialize 1007 * @v_idx: Index of vector to be reset 1008 * 1009 * If NAPI is enabled it will delete any references to the 1010 * NAPI struct. This is preparation for igb_free_q_vector. 1011 **/ 1012static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1013{ 1014 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1015 1016 if (q_vector->tx.ring) 1017 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1018 1019 if (q_vector->rx.ring) 1020 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; 1021 1022 netif_napi_del(&q_vector->napi); 1023 1024} 1025 1026static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1027{ 1028 int v_idx = adapter->num_q_vectors; 1029 1030 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1031 pci_disable_msix(adapter->pdev); 1032 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1033 pci_disable_msi(adapter->pdev); 1034 1035 while (v_idx--) 1036 igb_reset_q_vector(adapter, v_idx); 1037} 1038 1039/** 1040 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1041 * @adapter: board private structure to initialize 1042 * 1043 * This function frees the memory allocated to the q_vectors. In addition if 1044 * NAPI is enabled it will delete any references to the NAPI struct prior 1045 * to freeing the q_vector. 1046 **/ 1047static void igb_free_q_vectors(struct igb_adapter *adapter) 1048{ 1049 int v_idx = adapter->num_q_vectors; 1050 1051 adapter->num_tx_queues = 0; 1052 adapter->num_rx_queues = 0; 1053 adapter->num_q_vectors = 0; 1054 1055 while (v_idx--) { 1056 igb_reset_q_vector(adapter, v_idx); 1057 igb_free_q_vector(adapter, v_idx); 1058 } 1059} 1060 1061/** 1062 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1063 * @adapter: board private structure to initialize 1064 * 1065 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1066 * MSI-X interrupts allocated. 1067 */ 1068static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1069{ 1070 igb_free_q_vectors(adapter); 1071 igb_reset_interrupt_capability(adapter); 1072} 1073 1074/** 1075 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1076 * @adapter: board private structure to initialize 1077 * @msix: boolean value of MSIX capability 1078 * 1079 * Attempt to configure interrupts using the best available 1080 * capabilities of the hardware and kernel. 1081 **/ 1082static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1083{ 1084 int err; 1085 int numvecs, i; 1086 1087 if (!msix) 1088 goto msi_only; 1089 adapter->flags |= IGB_FLAG_HAS_MSIX; 1090 1091 /* Number of supported queues. */ 1092 adapter->num_rx_queues = adapter->rss_queues; 1093 if (adapter->vfs_allocated_count) 1094 adapter->num_tx_queues = 1; 1095 else 1096 adapter->num_tx_queues = adapter->rss_queues; 1097 1098 /* start with one vector for every Rx queue */ 1099 numvecs = adapter->num_rx_queues; 1100 1101 /* if Tx handler is separate add 1 for every Tx queue */ 1102 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1103 numvecs += adapter->num_tx_queues; 1104 1105 /* store the number of vectors reserved for queues */ 1106 adapter->num_q_vectors = numvecs; 1107 1108 /* add 1 vector for link status interrupts */ 1109 numvecs++; 1110 for (i = 0; i < numvecs; i++) 1111 adapter->msix_entries[i].entry = i; 1112 1113 err = pci_enable_msix_range(adapter->pdev, 1114 adapter->msix_entries, 1115 numvecs, 1116 numvecs); 1117 if (err > 0) 1118 return; 1119 1120 igb_reset_interrupt_capability(adapter); 1121 1122 /* If we can't do MSI-X, try MSI */ 1123msi_only: 1124#ifdef CONFIG_PCI_IOV 1125 /* disable SR-IOV for non MSI-X configurations */ 1126 if (adapter->vf_data) { 1127 struct e1000_hw *hw = &adapter->hw; 1128 /* disable iov and allow time for transactions to clear */ 1129 pci_disable_sriov(adapter->pdev); 1130 msleep(500); 1131 1132 kfree(adapter->vf_data); 1133 adapter->vf_data = NULL; 1134 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1135 wrfl(); 1136 msleep(100); 1137 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1138 } 1139#endif 1140 adapter->vfs_allocated_count = 0; 1141 adapter->rss_queues = 1; 1142 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1143 adapter->num_rx_queues = 1; 1144 adapter->num_tx_queues = 1; 1145 adapter->num_q_vectors = 1; 1146 if (!pci_enable_msi(adapter->pdev)) 1147 adapter->flags |= IGB_FLAG_HAS_MSI; 1148} 1149 1150static void igb_add_ring(struct igb_ring *ring, 1151 struct igb_ring_container *head) 1152{ 1153 head->ring = ring; 1154 head->count++; 1155} 1156 1157/** 1158 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1159 * @adapter: board private structure to initialize 1160 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1161 * @v_idx: index of vector in adapter struct 1162 * @txr_count: total number of Tx rings to allocate 1163 * @txr_idx: index of first Tx ring to allocate 1164 * @rxr_count: total number of Rx rings to allocate 1165 * @rxr_idx: index of first Rx ring to allocate 1166 * 1167 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1168 **/ 1169static int igb_alloc_q_vector(struct igb_adapter *adapter, 1170 int v_count, int v_idx, 1171 int txr_count, int txr_idx, 1172 int rxr_count, int rxr_idx) 1173{ 1174 struct igb_q_vector *q_vector; 1175 struct igb_ring *ring; 1176 int ring_count, size; 1177 1178 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1179 if (txr_count > 1 || rxr_count > 1) 1180 return -ENOMEM; 1181 1182 ring_count = txr_count + rxr_count; 1183 size = sizeof(struct igb_q_vector) + 1184 (sizeof(struct igb_ring) * ring_count); 1185 1186 /* allocate q_vector and rings */ 1187 q_vector = adapter->q_vector[v_idx]; 1188 if (!q_vector) 1189 q_vector = kzalloc(size, GFP_KERNEL); 1190 if (!q_vector) 1191 return -ENOMEM; 1192 1193 /* initialize NAPI */ 1194 netif_napi_add(adapter->netdev, &q_vector->napi, 1195 igb_poll, 64); 1196 1197 /* tie q_vector and adapter together */ 1198 adapter->q_vector[v_idx] = q_vector; 1199 q_vector->adapter = adapter; 1200 1201 /* initialize work limits */ 1202 q_vector->tx.work_limit = adapter->tx_work_limit; 1203 1204 /* initialize ITR configuration */ 1205 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); 1206 q_vector->itr_val = IGB_START_ITR; 1207 1208 /* initialize pointer to rings */ 1209 ring = q_vector->ring; 1210 1211 /* intialize ITR */ 1212 if (rxr_count) { 1213 /* rx or rx/tx vector */ 1214 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1215 q_vector->itr_val = adapter->rx_itr_setting; 1216 } else { 1217 /* tx only vector */ 1218 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1219 q_vector->itr_val = adapter->tx_itr_setting; 1220 } 1221 1222 if (txr_count) { 1223 /* assign generic ring traits */ 1224 ring->dev = &adapter->pdev->dev; 1225 ring->netdev = adapter->netdev; 1226 1227 /* configure backlink on ring */ 1228 ring->q_vector = q_vector; 1229 1230 /* update q_vector Tx values */ 1231 igb_add_ring(ring, &q_vector->tx); 1232 1233 /* For 82575, context index must be unique per ring. */ 1234 if (adapter->hw.mac.type == e1000_82575) 1235 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1236 1237 /* apply Tx specific ring traits */ 1238 ring->count = adapter->tx_ring_count; 1239 ring->queue_index = txr_idx; 1240 1241 u64_stats_init(&ring->tx_syncp); 1242 u64_stats_init(&ring->tx_syncp2); 1243 1244 /* assign ring to adapter */ 1245 adapter->tx_ring[txr_idx] = ring; 1246 1247 /* push pointer to next ring */ 1248 ring++; 1249 } 1250 1251 if (rxr_count) { 1252 /* assign generic ring traits */ 1253 ring->dev = &adapter->pdev->dev; 1254 ring->netdev = adapter->netdev; 1255 1256 /* configure backlink on ring */ 1257 ring->q_vector = q_vector; 1258 1259 /* update q_vector Rx values */ 1260 igb_add_ring(ring, &q_vector->rx); 1261 1262 /* set flag indicating ring supports SCTP checksum offload */ 1263 if (adapter->hw.mac.type >= e1000_82576) 1264 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1265 1266 /* 1267 * On i350, i354, i210, and i211, loopback VLAN packets 1268 * have the tag byte-swapped. 1269 */ 1270 if (adapter->hw.mac.type >= e1000_i350) 1271 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1272 1273 /* apply Rx specific ring traits */ 1274 ring->count = adapter->rx_ring_count; 1275 ring->queue_index = rxr_idx; 1276 1277 u64_stats_init(&ring->rx_syncp); 1278 1279 /* assign ring to adapter */ 1280 adapter->rx_ring[rxr_idx] = ring; 1281 } 1282 1283 return 0; 1284} 1285 1286 1287/** 1288 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1289 * @adapter: board private structure to initialize 1290 * 1291 * We allocate one q_vector per queue interrupt. If allocation fails we 1292 * return -ENOMEM. 1293 **/ 1294static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1295{ 1296 int q_vectors = adapter->num_q_vectors; 1297 int rxr_remaining = adapter->num_rx_queues; 1298 int txr_remaining = adapter->num_tx_queues; 1299 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1300 int err; 1301 1302 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1303 for (; rxr_remaining; v_idx++) { 1304 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1305 0, 0, 1, rxr_idx); 1306 1307 if (err) 1308 goto err_out; 1309 1310 /* update counts and index */ 1311 rxr_remaining--; 1312 rxr_idx++; 1313 } 1314 } 1315 1316 for (; v_idx < q_vectors; v_idx++) { 1317 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1318 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1319 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1320 tqpv, txr_idx, rqpv, rxr_idx); 1321 1322 if (err) 1323 goto err_out; 1324 1325 /* update counts and index */ 1326 rxr_remaining -= rqpv; 1327 txr_remaining -= tqpv; 1328 rxr_idx++; 1329 txr_idx++; 1330 } 1331 1332 return 0; 1333 1334err_out: 1335 adapter->num_tx_queues = 0; 1336 adapter->num_rx_queues = 0; 1337 adapter->num_q_vectors = 0; 1338 1339 while (v_idx--) 1340 igb_free_q_vector(adapter, v_idx); 1341 1342 return -ENOMEM; 1343} 1344 1345/** 1346 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1347 * @adapter: board private structure to initialize 1348 * @msix: boolean value of MSIX capability 1349 * 1350 * This function initializes the interrupts and allocates all of the queues. 1351 **/ 1352static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1353{ 1354 struct pci_dev *pdev = adapter->pdev; 1355 int err; 1356 1357 igb_set_interrupt_capability(adapter, msix); 1358 1359 err = igb_alloc_q_vectors(adapter); 1360 if (err) { 1361 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1362 goto err_alloc_q_vectors; 1363 } 1364 1365 igb_cache_ring_register(adapter); 1366 1367 return 0; 1368 1369err_alloc_q_vectors: 1370 igb_reset_interrupt_capability(adapter); 1371 return err; 1372} 1373 1374/** 1375 * igb_request_irq - initialize interrupts 1376 * @adapter: board private structure to initialize 1377 * 1378 * Attempts to configure interrupts using the best available 1379 * capabilities of the hardware and kernel. 1380 **/ 1381static int igb_request_irq(struct igb_adapter *adapter) 1382{ 1383 struct net_device *netdev = adapter->netdev; 1384 struct pci_dev *pdev = adapter->pdev; 1385 int err = 0; 1386 1387 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1388 err = igb_request_msix(adapter); 1389 if (!err) 1390 goto request_done; 1391 /* fall back to MSI */ 1392 igb_free_all_tx_resources(adapter); 1393 igb_free_all_rx_resources(adapter); 1394 1395 igb_clear_interrupt_scheme(adapter); 1396 err = igb_init_interrupt_scheme(adapter, false); 1397 if (err) 1398 goto request_done; 1399 1400 igb_setup_all_tx_resources(adapter); 1401 igb_setup_all_rx_resources(adapter); 1402 igb_configure(adapter); 1403 } 1404 1405 igb_assign_vector(adapter->q_vector[0], 0); 1406 1407 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1408 err = request_irq(pdev->irq, igb_intr_msi, 0, 1409 netdev->name, adapter); 1410 if (!err) 1411 goto request_done; 1412 1413 /* fall back to legacy interrupts */ 1414 igb_reset_interrupt_capability(adapter); 1415 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1416 } 1417 1418 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1419 netdev->name, adapter); 1420 1421 if (err) 1422 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1423 err); 1424 1425request_done: 1426 return err; 1427} 1428 1429static void igb_free_irq(struct igb_adapter *adapter) 1430{ 1431 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1432 int vector = 0, i; 1433 1434 free_irq(adapter->msix_entries[vector++].vector, adapter); 1435 1436 for (i = 0; i < adapter->num_q_vectors; i++) 1437 free_irq(adapter->msix_entries[vector++].vector, 1438 adapter->q_vector[i]); 1439 } else { 1440 free_irq(adapter->pdev->irq, adapter); 1441 } 1442} 1443 1444/** 1445 * igb_irq_disable - Mask off interrupt generation on the NIC 1446 * @adapter: board private structure 1447 **/ 1448static void igb_irq_disable(struct igb_adapter *adapter) 1449{ 1450 struct e1000_hw *hw = &adapter->hw; 1451 1452 /* we need to be careful when disabling interrupts. The VFs are also 1453 * mapped into these registers and so clearing the bits can cause 1454 * issues on the VF drivers so we only need to clear what we set 1455 */ 1456 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1457 u32 regval = rd32(E1000_EIAM); 1458 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1459 wr32(E1000_EIMC, adapter->eims_enable_mask); 1460 regval = rd32(E1000_EIAC); 1461 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1462 } 1463 1464 wr32(E1000_IAM, 0); 1465 wr32(E1000_IMC, ~0); 1466 wrfl(); 1467 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1468 int i; 1469 for (i = 0; i < adapter->num_q_vectors; i++) 1470 synchronize_irq(adapter->msix_entries[i].vector); 1471 } else { 1472 synchronize_irq(adapter->pdev->irq); 1473 } 1474} 1475 1476/** 1477 * igb_irq_enable - Enable default interrupt generation settings 1478 * @adapter: board private structure 1479 **/ 1480static void igb_irq_enable(struct igb_adapter *adapter) 1481{ 1482 struct e1000_hw *hw = &adapter->hw; 1483 1484 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1485 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1486 u32 regval = rd32(E1000_EIAC); 1487 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1488 regval = rd32(E1000_EIAM); 1489 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1490 wr32(E1000_EIMS, adapter->eims_enable_mask); 1491 if (adapter->vfs_allocated_count) { 1492 wr32(E1000_MBVFIMR, 0xFF); 1493 ims |= E1000_IMS_VMMB; 1494 } 1495 wr32(E1000_IMS, ims); 1496 } else { 1497 wr32(E1000_IMS, IMS_ENABLE_MASK | 1498 E1000_IMS_DRSTA); 1499 wr32(E1000_IAM, IMS_ENABLE_MASK | 1500 E1000_IMS_DRSTA); 1501 } 1502} 1503 1504static void igb_update_mng_vlan(struct igb_adapter *adapter) 1505{ 1506 struct e1000_hw *hw = &adapter->hw; 1507 u16 vid = adapter->hw.mng_cookie.vlan_id; 1508 u16 old_vid = adapter->mng_vlan_id; 1509 1510 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1511 /* add VID to filter table */ 1512 igb_vfta_set(hw, vid, true); 1513 adapter->mng_vlan_id = vid; 1514 } else { 1515 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1516 } 1517 1518 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1519 (vid != old_vid) && 1520 !test_bit(old_vid, adapter->active_vlans)) { 1521 /* remove VID from filter table */ 1522 igb_vfta_set(hw, old_vid, false); 1523 } 1524} 1525 1526/** 1527 * igb_release_hw_control - release control of the h/w to f/w 1528 * @adapter: address of board private structure 1529 * 1530 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1531 * For ASF and Pass Through versions of f/w this means that the 1532 * driver is no longer loaded. 1533 **/ 1534static void igb_release_hw_control(struct igb_adapter *adapter) 1535{ 1536 struct e1000_hw *hw = &adapter->hw; 1537 u32 ctrl_ext; 1538 1539 /* Let firmware take over control of h/w */ 1540 ctrl_ext = rd32(E1000_CTRL_EXT); 1541 wr32(E1000_CTRL_EXT, 1542 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1543} 1544 1545/** 1546 * igb_get_hw_control - get control of the h/w from f/w 1547 * @adapter: address of board private structure 1548 * 1549 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1550 * For ASF and Pass Through versions of f/w this means that 1551 * the driver is loaded. 1552 **/ 1553static void igb_get_hw_control(struct igb_adapter *adapter) 1554{ 1555 struct e1000_hw *hw = &adapter->hw; 1556 u32 ctrl_ext; 1557 1558 /* Let firmware know the driver has taken over */ 1559 ctrl_ext = rd32(E1000_CTRL_EXT); 1560 wr32(E1000_CTRL_EXT, 1561 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1562} 1563 1564/** 1565 * igb_configure - configure the hardware for RX and TX 1566 * @adapter: private board structure 1567 **/ 1568static void igb_configure(struct igb_adapter *adapter) 1569{ 1570 struct net_device *netdev = adapter->netdev; 1571 int i; 1572 1573 igb_get_hw_control(adapter); 1574 igb_set_rx_mode(netdev); 1575 1576 igb_restore_vlan(adapter); 1577 1578 igb_setup_tctl(adapter); 1579 igb_setup_mrqc(adapter); 1580 igb_setup_rctl(adapter); 1581 1582 igb_configure_tx(adapter); 1583 igb_configure_rx(adapter); 1584 1585 igb_rx_fifo_flush_82575(&adapter->hw); 1586 1587 /* call igb_desc_unused which always leaves 1588 * at least 1 descriptor unused to make sure 1589 * next_to_use != next_to_clean 1590 */ 1591 for (i = 0; i < adapter->num_rx_queues; i++) { 1592 struct igb_ring *ring = adapter->rx_ring[i]; 1593 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1594 } 1595} 1596 1597/** 1598 * igb_power_up_link - Power up the phy/serdes link 1599 * @adapter: address of board private structure 1600 **/ 1601void igb_power_up_link(struct igb_adapter *adapter) 1602{ 1603 igb_reset_phy(&adapter->hw); 1604 1605 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1606 igb_power_up_phy_copper(&adapter->hw); 1607 else 1608 igb_power_up_serdes_link_82575(&adapter->hw); 1609} 1610 1611/** 1612 * igb_power_down_link - Power down the phy/serdes link 1613 * @adapter: address of board private structure 1614 */ 1615static void igb_power_down_link(struct igb_adapter *adapter) 1616{ 1617 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1618 igb_power_down_phy_copper_82575(&adapter->hw); 1619 else 1620 igb_shutdown_serdes_link_82575(&adapter->hw); 1621} 1622 1623/** 1624 * Detect and switch function for Media Auto Sense 1625 * @adapter: address of the board private structure 1626 **/ 1627static void igb_check_swap_media(struct igb_adapter *adapter) 1628{ 1629 struct e1000_hw *hw = &adapter->hw; 1630 u32 ctrl_ext, connsw; 1631 bool swap_now = false; 1632 1633 ctrl_ext = rd32(E1000_CTRL_EXT); 1634 connsw = rd32(E1000_CONNSW); 1635 1636 /* need to live swap if current media is copper and we have fiber/serdes 1637 * to go to. 1638 */ 1639 1640 if ((hw->phy.media_type == e1000_media_type_copper) && 1641 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1642 swap_now = true; 1643 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1644 /* copper signal takes time to appear */ 1645 if (adapter->copper_tries < 4) { 1646 adapter->copper_tries++; 1647 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1648 wr32(E1000_CONNSW, connsw); 1649 return; 1650 } else { 1651 adapter->copper_tries = 0; 1652 if ((connsw & E1000_CONNSW_PHYSD) && 1653 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1654 swap_now = true; 1655 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1656 wr32(E1000_CONNSW, connsw); 1657 } 1658 } 1659 } 1660 1661 if (!swap_now) 1662 return; 1663 1664 switch (hw->phy.media_type) { 1665 case e1000_media_type_copper: 1666 netdev_info(adapter->netdev, 1667 "MAS: changing media to fiber/serdes\n"); 1668 ctrl_ext |= 1669 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1670 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1671 adapter->copper_tries = 0; 1672 break; 1673 case e1000_media_type_internal_serdes: 1674 case e1000_media_type_fiber: 1675 netdev_info(adapter->netdev, 1676 "MAS: changing media to copper\n"); 1677 ctrl_ext &= 1678 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1679 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1680 break; 1681 default: 1682 /* shouldn't get here during regular operation */ 1683 netdev_err(adapter->netdev, 1684 "AMS: Invalid media type found, returning\n"); 1685 break; 1686 } 1687 wr32(E1000_CTRL_EXT, ctrl_ext); 1688} 1689 1690/** 1691 * igb_up - Open the interface and prepare it to handle traffic 1692 * @adapter: board private structure 1693 **/ 1694int igb_up(struct igb_adapter *adapter) 1695{ 1696 struct e1000_hw *hw = &adapter->hw; 1697 int i; 1698 1699 /* hardware has been reset, we need to reload some things */ 1700 igb_configure(adapter); 1701 1702 clear_bit(__IGB_DOWN, &adapter->state); 1703 1704 for (i = 0; i < adapter->num_q_vectors; i++) 1705 napi_enable(&(adapter->q_vector[i]->napi)); 1706 1707 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1708 igb_configure_msix(adapter); 1709 else 1710 igb_assign_vector(adapter->q_vector[0], 0); 1711 1712 /* Clear any pending interrupts. */ 1713 rd32(E1000_ICR); 1714 igb_irq_enable(adapter); 1715 1716 /* notify VFs that reset has been completed */ 1717 if (adapter->vfs_allocated_count) { 1718 u32 reg_data = rd32(E1000_CTRL_EXT); 1719 reg_data |= E1000_CTRL_EXT_PFRSTD; 1720 wr32(E1000_CTRL_EXT, reg_data); 1721 } 1722 1723 netif_tx_start_all_queues(adapter->netdev); 1724 1725 /* start the watchdog. */ 1726 hw->mac.get_link_status = 1; 1727 schedule_work(&adapter->watchdog_task); 1728 1729 return 0; 1730} 1731 1732void igb_down(struct igb_adapter *adapter) 1733{ 1734 struct net_device *netdev = adapter->netdev; 1735 struct e1000_hw *hw = &adapter->hw; 1736 u32 tctl, rctl; 1737 int i; 1738 1739 /* signal that we're down so the interrupt handler does not 1740 * reschedule our watchdog timer 1741 */ 1742 set_bit(__IGB_DOWN, &adapter->state); 1743 1744 /* disable receives in the hardware */ 1745 rctl = rd32(E1000_RCTL); 1746 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1747 /* flush and sleep below */ 1748 1749 netif_tx_stop_all_queues(netdev); 1750 1751 /* disable transmits in the hardware */ 1752 tctl = rd32(E1000_TCTL); 1753 tctl &= ~E1000_TCTL_EN; 1754 wr32(E1000_TCTL, tctl); 1755 /* flush both disables and wait for them to finish */ 1756 wrfl(); 1757 msleep(10); 1758 1759 igb_irq_disable(adapter); 1760 1761 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1762 1763 for (i = 0; i < adapter->num_q_vectors; i++) { 1764 napi_synchronize(&(adapter->q_vector[i]->napi)); 1765 napi_disable(&(adapter->q_vector[i]->napi)); 1766 } 1767 1768 1769 del_timer_sync(&adapter->watchdog_timer); 1770 del_timer_sync(&adapter->phy_info_timer); 1771 1772 netif_carrier_off(netdev); 1773 1774 /* record the stats before reset*/ 1775 spin_lock(&adapter->stats64_lock); 1776 igb_update_stats(adapter, &adapter->stats64); 1777 spin_unlock(&adapter->stats64_lock); 1778 1779 adapter->link_speed = 0; 1780 adapter->link_duplex = 0; 1781 1782 if (!pci_channel_offline(adapter->pdev)) 1783 igb_reset(adapter); 1784 igb_clean_all_tx_rings(adapter); 1785 igb_clean_all_rx_rings(adapter); 1786#ifdef CONFIG_IGB_DCA 1787 1788 /* since we reset the hardware DCA settings were cleared */ 1789 igb_setup_dca(adapter); 1790#endif 1791} 1792 1793void igb_reinit_locked(struct igb_adapter *adapter) 1794{ 1795 WARN_ON(in_interrupt()); 1796 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1797 msleep(1); 1798 igb_down(adapter); 1799 igb_up(adapter); 1800 clear_bit(__IGB_RESETTING, &adapter->state); 1801} 1802 1803/** igb_enable_mas - Media Autosense re-enable after swap 1804 * 1805 * @adapter: adapter struct 1806 **/ 1807static s32 igb_enable_mas(struct igb_adapter *adapter) 1808{ 1809 struct e1000_hw *hw = &adapter->hw; 1810 u32 connsw; 1811 s32 ret_val = 0; 1812 1813 connsw = rd32(E1000_CONNSW); 1814 if (!(hw->phy.media_type == e1000_media_type_copper)) 1815 return ret_val; 1816 1817 /* configure for SerDes media detect */ 1818 if (!(connsw & E1000_CONNSW_SERDESD)) { 1819 connsw |= E1000_CONNSW_ENRGSRC; 1820 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1821 wr32(E1000_CONNSW, connsw); 1822 wrfl(); 1823 } else if (connsw & E1000_CONNSW_SERDESD) { 1824 /* already SerDes, no need to enable anything */ 1825 return ret_val; 1826 } else { 1827 netdev_info(adapter->netdev, 1828 "MAS: Unable to configure feature, disabling..\n"); 1829 adapter->flags &= ~IGB_FLAG_MAS_ENABLE; 1830 } 1831 return ret_val; 1832} 1833 1834void igb_reset(struct igb_adapter *adapter) 1835{ 1836 struct pci_dev *pdev = adapter->pdev; 1837 struct e1000_hw *hw = &adapter->hw; 1838 struct e1000_mac_info *mac = &hw->mac; 1839 struct e1000_fc_info *fc = &hw->fc; 1840 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; 1841 1842 /* Repartition Pba for greater than 9k mtu 1843 * To take effect CTRL.RST is required. 1844 */ 1845 switch (mac->type) { 1846 case e1000_i350: 1847 case e1000_i354: 1848 case e1000_82580: 1849 pba = rd32(E1000_RXPBS); 1850 pba = igb_rxpbs_adjust_82580(pba); 1851 break; 1852 case e1000_82576: 1853 pba = rd32(E1000_RXPBS); 1854 pba &= E1000_RXPBS_SIZE_MASK_82576; 1855 break; 1856 case e1000_82575: 1857 case e1000_i210: 1858 case e1000_i211: 1859 default: 1860 pba = E1000_PBA_34K; 1861 break; 1862 } 1863 1864 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1865 (mac->type < e1000_82576)) { 1866 /* adjust PBA for jumbo frames */ 1867 wr32(E1000_PBA, pba); 1868 1869 /* To maintain wire speed transmits, the Tx FIFO should be 1870 * large enough to accommodate two full transmit packets, 1871 * rounded up to the next 1KB and expressed in KB. Likewise, 1872 * the Rx FIFO should be large enough to accommodate at least 1873 * one full receive packet and is similarly rounded up and 1874 * expressed in KB. 1875 */ 1876 pba = rd32(E1000_PBA); 1877 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1878 tx_space = pba >> 16; 1879 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1880 pba &= 0xffff; 1881 /* the Tx fifo also stores 16 bytes of information about the Tx 1882 * but don't include ethernet FCS because hardware appends it 1883 */ 1884 min_tx_space = (adapter->max_frame_size + 1885 sizeof(union e1000_adv_tx_desc) - 1886 ETH_FCS_LEN) * 2; 1887 min_tx_space = ALIGN(min_tx_space, 1024); 1888 min_tx_space >>= 10; 1889 /* software strips receive CRC, so leave room for it */ 1890 min_rx_space = adapter->max_frame_size; 1891 min_rx_space = ALIGN(min_rx_space, 1024); 1892 min_rx_space >>= 10; 1893 1894 /* If current Tx allocation is less than the min Tx FIFO size, 1895 * and the min Tx FIFO size is less than the current Rx FIFO 1896 * allocation, take space away from current Rx allocation 1897 */ 1898 if (tx_space < min_tx_space && 1899 ((min_tx_space - tx_space) < pba)) { 1900 pba = pba - (min_tx_space - tx_space); 1901 1902 /* if short on Rx space, Rx wins and must trump Tx 1903 * adjustment 1904 */ 1905 if (pba < min_rx_space) 1906 pba = min_rx_space; 1907 } 1908 wr32(E1000_PBA, pba); 1909 } 1910 1911 /* flow control settings */ 1912 /* The high water mark must be low enough to fit one full frame 1913 * (or the size used for early receive) above it in the Rx FIFO. 1914 * Set it to the lower of: 1915 * - 90% of the Rx FIFO size, or 1916 * - the full Rx FIFO size minus one full frame 1917 */ 1918 hwm = min(((pba << 10) * 9 / 10), 1919 ((pba << 10) - 2 * adapter->max_frame_size)); 1920 1921 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1922 fc->low_water = fc->high_water - 16; 1923 fc->pause_time = 0xFFFF; 1924 fc->send_xon = 1; 1925 fc->current_mode = fc->requested_mode; 1926 1927 /* disable receive for all VFs and wait one second */ 1928 if (adapter->vfs_allocated_count) { 1929 int i; 1930 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1931 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1932 1933 /* ping all the active vfs to let them know we are going down */ 1934 igb_ping_all_vfs(adapter); 1935 1936 /* disable transmits and receives */ 1937 wr32(E1000_VFRE, 0); 1938 wr32(E1000_VFTE, 0); 1939 } 1940 1941 /* Allow time for pending master requests to run */ 1942 hw->mac.ops.reset_hw(hw); 1943 wr32(E1000_WUC, 0); 1944 1945 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1946 /* need to resetup here after media swap */ 1947 adapter->ei.get_invariants(hw); 1948 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1949 } 1950 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 1951 if (igb_enable_mas(adapter)) 1952 dev_err(&pdev->dev, 1953 "Error enabling Media Auto Sense\n"); 1954 } 1955 if (hw->mac.ops.init_hw(hw)) 1956 dev_err(&pdev->dev, "Hardware Error\n"); 1957 1958 /* Flow control settings reset on hardware reset, so guarantee flow 1959 * control is off when forcing speed. 1960 */ 1961 if (!hw->mac.autoneg) 1962 igb_force_mac_fc(hw); 1963 1964 igb_init_dmac(adapter, pba); 1965#ifdef CONFIG_IGB_HWMON 1966 /* Re-initialize the thermal sensor on i350 devices. */ 1967 if (!test_bit(__IGB_DOWN, &adapter->state)) { 1968 if (mac->type == e1000_i350 && hw->bus.func == 0) { 1969 /* If present, re-initialize the external thermal sensor 1970 * interface. 1971 */ 1972 if (adapter->ets) 1973 mac->ops.init_thermal_sensor_thresh(hw); 1974 } 1975 } 1976#endif 1977 if (!netif_running(adapter->netdev)) 1978 igb_power_down_link(adapter); 1979 1980 igb_update_mng_vlan(adapter); 1981 1982 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 1983 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 1984 1985 /* Re-enable PTP, where applicable. */ 1986 igb_ptp_reset(adapter); 1987 1988 igb_get_phy_info(hw); 1989} 1990 1991static netdev_features_t igb_fix_features(struct net_device *netdev, 1992 netdev_features_t features) 1993{ 1994 /* Since there is no support for separate Rx/Tx vlan accel 1995 * enable/disable make sure Tx flag is always in same state as Rx. 1996 */ 1997 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1998 features |= NETIF_F_HW_VLAN_CTAG_TX; 1999 else 2000 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2001 2002 return features; 2003} 2004 2005static int igb_set_features(struct net_device *netdev, 2006 netdev_features_t features) 2007{ 2008 netdev_features_t changed = netdev->features ^ features; 2009 struct igb_adapter *adapter = netdev_priv(netdev); 2010 2011 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2012 igb_vlan_mode(netdev, features); 2013 2014 if (!(changed & NETIF_F_RXALL)) 2015 return 0; 2016 2017 netdev->features = features; 2018 2019 if (netif_running(netdev)) 2020 igb_reinit_locked(adapter); 2021 else 2022 igb_reset(adapter); 2023 2024 return 0; 2025} 2026 2027static const struct net_device_ops igb_netdev_ops = { 2028 .ndo_open = igb_open, 2029 .ndo_stop = igb_close, 2030 .ndo_start_xmit = igb_xmit_frame, 2031 .ndo_get_stats64 = igb_get_stats64, 2032 .ndo_set_rx_mode = igb_set_rx_mode, 2033 .ndo_set_mac_address = igb_set_mac, 2034 .ndo_change_mtu = igb_change_mtu, 2035 .ndo_do_ioctl = igb_ioctl, 2036 .ndo_tx_timeout = igb_tx_timeout, 2037 .ndo_validate_addr = eth_validate_addr, 2038 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2039 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2040 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2041 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2042 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, 2043 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2044 .ndo_get_vf_config = igb_ndo_get_vf_config, 2045#ifdef CONFIG_NET_POLL_CONTROLLER 2046 .ndo_poll_controller = igb_netpoll, 2047#endif 2048 .ndo_fix_features = igb_fix_features, 2049 .ndo_set_features = igb_set_features, 2050}; 2051 2052/** 2053 * igb_set_fw_version - Configure version string for ethtool 2054 * @adapter: adapter struct 2055 **/ 2056void igb_set_fw_version(struct igb_adapter *adapter) 2057{ 2058 struct e1000_hw *hw = &adapter->hw; 2059 struct e1000_fw_version fw; 2060 2061 igb_get_fw_version(hw, &fw); 2062 2063 switch (hw->mac.type) { 2064 case e1000_i210: 2065 case e1000_i211: 2066 if (!(igb_get_flash_presence_i210(hw))) { 2067 snprintf(adapter->fw_version, 2068 sizeof(adapter->fw_version), 2069 "%2d.%2d-%d", 2070 fw.invm_major, fw.invm_minor, 2071 fw.invm_img_type); 2072 break; 2073 } 2074 /* fall through */ 2075 default: 2076 /* if option is rom valid, display its version too */ 2077 if (fw.or_valid) { 2078 snprintf(adapter->fw_version, 2079 sizeof(adapter->fw_version), 2080 "%d.%d, 0x%08x, %d.%d.%d", 2081 fw.eep_major, fw.eep_minor, fw.etrack_id, 2082 fw.or_major, fw.or_build, fw.or_patch); 2083 /* no option rom */ 2084 } else if (fw.etrack_id != 0X0000) { 2085 snprintf(adapter->fw_version, 2086 sizeof(adapter->fw_version), 2087 "%d.%d, 0x%08x", 2088 fw.eep_major, fw.eep_minor, fw.etrack_id); 2089 } else { 2090 snprintf(adapter->fw_version, 2091 sizeof(adapter->fw_version), 2092 "%d.%d.%d", 2093 fw.eep_major, fw.eep_minor, fw.eep_build); 2094 } 2095 break; 2096 } 2097 return; 2098} 2099 2100/** 2101 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2102 * 2103 * @adapter: adapter struct 2104 **/ 2105static void igb_init_mas(struct igb_adapter *adapter) 2106{ 2107 struct e1000_hw *hw = &adapter->hw; 2108 u16 eeprom_data; 2109 2110 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2111 switch (hw->bus.func) { 2112 case E1000_FUNC_0: 2113 if (eeprom_data & IGB_MAS_ENABLE_0) { 2114 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2115 netdev_info(adapter->netdev, 2116 "MAS: Enabling Media Autosense for port %d\n", 2117 hw->bus.func); 2118 } 2119 break; 2120 case E1000_FUNC_1: 2121 if (eeprom_data & IGB_MAS_ENABLE_1) { 2122 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2123 netdev_info(adapter->netdev, 2124 "MAS: Enabling Media Autosense for port %d\n", 2125 hw->bus.func); 2126 } 2127 break; 2128 case E1000_FUNC_2: 2129 if (eeprom_data & IGB_MAS_ENABLE_2) { 2130 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2131 netdev_info(adapter->netdev, 2132 "MAS: Enabling Media Autosense for port %d\n", 2133 hw->bus.func); 2134 } 2135 break; 2136 case E1000_FUNC_3: 2137 if (eeprom_data & IGB_MAS_ENABLE_3) { 2138 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2139 netdev_info(adapter->netdev, 2140 "MAS: Enabling Media Autosense for port %d\n", 2141 hw->bus.func); 2142 } 2143 break; 2144 default: 2145 /* Shouldn't get here */ 2146 netdev_err(adapter->netdev, 2147 "MAS: Invalid port configuration, returning\n"); 2148 break; 2149 } 2150} 2151 2152/** 2153 * igb_init_i2c - Init I2C interface 2154 * @adapter: pointer to adapter structure 2155 **/ 2156static s32 igb_init_i2c(struct igb_adapter *adapter) 2157{ 2158 s32 status = E1000_SUCCESS; 2159 2160 /* I2C interface supported on i350 devices */ 2161 if (adapter->hw.mac.type != e1000_i350) 2162 return E1000_SUCCESS; 2163 2164 /* Initialize the i2c bus which is controlled by the registers. 2165 * This bus will use the i2c_algo_bit structue that implements 2166 * the protocol through toggling of the 4 bits in the register. 2167 */ 2168 adapter->i2c_adap.owner = THIS_MODULE; 2169 adapter->i2c_algo = igb_i2c_algo; 2170 adapter->i2c_algo.data = adapter; 2171 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2172 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2173 strlcpy(adapter->i2c_adap.name, "igb BB", 2174 sizeof(adapter->i2c_adap.name)); 2175 status = i2c_bit_add_bus(&adapter->i2c_adap); 2176 return status; 2177} 2178 2179/** 2180 * igb_probe - Device Initialization Routine 2181 * @pdev: PCI device information struct 2182 * @ent: entry in igb_pci_tbl 2183 * 2184 * Returns 0 on success, negative on failure 2185 * 2186 * igb_probe initializes an adapter identified by a pci_dev structure. 2187 * The OS initialization, configuring of the adapter private structure, 2188 * and a hardware reset occur. 2189 **/ 2190static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2191{ 2192 struct net_device *netdev; 2193 struct igb_adapter *adapter; 2194 struct e1000_hw *hw; 2195 u16 eeprom_data = 0; 2196 s32 ret_val; 2197 static int global_quad_port_a; /* global quad port a indication */ 2198 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2199 int err, pci_using_dac; 2200 u8 part_str[E1000_PBANUM_LENGTH]; 2201 2202 /* Catch broken hardware that put the wrong VF device ID in 2203 * the PCIe SR-IOV capability. 2204 */ 2205 if (pdev->is_virtfn) { 2206 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2207 pci_name(pdev), pdev->vendor, pdev->device); 2208 return -EINVAL; 2209 } 2210 2211 err = pci_enable_device_mem(pdev); 2212 if (err) 2213 return err; 2214 2215 pci_using_dac = 0; 2216 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2217 if (!err) { 2218 pci_using_dac = 1; 2219 } else { 2220 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2221 if (err) { 2222 dev_err(&pdev->dev, 2223 "No usable DMA configuration, aborting\n"); 2224 goto err_dma; 2225 } 2226 } 2227 2228 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 2229 IORESOURCE_MEM), 2230 igb_driver_name); 2231 if (err) 2232 goto err_pci_reg; 2233 2234 pci_enable_pcie_error_reporting(pdev); 2235 2236 pci_set_master(pdev); 2237 pci_save_state(pdev); 2238 2239 err = -ENOMEM; 2240 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2241 IGB_MAX_TX_QUEUES); 2242 if (!netdev) 2243 goto err_alloc_etherdev; 2244 2245 SET_NETDEV_DEV(netdev, &pdev->dev); 2246 2247 pci_set_drvdata(pdev, netdev); 2248 adapter = netdev_priv(netdev); 2249 adapter->netdev = netdev; 2250 adapter->pdev = pdev; 2251 hw = &adapter->hw; 2252 hw->back = adapter; 2253 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2254 2255 err = -EIO; 2256 hw->hw_addr = pci_iomap(pdev, 0, 0); 2257 if (!hw->hw_addr) 2258 goto err_ioremap; 2259 2260 netdev->netdev_ops = &igb_netdev_ops; 2261 igb_set_ethtool_ops(netdev); 2262 netdev->watchdog_timeo = 5 * HZ; 2263 2264 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2265 2266 netdev->mem_start = pci_resource_start(pdev, 0); 2267 netdev->mem_end = pci_resource_end(pdev, 0); 2268 2269 /* PCI config space info */ 2270 hw->vendor_id = pdev->vendor; 2271 hw->device_id = pdev->device; 2272 hw->revision_id = pdev->revision; 2273 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2274 hw->subsystem_device_id = pdev->subsystem_device; 2275 2276 /* Copy the default MAC, PHY and NVM function pointers */ 2277 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2278 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2279 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2280 /* Initialize skew-specific constants */ 2281 err = ei->get_invariants(hw); 2282 if (err) 2283 goto err_sw_init; 2284 2285 /* setup the private structure */ 2286 err = igb_sw_init(adapter); 2287 if (err) 2288 goto err_sw_init; 2289 2290 igb_get_bus_info_pcie(hw); 2291 2292 hw->phy.autoneg_wait_to_complete = false; 2293 2294 /* Copper options */ 2295 if (hw->phy.media_type == e1000_media_type_copper) { 2296 hw->phy.mdix = AUTO_ALL_MODES; 2297 hw->phy.disable_polarity_correction = false; 2298 hw->phy.ms_type = e1000_ms_hw_default; 2299 } 2300 2301 if (igb_check_reset_block(hw)) 2302 dev_info(&pdev->dev, 2303 "PHY reset is blocked due to SOL/IDER session.\n"); 2304 2305 /* features is initialized to 0 in allocation, it might have bits 2306 * set by igb_sw_init so we should use an or instead of an 2307 * assignment. 2308 */ 2309 netdev->features |= NETIF_F_SG | 2310 NETIF_F_IP_CSUM | 2311 NETIF_F_IPV6_CSUM | 2312 NETIF_F_TSO | 2313 NETIF_F_TSO6 | 2314 NETIF_F_RXHASH | 2315 NETIF_F_RXCSUM | 2316 NETIF_F_HW_VLAN_CTAG_RX | 2317 NETIF_F_HW_VLAN_CTAG_TX; 2318 2319 /* copy netdev features into list of user selectable features */ 2320 netdev->hw_features |= netdev->features; 2321 netdev->hw_features |= NETIF_F_RXALL; 2322 2323 /* set this bit last since it cannot be part of hw_features */ 2324 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2325 2326 netdev->vlan_features |= NETIF_F_TSO | 2327 NETIF_F_TSO6 | 2328 NETIF_F_IP_CSUM | 2329 NETIF_F_IPV6_CSUM | 2330 NETIF_F_SG; 2331 2332 netdev->priv_flags |= IFF_SUPP_NOFCS; 2333 2334 if (pci_using_dac) { 2335 netdev->features |= NETIF_F_HIGHDMA; 2336 netdev->vlan_features |= NETIF_F_HIGHDMA; 2337 } 2338 2339 if (hw->mac.type >= e1000_82576) { 2340 netdev->hw_features |= NETIF_F_SCTP_CSUM; 2341 netdev->features |= NETIF_F_SCTP_CSUM; 2342 } 2343 2344 netdev->priv_flags |= IFF_UNICAST_FLT; 2345 2346 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2347 2348 /* before reading the NVM, reset the controller to put the device in a 2349 * known good starting state 2350 */ 2351 hw->mac.ops.reset_hw(hw); 2352 2353 /* make sure the NVM is good , i211/i210 parts can have special NVM 2354 * that doesn't contain a checksum 2355 */ 2356 switch (hw->mac.type) { 2357 case e1000_i210: 2358 case e1000_i211: 2359 if (igb_get_flash_presence_i210(hw)) { 2360 if (hw->nvm.ops.validate(hw) < 0) { 2361 dev_err(&pdev->dev, 2362 "The NVM Checksum Is Not Valid\n"); 2363 err = -EIO; 2364 goto err_eeprom; 2365 } 2366 } 2367 break; 2368 default: 2369 if (hw->nvm.ops.validate(hw) < 0) { 2370 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2371 err = -EIO; 2372 goto err_eeprom; 2373 } 2374 break; 2375 } 2376 2377 /* copy the MAC address out of the NVM */ 2378 if (hw->mac.ops.read_mac_addr(hw)) 2379 dev_err(&pdev->dev, "NVM Read Error\n"); 2380 2381 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2382 2383 if (!is_valid_ether_addr(netdev->dev_addr)) { 2384 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2385 err = -EIO; 2386 goto err_eeprom; 2387 } 2388 2389 /* get firmware version for ethtool -i */ 2390 igb_set_fw_version(adapter); 2391 2392 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2393 (unsigned long) adapter); 2394 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2395 (unsigned long) adapter); 2396 2397 INIT_WORK(&adapter->reset_task, igb_reset_task); 2398 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2399 2400 /* Initialize link properties that are user-changeable */ 2401 adapter->fc_autoneg = true; 2402 hw->mac.autoneg = true; 2403 hw->phy.autoneg_advertised = 0x2f; 2404 2405 hw->fc.requested_mode = e1000_fc_default; 2406 hw->fc.current_mode = e1000_fc_default; 2407 2408 igb_validate_mdi_setting(hw); 2409 2410 /* By default, support wake on port A */ 2411 if (hw->bus.func == 0) 2412 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2413 2414 /* Check the NVM for wake support on non-port A ports */ 2415 if (hw->mac.type >= e1000_82580) 2416 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2417 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2418 &eeprom_data); 2419 else if (hw->bus.func == 1) 2420 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2421 2422 if (eeprom_data & IGB_EEPROM_APME) 2423 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2424 2425 /* now that we have the eeprom settings, apply the special cases where 2426 * the eeprom may be wrong or the board simply won't support wake on 2427 * lan on a particular port 2428 */ 2429 switch (pdev->device) { 2430 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2431 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2432 break; 2433 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2434 case E1000_DEV_ID_82576_FIBER: 2435 case E1000_DEV_ID_82576_SERDES: 2436 /* Wake events only supported on port A for dual fiber 2437 * regardless of eeprom setting 2438 */ 2439 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2440 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2441 break; 2442 case E1000_DEV_ID_82576_QUAD_COPPER: 2443 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2444 /* if quad port adapter, disable WoL on all but port A */ 2445 if (global_quad_port_a != 0) 2446 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2447 else 2448 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2449 /* Reset for multiple quad port adapters */ 2450 if (++global_quad_port_a == 4) 2451 global_quad_port_a = 0; 2452 break; 2453 default: 2454 /* If the device can't wake, don't set software support */ 2455 if (!device_can_wakeup(&adapter->pdev->dev)) 2456 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2457 } 2458 2459 /* initialize the wol settings based on the eeprom settings */ 2460 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2461 adapter->wol |= E1000_WUFC_MAG; 2462 2463 /* Some vendors want WoL disabled by default, but still supported */ 2464 if ((hw->mac.type == e1000_i350) && 2465 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2466 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2467 adapter->wol = 0; 2468 } 2469 2470 device_set_wakeup_enable(&adapter->pdev->dev, 2471 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2472 2473 /* reset the hardware with the new settings */ 2474 igb_reset(adapter); 2475 2476 /* Init the I2C interface */ 2477 err = igb_init_i2c(adapter); 2478 if (err) { 2479 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2480 goto err_eeprom; 2481 } 2482 2483 /* let the f/w know that the h/w is now under the control of the 2484 * driver. */ 2485 igb_get_hw_control(adapter); 2486 2487 strcpy(netdev->name, "eth%d"); 2488 err = register_netdev(netdev); 2489 if (err) 2490 goto err_register; 2491 2492 /* carrier off reporting is important to ethtool even BEFORE open */ 2493 netif_carrier_off(netdev); 2494 2495#ifdef CONFIG_IGB_DCA 2496 if (dca_add_requester(&pdev->dev) == 0) { 2497 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2498 dev_info(&pdev->dev, "DCA enabled\n"); 2499 igb_setup_dca(adapter); 2500 } 2501 2502#endif 2503#ifdef CONFIG_IGB_HWMON 2504 /* Initialize the thermal sensor on i350 devices. */ 2505 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2506 u16 ets_word; 2507 2508 /* Read the NVM to determine if this i350 device supports an 2509 * external thermal sensor. 2510 */ 2511 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2512 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2513 adapter->ets = true; 2514 else 2515 adapter->ets = false; 2516 if (igb_sysfs_init(adapter)) 2517 dev_err(&pdev->dev, 2518 "failed to allocate sysfs resources\n"); 2519 } else { 2520 adapter->ets = false; 2521 } 2522#endif 2523 /* Check if Media Autosense is enabled */ 2524 adapter->ei = *ei; 2525 if (hw->dev_spec._82575.mas_capable) 2526 igb_init_mas(adapter); 2527 2528 /* do hw tstamp init after resetting */ 2529 igb_ptp_init(adapter); 2530 2531 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2532 /* print bus type/speed/width info, not applicable to i354 */ 2533 if (hw->mac.type != e1000_i354) { 2534 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2535 netdev->name, 2536 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2537 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2538 "unknown"), 2539 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2540 "Width x4" : 2541 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2542 "Width x2" : 2543 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2544 "Width x1" : "unknown"), netdev->dev_addr); 2545 } 2546 2547 if ((hw->mac.type >= e1000_i210 || 2548 igb_get_flash_presence_i210(hw))) { 2549 ret_val = igb_read_part_string(hw, part_str, 2550 E1000_PBANUM_LENGTH); 2551 } else { 2552 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2553 } 2554 2555 if (ret_val) 2556 strcpy(part_str, "Unknown"); 2557 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2558 dev_info(&pdev->dev, 2559 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2560 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2561 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2562 adapter->num_rx_queues, adapter->num_tx_queues); 2563 switch (hw->mac.type) { 2564 case e1000_i350: 2565 case e1000_i210: 2566 case e1000_i211: 2567 igb_set_eee_i350(hw); 2568 break; 2569 case e1000_i354: 2570 if (hw->phy.media_type == e1000_media_type_copper) { 2571 if ((rd32(E1000_CTRL_EXT) & 2572 E1000_CTRL_EXT_LINK_MODE_SGMII)) 2573 igb_set_eee_i354(hw); 2574 } 2575 break; 2576 default: 2577 break; 2578 } 2579 2580 pm_runtime_put_noidle(&pdev->dev); 2581 return 0; 2582 2583err_register: 2584 igb_release_hw_control(adapter); 2585 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2586err_eeprom: 2587 if (!igb_check_reset_block(hw)) 2588 igb_reset_phy(hw); 2589 2590 if (hw->flash_address) 2591 iounmap(hw->flash_address); 2592err_sw_init: 2593 igb_clear_interrupt_scheme(adapter); 2594 iounmap(hw->hw_addr); 2595err_ioremap: 2596 free_netdev(netdev); 2597err_alloc_etherdev: 2598 pci_release_selected_regions(pdev, 2599 pci_select_bars(pdev, IORESOURCE_MEM)); 2600err_pci_reg: 2601err_dma: 2602 pci_disable_device(pdev); 2603 return err; 2604} 2605 2606#ifdef CONFIG_PCI_IOV 2607static int igb_disable_sriov(struct pci_dev *pdev) 2608{ 2609 struct net_device *netdev = pci_get_drvdata(pdev); 2610 struct igb_adapter *adapter = netdev_priv(netdev); 2611 struct e1000_hw *hw = &adapter->hw; 2612 2613 /* reclaim resources allocated to VFs */ 2614 if (adapter->vf_data) { 2615 /* disable iov and allow time for transactions to clear */ 2616 if (pci_vfs_assigned(pdev)) { 2617 dev_warn(&pdev->dev, 2618 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2619 return -EPERM; 2620 } else { 2621 pci_disable_sriov(pdev); 2622 msleep(500); 2623 } 2624 2625 kfree(adapter->vf_data); 2626 adapter->vf_data = NULL; 2627 adapter->vfs_allocated_count = 0; 2628 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2629 wrfl(); 2630 msleep(100); 2631 dev_info(&pdev->dev, "IOV Disabled\n"); 2632 2633 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2634 adapter->flags |= IGB_FLAG_DMAC; 2635 } 2636 2637 return 0; 2638} 2639 2640static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2641{ 2642 struct net_device *netdev = pci_get_drvdata(pdev); 2643 struct igb_adapter *adapter = netdev_priv(netdev); 2644 int old_vfs = pci_num_vf(pdev); 2645 int err = 0; 2646 int i; 2647 2648 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2649 err = -EPERM; 2650 goto out; 2651 } 2652 if (!num_vfs) 2653 goto out; 2654 2655 if (old_vfs) { 2656 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2657 old_vfs, max_vfs); 2658 adapter->vfs_allocated_count = old_vfs; 2659 } else 2660 adapter->vfs_allocated_count = num_vfs; 2661 2662 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2663 sizeof(struct vf_data_storage), GFP_KERNEL); 2664 2665 /* if allocation failed then we do not support SR-IOV */ 2666 if (!adapter->vf_data) { 2667 adapter->vfs_allocated_count = 0; 2668 dev_err(&pdev->dev, 2669 "Unable to allocate memory for VF Data Storage\n"); 2670 err = -ENOMEM; 2671 goto out; 2672 } 2673 2674 /* only call pci_enable_sriov() if no VFs are allocated already */ 2675 if (!old_vfs) { 2676 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2677 if (err) 2678 goto err_out; 2679 } 2680 dev_info(&pdev->dev, "%d VFs allocated\n", 2681 adapter->vfs_allocated_count); 2682 for (i = 0; i < adapter->vfs_allocated_count; i++) 2683 igb_vf_configure(adapter, i); 2684 2685 /* DMA Coalescing is not supported in IOV mode. */ 2686 adapter->flags &= ~IGB_FLAG_DMAC; 2687 goto out; 2688 2689err_out: 2690 kfree(adapter->vf_data); 2691 adapter->vf_data = NULL; 2692 adapter->vfs_allocated_count = 0; 2693out: 2694 return err; 2695} 2696 2697#endif 2698/** 2699 * igb_remove_i2c - Cleanup I2C interface 2700 * @adapter: pointer to adapter structure 2701 **/ 2702static void igb_remove_i2c(struct igb_adapter *adapter) 2703{ 2704 /* free the adapter bus structure */ 2705 i2c_del_adapter(&adapter->i2c_adap); 2706} 2707 2708/** 2709 * igb_remove - Device Removal Routine 2710 * @pdev: PCI device information struct 2711 * 2712 * igb_remove is called by the PCI subsystem to alert the driver 2713 * that it should release a PCI device. The could be caused by a 2714 * Hot-Plug event, or because the driver is going to be removed from 2715 * memory. 2716 **/ 2717static void igb_remove(struct pci_dev *pdev) 2718{ 2719 struct net_device *netdev = pci_get_drvdata(pdev); 2720 struct igb_adapter *adapter = netdev_priv(netdev); 2721 struct e1000_hw *hw = &adapter->hw; 2722 2723 pm_runtime_get_noresume(&pdev->dev); 2724#ifdef CONFIG_IGB_HWMON 2725 igb_sysfs_exit(adapter); 2726#endif 2727 igb_remove_i2c(adapter); 2728 igb_ptp_stop(adapter); 2729 /* The watchdog timer may be rescheduled, so explicitly 2730 * disable watchdog from being rescheduled. 2731 */ 2732 set_bit(__IGB_DOWN, &adapter->state); 2733 del_timer_sync(&adapter->watchdog_timer); 2734 del_timer_sync(&adapter->phy_info_timer); 2735 2736 cancel_work_sync(&adapter->reset_task); 2737 cancel_work_sync(&adapter->watchdog_task); 2738 2739#ifdef CONFIG_IGB_DCA 2740 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2741 dev_info(&pdev->dev, "DCA disabled\n"); 2742 dca_remove_requester(&pdev->dev); 2743 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2744 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2745 } 2746#endif 2747 2748 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2749 * would have already happened in close and is redundant. 2750 */ 2751 igb_release_hw_control(adapter); 2752 2753 unregister_netdev(netdev); 2754 2755 igb_clear_interrupt_scheme(adapter); 2756 2757#ifdef CONFIG_PCI_IOV 2758 igb_disable_sriov(pdev); 2759#endif 2760 2761 iounmap(hw->hw_addr); 2762 if (hw->flash_address) 2763 iounmap(hw->flash_address); 2764 pci_release_selected_regions(pdev, 2765 pci_select_bars(pdev, IORESOURCE_MEM)); 2766 2767 kfree(adapter->shadow_vfta); 2768 free_netdev(netdev); 2769 2770 pci_disable_pcie_error_reporting(pdev); 2771 2772 pci_disable_device(pdev); 2773} 2774 2775/** 2776 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2777 * @adapter: board private structure to initialize 2778 * 2779 * This function initializes the vf specific data storage and then attempts to 2780 * allocate the VFs. The reason for ordering it this way is because it is much 2781 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2782 * the memory for the VFs. 2783 **/ 2784static void igb_probe_vfs(struct igb_adapter *adapter) 2785{ 2786#ifdef CONFIG_PCI_IOV 2787 struct pci_dev *pdev = adapter->pdev; 2788 struct e1000_hw *hw = &adapter->hw; 2789 2790 /* Virtualization features not supported on i210 family. */ 2791 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2792 return; 2793 2794 pci_sriov_set_totalvfs(pdev, 7); 2795 igb_pci_enable_sriov(pdev, max_vfs); 2796 2797#endif /* CONFIG_PCI_IOV */ 2798} 2799 2800static void igb_init_queue_configuration(struct igb_adapter *adapter) 2801{ 2802 struct e1000_hw *hw = &adapter->hw; 2803 u32 max_rss_queues; 2804 2805 /* Determine the maximum number of RSS queues supported. */ 2806 switch (hw->mac.type) { 2807 case e1000_i211: 2808 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2809 break; 2810 case e1000_82575: 2811 case e1000_i210: 2812 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2813 break; 2814 case e1000_i350: 2815 /* I350 cannot do RSS and SR-IOV at the same time */ 2816 if (!!adapter->vfs_allocated_count) { 2817 max_rss_queues = 1; 2818 break; 2819 } 2820 /* fall through */ 2821 case e1000_82576: 2822 if (!!adapter->vfs_allocated_count) { 2823 max_rss_queues = 2; 2824 break; 2825 } 2826 /* fall through */ 2827 case e1000_82580: 2828 case e1000_i354: 2829 default: 2830 max_rss_queues = IGB_MAX_RX_QUEUES; 2831 break; 2832 } 2833 2834 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2835 2836 /* Determine if we need to pair queues. */ 2837 switch (hw->mac.type) { 2838 case e1000_82575: 2839 case e1000_i211: 2840 /* Device supports enough interrupts without queue pairing. */ 2841 break; 2842 case e1000_82576: 2843 /* If VFs are going to be allocated with RSS queues then we 2844 * should pair the queues in order to conserve interrupts due 2845 * to limited supply. 2846 */ 2847 if ((adapter->rss_queues > 1) && 2848 (adapter->vfs_allocated_count > 6)) 2849 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2850 /* fall through */ 2851 case e1000_82580: 2852 case e1000_i350: 2853 case e1000_i354: 2854 case e1000_i210: 2855 default: 2856 /* If rss_queues > half of max_rss_queues, pair the queues in 2857 * order to conserve interrupts due to limited supply. 2858 */ 2859 if (adapter->rss_queues > (max_rss_queues / 2)) 2860 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2861 break; 2862 } 2863} 2864 2865/** 2866 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2867 * @adapter: board private structure to initialize 2868 * 2869 * igb_sw_init initializes the Adapter private data structure. 2870 * Fields are initialized based on PCI device information and 2871 * OS network device settings (MTU size). 2872 **/ 2873static int igb_sw_init(struct igb_adapter *adapter) 2874{ 2875 struct e1000_hw *hw = &adapter->hw; 2876 struct net_device *netdev = adapter->netdev; 2877 struct pci_dev *pdev = adapter->pdev; 2878 2879 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2880 2881 /* set default ring sizes */ 2882 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2883 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2884 2885 /* set default ITR values */ 2886 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2887 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2888 2889 /* set default work limits */ 2890 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2891 2892 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2893 VLAN_HLEN; 2894 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2895 2896 spin_lock_init(&adapter->stats64_lock); 2897#ifdef CONFIG_PCI_IOV 2898 switch (hw->mac.type) { 2899 case e1000_82576: 2900 case e1000_i350: 2901 if (max_vfs > 7) { 2902 dev_warn(&pdev->dev, 2903 "Maximum of 7 VFs per PF, using max\n"); 2904 max_vfs = adapter->vfs_allocated_count = 7; 2905 } else 2906 adapter->vfs_allocated_count = max_vfs; 2907 if (adapter->vfs_allocated_count) 2908 dev_warn(&pdev->dev, 2909 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 2910 break; 2911 default: 2912 break; 2913 } 2914#endif /* CONFIG_PCI_IOV */ 2915 2916 igb_init_queue_configuration(adapter); 2917 2918 /* Setup and initialize a copy of the hw vlan table array */ 2919 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 2920 GFP_ATOMIC); 2921 2922 /* This call may decrease the number of queues */ 2923 if (igb_init_interrupt_scheme(adapter, true)) { 2924 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2925 return -ENOMEM; 2926 } 2927 2928 igb_probe_vfs(adapter); 2929 2930 /* Explicitly disable IRQ since the NIC can be in any state. */ 2931 igb_irq_disable(adapter); 2932 2933 if (hw->mac.type >= e1000_i350) 2934 adapter->flags &= ~IGB_FLAG_DMAC; 2935 2936 set_bit(__IGB_DOWN, &adapter->state); 2937 return 0; 2938} 2939 2940/** 2941 * igb_open - Called when a network interface is made active 2942 * @netdev: network interface device structure 2943 * 2944 * Returns 0 on success, negative value on failure 2945 * 2946 * The open entry point is called when a network interface is made 2947 * active by the system (IFF_UP). At this point all resources needed 2948 * for transmit and receive operations are allocated, the interrupt 2949 * handler is registered with the OS, the watchdog timer is started, 2950 * and the stack is notified that the interface is ready. 2951 **/ 2952static int __igb_open(struct net_device *netdev, bool resuming) 2953{ 2954 struct igb_adapter *adapter = netdev_priv(netdev); 2955 struct e1000_hw *hw = &adapter->hw; 2956 struct pci_dev *pdev = adapter->pdev; 2957 int err; 2958 int i; 2959 2960 /* disallow open during test */ 2961 if (test_bit(__IGB_TESTING, &adapter->state)) { 2962 WARN_ON(resuming); 2963 return -EBUSY; 2964 } 2965 2966 if (!resuming) 2967 pm_runtime_get_sync(&pdev->dev); 2968 2969 netif_carrier_off(netdev); 2970 2971 /* allocate transmit descriptors */ 2972 err = igb_setup_all_tx_resources(adapter); 2973 if (err) 2974 goto err_setup_tx; 2975 2976 /* allocate receive descriptors */ 2977 err = igb_setup_all_rx_resources(adapter); 2978 if (err) 2979 goto err_setup_rx; 2980 2981 igb_power_up_link(adapter); 2982 2983 /* before we allocate an interrupt, we must be ready to handle it. 2984 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 2985 * as soon as we call pci_request_irq, so we have to setup our 2986 * clean_rx handler before we do so. 2987 */ 2988 igb_configure(adapter); 2989 2990 err = igb_request_irq(adapter); 2991 if (err) 2992 goto err_req_irq; 2993 2994 /* Notify the stack of the actual queue counts. */ 2995 err = netif_set_real_num_tx_queues(adapter->netdev, 2996 adapter->num_tx_queues); 2997 if (err) 2998 goto err_set_queues; 2999 3000 err = netif_set_real_num_rx_queues(adapter->netdev, 3001 adapter->num_rx_queues); 3002 if (err) 3003 goto err_set_queues; 3004 3005 /* From here on the code is the same as igb_up() */ 3006 clear_bit(__IGB_DOWN, &adapter->state); 3007 3008 for (i = 0; i < adapter->num_q_vectors; i++) 3009 napi_enable(&(adapter->q_vector[i]->napi)); 3010 3011 /* Clear any pending interrupts. */ 3012 rd32(E1000_ICR); 3013 3014 igb_irq_enable(adapter); 3015 3016 /* notify VFs that reset has been completed */ 3017 if (adapter->vfs_allocated_count) { 3018 u32 reg_data = rd32(E1000_CTRL_EXT); 3019 reg_data |= E1000_CTRL_EXT_PFRSTD; 3020 wr32(E1000_CTRL_EXT, reg_data); 3021 } 3022 3023 netif_tx_start_all_queues(netdev); 3024 3025 if (!resuming) 3026 pm_runtime_put(&pdev->dev); 3027 3028 /* start the watchdog. */ 3029 hw->mac.get_link_status = 1; 3030 schedule_work(&adapter->watchdog_task); 3031 3032 return 0; 3033 3034err_set_queues: 3035 igb_free_irq(adapter); 3036err_req_irq: 3037 igb_release_hw_control(adapter); 3038 igb_power_down_link(adapter); 3039 igb_free_all_rx_resources(adapter); 3040err_setup_rx: 3041 igb_free_all_tx_resources(adapter); 3042err_setup_tx: 3043 igb_reset(adapter); 3044 if (!resuming) 3045 pm_runtime_put(&pdev->dev); 3046 3047 return err; 3048} 3049 3050static int igb_open(struct net_device *netdev) 3051{ 3052 return __igb_open(netdev, false); 3053} 3054 3055/** 3056 * igb_close - Disables a network interface 3057 * @netdev: network interface device structure 3058 * 3059 * Returns 0, this is not allowed to fail 3060 * 3061 * The close entry point is called when an interface is de-activated 3062 * by the OS. The hardware is still under the driver's control, but 3063 * needs to be disabled. A global MAC reset is issued to stop the 3064 * hardware, and all transmit and receive resources are freed. 3065 **/ 3066static int __igb_close(struct net_device *netdev, bool suspending) 3067{ 3068 struct igb_adapter *adapter = netdev_priv(netdev); 3069 struct pci_dev *pdev = adapter->pdev; 3070 3071 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3072 3073 if (!suspending) 3074 pm_runtime_get_sync(&pdev->dev); 3075 3076 igb_down(adapter); 3077 igb_free_irq(adapter); 3078 3079 igb_free_all_tx_resources(adapter); 3080 igb_free_all_rx_resources(adapter); 3081 3082 if (!suspending) 3083 pm_runtime_put_sync(&pdev->dev); 3084 return 0; 3085} 3086 3087static int igb_close(struct net_device *netdev) 3088{ 3089 return __igb_close(netdev, false); 3090} 3091 3092/** 3093 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3094 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3095 * 3096 * Return 0 on success, negative on failure 3097 **/ 3098int igb_setup_tx_resources(struct igb_ring *tx_ring) 3099{ 3100 struct device *dev = tx_ring->dev; 3101 int size; 3102 3103 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3104 3105 tx_ring->tx_buffer_info = vzalloc(size); 3106 if (!tx_ring->tx_buffer_info) 3107 goto err; 3108 3109 /* round up to nearest 4K */ 3110 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3111 tx_ring->size = ALIGN(tx_ring->size, 4096); 3112 3113 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3114 &tx_ring->dma, GFP_KERNEL); 3115 if (!tx_ring->desc) 3116 goto err; 3117 3118 tx_ring->next_to_use = 0; 3119 tx_ring->next_to_clean = 0; 3120 3121 return 0; 3122 3123err: 3124 vfree(tx_ring->tx_buffer_info); 3125 tx_ring->tx_buffer_info = NULL; 3126 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3127 return -ENOMEM; 3128} 3129 3130/** 3131 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3132 * (Descriptors) for all queues 3133 * @adapter: board private structure 3134 * 3135 * Return 0 on success, negative on failure 3136 **/ 3137static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3138{ 3139 struct pci_dev *pdev = adapter->pdev; 3140 int i, err = 0; 3141 3142 for (i = 0; i < adapter->num_tx_queues; i++) { 3143 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3144 if (err) { 3145 dev_err(&pdev->dev, 3146 "Allocation for Tx Queue %u failed\n", i); 3147 for (i--; i >= 0; i--) 3148 igb_free_tx_resources(adapter->tx_ring[i]); 3149 break; 3150 } 3151 } 3152 3153 return err; 3154} 3155 3156/** 3157 * igb_setup_tctl - configure the transmit control registers 3158 * @adapter: Board private structure 3159 **/ 3160void igb_setup_tctl(struct igb_adapter *adapter) 3161{ 3162 struct e1000_hw *hw = &adapter->hw; 3163 u32 tctl; 3164 3165 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3166 wr32(E1000_TXDCTL(0), 0); 3167 3168 /* Program the Transmit Control Register */ 3169 tctl = rd32(E1000_TCTL); 3170 tctl &= ~E1000_TCTL_CT; 3171 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3172 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3173 3174 igb_config_collision_dist(hw); 3175 3176 /* Enable transmits */ 3177 tctl |= E1000_TCTL_EN; 3178 3179 wr32(E1000_TCTL, tctl); 3180} 3181 3182/** 3183 * igb_configure_tx_ring - Configure transmit ring after Reset 3184 * @adapter: board private structure 3185 * @ring: tx ring to configure 3186 * 3187 * Configure a transmit ring after a reset. 3188 **/ 3189void igb_configure_tx_ring(struct igb_adapter *adapter, 3190 struct igb_ring *ring) 3191{ 3192 struct e1000_hw *hw = &adapter->hw; 3193 u32 txdctl = 0; 3194 u64 tdba = ring->dma; 3195 int reg_idx = ring->reg_idx; 3196 3197 /* disable the queue */ 3198 wr32(E1000_TXDCTL(reg_idx), 0); 3199 wrfl(); 3200 mdelay(10); 3201 3202 wr32(E1000_TDLEN(reg_idx), 3203 ring->count * sizeof(union e1000_adv_tx_desc)); 3204 wr32(E1000_TDBAL(reg_idx), 3205 tdba & 0x00000000ffffffffULL); 3206 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3207 3208 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 3209 wr32(E1000_TDH(reg_idx), 0); 3210 writel(0, ring->tail); 3211 3212 txdctl |= IGB_TX_PTHRESH; 3213 txdctl |= IGB_TX_HTHRESH << 8; 3214 txdctl |= IGB_TX_WTHRESH << 16; 3215 3216 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3217 wr32(E1000_TXDCTL(reg_idx), txdctl); 3218} 3219 3220/** 3221 * igb_configure_tx - Configure transmit Unit after Reset 3222 * @adapter: board private structure 3223 * 3224 * Configure the Tx unit of the MAC after a reset. 3225 **/ 3226static void igb_configure_tx(struct igb_adapter *adapter) 3227{ 3228 int i; 3229 3230 for (i = 0; i < adapter->num_tx_queues; i++) 3231 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3232} 3233 3234/** 3235 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3236 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3237 * 3238 * Returns 0 on success, negative on failure 3239 **/ 3240int igb_setup_rx_resources(struct igb_ring *rx_ring) 3241{ 3242 struct device *dev = rx_ring->dev; 3243 int size; 3244 3245 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3246 3247 rx_ring->rx_buffer_info = vzalloc(size); 3248 if (!rx_ring->rx_buffer_info) 3249 goto err; 3250 3251 /* Round up to nearest 4K */ 3252 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3253 rx_ring->size = ALIGN(rx_ring->size, 4096); 3254 3255 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3256 &rx_ring->dma, GFP_KERNEL); 3257 if (!rx_ring->desc) 3258 goto err; 3259 3260 rx_ring->next_to_alloc = 0; 3261 rx_ring->next_to_clean = 0; 3262 rx_ring->next_to_use = 0; 3263 3264 return 0; 3265 3266err: 3267 vfree(rx_ring->rx_buffer_info); 3268 rx_ring->rx_buffer_info = NULL; 3269 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3270 return -ENOMEM; 3271} 3272 3273/** 3274 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3275 * (Descriptors) for all queues 3276 * @adapter: board private structure 3277 * 3278 * Return 0 on success, negative on failure 3279 **/ 3280static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3281{ 3282 struct pci_dev *pdev = adapter->pdev; 3283 int i, err = 0; 3284 3285 for (i = 0; i < adapter->num_rx_queues; i++) { 3286 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3287 if (err) { 3288 dev_err(&pdev->dev, 3289 "Allocation for Rx Queue %u failed\n", i); 3290 for (i--; i >= 0; i--) 3291 igb_free_rx_resources(adapter->rx_ring[i]); 3292 break; 3293 } 3294 } 3295 3296 return err; 3297} 3298 3299/** 3300 * igb_setup_mrqc - configure the multiple receive queue control registers 3301 * @adapter: Board private structure 3302 **/ 3303static void igb_setup_mrqc(struct igb_adapter *adapter) 3304{ 3305 struct e1000_hw *hw = &adapter->hw; 3306 u32 mrqc, rxcsum; 3307 u32 j, num_rx_queues; 3308 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, 3309 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, 3310 0xA32DCB77, 0x0CF23080, 0x3BB7426A, 3311 0xFA01ACBE }; 3312 3313 /* Fill out hash function seeds */ 3314 for (j = 0; j < 10; j++) 3315 wr32(E1000_RSSRK(j), rsskey[j]); 3316 3317 num_rx_queues = adapter->rss_queues; 3318 3319 switch (hw->mac.type) { 3320 case e1000_82576: 3321 /* 82576 supports 2 RSS queues for SR-IOV */ 3322 if (adapter->vfs_allocated_count) 3323 num_rx_queues = 2; 3324 break; 3325 default: 3326 break; 3327 } 3328 3329 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3330 for (j = 0; j < IGB_RETA_SIZE; j++) 3331 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE; 3332 adapter->rss_indir_tbl_init = num_rx_queues; 3333 } 3334 igb_write_rss_indir_tbl(adapter); 3335 3336 /* Disable raw packet checksumming so that RSS hash is placed in 3337 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3338 * offloads as they are enabled by default 3339 */ 3340 rxcsum = rd32(E1000_RXCSUM); 3341 rxcsum |= E1000_RXCSUM_PCSD; 3342 3343 if (adapter->hw.mac.type >= e1000_82576) 3344 /* Enable Receive Checksum Offload for SCTP */ 3345 rxcsum |= E1000_RXCSUM_CRCOFL; 3346 3347 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3348 wr32(E1000_RXCSUM, rxcsum); 3349 3350 /* Generate RSS hash based on packet types, TCP/UDP 3351 * port numbers and/or IPv4/v6 src and dst addresses 3352 */ 3353 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3354 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3355 E1000_MRQC_RSS_FIELD_IPV6 | 3356 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3357 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3358 3359 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3360 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3361 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3362 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3363 3364 /* If VMDq is enabled then we set the appropriate mode for that, else 3365 * we default to RSS so that an RSS hash is calculated per packet even 3366 * if we are only using one queue 3367 */ 3368 if (adapter->vfs_allocated_count) { 3369 if (hw->mac.type > e1000_82575) { 3370 /* Set the default pool for the PF's first queue */ 3371 u32 vtctl = rd32(E1000_VT_CTL); 3372 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3373 E1000_VT_CTL_DISABLE_DEF_POOL); 3374 vtctl |= adapter->vfs_allocated_count << 3375 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3376 wr32(E1000_VT_CTL, vtctl); 3377 } 3378 if (adapter->rss_queues > 1) 3379 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 3380 else 3381 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3382 } else { 3383 if (hw->mac.type != e1000_i211) 3384 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 3385 } 3386 igb_vmm_control(adapter); 3387 3388 wr32(E1000_MRQC, mrqc); 3389} 3390 3391/** 3392 * igb_setup_rctl - configure the receive control registers 3393 * @adapter: Board private structure 3394 **/ 3395void igb_setup_rctl(struct igb_adapter *adapter) 3396{ 3397 struct e1000_hw *hw = &adapter->hw; 3398 u32 rctl; 3399 3400 rctl = rd32(E1000_RCTL); 3401 3402 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3403 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3404 3405 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3406 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3407 3408 /* enable stripping of CRC. It's unlikely this will break BMC 3409 * redirection as it did with e1000. Newer features require 3410 * that the HW strips the CRC. 3411 */ 3412 rctl |= E1000_RCTL_SECRC; 3413 3414 /* disable store bad packets and clear size bits. */ 3415 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3416 3417 /* enable LPE to prevent packets larger than max_frame_size */ 3418 rctl |= E1000_RCTL_LPE; 3419 3420 /* disable queue 0 to prevent tail write w/o re-config */ 3421 wr32(E1000_RXDCTL(0), 0); 3422 3423 /* Attention!!! For SR-IOV PF driver operations you must enable 3424 * queue drop for all VF and PF queues to prevent head of line blocking 3425 * if an un-trusted VF does not provide descriptors to hardware. 3426 */ 3427 if (adapter->vfs_allocated_count) { 3428 /* set all queue drop enable bits */ 3429 wr32(E1000_QDE, ALL_QUEUES); 3430 } 3431 3432 /* This is useful for sniffing bad packets. */ 3433 if (adapter->netdev->features & NETIF_F_RXALL) { 3434 /* UPE and MPE will be handled by normal PROMISC logic 3435 * in e1000e_set_rx_mode 3436 */ 3437 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3438 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3439 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3440 3441 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3442 E1000_RCTL_DPF | /* Allow filtered pause */ 3443 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3444 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3445 * and that breaks VLANs. 3446 */ 3447 } 3448 3449 wr32(E1000_RCTL, rctl); 3450} 3451 3452static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3453 int vfn) 3454{ 3455 struct e1000_hw *hw = &adapter->hw; 3456 u32 vmolr; 3457 3458 /* if it isn't the PF check to see if VFs are enabled and 3459 * increase the size to support vlan tags 3460 */ 3461 if (vfn < adapter->vfs_allocated_count && 3462 adapter->vf_data[vfn].vlans_enabled) 3463 size += VLAN_TAG_SIZE; 3464 3465 vmolr = rd32(E1000_VMOLR(vfn)); 3466 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3467 vmolr |= size | E1000_VMOLR_LPE; 3468 wr32(E1000_VMOLR(vfn), vmolr); 3469 3470 return 0; 3471} 3472 3473/** 3474 * igb_rlpml_set - set maximum receive packet size 3475 * @adapter: board private structure 3476 * 3477 * Configure maximum receivable packet size. 3478 **/ 3479static void igb_rlpml_set(struct igb_adapter *adapter) 3480{ 3481 u32 max_frame_size = adapter->max_frame_size; 3482 struct e1000_hw *hw = &adapter->hw; 3483 u16 pf_id = adapter->vfs_allocated_count; 3484 3485 if (pf_id) { 3486 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3487 /* If we're in VMDQ or SR-IOV mode, then set global RLPML 3488 * to our max jumbo frame size, in case we need to enable 3489 * jumbo frames on one of the rings later. 3490 * This will not pass over-length frames into the default 3491 * queue because it's gated by the VMOLR.RLPML. 3492 */ 3493 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3494 } 3495 3496 wr32(E1000_RLPML, max_frame_size); 3497} 3498 3499static inline void igb_set_vmolr(struct igb_adapter *adapter, 3500 int vfn, bool aupe) 3501{ 3502 struct e1000_hw *hw = &adapter->hw; 3503 u32 vmolr; 3504 3505 /* This register exists only on 82576 and newer so if we are older then 3506 * we should exit and do nothing 3507 */ 3508 if (hw->mac.type < e1000_82576) 3509 return; 3510 3511 vmolr = rd32(E1000_VMOLR(vfn)); 3512 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3513 if (aupe) 3514 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3515 else 3516 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3517 3518 /* clear all bits that might not be set */ 3519 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3520 3521 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3522 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3523 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3524 * multicast packets 3525 */ 3526 if (vfn <= adapter->vfs_allocated_count) 3527 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3528 3529 wr32(E1000_VMOLR(vfn), vmolr); 3530} 3531 3532/** 3533 * igb_configure_rx_ring - Configure a receive ring after Reset 3534 * @adapter: board private structure 3535 * @ring: receive ring to be configured 3536 * 3537 * Configure the Rx unit of the MAC after a reset. 3538 **/ 3539void igb_configure_rx_ring(struct igb_adapter *adapter, 3540 struct igb_ring *ring) 3541{ 3542 struct e1000_hw *hw = &adapter->hw; 3543 u64 rdba = ring->dma; 3544 int reg_idx = ring->reg_idx; 3545 u32 srrctl = 0, rxdctl = 0; 3546 3547 /* disable the queue */ 3548 wr32(E1000_RXDCTL(reg_idx), 0); 3549 3550 /* Set DMA base address registers */ 3551 wr32(E1000_RDBAL(reg_idx), 3552 rdba & 0x00000000ffffffffULL); 3553 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3554 wr32(E1000_RDLEN(reg_idx), 3555 ring->count * sizeof(union e1000_adv_rx_desc)); 3556 3557 /* initialize head and tail */ 3558 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3559 wr32(E1000_RDH(reg_idx), 0); 3560 writel(0, ring->tail); 3561 3562 /* set descriptor configuration */ 3563 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3564 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3565 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3566 if (hw->mac.type >= e1000_82580) 3567 srrctl |= E1000_SRRCTL_TIMESTAMP; 3568 /* Only set Drop Enable if we are supporting multiple queues */ 3569 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3570 srrctl |= E1000_SRRCTL_DROP_EN; 3571 3572 wr32(E1000_SRRCTL(reg_idx), srrctl); 3573 3574 /* set filtering for VMDQ pools */ 3575 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3576 3577 rxdctl |= IGB_RX_PTHRESH; 3578 rxdctl |= IGB_RX_HTHRESH << 8; 3579 rxdctl |= IGB_RX_WTHRESH << 16; 3580 3581 /* enable receive descriptor fetching */ 3582 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3583 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3584} 3585 3586/** 3587 * igb_configure_rx - Configure receive Unit after Reset 3588 * @adapter: board private structure 3589 * 3590 * Configure the Rx unit of the MAC after a reset. 3591 **/ 3592static void igb_configure_rx(struct igb_adapter *adapter) 3593{ 3594 int i; 3595 3596 /* set UTA to appropriate mode */ 3597 igb_set_uta(adapter); 3598 3599 /* set the correct pool for the PF default MAC address in entry 0 */ 3600 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3601 adapter->vfs_allocated_count); 3602 3603 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3604 * the Base and Length of the Rx Descriptor Ring 3605 */ 3606 for (i = 0; i < adapter->num_rx_queues; i++) 3607 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3608} 3609 3610/** 3611 * igb_free_tx_resources - Free Tx Resources per Queue 3612 * @tx_ring: Tx descriptor ring for a specific queue 3613 * 3614 * Free all transmit software resources 3615 **/ 3616void igb_free_tx_resources(struct igb_ring *tx_ring) 3617{ 3618 igb_clean_tx_ring(tx_ring); 3619 3620 vfree(tx_ring->tx_buffer_info); 3621 tx_ring->tx_buffer_info = NULL; 3622 3623 /* if not set, then don't free */ 3624 if (!tx_ring->desc) 3625 return; 3626 3627 dma_free_coherent(tx_ring->dev, tx_ring->size, 3628 tx_ring->desc, tx_ring->dma); 3629 3630 tx_ring->desc = NULL; 3631} 3632 3633/** 3634 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3635 * @adapter: board private structure 3636 * 3637 * Free all transmit software resources 3638 **/ 3639static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3640{ 3641 int i; 3642 3643 for (i = 0; i < adapter->num_tx_queues; i++) 3644 igb_free_tx_resources(adapter->tx_ring[i]); 3645} 3646 3647void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3648 struct igb_tx_buffer *tx_buffer) 3649{ 3650 if (tx_buffer->skb) { 3651 dev_kfree_skb_any(tx_buffer->skb); 3652 if (dma_unmap_len(tx_buffer, len)) 3653 dma_unmap_single(ring->dev, 3654 dma_unmap_addr(tx_buffer, dma), 3655 dma_unmap_len(tx_buffer, len), 3656 DMA_TO_DEVICE); 3657 } else if (dma_unmap_len(tx_buffer, len)) { 3658 dma_unmap_page(ring->dev, 3659 dma_unmap_addr(tx_buffer, dma), 3660 dma_unmap_len(tx_buffer, len), 3661 DMA_TO_DEVICE); 3662 } 3663 tx_buffer->next_to_watch = NULL; 3664 tx_buffer->skb = NULL; 3665 dma_unmap_len_set(tx_buffer, len, 0); 3666 /* buffer_info must be completely set up in the transmit path */ 3667} 3668 3669/** 3670 * igb_clean_tx_ring - Free Tx Buffers 3671 * @tx_ring: ring to be cleaned 3672 **/ 3673static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3674{ 3675 struct igb_tx_buffer *buffer_info; 3676 unsigned long size; 3677 u16 i; 3678 3679 if (!tx_ring->tx_buffer_info) 3680 return; 3681 /* Free all the Tx ring sk_buffs */ 3682 3683 for (i = 0; i < tx_ring->count; i++) { 3684 buffer_info = &tx_ring->tx_buffer_info[i]; 3685 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3686 } 3687 3688 netdev_tx_reset_queue(txring_txq(tx_ring)); 3689 3690 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3691 memset(tx_ring->tx_buffer_info, 0, size); 3692 3693 /* Zero out the descriptor ring */ 3694 memset(tx_ring->desc, 0, tx_ring->size); 3695 3696 tx_ring->next_to_use = 0; 3697 tx_ring->next_to_clean = 0; 3698} 3699 3700/** 3701 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3702 * @adapter: board private structure 3703 **/ 3704static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3705{ 3706 int i; 3707 3708 for (i = 0; i < adapter->num_tx_queues; i++) 3709 igb_clean_tx_ring(adapter->tx_ring[i]); 3710} 3711 3712/** 3713 * igb_free_rx_resources - Free Rx Resources 3714 * @rx_ring: ring to clean the resources from 3715 * 3716 * Free all receive software resources 3717 **/ 3718void igb_free_rx_resources(struct igb_ring *rx_ring) 3719{ 3720 igb_clean_rx_ring(rx_ring); 3721 3722 vfree(rx_ring->rx_buffer_info); 3723 rx_ring->rx_buffer_info = NULL; 3724 3725 /* if not set, then don't free */ 3726 if (!rx_ring->desc) 3727 return; 3728 3729 dma_free_coherent(rx_ring->dev, rx_ring->size, 3730 rx_ring->desc, rx_ring->dma); 3731 3732 rx_ring->desc = NULL; 3733} 3734 3735/** 3736 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3737 * @adapter: board private structure 3738 * 3739 * Free all receive software resources 3740 **/ 3741static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3742{ 3743 int i; 3744 3745 for (i = 0; i < adapter->num_rx_queues; i++) 3746 igb_free_rx_resources(adapter->rx_ring[i]); 3747} 3748 3749/** 3750 * igb_clean_rx_ring - Free Rx Buffers per Queue 3751 * @rx_ring: ring to free buffers from 3752 **/ 3753static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3754{ 3755 unsigned long size; 3756 u16 i; 3757 3758 if (rx_ring->skb) 3759 dev_kfree_skb(rx_ring->skb); 3760 rx_ring->skb = NULL; 3761 3762 if (!rx_ring->rx_buffer_info) 3763 return; 3764 3765 /* Free all the Rx ring sk_buffs */ 3766 for (i = 0; i < rx_ring->count; i++) { 3767 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3768 3769 if (!buffer_info->page) 3770 continue; 3771 3772 dma_unmap_page(rx_ring->dev, 3773 buffer_info->dma, 3774 PAGE_SIZE, 3775 DMA_FROM_DEVICE); 3776 __free_page(buffer_info->page); 3777 3778 buffer_info->page = NULL; 3779 } 3780 3781 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3782 memset(rx_ring->rx_buffer_info, 0, size); 3783 3784 /* Zero out the descriptor ring */ 3785 memset(rx_ring->desc, 0, rx_ring->size); 3786 3787 rx_ring->next_to_alloc = 0; 3788 rx_ring->next_to_clean = 0; 3789 rx_ring->next_to_use = 0; 3790} 3791 3792/** 3793 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3794 * @adapter: board private structure 3795 **/ 3796static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3797{ 3798 int i; 3799 3800 for (i = 0; i < adapter->num_rx_queues; i++) 3801 igb_clean_rx_ring(adapter->rx_ring[i]); 3802} 3803 3804/** 3805 * igb_set_mac - Change the Ethernet Address of the NIC 3806 * @netdev: network interface device structure 3807 * @p: pointer to an address structure 3808 * 3809 * Returns 0 on success, negative on failure 3810 **/ 3811static int igb_set_mac(struct net_device *netdev, void *p) 3812{ 3813 struct igb_adapter *adapter = netdev_priv(netdev); 3814 struct e1000_hw *hw = &adapter->hw; 3815 struct sockaddr *addr = p; 3816 3817 if (!is_valid_ether_addr(addr->sa_data)) 3818 return -EADDRNOTAVAIL; 3819 3820 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3821 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3822 3823 /* set the correct pool for the new PF MAC address in entry 0 */ 3824 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3825 adapter->vfs_allocated_count); 3826 3827 return 0; 3828} 3829 3830/** 3831 * igb_write_mc_addr_list - write multicast addresses to MTA 3832 * @netdev: network interface device structure 3833 * 3834 * Writes multicast address list to the MTA hash table. 3835 * Returns: -ENOMEM on failure 3836 * 0 on no addresses written 3837 * X on writing X addresses to MTA 3838 **/ 3839static int igb_write_mc_addr_list(struct net_device *netdev) 3840{ 3841 struct igb_adapter *adapter = netdev_priv(netdev); 3842 struct e1000_hw *hw = &adapter->hw; 3843 struct netdev_hw_addr *ha; 3844 u8 *mta_list; 3845 int i; 3846 3847 if (netdev_mc_empty(netdev)) { 3848 /* nothing to program, so clear mc list */ 3849 igb_update_mc_addr_list(hw, NULL, 0); 3850 igb_restore_vf_multicasts(adapter); 3851 return 0; 3852 } 3853 3854 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3855 if (!mta_list) 3856 return -ENOMEM; 3857 3858 /* The shared function expects a packed array of only addresses. */ 3859 i = 0; 3860 netdev_for_each_mc_addr(ha, netdev) 3861 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3862 3863 igb_update_mc_addr_list(hw, mta_list, i); 3864 kfree(mta_list); 3865 3866 return netdev_mc_count(netdev); 3867} 3868 3869/** 3870 * igb_write_uc_addr_list - write unicast addresses to RAR table 3871 * @netdev: network interface device structure 3872 * 3873 * Writes unicast address list to the RAR table. 3874 * Returns: -ENOMEM on failure/insufficient address space 3875 * 0 on no addresses written 3876 * X on writing X addresses to the RAR table 3877 **/ 3878static int igb_write_uc_addr_list(struct net_device *netdev) 3879{ 3880 struct igb_adapter *adapter = netdev_priv(netdev); 3881 struct e1000_hw *hw = &adapter->hw; 3882 unsigned int vfn = adapter->vfs_allocated_count; 3883 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3884 int count = 0; 3885 3886 /* return ENOMEM indicating insufficient memory for addresses */ 3887 if (netdev_uc_count(netdev) > rar_entries) 3888 return -ENOMEM; 3889 3890 if (!netdev_uc_empty(netdev) && rar_entries) { 3891 struct netdev_hw_addr *ha; 3892 3893 netdev_for_each_uc_addr(ha, netdev) { 3894 if (!rar_entries) 3895 break; 3896 igb_rar_set_qsel(adapter, ha->addr, 3897 rar_entries--, 3898 vfn); 3899 count++; 3900 } 3901 } 3902 /* write the addresses in reverse order to avoid write combining */ 3903 for (; rar_entries > 0 ; rar_entries--) { 3904 wr32(E1000_RAH(rar_entries), 0); 3905 wr32(E1000_RAL(rar_entries), 0); 3906 } 3907 wrfl(); 3908 3909 return count; 3910} 3911 3912/** 3913 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3914 * @netdev: network interface device structure 3915 * 3916 * The set_rx_mode entry point is called whenever the unicast or multicast 3917 * address lists or the network interface flags are updated. This routine is 3918 * responsible for configuring the hardware for proper unicast, multicast, 3919 * promiscuous mode, and all-multi behavior. 3920 **/ 3921static void igb_set_rx_mode(struct net_device *netdev) 3922{ 3923 struct igb_adapter *adapter = netdev_priv(netdev); 3924 struct e1000_hw *hw = &adapter->hw; 3925 unsigned int vfn = adapter->vfs_allocated_count; 3926 u32 rctl, vmolr = 0; 3927 int count; 3928 3929 /* Check for Promiscuous and All Multicast modes */ 3930 rctl = rd32(E1000_RCTL); 3931 3932 /* clear the effected bits */ 3933 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 3934 3935 if (netdev->flags & IFF_PROMISC) { 3936 /* retain VLAN HW filtering if in VT mode */ 3937 if (adapter->vfs_allocated_count) 3938 rctl |= E1000_RCTL_VFE; 3939 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3940 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 3941 } else { 3942 if (netdev->flags & IFF_ALLMULTI) { 3943 rctl |= E1000_RCTL_MPE; 3944 vmolr |= E1000_VMOLR_MPME; 3945 } else { 3946 /* Write addresses to the MTA, if the attempt fails 3947 * then we should just turn on promiscuous mode so 3948 * that we can at least receive multicast traffic 3949 */ 3950 count = igb_write_mc_addr_list(netdev); 3951 if (count < 0) { 3952 rctl |= E1000_RCTL_MPE; 3953 vmolr |= E1000_VMOLR_MPME; 3954 } else if (count) { 3955 vmolr |= E1000_VMOLR_ROMPE; 3956 } 3957 } 3958 /* Write addresses to available RAR registers, if there is not 3959 * sufficient space to store all the addresses then enable 3960 * unicast promiscuous mode 3961 */ 3962 count = igb_write_uc_addr_list(netdev); 3963 if (count < 0) { 3964 rctl |= E1000_RCTL_UPE; 3965 vmolr |= E1000_VMOLR_ROPE; 3966 } 3967 rctl |= E1000_RCTL_VFE; 3968 } 3969 wr32(E1000_RCTL, rctl); 3970 3971 /* In order to support SR-IOV and eventually VMDq it is necessary to set 3972 * the VMOLR to enable the appropriate modes. Without this workaround 3973 * we will have issues with VLAN tag stripping not being done for frames 3974 * that are only arriving because we are the default pool 3975 */ 3976 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 3977 return; 3978 3979 vmolr |= rd32(E1000_VMOLR(vfn)) & 3980 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 3981 wr32(E1000_VMOLR(vfn), vmolr); 3982 igb_restore_vf_multicasts(adapter); 3983} 3984 3985static void igb_check_wvbr(struct igb_adapter *adapter) 3986{ 3987 struct e1000_hw *hw = &adapter->hw; 3988 u32 wvbr = 0; 3989 3990 switch (hw->mac.type) { 3991 case e1000_82576: 3992 case e1000_i350: 3993 if (!(wvbr = rd32(E1000_WVBR))) 3994 return; 3995 break; 3996 default: 3997 break; 3998 } 3999 4000 adapter->wvbr |= wvbr; 4001} 4002 4003#define IGB_STAGGERED_QUEUE_OFFSET 8 4004 4005static void igb_spoof_check(struct igb_adapter *adapter) 4006{ 4007 int j; 4008 4009 if (!adapter->wvbr) 4010 return; 4011 4012 for(j = 0; j < adapter->vfs_allocated_count; j++) { 4013 if (adapter->wvbr & (1 << j) || 4014 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 4015 dev_warn(&adapter->pdev->dev, 4016 "Spoof event(s) detected on VF %d\n", j); 4017 adapter->wvbr &= 4018 ~((1 << j) | 4019 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 4020 } 4021 } 4022} 4023 4024/* Need to wait a few seconds after link up to get diagnostic information from 4025 * the phy 4026 */ 4027static void igb_update_phy_info(unsigned long data) 4028{ 4029 struct igb_adapter *adapter = (struct igb_adapter *) data; 4030 igb_get_phy_info(&adapter->hw); 4031} 4032 4033/** 4034 * igb_has_link - check shared code for link and determine up/down 4035 * @adapter: pointer to driver private info 4036 **/ 4037bool igb_has_link(struct igb_adapter *adapter) 4038{ 4039 struct e1000_hw *hw = &adapter->hw; 4040 bool link_active = false; 4041 4042 /* get_link_status is set on LSC (link status) interrupt or 4043 * rx sequence error interrupt. get_link_status will stay 4044 * false until the e1000_check_for_link establishes link 4045 * for copper adapters ONLY 4046 */ 4047 switch (hw->phy.media_type) { 4048 case e1000_media_type_copper: 4049 if (!hw->mac.get_link_status) 4050 return true; 4051 case e1000_media_type_internal_serdes: 4052 hw->mac.ops.check_for_link(hw); 4053 link_active = !hw->mac.get_link_status; 4054 break; 4055 default: 4056 case e1000_media_type_unknown: 4057 break; 4058 } 4059 4060 if (((hw->mac.type == e1000_i210) || 4061 (hw->mac.type == e1000_i211)) && 4062 (hw->phy.id == I210_I_PHY_ID)) { 4063 if (!netif_carrier_ok(adapter->netdev)) { 4064 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4065 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4066 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4067 adapter->link_check_timeout = jiffies; 4068 } 4069 } 4070 4071 return link_active; 4072} 4073 4074static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4075{ 4076 bool ret = false; 4077 u32 ctrl_ext, thstat; 4078 4079 /* check for thermal sensor event on i350 copper only */ 4080 if (hw->mac.type == e1000_i350) { 4081 thstat = rd32(E1000_THSTAT); 4082 ctrl_ext = rd32(E1000_CTRL_EXT); 4083 4084 if ((hw->phy.media_type == e1000_media_type_copper) && 4085 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4086 ret = !!(thstat & event); 4087 } 4088 4089 return ret; 4090} 4091 4092/** 4093 * igb_watchdog - Timer Call-back 4094 * @data: pointer to adapter cast into an unsigned long 4095 **/ 4096static void igb_watchdog(unsigned long data) 4097{ 4098 struct igb_adapter *adapter = (struct igb_adapter *)data; 4099 /* Do the rest outside of interrupt context */ 4100 schedule_work(&adapter->watchdog_task); 4101} 4102 4103static void igb_watchdog_task(struct work_struct *work) 4104{ 4105 struct igb_adapter *adapter = container_of(work, 4106 struct igb_adapter, 4107 watchdog_task); 4108 struct e1000_hw *hw = &adapter->hw; 4109 struct e1000_phy_info *phy = &hw->phy; 4110 struct net_device *netdev = adapter->netdev; 4111 u32 link; 4112 int i; 4113 u32 connsw; 4114 4115 link = igb_has_link(adapter); 4116 4117 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4118 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4119 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4120 else 4121 link = false; 4122 } 4123 4124 /* Force link down if we have fiber to swap to */ 4125 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4126 if (hw->phy.media_type == e1000_media_type_copper) { 4127 connsw = rd32(E1000_CONNSW); 4128 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4129 link = 0; 4130 } 4131 } 4132 if (link) { 4133 /* Perform a reset if the media type changed. */ 4134 if (hw->dev_spec._82575.media_changed) { 4135 hw->dev_spec._82575.media_changed = false; 4136 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4137 igb_reset(adapter); 4138 } 4139 /* Cancel scheduled suspend requests. */ 4140 pm_runtime_resume(netdev->dev.parent); 4141 4142 if (!netif_carrier_ok(netdev)) { 4143 u32 ctrl; 4144 hw->mac.ops.get_speed_and_duplex(hw, 4145 &adapter->link_speed, 4146 &adapter->link_duplex); 4147 4148 ctrl = rd32(E1000_CTRL); 4149 /* Links status message must follow this format */ 4150 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s " 4151 "Duplex, Flow Control: %s\n", 4152 netdev->name, 4153 adapter->link_speed, 4154 adapter->link_duplex == FULL_DUPLEX ? 4155 "Full" : "Half", 4156 (ctrl & E1000_CTRL_TFCE) && 4157 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4158 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4159 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4160 4161 /* check if SmartSpeed worked */ 4162 igb_check_downshift(hw); 4163 if (phy->speed_downgraded) 4164 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4165 4166 /* check for thermal sensor event */ 4167 if (igb_thermal_sensor_event(hw, 4168 E1000_THSTAT_LINK_THROTTLE)) { 4169 netdev_info(netdev, "The network adapter link " 4170 "speed was downshifted because it " 4171 "overheated\n"); 4172 } 4173 4174 /* adjust timeout factor according to speed/duplex */ 4175 adapter->tx_timeout_factor = 1; 4176 switch (adapter->link_speed) { 4177 case SPEED_10: 4178 adapter->tx_timeout_factor = 14; 4179 break; 4180 case SPEED_100: 4181 /* maybe add some timeout factor ? */ 4182 break; 4183 } 4184 4185 netif_carrier_on(netdev); 4186 4187 igb_ping_all_vfs(adapter); 4188 igb_check_vf_rate_limit(adapter); 4189 4190 /* link state has changed, schedule phy info update */ 4191 if (!test_bit(__IGB_DOWN, &adapter->state)) 4192 mod_timer(&adapter->phy_info_timer, 4193 round_jiffies(jiffies + 2 * HZ)); 4194 } 4195 } else { 4196 if (netif_carrier_ok(netdev)) { 4197 adapter->link_speed = 0; 4198 adapter->link_duplex = 0; 4199 4200 /* check for thermal sensor event */ 4201 if (igb_thermal_sensor_event(hw, 4202 E1000_THSTAT_PWR_DOWN)) { 4203 netdev_err(netdev, "The network adapter was " 4204 "stopped because it overheated\n"); 4205 } 4206 4207 /* Links status message must follow this format */ 4208 printk(KERN_INFO "igb: %s NIC Link is Down\n", 4209 netdev->name); 4210 netif_carrier_off(netdev); 4211 4212 igb_ping_all_vfs(adapter); 4213 4214 /* link state has changed, schedule phy info update */ 4215 if (!test_bit(__IGB_DOWN, &adapter->state)) 4216 mod_timer(&adapter->phy_info_timer, 4217 round_jiffies(jiffies + 2 * HZ)); 4218 4219 /* link is down, time to check for alternate media */ 4220 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4221 igb_check_swap_media(adapter); 4222 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4223 schedule_work(&adapter->reset_task); 4224 /* return immediately */ 4225 return; 4226 } 4227 } 4228 pm_schedule_suspend(netdev->dev.parent, 4229 MSEC_PER_SEC * 5); 4230 4231 /* also check for alternate media here */ 4232 } else if (!netif_carrier_ok(netdev) && 4233 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4234 igb_check_swap_media(adapter); 4235 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4236 schedule_work(&adapter->reset_task); 4237 /* return immediately */ 4238 return; 4239 } 4240 } 4241 } 4242 4243 spin_lock(&adapter->stats64_lock); 4244 igb_update_stats(adapter, &adapter->stats64); 4245 spin_unlock(&adapter->stats64_lock); 4246 4247 for (i = 0; i < adapter->num_tx_queues; i++) { 4248 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4249 if (!netif_carrier_ok(netdev)) { 4250 /* We've lost link, so the controller stops DMA, 4251 * but we've got queued Tx work that's never going 4252 * to get done, so reset controller to flush Tx. 4253 * (Do the reset outside of interrupt context). 4254 */ 4255 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4256 adapter->tx_timeout_count++; 4257 schedule_work(&adapter->reset_task); 4258 /* return immediately since reset is imminent */ 4259 return; 4260 } 4261 } 4262 4263 /* Force detection of hung controller every watchdog period */ 4264 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4265 } 4266 4267 /* Cause software interrupt to ensure Rx ring is cleaned */ 4268 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4269 u32 eics = 0; 4270 for (i = 0; i < adapter->num_q_vectors; i++) 4271 eics |= adapter->q_vector[i]->eims_value; 4272 wr32(E1000_EICS, eics); 4273 } else { 4274 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4275 } 4276 4277 igb_spoof_check(adapter); 4278 igb_ptp_rx_hang(adapter); 4279 4280 /* Reset the timer */ 4281 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4282 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4283 mod_timer(&adapter->watchdog_timer, 4284 round_jiffies(jiffies + HZ)); 4285 else 4286 mod_timer(&adapter->watchdog_timer, 4287 round_jiffies(jiffies + 2 * HZ)); 4288 } 4289} 4290 4291enum latency_range { 4292 lowest_latency = 0, 4293 low_latency = 1, 4294 bulk_latency = 2, 4295 latency_invalid = 255 4296}; 4297 4298/** 4299 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4300 * @q_vector: pointer to q_vector 4301 * 4302 * Stores a new ITR value based on strictly on packet size. This 4303 * algorithm is less sophisticated than that used in igb_update_itr, 4304 * due to the difficulty of synchronizing statistics across multiple 4305 * receive rings. The divisors and thresholds used by this function 4306 * were determined based on theoretical maximum wire speed and testing 4307 * data, in order to minimize response time while increasing bulk 4308 * throughput. 4309 * This functionality is controlled by the InterruptThrottleRate module 4310 * parameter (see igb_param.c) 4311 * NOTE: This function is called only when operating in a multiqueue 4312 * receive environment. 4313 **/ 4314static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4315{ 4316 int new_val = q_vector->itr_val; 4317 int avg_wire_size = 0; 4318 struct igb_adapter *adapter = q_vector->adapter; 4319 unsigned int packets; 4320 4321 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4322 * ints/sec - ITR timer value of 120 ticks. 4323 */ 4324 if (adapter->link_speed != SPEED_1000) { 4325 new_val = IGB_4K_ITR; 4326 goto set_itr_val; 4327 } 4328 4329 packets = q_vector->rx.total_packets; 4330 if (packets) 4331 avg_wire_size = q_vector->rx.total_bytes / packets; 4332 4333 packets = q_vector->tx.total_packets; 4334 if (packets) 4335 avg_wire_size = max_t(u32, avg_wire_size, 4336 q_vector->tx.total_bytes / packets); 4337 4338 /* if avg_wire_size isn't set no work was done */ 4339 if (!avg_wire_size) 4340 goto clear_counts; 4341 4342 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4343 avg_wire_size += 24; 4344 4345 /* Don't starve jumbo frames */ 4346 avg_wire_size = min(avg_wire_size, 3000); 4347 4348 /* Give a little boost to mid-size frames */ 4349 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4350 new_val = avg_wire_size / 3; 4351 else 4352 new_val = avg_wire_size / 2; 4353 4354 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4355 if (new_val < IGB_20K_ITR && 4356 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4357 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4358 new_val = IGB_20K_ITR; 4359 4360set_itr_val: 4361 if (new_val != q_vector->itr_val) { 4362 q_vector->itr_val = new_val; 4363 q_vector->set_itr = 1; 4364 } 4365clear_counts: 4366 q_vector->rx.total_bytes = 0; 4367 q_vector->rx.total_packets = 0; 4368 q_vector->tx.total_bytes = 0; 4369 q_vector->tx.total_packets = 0; 4370} 4371 4372/** 4373 * igb_update_itr - update the dynamic ITR value based on statistics 4374 * @q_vector: pointer to q_vector 4375 * @ring_container: ring info to update the itr for 4376 * 4377 * Stores a new ITR value based on packets and byte 4378 * counts during the last interrupt. The advantage of per interrupt 4379 * computation is faster updates and more accurate ITR for the current 4380 * traffic pattern. Constants in this function were computed 4381 * based on theoretical maximum wire speed and thresholds were set based 4382 * on testing data as well as attempting to minimize response time 4383 * while increasing bulk throughput. 4384 * this functionality is controlled by the InterruptThrottleRate module 4385 * parameter (see igb_param.c) 4386 * NOTE: These calculations are only valid when operating in a single- 4387 * queue environment. 4388 **/ 4389static void igb_update_itr(struct igb_q_vector *q_vector, 4390 struct igb_ring_container *ring_container) 4391{ 4392 unsigned int packets = ring_container->total_packets; 4393 unsigned int bytes = ring_container->total_bytes; 4394 u8 itrval = ring_container->itr; 4395 4396 /* no packets, exit with status unchanged */ 4397 if (packets == 0) 4398 return; 4399 4400 switch (itrval) { 4401 case lowest_latency: 4402 /* handle TSO and jumbo frames */ 4403 if (bytes/packets > 8000) 4404 itrval = bulk_latency; 4405 else if ((packets < 5) && (bytes > 512)) 4406 itrval = low_latency; 4407 break; 4408 case low_latency: /* 50 usec aka 20000 ints/s */ 4409 if (bytes > 10000) { 4410 /* this if handles the TSO accounting */ 4411 if (bytes/packets > 8000) { 4412 itrval = bulk_latency; 4413 } else if ((packets < 10) || ((bytes/packets) > 1200)) { 4414 itrval = bulk_latency; 4415 } else if ((packets > 35)) { 4416 itrval = lowest_latency; 4417 } 4418 } else if (bytes/packets > 2000) { 4419 itrval = bulk_latency; 4420 } else if (packets <= 2 && bytes < 512) { 4421 itrval = lowest_latency; 4422 } 4423 break; 4424 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4425 if (bytes > 25000) { 4426 if (packets > 35) 4427 itrval = low_latency; 4428 } else if (bytes < 1500) { 4429 itrval = low_latency; 4430 } 4431 break; 4432 } 4433 4434 /* clear work counters since we have the values we need */ 4435 ring_container->total_bytes = 0; 4436 ring_container->total_packets = 0; 4437 4438 /* write updated itr to ring container */ 4439 ring_container->itr = itrval; 4440} 4441 4442static void igb_set_itr(struct igb_q_vector *q_vector) 4443{ 4444 struct igb_adapter *adapter = q_vector->adapter; 4445 u32 new_itr = q_vector->itr_val; 4446 u8 current_itr = 0; 4447 4448 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4449 if (adapter->link_speed != SPEED_1000) { 4450 current_itr = 0; 4451 new_itr = IGB_4K_ITR; 4452 goto set_itr_now; 4453 } 4454 4455 igb_update_itr(q_vector, &q_vector->tx); 4456 igb_update_itr(q_vector, &q_vector->rx); 4457 4458 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4459 4460 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4461 if (current_itr == lowest_latency && 4462 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4463 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4464 current_itr = low_latency; 4465 4466 switch (current_itr) { 4467 /* counts and packets in update_itr are dependent on these numbers */ 4468 case lowest_latency: 4469 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4470 break; 4471 case low_latency: 4472 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4473 break; 4474 case bulk_latency: 4475 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4476 break; 4477 default: 4478 break; 4479 } 4480 4481set_itr_now: 4482 if (new_itr != q_vector->itr_val) { 4483 /* this attempts to bias the interrupt rate towards Bulk 4484 * by adding intermediate steps when interrupt rate is 4485 * increasing 4486 */ 4487 new_itr = new_itr > q_vector->itr_val ? 4488 max((new_itr * q_vector->itr_val) / 4489 (new_itr + (q_vector->itr_val >> 2)), 4490 new_itr) : new_itr; 4491 /* Don't write the value here; it resets the adapter's 4492 * internal timer, and causes us to delay far longer than 4493 * we should between interrupts. Instead, we write the ITR 4494 * value at the beginning of the next interrupt so the timing 4495 * ends up being correct. 4496 */ 4497 q_vector->itr_val = new_itr; 4498 q_vector->set_itr = 1; 4499 } 4500} 4501 4502static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4503 u32 type_tucmd, u32 mss_l4len_idx) 4504{ 4505 struct e1000_adv_tx_context_desc *context_desc; 4506 u16 i = tx_ring->next_to_use; 4507 4508 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4509 4510 i++; 4511 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4512 4513 /* set bits to identify this as an advanced context descriptor */ 4514 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4515 4516 /* For 82575, context index must be unique per ring. */ 4517 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4518 mss_l4len_idx |= tx_ring->reg_idx << 4; 4519 4520 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4521 context_desc->seqnum_seed = 0; 4522 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4523 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4524} 4525 4526static int igb_tso(struct igb_ring *tx_ring, 4527 struct igb_tx_buffer *first, 4528 u8 *hdr_len) 4529{ 4530 struct sk_buff *skb = first->skb; 4531 u32 vlan_macip_lens, type_tucmd; 4532 u32 mss_l4len_idx, l4len; 4533 4534 if (skb->ip_summed != CHECKSUM_PARTIAL) 4535 return 0; 4536 4537 if (!skb_is_gso(skb)) 4538 return 0; 4539 4540 if (skb_header_cloned(skb)) { 4541 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 4542 if (err) 4543 return err; 4544 } 4545 4546 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4547 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4548 4549 if (first->protocol == __constant_htons(ETH_P_IP)) { 4550 struct iphdr *iph = ip_hdr(skb); 4551 iph->tot_len = 0; 4552 iph->check = 0; 4553 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4554 iph->daddr, 0, 4555 IPPROTO_TCP, 4556 0); 4557 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4558 first->tx_flags |= IGB_TX_FLAGS_TSO | 4559 IGB_TX_FLAGS_CSUM | 4560 IGB_TX_FLAGS_IPV4; 4561 } else if (skb_is_gso_v6(skb)) { 4562 ipv6_hdr(skb)->payload_len = 0; 4563 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4564 &ipv6_hdr(skb)->daddr, 4565 0, IPPROTO_TCP, 0); 4566 first->tx_flags |= IGB_TX_FLAGS_TSO | 4567 IGB_TX_FLAGS_CSUM; 4568 } 4569 4570 /* compute header lengths */ 4571 l4len = tcp_hdrlen(skb); 4572 *hdr_len = skb_transport_offset(skb) + l4len; 4573 4574 /* update gso size and bytecount with header size */ 4575 first->gso_segs = skb_shinfo(skb)->gso_segs; 4576 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4577 4578 /* MSS L4LEN IDX */ 4579 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4580 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4581 4582 /* VLAN MACLEN IPLEN */ 4583 vlan_macip_lens = skb_network_header_len(skb); 4584 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4585 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4586 4587 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4588 4589 return 1; 4590} 4591 4592static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4593{ 4594 struct sk_buff *skb = first->skb; 4595 u32 vlan_macip_lens = 0; 4596 u32 mss_l4len_idx = 0; 4597 u32 type_tucmd = 0; 4598 4599 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4600 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4601 return; 4602 } else { 4603 u8 l4_hdr = 0; 4604 switch (first->protocol) { 4605 case __constant_htons(ETH_P_IP): 4606 vlan_macip_lens |= skb_network_header_len(skb); 4607 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4608 l4_hdr = ip_hdr(skb)->protocol; 4609 break; 4610 case __constant_htons(ETH_P_IPV6): 4611 vlan_macip_lens |= skb_network_header_len(skb); 4612 l4_hdr = ipv6_hdr(skb)->nexthdr; 4613 break; 4614 default: 4615 if (unlikely(net_ratelimit())) { 4616 dev_warn(tx_ring->dev, 4617 "partial checksum but proto=%x!\n", 4618 first->protocol); 4619 } 4620 break; 4621 } 4622 4623 switch (l4_hdr) { 4624 case IPPROTO_TCP: 4625 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4626 mss_l4len_idx = tcp_hdrlen(skb) << 4627 E1000_ADVTXD_L4LEN_SHIFT; 4628 break; 4629 case IPPROTO_SCTP: 4630 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4631 mss_l4len_idx = sizeof(struct sctphdr) << 4632 E1000_ADVTXD_L4LEN_SHIFT; 4633 break; 4634 case IPPROTO_UDP: 4635 mss_l4len_idx = sizeof(struct udphdr) << 4636 E1000_ADVTXD_L4LEN_SHIFT; 4637 break; 4638 default: 4639 if (unlikely(net_ratelimit())) { 4640 dev_warn(tx_ring->dev, 4641 "partial checksum but l4 proto=%x!\n", 4642 l4_hdr); 4643 } 4644 break; 4645 } 4646 4647 /* update TX checksum flag */ 4648 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4649 } 4650 4651 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4652 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4653 4654 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4655} 4656 4657#define IGB_SET_FLAG(_input, _flag, _result) \ 4658 ((_flag <= _result) ? \ 4659 ((u32)(_input & _flag) * (_result / _flag)) : \ 4660 ((u32)(_input & _flag) / (_flag / _result))) 4661 4662static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 4663{ 4664 /* set type for advanced descriptor with frame checksum insertion */ 4665 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 4666 E1000_ADVTXD_DCMD_DEXT | 4667 E1000_ADVTXD_DCMD_IFCS; 4668 4669 /* set HW vlan bit if vlan is present */ 4670 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 4671 (E1000_ADVTXD_DCMD_VLE)); 4672 4673 /* set segmentation bits for TSO */ 4674 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 4675 (E1000_ADVTXD_DCMD_TSE)); 4676 4677 /* set timestamp bit if present */ 4678 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 4679 (E1000_ADVTXD_MAC_TSTAMP)); 4680 4681 /* insert frame checksum */ 4682 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 4683 4684 return cmd_type; 4685} 4686 4687static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4688 union e1000_adv_tx_desc *tx_desc, 4689 u32 tx_flags, unsigned int paylen) 4690{ 4691 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4692 4693 /* 82575 requires a unique index per ring */ 4694 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4695 olinfo_status |= tx_ring->reg_idx << 4; 4696 4697 /* insert L4 checksum */ 4698 olinfo_status |= IGB_SET_FLAG(tx_flags, 4699 IGB_TX_FLAGS_CSUM, 4700 (E1000_TXD_POPTS_TXSM << 8)); 4701 4702 /* insert IPv4 checksum */ 4703 olinfo_status |= IGB_SET_FLAG(tx_flags, 4704 IGB_TX_FLAGS_IPV4, 4705 (E1000_TXD_POPTS_IXSM << 8)); 4706 4707 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4708} 4709 4710static void igb_tx_map(struct igb_ring *tx_ring, 4711 struct igb_tx_buffer *first, 4712 const u8 hdr_len) 4713{ 4714 struct sk_buff *skb = first->skb; 4715 struct igb_tx_buffer *tx_buffer; 4716 union e1000_adv_tx_desc *tx_desc; 4717 struct skb_frag_struct *frag; 4718 dma_addr_t dma; 4719 unsigned int data_len, size; 4720 u32 tx_flags = first->tx_flags; 4721 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 4722 u16 i = tx_ring->next_to_use; 4723 4724 tx_desc = IGB_TX_DESC(tx_ring, i); 4725 4726 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 4727 4728 size = skb_headlen(skb); 4729 data_len = skb->data_len; 4730 4731 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4732 4733 tx_buffer = first; 4734 4735 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 4736 if (dma_mapping_error(tx_ring->dev, dma)) 4737 goto dma_error; 4738 4739 /* record length, and DMA address */ 4740 dma_unmap_len_set(tx_buffer, len, size); 4741 dma_unmap_addr_set(tx_buffer, dma, dma); 4742 4743 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4744 4745 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4746 tx_desc->read.cmd_type_len = 4747 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 4748 4749 i++; 4750 tx_desc++; 4751 if (i == tx_ring->count) { 4752 tx_desc = IGB_TX_DESC(tx_ring, 0); 4753 i = 0; 4754 } 4755 tx_desc->read.olinfo_status = 0; 4756 4757 dma += IGB_MAX_DATA_PER_TXD; 4758 size -= IGB_MAX_DATA_PER_TXD; 4759 4760 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4761 } 4762 4763 if (likely(!data_len)) 4764 break; 4765 4766 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 4767 4768 i++; 4769 tx_desc++; 4770 if (i == tx_ring->count) { 4771 tx_desc = IGB_TX_DESC(tx_ring, 0); 4772 i = 0; 4773 } 4774 tx_desc->read.olinfo_status = 0; 4775 4776 size = skb_frag_size(frag); 4777 data_len -= size; 4778 4779 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4780 size, DMA_TO_DEVICE); 4781 4782 tx_buffer = &tx_ring->tx_buffer_info[i]; 4783 } 4784 4785 /* write last descriptor with RS and EOP bits */ 4786 cmd_type |= size | IGB_TXD_DCMD; 4787 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 4788 4789 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4790 4791 /* set the timestamp */ 4792 first->time_stamp = jiffies; 4793 4794 /* Force memory writes to complete before letting h/w know there 4795 * are new descriptors to fetch. (Only applicable for weak-ordered 4796 * memory model archs, such as IA-64). 4797 * 4798 * We also need this memory barrier to make certain all of the 4799 * status bits have been updated before next_to_watch is written. 4800 */ 4801 wmb(); 4802 4803 /* set next_to_watch value indicating a packet is present */ 4804 first->next_to_watch = tx_desc; 4805 4806 i++; 4807 if (i == tx_ring->count) 4808 i = 0; 4809 4810 tx_ring->next_to_use = i; 4811 4812 writel(i, tx_ring->tail); 4813 4814 /* we need this if more than one processor can write to our tail 4815 * at a time, it synchronizes IO on IA64/Altix systems 4816 */ 4817 mmiowb(); 4818 4819 return; 4820 4821dma_error: 4822 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4823 4824 /* clear dma mappings for failed tx_buffer_info map */ 4825 for (;;) { 4826 tx_buffer = &tx_ring->tx_buffer_info[i]; 4827 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4828 if (tx_buffer == first) 4829 break; 4830 if (i == 0) 4831 i = tx_ring->count; 4832 i--; 4833 } 4834 4835 tx_ring->next_to_use = i; 4836} 4837 4838static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4839{ 4840 struct net_device *netdev = tx_ring->netdev; 4841 4842 netif_stop_subqueue(netdev, tx_ring->queue_index); 4843 4844 /* Herbert's original patch had: 4845 * smp_mb__after_netif_stop_queue(); 4846 * but since that doesn't exist yet, just open code it. 4847 */ 4848 smp_mb(); 4849 4850 /* We need to check again in a case another CPU has just 4851 * made room available. 4852 */ 4853 if (igb_desc_unused(tx_ring) < size) 4854 return -EBUSY; 4855 4856 /* A reprieve! */ 4857 netif_wake_subqueue(netdev, tx_ring->queue_index); 4858 4859 u64_stats_update_begin(&tx_ring->tx_syncp2); 4860 tx_ring->tx_stats.restart_queue2++; 4861 u64_stats_update_end(&tx_ring->tx_syncp2); 4862 4863 return 0; 4864} 4865 4866static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4867{ 4868 if (igb_desc_unused(tx_ring) >= size) 4869 return 0; 4870 return __igb_maybe_stop_tx(tx_ring, size); 4871} 4872 4873netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4874 struct igb_ring *tx_ring) 4875{ 4876 struct igb_tx_buffer *first; 4877 int tso; 4878 u32 tx_flags = 0; 4879 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 4880 __be16 protocol = vlan_get_protocol(skb); 4881 u8 hdr_len = 0; 4882 4883 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 4884 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 4885 * + 2 desc gap to keep tail from touching head, 4886 * + 1 desc for context descriptor, 4887 * otherwise try next time 4888 */ 4889 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) { 4890 unsigned short f; 4891 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 4892 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 4893 } else { 4894 count += skb_shinfo(skb)->nr_frags; 4895 } 4896 4897 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 4898 /* this is a hard error */ 4899 return NETDEV_TX_BUSY; 4900 } 4901 4902 /* record the location of the first descriptor for this packet */ 4903 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 4904 first->skb = skb; 4905 first->bytecount = skb->len; 4906 first->gso_segs = 1; 4907 4908 skb_tx_timestamp(skb); 4909 4910 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 4911 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 4912 4913 if (!(adapter->ptp_tx_skb)) { 4914 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4915 tx_flags |= IGB_TX_FLAGS_TSTAMP; 4916 4917 adapter->ptp_tx_skb = skb_get(skb); 4918 adapter->ptp_tx_start = jiffies; 4919 if (adapter->hw.mac.type == e1000_82576) 4920 schedule_work(&adapter->ptp_tx_work); 4921 } 4922 } 4923 4924 if (vlan_tx_tag_present(skb)) { 4925 tx_flags |= IGB_TX_FLAGS_VLAN; 4926 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 4927 } 4928 4929 /* record initial flags and protocol */ 4930 first->tx_flags = tx_flags; 4931 first->protocol = protocol; 4932 4933 tso = igb_tso(tx_ring, first, &hdr_len); 4934 if (tso < 0) 4935 goto out_drop; 4936 else if (!tso) 4937 igb_tx_csum(tx_ring, first); 4938 4939 igb_tx_map(tx_ring, first, hdr_len); 4940 4941 /* Make sure there is space in the ring for the next send. */ 4942 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 4943 4944 return NETDEV_TX_OK; 4945 4946out_drop: 4947 igb_unmap_and_free_tx_resource(tx_ring, first); 4948 4949 return NETDEV_TX_OK; 4950} 4951 4952static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 4953 struct sk_buff *skb) 4954{ 4955 unsigned int r_idx = skb->queue_mapping; 4956 4957 if (r_idx >= adapter->num_tx_queues) 4958 r_idx = r_idx % adapter->num_tx_queues; 4959 4960 return adapter->tx_ring[r_idx]; 4961} 4962 4963static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 4964 struct net_device *netdev) 4965{ 4966 struct igb_adapter *adapter = netdev_priv(netdev); 4967 4968 if (test_bit(__IGB_DOWN, &adapter->state)) { 4969 dev_kfree_skb_any(skb); 4970 return NETDEV_TX_OK; 4971 } 4972 4973 if (skb->len <= 0) { 4974 dev_kfree_skb_any(skb); 4975 return NETDEV_TX_OK; 4976 } 4977 4978 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 4979 * in order to meet this minimum size requirement. 4980 */ 4981 if (unlikely(skb->len < 17)) { 4982 if (skb_pad(skb, 17 - skb->len)) 4983 return NETDEV_TX_OK; 4984 skb->len = 17; 4985 skb_set_tail_pointer(skb, 17); 4986 } 4987 4988 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 4989} 4990 4991/** 4992 * igb_tx_timeout - Respond to a Tx Hang 4993 * @netdev: network interface device structure 4994 **/ 4995static void igb_tx_timeout(struct net_device *netdev) 4996{ 4997 struct igb_adapter *adapter = netdev_priv(netdev); 4998 struct e1000_hw *hw = &adapter->hw; 4999 5000 /* Do the reset outside of interrupt context */ 5001 adapter->tx_timeout_count++; 5002 5003 if (hw->mac.type >= e1000_82580) 5004 hw->dev_spec._82575.global_device_reset = true; 5005 5006 schedule_work(&adapter->reset_task); 5007 wr32(E1000_EICS, 5008 (adapter->eims_enable_mask & ~adapter->eims_other)); 5009} 5010 5011static void igb_reset_task(struct work_struct *work) 5012{ 5013 struct igb_adapter *adapter; 5014 adapter = container_of(work, struct igb_adapter, reset_task); 5015 5016 igb_dump(adapter); 5017 netdev_err(adapter->netdev, "Reset adapter\n"); 5018 igb_reinit_locked(adapter); 5019} 5020 5021/** 5022 * igb_get_stats64 - Get System Network Statistics 5023 * @netdev: network interface device structure 5024 * @stats: rtnl_link_stats64 pointer 5025 **/ 5026static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 5027 struct rtnl_link_stats64 *stats) 5028{ 5029 struct igb_adapter *adapter = netdev_priv(netdev); 5030 5031 spin_lock(&adapter->stats64_lock); 5032 igb_update_stats(adapter, &adapter->stats64); 5033 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5034 spin_unlock(&adapter->stats64_lock); 5035 5036 return stats; 5037} 5038 5039/** 5040 * igb_change_mtu - Change the Maximum Transfer Unit 5041 * @netdev: network interface device structure 5042 * @new_mtu: new value for maximum frame size 5043 * 5044 * Returns 0 on success, negative on failure 5045 **/ 5046static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5047{ 5048 struct igb_adapter *adapter = netdev_priv(netdev); 5049 struct pci_dev *pdev = adapter->pdev; 5050 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5051 5052 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 5053 dev_err(&pdev->dev, "Invalid MTU setting\n"); 5054 return -EINVAL; 5055 } 5056 5057#define MAX_STD_JUMBO_FRAME_SIZE 9238 5058 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 5059 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 5060 return -EINVAL; 5061 } 5062 5063 /* adjust max frame to be at least the size of a standard frame */ 5064 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5065 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5066 5067 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5068 msleep(1); 5069 5070 /* igb_down has a dependency on max_frame_size */ 5071 adapter->max_frame_size = max_frame; 5072 5073 if (netif_running(netdev)) 5074 igb_down(adapter); 5075 5076 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5077 netdev->mtu, new_mtu); 5078 netdev->mtu = new_mtu; 5079 5080 if (netif_running(netdev)) 5081 igb_up(adapter); 5082 else 5083 igb_reset(adapter); 5084 5085 clear_bit(__IGB_RESETTING, &adapter->state); 5086 5087 return 0; 5088} 5089 5090/** 5091 * igb_update_stats - Update the board statistics counters 5092 * @adapter: board private structure 5093 **/ 5094void igb_update_stats(struct igb_adapter *adapter, 5095 struct rtnl_link_stats64 *net_stats) 5096{ 5097 struct e1000_hw *hw = &adapter->hw; 5098 struct pci_dev *pdev = adapter->pdev; 5099 u32 reg, mpc; 5100 u16 phy_tmp; 5101 int i; 5102 u64 bytes, packets; 5103 unsigned int start; 5104 u64 _bytes, _packets; 5105 5106#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF 5107 5108 /* Prevent stats update while adapter is being reset, or if the pci 5109 * connection is down. 5110 */ 5111 if (adapter->link_speed == 0) 5112 return; 5113 if (pci_channel_offline(pdev)) 5114 return; 5115 5116 bytes = 0; 5117 packets = 0; 5118 5119 rcu_read_lock(); 5120 for (i = 0; i < adapter->num_rx_queues; i++) { 5121 u32 rqdpc = rd32(E1000_RQDPC(i)); 5122 struct igb_ring *ring = adapter->rx_ring[i]; 5123 5124 if (rqdpc) { 5125 ring->rx_stats.drops += rqdpc; 5126 net_stats->rx_fifo_errors += rqdpc; 5127 } 5128 5129 do { 5130 start = u64_stats_fetch_begin_bh(&ring->rx_syncp); 5131 _bytes = ring->rx_stats.bytes; 5132 _packets = ring->rx_stats.packets; 5133 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); 5134 bytes += _bytes; 5135 packets += _packets; 5136 } 5137 5138 net_stats->rx_bytes = bytes; 5139 net_stats->rx_packets = packets; 5140 5141 bytes = 0; 5142 packets = 0; 5143 for (i = 0; i < adapter->num_tx_queues; i++) { 5144 struct igb_ring *ring = adapter->tx_ring[i]; 5145 do { 5146 start = u64_stats_fetch_begin_bh(&ring->tx_syncp); 5147 _bytes = ring->tx_stats.bytes; 5148 _packets = ring->tx_stats.packets; 5149 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); 5150 bytes += _bytes; 5151 packets += _packets; 5152 } 5153 net_stats->tx_bytes = bytes; 5154 net_stats->tx_packets = packets; 5155 rcu_read_unlock(); 5156 5157 /* read stats registers */ 5158 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5159 adapter->stats.gprc += rd32(E1000_GPRC); 5160 adapter->stats.gorc += rd32(E1000_GORCL); 5161 rd32(E1000_GORCH); /* clear GORCL */ 5162 adapter->stats.bprc += rd32(E1000_BPRC); 5163 adapter->stats.mprc += rd32(E1000_MPRC); 5164 adapter->stats.roc += rd32(E1000_ROC); 5165 5166 adapter->stats.prc64 += rd32(E1000_PRC64); 5167 adapter->stats.prc127 += rd32(E1000_PRC127); 5168 adapter->stats.prc255 += rd32(E1000_PRC255); 5169 adapter->stats.prc511 += rd32(E1000_PRC511); 5170 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5171 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5172 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5173 adapter->stats.sec += rd32(E1000_SEC); 5174 5175 mpc = rd32(E1000_MPC); 5176 adapter->stats.mpc += mpc; 5177 net_stats->rx_fifo_errors += mpc; 5178 adapter->stats.scc += rd32(E1000_SCC); 5179 adapter->stats.ecol += rd32(E1000_ECOL); 5180 adapter->stats.mcc += rd32(E1000_MCC); 5181 adapter->stats.latecol += rd32(E1000_LATECOL); 5182 adapter->stats.dc += rd32(E1000_DC); 5183 adapter->stats.rlec += rd32(E1000_RLEC); 5184 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5185 adapter->stats.xontxc += rd32(E1000_XONTXC); 5186 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5187 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5188 adapter->stats.fcruc += rd32(E1000_FCRUC); 5189 adapter->stats.gptc += rd32(E1000_GPTC); 5190 adapter->stats.gotc += rd32(E1000_GOTCL); 5191 rd32(E1000_GOTCH); /* clear GOTCL */ 5192 adapter->stats.rnbc += rd32(E1000_RNBC); 5193 adapter->stats.ruc += rd32(E1000_RUC); 5194 adapter->stats.rfc += rd32(E1000_RFC); 5195 adapter->stats.rjc += rd32(E1000_RJC); 5196 adapter->stats.tor += rd32(E1000_TORH); 5197 adapter->stats.tot += rd32(E1000_TOTH); 5198 adapter->stats.tpr += rd32(E1000_TPR); 5199 5200 adapter->stats.ptc64 += rd32(E1000_PTC64); 5201 adapter->stats.ptc127 += rd32(E1000_PTC127); 5202 adapter->stats.ptc255 += rd32(E1000_PTC255); 5203 adapter->stats.ptc511 += rd32(E1000_PTC511); 5204 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5205 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5206 5207 adapter->stats.mptc += rd32(E1000_MPTC); 5208 adapter->stats.bptc += rd32(E1000_BPTC); 5209 5210 adapter->stats.tpt += rd32(E1000_TPT); 5211 adapter->stats.colc += rd32(E1000_COLC); 5212 5213 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5214 /* read internal phy specific stats */ 5215 reg = rd32(E1000_CTRL_EXT); 5216 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5217 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5218 5219 /* this stat has invalid values on i210/i211 */ 5220 if ((hw->mac.type != e1000_i210) && 5221 (hw->mac.type != e1000_i211)) 5222 adapter->stats.tncrs += rd32(E1000_TNCRS); 5223 } 5224 5225 adapter->stats.tsctc += rd32(E1000_TSCTC); 5226 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5227 5228 adapter->stats.iac += rd32(E1000_IAC); 5229 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5230 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5231 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5232 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5233 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5234 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5235 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5236 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5237 5238 /* Fill out the OS statistics structure */ 5239 net_stats->multicast = adapter->stats.mprc; 5240 net_stats->collisions = adapter->stats.colc; 5241 5242 /* Rx Errors */ 5243 5244 /* RLEC on some newer hardware can be incorrect so build 5245 * our own version based on RUC and ROC 5246 */ 5247 net_stats->rx_errors = adapter->stats.rxerrc + 5248 adapter->stats.crcerrs + adapter->stats.algnerrc + 5249 adapter->stats.ruc + adapter->stats.roc + 5250 adapter->stats.cexterr; 5251 net_stats->rx_length_errors = adapter->stats.ruc + 5252 adapter->stats.roc; 5253 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5254 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5255 net_stats->rx_missed_errors = adapter->stats.mpc; 5256 5257 /* Tx Errors */ 5258 net_stats->tx_errors = adapter->stats.ecol + 5259 adapter->stats.latecol; 5260 net_stats->tx_aborted_errors = adapter->stats.ecol; 5261 net_stats->tx_window_errors = adapter->stats.latecol; 5262 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5263 5264 /* Tx Dropped needs to be maintained elsewhere */ 5265 5266 /* Phy Stats */ 5267 if (hw->phy.media_type == e1000_media_type_copper) { 5268 if ((adapter->link_speed == SPEED_1000) && 5269 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 5270 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; 5271 adapter->phy_stats.idle_errors += phy_tmp; 5272 } 5273 } 5274 5275 /* Management Stats */ 5276 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5277 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5278 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5279 5280 /* OS2BMC Stats */ 5281 reg = rd32(E1000_MANC); 5282 if (reg & E1000_MANC_EN_BMC2OS) { 5283 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5284 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5285 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5286 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5287 } 5288} 5289 5290static irqreturn_t igb_msix_other(int irq, void *data) 5291{ 5292 struct igb_adapter *adapter = data; 5293 struct e1000_hw *hw = &adapter->hw; 5294 u32 icr = rd32(E1000_ICR); 5295 /* reading ICR causes bit 31 of EICR to be cleared */ 5296 5297 if (icr & E1000_ICR_DRSTA) 5298 schedule_work(&adapter->reset_task); 5299 5300 if (icr & E1000_ICR_DOUTSYNC) { 5301 /* HW is reporting DMA is out of sync */ 5302 adapter->stats.doosync++; 5303 /* The DMA Out of Sync is also indication of a spoof event 5304 * in IOV mode. Check the Wrong VM Behavior register to 5305 * see if it is really a spoof event. 5306 */ 5307 igb_check_wvbr(adapter); 5308 } 5309 5310 /* Check for a mailbox event */ 5311 if (icr & E1000_ICR_VMMB) 5312 igb_msg_task(adapter); 5313 5314 if (icr & E1000_ICR_LSC) { 5315 hw->mac.get_link_status = 1; 5316 /* guard against interrupt when we're going down */ 5317 if (!test_bit(__IGB_DOWN, &adapter->state)) 5318 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5319 } 5320 5321 if (icr & E1000_ICR_TS) { 5322 u32 tsicr = rd32(E1000_TSICR); 5323 5324 if (tsicr & E1000_TSICR_TXTS) { 5325 /* acknowledge the interrupt */ 5326 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5327 /* retrieve hardware timestamp */ 5328 schedule_work(&adapter->ptp_tx_work); 5329 } 5330 } 5331 5332 wr32(E1000_EIMS, adapter->eims_other); 5333 5334 return IRQ_HANDLED; 5335} 5336 5337static void igb_write_itr(struct igb_q_vector *q_vector) 5338{ 5339 struct igb_adapter *adapter = q_vector->adapter; 5340 u32 itr_val = q_vector->itr_val & 0x7FFC; 5341 5342 if (!q_vector->set_itr) 5343 return; 5344 5345 if (!itr_val) 5346 itr_val = 0x4; 5347 5348 if (adapter->hw.mac.type == e1000_82575) 5349 itr_val |= itr_val << 16; 5350 else 5351 itr_val |= E1000_EITR_CNT_IGNR; 5352 5353 writel(itr_val, q_vector->itr_register); 5354 q_vector->set_itr = 0; 5355} 5356 5357static irqreturn_t igb_msix_ring(int irq, void *data) 5358{ 5359 struct igb_q_vector *q_vector = data; 5360 5361 /* Write the ITR value calculated from the previous interrupt. */ 5362 igb_write_itr(q_vector); 5363 5364 napi_schedule(&q_vector->napi); 5365 5366 return IRQ_HANDLED; 5367} 5368 5369#ifdef CONFIG_IGB_DCA 5370static void igb_update_tx_dca(struct igb_adapter *adapter, 5371 struct igb_ring *tx_ring, 5372 int cpu) 5373{ 5374 struct e1000_hw *hw = &adapter->hw; 5375 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5376 5377 if (hw->mac.type != e1000_82575) 5378 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5379 5380 /* We can enable relaxed ordering for reads, but not writes when 5381 * DCA is enabled. This is due to a known issue in some chipsets 5382 * which will cause the DCA tag to be cleared. 5383 */ 5384 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5385 E1000_DCA_TXCTRL_DATA_RRO_EN | 5386 E1000_DCA_TXCTRL_DESC_DCA_EN; 5387 5388 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5389} 5390 5391static void igb_update_rx_dca(struct igb_adapter *adapter, 5392 struct igb_ring *rx_ring, 5393 int cpu) 5394{ 5395 struct e1000_hw *hw = &adapter->hw; 5396 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5397 5398 if (hw->mac.type != e1000_82575) 5399 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5400 5401 /* We can enable relaxed ordering for reads, but not writes when 5402 * DCA is enabled. This is due to a known issue in some chipsets 5403 * which will cause the DCA tag to be cleared. 5404 */ 5405 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5406 E1000_DCA_RXCTRL_DESC_DCA_EN; 5407 5408 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5409} 5410 5411static void igb_update_dca(struct igb_q_vector *q_vector) 5412{ 5413 struct igb_adapter *adapter = q_vector->adapter; 5414 int cpu = get_cpu(); 5415 5416 if (q_vector->cpu == cpu) 5417 goto out_no_update; 5418 5419 if (q_vector->tx.ring) 5420 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5421 5422 if (q_vector->rx.ring) 5423 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5424 5425 q_vector->cpu = cpu; 5426out_no_update: 5427 put_cpu(); 5428} 5429 5430static void igb_setup_dca(struct igb_adapter *adapter) 5431{ 5432 struct e1000_hw *hw = &adapter->hw; 5433 int i; 5434 5435 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5436 return; 5437 5438 /* Always use CB2 mode, difference is masked in the CB driver. */ 5439 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5440 5441 for (i = 0; i < adapter->num_q_vectors; i++) { 5442 adapter->q_vector[i]->cpu = -1; 5443 igb_update_dca(adapter->q_vector[i]); 5444 } 5445} 5446 5447static int __igb_notify_dca(struct device *dev, void *data) 5448{ 5449 struct net_device *netdev = dev_get_drvdata(dev); 5450 struct igb_adapter *adapter = netdev_priv(netdev); 5451 struct pci_dev *pdev = adapter->pdev; 5452 struct e1000_hw *hw = &adapter->hw; 5453 unsigned long event = *(unsigned long *)data; 5454 5455 switch (event) { 5456 case DCA_PROVIDER_ADD: 5457 /* if already enabled, don't do it again */ 5458 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5459 break; 5460 if (dca_add_requester(dev) == 0) { 5461 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5462 dev_info(&pdev->dev, "DCA enabled\n"); 5463 igb_setup_dca(adapter); 5464 break; 5465 } 5466 /* Fall Through since DCA is disabled. */ 5467 case DCA_PROVIDER_REMOVE: 5468 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5469 /* without this a class_device is left 5470 * hanging around in the sysfs model 5471 */ 5472 dca_remove_requester(dev); 5473 dev_info(&pdev->dev, "DCA disabled\n"); 5474 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5475 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5476 } 5477 break; 5478 } 5479 5480 return 0; 5481} 5482 5483static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5484 void *p) 5485{ 5486 int ret_val; 5487 5488 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5489 __igb_notify_dca); 5490 5491 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5492} 5493#endif /* CONFIG_IGB_DCA */ 5494 5495#ifdef CONFIG_PCI_IOV 5496static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5497{ 5498 unsigned char mac_addr[ETH_ALEN]; 5499 5500 eth_zero_addr(mac_addr); 5501 igb_set_vf_mac(adapter, vf, mac_addr); 5502 5503 /* By default spoof check is enabled for all VFs */ 5504 adapter->vf_data[vf].spoofchk_enabled = true; 5505 5506 return 0; 5507} 5508 5509#endif 5510static void igb_ping_all_vfs(struct igb_adapter *adapter) 5511{ 5512 struct e1000_hw *hw = &adapter->hw; 5513 u32 ping; 5514 int i; 5515 5516 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5517 ping = E1000_PF_CONTROL_MSG; 5518 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5519 ping |= E1000_VT_MSGTYPE_CTS; 5520 igb_write_mbx(hw, &ping, 1, i); 5521 } 5522} 5523 5524static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5525{ 5526 struct e1000_hw *hw = &adapter->hw; 5527 u32 vmolr = rd32(E1000_VMOLR(vf)); 5528 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5529 5530 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5531 IGB_VF_FLAG_MULTI_PROMISC); 5532 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5533 5534 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5535 vmolr |= E1000_VMOLR_MPME; 5536 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5537 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5538 } else { 5539 /* if we have hashes and we are clearing a multicast promisc 5540 * flag we need to write the hashes to the MTA as this step 5541 * was previously skipped 5542 */ 5543 if (vf_data->num_vf_mc_hashes > 30) { 5544 vmolr |= E1000_VMOLR_MPME; 5545 } else if (vf_data->num_vf_mc_hashes) { 5546 int j; 5547 vmolr |= E1000_VMOLR_ROMPE; 5548 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5549 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5550 } 5551 } 5552 5553 wr32(E1000_VMOLR(vf), vmolr); 5554 5555 /* there are flags left unprocessed, likely not supported */ 5556 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5557 return -EINVAL; 5558 5559 return 0; 5560} 5561 5562static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5563 u32 *msgbuf, u32 vf) 5564{ 5565 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5566 u16 *hash_list = (u16 *)&msgbuf[1]; 5567 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5568 int i; 5569 5570 /* salt away the number of multicast addresses assigned 5571 * to this VF for later use to restore when the PF multi cast 5572 * list changes 5573 */ 5574 vf_data->num_vf_mc_hashes = n; 5575 5576 /* only up to 30 hash values supported */ 5577 if (n > 30) 5578 n = 30; 5579 5580 /* store the hashes for later use */ 5581 for (i = 0; i < n; i++) 5582 vf_data->vf_mc_hashes[i] = hash_list[i]; 5583 5584 /* Flush and reset the mta with the new values */ 5585 igb_set_rx_mode(adapter->netdev); 5586 5587 return 0; 5588} 5589 5590static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5591{ 5592 struct e1000_hw *hw = &adapter->hw; 5593 struct vf_data_storage *vf_data; 5594 int i, j; 5595 5596 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5597 u32 vmolr = rd32(E1000_VMOLR(i)); 5598 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5599 5600 vf_data = &adapter->vf_data[i]; 5601 5602 if ((vf_data->num_vf_mc_hashes > 30) || 5603 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5604 vmolr |= E1000_VMOLR_MPME; 5605 } else if (vf_data->num_vf_mc_hashes) { 5606 vmolr |= E1000_VMOLR_ROMPE; 5607 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5608 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5609 } 5610 wr32(E1000_VMOLR(i), vmolr); 5611 } 5612} 5613 5614static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5615{ 5616 struct e1000_hw *hw = &adapter->hw; 5617 u32 pool_mask, reg, vid; 5618 int i; 5619 5620 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5621 5622 /* Find the vlan filter for this id */ 5623 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5624 reg = rd32(E1000_VLVF(i)); 5625 5626 /* remove the vf from the pool */ 5627 reg &= ~pool_mask; 5628 5629 /* if pool is empty then remove entry from vfta */ 5630 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5631 (reg & E1000_VLVF_VLANID_ENABLE)) { 5632 reg = 0; 5633 vid = reg & E1000_VLVF_VLANID_MASK; 5634 igb_vfta_set(hw, vid, false); 5635 } 5636 5637 wr32(E1000_VLVF(i), reg); 5638 } 5639 5640 adapter->vf_data[vf].vlans_enabled = 0; 5641} 5642 5643static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5644{ 5645 struct e1000_hw *hw = &adapter->hw; 5646 u32 reg, i; 5647 5648 /* The vlvf table only exists on 82576 hardware and newer */ 5649 if (hw->mac.type < e1000_82576) 5650 return -1; 5651 5652 /* we only need to do this if VMDq is enabled */ 5653 if (!adapter->vfs_allocated_count) 5654 return -1; 5655 5656 /* Find the vlan filter for this id */ 5657 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5658 reg = rd32(E1000_VLVF(i)); 5659 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5660 vid == (reg & E1000_VLVF_VLANID_MASK)) 5661 break; 5662 } 5663 5664 if (add) { 5665 if (i == E1000_VLVF_ARRAY_SIZE) { 5666 /* Did not find a matching VLAN ID entry that was 5667 * enabled. Search for a free filter entry, i.e. 5668 * one without the enable bit set 5669 */ 5670 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5671 reg = rd32(E1000_VLVF(i)); 5672 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5673 break; 5674 } 5675 } 5676 if (i < E1000_VLVF_ARRAY_SIZE) { 5677 /* Found an enabled/available entry */ 5678 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5679 5680 /* if !enabled we need to set this up in vfta */ 5681 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5682 /* add VID to filter table */ 5683 igb_vfta_set(hw, vid, true); 5684 reg |= E1000_VLVF_VLANID_ENABLE; 5685 } 5686 reg &= ~E1000_VLVF_VLANID_MASK; 5687 reg |= vid; 5688 wr32(E1000_VLVF(i), reg); 5689 5690 /* do not modify RLPML for PF devices */ 5691 if (vf >= adapter->vfs_allocated_count) 5692 return 0; 5693 5694 if (!adapter->vf_data[vf].vlans_enabled) { 5695 u32 size; 5696 reg = rd32(E1000_VMOLR(vf)); 5697 size = reg & E1000_VMOLR_RLPML_MASK; 5698 size += 4; 5699 reg &= ~E1000_VMOLR_RLPML_MASK; 5700 reg |= size; 5701 wr32(E1000_VMOLR(vf), reg); 5702 } 5703 5704 adapter->vf_data[vf].vlans_enabled++; 5705 } 5706 } else { 5707 if (i < E1000_VLVF_ARRAY_SIZE) { 5708 /* remove vf from the pool */ 5709 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5710 /* if pool is empty then remove entry from vfta */ 5711 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5712 reg = 0; 5713 igb_vfta_set(hw, vid, false); 5714 } 5715 wr32(E1000_VLVF(i), reg); 5716 5717 /* do not modify RLPML for PF devices */ 5718 if (vf >= adapter->vfs_allocated_count) 5719 return 0; 5720 5721 adapter->vf_data[vf].vlans_enabled--; 5722 if (!adapter->vf_data[vf].vlans_enabled) { 5723 u32 size; 5724 reg = rd32(E1000_VMOLR(vf)); 5725 size = reg & E1000_VMOLR_RLPML_MASK; 5726 size -= 4; 5727 reg &= ~E1000_VMOLR_RLPML_MASK; 5728 reg |= size; 5729 wr32(E1000_VMOLR(vf), reg); 5730 } 5731 } 5732 } 5733 return 0; 5734} 5735 5736static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5737{ 5738 struct e1000_hw *hw = &adapter->hw; 5739 5740 if (vid) 5741 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5742 else 5743 wr32(E1000_VMVIR(vf), 0); 5744} 5745 5746static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5747 int vf, u16 vlan, u8 qos) 5748{ 5749 int err = 0; 5750 struct igb_adapter *adapter = netdev_priv(netdev); 5751 5752 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5753 return -EINVAL; 5754 if (vlan || qos) { 5755 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5756 if (err) 5757 goto out; 5758 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5759 igb_set_vmolr(adapter, vf, !vlan); 5760 adapter->vf_data[vf].pf_vlan = vlan; 5761 adapter->vf_data[vf].pf_qos = qos; 5762 dev_info(&adapter->pdev->dev, 5763 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5764 if (test_bit(__IGB_DOWN, &adapter->state)) { 5765 dev_warn(&adapter->pdev->dev, 5766 "The VF VLAN has been set, but the PF device is not up.\n"); 5767 dev_warn(&adapter->pdev->dev, 5768 "Bring the PF device up before attempting to use the VF device.\n"); 5769 } 5770 } else { 5771 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5772 false, vf); 5773 igb_set_vmvir(adapter, vlan, vf); 5774 igb_set_vmolr(adapter, vf, true); 5775 adapter->vf_data[vf].pf_vlan = 0; 5776 adapter->vf_data[vf].pf_qos = 0; 5777 } 5778out: 5779 return err; 5780} 5781 5782static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid) 5783{ 5784 struct e1000_hw *hw = &adapter->hw; 5785 int i; 5786 u32 reg; 5787 5788 /* Find the vlan filter for this id */ 5789 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5790 reg = rd32(E1000_VLVF(i)); 5791 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5792 vid == (reg & E1000_VLVF_VLANID_MASK)) 5793 break; 5794 } 5795 5796 if (i >= E1000_VLVF_ARRAY_SIZE) 5797 i = -1; 5798 5799 return i; 5800} 5801 5802static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5803{ 5804 struct e1000_hw *hw = &adapter->hw; 5805 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5806 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5807 int err = 0; 5808 5809 /* If in promiscuous mode we need to make sure the PF also has 5810 * the VLAN filter set. 5811 */ 5812 if (add && (adapter->netdev->flags & IFF_PROMISC)) 5813 err = igb_vlvf_set(adapter, vid, add, 5814 adapter->vfs_allocated_count); 5815 if (err) 5816 goto out; 5817 5818 err = igb_vlvf_set(adapter, vid, add, vf); 5819 5820 if (err) 5821 goto out; 5822 5823 /* Go through all the checks to see if the VLAN filter should 5824 * be wiped completely. 5825 */ 5826 if (!add && (adapter->netdev->flags & IFF_PROMISC)) { 5827 u32 vlvf, bits; 5828 5829 int regndx = igb_find_vlvf_entry(adapter, vid); 5830 if (regndx < 0) 5831 goto out; 5832 /* See if any other pools are set for this VLAN filter 5833 * entry other than the PF. 5834 */ 5835 vlvf = bits = rd32(E1000_VLVF(regndx)); 5836 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT + 5837 adapter->vfs_allocated_count); 5838 /* If the filter was removed then ensure PF pool bit 5839 * is cleared if the PF only added itself to the pool 5840 * because the PF is in promiscuous mode. 5841 */ 5842 if ((vlvf & VLAN_VID_MASK) == vid && 5843 !test_bit(vid, adapter->active_vlans) && 5844 !bits) 5845 igb_vlvf_set(adapter, vid, add, 5846 adapter->vfs_allocated_count); 5847 } 5848 5849out: 5850 return err; 5851} 5852 5853static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 5854{ 5855 /* clear flags - except flag that indicates PF has set the MAC */ 5856 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 5857 adapter->vf_data[vf].last_nack = jiffies; 5858 5859 /* reset offloads to defaults */ 5860 igb_set_vmolr(adapter, vf, true); 5861 5862 /* reset vlans for device */ 5863 igb_clear_vf_vfta(adapter, vf); 5864 if (adapter->vf_data[vf].pf_vlan) 5865 igb_ndo_set_vf_vlan(adapter->netdev, vf, 5866 adapter->vf_data[vf].pf_vlan, 5867 adapter->vf_data[vf].pf_qos); 5868 else 5869 igb_clear_vf_vfta(adapter, vf); 5870 5871 /* reset multicast table array for vf */ 5872 adapter->vf_data[vf].num_vf_mc_hashes = 0; 5873 5874 /* Flush and reset the mta with the new values */ 5875 igb_set_rx_mode(adapter->netdev); 5876} 5877 5878static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 5879{ 5880 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5881 5882 /* clear mac address as we were hotplug removed/added */ 5883 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 5884 eth_zero_addr(vf_mac); 5885 5886 /* process remaining reset events */ 5887 igb_vf_reset(adapter, vf); 5888} 5889 5890static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 5891{ 5892 struct e1000_hw *hw = &adapter->hw; 5893 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5894 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 5895 u32 reg, msgbuf[3]; 5896 u8 *addr = (u8 *)(&msgbuf[1]); 5897 5898 /* process all the same items cleared in a function level reset */ 5899 igb_vf_reset(adapter, vf); 5900 5901 /* set vf mac address */ 5902 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 5903 5904 /* enable transmit and receive for vf */ 5905 reg = rd32(E1000_VFTE); 5906 wr32(E1000_VFTE, reg | (1 << vf)); 5907 reg = rd32(E1000_VFRE); 5908 wr32(E1000_VFRE, reg | (1 << vf)); 5909 5910 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 5911 5912 /* reply to reset with ack and vf mac address */ 5913 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 5914 memcpy(addr, vf_mac, ETH_ALEN); 5915 igb_write_mbx(hw, msgbuf, 3, vf); 5916} 5917 5918static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 5919{ 5920 /* The VF MAC Address is stored in a packed array of bytes 5921 * starting at the second 32 bit word of the msg array 5922 */ 5923 unsigned char *addr = (char *)&msg[1]; 5924 int err = -1; 5925 5926 if (is_valid_ether_addr(addr)) 5927 err = igb_set_vf_mac(adapter, vf, addr); 5928 5929 return err; 5930} 5931 5932static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 5933{ 5934 struct e1000_hw *hw = &adapter->hw; 5935 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5936 u32 msg = E1000_VT_MSGTYPE_NACK; 5937 5938 /* if device isn't clear to send it shouldn't be reading either */ 5939 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 5940 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 5941 igb_write_mbx(hw, &msg, 1, vf); 5942 vf_data->last_nack = jiffies; 5943 } 5944} 5945 5946static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 5947{ 5948 struct pci_dev *pdev = adapter->pdev; 5949 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 5950 struct e1000_hw *hw = &adapter->hw; 5951 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5952 s32 retval; 5953 5954 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 5955 5956 if (retval) { 5957 /* if receive failed revoke VF CTS stats and restart init */ 5958 dev_err(&pdev->dev, "Error receiving message from VF\n"); 5959 vf_data->flags &= ~IGB_VF_FLAG_CTS; 5960 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 5961 return; 5962 goto out; 5963 } 5964 5965 /* this is a message we already processed, do nothing */ 5966 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 5967 return; 5968 5969 /* until the vf completes a reset it should not be 5970 * allowed to start any configuration. 5971 */ 5972 if (msgbuf[0] == E1000_VF_RESET) { 5973 igb_vf_reset_msg(adapter, vf); 5974 return; 5975 } 5976 5977 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 5978 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 5979 return; 5980 retval = -1; 5981 goto out; 5982 } 5983 5984 switch ((msgbuf[0] & 0xFFFF)) { 5985 case E1000_VF_SET_MAC_ADDR: 5986 retval = -EINVAL; 5987 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 5988 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 5989 else 5990 dev_warn(&pdev->dev, 5991 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 5992 vf); 5993 break; 5994 case E1000_VF_SET_PROMISC: 5995 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 5996 break; 5997 case E1000_VF_SET_MULTICAST: 5998 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 5999 break; 6000 case E1000_VF_SET_LPE: 6001 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6002 break; 6003 case E1000_VF_SET_VLAN: 6004 retval = -1; 6005 if (vf_data->pf_vlan) 6006 dev_warn(&pdev->dev, 6007 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6008 vf); 6009 else 6010 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 6011 break; 6012 default: 6013 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6014 retval = -1; 6015 break; 6016 } 6017 6018 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6019out: 6020 /* notify the VF of the results of what it sent us */ 6021 if (retval) 6022 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6023 else 6024 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6025 6026 igb_write_mbx(hw, msgbuf, 1, vf); 6027} 6028 6029static void igb_msg_task(struct igb_adapter *adapter) 6030{ 6031 struct e1000_hw *hw = &adapter->hw; 6032 u32 vf; 6033 6034 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6035 /* process any reset requests */ 6036 if (!igb_check_for_rst(hw, vf)) 6037 igb_vf_reset_event(adapter, vf); 6038 6039 /* process any messages pending */ 6040 if (!igb_check_for_msg(hw, vf)) 6041 igb_rcv_msg_from_vf(adapter, vf); 6042 6043 /* process any acks */ 6044 if (!igb_check_for_ack(hw, vf)) 6045 igb_rcv_ack_from_vf(adapter, vf); 6046 } 6047} 6048 6049/** 6050 * igb_set_uta - Set unicast filter table address 6051 * @adapter: board private structure 6052 * 6053 * The unicast table address is a register array of 32-bit registers. 6054 * The table is meant to be used in a way similar to how the MTA is used 6055 * however due to certain limitations in the hardware it is necessary to 6056 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6057 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6058 **/ 6059static void igb_set_uta(struct igb_adapter *adapter) 6060{ 6061 struct e1000_hw *hw = &adapter->hw; 6062 int i; 6063 6064 /* The UTA table only exists on 82576 hardware and newer */ 6065 if (hw->mac.type < e1000_82576) 6066 return; 6067 6068 /* we only need to do this if VMDq is enabled */ 6069 if (!adapter->vfs_allocated_count) 6070 return; 6071 6072 for (i = 0; i < hw->mac.uta_reg_count; i++) 6073 array_wr32(E1000_UTA, i, ~0); 6074} 6075 6076/** 6077 * igb_intr_msi - Interrupt Handler 6078 * @irq: interrupt number 6079 * @data: pointer to a network interface device structure 6080 **/ 6081static irqreturn_t igb_intr_msi(int irq, void *data) 6082{ 6083 struct igb_adapter *adapter = data; 6084 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6085 struct e1000_hw *hw = &adapter->hw; 6086 /* read ICR disables interrupts using IAM */ 6087 u32 icr = rd32(E1000_ICR); 6088 6089 igb_write_itr(q_vector); 6090 6091 if (icr & E1000_ICR_DRSTA) 6092 schedule_work(&adapter->reset_task); 6093 6094 if (icr & E1000_ICR_DOUTSYNC) { 6095 /* HW is reporting DMA is out of sync */ 6096 adapter->stats.doosync++; 6097 } 6098 6099 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6100 hw->mac.get_link_status = 1; 6101 if (!test_bit(__IGB_DOWN, &adapter->state)) 6102 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6103 } 6104 6105 if (icr & E1000_ICR_TS) { 6106 u32 tsicr = rd32(E1000_TSICR); 6107 6108 if (tsicr & E1000_TSICR_TXTS) { 6109 /* acknowledge the interrupt */ 6110 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6111 /* retrieve hardware timestamp */ 6112 schedule_work(&adapter->ptp_tx_work); 6113 } 6114 } 6115 6116 napi_schedule(&q_vector->napi); 6117 6118 return IRQ_HANDLED; 6119} 6120 6121/** 6122 * igb_intr - Legacy Interrupt Handler 6123 * @irq: interrupt number 6124 * @data: pointer to a network interface device structure 6125 **/ 6126static irqreturn_t igb_intr(int irq, void *data) 6127{ 6128 struct igb_adapter *adapter = data; 6129 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6130 struct e1000_hw *hw = &adapter->hw; 6131 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6132 * need for the IMC write 6133 */ 6134 u32 icr = rd32(E1000_ICR); 6135 6136 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6137 * not set, then the adapter didn't send an interrupt 6138 */ 6139 if (!(icr & E1000_ICR_INT_ASSERTED)) 6140 return IRQ_NONE; 6141 6142 igb_write_itr(q_vector); 6143 6144 if (icr & E1000_ICR_DRSTA) 6145 schedule_work(&adapter->reset_task); 6146 6147 if (icr & E1000_ICR_DOUTSYNC) { 6148 /* HW is reporting DMA is out of sync */ 6149 adapter->stats.doosync++; 6150 } 6151 6152 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6153 hw->mac.get_link_status = 1; 6154 /* guard against interrupt when we're going down */ 6155 if (!test_bit(__IGB_DOWN, &adapter->state)) 6156 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6157 } 6158 6159 if (icr & E1000_ICR_TS) { 6160 u32 tsicr = rd32(E1000_TSICR); 6161 6162 if (tsicr & E1000_TSICR_TXTS) { 6163 /* acknowledge the interrupt */ 6164 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6165 /* retrieve hardware timestamp */ 6166 schedule_work(&adapter->ptp_tx_work); 6167 } 6168 } 6169 6170 napi_schedule(&q_vector->napi); 6171 6172 return IRQ_HANDLED; 6173} 6174 6175static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6176{ 6177 struct igb_adapter *adapter = q_vector->adapter; 6178 struct e1000_hw *hw = &adapter->hw; 6179 6180 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6181 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6182 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6183 igb_set_itr(q_vector); 6184 else 6185 igb_update_ring_itr(q_vector); 6186 } 6187 6188 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6189 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6190 wr32(E1000_EIMS, q_vector->eims_value); 6191 else 6192 igb_irq_enable(adapter); 6193 } 6194} 6195 6196/** 6197 * igb_poll - NAPI Rx polling callback 6198 * @napi: napi polling structure 6199 * @budget: count of how many packets we should handle 6200 **/ 6201static int igb_poll(struct napi_struct *napi, int budget) 6202{ 6203 struct igb_q_vector *q_vector = container_of(napi, 6204 struct igb_q_vector, 6205 napi); 6206 bool clean_complete = true; 6207 6208#ifdef CONFIG_IGB_DCA 6209 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6210 igb_update_dca(q_vector); 6211#endif 6212 if (q_vector->tx.ring) 6213 clean_complete = igb_clean_tx_irq(q_vector); 6214 6215 if (q_vector->rx.ring) 6216 clean_complete &= igb_clean_rx_irq(q_vector, budget); 6217 6218 /* If all work not completed, return budget and keep polling */ 6219 if (!clean_complete) 6220 return budget; 6221 6222 /* If not enough Rx work done, exit the polling mode */ 6223 napi_complete(napi); 6224 igb_ring_irq_enable(q_vector); 6225 6226 return 0; 6227} 6228 6229/** 6230 * igb_clean_tx_irq - Reclaim resources after transmit completes 6231 * @q_vector: pointer to q_vector containing needed info 6232 * 6233 * returns true if ring is completely cleaned 6234 **/ 6235static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 6236{ 6237 struct igb_adapter *adapter = q_vector->adapter; 6238 struct igb_ring *tx_ring = q_vector->tx.ring; 6239 struct igb_tx_buffer *tx_buffer; 6240 union e1000_adv_tx_desc *tx_desc; 6241 unsigned int total_bytes = 0, total_packets = 0; 6242 unsigned int budget = q_vector->tx.work_limit; 6243 unsigned int i = tx_ring->next_to_clean; 6244 6245 if (test_bit(__IGB_DOWN, &adapter->state)) 6246 return true; 6247 6248 tx_buffer = &tx_ring->tx_buffer_info[i]; 6249 tx_desc = IGB_TX_DESC(tx_ring, i); 6250 i -= tx_ring->count; 6251 6252 do { 6253 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6254 6255 /* if next_to_watch is not set then there is no work pending */ 6256 if (!eop_desc) 6257 break; 6258 6259 /* prevent any other reads prior to eop_desc */ 6260 read_barrier_depends(); 6261 6262 /* if DD is not set pending work has not been completed */ 6263 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6264 break; 6265 6266 /* clear next_to_watch to prevent false hangs */ 6267 tx_buffer->next_to_watch = NULL; 6268 6269 /* update the statistics for this packet */ 6270 total_bytes += tx_buffer->bytecount; 6271 total_packets += tx_buffer->gso_segs; 6272 6273 /* free the skb */ 6274 dev_kfree_skb_any(tx_buffer->skb); 6275 6276 /* unmap skb header data */ 6277 dma_unmap_single(tx_ring->dev, 6278 dma_unmap_addr(tx_buffer, dma), 6279 dma_unmap_len(tx_buffer, len), 6280 DMA_TO_DEVICE); 6281 6282 /* clear tx_buffer data */ 6283 tx_buffer->skb = NULL; 6284 dma_unmap_len_set(tx_buffer, len, 0); 6285 6286 /* clear last DMA location and unmap remaining buffers */ 6287 while (tx_desc != eop_desc) { 6288 tx_buffer++; 6289 tx_desc++; 6290 i++; 6291 if (unlikely(!i)) { 6292 i -= tx_ring->count; 6293 tx_buffer = tx_ring->tx_buffer_info; 6294 tx_desc = IGB_TX_DESC(tx_ring, 0); 6295 } 6296 6297 /* unmap any remaining paged data */ 6298 if (dma_unmap_len(tx_buffer, len)) { 6299 dma_unmap_page(tx_ring->dev, 6300 dma_unmap_addr(tx_buffer, dma), 6301 dma_unmap_len(tx_buffer, len), 6302 DMA_TO_DEVICE); 6303 dma_unmap_len_set(tx_buffer, len, 0); 6304 } 6305 } 6306 6307 /* move us one more past the eop_desc for start of next pkt */ 6308 tx_buffer++; 6309 tx_desc++; 6310 i++; 6311 if (unlikely(!i)) { 6312 i -= tx_ring->count; 6313 tx_buffer = tx_ring->tx_buffer_info; 6314 tx_desc = IGB_TX_DESC(tx_ring, 0); 6315 } 6316 6317 /* issue prefetch for next Tx descriptor */ 6318 prefetch(tx_desc); 6319 6320 /* update budget accounting */ 6321 budget--; 6322 } while (likely(budget)); 6323 6324 netdev_tx_completed_queue(txring_txq(tx_ring), 6325 total_packets, total_bytes); 6326 i += tx_ring->count; 6327 tx_ring->next_to_clean = i; 6328 u64_stats_update_begin(&tx_ring->tx_syncp); 6329 tx_ring->tx_stats.bytes += total_bytes; 6330 tx_ring->tx_stats.packets += total_packets; 6331 u64_stats_update_end(&tx_ring->tx_syncp); 6332 q_vector->tx.total_bytes += total_bytes; 6333 q_vector->tx.total_packets += total_packets; 6334 6335 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6336 struct e1000_hw *hw = &adapter->hw; 6337 6338 /* Detect a transmit hang in hardware, this serializes the 6339 * check with the clearing of time_stamp and movement of i 6340 */ 6341 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6342 if (tx_buffer->next_to_watch && 6343 time_after(jiffies, tx_buffer->time_stamp + 6344 (adapter->tx_timeout_factor * HZ)) && 6345 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6346 6347 /* detected Tx unit hang */ 6348 dev_err(tx_ring->dev, 6349 "Detected Tx Unit Hang\n" 6350 " Tx Queue <%d>\n" 6351 " TDH <%x>\n" 6352 " TDT <%x>\n" 6353 " next_to_use <%x>\n" 6354 " next_to_clean <%x>\n" 6355 "buffer_info[next_to_clean]\n" 6356 " time_stamp <%lx>\n" 6357 " next_to_watch <%p>\n" 6358 " jiffies <%lx>\n" 6359 " desc.status <%x>\n", 6360 tx_ring->queue_index, 6361 rd32(E1000_TDH(tx_ring->reg_idx)), 6362 readl(tx_ring->tail), 6363 tx_ring->next_to_use, 6364 tx_ring->next_to_clean, 6365 tx_buffer->time_stamp, 6366 tx_buffer->next_to_watch, 6367 jiffies, 6368 tx_buffer->next_to_watch->wb.status); 6369 netif_stop_subqueue(tx_ring->netdev, 6370 tx_ring->queue_index); 6371 6372 /* we are about to reset, no point in enabling stuff */ 6373 return true; 6374 } 6375 } 6376 6377#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6378 if (unlikely(total_packets && 6379 netif_carrier_ok(tx_ring->netdev) && 6380 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6381 /* Make sure that anybody stopping the queue after this 6382 * sees the new next_to_clean. 6383 */ 6384 smp_mb(); 6385 if (__netif_subqueue_stopped(tx_ring->netdev, 6386 tx_ring->queue_index) && 6387 !(test_bit(__IGB_DOWN, &adapter->state))) { 6388 netif_wake_subqueue(tx_ring->netdev, 6389 tx_ring->queue_index); 6390 6391 u64_stats_update_begin(&tx_ring->tx_syncp); 6392 tx_ring->tx_stats.restart_queue++; 6393 u64_stats_update_end(&tx_ring->tx_syncp); 6394 } 6395 } 6396 6397 return !!budget; 6398} 6399 6400/** 6401 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6402 * @rx_ring: rx descriptor ring to store buffers on 6403 * @old_buff: donor buffer to have page reused 6404 * 6405 * Synchronizes page for reuse by the adapter 6406 **/ 6407static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6408 struct igb_rx_buffer *old_buff) 6409{ 6410 struct igb_rx_buffer *new_buff; 6411 u16 nta = rx_ring->next_to_alloc; 6412 6413 new_buff = &rx_ring->rx_buffer_info[nta]; 6414 6415 /* update, and store next to alloc */ 6416 nta++; 6417 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6418 6419 /* transfer page from old buffer to new buffer */ 6420 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); 6421 6422 /* sync the buffer for use by the device */ 6423 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 6424 old_buff->page_offset, 6425 IGB_RX_BUFSZ, 6426 DMA_FROM_DEVICE); 6427} 6428 6429static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 6430 struct page *page, 6431 unsigned int truesize) 6432{ 6433 /* avoid re-using remote pages */ 6434 if (unlikely(page_to_nid(page) != numa_node_id())) 6435 return false; 6436 6437#if (PAGE_SIZE < 8192) 6438 /* if we are only owner of page we can reuse it */ 6439 if (unlikely(page_count(page) != 1)) 6440 return false; 6441 6442 /* flip page offset to other buffer */ 6443 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 6444 6445 /* since we are the only owner of the page and we need to 6446 * increment it, just set the value to 2 in order to avoid 6447 * an unnecessary locked operation 6448 */ 6449 atomic_set(&page->_count, 2); 6450#else 6451 /* move offset up to the next cache line */ 6452 rx_buffer->page_offset += truesize; 6453 6454 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 6455 return false; 6456 6457 /* bump ref count on page before it is given to the stack */ 6458 get_page(page); 6459#endif 6460 6461 return true; 6462} 6463 6464/** 6465 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6466 * @rx_ring: rx descriptor ring to transact packets on 6467 * @rx_buffer: buffer containing page to add 6468 * @rx_desc: descriptor containing length of buffer written by hardware 6469 * @skb: sk_buff to place the data into 6470 * 6471 * This function will add the data contained in rx_buffer->page to the skb. 6472 * This is done either through a direct copy if the data in the buffer is 6473 * less than the skb header size, otherwise it will just attach the page as 6474 * a frag to the skb. 6475 * 6476 * The function will then update the page offset if necessary and return 6477 * true if the buffer can be reused by the adapter. 6478 **/ 6479static bool igb_add_rx_frag(struct igb_ring *rx_ring, 6480 struct igb_rx_buffer *rx_buffer, 6481 union e1000_adv_rx_desc *rx_desc, 6482 struct sk_buff *skb) 6483{ 6484 struct page *page = rx_buffer->page; 6485 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 6486#if (PAGE_SIZE < 8192) 6487 unsigned int truesize = IGB_RX_BUFSZ; 6488#else 6489 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 6490#endif 6491 6492 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { 6493 unsigned char *va = page_address(page) + rx_buffer->page_offset; 6494 6495 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6496 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6497 va += IGB_TS_HDR_LEN; 6498 size -= IGB_TS_HDR_LEN; 6499 } 6500 6501 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 6502 6503 /* we can reuse buffer as-is, just make sure it is local */ 6504 if (likely(page_to_nid(page) == numa_node_id())) 6505 return true; 6506 6507 /* this page cannot be reused so discard it */ 6508 put_page(page); 6509 return false; 6510 } 6511 6512 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 6513 rx_buffer->page_offset, size, truesize); 6514 6515 return igb_can_reuse_rx_page(rx_buffer, page, truesize); 6516} 6517 6518static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 6519 union e1000_adv_rx_desc *rx_desc, 6520 struct sk_buff *skb) 6521{ 6522 struct igb_rx_buffer *rx_buffer; 6523 struct page *page; 6524 6525 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 6526 6527 page = rx_buffer->page; 6528 prefetchw(page); 6529 6530 if (likely(!skb)) { 6531 void *page_addr = page_address(page) + 6532 rx_buffer->page_offset; 6533 6534 /* prefetch first cache line of first page */ 6535 prefetch(page_addr); 6536#if L1_CACHE_BYTES < 128 6537 prefetch(page_addr + L1_CACHE_BYTES); 6538#endif 6539 6540 /* allocate a skb to store the frags */ 6541 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 6542 IGB_RX_HDR_LEN); 6543 if (unlikely(!skb)) { 6544 rx_ring->rx_stats.alloc_failed++; 6545 return NULL; 6546 } 6547 6548 /* we will be copying header into skb->data in 6549 * pskb_may_pull so it is in our interest to prefetch 6550 * it now to avoid a possible cache miss 6551 */ 6552 prefetchw(skb->data); 6553 } 6554 6555 /* we are reusing so sync this buffer for CPU use */ 6556 dma_sync_single_range_for_cpu(rx_ring->dev, 6557 rx_buffer->dma, 6558 rx_buffer->page_offset, 6559 IGB_RX_BUFSZ, 6560 DMA_FROM_DEVICE); 6561 6562 /* pull page into skb */ 6563 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 6564 /* hand second half of page back to the ring */ 6565 igb_reuse_rx_page(rx_ring, rx_buffer); 6566 } else { 6567 /* we are not reusing the buffer so unmap it */ 6568 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6569 PAGE_SIZE, DMA_FROM_DEVICE); 6570 } 6571 6572 /* clear contents of rx_buffer */ 6573 rx_buffer->page = NULL; 6574 6575 return skb; 6576} 6577 6578static inline void igb_rx_checksum(struct igb_ring *ring, 6579 union e1000_adv_rx_desc *rx_desc, 6580 struct sk_buff *skb) 6581{ 6582 skb_checksum_none_assert(skb); 6583 6584 /* Ignore Checksum bit is set */ 6585 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6586 return; 6587 6588 /* Rx checksum disabled via ethtool */ 6589 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6590 return; 6591 6592 /* TCP/UDP checksum error bit is set */ 6593 if (igb_test_staterr(rx_desc, 6594 E1000_RXDEXT_STATERR_TCPE | 6595 E1000_RXDEXT_STATERR_IPE)) { 6596 /* work around errata with sctp packets where the TCPE aka 6597 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6598 * packets, (aka let the stack check the crc32c) 6599 */ 6600 if (!((skb->len == 60) && 6601 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6602 u64_stats_update_begin(&ring->rx_syncp); 6603 ring->rx_stats.csum_err++; 6604 u64_stats_update_end(&ring->rx_syncp); 6605 } 6606 /* let the stack verify checksum errors */ 6607 return; 6608 } 6609 /* It must be a TCP or UDP packet with a valid checksum */ 6610 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 6611 E1000_RXD_STAT_UDPCS)) 6612 skb->ip_summed = CHECKSUM_UNNECESSARY; 6613 6614 dev_dbg(ring->dev, "cksum success: bits %08X\n", 6615 le32_to_cpu(rx_desc->wb.upper.status_error)); 6616} 6617 6618static inline void igb_rx_hash(struct igb_ring *ring, 6619 union e1000_adv_rx_desc *rx_desc, 6620 struct sk_buff *skb) 6621{ 6622 if (ring->netdev->features & NETIF_F_RXHASH) 6623 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); 6624} 6625 6626/** 6627 * igb_is_non_eop - process handling of non-EOP buffers 6628 * @rx_ring: Rx ring being processed 6629 * @rx_desc: Rx descriptor for current buffer 6630 * @skb: current socket buffer containing buffer in progress 6631 * 6632 * This function updates next to clean. If the buffer is an EOP buffer 6633 * this function exits returning false, otherwise it will place the 6634 * sk_buff in the next buffer to be chained and return true indicating 6635 * that this is in fact a non-EOP buffer. 6636 **/ 6637static bool igb_is_non_eop(struct igb_ring *rx_ring, 6638 union e1000_adv_rx_desc *rx_desc) 6639{ 6640 u32 ntc = rx_ring->next_to_clean + 1; 6641 6642 /* fetch, update, and store next to clean */ 6643 ntc = (ntc < rx_ring->count) ? ntc : 0; 6644 rx_ring->next_to_clean = ntc; 6645 6646 prefetch(IGB_RX_DESC(rx_ring, ntc)); 6647 6648 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 6649 return false; 6650 6651 return true; 6652} 6653 6654/** 6655 * igb_get_headlen - determine size of header for LRO/GRO 6656 * @data: pointer to the start of the headers 6657 * @max_len: total length of section to find headers in 6658 * 6659 * This function is meant to determine the length of headers that will 6660 * be recognized by hardware for LRO, and GRO offloads. The main 6661 * motivation of doing this is to only perform one pull for IPv4 TCP 6662 * packets so that we can do basic things like calculating the gso_size 6663 * based on the average data per packet. 6664 **/ 6665static unsigned int igb_get_headlen(unsigned char *data, 6666 unsigned int max_len) 6667{ 6668 union { 6669 unsigned char *network; 6670 /* l2 headers */ 6671 struct ethhdr *eth; 6672 struct vlan_hdr *vlan; 6673 /* l3 headers */ 6674 struct iphdr *ipv4; 6675 struct ipv6hdr *ipv6; 6676 } hdr; 6677 __be16 protocol; 6678 u8 nexthdr = 0; /* default to not TCP */ 6679 u8 hlen; 6680 6681 /* this should never happen, but better safe than sorry */ 6682 if (max_len < ETH_HLEN) 6683 return max_len; 6684 6685 /* initialize network frame pointer */ 6686 hdr.network = data; 6687 6688 /* set first protocol and move network header forward */ 6689 protocol = hdr.eth->h_proto; 6690 hdr.network += ETH_HLEN; 6691 6692 /* handle any vlan tag if present */ 6693 if (protocol == __constant_htons(ETH_P_8021Q)) { 6694 if ((hdr.network - data) > (max_len - VLAN_HLEN)) 6695 return max_len; 6696 6697 protocol = hdr.vlan->h_vlan_encapsulated_proto; 6698 hdr.network += VLAN_HLEN; 6699 } 6700 6701 /* handle L3 protocols */ 6702 if (protocol == __constant_htons(ETH_P_IP)) { 6703 if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) 6704 return max_len; 6705 6706 /* access ihl as a u8 to avoid unaligned access on ia64 */ 6707 hlen = (hdr.network[0] & 0x0F) << 2; 6708 6709 /* verify hlen meets minimum size requirements */ 6710 if (hlen < sizeof(struct iphdr)) 6711 return hdr.network - data; 6712 6713 /* record next protocol if header is present */ 6714 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET))) 6715 nexthdr = hdr.ipv4->protocol; 6716 } else if (protocol == __constant_htons(ETH_P_IPV6)) { 6717 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) 6718 return max_len; 6719 6720 /* record next protocol */ 6721 nexthdr = hdr.ipv6->nexthdr; 6722 hlen = sizeof(struct ipv6hdr); 6723 } else { 6724 return hdr.network - data; 6725 } 6726 6727 /* relocate pointer to start of L4 header */ 6728 hdr.network += hlen; 6729 6730 /* finally sort out TCP */ 6731 if (nexthdr == IPPROTO_TCP) { 6732 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) 6733 return max_len; 6734 6735 /* access doff as a u8 to avoid unaligned access on ia64 */ 6736 hlen = (hdr.network[12] & 0xF0) >> 2; 6737 6738 /* verify hlen meets minimum size requirements */ 6739 if (hlen < sizeof(struct tcphdr)) 6740 return hdr.network - data; 6741 6742 hdr.network += hlen; 6743 } else if (nexthdr == IPPROTO_UDP) { 6744 if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) 6745 return max_len; 6746 6747 hdr.network += sizeof(struct udphdr); 6748 } 6749 6750 /* If everything has gone correctly hdr.network should be the 6751 * data section of the packet and will be the end of the header. 6752 * If not then it probably represents the end of the last recognized 6753 * header. 6754 */ 6755 if ((hdr.network - data) < max_len) 6756 return hdr.network - data; 6757 else 6758 return max_len; 6759} 6760 6761/** 6762 * igb_pull_tail - igb specific version of skb_pull_tail 6763 * @rx_ring: rx descriptor ring packet is being transacted on 6764 * @rx_desc: pointer to the EOP Rx descriptor 6765 * @skb: pointer to current skb being adjusted 6766 * 6767 * This function is an igb specific version of __pskb_pull_tail. The 6768 * main difference between this version and the original function is that 6769 * this function can make several assumptions about the state of things 6770 * that allow for significant optimizations versus the standard function. 6771 * As a result we can do things like drop a frag and maintain an accurate 6772 * truesize for the skb. 6773 */ 6774static void igb_pull_tail(struct igb_ring *rx_ring, 6775 union e1000_adv_rx_desc *rx_desc, 6776 struct sk_buff *skb) 6777{ 6778 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6779 unsigned char *va; 6780 unsigned int pull_len; 6781 6782 /* it is valid to use page_address instead of kmap since we are 6783 * working with pages allocated out of the lomem pool per 6784 * alloc_page(GFP_ATOMIC) 6785 */ 6786 va = skb_frag_address(frag); 6787 6788 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6789 /* retrieve timestamp from buffer */ 6790 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6791 6792 /* update pointers to remove timestamp header */ 6793 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); 6794 frag->page_offset += IGB_TS_HDR_LEN; 6795 skb->data_len -= IGB_TS_HDR_LEN; 6796 skb->len -= IGB_TS_HDR_LEN; 6797 6798 /* move va to start of packet data */ 6799 va += IGB_TS_HDR_LEN; 6800 } 6801 6802 /* we need the header to contain the greater of either ETH_HLEN or 6803 * 60 bytes if the skb->len is less than 60 for skb_pad. 6804 */ 6805 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); 6806 6807 /* align pull length to size of long to optimize memcpy performance */ 6808 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 6809 6810 /* update all of the pointers */ 6811 skb_frag_size_sub(frag, pull_len); 6812 frag->page_offset += pull_len; 6813 skb->data_len -= pull_len; 6814 skb->tail += pull_len; 6815} 6816 6817/** 6818 * igb_cleanup_headers - Correct corrupted or empty headers 6819 * @rx_ring: rx descriptor ring packet is being transacted on 6820 * @rx_desc: pointer to the EOP Rx descriptor 6821 * @skb: pointer to current skb being fixed 6822 * 6823 * Address the case where we are pulling data in on pages only 6824 * and as such no data is present in the skb header. 6825 * 6826 * In addition if skb is not at least 60 bytes we need to pad it so that 6827 * it is large enough to qualify as a valid Ethernet frame. 6828 * 6829 * Returns true if an error was encountered and skb was freed. 6830 **/ 6831static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6832 union e1000_adv_rx_desc *rx_desc, 6833 struct sk_buff *skb) 6834{ 6835 if (unlikely((igb_test_staterr(rx_desc, 6836 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6837 struct net_device *netdev = rx_ring->netdev; 6838 if (!(netdev->features & NETIF_F_RXALL)) { 6839 dev_kfree_skb_any(skb); 6840 return true; 6841 } 6842 } 6843 6844 /* place header in linear portion of buffer */ 6845 if (skb_is_nonlinear(skb)) 6846 igb_pull_tail(rx_ring, rx_desc, skb); 6847 6848 /* if skb_pad returns an error the skb was freed */ 6849 if (unlikely(skb->len < 60)) { 6850 int pad_len = 60 - skb->len; 6851 6852 if (skb_pad(skb, pad_len)) 6853 return true; 6854 __skb_put(skb, pad_len); 6855 } 6856 6857 return false; 6858} 6859 6860/** 6861 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6862 * @rx_ring: rx descriptor ring packet is being transacted on 6863 * @rx_desc: pointer to the EOP Rx descriptor 6864 * @skb: pointer to current skb being populated 6865 * 6866 * This function checks the ring, descriptor, and packet information in 6867 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6868 * other fields within the skb. 6869 **/ 6870static void igb_process_skb_fields(struct igb_ring *rx_ring, 6871 union e1000_adv_rx_desc *rx_desc, 6872 struct sk_buff *skb) 6873{ 6874 struct net_device *dev = rx_ring->netdev; 6875 6876 igb_rx_hash(rx_ring, rx_desc, skb); 6877 6878 igb_rx_checksum(rx_ring, rx_desc, skb); 6879 6880 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 6881 6882 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 6883 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6884 u16 vid; 6885 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6886 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6887 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6888 else 6889 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6890 6891 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 6892 } 6893 6894 skb_record_rx_queue(skb, rx_ring->queue_index); 6895 6896 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6897} 6898 6899static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 6900{ 6901 struct igb_ring *rx_ring = q_vector->rx.ring; 6902 struct sk_buff *skb = rx_ring->skb; 6903 unsigned int total_bytes = 0, total_packets = 0; 6904 u16 cleaned_count = igb_desc_unused(rx_ring); 6905 6906 do { 6907 union e1000_adv_rx_desc *rx_desc; 6908 6909 /* return some buffers to hardware, one at a time is too slow */ 6910 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6911 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6912 cleaned_count = 0; 6913 } 6914 6915 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 6916 6917 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) 6918 break; 6919 6920 /* This memory barrier is needed to keep us from reading 6921 * any other fields out of the rx_desc until we know the 6922 * RXD_STAT_DD bit is set 6923 */ 6924 rmb(); 6925 6926 /* retrieve a buffer from the ring */ 6927 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 6928 6929 /* exit if we failed to retrieve a buffer */ 6930 if (!skb) 6931 break; 6932 6933 cleaned_count++; 6934 6935 /* fetch next buffer in frame if non-eop */ 6936 if (igb_is_non_eop(rx_ring, rx_desc)) 6937 continue; 6938 6939 /* verify the packet layout is correct */ 6940 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 6941 skb = NULL; 6942 continue; 6943 } 6944 6945 /* probably a little skewed due to removing CRC */ 6946 total_bytes += skb->len; 6947 6948 /* populate checksum, timestamp, VLAN, and protocol */ 6949 igb_process_skb_fields(rx_ring, rx_desc, skb); 6950 6951 napi_gro_receive(&q_vector->napi, skb); 6952 6953 /* reset skb pointer */ 6954 skb = NULL; 6955 6956 /* update budget accounting */ 6957 total_packets++; 6958 } while (likely(total_packets < budget)); 6959 6960 /* place incomplete frames back on ring for completion */ 6961 rx_ring->skb = skb; 6962 6963 u64_stats_update_begin(&rx_ring->rx_syncp); 6964 rx_ring->rx_stats.packets += total_packets; 6965 rx_ring->rx_stats.bytes += total_bytes; 6966 u64_stats_update_end(&rx_ring->rx_syncp); 6967 q_vector->rx.total_packets += total_packets; 6968 q_vector->rx.total_bytes += total_bytes; 6969 6970 if (cleaned_count) 6971 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6972 6973 return (total_packets < budget); 6974} 6975 6976static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 6977 struct igb_rx_buffer *bi) 6978{ 6979 struct page *page = bi->page; 6980 dma_addr_t dma; 6981 6982 /* since we are recycling buffers we should seldom need to alloc */ 6983 if (likely(page)) 6984 return true; 6985 6986 /* alloc new page for storage */ 6987 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); 6988 if (unlikely(!page)) { 6989 rx_ring->rx_stats.alloc_failed++; 6990 return false; 6991 } 6992 6993 /* map page for use */ 6994 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 6995 6996 /* if mapping failed free memory back to system since 6997 * there isn't much point in holding memory we can't use 6998 */ 6999 if (dma_mapping_error(rx_ring->dev, dma)) { 7000 __free_page(page); 7001 7002 rx_ring->rx_stats.alloc_failed++; 7003 return false; 7004 } 7005 7006 bi->dma = dma; 7007 bi->page = page; 7008 bi->page_offset = 0; 7009 7010 return true; 7011} 7012 7013/** 7014 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7015 * @adapter: address of board private structure 7016 **/ 7017void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7018{ 7019 union e1000_adv_rx_desc *rx_desc; 7020 struct igb_rx_buffer *bi; 7021 u16 i = rx_ring->next_to_use; 7022 7023 /* nothing to do */ 7024 if (!cleaned_count) 7025 return; 7026 7027 rx_desc = IGB_RX_DESC(rx_ring, i); 7028 bi = &rx_ring->rx_buffer_info[i]; 7029 i -= rx_ring->count; 7030 7031 do { 7032 if (!igb_alloc_mapped_page(rx_ring, bi)) 7033 break; 7034 7035 /* Refresh the desc even if buffer_addrs didn't change 7036 * because each write-back erases this info. 7037 */ 7038 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7039 7040 rx_desc++; 7041 bi++; 7042 i++; 7043 if (unlikely(!i)) { 7044 rx_desc = IGB_RX_DESC(rx_ring, 0); 7045 bi = rx_ring->rx_buffer_info; 7046 i -= rx_ring->count; 7047 } 7048 7049 /* clear the hdr_addr for the next_to_use descriptor */ 7050 rx_desc->read.hdr_addr = 0; 7051 7052 cleaned_count--; 7053 } while (cleaned_count); 7054 7055 i += rx_ring->count; 7056 7057 if (rx_ring->next_to_use != i) { 7058 /* record the next descriptor to use */ 7059 rx_ring->next_to_use = i; 7060 7061 /* update next to alloc since we have filled the ring */ 7062 rx_ring->next_to_alloc = i; 7063 7064 /* Force memory writes to complete before letting h/w 7065 * know there are new descriptors to fetch. (Only 7066 * applicable for weak-ordered memory model archs, 7067 * such as IA-64). 7068 */ 7069 wmb(); 7070 writel(i, rx_ring->tail); 7071 } 7072} 7073 7074/** 7075 * igb_mii_ioctl - 7076 * @netdev: 7077 * @ifreq: 7078 * @cmd: 7079 **/ 7080static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7081{ 7082 struct igb_adapter *adapter = netdev_priv(netdev); 7083 struct mii_ioctl_data *data = if_mii(ifr); 7084 7085 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7086 return -EOPNOTSUPP; 7087 7088 switch (cmd) { 7089 case SIOCGMIIPHY: 7090 data->phy_id = adapter->hw.phy.addr; 7091 break; 7092 case SIOCGMIIREG: 7093 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7094 &data->val_out)) 7095 return -EIO; 7096 break; 7097 case SIOCSMIIREG: 7098 default: 7099 return -EOPNOTSUPP; 7100 } 7101 return 0; 7102} 7103 7104/** 7105 * igb_ioctl - 7106 * @netdev: 7107 * @ifreq: 7108 * @cmd: 7109 **/ 7110static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7111{ 7112 switch (cmd) { 7113 case SIOCGMIIPHY: 7114 case SIOCGMIIREG: 7115 case SIOCSMIIREG: 7116 return igb_mii_ioctl(netdev, ifr, cmd); 7117 case SIOCSHWTSTAMP: 7118 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd); 7119 default: 7120 return -EOPNOTSUPP; 7121 } 7122} 7123 7124s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7125{ 7126 struct igb_adapter *adapter = hw->back; 7127 7128 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7129 return -E1000_ERR_CONFIG; 7130 7131 return 0; 7132} 7133 7134s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7135{ 7136 struct igb_adapter *adapter = hw->back; 7137 7138 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7139 return -E1000_ERR_CONFIG; 7140 7141 return 0; 7142} 7143 7144static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7145{ 7146 struct igb_adapter *adapter = netdev_priv(netdev); 7147 struct e1000_hw *hw = &adapter->hw; 7148 u32 ctrl, rctl; 7149 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7150 7151 if (enable) { 7152 /* enable VLAN tag insert/strip */ 7153 ctrl = rd32(E1000_CTRL); 7154 ctrl |= E1000_CTRL_VME; 7155 wr32(E1000_CTRL, ctrl); 7156 7157 /* Disable CFI check */ 7158 rctl = rd32(E1000_RCTL); 7159 rctl &= ~E1000_RCTL_CFIEN; 7160 wr32(E1000_RCTL, rctl); 7161 } else { 7162 /* disable VLAN tag insert/strip */ 7163 ctrl = rd32(E1000_CTRL); 7164 ctrl &= ~E1000_CTRL_VME; 7165 wr32(E1000_CTRL, ctrl); 7166 } 7167 7168 igb_rlpml_set(adapter); 7169} 7170 7171static int igb_vlan_rx_add_vid(struct net_device *netdev, 7172 __be16 proto, u16 vid) 7173{ 7174 struct igb_adapter *adapter = netdev_priv(netdev); 7175 struct e1000_hw *hw = &adapter->hw; 7176 int pf_id = adapter->vfs_allocated_count; 7177 7178 /* attempt to add filter to vlvf array */ 7179 igb_vlvf_set(adapter, vid, true, pf_id); 7180 7181 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7182 igb_vfta_set(hw, vid, true); 7183 7184 set_bit(vid, adapter->active_vlans); 7185 7186 return 0; 7187} 7188 7189static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7190 __be16 proto, u16 vid) 7191{ 7192 struct igb_adapter *adapter = netdev_priv(netdev); 7193 struct e1000_hw *hw = &adapter->hw; 7194 int pf_id = adapter->vfs_allocated_count; 7195 s32 err; 7196 7197 /* remove vlan from VLVF table array */ 7198 err = igb_vlvf_set(adapter, vid, false, pf_id); 7199 7200 /* if vid was not present in VLVF just remove it from table */ 7201 if (err) 7202 igb_vfta_set(hw, vid, false); 7203 7204 clear_bit(vid, adapter->active_vlans); 7205 7206 return 0; 7207} 7208 7209static void igb_restore_vlan(struct igb_adapter *adapter) 7210{ 7211 u16 vid; 7212 7213 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7214 7215 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 7216 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7217} 7218 7219int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7220{ 7221 struct pci_dev *pdev = adapter->pdev; 7222 struct e1000_mac_info *mac = &adapter->hw.mac; 7223 7224 mac->autoneg = 0; 7225 7226 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7227 * for the switch() below to work 7228 */ 7229 if ((spd & 1) || (dplx & ~1)) 7230 goto err_inval; 7231 7232 /* Fiber NIC's only allow 1000 gbps Full duplex 7233 * and 100Mbps Full duplex for 100baseFx sfp 7234 */ 7235 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7236 switch (spd + dplx) { 7237 case SPEED_10 + DUPLEX_HALF: 7238 case SPEED_10 + DUPLEX_FULL: 7239 case SPEED_100 + DUPLEX_HALF: 7240 goto err_inval; 7241 default: 7242 break; 7243 } 7244 } 7245 7246 switch (spd + dplx) { 7247 case SPEED_10 + DUPLEX_HALF: 7248 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7249 break; 7250 case SPEED_10 + DUPLEX_FULL: 7251 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7252 break; 7253 case SPEED_100 + DUPLEX_HALF: 7254 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7255 break; 7256 case SPEED_100 + DUPLEX_FULL: 7257 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7258 break; 7259 case SPEED_1000 + DUPLEX_FULL: 7260 mac->autoneg = 1; 7261 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7262 break; 7263 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7264 default: 7265 goto err_inval; 7266 } 7267 7268 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7269 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7270 7271 return 0; 7272 7273err_inval: 7274 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7275 return -EINVAL; 7276} 7277 7278static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7279 bool runtime) 7280{ 7281 struct net_device *netdev = pci_get_drvdata(pdev); 7282 struct igb_adapter *adapter = netdev_priv(netdev); 7283 struct e1000_hw *hw = &adapter->hw; 7284 u32 ctrl, rctl, status; 7285 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7286#ifdef CONFIG_PM 7287 int retval = 0; 7288#endif 7289 7290 netif_device_detach(netdev); 7291 7292 if (netif_running(netdev)) 7293 __igb_close(netdev, true); 7294 7295 igb_clear_interrupt_scheme(adapter); 7296 7297#ifdef CONFIG_PM 7298 retval = pci_save_state(pdev); 7299 if (retval) 7300 return retval; 7301#endif 7302 7303 status = rd32(E1000_STATUS); 7304 if (status & E1000_STATUS_LU) 7305 wufc &= ~E1000_WUFC_LNKC; 7306 7307 if (wufc) { 7308 igb_setup_rctl(adapter); 7309 igb_set_rx_mode(netdev); 7310 7311 /* turn on all-multi mode if wake on multicast is enabled */ 7312 if (wufc & E1000_WUFC_MC) { 7313 rctl = rd32(E1000_RCTL); 7314 rctl |= E1000_RCTL_MPE; 7315 wr32(E1000_RCTL, rctl); 7316 } 7317 7318 ctrl = rd32(E1000_CTRL); 7319 /* advertise wake from D3Cold */ 7320 #define E1000_CTRL_ADVD3WUC 0x00100000 7321 /* phy power management enable */ 7322 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7323 ctrl |= E1000_CTRL_ADVD3WUC; 7324 wr32(E1000_CTRL, ctrl); 7325 7326 /* Allow time for pending master requests to run */ 7327 igb_disable_pcie_master(hw); 7328 7329 wr32(E1000_WUC, E1000_WUC_PME_EN); 7330 wr32(E1000_WUFC, wufc); 7331 } else { 7332 wr32(E1000_WUC, 0); 7333 wr32(E1000_WUFC, 0); 7334 } 7335 7336 *enable_wake = wufc || adapter->en_mng_pt; 7337 if (!*enable_wake) 7338 igb_power_down_link(adapter); 7339 else 7340 igb_power_up_link(adapter); 7341 7342 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7343 * would have already happened in close and is redundant. 7344 */ 7345 igb_release_hw_control(adapter); 7346 7347 pci_disable_device(pdev); 7348 7349 return 0; 7350} 7351 7352#ifdef CONFIG_PM 7353#ifdef CONFIG_PM_SLEEP 7354static int igb_suspend(struct device *dev) 7355{ 7356 int retval; 7357 bool wake; 7358 struct pci_dev *pdev = to_pci_dev(dev); 7359 7360 retval = __igb_shutdown(pdev, &wake, 0); 7361 if (retval) 7362 return retval; 7363 7364 if (wake) { 7365 pci_prepare_to_sleep(pdev); 7366 } else { 7367 pci_wake_from_d3(pdev, false); 7368 pci_set_power_state(pdev, PCI_D3hot); 7369 } 7370 7371 return 0; 7372} 7373#endif /* CONFIG_PM_SLEEP */ 7374 7375static int igb_resume(struct device *dev) 7376{ 7377 struct pci_dev *pdev = to_pci_dev(dev); 7378 struct net_device *netdev = pci_get_drvdata(pdev); 7379 struct igb_adapter *adapter = netdev_priv(netdev); 7380 struct e1000_hw *hw = &adapter->hw; 7381 u32 err; 7382 7383 pci_set_power_state(pdev, PCI_D0); 7384 pci_restore_state(pdev); 7385 pci_save_state(pdev); 7386 7387 err = pci_enable_device_mem(pdev); 7388 if (err) { 7389 dev_err(&pdev->dev, 7390 "igb: Cannot enable PCI device from suspend\n"); 7391 return err; 7392 } 7393 pci_set_master(pdev); 7394 7395 pci_enable_wake(pdev, PCI_D3hot, 0); 7396 pci_enable_wake(pdev, PCI_D3cold, 0); 7397 7398 if (igb_init_interrupt_scheme(adapter, true)) { 7399 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7400 return -ENOMEM; 7401 } 7402 7403 igb_reset(adapter); 7404 7405 /* let the f/w know that the h/w is now under the control of the 7406 * driver. 7407 */ 7408 igb_get_hw_control(adapter); 7409 7410 wr32(E1000_WUS, ~0); 7411 7412 if (netdev->flags & IFF_UP) { 7413 rtnl_lock(); 7414 err = __igb_open(netdev, true); 7415 rtnl_unlock(); 7416 if (err) 7417 return err; 7418 } 7419 7420 netif_device_attach(netdev); 7421 return 0; 7422} 7423 7424#ifdef CONFIG_PM_RUNTIME 7425static int igb_runtime_idle(struct device *dev) 7426{ 7427 struct pci_dev *pdev = to_pci_dev(dev); 7428 struct net_device *netdev = pci_get_drvdata(pdev); 7429 struct igb_adapter *adapter = netdev_priv(netdev); 7430 7431 if (!igb_has_link(adapter)) 7432 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7433 7434 return -EBUSY; 7435} 7436 7437static int igb_runtime_suspend(struct device *dev) 7438{ 7439 struct pci_dev *pdev = to_pci_dev(dev); 7440 int retval; 7441 bool wake; 7442 7443 retval = __igb_shutdown(pdev, &wake, 1); 7444 if (retval) 7445 return retval; 7446 7447 if (wake) { 7448 pci_prepare_to_sleep(pdev); 7449 } else { 7450 pci_wake_from_d3(pdev, false); 7451 pci_set_power_state(pdev, PCI_D3hot); 7452 } 7453 7454 return 0; 7455} 7456 7457static int igb_runtime_resume(struct device *dev) 7458{ 7459 return igb_resume(dev); 7460} 7461#endif /* CONFIG_PM_RUNTIME */ 7462#endif 7463 7464static void igb_shutdown(struct pci_dev *pdev) 7465{ 7466 bool wake; 7467 7468 __igb_shutdown(pdev, &wake, 0); 7469 7470 if (system_state == SYSTEM_POWER_OFF) { 7471 pci_wake_from_d3(pdev, wake); 7472 pci_set_power_state(pdev, PCI_D3hot); 7473 } 7474} 7475 7476#ifdef CONFIG_PCI_IOV 7477static int igb_sriov_reinit(struct pci_dev *dev) 7478{ 7479 struct net_device *netdev = pci_get_drvdata(dev); 7480 struct igb_adapter *adapter = netdev_priv(netdev); 7481 struct pci_dev *pdev = adapter->pdev; 7482 7483 rtnl_lock(); 7484 7485 if (netif_running(netdev)) 7486 igb_close(netdev); 7487 7488 igb_clear_interrupt_scheme(adapter); 7489 7490 igb_init_queue_configuration(adapter); 7491 7492 if (igb_init_interrupt_scheme(adapter, true)) { 7493 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7494 return -ENOMEM; 7495 } 7496 7497 if (netif_running(netdev)) 7498 igb_open(netdev); 7499 7500 rtnl_unlock(); 7501 7502 return 0; 7503} 7504 7505static int igb_pci_disable_sriov(struct pci_dev *dev) 7506{ 7507 int err = igb_disable_sriov(dev); 7508 7509 if (!err) 7510 err = igb_sriov_reinit(dev); 7511 7512 return err; 7513} 7514 7515static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7516{ 7517 int err = igb_enable_sriov(dev, num_vfs); 7518 7519 if (err) 7520 goto out; 7521 7522 err = igb_sriov_reinit(dev); 7523 if (!err) 7524 return num_vfs; 7525 7526out: 7527 return err; 7528} 7529 7530#endif 7531static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7532{ 7533#ifdef CONFIG_PCI_IOV 7534 if (num_vfs == 0) 7535 return igb_pci_disable_sriov(dev); 7536 else 7537 return igb_pci_enable_sriov(dev, num_vfs); 7538#endif 7539 return 0; 7540} 7541 7542#ifdef CONFIG_NET_POLL_CONTROLLER 7543/* Polling 'interrupt' - used by things like netconsole to send skbs 7544 * without having to re-enable interrupts. It's not called while 7545 * the interrupt routine is executing. 7546 */ 7547static void igb_netpoll(struct net_device *netdev) 7548{ 7549 struct igb_adapter *adapter = netdev_priv(netdev); 7550 struct e1000_hw *hw = &adapter->hw; 7551 struct igb_q_vector *q_vector; 7552 int i; 7553 7554 for (i = 0; i < adapter->num_q_vectors; i++) { 7555 q_vector = adapter->q_vector[i]; 7556 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7557 wr32(E1000_EIMC, q_vector->eims_value); 7558 else 7559 igb_irq_disable(adapter); 7560 napi_schedule(&q_vector->napi); 7561 } 7562} 7563#endif /* CONFIG_NET_POLL_CONTROLLER */ 7564 7565/** 7566 * igb_io_error_detected - called when PCI error is detected 7567 * @pdev: Pointer to PCI device 7568 * @state: The current pci connection state 7569 * 7570 * This function is called after a PCI bus error affecting 7571 * this device has been detected. 7572 **/ 7573static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7574 pci_channel_state_t state) 7575{ 7576 struct net_device *netdev = pci_get_drvdata(pdev); 7577 struct igb_adapter *adapter = netdev_priv(netdev); 7578 7579 netif_device_detach(netdev); 7580 7581 if (state == pci_channel_io_perm_failure) 7582 return PCI_ERS_RESULT_DISCONNECT; 7583 7584 if (netif_running(netdev)) 7585 igb_down(adapter); 7586 pci_disable_device(pdev); 7587 7588 /* Request a slot slot reset. */ 7589 return PCI_ERS_RESULT_NEED_RESET; 7590} 7591 7592/** 7593 * igb_io_slot_reset - called after the pci bus has been reset. 7594 * @pdev: Pointer to PCI device 7595 * 7596 * Restart the card from scratch, as if from a cold-boot. Implementation 7597 * resembles the first-half of the igb_resume routine. 7598 **/ 7599static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 7600{ 7601 struct net_device *netdev = pci_get_drvdata(pdev); 7602 struct igb_adapter *adapter = netdev_priv(netdev); 7603 struct e1000_hw *hw = &adapter->hw; 7604 pci_ers_result_t result; 7605 int err; 7606 7607 if (pci_enable_device_mem(pdev)) { 7608 dev_err(&pdev->dev, 7609 "Cannot re-enable PCI device after reset.\n"); 7610 result = PCI_ERS_RESULT_DISCONNECT; 7611 } else { 7612 pci_set_master(pdev); 7613 pci_restore_state(pdev); 7614 pci_save_state(pdev); 7615 7616 pci_enable_wake(pdev, PCI_D3hot, 0); 7617 pci_enable_wake(pdev, PCI_D3cold, 0); 7618 7619 igb_reset(adapter); 7620 wr32(E1000_WUS, ~0); 7621 result = PCI_ERS_RESULT_RECOVERED; 7622 } 7623 7624 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7625 if (err) { 7626 dev_err(&pdev->dev, 7627 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7628 err); 7629 /* non-fatal, continue */ 7630 } 7631 7632 return result; 7633} 7634 7635/** 7636 * igb_io_resume - called when traffic can start flowing again. 7637 * @pdev: Pointer to PCI device 7638 * 7639 * This callback is called when the error recovery driver tells us that 7640 * its OK to resume normal operation. Implementation resembles the 7641 * second-half of the igb_resume routine. 7642 */ 7643static void igb_io_resume(struct pci_dev *pdev) 7644{ 7645 struct net_device *netdev = pci_get_drvdata(pdev); 7646 struct igb_adapter *adapter = netdev_priv(netdev); 7647 7648 if (netif_running(netdev)) { 7649 if (igb_up(adapter)) { 7650 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7651 return; 7652 } 7653 } 7654 7655 netif_device_attach(netdev); 7656 7657 /* let the f/w know that the h/w is now under the control of the 7658 * driver. 7659 */ 7660 igb_get_hw_control(adapter); 7661} 7662 7663static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7664 u8 qsel) 7665{ 7666 u32 rar_low, rar_high; 7667 struct e1000_hw *hw = &adapter->hw; 7668 7669 /* HW expects these in little endian so we reverse the byte order 7670 * from network order (big endian) to little endian 7671 */ 7672 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 7673 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 7674 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 7675 7676 /* Indicate to hardware the Address is Valid. */ 7677 rar_high |= E1000_RAH_AV; 7678 7679 if (hw->mac.type == e1000_82575) 7680 rar_high |= E1000_RAH_POOL_1 * qsel; 7681 else 7682 rar_high |= E1000_RAH_POOL_1 << qsel; 7683 7684 wr32(E1000_RAL(index), rar_low); 7685 wrfl(); 7686 wr32(E1000_RAH(index), rar_high); 7687 wrfl(); 7688} 7689 7690static int igb_set_vf_mac(struct igb_adapter *adapter, 7691 int vf, unsigned char *mac_addr) 7692{ 7693 struct e1000_hw *hw = &adapter->hw; 7694 /* VF MAC addresses start at end of receive addresses and moves 7695 * towards the first, as a result a collision should not be possible 7696 */ 7697 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7698 7699 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7700 7701 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7702 7703 return 0; 7704} 7705 7706static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7707{ 7708 struct igb_adapter *adapter = netdev_priv(netdev); 7709 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7710 return -EINVAL; 7711 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7712 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7713 dev_info(&adapter->pdev->dev, 7714 "Reload the VF driver to make this change effective."); 7715 if (test_bit(__IGB_DOWN, &adapter->state)) { 7716 dev_warn(&adapter->pdev->dev, 7717 "The VF MAC address has been set, but the PF device is not up.\n"); 7718 dev_warn(&adapter->pdev->dev, 7719 "Bring the PF device up before attempting to use the VF device.\n"); 7720 } 7721 return igb_set_vf_mac(adapter, vf, mac); 7722} 7723 7724static int igb_link_mbps(int internal_link_speed) 7725{ 7726 switch (internal_link_speed) { 7727 case SPEED_100: 7728 return 100; 7729 case SPEED_1000: 7730 return 1000; 7731 default: 7732 return 0; 7733 } 7734} 7735 7736static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7737 int link_speed) 7738{ 7739 int rf_dec, rf_int; 7740 u32 bcnrc_val; 7741 7742 if (tx_rate != 0) { 7743 /* Calculate the rate factor values to set */ 7744 rf_int = link_speed / tx_rate; 7745 rf_dec = (link_speed - (rf_int * tx_rate)); 7746 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / 7747 tx_rate; 7748 7749 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7750 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 7751 E1000_RTTBCNRC_RF_INT_MASK); 7752 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7753 } else { 7754 bcnrc_val = 0; 7755 } 7756 7757 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7758 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7759 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7760 */ 7761 wr32(E1000_RTTBCNRM, 0x14); 7762 wr32(E1000_RTTBCNRC, bcnrc_val); 7763} 7764 7765static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7766{ 7767 int actual_link_speed, i; 7768 bool reset_rate = false; 7769 7770 /* VF TX rate limit was not set or not supported */ 7771 if ((adapter->vf_rate_link_speed == 0) || 7772 (adapter->hw.mac.type != e1000_82576)) 7773 return; 7774 7775 actual_link_speed = igb_link_mbps(adapter->link_speed); 7776 if (actual_link_speed != adapter->vf_rate_link_speed) { 7777 reset_rate = true; 7778 adapter->vf_rate_link_speed = 0; 7779 dev_info(&adapter->pdev->dev, 7780 "Link speed has been changed. VF Transmit rate is disabled\n"); 7781 } 7782 7783 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7784 if (reset_rate) 7785 adapter->vf_data[i].tx_rate = 0; 7786 7787 igb_set_vf_rate_limit(&adapter->hw, i, 7788 adapter->vf_data[i].tx_rate, 7789 actual_link_speed); 7790 } 7791} 7792 7793static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) 7794{ 7795 struct igb_adapter *adapter = netdev_priv(netdev); 7796 struct e1000_hw *hw = &adapter->hw; 7797 int actual_link_speed; 7798 7799 if (hw->mac.type != e1000_82576) 7800 return -EOPNOTSUPP; 7801 7802 actual_link_speed = igb_link_mbps(adapter->link_speed); 7803 if ((vf >= adapter->vfs_allocated_count) || 7804 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7805 (tx_rate < 0) || (tx_rate > actual_link_speed)) 7806 return -EINVAL; 7807 7808 adapter->vf_rate_link_speed = actual_link_speed; 7809 adapter->vf_data[vf].tx_rate = (u16)tx_rate; 7810 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); 7811 7812 return 0; 7813} 7814 7815static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 7816 bool setting) 7817{ 7818 struct igb_adapter *adapter = netdev_priv(netdev); 7819 struct e1000_hw *hw = &adapter->hw; 7820 u32 reg_val, reg_offset; 7821 7822 if (!adapter->vfs_allocated_count) 7823 return -EOPNOTSUPP; 7824 7825 if (vf >= adapter->vfs_allocated_count) 7826 return -EINVAL; 7827 7828 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 7829 reg_val = rd32(reg_offset); 7830 if (setting) 7831 reg_val |= ((1 << vf) | 7832 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7833 else 7834 reg_val &= ~((1 << vf) | 7835 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7836 wr32(reg_offset, reg_val); 7837 7838 adapter->vf_data[vf].spoofchk_enabled = setting; 7839 return E1000_SUCCESS; 7840} 7841 7842static int igb_ndo_get_vf_config(struct net_device *netdev, 7843 int vf, struct ifla_vf_info *ivi) 7844{ 7845 struct igb_adapter *adapter = netdev_priv(netdev); 7846 if (vf >= adapter->vfs_allocated_count) 7847 return -EINVAL; 7848 ivi->vf = vf; 7849 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7850 ivi->tx_rate = adapter->vf_data[vf].tx_rate; 7851 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7852 ivi->qos = adapter->vf_data[vf].pf_qos; 7853 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 7854 return 0; 7855} 7856 7857static void igb_vmm_control(struct igb_adapter *adapter) 7858{ 7859 struct e1000_hw *hw = &adapter->hw; 7860 u32 reg; 7861 7862 switch (hw->mac.type) { 7863 case e1000_82575: 7864 case e1000_i210: 7865 case e1000_i211: 7866 case e1000_i354: 7867 default: 7868 /* replication is not supported for 82575 */ 7869 return; 7870 case e1000_82576: 7871 /* notify HW that the MAC is adding vlan tags */ 7872 reg = rd32(E1000_DTXCTL); 7873 reg |= E1000_DTXCTL_VLAN_ADDED; 7874 wr32(E1000_DTXCTL, reg); 7875 case e1000_82580: 7876 /* enable replication vlan tag stripping */ 7877 reg = rd32(E1000_RPLOLR); 7878 reg |= E1000_RPLOLR_STRVLAN; 7879 wr32(E1000_RPLOLR, reg); 7880 case e1000_i350: 7881 /* none of the above registers are supported by i350 */ 7882 break; 7883 } 7884 7885 if (adapter->vfs_allocated_count) { 7886 igb_vmdq_set_loopback_pf(hw, true); 7887 igb_vmdq_set_replication_pf(hw, true); 7888 igb_vmdq_set_anti_spoofing_pf(hw, true, 7889 adapter->vfs_allocated_count); 7890 } else { 7891 igb_vmdq_set_loopback_pf(hw, false); 7892 igb_vmdq_set_replication_pf(hw, false); 7893 } 7894} 7895 7896static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7897{ 7898 struct e1000_hw *hw = &adapter->hw; 7899 u32 dmac_thr; 7900 u16 hwm; 7901 7902 if (hw->mac.type > e1000_82580) { 7903 if (adapter->flags & IGB_FLAG_DMAC) { 7904 u32 reg; 7905 7906 /* force threshold to 0. */ 7907 wr32(E1000_DMCTXTH, 0); 7908 7909 /* DMA Coalescing high water mark needs to be greater 7910 * than the Rx threshold. Set hwm to PBA - max frame 7911 * size in 16B units, capping it at PBA - 6KB. 7912 */ 7913 hwm = 64 * pba - adapter->max_frame_size / 16; 7914 if (hwm < 64 * (pba - 6)) 7915 hwm = 64 * (pba - 6); 7916 reg = rd32(E1000_FCRTC); 7917 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 7918 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 7919 & E1000_FCRTC_RTH_COAL_MASK); 7920 wr32(E1000_FCRTC, reg); 7921 7922 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 7923 * frame size, capping it at PBA - 10KB. 7924 */ 7925 dmac_thr = pba - adapter->max_frame_size / 512; 7926 if (dmac_thr < pba - 10) 7927 dmac_thr = pba - 10; 7928 reg = rd32(E1000_DMACR); 7929 reg &= ~E1000_DMACR_DMACTHR_MASK; 7930 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 7931 & E1000_DMACR_DMACTHR_MASK); 7932 7933 /* transition to L0x or L1 if available..*/ 7934 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 7935 7936 /* watchdog timer= +-1000 usec in 32usec intervals */ 7937 reg |= (1000 >> 5); 7938 7939 /* Disable BMC-to-OS Watchdog Enable */ 7940 if (hw->mac.type != e1000_i354) 7941 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 7942 7943 wr32(E1000_DMACR, reg); 7944 7945 /* no lower threshold to disable 7946 * coalescing(smart fifb)-UTRESH=0 7947 */ 7948 wr32(E1000_DMCRTRH, 0); 7949 7950 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 7951 7952 wr32(E1000_DMCTLX, reg); 7953 7954 /* free space in tx packet buffer to wake from 7955 * DMA coal 7956 */ 7957 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 7958 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 7959 7960 /* make low power state decision controlled 7961 * by DMA coal 7962 */ 7963 reg = rd32(E1000_PCIEMISC); 7964 reg &= ~E1000_PCIEMISC_LX_DECISION; 7965 wr32(E1000_PCIEMISC, reg); 7966 } /* endif adapter->dmac is not disabled */ 7967 } else if (hw->mac.type == e1000_82580) { 7968 u32 reg = rd32(E1000_PCIEMISC); 7969 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 7970 wr32(E1000_DMACR, 0); 7971 } 7972} 7973 7974/** 7975 * igb_read_i2c_byte - Reads 8 bit word over I2C 7976 * @hw: pointer to hardware structure 7977 * @byte_offset: byte offset to read 7978 * @dev_addr: device address 7979 * @data: value read 7980 * 7981 * Performs byte read operation over I2C interface at 7982 * a specified device address. 7983 **/ 7984s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 7985 u8 dev_addr, u8 *data) 7986{ 7987 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 7988 struct i2c_client *this_client = adapter->i2c_client; 7989 s32 status; 7990 u16 swfw_mask = 0; 7991 7992 if (!this_client) 7993 return E1000_ERR_I2C; 7994 7995 swfw_mask = E1000_SWFW_PHY0_SM; 7996 7997 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 7998 != E1000_SUCCESS) 7999 return E1000_ERR_SWFW_SYNC; 8000 8001 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8002 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8003 8004 if (status < 0) 8005 return E1000_ERR_I2C; 8006 else { 8007 *data = status; 8008 return E1000_SUCCESS; 8009 } 8010} 8011 8012/** 8013 * igb_write_i2c_byte - Writes 8 bit word over I2C 8014 * @hw: pointer to hardware structure 8015 * @byte_offset: byte offset to write 8016 * @dev_addr: device address 8017 * @data: value to write 8018 * 8019 * Performs byte write operation over I2C interface at 8020 * a specified device address. 8021 **/ 8022s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8023 u8 dev_addr, u8 data) 8024{ 8025 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8026 struct i2c_client *this_client = adapter->i2c_client; 8027 s32 status; 8028 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8029 8030 if (!this_client) 8031 return E1000_ERR_I2C; 8032 8033 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) 8034 return E1000_ERR_SWFW_SYNC; 8035 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8036 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8037 8038 if (status) 8039 return E1000_ERR_I2C; 8040 else 8041 return E1000_SUCCESS; 8042 8043} 8044 8045int igb_reinit_queues(struct igb_adapter *adapter) 8046{ 8047 struct net_device *netdev = adapter->netdev; 8048 struct pci_dev *pdev = adapter->pdev; 8049 int err = 0; 8050 8051 if (netif_running(netdev)) 8052 igb_close(netdev); 8053 8054 igb_reset_interrupt_capability(adapter); 8055 8056 if (igb_init_interrupt_scheme(adapter, true)) { 8057 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8058 return -ENOMEM; 8059 } 8060 8061 if (netif_running(netdev)) 8062 err = igb_open(netdev); 8063 8064 return err; 8065} 8066/* igb_main.c */ 8067