igb_main.c revision 9005df38615bb3545cb6e4db59db73b27b6c0140
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25*******************************************************************************/ 26 27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 28 29#include <linux/module.h> 30#include <linux/types.h> 31#include <linux/init.h> 32#include <linux/bitops.h> 33#include <linux/vmalloc.h> 34#include <linux/pagemap.h> 35#include <linux/netdevice.h> 36#include <linux/ipv6.h> 37#include <linux/slab.h> 38#include <net/checksum.h> 39#include <net/ip6_checksum.h> 40#include <linux/net_tstamp.h> 41#include <linux/mii.h> 42#include <linux/ethtool.h> 43#include <linux/if.h> 44#include <linux/if_vlan.h> 45#include <linux/pci.h> 46#include <linux/pci-aspm.h> 47#include <linux/delay.h> 48#include <linux/interrupt.h> 49#include <linux/ip.h> 50#include <linux/tcp.h> 51#include <linux/sctp.h> 52#include <linux/if_ether.h> 53#include <linux/aer.h> 54#include <linux/prefetch.h> 55#include <linux/pm_runtime.h> 56#ifdef CONFIG_IGB_DCA 57#include <linux/dca.h> 58#endif 59#include <linux/i2c.h> 60#include "igb.h" 61 62#define MAJ 5 63#define MIN 0 64#define BUILD 5 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 66__stringify(BUILD) "-k" 67char igb_driver_name[] = "igb"; 68char igb_driver_version[] = DRV_VERSION; 69static const char igb_driver_string[] = 70 "Intel(R) Gigabit Ethernet Network Driver"; 71static const char igb_copyright[] = 72 "Copyright (c) 2007-2014 Intel Corporation."; 73 74static const struct e1000_info *igb_info_tbl[] = { 75 [board_82575] = &e1000_82575_info, 76}; 77 78static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 114 /* required last entry */ 115 {0, } 116}; 117 118MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 119 120void igb_reset(struct igb_adapter *); 121static int igb_setup_all_tx_resources(struct igb_adapter *); 122static int igb_setup_all_rx_resources(struct igb_adapter *); 123static void igb_free_all_tx_resources(struct igb_adapter *); 124static void igb_free_all_rx_resources(struct igb_adapter *); 125static void igb_setup_mrqc(struct igb_adapter *); 126static int igb_probe(struct pci_dev *, const struct pci_device_id *); 127static void igb_remove(struct pci_dev *pdev); 128static int igb_sw_init(struct igb_adapter *); 129static int igb_open(struct net_device *); 130static int igb_close(struct net_device *); 131static void igb_configure(struct igb_adapter *); 132static void igb_configure_tx(struct igb_adapter *); 133static void igb_configure_rx(struct igb_adapter *); 134static void igb_clean_all_tx_rings(struct igb_adapter *); 135static void igb_clean_all_rx_rings(struct igb_adapter *); 136static void igb_clean_tx_ring(struct igb_ring *); 137static void igb_clean_rx_ring(struct igb_ring *); 138static void igb_set_rx_mode(struct net_device *); 139static void igb_update_phy_info(unsigned long); 140static void igb_watchdog(unsigned long); 141static void igb_watchdog_task(struct work_struct *); 142static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 143static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 144 struct rtnl_link_stats64 *stats); 145static int igb_change_mtu(struct net_device *, int); 146static int igb_set_mac(struct net_device *, void *); 147static void igb_set_uta(struct igb_adapter *adapter); 148static irqreturn_t igb_intr(int irq, void *); 149static irqreturn_t igb_intr_msi(int irq, void *); 150static irqreturn_t igb_msix_other(int irq, void *); 151static irqreturn_t igb_msix_ring(int irq, void *); 152#ifdef CONFIG_IGB_DCA 153static void igb_update_dca(struct igb_q_vector *); 154static void igb_setup_dca(struct igb_adapter *); 155#endif /* CONFIG_IGB_DCA */ 156static int igb_poll(struct napi_struct *, int); 157static bool igb_clean_tx_irq(struct igb_q_vector *); 158static bool igb_clean_rx_irq(struct igb_q_vector *, int); 159static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 160static void igb_tx_timeout(struct net_device *); 161static void igb_reset_task(struct work_struct *); 162static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); 163static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 164static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 165static void igb_restore_vlan(struct igb_adapter *); 166static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 167static void igb_ping_all_vfs(struct igb_adapter *); 168static void igb_msg_task(struct igb_adapter *); 169static void igb_vmm_control(struct igb_adapter *); 170static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 171static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 172static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 173static int igb_ndo_set_vf_vlan(struct net_device *netdev, 174 int vf, u16 vlan, u8 qos); 175static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 176static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 177 bool setting); 178static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 179 struct ifla_vf_info *ivi); 180static void igb_check_vf_rate_limit(struct igb_adapter *); 181 182#ifdef CONFIG_PCI_IOV 183static int igb_vf_configure(struct igb_adapter *adapter, int vf); 184static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 185#endif 186 187#ifdef CONFIG_PM 188#ifdef CONFIG_PM_SLEEP 189static int igb_suspend(struct device *); 190#endif 191static int igb_resume(struct device *); 192#ifdef CONFIG_PM_RUNTIME 193static int igb_runtime_suspend(struct device *dev); 194static int igb_runtime_resume(struct device *dev); 195static int igb_runtime_idle(struct device *dev); 196#endif 197static const struct dev_pm_ops igb_pm_ops = { 198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 200 igb_runtime_idle) 201}; 202#endif 203static void igb_shutdown(struct pci_dev *); 204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 205#ifdef CONFIG_IGB_DCA 206static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 207static struct notifier_block dca_notifier = { 208 .notifier_call = igb_notify_dca, 209 .next = NULL, 210 .priority = 0 211}; 212#endif 213#ifdef CONFIG_NET_POLL_CONTROLLER 214/* for netdump / net console */ 215static void igb_netpoll(struct net_device *); 216#endif 217#ifdef CONFIG_PCI_IOV 218static unsigned int max_vfs = 0; 219module_param(max_vfs, uint, 0); 220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 221#endif /* CONFIG_PCI_IOV */ 222 223static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 224 pci_channel_state_t); 225static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 226static void igb_io_resume(struct pci_dev *); 227 228static const struct pci_error_handlers igb_err_handler = { 229 .error_detected = igb_io_error_detected, 230 .slot_reset = igb_io_slot_reset, 231 .resume = igb_io_resume, 232}; 233 234static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 235 236static struct pci_driver igb_driver = { 237 .name = igb_driver_name, 238 .id_table = igb_pci_tbl, 239 .probe = igb_probe, 240 .remove = igb_remove, 241#ifdef CONFIG_PM 242 .driver.pm = &igb_pm_ops, 243#endif 244 .shutdown = igb_shutdown, 245 .sriov_configure = igb_pci_sriov_configure, 246 .err_handler = &igb_err_handler 247}; 248 249MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 250MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 251MODULE_LICENSE("GPL"); 252MODULE_VERSION(DRV_VERSION); 253 254#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 255static int debug = -1; 256module_param(debug, int, 0); 257MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 258 259struct igb_reg_info { 260 u32 ofs; 261 char *name; 262}; 263 264static const struct igb_reg_info igb_reg_info_tbl[] = { 265 266 /* General Registers */ 267 {E1000_CTRL, "CTRL"}, 268 {E1000_STATUS, "STATUS"}, 269 {E1000_CTRL_EXT, "CTRL_EXT"}, 270 271 /* Interrupt Registers */ 272 {E1000_ICR, "ICR"}, 273 274 /* RX Registers */ 275 {E1000_RCTL, "RCTL"}, 276 {E1000_RDLEN(0), "RDLEN"}, 277 {E1000_RDH(0), "RDH"}, 278 {E1000_RDT(0), "RDT"}, 279 {E1000_RXDCTL(0), "RXDCTL"}, 280 {E1000_RDBAL(0), "RDBAL"}, 281 {E1000_RDBAH(0), "RDBAH"}, 282 283 /* TX Registers */ 284 {E1000_TCTL, "TCTL"}, 285 {E1000_TDBAL(0), "TDBAL"}, 286 {E1000_TDBAH(0), "TDBAH"}, 287 {E1000_TDLEN(0), "TDLEN"}, 288 {E1000_TDH(0), "TDH"}, 289 {E1000_TDT(0), "TDT"}, 290 {E1000_TXDCTL(0), "TXDCTL"}, 291 {E1000_TDFH, "TDFH"}, 292 {E1000_TDFT, "TDFT"}, 293 {E1000_TDFHS, "TDFHS"}, 294 {E1000_TDFPC, "TDFPC"}, 295 296 /* List Terminator */ 297 {} 298}; 299 300/* igb_regdump - register printout routine */ 301static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 302{ 303 int n = 0; 304 char rname[16]; 305 u32 regs[8]; 306 307 switch (reginfo->ofs) { 308 case E1000_RDLEN(0): 309 for (n = 0; n < 4; n++) 310 regs[n] = rd32(E1000_RDLEN(n)); 311 break; 312 case E1000_RDH(0): 313 for (n = 0; n < 4; n++) 314 regs[n] = rd32(E1000_RDH(n)); 315 break; 316 case E1000_RDT(0): 317 for (n = 0; n < 4; n++) 318 regs[n] = rd32(E1000_RDT(n)); 319 break; 320 case E1000_RXDCTL(0): 321 for (n = 0; n < 4; n++) 322 regs[n] = rd32(E1000_RXDCTL(n)); 323 break; 324 case E1000_RDBAL(0): 325 for (n = 0; n < 4; n++) 326 regs[n] = rd32(E1000_RDBAL(n)); 327 break; 328 case E1000_RDBAH(0): 329 for (n = 0; n < 4; n++) 330 regs[n] = rd32(E1000_RDBAH(n)); 331 break; 332 case E1000_TDBAL(0): 333 for (n = 0; n < 4; n++) 334 regs[n] = rd32(E1000_RDBAL(n)); 335 break; 336 case E1000_TDBAH(0): 337 for (n = 0; n < 4; n++) 338 regs[n] = rd32(E1000_TDBAH(n)); 339 break; 340 case E1000_TDLEN(0): 341 for (n = 0; n < 4; n++) 342 regs[n] = rd32(E1000_TDLEN(n)); 343 break; 344 case E1000_TDH(0): 345 for (n = 0; n < 4; n++) 346 regs[n] = rd32(E1000_TDH(n)); 347 break; 348 case E1000_TDT(0): 349 for (n = 0; n < 4; n++) 350 regs[n] = rd32(E1000_TDT(n)); 351 break; 352 case E1000_TXDCTL(0): 353 for (n = 0; n < 4; n++) 354 regs[n] = rd32(E1000_TXDCTL(n)); 355 break; 356 default: 357 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 358 return; 359 } 360 361 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 362 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 363 regs[2], regs[3]); 364} 365 366/* igb_dump - Print registers, Tx-rings and Rx-rings */ 367static void igb_dump(struct igb_adapter *adapter) 368{ 369 struct net_device *netdev = adapter->netdev; 370 struct e1000_hw *hw = &adapter->hw; 371 struct igb_reg_info *reginfo; 372 struct igb_ring *tx_ring; 373 union e1000_adv_tx_desc *tx_desc; 374 struct my_u0 { u64 a; u64 b; } *u0; 375 struct igb_ring *rx_ring; 376 union e1000_adv_rx_desc *rx_desc; 377 u32 staterr; 378 u16 i, n; 379 380 if (!netif_msg_hw(adapter)) 381 return; 382 383 /* Print netdevice Info */ 384 if (netdev) { 385 dev_info(&adapter->pdev->dev, "Net device Info\n"); 386 pr_info("Device Name state trans_start last_rx\n"); 387 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 388 netdev->state, netdev->trans_start, netdev->last_rx); 389 } 390 391 /* Print Registers */ 392 dev_info(&adapter->pdev->dev, "Register Dump\n"); 393 pr_info(" Register Name Value\n"); 394 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 395 reginfo->name; reginfo++) { 396 igb_regdump(hw, reginfo); 397 } 398 399 /* Print TX Ring Summary */ 400 if (!netdev || !netif_running(netdev)) 401 goto exit; 402 403 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 404 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 405 for (n = 0; n < adapter->num_tx_queues; n++) { 406 struct igb_tx_buffer *buffer_info; 407 tx_ring = adapter->tx_ring[n]; 408 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 409 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 410 n, tx_ring->next_to_use, tx_ring->next_to_clean, 411 (u64)dma_unmap_addr(buffer_info, dma), 412 dma_unmap_len(buffer_info, len), 413 buffer_info->next_to_watch, 414 (u64)buffer_info->time_stamp); 415 } 416 417 /* Print TX Rings */ 418 if (!netif_msg_tx_done(adapter)) 419 goto rx_ring_summary; 420 421 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 422 423 /* Transmit Descriptor Formats 424 * 425 * Advanced Transmit Descriptor 426 * +--------------------------------------------------------------+ 427 * 0 | Buffer Address [63:0] | 428 * +--------------------------------------------------------------+ 429 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 430 * +--------------------------------------------------------------+ 431 * 63 46 45 40 39 38 36 35 32 31 24 15 0 432 */ 433 434 for (n = 0; n < adapter->num_tx_queues; n++) { 435 tx_ring = adapter->tx_ring[n]; 436 pr_info("------------------------------------\n"); 437 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 438 pr_info("------------------------------------\n"); 439 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 440 441 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 442 const char *next_desc; 443 struct igb_tx_buffer *buffer_info; 444 tx_desc = IGB_TX_DESC(tx_ring, i); 445 buffer_info = &tx_ring->tx_buffer_info[i]; 446 u0 = (struct my_u0 *)tx_desc; 447 if (i == tx_ring->next_to_use && 448 i == tx_ring->next_to_clean) 449 next_desc = " NTC/U"; 450 else if (i == tx_ring->next_to_use) 451 next_desc = " NTU"; 452 else if (i == tx_ring->next_to_clean) 453 next_desc = " NTC"; 454 else 455 next_desc = ""; 456 457 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 458 i, le64_to_cpu(u0->a), 459 le64_to_cpu(u0->b), 460 (u64)dma_unmap_addr(buffer_info, dma), 461 dma_unmap_len(buffer_info, len), 462 buffer_info->next_to_watch, 463 (u64)buffer_info->time_stamp, 464 buffer_info->skb, next_desc); 465 466 if (netif_msg_pktdata(adapter) && buffer_info->skb) 467 print_hex_dump(KERN_INFO, "", 468 DUMP_PREFIX_ADDRESS, 469 16, 1, buffer_info->skb->data, 470 dma_unmap_len(buffer_info, len), 471 true); 472 } 473 } 474 475 /* Print RX Rings Summary */ 476rx_ring_summary: 477 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 478 pr_info("Queue [NTU] [NTC]\n"); 479 for (n = 0; n < adapter->num_rx_queues; n++) { 480 rx_ring = adapter->rx_ring[n]; 481 pr_info(" %5d %5X %5X\n", 482 n, rx_ring->next_to_use, rx_ring->next_to_clean); 483 } 484 485 /* Print RX Rings */ 486 if (!netif_msg_rx_status(adapter)) 487 goto exit; 488 489 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 490 491 /* Advanced Receive Descriptor (Read) Format 492 * 63 1 0 493 * +-----------------------------------------------------+ 494 * 0 | Packet Buffer Address [63:1] |A0/NSE| 495 * +----------------------------------------------+------+ 496 * 8 | Header Buffer Address [63:1] | DD | 497 * +-----------------------------------------------------+ 498 * 499 * 500 * Advanced Receive Descriptor (Write-Back) Format 501 * 502 * 63 48 47 32 31 30 21 20 17 16 4 3 0 503 * +------------------------------------------------------+ 504 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 505 * | Checksum Ident | | | | Type | Type | 506 * +------------------------------------------------------+ 507 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 508 * +------------------------------------------------------+ 509 * 63 48 47 32 31 20 19 0 510 */ 511 512 for (n = 0; n < adapter->num_rx_queues; n++) { 513 rx_ring = adapter->rx_ring[n]; 514 pr_info("------------------------------------\n"); 515 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 516 pr_info("------------------------------------\n"); 517 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 518 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 519 520 for (i = 0; i < rx_ring->count; i++) { 521 const char *next_desc; 522 struct igb_rx_buffer *buffer_info; 523 buffer_info = &rx_ring->rx_buffer_info[i]; 524 rx_desc = IGB_RX_DESC(rx_ring, i); 525 u0 = (struct my_u0 *)rx_desc; 526 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 527 528 if (i == rx_ring->next_to_use) 529 next_desc = " NTU"; 530 else if (i == rx_ring->next_to_clean) 531 next_desc = " NTC"; 532 else 533 next_desc = ""; 534 535 if (staterr & E1000_RXD_STAT_DD) { 536 /* Descriptor Done */ 537 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 538 "RWB", i, 539 le64_to_cpu(u0->a), 540 le64_to_cpu(u0->b), 541 next_desc); 542 } else { 543 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 544 "R ", i, 545 le64_to_cpu(u0->a), 546 le64_to_cpu(u0->b), 547 (u64)buffer_info->dma, 548 next_desc); 549 550 if (netif_msg_pktdata(adapter) && 551 buffer_info->dma && buffer_info->page) { 552 print_hex_dump(KERN_INFO, "", 553 DUMP_PREFIX_ADDRESS, 554 16, 1, 555 page_address(buffer_info->page) + 556 buffer_info->page_offset, 557 IGB_RX_BUFSZ, true); 558 } 559 } 560 } 561 } 562 563exit: 564 return; 565} 566 567/** 568 * igb_get_i2c_data - Reads the I2C SDA data bit 569 * @hw: pointer to hardware structure 570 * @i2cctl: Current value of I2CCTL register 571 * 572 * Returns the I2C data bit value 573 **/ 574static int igb_get_i2c_data(void *data) 575{ 576 struct igb_adapter *adapter = (struct igb_adapter *)data; 577 struct e1000_hw *hw = &adapter->hw; 578 s32 i2cctl = rd32(E1000_I2CPARAMS); 579 580 return ((i2cctl & E1000_I2C_DATA_IN) != 0); 581} 582 583/** 584 * igb_set_i2c_data - Sets the I2C data bit 585 * @data: pointer to hardware structure 586 * @state: I2C data value (0 or 1) to set 587 * 588 * Sets the I2C data bit 589 **/ 590static void igb_set_i2c_data(void *data, int state) 591{ 592 struct igb_adapter *adapter = (struct igb_adapter *)data; 593 struct e1000_hw *hw = &adapter->hw; 594 s32 i2cctl = rd32(E1000_I2CPARAMS); 595 596 if (state) 597 i2cctl |= E1000_I2C_DATA_OUT; 598 else 599 i2cctl &= ~E1000_I2C_DATA_OUT; 600 601 i2cctl &= ~E1000_I2C_DATA_OE_N; 602 i2cctl |= E1000_I2C_CLK_OE_N; 603 wr32(E1000_I2CPARAMS, i2cctl); 604 wrfl(); 605 606} 607 608/** 609 * igb_set_i2c_clk - Sets the I2C SCL clock 610 * @data: pointer to hardware structure 611 * @state: state to set clock 612 * 613 * Sets the I2C clock line to state 614 **/ 615static void igb_set_i2c_clk(void *data, int state) 616{ 617 struct igb_adapter *adapter = (struct igb_adapter *)data; 618 struct e1000_hw *hw = &adapter->hw; 619 s32 i2cctl = rd32(E1000_I2CPARAMS); 620 621 if (state) { 622 i2cctl |= E1000_I2C_CLK_OUT; 623 i2cctl &= ~E1000_I2C_CLK_OE_N; 624 } else { 625 i2cctl &= ~E1000_I2C_CLK_OUT; 626 i2cctl &= ~E1000_I2C_CLK_OE_N; 627 } 628 wr32(E1000_I2CPARAMS, i2cctl); 629 wrfl(); 630} 631 632/** 633 * igb_get_i2c_clk - Gets the I2C SCL clock state 634 * @data: pointer to hardware structure 635 * 636 * Gets the I2C clock state 637 **/ 638static int igb_get_i2c_clk(void *data) 639{ 640 struct igb_adapter *adapter = (struct igb_adapter *)data; 641 struct e1000_hw *hw = &adapter->hw; 642 s32 i2cctl = rd32(E1000_I2CPARAMS); 643 644 return ((i2cctl & E1000_I2C_CLK_IN) != 0); 645} 646 647static const struct i2c_algo_bit_data igb_i2c_algo = { 648 .setsda = igb_set_i2c_data, 649 .setscl = igb_set_i2c_clk, 650 .getsda = igb_get_i2c_data, 651 .getscl = igb_get_i2c_clk, 652 .udelay = 5, 653 .timeout = 20, 654}; 655 656/** 657 * igb_get_hw_dev - return device 658 * @hw: pointer to hardware structure 659 * 660 * used by hardware layer to print debugging information 661 **/ 662struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 663{ 664 struct igb_adapter *adapter = hw->back; 665 return adapter->netdev; 666} 667 668/** 669 * igb_init_module - Driver Registration Routine 670 * 671 * igb_init_module is the first routine called when the driver is 672 * loaded. All it does is register with the PCI subsystem. 673 **/ 674static int __init igb_init_module(void) 675{ 676 int ret; 677 678 pr_info("%s - version %s\n", 679 igb_driver_string, igb_driver_version); 680 pr_info("%s\n", igb_copyright); 681 682#ifdef CONFIG_IGB_DCA 683 dca_register_notify(&dca_notifier); 684#endif 685 ret = pci_register_driver(&igb_driver); 686 return ret; 687} 688 689module_init(igb_init_module); 690 691/** 692 * igb_exit_module - Driver Exit Cleanup Routine 693 * 694 * igb_exit_module is called just before the driver is removed 695 * from memory. 696 **/ 697static void __exit igb_exit_module(void) 698{ 699#ifdef CONFIG_IGB_DCA 700 dca_unregister_notify(&dca_notifier); 701#endif 702 pci_unregister_driver(&igb_driver); 703} 704 705module_exit(igb_exit_module); 706 707#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 708/** 709 * igb_cache_ring_register - Descriptor ring to register mapping 710 * @adapter: board private structure to initialize 711 * 712 * Once we know the feature-set enabled for the device, we'll cache 713 * the register offset the descriptor ring is assigned to. 714 **/ 715static void igb_cache_ring_register(struct igb_adapter *adapter) 716{ 717 int i = 0, j = 0; 718 u32 rbase_offset = adapter->vfs_allocated_count; 719 720 switch (adapter->hw.mac.type) { 721 case e1000_82576: 722 /* The queues are allocated for virtualization such that VF 0 723 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 724 * In order to avoid collision we start at the first free queue 725 * and continue consuming queues in the same sequence 726 */ 727 if (adapter->vfs_allocated_count) { 728 for (; i < adapter->rss_queues; i++) 729 adapter->rx_ring[i]->reg_idx = rbase_offset + 730 Q_IDX_82576(i); 731 } 732 case e1000_82575: 733 case e1000_82580: 734 case e1000_i350: 735 case e1000_i354: 736 case e1000_i210: 737 case e1000_i211: 738 default: 739 for (; i < adapter->num_rx_queues; i++) 740 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 741 for (; j < adapter->num_tx_queues; j++) 742 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 743 break; 744 } 745} 746 747u32 igb_rd32(struct e1000_hw *hw, u32 reg) 748{ 749 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 750 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 751 u32 value = 0; 752 753 if (E1000_REMOVED(hw_addr)) 754 return ~value; 755 756 value = readl(&hw_addr[reg]); 757 758 /* reads should not return all F's */ 759 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 760 struct net_device *netdev = igb->netdev; 761 hw->hw_addr = NULL; 762 netif_device_detach(netdev); 763 netdev_err(netdev, "PCIe link lost, device now detached\n"); 764 } 765 766 return value; 767} 768 769/** 770 * igb_write_ivar - configure ivar for given MSI-X vector 771 * @hw: pointer to the HW structure 772 * @msix_vector: vector number we are allocating to a given ring 773 * @index: row index of IVAR register to write within IVAR table 774 * @offset: column offset of in IVAR, should be multiple of 8 775 * 776 * This function is intended to handle the writing of the IVAR register 777 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 778 * each containing an cause allocation for an Rx and Tx ring, and a 779 * variable number of rows depending on the number of queues supported. 780 **/ 781static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 782 int index, int offset) 783{ 784 u32 ivar = array_rd32(E1000_IVAR0, index); 785 786 /* clear any bits that are currently set */ 787 ivar &= ~((u32)0xFF << offset); 788 789 /* write vector and valid bit */ 790 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 791 792 array_wr32(E1000_IVAR0, index, ivar); 793} 794 795#define IGB_N0_QUEUE -1 796static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 797{ 798 struct igb_adapter *adapter = q_vector->adapter; 799 struct e1000_hw *hw = &adapter->hw; 800 int rx_queue = IGB_N0_QUEUE; 801 int tx_queue = IGB_N0_QUEUE; 802 u32 msixbm = 0; 803 804 if (q_vector->rx.ring) 805 rx_queue = q_vector->rx.ring->reg_idx; 806 if (q_vector->tx.ring) 807 tx_queue = q_vector->tx.ring->reg_idx; 808 809 switch (hw->mac.type) { 810 case e1000_82575: 811 /* The 82575 assigns vectors using a bitmask, which matches the 812 * bitmask for the EICR/EIMS/EIMC registers. To assign one 813 * or more queues to a vector, we write the appropriate bits 814 * into the MSIXBM register for that vector. 815 */ 816 if (rx_queue > IGB_N0_QUEUE) 817 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 818 if (tx_queue > IGB_N0_QUEUE) 819 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 820 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 821 msixbm |= E1000_EIMS_OTHER; 822 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 823 q_vector->eims_value = msixbm; 824 break; 825 case e1000_82576: 826 /* 82576 uses a table that essentially consists of 2 columns 827 * with 8 rows. The ordering is column-major so we use the 828 * lower 3 bits as the row index, and the 4th bit as the 829 * column offset. 830 */ 831 if (rx_queue > IGB_N0_QUEUE) 832 igb_write_ivar(hw, msix_vector, 833 rx_queue & 0x7, 834 (rx_queue & 0x8) << 1); 835 if (tx_queue > IGB_N0_QUEUE) 836 igb_write_ivar(hw, msix_vector, 837 tx_queue & 0x7, 838 ((tx_queue & 0x8) << 1) + 8); 839 q_vector->eims_value = 1 << msix_vector; 840 break; 841 case e1000_82580: 842 case e1000_i350: 843 case e1000_i354: 844 case e1000_i210: 845 case e1000_i211: 846 /* On 82580 and newer adapters the scheme is similar to 82576 847 * however instead of ordering column-major we have things 848 * ordered row-major. So we traverse the table by using 849 * bit 0 as the column offset, and the remaining bits as the 850 * row index. 851 */ 852 if (rx_queue > IGB_N0_QUEUE) 853 igb_write_ivar(hw, msix_vector, 854 rx_queue >> 1, 855 (rx_queue & 0x1) << 4); 856 if (tx_queue > IGB_N0_QUEUE) 857 igb_write_ivar(hw, msix_vector, 858 tx_queue >> 1, 859 ((tx_queue & 0x1) << 4) + 8); 860 q_vector->eims_value = 1 << msix_vector; 861 break; 862 default: 863 BUG(); 864 break; 865 } 866 867 /* add q_vector eims value to global eims_enable_mask */ 868 adapter->eims_enable_mask |= q_vector->eims_value; 869 870 /* configure q_vector to set itr on first interrupt */ 871 q_vector->set_itr = 1; 872} 873 874/** 875 * igb_configure_msix - Configure MSI-X hardware 876 * @adapter: board private structure to initialize 877 * 878 * igb_configure_msix sets up the hardware to properly 879 * generate MSI-X interrupts. 880 **/ 881static void igb_configure_msix(struct igb_adapter *adapter) 882{ 883 u32 tmp; 884 int i, vector = 0; 885 struct e1000_hw *hw = &adapter->hw; 886 887 adapter->eims_enable_mask = 0; 888 889 /* set vector for other causes, i.e. link changes */ 890 switch (hw->mac.type) { 891 case e1000_82575: 892 tmp = rd32(E1000_CTRL_EXT); 893 /* enable MSI-X PBA support*/ 894 tmp |= E1000_CTRL_EXT_PBA_CLR; 895 896 /* Auto-Mask interrupts upon ICR read. */ 897 tmp |= E1000_CTRL_EXT_EIAME; 898 tmp |= E1000_CTRL_EXT_IRCA; 899 900 wr32(E1000_CTRL_EXT, tmp); 901 902 /* enable msix_other interrupt */ 903 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 904 adapter->eims_other = E1000_EIMS_OTHER; 905 906 break; 907 908 case e1000_82576: 909 case e1000_82580: 910 case e1000_i350: 911 case e1000_i354: 912 case e1000_i210: 913 case e1000_i211: 914 /* Turn on MSI-X capability first, or our settings 915 * won't stick. And it will take days to debug. 916 */ 917 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 918 E1000_GPIE_PBA | E1000_GPIE_EIAME | 919 E1000_GPIE_NSICR); 920 921 /* enable msix_other interrupt */ 922 adapter->eims_other = 1 << vector; 923 tmp = (vector++ | E1000_IVAR_VALID) << 8; 924 925 wr32(E1000_IVAR_MISC, tmp); 926 break; 927 default: 928 /* do nothing, since nothing else supports MSI-X */ 929 break; 930 } /* switch (hw->mac.type) */ 931 932 adapter->eims_enable_mask |= adapter->eims_other; 933 934 for (i = 0; i < adapter->num_q_vectors; i++) 935 igb_assign_vector(adapter->q_vector[i], vector++); 936 937 wrfl(); 938} 939 940/** 941 * igb_request_msix - Initialize MSI-X interrupts 942 * @adapter: board private structure to initialize 943 * 944 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 945 * kernel. 946 **/ 947static int igb_request_msix(struct igb_adapter *adapter) 948{ 949 struct net_device *netdev = adapter->netdev; 950 struct e1000_hw *hw = &adapter->hw; 951 int i, err = 0, vector = 0, free_vector = 0; 952 953 err = request_irq(adapter->msix_entries[vector].vector, 954 igb_msix_other, 0, netdev->name, adapter); 955 if (err) 956 goto err_out; 957 958 for (i = 0; i < adapter->num_q_vectors; i++) { 959 struct igb_q_vector *q_vector = adapter->q_vector[i]; 960 961 vector++; 962 963 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 964 965 if (q_vector->rx.ring && q_vector->tx.ring) 966 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 967 q_vector->rx.ring->queue_index); 968 else if (q_vector->tx.ring) 969 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 970 q_vector->tx.ring->queue_index); 971 else if (q_vector->rx.ring) 972 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 973 q_vector->rx.ring->queue_index); 974 else 975 sprintf(q_vector->name, "%s-unused", netdev->name); 976 977 err = request_irq(adapter->msix_entries[vector].vector, 978 igb_msix_ring, 0, q_vector->name, 979 q_vector); 980 if (err) 981 goto err_free; 982 } 983 984 igb_configure_msix(adapter); 985 return 0; 986 987err_free: 988 /* free already assigned IRQs */ 989 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 990 991 vector--; 992 for (i = 0; i < vector; i++) { 993 free_irq(adapter->msix_entries[free_vector++].vector, 994 adapter->q_vector[i]); 995 } 996err_out: 997 return err; 998} 999 1000/** 1001 * igb_free_q_vector - Free memory allocated for specific interrupt vector 1002 * @adapter: board private structure to initialize 1003 * @v_idx: Index of vector to be freed 1004 * 1005 * This function frees the memory allocated to the q_vector. 1006 **/ 1007static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1008{ 1009 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1010 1011 adapter->q_vector[v_idx] = NULL; 1012 1013 /* igb_get_stats64() might access the rings on this vector, 1014 * we must wait a grace period before freeing it. 1015 */ 1016 kfree_rcu(q_vector, rcu); 1017} 1018 1019/** 1020 * igb_reset_q_vector - Reset config for interrupt vector 1021 * @adapter: board private structure to initialize 1022 * @v_idx: Index of vector to be reset 1023 * 1024 * If NAPI is enabled it will delete any references to the 1025 * NAPI struct. This is preparation for igb_free_q_vector. 1026 **/ 1027static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1028{ 1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1030 1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1032 * allocated. So, q_vector is NULL so we should stop here. 1033 */ 1034 if (!q_vector) 1035 return; 1036 1037 if (q_vector->tx.ring) 1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1039 1040 if (q_vector->rx.ring) 1041 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; 1042 1043 netif_napi_del(&q_vector->napi); 1044 1045} 1046 1047static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1048{ 1049 int v_idx = adapter->num_q_vectors; 1050 1051 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1052 pci_disable_msix(adapter->pdev); 1053 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1054 pci_disable_msi(adapter->pdev); 1055 1056 while (v_idx--) 1057 igb_reset_q_vector(adapter, v_idx); 1058} 1059 1060/** 1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1062 * @adapter: board private structure to initialize 1063 * 1064 * This function frees the memory allocated to the q_vectors. In addition if 1065 * NAPI is enabled it will delete any references to the NAPI struct prior 1066 * to freeing the q_vector. 1067 **/ 1068static void igb_free_q_vectors(struct igb_adapter *adapter) 1069{ 1070 int v_idx = adapter->num_q_vectors; 1071 1072 adapter->num_tx_queues = 0; 1073 adapter->num_rx_queues = 0; 1074 adapter->num_q_vectors = 0; 1075 1076 while (v_idx--) { 1077 igb_reset_q_vector(adapter, v_idx); 1078 igb_free_q_vector(adapter, v_idx); 1079 } 1080} 1081 1082/** 1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1084 * @adapter: board private structure to initialize 1085 * 1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1087 * MSI-X interrupts allocated. 1088 */ 1089static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1090{ 1091 igb_free_q_vectors(adapter); 1092 igb_reset_interrupt_capability(adapter); 1093} 1094 1095/** 1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1097 * @adapter: board private structure to initialize 1098 * @msix: boolean value of MSIX capability 1099 * 1100 * Attempt to configure interrupts using the best available 1101 * capabilities of the hardware and kernel. 1102 **/ 1103static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1104{ 1105 int err; 1106 int numvecs, i; 1107 1108 if (!msix) 1109 goto msi_only; 1110 adapter->flags |= IGB_FLAG_HAS_MSIX; 1111 1112 /* Number of supported queues. */ 1113 adapter->num_rx_queues = adapter->rss_queues; 1114 if (adapter->vfs_allocated_count) 1115 adapter->num_tx_queues = 1; 1116 else 1117 adapter->num_tx_queues = adapter->rss_queues; 1118 1119 /* start with one vector for every Rx queue */ 1120 numvecs = adapter->num_rx_queues; 1121 1122 /* if Tx handler is separate add 1 for every Tx queue */ 1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1124 numvecs += adapter->num_tx_queues; 1125 1126 /* store the number of vectors reserved for queues */ 1127 adapter->num_q_vectors = numvecs; 1128 1129 /* add 1 vector for link status interrupts */ 1130 numvecs++; 1131 for (i = 0; i < numvecs; i++) 1132 adapter->msix_entries[i].entry = i; 1133 1134 err = pci_enable_msix_range(adapter->pdev, 1135 adapter->msix_entries, 1136 numvecs, 1137 numvecs); 1138 if (err > 0) 1139 return; 1140 1141 igb_reset_interrupt_capability(adapter); 1142 1143 /* If we can't do MSI-X, try MSI */ 1144msi_only: 1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1146#ifdef CONFIG_PCI_IOV 1147 /* disable SR-IOV for non MSI-X configurations */ 1148 if (adapter->vf_data) { 1149 struct e1000_hw *hw = &adapter->hw; 1150 /* disable iov and allow time for transactions to clear */ 1151 pci_disable_sriov(adapter->pdev); 1152 msleep(500); 1153 1154 kfree(adapter->vf_data); 1155 adapter->vf_data = NULL; 1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1157 wrfl(); 1158 msleep(100); 1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1160 } 1161#endif 1162 adapter->vfs_allocated_count = 0; 1163 adapter->rss_queues = 1; 1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1165 adapter->num_rx_queues = 1; 1166 adapter->num_tx_queues = 1; 1167 adapter->num_q_vectors = 1; 1168 if (!pci_enable_msi(adapter->pdev)) 1169 adapter->flags |= IGB_FLAG_HAS_MSI; 1170} 1171 1172static void igb_add_ring(struct igb_ring *ring, 1173 struct igb_ring_container *head) 1174{ 1175 head->ring = ring; 1176 head->count++; 1177} 1178 1179/** 1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1181 * @adapter: board private structure to initialize 1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1183 * @v_idx: index of vector in adapter struct 1184 * @txr_count: total number of Tx rings to allocate 1185 * @txr_idx: index of first Tx ring to allocate 1186 * @rxr_count: total number of Rx rings to allocate 1187 * @rxr_idx: index of first Rx ring to allocate 1188 * 1189 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1190 **/ 1191static int igb_alloc_q_vector(struct igb_adapter *adapter, 1192 int v_count, int v_idx, 1193 int txr_count, int txr_idx, 1194 int rxr_count, int rxr_idx) 1195{ 1196 struct igb_q_vector *q_vector; 1197 struct igb_ring *ring; 1198 int ring_count, size; 1199 1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1201 if (txr_count > 1 || rxr_count > 1) 1202 return -ENOMEM; 1203 1204 ring_count = txr_count + rxr_count; 1205 size = sizeof(struct igb_q_vector) + 1206 (sizeof(struct igb_ring) * ring_count); 1207 1208 /* allocate q_vector and rings */ 1209 q_vector = adapter->q_vector[v_idx]; 1210 if (!q_vector) 1211 q_vector = kzalloc(size, GFP_KERNEL); 1212 if (!q_vector) 1213 return -ENOMEM; 1214 1215 /* initialize NAPI */ 1216 netif_napi_add(adapter->netdev, &q_vector->napi, 1217 igb_poll, 64); 1218 1219 /* tie q_vector and adapter together */ 1220 adapter->q_vector[v_idx] = q_vector; 1221 q_vector->adapter = adapter; 1222 1223 /* initialize work limits */ 1224 q_vector->tx.work_limit = adapter->tx_work_limit; 1225 1226 /* initialize ITR configuration */ 1227 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); 1228 q_vector->itr_val = IGB_START_ITR; 1229 1230 /* initialize pointer to rings */ 1231 ring = q_vector->ring; 1232 1233 /* intialize ITR */ 1234 if (rxr_count) { 1235 /* rx or rx/tx vector */ 1236 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1237 q_vector->itr_val = adapter->rx_itr_setting; 1238 } else { 1239 /* tx only vector */ 1240 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1241 q_vector->itr_val = adapter->tx_itr_setting; 1242 } 1243 1244 if (txr_count) { 1245 /* assign generic ring traits */ 1246 ring->dev = &adapter->pdev->dev; 1247 ring->netdev = adapter->netdev; 1248 1249 /* configure backlink on ring */ 1250 ring->q_vector = q_vector; 1251 1252 /* update q_vector Tx values */ 1253 igb_add_ring(ring, &q_vector->tx); 1254 1255 /* For 82575, context index must be unique per ring. */ 1256 if (adapter->hw.mac.type == e1000_82575) 1257 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1258 1259 /* apply Tx specific ring traits */ 1260 ring->count = adapter->tx_ring_count; 1261 ring->queue_index = txr_idx; 1262 1263 u64_stats_init(&ring->tx_syncp); 1264 u64_stats_init(&ring->tx_syncp2); 1265 1266 /* assign ring to adapter */ 1267 adapter->tx_ring[txr_idx] = ring; 1268 1269 /* push pointer to next ring */ 1270 ring++; 1271 } 1272 1273 if (rxr_count) { 1274 /* assign generic ring traits */ 1275 ring->dev = &adapter->pdev->dev; 1276 ring->netdev = adapter->netdev; 1277 1278 /* configure backlink on ring */ 1279 ring->q_vector = q_vector; 1280 1281 /* update q_vector Rx values */ 1282 igb_add_ring(ring, &q_vector->rx); 1283 1284 /* set flag indicating ring supports SCTP checksum offload */ 1285 if (adapter->hw.mac.type >= e1000_82576) 1286 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1287 1288 /* 1289 * On i350, i354, i210, and i211, loopback VLAN packets 1290 * have the tag byte-swapped. 1291 */ 1292 if (adapter->hw.mac.type >= e1000_i350) 1293 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1294 1295 /* apply Rx specific ring traits */ 1296 ring->count = adapter->rx_ring_count; 1297 ring->queue_index = rxr_idx; 1298 1299 u64_stats_init(&ring->rx_syncp); 1300 1301 /* assign ring to adapter */ 1302 adapter->rx_ring[rxr_idx] = ring; 1303 } 1304 1305 return 0; 1306} 1307 1308 1309/** 1310 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1311 * @adapter: board private structure to initialize 1312 * 1313 * We allocate one q_vector per queue interrupt. If allocation fails we 1314 * return -ENOMEM. 1315 **/ 1316static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1317{ 1318 int q_vectors = adapter->num_q_vectors; 1319 int rxr_remaining = adapter->num_rx_queues; 1320 int txr_remaining = adapter->num_tx_queues; 1321 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1322 int err; 1323 1324 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1325 for (; rxr_remaining; v_idx++) { 1326 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1327 0, 0, 1, rxr_idx); 1328 1329 if (err) 1330 goto err_out; 1331 1332 /* update counts and index */ 1333 rxr_remaining--; 1334 rxr_idx++; 1335 } 1336 } 1337 1338 for (; v_idx < q_vectors; v_idx++) { 1339 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1340 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1341 1342 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1343 tqpv, txr_idx, rqpv, rxr_idx); 1344 1345 if (err) 1346 goto err_out; 1347 1348 /* update counts and index */ 1349 rxr_remaining -= rqpv; 1350 txr_remaining -= tqpv; 1351 rxr_idx++; 1352 txr_idx++; 1353 } 1354 1355 return 0; 1356 1357err_out: 1358 adapter->num_tx_queues = 0; 1359 adapter->num_rx_queues = 0; 1360 adapter->num_q_vectors = 0; 1361 1362 while (v_idx--) 1363 igb_free_q_vector(adapter, v_idx); 1364 1365 return -ENOMEM; 1366} 1367 1368/** 1369 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1370 * @adapter: board private structure to initialize 1371 * @msix: boolean value of MSIX capability 1372 * 1373 * This function initializes the interrupts and allocates all of the queues. 1374 **/ 1375static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1376{ 1377 struct pci_dev *pdev = adapter->pdev; 1378 int err; 1379 1380 igb_set_interrupt_capability(adapter, msix); 1381 1382 err = igb_alloc_q_vectors(adapter); 1383 if (err) { 1384 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1385 goto err_alloc_q_vectors; 1386 } 1387 1388 igb_cache_ring_register(adapter); 1389 1390 return 0; 1391 1392err_alloc_q_vectors: 1393 igb_reset_interrupt_capability(adapter); 1394 return err; 1395} 1396 1397/** 1398 * igb_request_irq - initialize interrupts 1399 * @adapter: board private structure to initialize 1400 * 1401 * Attempts to configure interrupts using the best available 1402 * capabilities of the hardware and kernel. 1403 **/ 1404static int igb_request_irq(struct igb_adapter *adapter) 1405{ 1406 struct net_device *netdev = adapter->netdev; 1407 struct pci_dev *pdev = adapter->pdev; 1408 int err = 0; 1409 1410 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1411 err = igb_request_msix(adapter); 1412 if (!err) 1413 goto request_done; 1414 /* fall back to MSI */ 1415 igb_free_all_tx_resources(adapter); 1416 igb_free_all_rx_resources(adapter); 1417 1418 igb_clear_interrupt_scheme(adapter); 1419 err = igb_init_interrupt_scheme(adapter, false); 1420 if (err) 1421 goto request_done; 1422 1423 igb_setup_all_tx_resources(adapter); 1424 igb_setup_all_rx_resources(adapter); 1425 igb_configure(adapter); 1426 } 1427 1428 igb_assign_vector(adapter->q_vector[0], 0); 1429 1430 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1431 err = request_irq(pdev->irq, igb_intr_msi, 0, 1432 netdev->name, adapter); 1433 if (!err) 1434 goto request_done; 1435 1436 /* fall back to legacy interrupts */ 1437 igb_reset_interrupt_capability(adapter); 1438 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1439 } 1440 1441 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1442 netdev->name, adapter); 1443 1444 if (err) 1445 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1446 err); 1447 1448request_done: 1449 return err; 1450} 1451 1452static void igb_free_irq(struct igb_adapter *adapter) 1453{ 1454 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1455 int vector = 0, i; 1456 1457 free_irq(adapter->msix_entries[vector++].vector, adapter); 1458 1459 for (i = 0; i < adapter->num_q_vectors; i++) 1460 free_irq(adapter->msix_entries[vector++].vector, 1461 adapter->q_vector[i]); 1462 } else { 1463 free_irq(adapter->pdev->irq, adapter); 1464 } 1465} 1466 1467/** 1468 * igb_irq_disable - Mask off interrupt generation on the NIC 1469 * @adapter: board private structure 1470 **/ 1471static void igb_irq_disable(struct igb_adapter *adapter) 1472{ 1473 struct e1000_hw *hw = &adapter->hw; 1474 1475 /* we need to be careful when disabling interrupts. The VFs are also 1476 * mapped into these registers and so clearing the bits can cause 1477 * issues on the VF drivers so we only need to clear what we set 1478 */ 1479 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1480 u32 regval = rd32(E1000_EIAM); 1481 1482 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1483 wr32(E1000_EIMC, adapter->eims_enable_mask); 1484 regval = rd32(E1000_EIAC); 1485 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1486 } 1487 1488 wr32(E1000_IAM, 0); 1489 wr32(E1000_IMC, ~0); 1490 wrfl(); 1491 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1492 int i; 1493 1494 for (i = 0; i < adapter->num_q_vectors; i++) 1495 synchronize_irq(adapter->msix_entries[i].vector); 1496 } else { 1497 synchronize_irq(adapter->pdev->irq); 1498 } 1499} 1500 1501/** 1502 * igb_irq_enable - Enable default interrupt generation settings 1503 * @adapter: board private structure 1504 **/ 1505static void igb_irq_enable(struct igb_adapter *adapter) 1506{ 1507 struct e1000_hw *hw = &adapter->hw; 1508 1509 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1510 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1511 u32 regval = rd32(E1000_EIAC); 1512 1513 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1514 regval = rd32(E1000_EIAM); 1515 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1516 wr32(E1000_EIMS, adapter->eims_enable_mask); 1517 if (adapter->vfs_allocated_count) { 1518 wr32(E1000_MBVFIMR, 0xFF); 1519 ims |= E1000_IMS_VMMB; 1520 } 1521 wr32(E1000_IMS, ims); 1522 } else { 1523 wr32(E1000_IMS, IMS_ENABLE_MASK | 1524 E1000_IMS_DRSTA); 1525 wr32(E1000_IAM, IMS_ENABLE_MASK | 1526 E1000_IMS_DRSTA); 1527 } 1528} 1529 1530static void igb_update_mng_vlan(struct igb_adapter *adapter) 1531{ 1532 struct e1000_hw *hw = &adapter->hw; 1533 u16 vid = adapter->hw.mng_cookie.vlan_id; 1534 u16 old_vid = adapter->mng_vlan_id; 1535 1536 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1537 /* add VID to filter table */ 1538 igb_vfta_set(hw, vid, true); 1539 adapter->mng_vlan_id = vid; 1540 } else { 1541 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1542 } 1543 1544 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1545 (vid != old_vid) && 1546 !test_bit(old_vid, adapter->active_vlans)) { 1547 /* remove VID from filter table */ 1548 igb_vfta_set(hw, old_vid, false); 1549 } 1550} 1551 1552/** 1553 * igb_release_hw_control - release control of the h/w to f/w 1554 * @adapter: address of board private structure 1555 * 1556 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1557 * For ASF and Pass Through versions of f/w this means that the 1558 * driver is no longer loaded. 1559 **/ 1560static void igb_release_hw_control(struct igb_adapter *adapter) 1561{ 1562 struct e1000_hw *hw = &adapter->hw; 1563 u32 ctrl_ext; 1564 1565 /* Let firmware take over control of h/w */ 1566 ctrl_ext = rd32(E1000_CTRL_EXT); 1567 wr32(E1000_CTRL_EXT, 1568 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1569} 1570 1571/** 1572 * igb_get_hw_control - get control of the h/w from f/w 1573 * @adapter: address of board private structure 1574 * 1575 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1576 * For ASF and Pass Through versions of f/w this means that 1577 * the driver is loaded. 1578 **/ 1579static void igb_get_hw_control(struct igb_adapter *adapter) 1580{ 1581 struct e1000_hw *hw = &adapter->hw; 1582 u32 ctrl_ext; 1583 1584 /* Let firmware know the driver has taken over */ 1585 ctrl_ext = rd32(E1000_CTRL_EXT); 1586 wr32(E1000_CTRL_EXT, 1587 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1588} 1589 1590/** 1591 * igb_configure - configure the hardware for RX and TX 1592 * @adapter: private board structure 1593 **/ 1594static void igb_configure(struct igb_adapter *adapter) 1595{ 1596 struct net_device *netdev = adapter->netdev; 1597 int i; 1598 1599 igb_get_hw_control(adapter); 1600 igb_set_rx_mode(netdev); 1601 1602 igb_restore_vlan(adapter); 1603 1604 igb_setup_tctl(adapter); 1605 igb_setup_mrqc(adapter); 1606 igb_setup_rctl(adapter); 1607 1608 igb_configure_tx(adapter); 1609 igb_configure_rx(adapter); 1610 1611 igb_rx_fifo_flush_82575(&adapter->hw); 1612 1613 /* call igb_desc_unused which always leaves 1614 * at least 1 descriptor unused to make sure 1615 * next_to_use != next_to_clean 1616 */ 1617 for (i = 0; i < adapter->num_rx_queues; i++) { 1618 struct igb_ring *ring = adapter->rx_ring[i]; 1619 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1620 } 1621} 1622 1623/** 1624 * igb_power_up_link - Power up the phy/serdes link 1625 * @adapter: address of board private structure 1626 **/ 1627void igb_power_up_link(struct igb_adapter *adapter) 1628{ 1629 igb_reset_phy(&adapter->hw); 1630 1631 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1632 igb_power_up_phy_copper(&adapter->hw); 1633 else 1634 igb_power_up_serdes_link_82575(&adapter->hw); 1635} 1636 1637/** 1638 * igb_power_down_link - Power down the phy/serdes link 1639 * @adapter: address of board private structure 1640 */ 1641static void igb_power_down_link(struct igb_adapter *adapter) 1642{ 1643 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1644 igb_power_down_phy_copper_82575(&adapter->hw); 1645 else 1646 igb_shutdown_serdes_link_82575(&adapter->hw); 1647} 1648 1649/** 1650 * Detect and switch function for Media Auto Sense 1651 * @adapter: address of the board private structure 1652 **/ 1653static void igb_check_swap_media(struct igb_adapter *adapter) 1654{ 1655 struct e1000_hw *hw = &adapter->hw; 1656 u32 ctrl_ext, connsw; 1657 bool swap_now = false; 1658 1659 ctrl_ext = rd32(E1000_CTRL_EXT); 1660 connsw = rd32(E1000_CONNSW); 1661 1662 /* need to live swap if current media is copper and we have fiber/serdes 1663 * to go to. 1664 */ 1665 1666 if ((hw->phy.media_type == e1000_media_type_copper) && 1667 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1668 swap_now = true; 1669 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1670 /* copper signal takes time to appear */ 1671 if (adapter->copper_tries < 4) { 1672 adapter->copper_tries++; 1673 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1674 wr32(E1000_CONNSW, connsw); 1675 return; 1676 } else { 1677 adapter->copper_tries = 0; 1678 if ((connsw & E1000_CONNSW_PHYSD) && 1679 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1680 swap_now = true; 1681 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1682 wr32(E1000_CONNSW, connsw); 1683 } 1684 } 1685 } 1686 1687 if (!swap_now) 1688 return; 1689 1690 switch (hw->phy.media_type) { 1691 case e1000_media_type_copper: 1692 netdev_info(adapter->netdev, 1693 "MAS: changing media to fiber/serdes\n"); 1694 ctrl_ext |= 1695 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1696 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1697 adapter->copper_tries = 0; 1698 break; 1699 case e1000_media_type_internal_serdes: 1700 case e1000_media_type_fiber: 1701 netdev_info(adapter->netdev, 1702 "MAS: changing media to copper\n"); 1703 ctrl_ext &= 1704 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1705 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1706 break; 1707 default: 1708 /* shouldn't get here during regular operation */ 1709 netdev_err(adapter->netdev, 1710 "AMS: Invalid media type found, returning\n"); 1711 break; 1712 } 1713 wr32(E1000_CTRL_EXT, ctrl_ext); 1714} 1715 1716/** 1717 * igb_up - Open the interface and prepare it to handle traffic 1718 * @adapter: board private structure 1719 **/ 1720int igb_up(struct igb_adapter *adapter) 1721{ 1722 struct e1000_hw *hw = &adapter->hw; 1723 int i; 1724 1725 /* hardware has been reset, we need to reload some things */ 1726 igb_configure(adapter); 1727 1728 clear_bit(__IGB_DOWN, &adapter->state); 1729 1730 for (i = 0; i < adapter->num_q_vectors; i++) 1731 napi_enable(&(adapter->q_vector[i]->napi)); 1732 1733 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1734 igb_configure_msix(adapter); 1735 else 1736 igb_assign_vector(adapter->q_vector[0], 0); 1737 1738 /* Clear any pending interrupts. */ 1739 rd32(E1000_ICR); 1740 igb_irq_enable(adapter); 1741 1742 /* notify VFs that reset has been completed */ 1743 if (adapter->vfs_allocated_count) { 1744 u32 reg_data = rd32(E1000_CTRL_EXT); 1745 1746 reg_data |= E1000_CTRL_EXT_PFRSTD; 1747 wr32(E1000_CTRL_EXT, reg_data); 1748 } 1749 1750 netif_tx_start_all_queues(adapter->netdev); 1751 1752 /* start the watchdog. */ 1753 hw->mac.get_link_status = 1; 1754 schedule_work(&adapter->watchdog_task); 1755 1756 if ((adapter->flags & IGB_FLAG_EEE) && 1757 (!hw->dev_spec._82575.eee_disable)) 1758 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1759 1760 return 0; 1761} 1762 1763void igb_down(struct igb_adapter *adapter) 1764{ 1765 struct net_device *netdev = adapter->netdev; 1766 struct e1000_hw *hw = &adapter->hw; 1767 u32 tctl, rctl; 1768 int i; 1769 1770 /* signal that we're down so the interrupt handler does not 1771 * reschedule our watchdog timer 1772 */ 1773 set_bit(__IGB_DOWN, &adapter->state); 1774 1775 /* disable receives in the hardware */ 1776 rctl = rd32(E1000_RCTL); 1777 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1778 /* flush and sleep below */ 1779 1780 netif_tx_stop_all_queues(netdev); 1781 1782 /* disable transmits in the hardware */ 1783 tctl = rd32(E1000_TCTL); 1784 tctl &= ~E1000_TCTL_EN; 1785 wr32(E1000_TCTL, tctl); 1786 /* flush both disables and wait for them to finish */ 1787 wrfl(); 1788 msleep(10); 1789 1790 igb_irq_disable(adapter); 1791 1792 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1793 1794 for (i = 0; i < adapter->num_q_vectors; i++) { 1795 napi_synchronize(&(adapter->q_vector[i]->napi)); 1796 napi_disable(&(adapter->q_vector[i]->napi)); 1797 } 1798 1799 1800 del_timer_sync(&adapter->watchdog_timer); 1801 del_timer_sync(&adapter->phy_info_timer); 1802 1803 netif_carrier_off(netdev); 1804 1805 /* record the stats before reset*/ 1806 spin_lock(&adapter->stats64_lock); 1807 igb_update_stats(adapter, &adapter->stats64); 1808 spin_unlock(&adapter->stats64_lock); 1809 1810 adapter->link_speed = 0; 1811 adapter->link_duplex = 0; 1812 1813 if (!pci_channel_offline(adapter->pdev)) 1814 igb_reset(adapter); 1815 igb_clean_all_tx_rings(adapter); 1816 igb_clean_all_rx_rings(adapter); 1817#ifdef CONFIG_IGB_DCA 1818 1819 /* since we reset the hardware DCA settings were cleared */ 1820 igb_setup_dca(adapter); 1821#endif 1822} 1823 1824void igb_reinit_locked(struct igb_adapter *adapter) 1825{ 1826 WARN_ON(in_interrupt()); 1827 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1828 msleep(1); 1829 igb_down(adapter); 1830 igb_up(adapter); 1831 clear_bit(__IGB_RESETTING, &adapter->state); 1832} 1833 1834/** igb_enable_mas - Media Autosense re-enable after swap 1835 * 1836 * @adapter: adapter struct 1837 **/ 1838static s32 igb_enable_mas(struct igb_adapter *adapter) 1839{ 1840 struct e1000_hw *hw = &adapter->hw; 1841 u32 connsw; 1842 s32 ret_val = 0; 1843 1844 connsw = rd32(E1000_CONNSW); 1845 if (!(hw->phy.media_type == e1000_media_type_copper)) 1846 return ret_val; 1847 1848 /* configure for SerDes media detect */ 1849 if (!(connsw & E1000_CONNSW_SERDESD)) { 1850 connsw |= E1000_CONNSW_ENRGSRC; 1851 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1852 wr32(E1000_CONNSW, connsw); 1853 wrfl(); 1854 } else if (connsw & E1000_CONNSW_SERDESD) { 1855 /* already SerDes, no need to enable anything */ 1856 return ret_val; 1857 } else { 1858 netdev_info(adapter->netdev, 1859 "MAS: Unable to configure feature, disabling..\n"); 1860 adapter->flags &= ~IGB_FLAG_MAS_ENABLE; 1861 } 1862 return ret_val; 1863} 1864 1865void igb_reset(struct igb_adapter *adapter) 1866{ 1867 struct pci_dev *pdev = adapter->pdev; 1868 struct e1000_hw *hw = &adapter->hw; 1869 struct e1000_mac_info *mac = &hw->mac; 1870 struct e1000_fc_info *fc = &hw->fc; 1871 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; 1872 1873 /* Repartition Pba for greater than 9k mtu 1874 * To take effect CTRL.RST is required. 1875 */ 1876 switch (mac->type) { 1877 case e1000_i350: 1878 case e1000_i354: 1879 case e1000_82580: 1880 pba = rd32(E1000_RXPBS); 1881 pba = igb_rxpbs_adjust_82580(pba); 1882 break; 1883 case e1000_82576: 1884 pba = rd32(E1000_RXPBS); 1885 pba &= E1000_RXPBS_SIZE_MASK_82576; 1886 break; 1887 case e1000_82575: 1888 case e1000_i210: 1889 case e1000_i211: 1890 default: 1891 pba = E1000_PBA_34K; 1892 break; 1893 } 1894 1895 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1896 (mac->type < e1000_82576)) { 1897 /* adjust PBA for jumbo frames */ 1898 wr32(E1000_PBA, pba); 1899 1900 /* To maintain wire speed transmits, the Tx FIFO should be 1901 * large enough to accommodate two full transmit packets, 1902 * rounded up to the next 1KB and expressed in KB. Likewise, 1903 * the Rx FIFO should be large enough to accommodate at least 1904 * one full receive packet and is similarly rounded up and 1905 * expressed in KB. 1906 */ 1907 pba = rd32(E1000_PBA); 1908 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1909 tx_space = pba >> 16; 1910 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1911 pba &= 0xffff; 1912 /* the Tx fifo also stores 16 bytes of information about the Tx 1913 * but don't include ethernet FCS because hardware appends it 1914 */ 1915 min_tx_space = (adapter->max_frame_size + 1916 sizeof(union e1000_adv_tx_desc) - 1917 ETH_FCS_LEN) * 2; 1918 min_tx_space = ALIGN(min_tx_space, 1024); 1919 min_tx_space >>= 10; 1920 /* software strips receive CRC, so leave room for it */ 1921 min_rx_space = adapter->max_frame_size; 1922 min_rx_space = ALIGN(min_rx_space, 1024); 1923 min_rx_space >>= 10; 1924 1925 /* If current Tx allocation is less than the min Tx FIFO size, 1926 * and the min Tx FIFO size is less than the current Rx FIFO 1927 * allocation, take space away from current Rx allocation 1928 */ 1929 if (tx_space < min_tx_space && 1930 ((min_tx_space - tx_space) < pba)) { 1931 pba = pba - (min_tx_space - tx_space); 1932 1933 /* if short on Rx space, Rx wins and must trump Tx 1934 * adjustment 1935 */ 1936 if (pba < min_rx_space) 1937 pba = min_rx_space; 1938 } 1939 wr32(E1000_PBA, pba); 1940 } 1941 1942 /* flow control settings */ 1943 /* The high water mark must be low enough to fit one full frame 1944 * (or the size used for early receive) above it in the Rx FIFO. 1945 * Set it to the lower of: 1946 * - 90% of the Rx FIFO size, or 1947 * - the full Rx FIFO size minus one full frame 1948 */ 1949 hwm = min(((pba << 10) * 9 / 10), 1950 ((pba << 10) - 2 * adapter->max_frame_size)); 1951 1952 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1953 fc->low_water = fc->high_water - 16; 1954 fc->pause_time = 0xFFFF; 1955 fc->send_xon = 1; 1956 fc->current_mode = fc->requested_mode; 1957 1958 /* disable receive for all VFs and wait one second */ 1959 if (adapter->vfs_allocated_count) { 1960 int i; 1961 1962 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1963 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1964 1965 /* ping all the active vfs to let them know we are going down */ 1966 igb_ping_all_vfs(adapter); 1967 1968 /* disable transmits and receives */ 1969 wr32(E1000_VFRE, 0); 1970 wr32(E1000_VFTE, 0); 1971 } 1972 1973 /* Allow time for pending master requests to run */ 1974 hw->mac.ops.reset_hw(hw); 1975 wr32(E1000_WUC, 0); 1976 1977 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1978 /* need to resetup here after media swap */ 1979 adapter->ei.get_invariants(hw); 1980 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1981 } 1982 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 1983 if (igb_enable_mas(adapter)) 1984 dev_err(&pdev->dev, 1985 "Error enabling Media Auto Sense\n"); 1986 } 1987 if (hw->mac.ops.init_hw(hw)) 1988 dev_err(&pdev->dev, "Hardware Error\n"); 1989 1990 /* Flow control settings reset on hardware reset, so guarantee flow 1991 * control is off when forcing speed. 1992 */ 1993 if (!hw->mac.autoneg) 1994 igb_force_mac_fc(hw); 1995 1996 igb_init_dmac(adapter, pba); 1997#ifdef CONFIG_IGB_HWMON 1998 /* Re-initialize the thermal sensor on i350 devices. */ 1999 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2000 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2001 /* If present, re-initialize the external thermal sensor 2002 * interface. 2003 */ 2004 if (adapter->ets) 2005 mac->ops.init_thermal_sensor_thresh(hw); 2006 } 2007 } 2008#endif 2009 /* Re-establish EEE setting */ 2010 if (hw->phy.media_type == e1000_media_type_copper) { 2011 switch (mac->type) { 2012 case e1000_i350: 2013 case e1000_i210: 2014 case e1000_i211: 2015 igb_set_eee_i350(hw); 2016 break; 2017 case e1000_i354: 2018 igb_set_eee_i354(hw); 2019 break; 2020 default: 2021 break; 2022 } 2023 } 2024 if (!netif_running(adapter->netdev)) 2025 igb_power_down_link(adapter); 2026 2027 igb_update_mng_vlan(adapter); 2028 2029 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2030 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2031 2032 /* Re-enable PTP, where applicable. */ 2033 igb_ptp_reset(adapter); 2034 2035 igb_get_phy_info(hw); 2036} 2037 2038static netdev_features_t igb_fix_features(struct net_device *netdev, 2039 netdev_features_t features) 2040{ 2041 /* Since there is no support for separate Rx/Tx vlan accel 2042 * enable/disable make sure Tx flag is always in same state as Rx. 2043 */ 2044 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2045 features |= NETIF_F_HW_VLAN_CTAG_TX; 2046 else 2047 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2048 2049 return features; 2050} 2051 2052static int igb_set_features(struct net_device *netdev, 2053 netdev_features_t features) 2054{ 2055 netdev_features_t changed = netdev->features ^ features; 2056 struct igb_adapter *adapter = netdev_priv(netdev); 2057 2058 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2059 igb_vlan_mode(netdev, features); 2060 2061 if (!(changed & NETIF_F_RXALL)) 2062 return 0; 2063 2064 netdev->features = features; 2065 2066 if (netif_running(netdev)) 2067 igb_reinit_locked(adapter); 2068 else 2069 igb_reset(adapter); 2070 2071 return 0; 2072} 2073 2074static const struct net_device_ops igb_netdev_ops = { 2075 .ndo_open = igb_open, 2076 .ndo_stop = igb_close, 2077 .ndo_start_xmit = igb_xmit_frame, 2078 .ndo_get_stats64 = igb_get_stats64, 2079 .ndo_set_rx_mode = igb_set_rx_mode, 2080 .ndo_set_mac_address = igb_set_mac, 2081 .ndo_change_mtu = igb_change_mtu, 2082 .ndo_do_ioctl = igb_ioctl, 2083 .ndo_tx_timeout = igb_tx_timeout, 2084 .ndo_validate_addr = eth_validate_addr, 2085 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2086 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2087 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2088 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2089 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, 2090 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2091 .ndo_get_vf_config = igb_ndo_get_vf_config, 2092#ifdef CONFIG_NET_POLL_CONTROLLER 2093 .ndo_poll_controller = igb_netpoll, 2094#endif 2095 .ndo_fix_features = igb_fix_features, 2096 .ndo_set_features = igb_set_features, 2097}; 2098 2099/** 2100 * igb_set_fw_version - Configure version string for ethtool 2101 * @adapter: adapter struct 2102 **/ 2103void igb_set_fw_version(struct igb_adapter *adapter) 2104{ 2105 struct e1000_hw *hw = &adapter->hw; 2106 struct e1000_fw_version fw; 2107 2108 igb_get_fw_version(hw, &fw); 2109 2110 switch (hw->mac.type) { 2111 case e1000_i210: 2112 case e1000_i211: 2113 if (!(igb_get_flash_presence_i210(hw))) { 2114 snprintf(adapter->fw_version, 2115 sizeof(adapter->fw_version), 2116 "%2d.%2d-%d", 2117 fw.invm_major, fw.invm_minor, 2118 fw.invm_img_type); 2119 break; 2120 } 2121 /* fall through */ 2122 default: 2123 /* if option is rom valid, display its version too */ 2124 if (fw.or_valid) { 2125 snprintf(adapter->fw_version, 2126 sizeof(adapter->fw_version), 2127 "%d.%d, 0x%08x, %d.%d.%d", 2128 fw.eep_major, fw.eep_minor, fw.etrack_id, 2129 fw.or_major, fw.or_build, fw.or_patch); 2130 /* no option rom */ 2131 } else if (fw.etrack_id != 0X0000) { 2132 snprintf(adapter->fw_version, 2133 sizeof(adapter->fw_version), 2134 "%d.%d, 0x%08x", 2135 fw.eep_major, fw.eep_minor, fw.etrack_id); 2136 } else { 2137 snprintf(adapter->fw_version, 2138 sizeof(adapter->fw_version), 2139 "%d.%d.%d", 2140 fw.eep_major, fw.eep_minor, fw.eep_build); 2141 } 2142 break; 2143 } 2144 return; 2145} 2146 2147/** 2148 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2149 * 2150 * @adapter: adapter struct 2151 **/ 2152static void igb_init_mas(struct igb_adapter *adapter) 2153{ 2154 struct e1000_hw *hw = &adapter->hw; 2155 u16 eeprom_data; 2156 2157 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2158 switch (hw->bus.func) { 2159 case E1000_FUNC_0: 2160 if (eeprom_data & IGB_MAS_ENABLE_0) { 2161 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2162 netdev_info(adapter->netdev, 2163 "MAS: Enabling Media Autosense for port %d\n", 2164 hw->bus.func); 2165 } 2166 break; 2167 case E1000_FUNC_1: 2168 if (eeprom_data & IGB_MAS_ENABLE_1) { 2169 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2170 netdev_info(adapter->netdev, 2171 "MAS: Enabling Media Autosense for port %d\n", 2172 hw->bus.func); 2173 } 2174 break; 2175 case E1000_FUNC_2: 2176 if (eeprom_data & IGB_MAS_ENABLE_2) { 2177 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2178 netdev_info(adapter->netdev, 2179 "MAS: Enabling Media Autosense for port %d\n", 2180 hw->bus.func); 2181 } 2182 break; 2183 case E1000_FUNC_3: 2184 if (eeprom_data & IGB_MAS_ENABLE_3) { 2185 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2186 netdev_info(adapter->netdev, 2187 "MAS: Enabling Media Autosense for port %d\n", 2188 hw->bus.func); 2189 } 2190 break; 2191 default: 2192 /* Shouldn't get here */ 2193 netdev_err(adapter->netdev, 2194 "MAS: Invalid port configuration, returning\n"); 2195 break; 2196 } 2197} 2198 2199/** 2200 * igb_init_i2c - Init I2C interface 2201 * @adapter: pointer to adapter structure 2202 **/ 2203static s32 igb_init_i2c(struct igb_adapter *adapter) 2204{ 2205 s32 status = E1000_SUCCESS; 2206 2207 /* I2C interface supported on i350 devices */ 2208 if (adapter->hw.mac.type != e1000_i350) 2209 return E1000_SUCCESS; 2210 2211 /* Initialize the i2c bus which is controlled by the registers. 2212 * This bus will use the i2c_algo_bit structue that implements 2213 * the protocol through toggling of the 4 bits in the register. 2214 */ 2215 adapter->i2c_adap.owner = THIS_MODULE; 2216 adapter->i2c_algo = igb_i2c_algo; 2217 adapter->i2c_algo.data = adapter; 2218 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2219 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2220 strlcpy(adapter->i2c_adap.name, "igb BB", 2221 sizeof(adapter->i2c_adap.name)); 2222 status = i2c_bit_add_bus(&adapter->i2c_adap); 2223 return status; 2224} 2225 2226/** 2227 * igb_probe - Device Initialization Routine 2228 * @pdev: PCI device information struct 2229 * @ent: entry in igb_pci_tbl 2230 * 2231 * Returns 0 on success, negative on failure 2232 * 2233 * igb_probe initializes an adapter identified by a pci_dev structure. 2234 * The OS initialization, configuring of the adapter private structure, 2235 * and a hardware reset occur. 2236 **/ 2237static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2238{ 2239 struct net_device *netdev; 2240 struct igb_adapter *adapter; 2241 struct e1000_hw *hw; 2242 u16 eeprom_data = 0; 2243 s32 ret_val; 2244 static int global_quad_port_a; /* global quad port a indication */ 2245 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2246 int err, pci_using_dac; 2247 u8 part_str[E1000_PBANUM_LENGTH]; 2248 2249 /* Catch broken hardware that put the wrong VF device ID in 2250 * the PCIe SR-IOV capability. 2251 */ 2252 if (pdev->is_virtfn) { 2253 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2254 pci_name(pdev), pdev->vendor, pdev->device); 2255 return -EINVAL; 2256 } 2257 2258 err = pci_enable_device_mem(pdev); 2259 if (err) 2260 return err; 2261 2262 pci_using_dac = 0; 2263 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2264 if (!err) { 2265 pci_using_dac = 1; 2266 } else { 2267 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2268 if (err) { 2269 dev_err(&pdev->dev, 2270 "No usable DMA configuration, aborting\n"); 2271 goto err_dma; 2272 } 2273 } 2274 2275 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 2276 IORESOURCE_MEM), 2277 igb_driver_name); 2278 if (err) 2279 goto err_pci_reg; 2280 2281 pci_enable_pcie_error_reporting(pdev); 2282 2283 pci_set_master(pdev); 2284 pci_save_state(pdev); 2285 2286 err = -ENOMEM; 2287 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2288 IGB_MAX_TX_QUEUES); 2289 if (!netdev) 2290 goto err_alloc_etherdev; 2291 2292 SET_NETDEV_DEV(netdev, &pdev->dev); 2293 2294 pci_set_drvdata(pdev, netdev); 2295 adapter = netdev_priv(netdev); 2296 adapter->netdev = netdev; 2297 adapter->pdev = pdev; 2298 hw = &adapter->hw; 2299 hw->back = adapter; 2300 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2301 2302 err = -EIO; 2303 hw->hw_addr = pci_iomap(pdev, 0, 0); 2304 if (!hw->hw_addr) 2305 goto err_ioremap; 2306 2307 netdev->netdev_ops = &igb_netdev_ops; 2308 igb_set_ethtool_ops(netdev); 2309 netdev->watchdog_timeo = 5 * HZ; 2310 2311 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2312 2313 netdev->mem_start = pci_resource_start(pdev, 0); 2314 netdev->mem_end = pci_resource_end(pdev, 0); 2315 2316 /* PCI config space info */ 2317 hw->vendor_id = pdev->vendor; 2318 hw->device_id = pdev->device; 2319 hw->revision_id = pdev->revision; 2320 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2321 hw->subsystem_device_id = pdev->subsystem_device; 2322 2323 /* Copy the default MAC, PHY and NVM function pointers */ 2324 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2325 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2326 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2327 /* Initialize skew-specific constants */ 2328 err = ei->get_invariants(hw); 2329 if (err) 2330 goto err_sw_init; 2331 2332 /* setup the private structure */ 2333 err = igb_sw_init(adapter); 2334 if (err) 2335 goto err_sw_init; 2336 2337 igb_get_bus_info_pcie(hw); 2338 2339 hw->phy.autoneg_wait_to_complete = false; 2340 2341 /* Copper options */ 2342 if (hw->phy.media_type == e1000_media_type_copper) { 2343 hw->phy.mdix = AUTO_ALL_MODES; 2344 hw->phy.disable_polarity_correction = false; 2345 hw->phy.ms_type = e1000_ms_hw_default; 2346 } 2347 2348 if (igb_check_reset_block(hw)) 2349 dev_info(&pdev->dev, 2350 "PHY reset is blocked due to SOL/IDER session.\n"); 2351 2352 /* features is initialized to 0 in allocation, it might have bits 2353 * set by igb_sw_init so we should use an or instead of an 2354 * assignment. 2355 */ 2356 netdev->features |= NETIF_F_SG | 2357 NETIF_F_IP_CSUM | 2358 NETIF_F_IPV6_CSUM | 2359 NETIF_F_TSO | 2360 NETIF_F_TSO6 | 2361 NETIF_F_RXHASH | 2362 NETIF_F_RXCSUM | 2363 NETIF_F_HW_VLAN_CTAG_RX | 2364 NETIF_F_HW_VLAN_CTAG_TX; 2365 2366 /* copy netdev features into list of user selectable features */ 2367 netdev->hw_features |= netdev->features; 2368 netdev->hw_features |= NETIF_F_RXALL; 2369 2370 /* set this bit last since it cannot be part of hw_features */ 2371 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2372 2373 netdev->vlan_features |= NETIF_F_TSO | 2374 NETIF_F_TSO6 | 2375 NETIF_F_IP_CSUM | 2376 NETIF_F_IPV6_CSUM | 2377 NETIF_F_SG; 2378 2379 netdev->priv_flags |= IFF_SUPP_NOFCS; 2380 2381 if (pci_using_dac) { 2382 netdev->features |= NETIF_F_HIGHDMA; 2383 netdev->vlan_features |= NETIF_F_HIGHDMA; 2384 } 2385 2386 if (hw->mac.type >= e1000_82576) { 2387 netdev->hw_features |= NETIF_F_SCTP_CSUM; 2388 netdev->features |= NETIF_F_SCTP_CSUM; 2389 } 2390 2391 netdev->priv_flags |= IFF_UNICAST_FLT; 2392 2393 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2394 2395 /* before reading the NVM, reset the controller to put the device in a 2396 * known good starting state 2397 */ 2398 hw->mac.ops.reset_hw(hw); 2399 2400 /* make sure the NVM is good , i211/i210 parts can have special NVM 2401 * that doesn't contain a checksum 2402 */ 2403 switch (hw->mac.type) { 2404 case e1000_i210: 2405 case e1000_i211: 2406 if (igb_get_flash_presence_i210(hw)) { 2407 if (hw->nvm.ops.validate(hw) < 0) { 2408 dev_err(&pdev->dev, 2409 "The NVM Checksum Is Not Valid\n"); 2410 err = -EIO; 2411 goto err_eeprom; 2412 } 2413 } 2414 break; 2415 default: 2416 if (hw->nvm.ops.validate(hw) < 0) { 2417 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2418 err = -EIO; 2419 goto err_eeprom; 2420 } 2421 break; 2422 } 2423 2424 /* copy the MAC address out of the NVM */ 2425 if (hw->mac.ops.read_mac_addr(hw)) 2426 dev_err(&pdev->dev, "NVM Read Error\n"); 2427 2428 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2429 2430 if (!is_valid_ether_addr(netdev->dev_addr)) { 2431 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2432 err = -EIO; 2433 goto err_eeprom; 2434 } 2435 2436 /* get firmware version for ethtool -i */ 2437 igb_set_fw_version(adapter); 2438 2439 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2440 (unsigned long) adapter); 2441 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2442 (unsigned long) adapter); 2443 2444 INIT_WORK(&adapter->reset_task, igb_reset_task); 2445 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2446 2447 /* Initialize link properties that are user-changeable */ 2448 adapter->fc_autoneg = true; 2449 hw->mac.autoneg = true; 2450 hw->phy.autoneg_advertised = 0x2f; 2451 2452 hw->fc.requested_mode = e1000_fc_default; 2453 hw->fc.current_mode = e1000_fc_default; 2454 2455 igb_validate_mdi_setting(hw); 2456 2457 /* By default, support wake on port A */ 2458 if (hw->bus.func == 0) 2459 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2460 2461 /* Check the NVM for wake support on non-port A ports */ 2462 if (hw->mac.type >= e1000_82580) 2463 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2464 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2465 &eeprom_data); 2466 else if (hw->bus.func == 1) 2467 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2468 2469 if (eeprom_data & IGB_EEPROM_APME) 2470 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2471 2472 /* now that we have the eeprom settings, apply the special cases where 2473 * the eeprom may be wrong or the board simply won't support wake on 2474 * lan on a particular port 2475 */ 2476 switch (pdev->device) { 2477 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2478 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2479 break; 2480 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2481 case E1000_DEV_ID_82576_FIBER: 2482 case E1000_DEV_ID_82576_SERDES: 2483 /* Wake events only supported on port A for dual fiber 2484 * regardless of eeprom setting 2485 */ 2486 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2487 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2488 break; 2489 case E1000_DEV_ID_82576_QUAD_COPPER: 2490 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2491 /* if quad port adapter, disable WoL on all but port A */ 2492 if (global_quad_port_a != 0) 2493 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2494 else 2495 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2496 /* Reset for multiple quad port adapters */ 2497 if (++global_quad_port_a == 4) 2498 global_quad_port_a = 0; 2499 break; 2500 default: 2501 /* If the device can't wake, don't set software support */ 2502 if (!device_can_wakeup(&adapter->pdev->dev)) 2503 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2504 } 2505 2506 /* initialize the wol settings based on the eeprom settings */ 2507 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2508 adapter->wol |= E1000_WUFC_MAG; 2509 2510 /* Some vendors want WoL disabled by default, but still supported */ 2511 if ((hw->mac.type == e1000_i350) && 2512 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2513 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2514 adapter->wol = 0; 2515 } 2516 2517 device_set_wakeup_enable(&adapter->pdev->dev, 2518 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2519 2520 /* reset the hardware with the new settings */ 2521 igb_reset(adapter); 2522 2523 /* Init the I2C interface */ 2524 err = igb_init_i2c(adapter); 2525 if (err) { 2526 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2527 goto err_eeprom; 2528 } 2529 2530 /* let the f/w know that the h/w is now under the control of the 2531 * driver. */ 2532 igb_get_hw_control(adapter); 2533 2534 strcpy(netdev->name, "eth%d"); 2535 err = register_netdev(netdev); 2536 if (err) 2537 goto err_register; 2538 2539 /* carrier off reporting is important to ethtool even BEFORE open */ 2540 netif_carrier_off(netdev); 2541 2542#ifdef CONFIG_IGB_DCA 2543 if (dca_add_requester(&pdev->dev) == 0) { 2544 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2545 dev_info(&pdev->dev, "DCA enabled\n"); 2546 igb_setup_dca(adapter); 2547 } 2548 2549#endif 2550#ifdef CONFIG_IGB_HWMON 2551 /* Initialize the thermal sensor on i350 devices. */ 2552 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2553 u16 ets_word; 2554 2555 /* Read the NVM to determine if this i350 device supports an 2556 * external thermal sensor. 2557 */ 2558 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2559 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2560 adapter->ets = true; 2561 else 2562 adapter->ets = false; 2563 if (igb_sysfs_init(adapter)) 2564 dev_err(&pdev->dev, 2565 "failed to allocate sysfs resources\n"); 2566 } else { 2567 adapter->ets = false; 2568 } 2569#endif 2570 /* Check if Media Autosense is enabled */ 2571 adapter->ei = *ei; 2572 if (hw->dev_spec._82575.mas_capable) 2573 igb_init_mas(adapter); 2574 2575 /* do hw tstamp init after resetting */ 2576 igb_ptp_init(adapter); 2577 2578 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2579 /* print bus type/speed/width info, not applicable to i354 */ 2580 if (hw->mac.type != e1000_i354) { 2581 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2582 netdev->name, 2583 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2584 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2585 "unknown"), 2586 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2587 "Width x4" : 2588 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2589 "Width x2" : 2590 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2591 "Width x1" : "unknown"), netdev->dev_addr); 2592 } 2593 2594 if ((hw->mac.type >= e1000_i210 || 2595 igb_get_flash_presence_i210(hw))) { 2596 ret_val = igb_read_part_string(hw, part_str, 2597 E1000_PBANUM_LENGTH); 2598 } else { 2599 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2600 } 2601 2602 if (ret_val) 2603 strcpy(part_str, "Unknown"); 2604 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2605 dev_info(&pdev->dev, 2606 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2607 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2608 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2609 adapter->num_rx_queues, adapter->num_tx_queues); 2610 if (hw->phy.media_type == e1000_media_type_copper) { 2611 switch (hw->mac.type) { 2612 case e1000_i350: 2613 case e1000_i210: 2614 case e1000_i211: 2615 /* Enable EEE for internal copper PHY devices */ 2616 err = igb_set_eee_i350(hw); 2617 if ((!err) && 2618 (!hw->dev_spec._82575.eee_disable)) { 2619 adapter->eee_advert = 2620 MDIO_EEE_100TX | MDIO_EEE_1000T; 2621 adapter->flags |= IGB_FLAG_EEE; 2622 } 2623 break; 2624 case e1000_i354: 2625 if ((rd32(E1000_CTRL_EXT) & 2626 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2627 err = igb_set_eee_i354(hw); 2628 if ((!err) && 2629 (!hw->dev_spec._82575.eee_disable)) { 2630 adapter->eee_advert = 2631 MDIO_EEE_100TX | MDIO_EEE_1000T; 2632 adapter->flags |= IGB_FLAG_EEE; 2633 } 2634 } 2635 break; 2636 default: 2637 break; 2638 } 2639 } 2640 pm_runtime_put_noidle(&pdev->dev); 2641 return 0; 2642 2643err_register: 2644 igb_release_hw_control(adapter); 2645 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2646err_eeprom: 2647 if (!igb_check_reset_block(hw)) 2648 igb_reset_phy(hw); 2649 2650 if (hw->flash_address) 2651 iounmap(hw->flash_address); 2652err_sw_init: 2653 igb_clear_interrupt_scheme(adapter); 2654 pci_iounmap(pdev, hw->hw_addr); 2655err_ioremap: 2656 free_netdev(netdev); 2657err_alloc_etherdev: 2658 pci_release_selected_regions(pdev, 2659 pci_select_bars(pdev, IORESOURCE_MEM)); 2660err_pci_reg: 2661err_dma: 2662 pci_disable_device(pdev); 2663 return err; 2664} 2665 2666#ifdef CONFIG_PCI_IOV 2667static int igb_disable_sriov(struct pci_dev *pdev) 2668{ 2669 struct net_device *netdev = pci_get_drvdata(pdev); 2670 struct igb_adapter *adapter = netdev_priv(netdev); 2671 struct e1000_hw *hw = &adapter->hw; 2672 2673 /* reclaim resources allocated to VFs */ 2674 if (adapter->vf_data) { 2675 /* disable iov and allow time for transactions to clear */ 2676 if (pci_vfs_assigned(pdev)) { 2677 dev_warn(&pdev->dev, 2678 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2679 return -EPERM; 2680 } else { 2681 pci_disable_sriov(pdev); 2682 msleep(500); 2683 } 2684 2685 kfree(adapter->vf_data); 2686 adapter->vf_data = NULL; 2687 adapter->vfs_allocated_count = 0; 2688 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2689 wrfl(); 2690 msleep(100); 2691 dev_info(&pdev->dev, "IOV Disabled\n"); 2692 2693 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2694 adapter->flags |= IGB_FLAG_DMAC; 2695 } 2696 2697 return 0; 2698} 2699 2700static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2701{ 2702 struct net_device *netdev = pci_get_drvdata(pdev); 2703 struct igb_adapter *adapter = netdev_priv(netdev); 2704 int old_vfs = pci_num_vf(pdev); 2705 int err = 0; 2706 int i; 2707 2708 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2709 err = -EPERM; 2710 goto out; 2711 } 2712 if (!num_vfs) 2713 goto out; 2714 2715 if (old_vfs) { 2716 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2717 old_vfs, max_vfs); 2718 adapter->vfs_allocated_count = old_vfs; 2719 } else 2720 adapter->vfs_allocated_count = num_vfs; 2721 2722 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2723 sizeof(struct vf_data_storage), GFP_KERNEL); 2724 2725 /* if allocation failed then we do not support SR-IOV */ 2726 if (!adapter->vf_data) { 2727 adapter->vfs_allocated_count = 0; 2728 dev_err(&pdev->dev, 2729 "Unable to allocate memory for VF Data Storage\n"); 2730 err = -ENOMEM; 2731 goto out; 2732 } 2733 2734 /* only call pci_enable_sriov() if no VFs are allocated already */ 2735 if (!old_vfs) { 2736 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2737 if (err) 2738 goto err_out; 2739 } 2740 dev_info(&pdev->dev, "%d VFs allocated\n", 2741 adapter->vfs_allocated_count); 2742 for (i = 0; i < adapter->vfs_allocated_count; i++) 2743 igb_vf_configure(adapter, i); 2744 2745 /* DMA Coalescing is not supported in IOV mode. */ 2746 adapter->flags &= ~IGB_FLAG_DMAC; 2747 goto out; 2748 2749err_out: 2750 kfree(adapter->vf_data); 2751 adapter->vf_data = NULL; 2752 adapter->vfs_allocated_count = 0; 2753out: 2754 return err; 2755} 2756 2757#endif 2758/** 2759 * igb_remove_i2c - Cleanup I2C interface 2760 * @adapter: pointer to adapter structure 2761 **/ 2762static void igb_remove_i2c(struct igb_adapter *adapter) 2763{ 2764 /* free the adapter bus structure */ 2765 i2c_del_adapter(&adapter->i2c_adap); 2766} 2767 2768/** 2769 * igb_remove - Device Removal Routine 2770 * @pdev: PCI device information struct 2771 * 2772 * igb_remove is called by the PCI subsystem to alert the driver 2773 * that it should release a PCI device. The could be caused by a 2774 * Hot-Plug event, or because the driver is going to be removed from 2775 * memory. 2776 **/ 2777static void igb_remove(struct pci_dev *pdev) 2778{ 2779 struct net_device *netdev = pci_get_drvdata(pdev); 2780 struct igb_adapter *adapter = netdev_priv(netdev); 2781 struct e1000_hw *hw = &adapter->hw; 2782 2783 pm_runtime_get_noresume(&pdev->dev); 2784#ifdef CONFIG_IGB_HWMON 2785 igb_sysfs_exit(adapter); 2786#endif 2787 igb_remove_i2c(adapter); 2788 igb_ptp_stop(adapter); 2789 /* The watchdog timer may be rescheduled, so explicitly 2790 * disable watchdog from being rescheduled. 2791 */ 2792 set_bit(__IGB_DOWN, &adapter->state); 2793 del_timer_sync(&adapter->watchdog_timer); 2794 del_timer_sync(&adapter->phy_info_timer); 2795 2796 cancel_work_sync(&adapter->reset_task); 2797 cancel_work_sync(&adapter->watchdog_task); 2798 2799#ifdef CONFIG_IGB_DCA 2800 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2801 dev_info(&pdev->dev, "DCA disabled\n"); 2802 dca_remove_requester(&pdev->dev); 2803 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2804 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2805 } 2806#endif 2807 2808 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2809 * would have already happened in close and is redundant. 2810 */ 2811 igb_release_hw_control(adapter); 2812 2813 unregister_netdev(netdev); 2814 2815 igb_clear_interrupt_scheme(adapter); 2816 2817#ifdef CONFIG_PCI_IOV 2818 igb_disable_sriov(pdev); 2819#endif 2820 2821 pci_iounmap(pdev, hw->hw_addr); 2822 if (hw->flash_address) 2823 iounmap(hw->flash_address); 2824 pci_release_selected_regions(pdev, 2825 pci_select_bars(pdev, IORESOURCE_MEM)); 2826 2827 kfree(adapter->shadow_vfta); 2828 free_netdev(netdev); 2829 2830 pci_disable_pcie_error_reporting(pdev); 2831 2832 pci_disable_device(pdev); 2833} 2834 2835/** 2836 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2837 * @adapter: board private structure to initialize 2838 * 2839 * This function initializes the vf specific data storage and then attempts to 2840 * allocate the VFs. The reason for ordering it this way is because it is much 2841 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2842 * the memory for the VFs. 2843 **/ 2844static void igb_probe_vfs(struct igb_adapter *adapter) 2845{ 2846#ifdef CONFIG_PCI_IOV 2847 struct pci_dev *pdev = adapter->pdev; 2848 struct e1000_hw *hw = &adapter->hw; 2849 2850 /* Virtualization features not supported on i210 family. */ 2851 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2852 return; 2853 2854 pci_sriov_set_totalvfs(pdev, 7); 2855 igb_pci_enable_sriov(pdev, max_vfs); 2856 2857#endif /* CONFIG_PCI_IOV */ 2858} 2859 2860static void igb_init_queue_configuration(struct igb_adapter *adapter) 2861{ 2862 struct e1000_hw *hw = &adapter->hw; 2863 u32 max_rss_queues; 2864 2865 /* Determine the maximum number of RSS queues supported. */ 2866 switch (hw->mac.type) { 2867 case e1000_i211: 2868 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2869 break; 2870 case e1000_82575: 2871 case e1000_i210: 2872 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2873 break; 2874 case e1000_i350: 2875 /* I350 cannot do RSS and SR-IOV at the same time */ 2876 if (!!adapter->vfs_allocated_count) { 2877 max_rss_queues = 1; 2878 break; 2879 } 2880 /* fall through */ 2881 case e1000_82576: 2882 if (!!adapter->vfs_allocated_count) { 2883 max_rss_queues = 2; 2884 break; 2885 } 2886 /* fall through */ 2887 case e1000_82580: 2888 case e1000_i354: 2889 default: 2890 max_rss_queues = IGB_MAX_RX_QUEUES; 2891 break; 2892 } 2893 2894 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2895 2896 /* Determine if we need to pair queues. */ 2897 switch (hw->mac.type) { 2898 case e1000_82575: 2899 case e1000_i211: 2900 /* Device supports enough interrupts without queue pairing. */ 2901 break; 2902 case e1000_82576: 2903 /* If VFs are going to be allocated with RSS queues then we 2904 * should pair the queues in order to conserve interrupts due 2905 * to limited supply. 2906 */ 2907 if ((adapter->rss_queues > 1) && 2908 (adapter->vfs_allocated_count > 6)) 2909 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2910 /* fall through */ 2911 case e1000_82580: 2912 case e1000_i350: 2913 case e1000_i354: 2914 case e1000_i210: 2915 default: 2916 /* If rss_queues > half of max_rss_queues, pair the queues in 2917 * order to conserve interrupts due to limited supply. 2918 */ 2919 if (adapter->rss_queues > (max_rss_queues / 2)) 2920 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2921 break; 2922 } 2923} 2924 2925/** 2926 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2927 * @adapter: board private structure to initialize 2928 * 2929 * igb_sw_init initializes the Adapter private data structure. 2930 * Fields are initialized based on PCI device information and 2931 * OS network device settings (MTU size). 2932 **/ 2933static int igb_sw_init(struct igb_adapter *adapter) 2934{ 2935 struct e1000_hw *hw = &adapter->hw; 2936 struct net_device *netdev = adapter->netdev; 2937 struct pci_dev *pdev = adapter->pdev; 2938 2939 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2940 2941 /* set default ring sizes */ 2942 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2943 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2944 2945 /* set default ITR values */ 2946 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2947 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2948 2949 /* set default work limits */ 2950 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2951 2952 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2953 VLAN_HLEN; 2954 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2955 2956 spin_lock_init(&adapter->stats64_lock); 2957#ifdef CONFIG_PCI_IOV 2958 switch (hw->mac.type) { 2959 case e1000_82576: 2960 case e1000_i350: 2961 if (max_vfs > 7) { 2962 dev_warn(&pdev->dev, 2963 "Maximum of 7 VFs per PF, using max\n"); 2964 max_vfs = adapter->vfs_allocated_count = 7; 2965 } else 2966 adapter->vfs_allocated_count = max_vfs; 2967 if (adapter->vfs_allocated_count) 2968 dev_warn(&pdev->dev, 2969 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 2970 break; 2971 default: 2972 break; 2973 } 2974#endif /* CONFIG_PCI_IOV */ 2975 2976 igb_init_queue_configuration(adapter); 2977 2978 /* Setup and initialize a copy of the hw vlan table array */ 2979 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 2980 GFP_ATOMIC); 2981 2982 /* This call may decrease the number of queues */ 2983 if (igb_init_interrupt_scheme(adapter, true)) { 2984 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2985 return -ENOMEM; 2986 } 2987 2988 igb_probe_vfs(adapter); 2989 2990 /* Explicitly disable IRQ since the NIC can be in any state. */ 2991 igb_irq_disable(adapter); 2992 2993 if (hw->mac.type >= e1000_i350) 2994 adapter->flags &= ~IGB_FLAG_DMAC; 2995 2996 set_bit(__IGB_DOWN, &adapter->state); 2997 return 0; 2998} 2999 3000/** 3001 * igb_open - Called when a network interface is made active 3002 * @netdev: network interface device structure 3003 * 3004 * Returns 0 on success, negative value on failure 3005 * 3006 * The open entry point is called when a network interface is made 3007 * active by the system (IFF_UP). At this point all resources needed 3008 * for transmit and receive operations are allocated, the interrupt 3009 * handler is registered with the OS, the watchdog timer is started, 3010 * and the stack is notified that the interface is ready. 3011 **/ 3012static int __igb_open(struct net_device *netdev, bool resuming) 3013{ 3014 struct igb_adapter *adapter = netdev_priv(netdev); 3015 struct e1000_hw *hw = &adapter->hw; 3016 struct pci_dev *pdev = adapter->pdev; 3017 int err; 3018 int i; 3019 3020 /* disallow open during test */ 3021 if (test_bit(__IGB_TESTING, &adapter->state)) { 3022 WARN_ON(resuming); 3023 return -EBUSY; 3024 } 3025 3026 if (!resuming) 3027 pm_runtime_get_sync(&pdev->dev); 3028 3029 netif_carrier_off(netdev); 3030 3031 /* allocate transmit descriptors */ 3032 err = igb_setup_all_tx_resources(adapter); 3033 if (err) 3034 goto err_setup_tx; 3035 3036 /* allocate receive descriptors */ 3037 err = igb_setup_all_rx_resources(adapter); 3038 if (err) 3039 goto err_setup_rx; 3040 3041 igb_power_up_link(adapter); 3042 3043 /* before we allocate an interrupt, we must be ready to handle it. 3044 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3045 * as soon as we call pci_request_irq, so we have to setup our 3046 * clean_rx handler before we do so. 3047 */ 3048 igb_configure(adapter); 3049 3050 err = igb_request_irq(adapter); 3051 if (err) 3052 goto err_req_irq; 3053 3054 /* Notify the stack of the actual queue counts. */ 3055 err = netif_set_real_num_tx_queues(adapter->netdev, 3056 adapter->num_tx_queues); 3057 if (err) 3058 goto err_set_queues; 3059 3060 err = netif_set_real_num_rx_queues(adapter->netdev, 3061 adapter->num_rx_queues); 3062 if (err) 3063 goto err_set_queues; 3064 3065 /* From here on the code is the same as igb_up() */ 3066 clear_bit(__IGB_DOWN, &adapter->state); 3067 3068 for (i = 0; i < adapter->num_q_vectors; i++) 3069 napi_enable(&(adapter->q_vector[i]->napi)); 3070 3071 /* Clear any pending interrupts. */ 3072 rd32(E1000_ICR); 3073 3074 igb_irq_enable(adapter); 3075 3076 /* notify VFs that reset has been completed */ 3077 if (adapter->vfs_allocated_count) { 3078 u32 reg_data = rd32(E1000_CTRL_EXT); 3079 3080 reg_data |= E1000_CTRL_EXT_PFRSTD; 3081 wr32(E1000_CTRL_EXT, reg_data); 3082 } 3083 3084 netif_tx_start_all_queues(netdev); 3085 3086 if (!resuming) 3087 pm_runtime_put(&pdev->dev); 3088 3089 /* start the watchdog. */ 3090 hw->mac.get_link_status = 1; 3091 schedule_work(&adapter->watchdog_task); 3092 3093 return 0; 3094 3095err_set_queues: 3096 igb_free_irq(adapter); 3097err_req_irq: 3098 igb_release_hw_control(adapter); 3099 igb_power_down_link(adapter); 3100 igb_free_all_rx_resources(adapter); 3101err_setup_rx: 3102 igb_free_all_tx_resources(adapter); 3103err_setup_tx: 3104 igb_reset(adapter); 3105 if (!resuming) 3106 pm_runtime_put(&pdev->dev); 3107 3108 return err; 3109} 3110 3111static int igb_open(struct net_device *netdev) 3112{ 3113 return __igb_open(netdev, false); 3114} 3115 3116/** 3117 * igb_close - Disables a network interface 3118 * @netdev: network interface device structure 3119 * 3120 * Returns 0, this is not allowed to fail 3121 * 3122 * The close entry point is called when an interface is de-activated 3123 * by the OS. The hardware is still under the driver's control, but 3124 * needs to be disabled. A global MAC reset is issued to stop the 3125 * hardware, and all transmit and receive resources are freed. 3126 **/ 3127static int __igb_close(struct net_device *netdev, bool suspending) 3128{ 3129 struct igb_adapter *adapter = netdev_priv(netdev); 3130 struct pci_dev *pdev = adapter->pdev; 3131 3132 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3133 3134 if (!suspending) 3135 pm_runtime_get_sync(&pdev->dev); 3136 3137 igb_down(adapter); 3138 igb_free_irq(adapter); 3139 3140 igb_free_all_tx_resources(adapter); 3141 igb_free_all_rx_resources(adapter); 3142 3143 if (!suspending) 3144 pm_runtime_put_sync(&pdev->dev); 3145 return 0; 3146} 3147 3148static int igb_close(struct net_device *netdev) 3149{ 3150 return __igb_close(netdev, false); 3151} 3152 3153/** 3154 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3155 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3156 * 3157 * Return 0 on success, negative on failure 3158 **/ 3159int igb_setup_tx_resources(struct igb_ring *tx_ring) 3160{ 3161 struct device *dev = tx_ring->dev; 3162 int size; 3163 3164 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3165 3166 tx_ring->tx_buffer_info = vzalloc(size); 3167 if (!tx_ring->tx_buffer_info) 3168 goto err; 3169 3170 /* round up to nearest 4K */ 3171 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3172 tx_ring->size = ALIGN(tx_ring->size, 4096); 3173 3174 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3175 &tx_ring->dma, GFP_KERNEL); 3176 if (!tx_ring->desc) 3177 goto err; 3178 3179 tx_ring->next_to_use = 0; 3180 tx_ring->next_to_clean = 0; 3181 3182 return 0; 3183 3184err: 3185 vfree(tx_ring->tx_buffer_info); 3186 tx_ring->tx_buffer_info = NULL; 3187 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3188 return -ENOMEM; 3189} 3190 3191/** 3192 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3193 * (Descriptors) for all queues 3194 * @adapter: board private structure 3195 * 3196 * Return 0 on success, negative on failure 3197 **/ 3198static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3199{ 3200 struct pci_dev *pdev = adapter->pdev; 3201 int i, err = 0; 3202 3203 for (i = 0; i < adapter->num_tx_queues; i++) { 3204 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3205 if (err) { 3206 dev_err(&pdev->dev, 3207 "Allocation for Tx Queue %u failed\n", i); 3208 for (i--; i >= 0; i--) 3209 igb_free_tx_resources(adapter->tx_ring[i]); 3210 break; 3211 } 3212 } 3213 3214 return err; 3215} 3216 3217/** 3218 * igb_setup_tctl - configure the transmit control registers 3219 * @adapter: Board private structure 3220 **/ 3221void igb_setup_tctl(struct igb_adapter *adapter) 3222{ 3223 struct e1000_hw *hw = &adapter->hw; 3224 u32 tctl; 3225 3226 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3227 wr32(E1000_TXDCTL(0), 0); 3228 3229 /* Program the Transmit Control Register */ 3230 tctl = rd32(E1000_TCTL); 3231 tctl &= ~E1000_TCTL_CT; 3232 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3233 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3234 3235 igb_config_collision_dist(hw); 3236 3237 /* Enable transmits */ 3238 tctl |= E1000_TCTL_EN; 3239 3240 wr32(E1000_TCTL, tctl); 3241} 3242 3243/** 3244 * igb_configure_tx_ring - Configure transmit ring after Reset 3245 * @adapter: board private structure 3246 * @ring: tx ring to configure 3247 * 3248 * Configure a transmit ring after a reset. 3249 **/ 3250void igb_configure_tx_ring(struct igb_adapter *adapter, 3251 struct igb_ring *ring) 3252{ 3253 struct e1000_hw *hw = &adapter->hw; 3254 u32 txdctl = 0; 3255 u64 tdba = ring->dma; 3256 int reg_idx = ring->reg_idx; 3257 3258 /* disable the queue */ 3259 wr32(E1000_TXDCTL(reg_idx), 0); 3260 wrfl(); 3261 mdelay(10); 3262 3263 wr32(E1000_TDLEN(reg_idx), 3264 ring->count * sizeof(union e1000_adv_tx_desc)); 3265 wr32(E1000_TDBAL(reg_idx), 3266 tdba & 0x00000000ffffffffULL); 3267 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3268 3269 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 3270 wr32(E1000_TDH(reg_idx), 0); 3271 writel(0, ring->tail); 3272 3273 txdctl |= IGB_TX_PTHRESH; 3274 txdctl |= IGB_TX_HTHRESH << 8; 3275 txdctl |= IGB_TX_WTHRESH << 16; 3276 3277 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3278 wr32(E1000_TXDCTL(reg_idx), txdctl); 3279} 3280 3281/** 3282 * igb_configure_tx - Configure transmit Unit after Reset 3283 * @adapter: board private structure 3284 * 3285 * Configure the Tx unit of the MAC after a reset. 3286 **/ 3287static void igb_configure_tx(struct igb_adapter *adapter) 3288{ 3289 int i; 3290 3291 for (i = 0; i < adapter->num_tx_queues; i++) 3292 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3293} 3294 3295/** 3296 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3297 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3298 * 3299 * Returns 0 on success, negative on failure 3300 **/ 3301int igb_setup_rx_resources(struct igb_ring *rx_ring) 3302{ 3303 struct device *dev = rx_ring->dev; 3304 int size; 3305 3306 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3307 3308 rx_ring->rx_buffer_info = vzalloc(size); 3309 if (!rx_ring->rx_buffer_info) 3310 goto err; 3311 3312 /* Round up to nearest 4K */ 3313 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3314 rx_ring->size = ALIGN(rx_ring->size, 4096); 3315 3316 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3317 &rx_ring->dma, GFP_KERNEL); 3318 if (!rx_ring->desc) 3319 goto err; 3320 3321 rx_ring->next_to_alloc = 0; 3322 rx_ring->next_to_clean = 0; 3323 rx_ring->next_to_use = 0; 3324 3325 return 0; 3326 3327err: 3328 vfree(rx_ring->rx_buffer_info); 3329 rx_ring->rx_buffer_info = NULL; 3330 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3331 return -ENOMEM; 3332} 3333 3334/** 3335 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3336 * (Descriptors) for all queues 3337 * @adapter: board private structure 3338 * 3339 * Return 0 on success, negative on failure 3340 **/ 3341static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3342{ 3343 struct pci_dev *pdev = adapter->pdev; 3344 int i, err = 0; 3345 3346 for (i = 0; i < adapter->num_rx_queues; i++) { 3347 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3348 if (err) { 3349 dev_err(&pdev->dev, 3350 "Allocation for Rx Queue %u failed\n", i); 3351 for (i--; i >= 0; i--) 3352 igb_free_rx_resources(adapter->rx_ring[i]); 3353 break; 3354 } 3355 } 3356 3357 return err; 3358} 3359 3360/** 3361 * igb_setup_mrqc - configure the multiple receive queue control registers 3362 * @adapter: Board private structure 3363 **/ 3364static void igb_setup_mrqc(struct igb_adapter *adapter) 3365{ 3366 struct e1000_hw *hw = &adapter->hw; 3367 u32 mrqc, rxcsum; 3368 u32 j, num_rx_queues; 3369 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, 3370 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, 3371 0xA32DCB77, 0x0CF23080, 0x3BB7426A, 3372 0xFA01ACBE }; 3373 3374 /* Fill out hash function seeds */ 3375 for (j = 0; j < 10; j++) 3376 wr32(E1000_RSSRK(j), rsskey[j]); 3377 3378 num_rx_queues = adapter->rss_queues; 3379 3380 switch (hw->mac.type) { 3381 case e1000_82576: 3382 /* 82576 supports 2 RSS queues for SR-IOV */ 3383 if (adapter->vfs_allocated_count) 3384 num_rx_queues = 2; 3385 break; 3386 default: 3387 break; 3388 } 3389 3390 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3391 for (j = 0; j < IGB_RETA_SIZE; j++) 3392 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE; 3393 adapter->rss_indir_tbl_init = num_rx_queues; 3394 } 3395 igb_write_rss_indir_tbl(adapter); 3396 3397 /* Disable raw packet checksumming so that RSS hash is placed in 3398 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3399 * offloads as they are enabled by default 3400 */ 3401 rxcsum = rd32(E1000_RXCSUM); 3402 rxcsum |= E1000_RXCSUM_PCSD; 3403 3404 if (adapter->hw.mac.type >= e1000_82576) 3405 /* Enable Receive Checksum Offload for SCTP */ 3406 rxcsum |= E1000_RXCSUM_CRCOFL; 3407 3408 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3409 wr32(E1000_RXCSUM, rxcsum); 3410 3411 /* Generate RSS hash based on packet types, TCP/UDP 3412 * port numbers and/or IPv4/v6 src and dst addresses 3413 */ 3414 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3415 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3416 E1000_MRQC_RSS_FIELD_IPV6 | 3417 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3418 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3419 3420 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3421 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3422 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3423 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3424 3425 /* If VMDq is enabled then we set the appropriate mode for that, else 3426 * we default to RSS so that an RSS hash is calculated per packet even 3427 * if we are only using one queue 3428 */ 3429 if (adapter->vfs_allocated_count) { 3430 if (hw->mac.type > e1000_82575) { 3431 /* Set the default pool for the PF's first queue */ 3432 u32 vtctl = rd32(E1000_VT_CTL); 3433 3434 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3435 E1000_VT_CTL_DISABLE_DEF_POOL); 3436 vtctl |= adapter->vfs_allocated_count << 3437 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3438 wr32(E1000_VT_CTL, vtctl); 3439 } 3440 if (adapter->rss_queues > 1) 3441 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 3442 else 3443 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3444 } else { 3445 if (hw->mac.type != e1000_i211) 3446 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 3447 } 3448 igb_vmm_control(adapter); 3449 3450 wr32(E1000_MRQC, mrqc); 3451} 3452 3453/** 3454 * igb_setup_rctl - configure the receive control registers 3455 * @adapter: Board private structure 3456 **/ 3457void igb_setup_rctl(struct igb_adapter *adapter) 3458{ 3459 struct e1000_hw *hw = &adapter->hw; 3460 u32 rctl; 3461 3462 rctl = rd32(E1000_RCTL); 3463 3464 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3465 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3466 3467 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3468 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3469 3470 /* enable stripping of CRC. It's unlikely this will break BMC 3471 * redirection as it did with e1000. Newer features require 3472 * that the HW strips the CRC. 3473 */ 3474 rctl |= E1000_RCTL_SECRC; 3475 3476 /* disable store bad packets and clear size bits. */ 3477 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3478 3479 /* enable LPE to prevent packets larger than max_frame_size */ 3480 rctl |= E1000_RCTL_LPE; 3481 3482 /* disable queue 0 to prevent tail write w/o re-config */ 3483 wr32(E1000_RXDCTL(0), 0); 3484 3485 /* Attention!!! For SR-IOV PF driver operations you must enable 3486 * queue drop for all VF and PF queues to prevent head of line blocking 3487 * if an un-trusted VF does not provide descriptors to hardware. 3488 */ 3489 if (adapter->vfs_allocated_count) { 3490 /* set all queue drop enable bits */ 3491 wr32(E1000_QDE, ALL_QUEUES); 3492 } 3493 3494 /* This is useful for sniffing bad packets. */ 3495 if (adapter->netdev->features & NETIF_F_RXALL) { 3496 /* UPE and MPE will be handled by normal PROMISC logic 3497 * in e1000e_set_rx_mode 3498 */ 3499 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3500 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3501 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3502 3503 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3504 E1000_RCTL_DPF | /* Allow filtered pause */ 3505 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3506 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3507 * and that breaks VLANs. 3508 */ 3509 } 3510 3511 wr32(E1000_RCTL, rctl); 3512} 3513 3514static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3515 int vfn) 3516{ 3517 struct e1000_hw *hw = &adapter->hw; 3518 u32 vmolr; 3519 3520 /* if it isn't the PF check to see if VFs are enabled and 3521 * increase the size to support vlan tags 3522 */ 3523 if (vfn < adapter->vfs_allocated_count && 3524 adapter->vf_data[vfn].vlans_enabled) 3525 size += VLAN_TAG_SIZE; 3526 3527 vmolr = rd32(E1000_VMOLR(vfn)); 3528 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3529 vmolr |= size | E1000_VMOLR_LPE; 3530 wr32(E1000_VMOLR(vfn), vmolr); 3531 3532 return 0; 3533} 3534 3535/** 3536 * igb_rlpml_set - set maximum receive packet size 3537 * @adapter: board private structure 3538 * 3539 * Configure maximum receivable packet size. 3540 **/ 3541static void igb_rlpml_set(struct igb_adapter *adapter) 3542{ 3543 u32 max_frame_size = adapter->max_frame_size; 3544 struct e1000_hw *hw = &adapter->hw; 3545 u16 pf_id = adapter->vfs_allocated_count; 3546 3547 if (pf_id) { 3548 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3549 /* If we're in VMDQ or SR-IOV mode, then set global RLPML 3550 * to our max jumbo frame size, in case we need to enable 3551 * jumbo frames on one of the rings later. 3552 * This will not pass over-length frames into the default 3553 * queue because it's gated by the VMOLR.RLPML. 3554 */ 3555 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3556 } 3557 3558 wr32(E1000_RLPML, max_frame_size); 3559} 3560 3561static inline void igb_set_vmolr(struct igb_adapter *adapter, 3562 int vfn, bool aupe) 3563{ 3564 struct e1000_hw *hw = &adapter->hw; 3565 u32 vmolr; 3566 3567 /* This register exists only on 82576 and newer so if we are older then 3568 * we should exit and do nothing 3569 */ 3570 if (hw->mac.type < e1000_82576) 3571 return; 3572 3573 vmolr = rd32(E1000_VMOLR(vfn)); 3574 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3575 if (hw->mac.type == e1000_i350) { 3576 u32 dvmolr; 3577 3578 dvmolr = rd32(E1000_DVMOLR(vfn)); 3579 dvmolr |= E1000_DVMOLR_STRVLAN; 3580 wr32(E1000_DVMOLR(vfn), dvmolr); 3581 } 3582 if (aupe) 3583 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3584 else 3585 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3586 3587 /* clear all bits that might not be set */ 3588 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3589 3590 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3591 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3592 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3593 * multicast packets 3594 */ 3595 if (vfn <= adapter->vfs_allocated_count) 3596 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3597 3598 wr32(E1000_VMOLR(vfn), vmolr); 3599} 3600 3601/** 3602 * igb_configure_rx_ring - Configure a receive ring after Reset 3603 * @adapter: board private structure 3604 * @ring: receive ring to be configured 3605 * 3606 * Configure the Rx unit of the MAC after a reset. 3607 **/ 3608void igb_configure_rx_ring(struct igb_adapter *adapter, 3609 struct igb_ring *ring) 3610{ 3611 struct e1000_hw *hw = &adapter->hw; 3612 u64 rdba = ring->dma; 3613 int reg_idx = ring->reg_idx; 3614 u32 srrctl = 0, rxdctl = 0; 3615 3616 /* disable the queue */ 3617 wr32(E1000_RXDCTL(reg_idx), 0); 3618 3619 /* Set DMA base address registers */ 3620 wr32(E1000_RDBAL(reg_idx), 3621 rdba & 0x00000000ffffffffULL); 3622 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3623 wr32(E1000_RDLEN(reg_idx), 3624 ring->count * sizeof(union e1000_adv_rx_desc)); 3625 3626 /* initialize head and tail */ 3627 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3628 wr32(E1000_RDH(reg_idx), 0); 3629 writel(0, ring->tail); 3630 3631 /* set descriptor configuration */ 3632 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3633 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3634 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3635 if (hw->mac.type >= e1000_82580) 3636 srrctl |= E1000_SRRCTL_TIMESTAMP; 3637 /* Only set Drop Enable if we are supporting multiple queues */ 3638 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3639 srrctl |= E1000_SRRCTL_DROP_EN; 3640 3641 wr32(E1000_SRRCTL(reg_idx), srrctl); 3642 3643 /* set filtering for VMDQ pools */ 3644 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3645 3646 rxdctl |= IGB_RX_PTHRESH; 3647 rxdctl |= IGB_RX_HTHRESH << 8; 3648 rxdctl |= IGB_RX_WTHRESH << 16; 3649 3650 /* enable receive descriptor fetching */ 3651 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3652 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3653} 3654 3655/** 3656 * igb_configure_rx - Configure receive Unit after Reset 3657 * @adapter: board private structure 3658 * 3659 * Configure the Rx unit of the MAC after a reset. 3660 **/ 3661static void igb_configure_rx(struct igb_adapter *adapter) 3662{ 3663 int i; 3664 3665 /* set UTA to appropriate mode */ 3666 igb_set_uta(adapter); 3667 3668 /* set the correct pool for the PF default MAC address in entry 0 */ 3669 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3670 adapter->vfs_allocated_count); 3671 3672 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3673 * the Base and Length of the Rx Descriptor Ring 3674 */ 3675 for (i = 0; i < adapter->num_rx_queues; i++) 3676 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3677} 3678 3679/** 3680 * igb_free_tx_resources - Free Tx Resources per Queue 3681 * @tx_ring: Tx descriptor ring for a specific queue 3682 * 3683 * Free all transmit software resources 3684 **/ 3685void igb_free_tx_resources(struct igb_ring *tx_ring) 3686{ 3687 igb_clean_tx_ring(tx_ring); 3688 3689 vfree(tx_ring->tx_buffer_info); 3690 tx_ring->tx_buffer_info = NULL; 3691 3692 /* if not set, then don't free */ 3693 if (!tx_ring->desc) 3694 return; 3695 3696 dma_free_coherent(tx_ring->dev, tx_ring->size, 3697 tx_ring->desc, tx_ring->dma); 3698 3699 tx_ring->desc = NULL; 3700} 3701 3702/** 3703 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3704 * @adapter: board private structure 3705 * 3706 * Free all transmit software resources 3707 **/ 3708static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3709{ 3710 int i; 3711 3712 for (i = 0; i < adapter->num_tx_queues; i++) 3713 igb_free_tx_resources(adapter->tx_ring[i]); 3714} 3715 3716void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3717 struct igb_tx_buffer *tx_buffer) 3718{ 3719 if (tx_buffer->skb) { 3720 dev_kfree_skb_any(tx_buffer->skb); 3721 if (dma_unmap_len(tx_buffer, len)) 3722 dma_unmap_single(ring->dev, 3723 dma_unmap_addr(tx_buffer, dma), 3724 dma_unmap_len(tx_buffer, len), 3725 DMA_TO_DEVICE); 3726 } else if (dma_unmap_len(tx_buffer, len)) { 3727 dma_unmap_page(ring->dev, 3728 dma_unmap_addr(tx_buffer, dma), 3729 dma_unmap_len(tx_buffer, len), 3730 DMA_TO_DEVICE); 3731 } 3732 tx_buffer->next_to_watch = NULL; 3733 tx_buffer->skb = NULL; 3734 dma_unmap_len_set(tx_buffer, len, 0); 3735 /* buffer_info must be completely set up in the transmit path */ 3736} 3737 3738/** 3739 * igb_clean_tx_ring - Free Tx Buffers 3740 * @tx_ring: ring to be cleaned 3741 **/ 3742static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3743{ 3744 struct igb_tx_buffer *buffer_info; 3745 unsigned long size; 3746 u16 i; 3747 3748 if (!tx_ring->tx_buffer_info) 3749 return; 3750 /* Free all the Tx ring sk_buffs */ 3751 3752 for (i = 0; i < tx_ring->count; i++) { 3753 buffer_info = &tx_ring->tx_buffer_info[i]; 3754 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3755 } 3756 3757 netdev_tx_reset_queue(txring_txq(tx_ring)); 3758 3759 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3760 memset(tx_ring->tx_buffer_info, 0, size); 3761 3762 /* Zero out the descriptor ring */ 3763 memset(tx_ring->desc, 0, tx_ring->size); 3764 3765 tx_ring->next_to_use = 0; 3766 tx_ring->next_to_clean = 0; 3767} 3768 3769/** 3770 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3771 * @adapter: board private structure 3772 **/ 3773static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3774{ 3775 int i; 3776 3777 for (i = 0; i < adapter->num_tx_queues; i++) 3778 igb_clean_tx_ring(adapter->tx_ring[i]); 3779} 3780 3781/** 3782 * igb_free_rx_resources - Free Rx Resources 3783 * @rx_ring: ring to clean the resources from 3784 * 3785 * Free all receive software resources 3786 **/ 3787void igb_free_rx_resources(struct igb_ring *rx_ring) 3788{ 3789 igb_clean_rx_ring(rx_ring); 3790 3791 vfree(rx_ring->rx_buffer_info); 3792 rx_ring->rx_buffer_info = NULL; 3793 3794 /* if not set, then don't free */ 3795 if (!rx_ring->desc) 3796 return; 3797 3798 dma_free_coherent(rx_ring->dev, rx_ring->size, 3799 rx_ring->desc, rx_ring->dma); 3800 3801 rx_ring->desc = NULL; 3802} 3803 3804/** 3805 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3806 * @adapter: board private structure 3807 * 3808 * Free all receive software resources 3809 **/ 3810static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3811{ 3812 int i; 3813 3814 for (i = 0; i < adapter->num_rx_queues; i++) 3815 igb_free_rx_resources(adapter->rx_ring[i]); 3816} 3817 3818/** 3819 * igb_clean_rx_ring - Free Rx Buffers per Queue 3820 * @rx_ring: ring to free buffers from 3821 **/ 3822static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3823{ 3824 unsigned long size; 3825 u16 i; 3826 3827 if (rx_ring->skb) 3828 dev_kfree_skb(rx_ring->skb); 3829 rx_ring->skb = NULL; 3830 3831 if (!rx_ring->rx_buffer_info) 3832 return; 3833 3834 /* Free all the Rx ring sk_buffs */ 3835 for (i = 0; i < rx_ring->count; i++) { 3836 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3837 3838 if (!buffer_info->page) 3839 continue; 3840 3841 dma_unmap_page(rx_ring->dev, 3842 buffer_info->dma, 3843 PAGE_SIZE, 3844 DMA_FROM_DEVICE); 3845 __free_page(buffer_info->page); 3846 3847 buffer_info->page = NULL; 3848 } 3849 3850 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3851 memset(rx_ring->rx_buffer_info, 0, size); 3852 3853 /* Zero out the descriptor ring */ 3854 memset(rx_ring->desc, 0, rx_ring->size); 3855 3856 rx_ring->next_to_alloc = 0; 3857 rx_ring->next_to_clean = 0; 3858 rx_ring->next_to_use = 0; 3859} 3860 3861/** 3862 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3863 * @adapter: board private structure 3864 **/ 3865static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3866{ 3867 int i; 3868 3869 for (i = 0; i < adapter->num_rx_queues; i++) 3870 igb_clean_rx_ring(adapter->rx_ring[i]); 3871} 3872 3873/** 3874 * igb_set_mac - Change the Ethernet Address of the NIC 3875 * @netdev: network interface device structure 3876 * @p: pointer to an address structure 3877 * 3878 * Returns 0 on success, negative on failure 3879 **/ 3880static int igb_set_mac(struct net_device *netdev, void *p) 3881{ 3882 struct igb_adapter *adapter = netdev_priv(netdev); 3883 struct e1000_hw *hw = &adapter->hw; 3884 struct sockaddr *addr = p; 3885 3886 if (!is_valid_ether_addr(addr->sa_data)) 3887 return -EADDRNOTAVAIL; 3888 3889 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3890 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3891 3892 /* set the correct pool for the new PF MAC address in entry 0 */ 3893 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3894 adapter->vfs_allocated_count); 3895 3896 return 0; 3897} 3898 3899/** 3900 * igb_write_mc_addr_list - write multicast addresses to MTA 3901 * @netdev: network interface device structure 3902 * 3903 * Writes multicast address list to the MTA hash table. 3904 * Returns: -ENOMEM on failure 3905 * 0 on no addresses written 3906 * X on writing X addresses to MTA 3907 **/ 3908static int igb_write_mc_addr_list(struct net_device *netdev) 3909{ 3910 struct igb_adapter *adapter = netdev_priv(netdev); 3911 struct e1000_hw *hw = &adapter->hw; 3912 struct netdev_hw_addr *ha; 3913 u8 *mta_list; 3914 int i; 3915 3916 if (netdev_mc_empty(netdev)) { 3917 /* nothing to program, so clear mc list */ 3918 igb_update_mc_addr_list(hw, NULL, 0); 3919 igb_restore_vf_multicasts(adapter); 3920 return 0; 3921 } 3922 3923 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3924 if (!mta_list) 3925 return -ENOMEM; 3926 3927 /* The shared function expects a packed array of only addresses. */ 3928 i = 0; 3929 netdev_for_each_mc_addr(ha, netdev) 3930 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3931 3932 igb_update_mc_addr_list(hw, mta_list, i); 3933 kfree(mta_list); 3934 3935 return netdev_mc_count(netdev); 3936} 3937 3938/** 3939 * igb_write_uc_addr_list - write unicast addresses to RAR table 3940 * @netdev: network interface device structure 3941 * 3942 * Writes unicast address list to the RAR table. 3943 * Returns: -ENOMEM on failure/insufficient address space 3944 * 0 on no addresses written 3945 * X on writing X addresses to the RAR table 3946 **/ 3947static int igb_write_uc_addr_list(struct net_device *netdev) 3948{ 3949 struct igb_adapter *adapter = netdev_priv(netdev); 3950 struct e1000_hw *hw = &adapter->hw; 3951 unsigned int vfn = adapter->vfs_allocated_count; 3952 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3953 int count = 0; 3954 3955 /* return ENOMEM indicating insufficient memory for addresses */ 3956 if (netdev_uc_count(netdev) > rar_entries) 3957 return -ENOMEM; 3958 3959 if (!netdev_uc_empty(netdev) && rar_entries) { 3960 struct netdev_hw_addr *ha; 3961 3962 netdev_for_each_uc_addr(ha, netdev) { 3963 if (!rar_entries) 3964 break; 3965 igb_rar_set_qsel(adapter, ha->addr, 3966 rar_entries--, 3967 vfn); 3968 count++; 3969 } 3970 } 3971 /* write the addresses in reverse order to avoid write combining */ 3972 for (; rar_entries > 0 ; rar_entries--) { 3973 wr32(E1000_RAH(rar_entries), 0); 3974 wr32(E1000_RAL(rar_entries), 0); 3975 } 3976 wrfl(); 3977 3978 return count; 3979} 3980 3981/** 3982 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3983 * @netdev: network interface device structure 3984 * 3985 * The set_rx_mode entry point is called whenever the unicast or multicast 3986 * address lists or the network interface flags are updated. This routine is 3987 * responsible for configuring the hardware for proper unicast, multicast, 3988 * promiscuous mode, and all-multi behavior. 3989 **/ 3990static void igb_set_rx_mode(struct net_device *netdev) 3991{ 3992 struct igb_adapter *adapter = netdev_priv(netdev); 3993 struct e1000_hw *hw = &adapter->hw; 3994 unsigned int vfn = adapter->vfs_allocated_count; 3995 u32 rctl, vmolr = 0; 3996 int count; 3997 3998 /* Check for Promiscuous and All Multicast modes */ 3999 rctl = rd32(E1000_RCTL); 4000 4001 /* clear the effected bits */ 4002 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 4003 4004 if (netdev->flags & IFF_PROMISC) { 4005 /* retain VLAN HW filtering if in VT mode */ 4006 if (adapter->vfs_allocated_count) 4007 rctl |= E1000_RCTL_VFE; 4008 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 4009 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 4010 } else { 4011 if (netdev->flags & IFF_ALLMULTI) { 4012 rctl |= E1000_RCTL_MPE; 4013 vmolr |= E1000_VMOLR_MPME; 4014 } else { 4015 /* Write addresses to the MTA, if the attempt fails 4016 * then we should just turn on promiscuous mode so 4017 * that we can at least receive multicast traffic 4018 */ 4019 count = igb_write_mc_addr_list(netdev); 4020 if (count < 0) { 4021 rctl |= E1000_RCTL_MPE; 4022 vmolr |= E1000_VMOLR_MPME; 4023 } else if (count) { 4024 vmolr |= E1000_VMOLR_ROMPE; 4025 } 4026 } 4027 /* Write addresses to available RAR registers, if there is not 4028 * sufficient space to store all the addresses then enable 4029 * unicast promiscuous mode 4030 */ 4031 count = igb_write_uc_addr_list(netdev); 4032 if (count < 0) { 4033 rctl |= E1000_RCTL_UPE; 4034 vmolr |= E1000_VMOLR_ROPE; 4035 } 4036 rctl |= E1000_RCTL_VFE; 4037 } 4038 wr32(E1000_RCTL, rctl); 4039 4040 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4041 * the VMOLR to enable the appropriate modes. Without this workaround 4042 * we will have issues with VLAN tag stripping not being done for frames 4043 * that are only arriving because we are the default pool 4044 */ 4045 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4046 return; 4047 4048 vmolr |= rd32(E1000_VMOLR(vfn)) & 4049 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4050 wr32(E1000_VMOLR(vfn), vmolr); 4051 igb_restore_vf_multicasts(adapter); 4052} 4053 4054static void igb_check_wvbr(struct igb_adapter *adapter) 4055{ 4056 struct e1000_hw *hw = &adapter->hw; 4057 u32 wvbr = 0; 4058 4059 switch (hw->mac.type) { 4060 case e1000_82576: 4061 case e1000_i350: 4062 if (!(wvbr = rd32(E1000_WVBR))) 4063 return; 4064 break; 4065 default: 4066 break; 4067 } 4068 4069 adapter->wvbr |= wvbr; 4070} 4071 4072#define IGB_STAGGERED_QUEUE_OFFSET 8 4073 4074static void igb_spoof_check(struct igb_adapter *adapter) 4075{ 4076 int j; 4077 4078 if (!adapter->wvbr) 4079 return; 4080 4081 for (j = 0; j < adapter->vfs_allocated_count; j++) { 4082 if (adapter->wvbr & (1 << j) || 4083 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 4084 dev_warn(&adapter->pdev->dev, 4085 "Spoof event(s) detected on VF %d\n", j); 4086 adapter->wvbr &= 4087 ~((1 << j) | 4088 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 4089 } 4090 } 4091} 4092 4093/* Need to wait a few seconds after link up to get diagnostic information from 4094 * the phy 4095 */ 4096static void igb_update_phy_info(unsigned long data) 4097{ 4098 struct igb_adapter *adapter = (struct igb_adapter *) data; 4099 igb_get_phy_info(&adapter->hw); 4100} 4101 4102/** 4103 * igb_has_link - check shared code for link and determine up/down 4104 * @adapter: pointer to driver private info 4105 **/ 4106bool igb_has_link(struct igb_adapter *adapter) 4107{ 4108 struct e1000_hw *hw = &adapter->hw; 4109 bool link_active = false; 4110 4111 /* get_link_status is set on LSC (link status) interrupt or 4112 * rx sequence error interrupt. get_link_status will stay 4113 * false until the e1000_check_for_link establishes link 4114 * for copper adapters ONLY 4115 */ 4116 switch (hw->phy.media_type) { 4117 case e1000_media_type_copper: 4118 if (!hw->mac.get_link_status) 4119 return true; 4120 case e1000_media_type_internal_serdes: 4121 hw->mac.ops.check_for_link(hw); 4122 link_active = !hw->mac.get_link_status; 4123 break; 4124 default: 4125 case e1000_media_type_unknown: 4126 break; 4127 } 4128 4129 if (((hw->mac.type == e1000_i210) || 4130 (hw->mac.type == e1000_i211)) && 4131 (hw->phy.id == I210_I_PHY_ID)) { 4132 if (!netif_carrier_ok(adapter->netdev)) { 4133 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4134 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4135 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4136 adapter->link_check_timeout = jiffies; 4137 } 4138 } 4139 4140 return link_active; 4141} 4142 4143static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4144{ 4145 bool ret = false; 4146 u32 ctrl_ext, thstat; 4147 4148 /* check for thermal sensor event on i350 copper only */ 4149 if (hw->mac.type == e1000_i350) { 4150 thstat = rd32(E1000_THSTAT); 4151 ctrl_ext = rd32(E1000_CTRL_EXT); 4152 4153 if ((hw->phy.media_type == e1000_media_type_copper) && 4154 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4155 ret = !!(thstat & event); 4156 } 4157 4158 return ret; 4159} 4160 4161/** 4162 * igb_watchdog - Timer Call-back 4163 * @data: pointer to adapter cast into an unsigned long 4164 **/ 4165static void igb_watchdog(unsigned long data) 4166{ 4167 struct igb_adapter *adapter = (struct igb_adapter *)data; 4168 /* Do the rest outside of interrupt context */ 4169 schedule_work(&adapter->watchdog_task); 4170} 4171 4172static void igb_watchdog_task(struct work_struct *work) 4173{ 4174 struct igb_adapter *adapter = container_of(work, 4175 struct igb_adapter, 4176 watchdog_task); 4177 struct e1000_hw *hw = &adapter->hw; 4178 struct e1000_phy_info *phy = &hw->phy; 4179 struct net_device *netdev = adapter->netdev; 4180 u32 link; 4181 int i; 4182 u32 connsw; 4183 4184 link = igb_has_link(adapter); 4185 4186 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4187 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4188 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4189 else 4190 link = false; 4191 } 4192 4193 /* Force link down if we have fiber to swap to */ 4194 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4195 if (hw->phy.media_type == e1000_media_type_copper) { 4196 connsw = rd32(E1000_CONNSW); 4197 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4198 link = 0; 4199 } 4200 } 4201 if (link) { 4202 /* Perform a reset if the media type changed. */ 4203 if (hw->dev_spec._82575.media_changed) { 4204 hw->dev_spec._82575.media_changed = false; 4205 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4206 igb_reset(adapter); 4207 } 4208 /* Cancel scheduled suspend requests. */ 4209 pm_runtime_resume(netdev->dev.parent); 4210 4211 if (!netif_carrier_ok(netdev)) { 4212 u32 ctrl; 4213 4214 hw->mac.ops.get_speed_and_duplex(hw, 4215 &adapter->link_speed, 4216 &adapter->link_duplex); 4217 4218 ctrl = rd32(E1000_CTRL); 4219 /* Links status message must follow this format */ 4220 netdev_info(netdev, 4221 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4222 netdev->name, 4223 adapter->link_speed, 4224 adapter->link_duplex == FULL_DUPLEX ? 4225 "Full" : "Half", 4226 (ctrl & E1000_CTRL_TFCE) && 4227 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4228 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4229 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4230 4231 /* disable EEE if enabled */ 4232 if ((adapter->flags & IGB_FLAG_EEE) && 4233 (adapter->link_duplex == HALF_DUPLEX)) { 4234 dev_info(&adapter->pdev->dev, 4235 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4236 adapter->hw.dev_spec._82575.eee_disable = true; 4237 adapter->flags &= ~IGB_FLAG_EEE; 4238 } 4239 4240 /* check if SmartSpeed worked */ 4241 igb_check_downshift(hw); 4242 if (phy->speed_downgraded) 4243 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4244 4245 /* check for thermal sensor event */ 4246 if (igb_thermal_sensor_event(hw, 4247 E1000_THSTAT_LINK_THROTTLE)) 4248 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 4249 4250 /* adjust timeout factor according to speed/duplex */ 4251 adapter->tx_timeout_factor = 1; 4252 switch (adapter->link_speed) { 4253 case SPEED_10: 4254 adapter->tx_timeout_factor = 14; 4255 break; 4256 case SPEED_100: 4257 /* maybe add some timeout factor ? */ 4258 break; 4259 } 4260 4261 netif_carrier_on(netdev); 4262 4263 igb_ping_all_vfs(adapter); 4264 igb_check_vf_rate_limit(adapter); 4265 4266 /* link state has changed, schedule phy info update */ 4267 if (!test_bit(__IGB_DOWN, &adapter->state)) 4268 mod_timer(&adapter->phy_info_timer, 4269 round_jiffies(jiffies + 2 * HZ)); 4270 } 4271 } else { 4272 if (netif_carrier_ok(netdev)) { 4273 adapter->link_speed = 0; 4274 adapter->link_duplex = 0; 4275 4276 /* check for thermal sensor event */ 4277 if (igb_thermal_sensor_event(hw, 4278 E1000_THSTAT_PWR_DOWN)) { 4279 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 4280 } 4281 4282 /* Links status message must follow this format */ 4283 netdev_info(netdev, "igb: %s NIC Link is Down\n", 4284 netdev->name); 4285 netif_carrier_off(netdev); 4286 4287 igb_ping_all_vfs(adapter); 4288 4289 /* link state has changed, schedule phy info update */ 4290 if (!test_bit(__IGB_DOWN, &adapter->state)) 4291 mod_timer(&adapter->phy_info_timer, 4292 round_jiffies(jiffies + 2 * HZ)); 4293 4294 /* link is down, time to check for alternate media */ 4295 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4296 igb_check_swap_media(adapter); 4297 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4298 schedule_work(&adapter->reset_task); 4299 /* return immediately */ 4300 return; 4301 } 4302 } 4303 pm_schedule_suspend(netdev->dev.parent, 4304 MSEC_PER_SEC * 5); 4305 4306 /* also check for alternate media here */ 4307 } else if (!netif_carrier_ok(netdev) && 4308 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4309 igb_check_swap_media(adapter); 4310 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4311 schedule_work(&adapter->reset_task); 4312 /* return immediately */ 4313 return; 4314 } 4315 } 4316 } 4317 4318 spin_lock(&adapter->stats64_lock); 4319 igb_update_stats(adapter, &adapter->stats64); 4320 spin_unlock(&adapter->stats64_lock); 4321 4322 for (i = 0; i < adapter->num_tx_queues; i++) { 4323 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4324 if (!netif_carrier_ok(netdev)) { 4325 /* We've lost link, so the controller stops DMA, 4326 * but we've got queued Tx work that's never going 4327 * to get done, so reset controller to flush Tx. 4328 * (Do the reset outside of interrupt context). 4329 */ 4330 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4331 adapter->tx_timeout_count++; 4332 schedule_work(&adapter->reset_task); 4333 /* return immediately since reset is imminent */ 4334 return; 4335 } 4336 } 4337 4338 /* Force detection of hung controller every watchdog period */ 4339 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4340 } 4341 4342 /* Cause software interrupt to ensure Rx ring is cleaned */ 4343 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4344 u32 eics = 0; 4345 4346 for (i = 0; i < adapter->num_q_vectors; i++) 4347 eics |= adapter->q_vector[i]->eims_value; 4348 wr32(E1000_EICS, eics); 4349 } else { 4350 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4351 } 4352 4353 igb_spoof_check(adapter); 4354 igb_ptp_rx_hang(adapter); 4355 4356 /* Reset the timer */ 4357 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4358 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4359 mod_timer(&adapter->watchdog_timer, 4360 round_jiffies(jiffies + HZ)); 4361 else 4362 mod_timer(&adapter->watchdog_timer, 4363 round_jiffies(jiffies + 2 * HZ)); 4364 } 4365} 4366 4367enum latency_range { 4368 lowest_latency = 0, 4369 low_latency = 1, 4370 bulk_latency = 2, 4371 latency_invalid = 255 4372}; 4373 4374/** 4375 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4376 * @q_vector: pointer to q_vector 4377 * 4378 * Stores a new ITR value based on strictly on packet size. This 4379 * algorithm is less sophisticated than that used in igb_update_itr, 4380 * due to the difficulty of synchronizing statistics across multiple 4381 * receive rings. The divisors and thresholds used by this function 4382 * were determined based on theoretical maximum wire speed and testing 4383 * data, in order to minimize response time while increasing bulk 4384 * throughput. 4385 * This functionality is controlled by ethtool's coalescing settings. 4386 * NOTE: This function is called only when operating in a multiqueue 4387 * receive environment. 4388 **/ 4389static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4390{ 4391 int new_val = q_vector->itr_val; 4392 int avg_wire_size = 0; 4393 struct igb_adapter *adapter = q_vector->adapter; 4394 unsigned int packets; 4395 4396 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4397 * ints/sec - ITR timer value of 120 ticks. 4398 */ 4399 if (adapter->link_speed != SPEED_1000) { 4400 new_val = IGB_4K_ITR; 4401 goto set_itr_val; 4402 } 4403 4404 packets = q_vector->rx.total_packets; 4405 if (packets) 4406 avg_wire_size = q_vector->rx.total_bytes / packets; 4407 4408 packets = q_vector->tx.total_packets; 4409 if (packets) 4410 avg_wire_size = max_t(u32, avg_wire_size, 4411 q_vector->tx.total_bytes / packets); 4412 4413 /* if avg_wire_size isn't set no work was done */ 4414 if (!avg_wire_size) 4415 goto clear_counts; 4416 4417 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4418 avg_wire_size += 24; 4419 4420 /* Don't starve jumbo frames */ 4421 avg_wire_size = min(avg_wire_size, 3000); 4422 4423 /* Give a little boost to mid-size frames */ 4424 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4425 new_val = avg_wire_size / 3; 4426 else 4427 new_val = avg_wire_size / 2; 4428 4429 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4430 if (new_val < IGB_20K_ITR && 4431 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4432 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4433 new_val = IGB_20K_ITR; 4434 4435set_itr_val: 4436 if (new_val != q_vector->itr_val) { 4437 q_vector->itr_val = new_val; 4438 q_vector->set_itr = 1; 4439 } 4440clear_counts: 4441 q_vector->rx.total_bytes = 0; 4442 q_vector->rx.total_packets = 0; 4443 q_vector->tx.total_bytes = 0; 4444 q_vector->tx.total_packets = 0; 4445} 4446 4447/** 4448 * igb_update_itr - update the dynamic ITR value based on statistics 4449 * @q_vector: pointer to q_vector 4450 * @ring_container: ring info to update the itr for 4451 * 4452 * Stores a new ITR value based on packets and byte 4453 * counts during the last interrupt. The advantage of per interrupt 4454 * computation is faster updates and more accurate ITR for the current 4455 * traffic pattern. Constants in this function were computed 4456 * based on theoretical maximum wire speed and thresholds were set based 4457 * on testing data as well as attempting to minimize response time 4458 * while increasing bulk throughput. 4459 * This functionality is controlled by ethtool's coalescing settings. 4460 * NOTE: These calculations are only valid when operating in a single- 4461 * queue environment. 4462 **/ 4463static void igb_update_itr(struct igb_q_vector *q_vector, 4464 struct igb_ring_container *ring_container) 4465{ 4466 unsigned int packets = ring_container->total_packets; 4467 unsigned int bytes = ring_container->total_bytes; 4468 u8 itrval = ring_container->itr; 4469 4470 /* no packets, exit with status unchanged */ 4471 if (packets == 0) 4472 return; 4473 4474 switch (itrval) { 4475 case lowest_latency: 4476 /* handle TSO and jumbo frames */ 4477 if (bytes/packets > 8000) 4478 itrval = bulk_latency; 4479 else if ((packets < 5) && (bytes > 512)) 4480 itrval = low_latency; 4481 break; 4482 case low_latency: /* 50 usec aka 20000 ints/s */ 4483 if (bytes > 10000) { 4484 /* this if handles the TSO accounting */ 4485 if (bytes/packets > 8000) 4486 itrval = bulk_latency; 4487 else if ((packets < 10) || ((bytes/packets) > 1200)) 4488 itrval = bulk_latency; 4489 else if ((packets > 35)) 4490 itrval = lowest_latency; 4491 } else if (bytes/packets > 2000) { 4492 itrval = bulk_latency; 4493 } else if (packets <= 2 && bytes < 512) { 4494 itrval = lowest_latency; 4495 } 4496 break; 4497 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4498 if (bytes > 25000) { 4499 if (packets > 35) 4500 itrval = low_latency; 4501 } else if (bytes < 1500) { 4502 itrval = low_latency; 4503 } 4504 break; 4505 } 4506 4507 /* clear work counters since we have the values we need */ 4508 ring_container->total_bytes = 0; 4509 ring_container->total_packets = 0; 4510 4511 /* write updated itr to ring container */ 4512 ring_container->itr = itrval; 4513} 4514 4515static void igb_set_itr(struct igb_q_vector *q_vector) 4516{ 4517 struct igb_adapter *adapter = q_vector->adapter; 4518 u32 new_itr = q_vector->itr_val; 4519 u8 current_itr = 0; 4520 4521 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4522 if (adapter->link_speed != SPEED_1000) { 4523 current_itr = 0; 4524 new_itr = IGB_4K_ITR; 4525 goto set_itr_now; 4526 } 4527 4528 igb_update_itr(q_vector, &q_vector->tx); 4529 igb_update_itr(q_vector, &q_vector->rx); 4530 4531 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4532 4533 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4534 if (current_itr == lowest_latency && 4535 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4536 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4537 current_itr = low_latency; 4538 4539 switch (current_itr) { 4540 /* counts and packets in update_itr are dependent on these numbers */ 4541 case lowest_latency: 4542 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4543 break; 4544 case low_latency: 4545 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4546 break; 4547 case bulk_latency: 4548 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4549 break; 4550 default: 4551 break; 4552 } 4553 4554set_itr_now: 4555 if (new_itr != q_vector->itr_val) { 4556 /* this attempts to bias the interrupt rate towards Bulk 4557 * by adding intermediate steps when interrupt rate is 4558 * increasing 4559 */ 4560 new_itr = new_itr > q_vector->itr_val ? 4561 max((new_itr * q_vector->itr_val) / 4562 (new_itr + (q_vector->itr_val >> 2)), 4563 new_itr) : new_itr; 4564 /* Don't write the value here; it resets the adapter's 4565 * internal timer, and causes us to delay far longer than 4566 * we should between interrupts. Instead, we write the ITR 4567 * value at the beginning of the next interrupt so the timing 4568 * ends up being correct. 4569 */ 4570 q_vector->itr_val = new_itr; 4571 q_vector->set_itr = 1; 4572 } 4573} 4574 4575static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4576 u32 type_tucmd, u32 mss_l4len_idx) 4577{ 4578 struct e1000_adv_tx_context_desc *context_desc; 4579 u16 i = tx_ring->next_to_use; 4580 4581 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4582 4583 i++; 4584 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4585 4586 /* set bits to identify this as an advanced context descriptor */ 4587 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4588 4589 /* For 82575, context index must be unique per ring. */ 4590 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4591 mss_l4len_idx |= tx_ring->reg_idx << 4; 4592 4593 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4594 context_desc->seqnum_seed = 0; 4595 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4596 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4597} 4598 4599static int igb_tso(struct igb_ring *tx_ring, 4600 struct igb_tx_buffer *first, 4601 u8 *hdr_len) 4602{ 4603 struct sk_buff *skb = first->skb; 4604 u32 vlan_macip_lens, type_tucmd; 4605 u32 mss_l4len_idx, l4len; 4606 int err; 4607 4608 if (skb->ip_summed != CHECKSUM_PARTIAL) 4609 return 0; 4610 4611 if (!skb_is_gso(skb)) 4612 return 0; 4613 4614 err = skb_cow_head(skb, 0); 4615 if (err < 0) 4616 return err; 4617 4618 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4619 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4620 4621 if (first->protocol == htons(ETH_P_IP)) { 4622 struct iphdr *iph = ip_hdr(skb); 4623 iph->tot_len = 0; 4624 iph->check = 0; 4625 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4626 iph->daddr, 0, 4627 IPPROTO_TCP, 4628 0); 4629 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4630 first->tx_flags |= IGB_TX_FLAGS_TSO | 4631 IGB_TX_FLAGS_CSUM | 4632 IGB_TX_FLAGS_IPV4; 4633 } else if (skb_is_gso_v6(skb)) { 4634 ipv6_hdr(skb)->payload_len = 0; 4635 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4636 &ipv6_hdr(skb)->daddr, 4637 0, IPPROTO_TCP, 0); 4638 first->tx_flags |= IGB_TX_FLAGS_TSO | 4639 IGB_TX_FLAGS_CSUM; 4640 } 4641 4642 /* compute header lengths */ 4643 l4len = tcp_hdrlen(skb); 4644 *hdr_len = skb_transport_offset(skb) + l4len; 4645 4646 /* update gso size and bytecount with header size */ 4647 first->gso_segs = skb_shinfo(skb)->gso_segs; 4648 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4649 4650 /* MSS L4LEN IDX */ 4651 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4652 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4653 4654 /* VLAN MACLEN IPLEN */ 4655 vlan_macip_lens = skb_network_header_len(skb); 4656 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4657 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4658 4659 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4660 4661 return 1; 4662} 4663 4664static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4665{ 4666 struct sk_buff *skb = first->skb; 4667 u32 vlan_macip_lens = 0; 4668 u32 mss_l4len_idx = 0; 4669 u32 type_tucmd = 0; 4670 4671 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4672 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4673 return; 4674 } else { 4675 u8 l4_hdr = 0; 4676 4677 switch (first->protocol) { 4678 case htons(ETH_P_IP): 4679 vlan_macip_lens |= skb_network_header_len(skb); 4680 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4681 l4_hdr = ip_hdr(skb)->protocol; 4682 break; 4683 case htons(ETH_P_IPV6): 4684 vlan_macip_lens |= skb_network_header_len(skb); 4685 l4_hdr = ipv6_hdr(skb)->nexthdr; 4686 break; 4687 default: 4688 if (unlikely(net_ratelimit())) { 4689 dev_warn(tx_ring->dev, 4690 "partial checksum but proto=%x!\n", 4691 first->protocol); 4692 } 4693 break; 4694 } 4695 4696 switch (l4_hdr) { 4697 case IPPROTO_TCP: 4698 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4699 mss_l4len_idx = tcp_hdrlen(skb) << 4700 E1000_ADVTXD_L4LEN_SHIFT; 4701 break; 4702 case IPPROTO_SCTP: 4703 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4704 mss_l4len_idx = sizeof(struct sctphdr) << 4705 E1000_ADVTXD_L4LEN_SHIFT; 4706 break; 4707 case IPPROTO_UDP: 4708 mss_l4len_idx = sizeof(struct udphdr) << 4709 E1000_ADVTXD_L4LEN_SHIFT; 4710 break; 4711 default: 4712 if (unlikely(net_ratelimit())) { 4713 dev_warn(tx_ring->dev, 4714 "partial checksum but l4 proto=%x!\n", 4715 l4_hdr); 4716 } 4717 break; 4718 } 4719 4720 /* update TX checksum flag */ 4721 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4722 } 4723 4724 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4725 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4726 4727 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4728} 4729 4730#define IGB_SET_FLAG(_input, _flag, _result) \ 4731 ((_flag <= _result) ? \ 4732 ((u32)(_input & _flag) * (_result / _flag)) : \ 4733 ((u32)(_input & _flag) / (_flag / _result))) 4734 4735static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 4736{ 4737 /* set type for advanced descriptor with frame checksum insertion */ 4738 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 4739 E1000_ADVTXD_DCMD_DEXT | 4740 E1000_ADVTXD_DCMD_IFCS; 4741 4742 /* set HW vlan bit if vlan is present */ 4743 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 4744 (E1000_ADVTXD_DCMD_VLE)); 4745 4746 /* set segmentation bits for TSO */ 4747 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 4748 (E1000_ADVTXD_DCMD_TSE)); 4749 4750 /* set timestamp bit if present */ 4751 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 4752 (E1000_ADVTXD_MAC_TSTAMP)); 4753 4754 /* insert frame checksum */ 4755 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 4756 4757 return cmd_type; 4758} 4759 4760static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4761 union e1000_adv_tx_desc *tx_desc, 4762 u32 tx_flags, unsigned int paylen) 4763{ 4764 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4765 4766 /* 82575 requires a unique index per ring */ 4767 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4768 olinfo_status |= tx_ring->reg_idx << 4; 4769 4770 /* insert L4 checksum */ 4771 olinfo_status |= IGB_SET_FLAG(tx_flags, 4772 IGB_TX_FLAGS_CSUM, 4773 (E1000_TXD_POPTS_TXSM << 8)); 4774 4775 /* insert IPv4 checksum */ 4776 olinfo_status |= IGB_SET_FLAG(tx_flags, 4777 IGB_TX_FLAGS_IPV4, 4778 (E1000_TXD_POPTS_IXSM << 8)); 4779 4780 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4781} 4782 4783static void igb_tx_map(struct igb_ring *tx_ring, 4784 struct igb_tx_buffer *first, 4785 const u8 hdr_len) 4786{ 4787 struct sk_buff *skb = first->skb; 4788 struct igb_tx_buffer *tx_buffer; 4789 union e1000_adv_tx_desc *tx_desc; 4790 struct skb_frag_struct *frag; 4791 dma_addr_t dma; 4792 unsigned int data_len, size; 4793 u32 tx_flags = first->tx_flags; 4794 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 4795 u16 i = tx_ring->next_to_use; 4796 4797 tx_desc = IGB_TX_DESC(tx_ring, i); 4798 4799 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 4800 4801 size = skb_headlen(skb); 4802 data_len = skb->data_len; 4803 4804 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4805 4806 tx_buffer = first; 4807 4808 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 4809 if (dma_mapping_error(tx_ring->dev, dma)) 4810 goto dma_error; 4811 4812 /* record length, and DMA address */ 4813 dma_unmap_len_set(tx_buffer, len, size); 4814 dma_unmap_addr_set(tx_buffer, dma, dma); 4815 4816 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4817 4818 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4819 tx_desc->read.cmd_type_len = 4820 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 4821 4822 i++; 4823 tx_desc++; 4824 if (i == tx_ring->count) { 4825 tx_desc = IGB_TX_DESC(tx_ring, 0); 4826 i = 0; 4827 } 4828 tx_desc->read.olinfo_status = 0; 4829 4830 dma += IGB_MAX_DATA_PER_TXD; 4831 size -= IGB_MAX_DATA_PER_TXD; 4832 4833 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4834 } 4835 4836 if (likely(!data_len)) 4837 break; 4838 4839 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 4840 4841 i++; 4842 tx_desc++; 4843 if (i == tx_ring->count) { 4844 tx_desc = IGB_TX_DESC(tx_ring, 0); 4845 i = 0; 4846 } 4847 tx_desc->read.olinfo_status = 0; 4848 4849 size = skb_frag_size(frag); 4850 data_len -= size; 4851 4852 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4853 size, DMA_TO_DEVICE); 4854 4855 tx_buffer = &tx_ring->tx_buffer_info[i]; 4856 } 4857 4858 /* write last descriptor with RS and EOP bits */ 4859 cmd_type |= size | IGB_TXD_DCMD; 4860 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 4861 4862 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4863 4864 /* set the timestamp */ 4865 first->time_stamp = jiffies; 4866 4867 /* Force memory writes to complete before letting h/w know there 4868 * are new descriptors to fetch. (Only applicable for weak-ordered 4869 * memory model archs, such as IA-64). 4870 * 4871 * We also need this memory barrier to make certain all of the 4872 * status bits have been updated before next_to_watch is written. 4873 */ 4874 wmb(); 4875 4876 /* set next_to_watch value indicating a packet is present */ 4877 first->next_to_watch = tx_desc; 4878 4879 i++; 4880 if (i == tx_ring->count) 4881 i = 0; 4882 4883 tx_ring->next_to_use = i; 4884 4885 writel(i, tx_ring->tail); 4886 4887 /* we need this if more than one processor can write to our tail 4888 * at a time, it synchronizes IO on IA64/Altix systems 4889 */ 4890 mmiowb(); 4891 4892 return; 4893 4894dma_error: 4895 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4896 4897 /* clear dma mappings for failed tx_buffer_info map */ 4898 for (;;) { 4899 tx_buffer = &tx_ring->tx_buffer_info[i]; 4900 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4901 if (tx_buffer == first) 4902 break; 4903 if (i == 0) 4904 i = tx_ring->count; 4905 i--; 4906 } 4907 4908 tx_ring->next_to_use = i; 4909} 4910 4911static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4912{ 4913 struct net_device *netdev = tx_ring->netdev; 4914 4915 netif_stop_subqueue(netdev, tx_ring->queue_index); 4916 4917 /* Herbert's original patch had: 4918 * smp_mb__after_netif_stop_queue(); 4919 * but since that doesn't exist yet, just open code it. 4920 */ 4921 smp_mb(); 4922 4923 /* We need to check again in a case another CPU has just 4924 * made room available. 4925 */ 4926 if (igb_desc_unused(tx_ring) < size) 4927 return -EBUSY; 4928 4929 /* A reprieve! */ 4930 netif_wake_subqueue(netdev, tx_ring->queue_index); 4931 4932 u64_stats_update_begin(&tx_ring->tx_syncp2); 4933 tx_ring->tx_stats.restart_queue2++; 4934 u64_stats_update_end(&tx_ring->tx_syncp2); 4935 4936 return 0; 4937} 4938 4939static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4940{ 4941 if (igb_desc_unused(tx_ring) >= size) 4942 return 0; 4943 return __igb_maybe_stop_tx(tx_ring, size); 4944} 4945 4946netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4947 struct igb_ring *tx_ring) 4948{ 4949 struct igb_tx_buffer *first; 4950 int tso; 4951 u32 tx_flags = 0; 4952 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 4953 __be16 protocol = vlan_get_protocol(skb); 4954 u8 hdr_len = 0; 4955 4956 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 4957 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 4958 * + 2 desc gap to keep tail from touching head, 4959 * + 1 desc for context descriptor, 4960 * otherwise try next time 4961 */ 4962 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) { 4963 unsigned short f; 4964 4965 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 4966 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 4967 } else { 4968 count += skb_shinfo(skb)->nr_frags; 4969 } 4970 4971 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 4972 /* this is a hard error */ 4973 return NETDEV_TX_BUSY; 4974 } 4975 4976 /* record the location of the first descriptor for this packet */ 4977 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 4978 first->skb = skb; 4979 first->bytecount = skb->len; 4980 first->gso_segs = 1; 4981 4982 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 4983 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 4984 4985 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 4986 &adapter->state)) { 4987 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4988 tx_flags |= IGB_TX_FLAGS_TSTAMP; 4989 4990 adapter->ptp_tx_skb = skb_get(skb); 4991 adapter->ptp_tx_start = jiffies; 4992 if (adapter->hw.mac.type == e1000_82576) 4993 schedule_work(&adapter->ptp_tx_work); 4994 } 4995 } 4996 4997 skb_tx_timestamp(skb); 4998 4999 if (vlan_tx_tag_present(skb)) { 5000 tx_flags |= IGB_TX_FLAGS_VLAN; 5001 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 5002 } 5003 5004 /* record initial flags and protocol */ 5005 first->tx_flags = tx_flags; 5006 first->protocol = protocol; 5007 5008 tso = igb_tso(tx_ring, first, &hdr_len); 5009 if (tso < 0) 5010 goto out_drop; 5011 else if (!tso) 5012 igb_tx_csum(tx_ring, first); 5013 5014 igb_tx_map(tx_ring, first, hdr_len); 5015 5016 /* Make sure there is space in the ring for the next send. */ 5017 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 5018 5019 return NETDEV_TX_OK; 5020 5021out_drop: 5022 igb_unmap_and_free_tx_resource(tx_ring, first); 5023 5024 return NETDEV_TX_OK; 5025} 5026 5027static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5028 struct sk_buff *skb) 5029{ 5030 unsigned int r_idx = skb->queue_mapping; 5031 5032 if (r_idx >= adapter->num_tx_queues) 5033 r_idx = r_idx % adapter->num_tx_queues; 5034 5035 return adapter->tx_ring[r_idx]; 5036} 5037 5038static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5039 struct net_device *netdev) 5040{ 5041 struct igb_adapter *adapter = netdev_priv(netdev); 5042 5043 if (test_bit(__IGB_DOWN, &adapter->state)) { 5044 dev_kfree_skb_any(skb); 5045 return NETDEV_TX_OK; 5046 } 5047 5048 if (skb->len <= 0) { 5049 dev_kfree_skb_any(skb); 5050 return NETDEV_TX_OK; 5051 } 5052 5053 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5054 * in order to meet this minimum size requirement. 5055 */ 5056 if (unlikely(skb->len < 17)) { 5057 if (skb_pad(skb, 17 - skb->len)) 5058 return NETDEV_TX_OK; 5059 skb->len = 17; 5060 skb_set_tail_pointer(skb, 17); 5061 } 5062 5063 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5064} 5065 5066/** 5067 * igb_tx_timeout - Respond to a Tx Hang 5068 * @netdev: network interface device structure 5069 **/ 5070static void igb_tx_timeout(struct net_device *netdev) 5071{ 5072 struct igb_adapter *adapter = netdev_priv(netdev); 5073 struct e1000_hw *hw = &adapter->hw; 5074 5075 /* Do the reset outside of interrupt context */ 5076 adapter->tx_timeout_count++; 5077 5078 if (hw->mac.type >= e1000_82580) 5079 hw->dev_spec._82575.global_device_reset = true; 5080 5081 schedule_work(&adapter->reset_task); 5082 wr32(E1000_EICS, 5083 (adapter->eims_enable_mask & ~adapter->eims_other)); 5084} 5085 5086static void igb_reset_task(struct work_struct *work) 5087{ 5088 struct igb_adapter *adapter; 5089 adapter = container_of(work, struct igb_adapter, reset_task); 5090 5091 igb_dump(adapter); 5092 netdev_err(adapter->netdev, "Reset adapter\n"); 5093 igb_reinit_locked(adapter); 5094} 5095 5096/** 5097 * igb_get_stats64 - Get System Network Statistics 5098 * @netdev: network interface device structure 5099 * @stats: rtnl_link_stats64 pointer 5100 **/ 5101static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 5102 struct rtnl_link_stats64 *stats) 5103{ 5104 struct igb_adapter *adapter = netdev_priv(netdev); 5105 5106 spin_lock(&adapter->stats64_lock); 5107 igb_update_stats(adapter, &adapter->stats64); 5108 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5109 spin_unlock(&adapter->stats64_lock); 5110 5111 return stats; 5112} 5113 5114/** 5115 * igb_change_mtu - Change the Maximum Transfer Unit 5116 * @netdev: network interface device structure 5117 * @new_mtu: new value for maximum frame size 5118 * 5119 * Returns 0 on success, negative on failure 5120 **/ 5121static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5122{ 5123 struct igb_adapter *adapter = netdev_priv(netdev); 5124 struct pci_dev *pdev = adapter->pdev; 5125 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5126 5127 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 5128 dev_err(&pdev->dev, "Invalid MTU setting\n"); 5129 return -EINVAL; 5130 } 5131 5132#define MAX_STD_JUMBO_FRAME_SIZE 9238 5133 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 5134 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 5135 return -EINVAL; 5136 } 5137 5138 /* adjust max frame to be at least the size of a standard frame */ 5139 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5140 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5141 5142 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5143 msleep(1); 5144 5145 /* igb_down has a dependency on max_frame_size */ 5146 adapter->max_frame_size = max_frame; 5147 5148 if (netif_running(netdev)) 5149 igb_down(adapter); 5150 5151 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5152 netdev->mtu, new_mtu); 5153 netdev->mtu = new_mtu; 5154 5155 if (netif_running(netdev)) 5156 igb_up(adapter); 5157 else 5158 igb_reset(adapter); 5159 5160 clear_bit(__IGB_RESETTING, &adapter->state); 5161 5162 return 0; 5163} 5164 5165/** 5166 * igb_update_stats - Update the board statistics counters 5167 * @adapter: board private structure 5168 **/ 5169void igb_update_stats(struct igb_adapter *adapter, 5170 struct rtnl_link_stats64 *net_stats) 5171{ 5172 struct e1000_hw *hw = &adapter->hw; 5173 struct pci_dev *pdev = adapter->pdev; 5174 u32 reg, mpc; 5175 u16 phy_tmp; 5176 int i; 5177 u64 bytes, packets; 5178 unsigned int start; 5179 u64 _bytes, _packets; 5180 5181#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF 5182 5183 /* Prevent stats update while adapter is being reset, or if the pci 5184 * connection is down. 5185 */ 5186 if (adapter->link_speed == 0) 5187 return; 5188 if (pci_channel_offline(pdev)) 5189 return; 5190 5191 bytes = 0; 5192 packets = 0; 5193 5194 rcu_read_lock(); 5195 for (i = 0; i < adapter->num_rx_queues; i++) { 5196 u32 rqdpc = rd32(E1000_RQDPC(i)); 5197 struct igb_ring *ring = adapter->rx_ring[i]; 5198 5199 if (rqdpc) { 5200 ring->rx_stats.drops += rqdpc; 5201 net_stats->rx_fifo_errors += rqdpc; 5202 } 5203 5204 do { 5205 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5206 _bytes = ring->rx_stats.bytes; 5207 _packets = ring->rx_stats.packets; 5208 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5209 bytes += _bytes; 5210 packets += _packets; 5211 } 5212 5213 net_stats->rx_bytes = bytes; 5214 net_stats->rx_packets = packets; 5215 5216 bytes = 0; 5217 packets = 0; 5218 for (i = 0; i < adapter->num_tx_queues; i++) { 5219 struct igb_ring *ring = adapter->tx_ring[i]; 5220 do { 5221 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5222 _bytes = ring->tx_stats.bytes; 5223 _packets = ring->tx_stats.packets; 5224 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5225 bytes += _bytes; 5226 packets += _packets; 5227 } 5228 net_stats->tx_bytes = bytes; 5229 net_stats->tx_packets = packets; 5230 rcu_read_unlock(); 5231 5232 /* read stats registers */ 5233 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5234 adapter->stats.gprc += rd32(E1000_GPRC); 5235 adapter->stats.gorc += rd32(E1000_GORCL); 5236 rd32(E1000_GORCH); /* clear GORCL */ 5237 adapter->stats.bprc += rd32(E1000_BPRC); 5238 adapter->stats.mprc += rd32(E1000_MPRC); 5239 adapter->stats.roc += rd32(E1000_ROC); 5240 5241 adapter->stats.prc64 += rd32(E1000_PRC64); 5242 adapter->stats.prc127 += rd32(E1000_PRC127); 5243 adapter->stats.prc255 += rd32(E1000_PRC255); 5244 adapter->stats.prc511 += rd32(E1000_PRC511); 5245 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5246 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5247 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5248 adapter->stats.sec += rd32(E1000_SEC); 5249 5250 mpc = rd32(E1000_MPC); 5251 adapter->stats.mpc += mpc; 5252 net_stats->rx_fifo_errors += mpc; 5253 adapter->stats.scc += rd32(E1000_SCC); 5254 adapter->stats.ecol += rd32(E1000_ECOL); 5255 adapter->stats.mcc += rd32(E1000_MCC); 5256 adapter->stats.latecol += rd32(E1000_LATECOL); 5257 adapter->stats.dc += rd32(E1000_DC); 5258 adapter->stats.rlec += rd32(E1000_RLEC); 5259 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5260 adapter->stats.xontxc += rd32(E1000_XONTXC); 5261 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5262 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5263 adapter->stats.fcruc += rd32(E1000_FCRUC); 5264 adapter->stats.gptc += rd32(E1000_GPTC); 5265 adapter->stats.gotc += rd32(E1000_GOTCL); 5266 rd32(E1000_GOTCH); /* clear GOTCL */ 5267 adapter->stats.rnbc += rd32(E1000_RNBC); 5268 adapter->stats.ruc += rd32(E1000_RUC); 5269 adapter->stats.rfc += rd32(E1000_RFC); 5270 adapter->stats.rjc += rd32(E1000_RJC); 5271 adapter->stats.tor += rd32(E1000_TORH); 5272 adapter->stats.tot += rd32(E1000_TOTH); 5273 adapter->stats.tpr += rd32(E1000_TPR); 5274 5275 adapter->stats.ptc64 += rd32(E1000_PTC64); 5276 adapter->stats.ptc127 += rd32(E1000_PTC127); 5277 adapter->stats.ptc255 += rd32(E1000_PTC255); 5278 adapter->stats.ptc511 += rd32(E1000_PTC511); 5279 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5280 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5281 5282 adapter->stats.mptc += rd32(E1000_MPTC); 5283 adapter->stats.bptc += rd32(E1000_BPTC); 5284 5285 adapter->stats.tpt += rd32(E1000_TPT); 5286 adapter->stats.colc += rd32(E1000_COLC); 5287 5288 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5289 /* read internal phy specific stats */ 5290 reg = rd32(E1000_CTRL_EXT); 5291 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5292 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5293 5294 /* this stat has invalid values on i210/i211 */ 5295 if ((hw->mac.type != e1000_i210) && 5296 (hw->mac.type != e1000_i211)) 5297 adapter->stats.tncrs += rd32(E1000_TNCRS); 5298 } 5299 5300 adapter->stats.tsctc += rd32(E1000_TSCTC); 5301 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5302 5303 adapter->stats.iac += rd32(E1000_IAC); 5304 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5305 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5306 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5307 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5308 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5309 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5310 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5311 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5312 5313 /* Fill out the OS statistics structure */ 5314 net_stats->multicast = adapter->stats.mprc; 5315 net_stats->collisions = adapter->stats.colc; 5316 5317 /* Rx Errors */ 5318 5319 /* RLEC on some newer hardware can be incorrect so build 5320 * our own version based on RUC and ROC 5321 */ 5322 net_stats->rx_errors = adapter->stats.rxerrc + 5323 adapter->stats.crcerrs + adapter->stats.algnerrc + 5324 adapter->stats.ruc + adapter->stats.roc + 5325 adapter->stats.cexterr; 5326 net_stats->rx_length_errors = adapter->stats.ruc + 5327 adapter->stats.roc; 5328 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5329 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5330 net_stats->rx_missed_errors = adapter->stats.mpc; 5331 5332 /* Tx Errors */ 5333 net_stats->tx_errors = adapter->stats.ecol + 5334 adapter->stats.latecol; 5335 net_stats->tx_aborted_errors = adapter->stats.ecol; 5336 net_stats->tx_window_errors = adapter->stats.latecol; 5337 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5338 5339 /* Tx Dropped needs to be maintained elsewhere */ 5340 5341 /* Phy Stats */ 5342 if (hw->phy.media_type == e1000_media_type_copper) { 5343 if ((adapter->link_speed == SPEED_1000) && 5344 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 5345 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; 5346 adapter->phy_stats.idle_errors += phy_tmp; 5347 } 5348 } 5349 5350 /* Management Stats */ 5351 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5352 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5353 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5354 5355 /* OS2BMC Stats */ 5356 reg = rd32(E1000_MANC); 5357 if (reg & E1000_MANC_EN_BMC2OS) { 5358 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5359 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5360 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5361 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5362 } 5363} 5364 5365static irqreturn_t igb_msix_other(int irq, void *data) 5366{ 5367 struct igb_adapter *adapter = data; 5368 struct e1000_hw *hw = &adapter->hw; 5369 u32 icr = rd32(E1000_ICR); 5370 /* reading ICR causes bit 31 of EICR to be cleared */ 5371 5372 if (icr & E1000_ICR_DRSTA) 5373 schedule_work(&adapter->reset_task); 5374 5375 if (icr & E1000_ICR_DOUTSYNC) { 5376 /* HW is reporting DMA is out of sync */ 5377 adapter->stats.doosync++; 5378 /* The DMA Out of Sync is also indication of a spoof event 5379 * in IOV mode. Check the Wrong VM Behavior register to 5380 * see if it is really a spoof event. 5381 */ 5382 igb_check_wvbr(adapter); 5383 } 5384 5385 /* Check for a mailbox event */ 5386 if (icr & E1000_ICR_VMMB) 5387 igb_msg_task(adapter); 5388 5389 if (icr & E1000_ICR_LSC) { 5390 hw->mac.get_link_status = 1; 5391 /* guard against interrupt when we're going down */ 5392 if (!test_bit(__IGB_DOWN, &adapter->state)) 5393 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5394 } 5395 5396 if (icr & E1000_ICR_TS) { 5397 u32 tsicr = rd32(E1000_TSICR); 5398 5399 if (tsicr & E1000_TSICR_TXTS) { 5400 /* acknowledge the interrupt */ 5401 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5402 /* retrieve hardware timestamp */ 5403 schedule_work(&adapter->ptp_tx_work); 5404 } 5405 } 5406 5407 wr32(E1000_EIMS, adapter->eims_other); 5408 5409 return IRQ_HANDLED; 5410} 5411 5412static void igb_write_itr(struct igb_q_vector *q_vector) 5413{ 5414 struct igb_adapter *adapter = q_vector->adapter; 5415 u32 itr_val = q_vector->itr_val & 0x7FFC; 5416 5417 if (!q_vector->set_itr) 5418 return; 5419 5420 if (!itr_val) 5421 itr_val = 0x4; 5422 5423 if (adapter->hw.mac.type == e1000_82575) 5424 itr_val |= itr_val << 16; 5425 else 5426 itr_val |= E1000_EITR_CNT_IGNR; 5427 5428 writel(itr_val, q_vector->itr_register); 5429 q_vector->set_itr = 0; 5430} 5431 5432static irqreturn_t igb_msix_ring(int irq, void *data) 5433{ 5434 struct igb_q_vector *q_vector = data; 5435 5436 /* Write the ITR value calculated from the previous interrupt. */ 5437 igb_write_itr(q_vector); 5438 5439 napi_schedule(&q_vector->napi); 5440 5441 return IRQ_HANDLED; 5442} 5443 5444#ifdef CONFIG_IGB_DCA 5445static void igb_update_tx_dca(struct igb_adapter *adapter, 5446 struct igb_ring *tx_ring, 5447 int cpu) 5448{ 5449 struct e1000_hw *hw = &adapter->hw; 5450 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5451 5452 if (hw->mac.type != e1000_82575) 5453 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5454 5455 /* We can enable relaxed ordering for reads, but not writes when 5456 * DCA is enabled. This is due to a known issue in some chipsets 5457 * which will cause the DCA tag to be cleared. 5458 */ 5459 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5460 E1000_DCA_TXCTRL_DATA_RRO_EN | 5461 E1000_DCA_TXCTRL_DESC_DCA_EN; 5462 5463 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5464} 5465 5466static void igb_update_rx_dca(struct igb_adapter *adapter, 5467 struct igb_ring *rx_ring, 5468 int cpu) 5469{ 5470 struct e1000_hw *hw = &adapter->hw; 5471 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5472 5473 if (hw->mac.type != e1000_82575) 5474 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5475 5476 /* We can enable relaxed ordering for reads, but not writes when 5477 * DCA is enabled. This is due to a known issue in some chipsets 5478 * which will cause the DCA tag to be cleared. 5479 */ 5480 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5481 E1000_DCA_RXCTRL_DESC_DCA_EN; 5482 5483 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5484} 5485 5486static void igb_update_dca(struct igb_q_vector *q_vector) 5487{ 5488 struct igb_adapter *adapter = q_vector->adapter; 5489 int cpu = get_cpu(); 5490 5491 if (q_vector->cpu == cpu) 5492 goto out_no_update; 5493 5494 if (q_vector->tx.ring) 5495 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5496 5497 if (q_vector->rx.ring) 5498 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5499 5500 q_vector->cpu = cpu; 5501out_no_update: 5502 put_cpu(); 5503} 5504 5505static void igb_setup_dca(struct igb_adapter *adapter) 5506{ 5507 struct e1000_hw *hw = &adapter->hw; 5508 int i; 5509 5510 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5511 return; 5512 5513 /* Always use CB2 mode, difference is masked in the CB driver. */ 5514 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5515 5516 for (i = 0; i < adapter->num_q_vectors; i++) { 5517 adapter->q_vector[i]->cpu = -1; 5518 igb_update_dca(adapter->q_vector[i]); 5519 } 5520} 5521 5522static int __igb_notify_dca(struct device *dev, void *data) 5523{ 5524 struct net_device *netdev = dev_get_drvdata(dev); 5525 struct igb_adapter *adapter = netdev_priv(netdev); 5526 struct pci_dev *pdev = adapter->pdev; 5527 struct e1000_hw *hw = &adapter->hw; 5528 unsigned long event = *(unsigned long *)data; 5529 5530 switch (event) { 5531 case DCA_PROVIDER_ADD: 5532 /* if already enabled, don't do it again */ 5533 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5534 break; 5535 if (dca_add_requester(dev) == 0) { 5536 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5537 dev_info(&pdev->dev, "DCA enabled\n"); 5538 igb_setup_dca(adapter); 5539 break; 5540 } 5541 /* Fall Through since DCA is disabled. */ 5542 case DCA_PROVIDER_REMOVE: 5543 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5544 /* without this a class_device is left 5545 * hanging around in the sysfs model 5546 */ 5547 dca_remove_requester(dev); 5548 dev_info(&pdev->dev, "DCA disabled\n"); 5549 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5550 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5551 } 5552 break; 5553 } 5554 5555 return 0; 5556} 5557 5558static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5559 void *p) 5560{ 5561 int ret_val; 5562 5563 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5564 __igb_notify_dca); 5565 5566 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5567} 5568#endif /* CONFIG_IGB_DCA */ 5569 5570#ifdef CONFIG_PCI_IOV 5571static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5572{ 5573 unsigned char mac_addr[ETH_ALEN]; 5574 5575 eth_zero_addr(mac_addr); 5576 igb_set_vf_mac(adapter, vf, mac_addr); 5577 5578 /* By default spoof check is enabled for all VFs */ 5579 adapter->vf_data[vf].spoofchk_enabled = true; 5580 5581 return 0; 5582} 5583 5584#endif 5585static void igb_ping_all_vfs(struct igb_adapter *adapter) 5586{ 5587 struct e1000_hw *hw = &adapter->hw; 5588 u32 ping; 5589 int i; 5590 5591 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5592 ping = E1000_PF_CONTROL_MSG; 5593 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5594 ping |= E1000_VT_MSGTYPE_CTS; 5595 igb_write_mbx(hw, &ping, 1, i); 5596 } 5597} 5598 5599static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5600{ 5601 struct e1000_hw *hw = &adapter->hw; 5602 u32 vmolr = rd32(E1000_VMOLR(vf)); 5603 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5604 5605 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5606 IGB_VF_FLAG_MULTI_PROMISC); 5607 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5608 5609 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5610 vmolr |= E1000_VMOLR_MPME; 5611 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5612 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5613 } else { 5614 /* if we have hashes and we are clearing a multicast promisc 5615 * flag we need to write the hashes to the MTA as this step 5616 * was previously skipped 5617 */ 5618 if (vf_data->num_vf_mc_hashes > 30) { 5619 vmolr |= E1000_VMOLR_MPME; 5620 } else if (vf_data->num_vf_mc_hashes) { 5621 int j; 5622 5623 vmolr |= E1000_VMOLR_ROMPE; 5624 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5625 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5626 } 5627 } 5628 5629 wr32(E1000_VMOLR(vf), vmolr); 5630 5631 /* there are flags left unprocessed, likely not supported */ 5632 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5633 return -EINVAL; 5634 5635 return 0; 5636} 5637 5638static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5639 u32 *msgbuf, u32 vf) 5640{ 5641 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5642 u16 *hash_list = (u16 *)&msgbuf[1]; 5643 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5644 int i; 5645 5646 /* salt away the number of multicast addresses assigned 5647 * to this VF for later use to restore when the PF multi cast 5648 * list changes 5649 */ 5650 vf_data->num_vf_mc_hashes = n; 5651 5652 /* only up to 30 hash values supported */ 5653 if (n > 30) 5654 n = 30; 5655 5656 /* store the hashes for later use */ 5657 for (i = 0; i < n; i++) 5658 vf_data->vf_mc_hashes[i] = hash_list[i]; 5659 5660 /* Flush and reset the mta with the new values */ 5661 igb_set_rx_mode(adapter->netdev); 5662 5663 return 0; 5664} 5665 5666static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5667{ 5668 struct e1000_hw *hw = &adapter->hw; 5669 struct vf_data_storage *vf_data; 5670 int i, j; 5671 5672 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5673 u32 vmolr = rd32(E1000_VMOLR(i)); 5674 5675 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5676 5677 vf_data = &adapter->vf_data[i]; 5678 5679 if ((vf_data->num_vf_mc_hashes > 30) || 5680 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5681 vmolr |= E1000_VMOLR_MPME; 5682 } else if (vf_data->num_vf_mc_hashes) { 5683 vmolr |= E1000_VMOLR_ROMPE; 5684 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5685 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5686 } 5687 wr32(E1000_VMOLR(i), vmolr); 5688 } 5689} 5690 5691static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5692{ 5693 struct e1000_hw *hw = &adapter->hw; 5694 u32 pool_mask, reg, vid; 5695 int i; 5696 5697 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5698 5699 /* Find the vlan filter for this id */ 5700 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5701 reg = rd32(E1000_VLVF(i)); 5702 5703 /* remove the vf from the pool */ 5704 reg &= ~pool_mask; 5705 5706 /* if pool is empty then remove entry from vfta */ 5707 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5708 (reg & E1000_VLVF_VLANID_ENABLE)) { 5709 reg = 0; 5710 vid = reg & E1000_VLVF_VLANID_MASK; 5711 igb_vfta_set(hw, vid, false); 5712 } 5713 5714 wr32(E1000_VLVF(i), reg); 5715 } 5716 5717 adapter->vf_data[vf].vlans_enabled = 0; 5718} 5719 5720static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5721{ 5722 struct e1000_hw *hw = &adapter->hw; 5723 u32 reg, i; 5724 5725 /* The vlvf table only exists on 82576 hardware and newer */ 5726 if (hw->mac.type < e1000_82576) 5727 return -1; 5728 5729 /* we only need to do this if VMDq is enabled */ 5730 if (!adapter->vfs_allocated_count) 5731 return -1; 5732 5733 /* Find the vlan filter for this id */ 5734 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5735 reg = rd32(E1000_VLVF(i)); 5736 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5737 vid == (reg & E1000_VLVF_VLANID_MASK)) 5738 break; 5739 } 5740 5741 if (add) { 5742 if (i == E1000_VLVF_ARRAY_SIZE) { 5743 /* Did not find a matching VLAN ID entry that was 5744 * enabled. Search for a free filter entry, i.e. 5745 * one without the enable bit set 5746 */ 5747 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5748 reg = rd32(E1000_VLVF(i)); 5749 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5750 break; 5751 } 5752 } 5753 if (i < E1000_VLVF_ARRAY_SIZE) { 5754 /* Found an enabled/available entry */ 5755 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5756 5757 /* if !enabled we need to set this up in vfta */ 5758 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5759 /* add VID to filter table */ 5760 igb_vfta_set(hw, vid, true); 5761 reg |= E1000_VLVF_VLANID_ENABLE; 5762 } 5763 reg &= ~E1000_VLVF_VLANID_MASK; 5764 reg |= vid; 5765 wr32(E1000_VLVF(i), reg); 5766 5767 /* do not modify RLPML for PF devices */ 5768 if (vf >= adapter->vfs_allocated_count) 5769 return 0; 5770 5771 if (!adapter->vf_data[vf].vlans_enabled) { 5772 u32 size; 5773 5774 reg = rd32(E1000_VMOLR(vf)); 5775 size = reg & E1000_VMOLR_RLPML_MASK; 5776 size += 4; 5777 reg &= ~E1000_VMOLR_RLPML_MASK; 5778 reg |= size; 5779 wr32(E1000_VMOLR(vf), reg); 5780 } 5781 5782 adapter->vf_data[vf].vlans_enabled++; 5783 } 5784 } else { 5785 if (i < E1000_VLVF_ARRAY_SIZE) { 5786 /* remove vf from the pool */ 5787 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5788 /* if pool is empty then remove entry from vfta */ 5789 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5790 reg = 0; 5791 igb_vfta_set(hw, vid, false); 5792 } 5793 wr32(E1000_VLVF(i), reg); 5794 5795 /* do not modify RLPML for PF devices */ 5796 if (vf >= adapter->vfs_allocated_count) 5797 return 0; 5798 5799 adapter->vf_data[vf].vlans_enabled--; 5800 if (!adapter->vf_data[vf].vlans_enabled) { 5801 u32 size; 5802 5803 reg = rd32(E1000_VMOLR(vf)); 5804 size = reg & E1000_VMOLR_RLPML_MASK; 5805 size -= 4; 5806 reg &= ~E1000_VMOLR_RLPML_MASK; 5807 reg |= size; 5808 wr32(E1000_VMOLR(vf), reg); 5809 } 5810 } 5811 } 5812 return 0; 5813} 5814 5815static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5816{ 5817 struct e1000_hw *hw = &adapter->hw; 5818 5819 if (vid) 5820 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5821 else 5822 wr32(E1000_VMVIR(vf), 0); 5823} 5824 5825static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5826 int vf, u16 vlan, u8 qos) 5827{ 5828 int err = 0; 5829 struct igb_adapter *adapter = netdev_priv(netdev); 5830 5831 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5832 return -EINVAL; 5833 if (vlan || qos) { 5834 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5835 if (err) 5836 goto out; 5837 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5838 igb_set_vmolr(adapter, vf, !vlan); 5839 adapter->vf_data[vf].pf_vlan = vlan; 5840 adapter->vf_data[vf].pf_qos = qos; 5841 dev_info(&adapter->pdev->dev, 5842 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5843 if (test_bit(__IGB_DOWN, &adapter->state)) { 5844 dev_warn(&adapter->pdev->dev, 5845 "The VF VLAN has been set, but the PF device is not up.\n"); 5846 dev_warn(&adapter->pdev->dev, 5847 "Bring the PF device up before attempting to use the VF device.\n"); 5848 } 5849 } else { 5850 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5851 false, vf); 5852 igb_set_vmvir(adapter, vlan, vf); 5853 igb_set_vmolr(adapter, vf, true); 5854 adapter->vf_data[vf].pf_vlan = 0; 5855 adapter->vf_data[vf].pf_qos = 0; 5856 } 5857out: 5858 return err; 5859} 5860 5861static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid) 5862{ 5863 struct e1000_hw *hw = &adapter->hw; 5864 int i; 5865 u32 reg; 5866 5867 /* Find the vlan filter for this id */ 5868 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5869 reg = rd32(E1000_VLVF(i)); 5870 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5871 vid == (reg & E1000_VLVF_VLANID_MASK)) 5872 break; 5873 } 5874 5875 if (i >= E1000_VLVF_ARRAY_SIZE) 5876 i = -1; 5877 5878 return i; 5879} 5880 5881static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5882{ 5883 struct e1000_hw *hw = &adapter->hw; 5884 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5885 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5886 int err = 0; 5887 5888 /* If in promiscuous mode we need to make sure the PF also has 5889 * the VLAN filter set. 5890 */ 5891 if (add && (adapter->netdev->flags & IFF_PROMISC)) 5892 err = igb_vlvf_set(adapter, vid, add, 5893 adapter->vfs_allocated_count); 5894 if (err) 5895 goto out; 5896 5897 err = igb_vlvf_set(adapter, vid, add, vf); 5898 5899 if (err) 5900 goto out; 5901 5902 /* Go through all the checks to see if the VLAN filter should 5903 * be wiped completely. 5904 */ 5905 if (!add && (adapter->netdev->flags & IFF_PROMISC)) { 5906 u32 vlvf, bits; 5907 int regndx = igb_find_vlvf_entry(adapter, vid); 5908 5909 if (regndx < 0) 5910 goto out; 5911 /* See if any other pools are set for this VLAN filter 5912 * entry other than the PF. 5913 */ 5914 vlvf = bits = rd32(E1000_VLVF(regndx)); 5915 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT + 5916 adapter->vfs_allocated_count); 5917 /* If the filter was removed then ensure PF pool bit 5918 * is cleared if the PF only added itself to the pool 5919 * because the PF is in promiscuous mode. 5920 */ 5921 if ((vlvf & VLAN_VID_MASK) == vid && 5922 !test_bit(vid, adapter->active_vlans) && 5923 !bits) 5924 igb_vlvf_set(adapter, vid, add, 5925 adapter->vfs_allocated_count); 5926 } 5927 5928out: 5929 return err; 5930} 5931 5932static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 5933{ 5934 /* clear flags - except flag that indicates PF has set the MAC */ 5935 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 5936 adapter->vf_data[vf].last_nack = jiffies; 5937 5938 /* reset offloads to defaults */ 5939 igb_set_vmolr(adapter, vf, true); 5940 5941 /* reset vlans for device */ 5942 igb_clear_vf_vfta(adapter, vf); 5943 if (adapter->vf_data[vf].pf_vlan) 5944 igb_ndo_set_vf_vlan(adapter->netdev, vf, 5945 adapter->vf_data[vf].pf_vlan, 5946 adapter->vf_data[vf].pf_qos); 5947 else 5948 igb_clear_vf_vfta(adapter, vf); 5949 5950 /* reset multicast table array for vf */ 5951 adapter->vf_data[vf].num_vf_mc_hashes = 0; 5952 5953 /* Flush and reset the mta with the new values */ 5954 igb_set_rx_mode(adapter->netdev); 5955} 5956 5957static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 5958{ 5959 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5960 5961 /* clear mac address as we were hotplug removed/added */ 5962 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 5963 eth_zero_addr(vf_mac); 5964 5965 /* process remaining reset events */ 5966 igb_vf_reset(adapter, vf); 5967} 5968 5969static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 5970{ 5971 struct e1000_hw *hw = &adapter->hw; 5972 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5973 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 5974 u32 reg, msgbuf[3]; 5975 u8 *addr = (u8 *)(&msgbuf[1]); 5976 5977 /* process all the same items cleared in a function level reset */ 5978 igb_vf_reset(adapter, vf); 5979 5980 /* set vf mac address */ 5981 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 5982 5983 /* enable transmit and receive for vf */ 5984 reg = rd32(E1000_VFTE); 5985 wr32(E1000_VFTE, reg | (1 << vf)); 5986 reg = rd32(E1000_VFRE); 5987 wr32(E1000_VFRE, reg | (1 << vf)); 5988 5989 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 5990 5991 /* reply to reset with ack and vf mac address */ 5992 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 5993 memcpy(addr, vf_mac, ETH_ALEN); 5994 igb_write_mbx(hw, msgbuf, 3, vf); 5995} 5996 5997static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 5998{ 5999 /* The VF MAC Address is stored in a packed array of bytes 6000 * starting at the second 32 bit word of the msg array 6001 */ 6002 unsigned char *addr = (char *)&msg[1]; 6003 int err = -1; 6004 6005 if (is_valid_ether_addr(addr)) 6006 err = igb_set_vf_mac(adapter, vf, addr); 6007 6008 return err; 6009} 6010 6011static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 6012{ 6013 struct e1000_hw *hw = &adapter->hw; 6014 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6015 u32 msg = E1000_VT_MSGTYPE_NACK; 6016 6017 /* if device isn't clear to send it shouldn't be reading either */ 6018 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6019 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6020 igb_write_mbx(hw, &msg, 1, vf); 6021 vf_data->last_nack = jiffies; 6022 } 6023} 6024 6025static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6026{ 6027 struct pci_dev *pdev = adapter->pdev; 6028 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6029 struct e1000_hw *hw = &adapter->hw; 6030 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6031 s32 retval; 6032 6033 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6034 6035 if (retval) { 6036 /* if receive failed revoke VF CTS stats and restart init */ 6037 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6038 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6039 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6040 return; 6041 goto out; 6042 } 6043 6044 /* this is a message we already processed, do nothing */ 6045 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6046 return; 6047 6048 /* until the vf completes a reset it should not be 6049 * allowed to start any configuration. 6050 */ 6051 if (msgbuf[0] == E1000_VF_RESET) { 6052 igb_vf_reset_msg(adapter, vf); 6053 return; 6054 } 6055 6056 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6057 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6058 return; 6059 retval = -1; 6060 goto out; 6061 } 6062 6063 switch ((msgbuf[0] & 0xFFFF)) { 6064 case E1000_VF_SET_MAC_ADDR: 6065 retval = -EINVAL; 6066 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 6067 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6068 else 6069 dev_warn(&pdev->dev, 6070 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6071 vf); 6072 break; 6073 case E1000_VF_SET_PROMISC: 6074 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6075 break; 6076 case E1000_VF_SET_MULTICAST: 6077 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6078 break; 6079 case E1000_VF_SET_LPE: 6080 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6081 break; 6082 case E1000_VF_SET_VLAN: 6083 retval = -1; 6084 if (vf_data->pf_vlan) 6085 dev_warn(&pdev->dev, 6086 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6087 vf); 6088 else 6089 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 6090 break; 6091 default: 6092 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6093 retval = -1; 6094 break; 6095 } 6096 6097 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6098out: 6099 /* notify the VF of the results of what it sent us */ 6100 if (retval) 6101 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6102 else 6103 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6104 6105 igb_write_mbx(hw, msgbuf, 1, vf); 6106} 6107 6108static void igb_msg_task(struct igb_adapter *adapter) 6109{ 6110 struct e1000_hw *hw = &adapter->hw; 6111 u32 vf; 6112 6113 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6114 /* process any reset requests */ 6115 if (!igb_check_for_rst(hw, vf)) 6116 igb_vf_reset_event(adapter, vf); 6117 6118 /* process any messages pending */ 6119 if (!igb_check_for_msg(hw, vf)) 6120 igb_rcv_msg_from_vf(adapter, vf); 6121 6122 /* process any acks */ 6123 if (!igb_check_for_ack(hw, vf)) 6124 igb_rcv_ack_from_vf(adapter, vf); 6125 } 6126} 6127 6128/** 6129 * igb_set_uta - Set unicast filter table address 6130 * @adapter: board private structure 6131 * 6132 * The unicast table address is a register array of 32-bit registers. 6133 * The table is meant to be used in a way similar to how the MTA is used 6134 * however due to certain limitations in the hardware it is necessary to 6135 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6136 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6137 **/ 6138static void igb_set_uta(struct igb_adapter *adapter) 6139{ 6140 struct e1000_hw *hw = &adapter->hw; 6141 int i; 6142 6143 /* The UTA table only exists on 82576 hardware and newer */ 6144 if (hw->mac.type < e1000_82576) 6145 return; 6146 6147 /* we only need to do this if VMDq is enabled */ 6148 if (!adapter->vfs_allocated_count) 6149 return; 6150 6151 for (i = 0; i < hw->mac.uta_reg_count; i++) 6152 array_wr32(E1000_UTA, i, ~0); 6153} 6154 6155/** 6156 * igb_intr_msi - Interrupt Handler 6157 * @irq: interrupt number 6158 * @data: pointer to a network interface device structure 6159 **/ 6160static irqreturn_t igb_intr_msi(int irq, void *data) 6161{ 6162 struct igb_adapter *adapter = data; 6163 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6164 struct e1000_hw *hw = &adapter->hw; 6165 /* read ICR disables interrupts using IAM */ 6166 u32 icr = rd32(E1000_ICR); 6167 6168 igb_write_itr(q_vector); 6169 6170 if (icr & E1000_ICR_DRSTA) 6171 schedule_work(&adapter->reset_task); 6172 6173 if (icr & E1000_ICR_DOUTSYNC) { 6174 /* HW is reporting DMA is out of sync */ 6175 adapter->stats.doosync++; 6176 } 6177 6178 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6179 hw->mac.get_link_status = 1; 6180 if (!test_bit(__IGB_DOWN, &adapter->state)) 6181 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6182 } 6183 6184 if (icr & E1000_ICR_TS) { 6185 u32 tsicr = rd32(E1000_TSICR); 6186 6187 if (tsicr & E1000_TSICR_TXTS) { 6188 /* acknowledge the interrupt */ 6189 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6190 /* retrieve hardware timestamp */ 6191 schedule_work(&adapter->ptp_tx_work); 6192 } 6193 } 6194 6195 napi_schedule(&q_vector->napi); 6196 6197 return IRQ_HANDLED; 6198} 6199 6200/** 6201 * igb_intr - Legacy Interrupt Handler 6202 * @irq: interrupt number 6203 * @data: pointer to a network interface device structure 6204 **/ 6205static irqreturn_t igb_intr(int irq, void *data) 6206{ 6207 struct igb_adapter *adapter = data; 6208 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6209 struct e1000_hw *hw = &adapter->hw; 6210 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6211 * need for the IMC write 6212 */ 6213 u32 icr = rd32(E1000_ICR); 6214 6215 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6216 * not set, then the adapter didn't send an interrupt 6217 */ 6218 if (!(icr & E1000_ICR_INT_ASSERTED)) 6219 return IRQ_NONE; 6220 6221 igb_write_itr(q_vector); 6222 6223 if (icr & E1000_ICR_DRSTA) 6224 schedule_work(&adapter->reset_task); 6225 6226 if (icr & E1000_ICR_DOUTSYNC) { 6227 /* HW is reporting DMA is out of sync */ 6228 adapter->stats.doosync++; 6229 } 6230 6231 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6232 hw->mac.get_link_status = 1; 6233 /* guard against interrupt when we're going down */ 6234 if (!test_bit(__IGB_DOWN, &adapter->state)) 6235 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6236 } 6237 6238 if (icr & E1000_ICR_TS) { 6239 u32 tsicr = rd32(E1000_TSICR); 6240 6241 if (tsicr & E1000_TSICR_TXTS) { 6242 /* acknowledge the interrupt */ 6243 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6244 /* retrieve hardware timestamp */ 6245 schedule_work(&adapter->ptp_tx_work); 6246 } 6247 } 6248 6249 napi_schedule(&q_vector->napi); 6250 6251 return IRQ_HANDLED; 6252} 6253 6254static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6255{ 6256 struct igb_adapter *adapter = q_vector->adapter; 6257 struct e1000_hw *hw = &adapter->hw; 6258 6259 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6260 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6261 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6262 igb_set_itr(q_vector); 6263 else 6264 igb_update_ring_itr(q_vector); 6265 } 6266 6267 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6268 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6269 wr32(E1000_EIMS, q_vector->eims_value); 6270 else 6271 igb_irq_enable(adapter); 6272 } 6273} 6274 6275/** 6276 * igb_poll - NAPI Rx polling callback 6277 * @napi: napi polling structure 6278 * @budget: count of how many packets we should handle 6279 **/ 6280static int igb_poll(struct napi_struct *napi, int budget) 6281{ 6282 struct igb_q_vector *q_vector = container_of(napi, 6283 struct igb_q_vector, 6284 napi); 6285 bool clean_complete = true; 6286 6287#ifdef CONFIG_IGB_DCA 6288 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6289 igb_update_dca(q_vector); 6290#endif 6291 if (q_vector->tx.ring) 6292 clean_complete = igb_clean_tx_irq(q_vector); 6293 6294 if (q_vector->rx.ring) 6295 clean_complete &= igb_clean_rx_irq(q_vector, budget); 6296 6297 /* If all work not completed, return budget and keep polling */ 6298 if (!clean_complete) 6299 return budget; 6300 6301 /* If not enough Rx work done, exit the polling mode */ 6302 napi_complete(napi); 6303 igb_ring_irq_enable(q_vector); 6304 6305 return 0; 6306} 6307 6308/** 6309 * igb_clean_tx_irq - Reclaim resources after transmit completes 6310 * @q_vector: pointer to q_vector containing needed info 6311 * 6312 * returns true if ring is completely cleaned 6313 **/ 6314static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 6315{ 6316 struct igb_adapter *adapter = q_vector->adapter; 6317 struct igb_ring *tx_ring = q_vector->tx.ring; 6318 struct igb_tx_buffer *tx_buffer; 6319 union e1000_adv_tx_desc *tx_desc; 6320 unsigned int total_bytes = 0, total_packets = 0; 6321 unsigned int budget = q_vector->tx.work_limit; 6322 unsigned int i = tx_ring->next_to_clean; 6323 6324 if (test_bit(__IGB_DOWN, &adapter->state)) 6325 return true; 6326 6327 tx_buffer = &tx_ring->tx_buffer_info[i]; 6328 tx_desc = IGB_TX_DESC(tx_ring, i); 6329 i -= tx_ring->count; 6330 6331 do { 6332 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6333 6334 /* if next_to_watch is not set then there is no work pending */ 6335 if (!eop_desc) 6336 break; 6337 6338 /* prevent any other reads prior to eop_desc */ 6339 read_barrier_depends(); 6340 6341 /* if DD is not set pending work has not been completed */ 6342 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6343 break; 6344 6345 /* clear next_to_watch to prevent false hangs */ 6346 tx_buffer->next_to_watch = NULL; 6347 6348 /* update the statistics for this packet */ 6349 total_bytes += tx_buffer->bytecount; 6350 total_packets += tx_buffer->gso_segs; 6351 6352 /* free the skb */ 6353 dev_kfree_skb_any(tx_buffer->skb); 6354 6355 /* unmap skb header data */ 6356 dma_unmap_single(tx_ring->dev, 6357 dma_unmap_addr(tx_buffer, dma), 6358 dma_unmap_len(tx_buffer, len), 6359 DMA_TO_DEVICE); 6360 6361 /* clear tx_buffer data */ 6362 tx_buffer->skb = NULL; 6363 dma_unmap_len_set(tx_buffer, len, 0); 6364 6365 /* clear last DMA location and unmap remaining buffers */ 6366 while (tx_desc != eop_desc) { 6367 tx_buffer++; 6368 tx_desc++; 6369 i++; 6370 if (unlikely(!i)) { 6371 i -= tx_ring->count; 6372 tx_buffer = tx_ring->tx_buffer_info; 6373 tx_desc = IGB_TX_DESC(tx_ring, 0); 6374 } 6375 6376 /* unmap any remaining paged data */ 6377 if (dma_unmap_len(tx_buffer, len)) { 6378 dma_unmap_page(tx_ring->dev, 6379 dma_unmap_addr(tx_buffer, dma), 6380 dma_unmap_len(tx_buffer, len), 6381 DMA_TO_DEVICE); 6382 dma_unmap_len_set(tx_buffer, len, 0); 6383 } 6384 } 6385 6386 /* move us one more past the eop_desc for start of next pkt */ 6387 tx_buffer++; 6388 tx_desc++; 6389 i++; 6390 if (unlikely(!i)) { 6391 i -= tx_ring->count; 6392 tx_buffer = tx_ring->tx_buffer_info; 6393 tx_desc = IGB_TX_DESC(tx_ring, 0); 6394 } 6395 6396 /* issue prefetch for next Tx descriptor */ 6397 prefetch(tx_desc); 6398 6399 /* update budget accounting */ 6400 budget--; 6401 } while (likely(budget)); 6402 6403 netdev_tx_completed_queue(txring_txq(tx_ring), 6404 total_packets, total_bytes); 6405 i += tx_ring->count; 6406 tx_ring->next_to_clean = i; 6407 u64_stats_update_begin(&tx_ring->tx_syncp); 6408 tx_ring->tx_stats.bytes += total_bytes; 6409 tx_ring->tx_stats.packets += total_packets; 6410 u64_stats_update_end(&tx_ring->tx_syncp); 6411 q_vector->tx.total_bytes += total_bytes; 6412 q_vector->tx.total_packets += total_packets; 6413 6414 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6415 struct e1000_hw *hw = &adapter->hw; 6416 6417 /* Detect a transmit hang in hardware, this serializes the 6418 * check with the clearing of time_stamp and movement of i 6419 */ 6420 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6421 if (tx_buffer->next_to_watch && 6422 time_after(jiffies, tx_buffer->time_stamp + 6423 (adapter->tx_timeout_factor * HZ)) && 6424 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6425 6426 /* detected Tx unit hang */ 6427 dev_err(tx_ring->dev, 6428 "Detected Tx Unit Hang\n" 6429 " Tx Queue <%d>\n" 6430 " TDH <%x>\n" 6431 " TDT <%x>\n" 6432 " next_to_use <%x>\n" 6433 " next_to_clean <%x>\n" 6434 "buffer_info[next_to_clean]\n" 6435 " time_stamp <%lx>\n" 6436 " next_to_watch <%p>\n" 6437 " jiffies <%lx>\n" 6438 " desc.status <%x>\n", 6439 tx_ring->queue_index, 6440 rd32(E1000_TDH(tx_ring->reg_idx)), 6441 readl(tx_ring->tail), 6442 tx_ring->next_to_use, 6443 tx_ring->next_to_clean, 6444 tx_buffer->time_stamp, 6445 tx_buffer->next_to_watch, 6446 jiffies, 6447 tx_buffer->next_to_watch->wb.status); 6448 netif_stop_subqueue(tx_ring->netdev, 6449 tx_ring->queue_index); 6450 6451 /* we are about to reset, no point in enabling stuff */ 6452 return true; 6453 } 6454 } 6455 6456#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6457 if (unlikely(total_packets && 6458 netif_carrier_ok(tx_ring->netdev) && 6459 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6460 /* Make sure that anybody stopping the queue after this 6461 * sees the new next_to_clean. 6462 */ 6463 smp_mb(); 6464 if (__netif_subqueue_stopped(tx_ring->netdev, 6465 tx_ring->queue_index) && 6466 !(test_bit(__IGB_DOWN, &adapter->state))) { 6467 netif_wake_subqueue(tx_ring->netdev, 6468 tx_ring->queue_index); 6469 6470 u64_stats_update_begin(&tx_ring->tx_syncp); 6471 tx_ring->tx_stats.restart_queue++; 6472 u64_stats_update_end(&tx_ring->tx_syncp); 6473 } 6474 } 6475 6476 return !!budget; 6477} 6478 6479/** 6480 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6481 * @rx_ring: rx descriptor ring to store buffers on 6482 * @old_buff: donor buffer to have page reused 6483 * 6484 * Synchronizes page for reuse by the adapter 6485 **/ 6486static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6487 struct igb_rx_buffer *old_buff) 6488{ 6489 struct igb_rx_buffer *new_buff; 6490 u16 nta = rx_ring->next_to_alloc; 6491 6492 new_buff = &rx_ring->rx_buffer_info[nta]; 6493 6494 /* update, and store next to alloc */ 6495 nta++; 6496 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6497 6498 /* transfer page from old buffer to new buffer */ 6499 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); 6500 6501 /* sync the buffer for use by the device */ 6502 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 6503 old_buff->page_offset, 6504 IGB_RX_BUFSZ, 6505 DMA_FROM_DEVICE); 6506} 6507 6508static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 6509 struct page *page, 6510 unsigned int truesize) 6511{ 6512 /* avoid re-using remote pages */ 6513 if (unlikely(page_to_nid(page) != numa_node_id())) 6514 return false; 6515 6516#if (PAGE_SIZE < 8192) 6517 /* if we are only owner of page we can reuse it */ 6518 if (unlikely(page_count(page) != 1)) 6519 return false; 6520 6521 /* flip page offset to other buffer */ 6522 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 6523 6524 /* since we are the only owner of the page and we need to 6525 * increment it, just set the value to 2 in order to avoid 6526 * an unnecessary locked operation 6527 */ 6528 atomic_set(&page->_count, 2); 6529#else 6530 /* move offset up to the next cache line */ 6531 rx_buffer->page_offset += truesize; 6532 6533 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 6534 return false; 6535 6536 /* bump ref count on page before it is given to the stack */ 6537 get_page(page); 6538#endif 6539 6540 return true; 6541} 6542 6543/** 6544 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6545 * @rx_ring: rx descriptor ring to transact packets on 6546 * @rx_buffer: buffer containing page to add 6547 * @rx_desc: descriptor containing length of buffer written by hardware 6548 * @skb: sk_buff to place the data into 6549 * 6550 * This function will add the data contained in rx_buffer->page to the skb. 6551 * This is done either through a direct copy if the data in the buffer is 6552 * less than the skb header size, otherwise it will just attach the page as 6553 * a frag to the skb. 6554 * 6555 * The function will then update the page offset if necessary and return 6556 * true if the buffer can be reused by the adapter. 6557 **/ 6558static bool igb_add_rx_frag(struct igb_ring *rx_ring, 6559 struct igb_rx_buffer *rx_buffer, 6560 union e1000_adv_rx_desc *rx_desc, 6561 struct sk_buff *skb) 6562{ 6563 struct page *page = rx_buffer->page; 6564 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 6565#if (PAGE_SIZE < 8192) 6566 unsigned int truesize = IGB_RX_BUFSZ; 6567#else 6568 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 6569#endif 6570 6571 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { 6572 unsigned char *va = page_address(page) + rx_buffer->page_offset; 6573 6574 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6575 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6576 va += IGB_TS_HDR_LEN; 6577 size -= IGB_TS_HDR_LEN; 6578 } 6579 6580 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 6581 6582 /* we can reuse buffer as-is, just make sure it is local */ 6583 if (likely(page_to_nid(page) == numa_node_id())) 6584 return true; 6585 6586 /* this page cannot be reused so discard it */ 6587 put_page(page); 6588 return false; 6589 } 6590 6591 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 6592 rx_buffer->page_offset, size, truesize); 6593 6594 return igb_can_reuse_rx_page(rx_buffer, page, truesize); 6595} 6596 6597static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 6598 union e1000_adv_rx_desc *rx_desc, 6599 struct sk_buff *skb) 6600{ 6601 struct igb_rx_buffer *rx_buffer; 6602 struct page *page; 6603 6604 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 6605 6606 page = rx_buffer->page; 6607 prefetchw(page); 6608 6609 if (likely(!skb)) { 6610 void *page_addr = page_address(page) + 6611 rx_buffer->page_offset; 6612 6613 /* prefetch first cache line of first page */ 6614 prefetch(page_addr); 6615#if L1_CACHE_BYTES < 128 6616 prefetch(page_addr + L1_CACHE_BYTES); 6617#endif 6618 6619 /* allocate a skb to store the frags */ 6620 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 6621 IGB_RX_HDR_LEN); 6622 if (unlikely(!skb)) { 6623 rx_ring->rx_stats.alloc_failed++; 6624 return NULL; 6625 } 6626 6627 /* we will be copying header into skb->data in 6628 * pskb_may_pull so it is in our interest to prefetch 6629 * it now to avoid a possible cache miss 6630 */ 6631 prefetchw(skb->data); 6632 } 6633 6634 /* we are reusing so sync this buffer for CPU use */ 6635 dma_sync_single_range_for_cpu(rx_ring->dev, 6636 rx_buffer->dma, 6637 rx_buffer->page_offset, 6638 IGB_RX_BUFSZ, 6639 DMA_FROM_DEVICE); 6640 6641 /* pull page into skb */ 6642 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 6643 /* hand second half of page back to the ring */ 6644 igb_reuse_rx_page(rx_ring, rx_buffer); 6645 } else { 6646 /* we are not reusing the buffer so unmap it */ 6647 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6648 PAGE_SIZE, DMA_FROM_DEVICE); 6649 } 6650 6651 /* clear contents of rx_buffer */ 6652 rx_buffer->page = NULL; 6653 6654 return skb; 6655} 6656 6657static inline void igb_rx_checksum(struct igb_ring *ring, 6658 union e1000_adv_rx_desc *rx_desc, 6659 struct sk_buff *skb) 6660{ 6661 skb_checksum_none_assert(skb); 6662 6663 /* Ignore Checksum bit is set */ 6664 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6665 return; 6666 6667 /* Rx checksum disabled via ethtool */ 6668 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6669 return; 6670 6671 /* TCP/UDP checksum error bit is set */ 6672 if (igb_test_staterr(rx_desc, 6673 E1000_RXDEXT_STATERR_TCPE | 6674 E1000_RXDEXT_STATERR_IPE)) { 6675 /* work around errata with sctp packets where the TCPE aka 6676 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6677 * packets, (aka let the stack check the crc32c) 6678 */ 6679 if (!((skb->len == 60) && 6680 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6681 u64_stats_update_begin(&ring->rx_syncp); 6682 ring->rx_stats.csum_err++; 6683 u64_stats_update_end(&ring->rx_syncp); 6684 } 6685 /* let the stack verify checksum errors */ 6686 return; 6687 } 6688 /* It must be a TCP or UDP packet with a valid checksum */ 6689 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 6690 E1000_RXD_STAT_UDPCS)) 6691 skb->ip_summed = CHECKSUM_UNNECESSARY; 6692 6693 dev_dbg(ring->dev, "cksum success: bits %08X\n", 6694 le32_to_cpu(rx_desc->wb.upper.status_error)); 6695} 6696 6697static inline void igb_rx_hash(struct igb_ring *ring, 6698 union e1000_adv_rx_desc *rx_desc, 6699 struct sk_buff *skb) 6700{ 6701 if (ring->netdev->features & NETIF_F_RXHASH) 6702 skb_set_hash(skb, 6703 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 6704 PKT_HASH_TYPE_L3); 6705} 6706 6707/** 6708 * igb_is_non_eop - process handling of non-EOP buffers 6709 * @rx_ring: Rx ring being processed 6710 * @rx_desc: Rx descriptor for current buffer 6711 * @skb: current socket buffer containing buffer in progress 6712 * 6713 * This function updates next to clean. If the buffer is an EOP buffer 6714 * this function exits returning false, otherwise it will place the 6715 * sk_buff in the next buffer to be chained and return true indicating 6716 * that this is in fact a non-EOP buffer. 6717 **/ 6718static bool igb_is_non_eop(struct igb_ring *rx_ring, 6719 union e1000_adv_rx_desc *rx_desc) 6720{ 6721 u32 ntc = rx_ring->next_to_clean + 1; 6722 6723 /* fetch, update, and store next to clean */ 6724 ntc = (ntc < rx_ring->count) ? ntc : 0; 6725 rx_ring->next_to_clean = ntc; 6726 6727 prefetch(IGB_RX_DESC(rx_ring, ntc)); 6728 6729 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 6730 return false; 6731 6732 return true; 6733} 6734 6735/** 6736 * igb_get_headlen - determine size of header for LRO/GRO 6737 * @data: pointer to the start of the headers 6738 * @max_len: total length of section to find headers in 6739 * 6740 * This function is meant to determine the length of headers that will 6741 * be recognized by hardware for LRO, and GRO offloads. The main 6742 * motivation of doing this is to only perform one pull for IPv4 TCP 6743 * packets so that we can do basic things like calculating the gso_size 6744 * based on the average data per packet. 6745 **/ 6746static unsigned int igb_get_headlen(unsigned char *data, 6747 unsigned int max_len) 6748{ 6749 union { 6750 unsigned char *network; 6751 /* l2 headers */ 6752 struct ethhdr *eth; 6753 struct vlan_hdr *vlan; 6754 /* l3 headers */ 6755 struct iphdr *ipv4; 6756 struct ipv6hdr *ipv6; 6757 } hdr; 6758 __be16 protocol; 6759 u8 nexthdr = 0; /* default to not TCP */ 6760 u8 hlen; 6761 6762 /* this should never happen, but better safe than sorry */ 6763 if (max_len < ETH_HLEN) 6764 return max_len; 6765 6766 /* initialize network frame pointer */ 6767 hdr.network = data; 6768 6769 /* set first protocol and move network header forward */ 6770 protocol = hdr.eth->h_proto; 6771 hdr.network += ETH_HLEN; 6772 6773 /* handle any vlan tag if present */ 6774 if (protocol == htons(ETH_P_8021Q)) { 6775 if ((hdr.network - data) > (max_len - VLAN_HLEN)) 6776 return max_len; 6777 6778 protocol = hdr.vlan->h_vlan_encapsulated_proto; 6779 hdr.network += VLAN_HLEN; 6780 } 6781 6782 /* handle L3 protocols */ 6783 if (protocol == htons(ETH_P_IP)) { 6784 if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) 6785 return max_len; 6786 6787 /* access ihl as a u8 to avoid unaligned access on ia64 */ 6788 hlen = (hdr.network[0] & 0x0F) << 2; 6789 6790 /* verify hlen meets minimum size requirements */ 6791 if (hlen < sizeof(struct iphdr)) 6792 return hdr.network - data; 6793 6794 /* record next protocol if header is present */ 6795 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET))) 6796 nexthdr = hdr.ipv4->protocol; 6797 } else if (protocol == htons(ETH_P_IPV6)) { 6798 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) 6799 return max_len; 6800 6801 /* record next protocol */ 6802 nexthdr = hdr.ipv6->nexthdr; 6803 hlen = sizeof(struct ipv6hdr); 6804 } else { 6805 return hdr.network - data; 6806 } 6807 6808 /* relocate pointer to start of L4 header */ 6809 hdr.network += hlen; 6810 6811 /* finally sort out TCP */ 6812 if (nexthdr == IPPROTO_TCP) { 6813 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) 6814 return max_len; 6815 6816 /* access doff as a u8 to avoid unaligned access on ia64 */ 6817 hlen = (hdr.network[12] & 0xF0) >> 2; 6818 6819 /* verify hlen meets minimum size requirements */ 6820 if (hlen < sizeof(struct tcphdr)) 6821 return hdr.network - data; 6822 6823 hdr.network += hlen; 6824 } else if (nexthdr == IPPROTO_UDP) { 6825 if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) 6826 return max_len; 6827 6828 hdr.network += sizeof(struct udphdr); 6829 } 6830 6831 /* If everything has gone correctly hdr.network should be the 6832 * data section of the packet and will be the end of the header. 6833 * If not then it probably represents the end of the last recognized 6834 * header. 6835 */ 6836 if ((hdr.network - data) < max_len) 6837 return hdr.network - data; 6838 else 6839 return max_len; 6840} 6841 6842/** 6843 * igb_pull_tail - igb specific version of skb_pull_tail 6844 * @rx_ring: rx descriptor ring packet is being transacted on 6845 * @rx_desc: pointer to the EOP Rx descriptor 6846 * @skb: pointer to current skb being adjusted 6847 * 6848 * This function is an igb specific version of __pskb_pull_tail. The 6849 * main difference between this version and the original function is that 6850 * this function can make several assumptions about the state of things 6851 * that allow for significant optimizations versus the standard function. 6852 * As a result we can do things like drop a frag and maintain an accurate 6853 * truesize for the skb. 6854 */ 6855static void igb_pull_tail(struct igb_ring *rx_ring, 6856 union e1000_adv_rx_desc *rx_desc, 6857 struct sk_buff *skb) 6858{ 6859 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6860 unsigned char *va; 6861 unsigned int pull_len; 6862 6863 /* it is valid to use page_address instead of kmap since we are 6864 * working with pages allocated out of the lomem pool per 6865 * alloc_page(GFP_ATOMIC) 6866 */ 6867 va = skb_frag_address(frag); 6868 6869 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6870 /* retrieve timestamp from buffer */ 6871 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6872 6873 /* update pointers to remove timestamp header */ 6874 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); 6875 frag->page_offset += IGB_TS_HDR_LEN; 6876 skb->data_len -= IGB_TS_HDR_LEN; 6877 skb->len -= IGB_TS_HDR_LEN; 6878 6879 /* move va to start of packet data */ 6880 va += IGB_TS_HDR_LEN; 6881 } 6882 6883 /* we need the header to contain the greater of either ETH_HLEN or 6884 * 60 bytes if the skb->len is less than 60 for skb_pad. 6885 */ 6886 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); 6887 6888 /* align pull length to size of long to optimize memcpy performance */ 6889 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 6890 6891 /* update all of the pointers */ 6892 skb_frag_size_sub(frag, pull_len); 6893 frag->page_offset += pull_len; 6894 skb->data_len -= pull_len; 6895 skb->tail += pull_len; 6896} 6897 6898/** 6899 * igb_cleanup_headers - Correct corrupted or empty headers 6900 * @rx_ring: rx descriptor ring packet is being transacted on 6901 * @rx_desc: pointer to the EOP Rx descriptor 6902 * @skb: pointer to current skb being fixed 6903 * 6904 * Address the case where we are pulling data in on pages only 6905 * and as such no data is present in the skb header. 6906 * 6907 * In addition if skb is not at least 60 bytes we need to pad it so that 6908 * it is large enough to qualify as a valid Ethernet frame. 6909 * 6910 * Returns true if an error was encountered and skb was freed. 6911 **/ 6912static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6913 union e1000_adv_rx_desc *rx_desc, 6914 struct sk_buff *skb) 6915{ 6916 if (unlikely((igb_test_staterr(rx_desc, 6917 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6918 struct net_device *netdev = rx_ring->netdev; 6919 if (!(netdev->features & NETIF_F_RXALL)) { 6920 dev_kfree_skb_any(skb); 6921 return true; 6922 } 6923 } 6924 6925 /* place header in linear portion of buffer */ 6926 if (skb_is_nonlinear(skb)) 6927 igb_pull_tail(rx_ring, rx_desc, skb); 6928 6929 /* if skb_pad returns an error the skb was freed */ 6930 if (unlikely(skb->len < 60)) { 6931 int pad_len = 60 - skb->len; 6932 6933 if (skb_pad(skb, pad_len)) 6934 return true; 6935 __skb_put(skb, pad_len); 6936 } 6937 6938 return false; 6939} 6940 6941/** 6942 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6943 * @rx_ring: rx descriptor ring packet is being transacted on 6944 * @rx_desc: pointer to the EOP Rx descriptor 6945 * @skb: pointer to current skb being populated 6946 * 6947 * This function checks the ring, descriptor, and packet information in 6948 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6949 * other fields within the skb. 6950 **/ 6951static void igb_process_skb_fields(struct igb_ring *rx_ring, 6952 union e1000_adv_rx_desc *rx_desc, 6953 struct sk_buff *skb) 6954{ 6955 struct net_device *dev = rx_ring->netdev; 6956 6957 igb_rx_hash(rx_ring, rx_desc, skb); 6958 6959 igb_rx_checksum(rx_ring, rx_desc, skb); 6960 6961 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 6962 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 6963 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 6964 6965 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 6966 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6967 u16 vid; 6968 6969 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6970 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6971 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6972 else 6973 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6974 6975 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 6976 } 6977 6978 skb_record_rx_queue(skb, rx_ring->queue_index); 6979 6980 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6981} 6982 6983static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 6984{ 6985 struct igb_ring *rx_ring = q_vector->rx.ring; 6986 struct sk_buff *skb = rx_ring->skb; 6987 unsigned int total_bytes = 0, total_packets = 0; 6988 u16 cleaned_count = igb_desc_unused(rx_ring); 6989 6990 while (likely(total_packets < budget)) { 6991 union e1000_adv_rx_desc *rx_desc; 6992 6993 /* return some buffers to hardware, one at a time is too slow */ 6994 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6995 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6996 cleaned_count = 0; 6997 } 6998 6999 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 7000 7001 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) 7002 break; 7003 7004 /* This memory barrier is needed to keep us from reading 7005 * any other fields out of the rx_desc until we know the 7006 * RXD_STAT_DD bit is set 7007 */ 7008 rmb(); 7009 7010 /* retrieve a buffer from the ring */ 7011 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 7012 7013 /* exit if we failed to retrieve a buffer */ 7014 if (!skb) 7015 break; 7016 7017 cleaned_count++; 7018 7019 /* fetch next buffer in frame if non-eop */ 7020 if (igb_is_non_eop(rx_ring, rx_desc)) 7021 continue; 7022 7023 /* verify the packet layout is correct */ 7024 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 7025 skb = NULL; 7026 continue; 7027 } 7028 7029 /* probably a little skewed due to removing CRC */ 7030 total_bytes += skb->len; 7031 7032 /* populate checksum, timestamp, VLAN, and protocol */ 7033 igb_process_skb_fields(rx_ring, rx_desc, skb); 7034 7035 napi_gro_receive(&q_vector->napi, skb); 7036 7037 /* reset skb pointer */ 7038 skb = NULL; 7039 7040 /* update budget accounting */ 7041 total_packets++; 7042 } 7043 7044 /* place incomplete frames back on ring for completion */ 7045 rx_ring->skb = skb; 7046 7047 u64_stats_update_begin(&rx_ring->rx_syncp); 7048 rx_ring->rx_stats.packets += total_packets; 7049 rx_ring->rx_stats.bytes += total_bytes; 7050 u64_stats_update_end(&rx_ring->rx_syncp); 7051 q_vector->rx.total_packets += total_packets; 7052 q_vector->rx.total_bytes += total_bytes; 7053 7054 if (cleaned_count) 7055 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7056 7057 return (total_packets < budget); 7058} 7059 7060static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7061 struct igb_rx_buffer *bi) 7062{ 7063 struct page *page = bi->page; 7064 dma_addr_t dma; 7065 7066 /* since we are recycling buffers we should seldom need to alloc */ 7067 if (likely(page)) 7068 return true; 7069 7070 /* alloc new page for storage */ 7071 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); 7072 if (unlikely(!page)) { 7073 rx_ring->rx_stats.alloc_failed++; 7074 return false; 7075 } 7076 7077 /* map page for use */ 7078 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 7079 7080 /* if mapping failed free memory back to system since 7081 * there isn't much point in holding memory we can't use 7082 */ 7083 if (dma_mapping_error(rx_ring->dev, dma)) { 7084 __free_page(page); 7085 7086 rx_ring->rx_stats.alloc_failed++; 7087 return false; 7088 } 7089 7090 bi->dma = dma; 7091 bi->page = page; 7092 bi->page_offset = 0; 7093 7094 return true; 7095} 7096 7097/** 7098 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7099 * @adapter: address of board private structure 7100 **/ 7101void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7102{ 7103 union e1000_adv_rx_desc *rx_desc; 7104 struct igb_rx_buffer *bi; 7105 u16 i = rx_ring->next_to_use; 7106 7107 /* nothing to do */ 7108 if (!cleaned_count) 7109 return; 7110 7111 rx_desc = IGB_RX_DESC(rx_ring, i); 7112 bi = &rx_ring->rx_buffer_info[i]; 7113 i -= rx_ring->count; 7114 7115 do { 7116 if (!igb_alloc_mapped_page(rx_ring, bi)) 7117 break; 7118 7119 /* Refresh the desc even if buffer_addrs didn't change 7120 * because each write-back erases this info. 7121 */ 7122 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7123 7124 rx_desc++; 7125 bi++; 7126 i++; 7127 if (unlikely(!i)) { 7128 rx_desc = IGB_RX_DESC(rx_ring, 0); 7129 bi = rx_ring->rx_buffer_info; 7130 i -= rx_ring->count; 7131 } 7132 7133 /* clear the hdr_addr for the next_to_use descriptor */ 7134 rx_desc->read.hdr_addr = 0; 7135 7136 cleaned_count--; 7137 } while (cleaned_count); 7138 7139 i += rx_ring->count; 7140 7141 if (rx_ring->next_to_use != i) { 7142 /* record the next descriptor to use */ 7143 rx_ring->next_to_use = i; 7144 7145 /* update next to alloc since we have filled the ring */ 7146 rx_ring->next_to_alloc = i; 7147 7148 /* Force memory writes to complete before letting h/w 7149 * know there are new descriptors to fetch. (Only 7150 * applicable for weak-ordered memory model archs, 7151 * such as IA-64). 7152 */ 7153 wmb(); 7154 writel(i, rx_ring->tail); 7155 } 7156} 7157 7158/** 7159 * igb_mii_ioctl - 7160 * @netdev: 7161 * @ifreq: 7162 * @cmd: 7163 **/ 7164static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7165{ 7166 struct igb_adapter *adapter = netdev_priv(netdev); 7167 struct mii_ioctl_data *data = if_mii(ifr); 7168 7169 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7170 return -EOPNOTSUPP; 7171 7172 switch (cmd) { 7173 case SIOCGMIIPHY: 7174 data->phy_id = adapter->hw.phy.addr; 7175 break; 7176 case SIOCGMIIREG: 7177 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7178 &data->val_out)) 7179 return -EIO; 7180 break; 7181 case SIOCSMIIREG: 7182 default: 7183 return -EOPNOTSUPP; 7184 } 7185 return 0; 7186} 7187 7188/** 7189 * igb_ioctl - 7190 * @netdev: 7191 * @ifreq: 7192 * @cmd: 7193 **/ 7194static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7195{ 7196 switch (cmd) { 7197 case SIOCGMIIPHY: 7198 case SIOCGMIIREG: 7199 case SIOCSMIIREG: 7200 return igb_mii_ioctl(netdev, ifr, cmd); 7201 case SIOCGHWTSTAMP: 7202 return igb_ptp_get_ts_config(netdev, ifr); 7203 case SIOCSHWTSTAMP: 7204 return igb_ptp_set_ts_config(netdev, ifr); 7205 default: 7206 return -EOPNOTSUPP; 7207 } 7208} 7209 7210s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7211{ 7212 struct igb_adapter *adapter = hw->back; 7213 7214 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7215 return -E1000_ERR_CONFIG; 7216 7217 return 0; 7218} 7219 7220s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7221{ 7222 struct igb_adapter *adapter = hw->back; 7223 7224 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7225 return -E1000_ERR_CONFIG; 7226 7227 return 0; 7228} 7229 7230static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7231{ 7232 struct igb_adapter *adapter = netdev_priv(netdev); 7233 struct e1000_hw *hw = &adapter->hw; 7234 u32 ctrl, rctl; 7235 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7236 7237 if (enable) { 7238 /* enable VLAN tag insert/strip */ 7239 ctrl = rd32(E1000_CTRL); 7240 ctrl |= E1000_CTRL_VME; 7241 wr32(E1000_CTRL, ctrl); 7242 7243 /* Disable CFI check */ 7244 rctl = rd32(E1000_RCTL); 7245 rctl &= ~E1000_RCTL_CFIEN; 7246 wr32(E1000_RCTL, rctl); 7247 } else { 7248 /* disable VLAN tag insert/strip */ 7249 ctrl = rd32(E1000_CTRL); 7250 ctrl &= ~E1000_CTRL_VME; 7251 wr32(E1000_CTRL, ctrl); 7252 } 7253 7254 igb_rlpml_set(adapter); 7255} 7256 7257static int igb_vlan_rx_add_vid(struct net_device *netdev, 7258 __be16 proto, u16 vid) 7259{ 7260 struct igb_adapter *adapter = netdev_priv(netdev); 7261 struct e1000_hw *hw = &adapter->hw; 7262 int pf_id = adapter->vfs_allocated_count; 7263 7264 /* attempt to add filter to vlvf array */ 7265 igb_vlvf_set(adapter, vid, true, pf_id); 7266 7267 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7268 igb_vfta_set(hw, vid, true); 7269 7270 set_bit(vid, adapter->active_vlans); 7271 7272 return 0; 7273} 7274 7275static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7276 __be16 proto, u16 vid) 7277{ 7278 struct igb_adapter *adapter = netdev_priv(netdev); 7279 struct e1000_hw *hw = &adapter->hw; 7280 int pf_id = adapter->vfs_allocated_count; 7281 s32 err; 7282 7283 /* remove vlan from VLVF table array */ 7284 err = igb_vlvf_set(adapter, vid, false, pf_id); 7285 7286 /* if vid was not present in VLVF just remove it from table */ 7287 if (err) 7288 igb_vfta_set(hw, vid, false); 7289 7290 clear_bit(vid, adapter->active_vlans); 7291 7292 return 0; 7293} 7294 7295static void igb_restore_vlan(struct igb_adapter *adapter) 7296{ 7297 u16 vid; 7298 7299 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7300 7301 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 7302 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7303} 7304 7305int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7306{ 7307 struct pci_dev *pdev = adapter->pdev; 7308 struct e1000_mac_info *mac = &adapter->hw.mac; 7309 7310 mac->autoneg = 0; 7311 7312 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7313 * for the switch() below to work 7314 */ 7315 if ((spd & 1) || (dplx & ~1)) 7316 goto err_inval; 7317 7318 /* Fiber NIC's only allow 1000 gbps Full duplex 7319 * and 100Mbps Full duplex for 100baseFx sfp 7320 */ 7321 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7322 switch (spd + dplx) { 7323 case SPEED_10 + DUPLEX_HALF: 7324 case SPEED_10 + DUPLEX_FULL: 7325 case SPEED_100 + DUPLEX_HALF: 7326 goto err_inval; 7327 default: 7328 break; 7329 } 7330 } 7331 7332 switch (spd + dplx) { 7333 case SPEED_10 + DUPLEX_HALF: 7334 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7335 break; 7336 case SPEED_10 + DUPLEX_FULL: 7337 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7338 break; 7339 case SPEED_100 + DUPLEX_HALF: 7340 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7341 break; 7342 case SPEED_100 + DUPLEX_FULL: 7343 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7344 break; 7345 case SPEED_1000 + DUPLEX_FULL: 7346 mac->autoneg = 1; 7347 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7348 break; 7349 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7350 default: 7351 goto err_inval; 7352 } 7353 7354 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7355 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7356 7357 return 0; 7358 7359err_inval: 7360 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7361 return -EINVAL; 7362} 7363 7364static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7365 bool runtime) 7366{ 7367 struct net_device *netdev = pci_get_drvdata(pdev); 7368 struct igb_adapter *adapter = netdev_priv(netdev); 7369 struct e1000_hw *hw = &adapter->hw; 7370 u32 ctrl, rctl, status; 7371 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7372#ifdef CONFIG_PM 7373 int retval = 0; 7374#endif 7375 7376 netif_device_detach(netdev); 7377 7378 if (netif_running(netdev)) 7379 __igb_close(netdev, true); 7380 7381 igb_clear_interrupt_scheme(adapter); 7382 7383#ifdef CONFIG_PM 7384 retval = pci_save_state(pdev); 7385 if (retval) 7386 return retval; 7387#endif 7388 7389 status = rd32(E1000_STATUS); 7390 if (status & E1000_STATUS_LU) 7391 wufc &= ~E1000_WUFC_LNKC; 7392 7393 if (wufc) { 7394 igb_setup_rctl(adapter); 7395 igb_set_rx_mode(netdev); 7396 7397 /* turn on all-multi mode if wake on multicast is enabled */ 7398 if (wufc & E1000_WUFC_MC) { 7399 rctl = rd32(E1000_RCTL); 7400 rctl |= E1000_RCTL_MPE; 7401 wr32(E1000_RCTL, rctl); 7402 } 7403 7404 ctrl = rd32(E1000_CTRL); 7405 /* advertise wake from D3Cold */ 7406 #define E1000_CTRL_ADVD3WUC 0x00100000 7407 /* phy power management enable */ 7408 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7409 ctrl |= E1000_CTRL_ADVD3WUC; 7410 wr32(E1000_CTRL, ctrl); 7411 7412 /* Allow time for pending master requests to run */ 7413 igb_disable_pcie_master(hw); 7414 7415 wr32(E1000_WUC, E1000_WUC_PME_EN); 7416 wr32(E1000_WUFC, wufc); 7417 } else { 7418 wr32(E1000_WUC, 0); 7419 wr32(E1000_WUFC, 0); 7420 } 7421 7422 *enable_wake = wufc || adapter->en_mng_pt; 7423 if (!*enable_wake) 7424 igb_power_down_link(adapter); 7425 else 7426 igb_power_up_link(adapter); 7427 7428 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7429 * would have already happened in close and is redundant. 7430 */ 7431 igb_release_hw_control(adapter); 7432 7433 pci_disable_device(pdev); 7434 7435 return 0; 7436} 7437 7438#ifdef CONFIG_PM 7439#ifdef CONFIG_PM_SLEEP 7440static int igb_suspend(struct device *dev) 7441{ 7442 int retval; 7443 bool wake; 7444 struct pci_dev *pdev = to_pci_dev(dev); 7445 7446 retval = __igb_shutdown(pdev, &wake, 0); 7447 if (retval) 7448 return retval; 7449 7450 if (wake) { 7451 pci_prepare_to_sleep(pdev); 7452 } else { 7453 pci_wake_from_d3(pdev, false); 7454 pci_set_power_state(pdev, PCI_D3hot); 7455 } 7456 7457 return 0; 7458} 7459#endif /* CONFIG_PM_SLEEP */ 7460 7461static int igb_resume(struct device *dev) 7462{ 7463 struct pci_dev *pdev = to_pci_dev(dev); 7464 struct net_device *netdev = pci_get_drvdata(pdev); 7465 struct igb_adapter *adapter = netdev_priv(netdev); 7466 struct e1000_hw *hw = &adapter->hw; 7467 u32 err; 7468 7469 pci_set_power_state(pdev, PCI_D0); 7470 pci_restore_state(pdev); 7471 pci_save_state(pdev); 7472 7473 err = pci_enable_device_mem(pdev); 7474 if (err) { 7475 dev_err(&pdev->dev, 7476 "igb: Cannot enable PCI device from suspend\n"); 7477 return err; 7478 } 7479 pci_set_master(pdev); 7480 7481 pci_enable_wake(pdev, PCI_D3hot, 0); 7482 pci_enable_wake(pdev, PCI_D3cold, 0); 7483 7484 if (igb_init_interrupt_scheme(adapter, true)) { 7485 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7486 return -ENOMEM; 7487 } 7488 7489 igb_reset(adapter); 7490 7491 /* let the f/w know that the h/w is now under the control of the 7492 * driver. 7493 */ 7494 igb_get_hw_control(adapter); 7495 7496 wr32(E1000_WUS, ~0); 7497 7498 if (netdev->flags & IFF_UP) { 7499 rtnl_lock(); 7500 err = __igb_open(netdev, true); 7501 rtnl_unlock(); 7502 if (err) 7503 return err; 7504 } 7505 7506 netif_device_attach(netdev); 7507 return 0; 7508} 7509 7510#ifdef CONFIG_PM_RUNTIME 7511static int igb_runtime_idle(struct device *dev) 7512{ 7513 struct pci_dev *pdev = to_pci_dev(dev); 7514 struct net_device *netdev = pci_get_drvdata(pdev); 7515 struct igb_adapter *adapter = netdev_priv(netdev); 7516 7517 if (!igb_has_link(adapter)) 7518 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7519 7520 return -EBUSY; 7521} 7522 7523static int igb_runtime_suspend(struct device *dev) 7524{ 7525 struct pci_dev *pdev = to_pci_dev(dev); 7526 int retval; 7527 bool wake; 7528 7529 retval = __igb_shutdown(pdev, &wake, 1); 7530 if (retval) 7531 return retval; 7532 7533 if (wake) { 7534 pci_prepare_to_sleep(pdev); 7535 } else { 7536 pci_wake_from_d3(pdev, false); 7537 pci_set_power_state(pdev, PCI_D3hot); 7538 } 7539 7540 return 0; 7541} 7542 7543static int igb_runtime_resume(struct device *dev) 7544{ 7545 return igb_resume(dev); 7546} 7547#endif /* CONFIG_PM_RUNTIME */ 7548#endif 7549 7550static void igb_shutdown(struct pci_dev *pdev) 7551{ 7552 bool wake; 7553 7554 __igb_shutdown(pdev, &wake, 0); 7555 7556 if (system_state == SYSTEM_POWER_OFF) { 7557 pci_wake_from_d3(pdev, wake); 7558 pci_set_power_state(pdev, PCI_D3hot); 7559 } 7560} 7561 7562#ifdef CONFIG_PCI_IOV 7563static int igb_sriov_reinit(struct pci_dev *dev) 7564{ 7565 struct net_device *netdev = pci_get_drvdata(dev); 7566 struct igb_adapter *adapter = netdev_priv(netdev); 7567 struct pci_dev *pdev = adapter->pdev; 7568 7569 rtnl_lock(); 7570 7571 if (netif_running(netdev)) 7572 igb_close(netdev); 7573 7574 igb_clear_interrupt_scheme(adapter); 7575 7576 igb_init_queue_configuration(adapter); 7577 7578 if (igb_init_interrupt_scheme(adapter, true)) { 7579 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7580 return -ENOMEM; 7581 } 7582 7583 if (netif_running(netdev)) 7584 igb_open(netdev); 7585 7586 rtnl_unlock(); 7587 7588 return 0; 7589} 7590 7591static int igb_pci_disable_sriov(struct pci_dev *dev) 7592{ 7593 int err = igb_disable_sriov(dev); 7594 7595 if (!err) 7596 err = igb_sriov_reinit(dev); 7597 7598 return err; 7599} 7600 7601static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7602{ 7603 int err = igb_enable_sriov(dev, num_vfs); 7604 7605 if (err) 7606 goto out; 7607 7608 err = igb_sriov_reinit(dev); 7609 if (!err) 7610 return num_vfs; 7611 7612out: 7613 return err; 7614} 7615 7616#endif 7617static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7618{ 7619#ifdef CONFIG_PCI_IOV 7620 if (num_vfs == 0) 7621 return igb_pci_disable_sriov(dev); 7622 else 7623 return igb_pci_enable_sriov(dev, num_vfs); 7624#endif 7625 return 0; 7626} 7627 7628#ifdef CONFIG_NET_POLL_CONTROLLER 7629/* Polling 'interrupt' - used by things like netconsole to send skbs 7630 * without having to re-enable interrupts. It's not called while 7631 * the interrupt routine is executing. 7632 */ 7633static void igb_netpoll(struct net_device *netdev) 7634{ 7635 struct igb_adapter *adapter = netdev_priv(netdev); 7636 struct e1000_hw *hw = &adapter->hw; 7637 struct igb_q_vector *q_vector; 7638 int i; 7639 7640 for (i = 0; i < adapter->num_q_vectors; i++) { 7641 q_vector = adapter->q_vector[i]; 7642 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7643 wr32(E1000_EIMC, q_vector->eims_value); 7644 else 7645 igb_irq_disable(adapter); 7646 napi_schedule(&q_vector->napi); 7647 } 7648} 7649#endif /* CONFIG_NET_POLL_CONTROLLER */ 7650 7651/** 7652 * igb_io_error_detected - called when PCI error is detected 7653 * @pdev: Pointer to PCI device 7654 * @state: The current pci connection state 7655 * 7656 * This function is called after a PCI bus error affecting 7657 * this device has been detected. 7658 **/ 7659static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7660 pci_channel_state_t state) 7661{ 7662 struct net_device *netdev = pci_get_drvdata(pdev); 7663 struct igb_adapter *adapter = netdev_priv(netdev); 7664 7665 netif_device_detach(netdev); 7666 7667 if (state == pci_channel_io_perm_failure) 7668 return PCI_ERS_RESULT_DISCONNECT; 7669 7670 if (netif_running(netdev)) 7671 igb_down(adapter); 7672 pci_disable_device(pdev); 7673 7674 /* Request a slot slot reset. */ 7675 return PCI_ERS_RESULT_NEED_RESET; 7676} 7677 7678/** 7679 * igb_io_slot_reset - called after the pci bus has been reset. 7680 * @pdev: Pointer to PCI device 7681 * 7682 * Restart the card from scratch, as if from a cold-boot. Implementation 7683 * resembles the first-half of the igb_resume routine. 7684 **/ 7685static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 7686{ 7687 struct net_device *netdev = pci_get_drvdata(pdev); 7688 struct igb_adapter *adapter = netdev_priv(netdev); 7689 struct e1000_hw *hw = &adapter->hw; 7690 pci_ers_result_t result; 7691 int err; 7692 7693 if (pci_enable_device_mem(pdev)) { 7694 dev_err(&pdev->dev, 7695 "Cannot re-enable PCI device after reset.\n"); 7696 result = PCI_ERS_RESULT_DISCONNECT; 7697 } else { 7698 pci_set_master(pdev); 7699 pci_restore_state(pdev); 7700 pci_save_state(pdev); 7701 7702 pci_enable_wake(pdev, PCI_D3hot, 0); 7703 pci_enable_wake(pdev, PCI_D3cold, 0); 7704 7705 igb_reset(adapter); 7706 wr32(E1000_WUS, ~0); 7707 result = PCI_ERS_RESULT_RECOVERED; 7708 } 7709 7710 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7711 if (err) { 7712 dev_err(&pdev->dev, 7713 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7714 err); 7715 /* non-fatal, continue */ 7716 } 7717 7718 return result; 7719} 7720 7721/** 7722 * igb_io_resume - called when traffic can start flowing again. 7723 * @pdev: Pointer to PCI device 7724 * 7725 * This callback is called when the error recovery driver tells us that 7726 * its OK to resume normal operation. Implementation resembles the 7727 * second-half of the igb_resume routine. 7728 */ 7729static void igb_io_resume(struct pci_dev *pdev) 7730{ 7731 struct net_device *netdev = pci_get_drvdata(pdev); 7732 struct igb_adapter *adapter = netdev_priv(netdev); 7733 7734 if (netif_running(netdev)) { 7735 if (igb_up(adapter)) { 7736 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7737 return; 7738 } 7739 } 7740 7741 netif_device_attach(netdev); 7742 7743 /* let the f/w know that the h/w is now under the control of the 7744 * driver. 7745 */ 7746 igb_get_hw_control(adapter); 7747} 7748 7749static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7750 u8 qsel) 7751{ 7752 u32 rar_low, rar_high; 7753 struct e1000_hw *hw = &adapter->hw; 7754 7755 /* HW expects these in little endian so we reverse the byte order 7756 * from network order (big endian) to little endian 7757 */ 7758 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 7759 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 7760 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 7761 7762 /* Indicate to hardware the Address is Valid. */ 7763 rar_high |= E1000_RAH_AV; 7764 7765 if (hw->mac.type == e1000_82575) 7766 rar_high |= E1000_RAH_POOL_1 * qsel; 7767 else 7768 rar_high |= E1000_RAH_POOL_1 << qsel; 7769 7770 wr32(E1000_RAL(index), rar_low); 7771 wrfl(); 7772 wr32(E1000_RAH(index), rar_high); 7773 wrfl(); 7774} 7775 7776static int igb_set_vf_mac(struct igb_adapter *adapter, 7777 int vf, unsigned char *mac_addr) 7778{ 7779 struct e1000_hw *hw = &adapter->hw; 7780 /* VF MAC addresses start at end of receive addresses and moves 7781 * towards the first, as a result a collision should not be possible 7782 */ 7783 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7784 7785 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7786 7787 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7788 7789 return 0; 7790} 7791 7792static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7793{ 7794 struct igb_adapter *adapter = netdev_priv(netdev); 7795 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7796 return -EINVAL; 7797 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7798 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7799 dev_info(&adapter->pdev->dev, 7800 "Reload the VF driver to make this change effective."); 7801 if (test_bit(__IGB_DOWN, &adapter->state)) { 7802 dev_warn(&adapter->pdev->dev, 7803 "The VF MAC address has been set, but the PF device is not up.\n"); 7804 dev_warn(&adapter->pdev->dev, 7805 "Bring the PF device up before attempting to use the VF device.\n"); 7806 } 7807 return igb_set_vf_mac(adapter, vf, mac); 7808} 7809 7810static int igb_link_mbps(int internal_link_speed) 7811{ 7812 switch (internal_link_speed) { 7813 case SPEED_100: 7814 return 100; 7815 case SPEED_1000: 7816 return 1000; 7817 default: 7818 return 0; 7819 } 7820} 7821 7822static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7823 int link_speed) 7824{ 7825 int rf_dec, rf_int; 7826 u32 bcnrc_val; 7827 7828 if (tx_rate != 0) { 7829 /* Calculate the rate factor values to set */ 7830 rf_int = link_speed / tx_rate; 7831 rf_dec = (link_speed - (rf_int * tx_rate)); 7832 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / 7833 tx_rate; 7834 7835 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7836 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 7837 E1000_RTTBCNRC_RF_INT_MASK); 7838 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7839 } else { 7840 bcnrc_val = 0; 7841 } 7842 7843 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7844 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7845 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7846 */ 7847 wr32(E1000_RTTBCNRM, 0x14); 7848 wr32(E1000_RTTBCNRC, bcnrc_val); 7849} 7850 7851static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7852{ 7853 int actual_link_speed, i; 7854 bool reset_rate = false; 7855 7856 /* VF TX rate limit was not set or not supported */ 7857 if ((adapter->vf_rate_link_speed == 0) || 7858 (adapter->hw.mac.type != e1000_82576)) 7859 return; 7860 7861 actual_link_speed = igb_link_mbps(adapter->link_speed); 7862 if (actual_link_speed != adapter->vf_rate_link_speed) { 7863 reset_rate = true; 7864 adapter->vf_rate_link_speed = 0; 7865 dev_info(&adapter->pdev->dev, 7866 "Link speed has been changed. VF Transmit rate is disabled\n"); 7867 } 7868 7869 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7870 if (reset_rate) 7871 adapter->vf_data[i].tx_rate = 0; 7872 7873 igb_set_vf_rate_limit(&adapter->hw, i, 7874 adapter->vf_data[i].tx_rate, 7875 actual_link_speed); 7876 } 7877} 7878 7879static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) 7880{ 7881 struct igb_adapter *adapter = netdev_priv(netdev); 7882 struct e1000_hw *hw = &adapter->hw; 7883 int actual_link_speed; 7884 7885 if (hw->mac.type != e1000_82576) 7886 return -EOPNOTSUPP; 7887 7888 actual_link_speed = igb_link_mbps(adapter->link_speed); 7889 if ((vf >= adapter->vfs_allocated_count) || 7890 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7891 (tx_rate < 0) || (tx_rate > actual_link_speed)) 7892 return -EINVAL; 7893 7894 adapter->vf_rate_link_speed = actual_link_speed; 7895 adapter->vf_data[vf].tx_rate = (u16)tx_rate; 7896 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); 7897 7898 return 0; 7899} 7900 7901static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 7902 bool setting) 7903{ 7904 struct igb_adapter *adapter = netdev_priv(netdev); 7905 struct e1000_hw *hw = &adapter->hw; 7906 u32 reg_val, reg_offset; 7907 7908 if (!adapter->vfs_allocated_count) 7909 return -EOPNOTSUPP; 7910 7911 if (vf >= adapter->vfs_allocated_count) 7912 return -EINVAL; 7913 7914 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 7915 reg_val = rd32(reg_offset); 7916 if (setting) 7917 reg_val |= ((1 << vf) | 7918 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7919 else 7920 reg_val &= ~((1 << vf) | 7921 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7922 wr32(reg_offset, reg_val); 7923 7924 adapter->vf_data[vf].spoofchk_enabled = setting; 7925 return E1000_SUCCESS; 7926} 7927 7928static int igb_ndo_get_vf_config(struct net_device *netdev, 7929 int vf, struct ifla_vf_info *ivi) 7930{ 7931 struct igb_adapter *adapter = netdev_priv(netdev); 7932 if (vf >= adapter->vfs_allocated_count) 7933 return -EINVAL; 7934 ivi->vf = vf; 7935 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7936 ivi->tx_rate = adapter->vf_data[vf].tx_rate; 7937 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7938 ivi->qos = adapter->vf_data[vf].pf_qos; 7939 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 7940 return 0; 7941} 7942 7943static void igb_vmm_control(struct igb_adapter *adapter) 7944{ 7945 struct e1000_hw *hw = &adapter->hw; 7946 u32 reg; 7947 7948 switch (hw->mac.type) { 7949 case e1000_82575: 7950 case e1000_i210: 7951 case e1000_i211: 7952 case e1000_i354: 7953 default: 7954 /* replication is not supported for 82575 */ 7955 return; 7956 case e1000_82576: 7957 /* notify HW that the MAC is adding vlan tags */ 7958 reg = rd32(E1000_DTXCTL); 7959 reg |= E1000_DTXCTL_VLAN_ADDED; 7960 wr32(E1000_DTXCTL, reg); 7961 case e1000_82580: 7962 /* enable replication vlan tag stripping */ 7963 reg = rd32(E1000_RPLOLR); 7964 reg |= E1000_RPLOLR_STRVLAN; 7965 wr32(E1000_RPLOLR, reg); 7966 case e1000_i350: 7967 /* none of the above registers are supported by i350 */ 7968 break; 7969 } 7970 7971 if (adapter->vfs_allocated_count) { 7972 igb_vmdq_set_loopback_pf(hw, true); 7973 igb_vmdq_set_replication_pf(hw, true); 7974 igb_vmdq_set_anti_spoofing_pf(hw, true, 7975 adapter->vfs_allocated_count); 7976 } else { 7977 igb_vmdq_set_loopback_pf(hw, false); 7978 igb_vmdq_set_replication_pf(hw, false); 7979 } 7980} 7981 7982static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7983{ 7984 struct e1000_hw *hw = &adapter->hw; 7985 u32 dmac_thr; 7986 u16 hwm; 7987 7988 if (hw->mac.type > e1000_82580) { 7989 if (adapter->flags & IGB_FLAG_DMAC) { 7990 u32 reg; 7991 7992 /* force threshold to 0. */ 7993 wr32(E1000_DMCTXTH, 0); 7994 7995 /* DMA Coalescing high water mark needs to be greater 7996 * than the Rx threshold. Set hwm to PBA - max frame 7997 * size in 16B units, capping it at PBA - 6KB. 7998 */ 7999 hwm = 64 * pba - adapter->max_frame_size / 16; 8000 if (hwm < 64 * (pba - 6)) 8001 hwm = 64 * (pba - 6); 8002 reg = rd32(E1000_FCRTC); 8003 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 8004 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 8005 & E1000_FCRTC_RTH_COAL_MASK); 8006 wr32(E1000_FCRTC, reg); 8007 8008 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 8009 * frame size, capping it at PBA - 10KB. 8010 */ 8011 dmac_thr = pba - adapter->max_frame_size / 512; 8012 if (dmac_thr < pba - 10) 8013 dmac_thr = pba - 10; 8014 reg = rd32(E1000_DMACR); 8015 reg &= ~E1000_DMACR_DMACTHR_MASK; 8016 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 8017 & E1000_DMACR_DMACTHR_MASK); 8018 8019 /* transition to L0x or L1 if available..*/ 8020 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 8021 8022 /* watchdog timer= +-1000 usec in 32usec intervals */ 8023 reg |= (1000 >> 5); 8024 8025 /* Disable BMC-to-OS Watchdog Enable */ 8026 if (hw->mac.type != e1000_i354) 8027 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 8028 8029 wr32(E1000_DMACR, reg); 8030 8031 /* no lower threshold to disable 8032 * coalescing(smart fifb)-UTRESH=0 8033 */ 8034 wr32(E1000_DMCRTRH, 0); 8035 8036 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8037 8038 wr32(E1000_DMCTLX, reg); 8039 8040 /* free space in tx packet buffer to wake from 8041 * DMA coal 8042 */ 8043 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8044 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8045 8046 /* make low power state decision controlled 8047 * by DMA coal 8048 */ 8049 reg = rd32(E1000_PCIEMISC); 8050 reg &= ~E1000_PCIEMISC_LX_DECISION; 8051 wr32(E1000_PCIEMISC, reg); 8052 } /* endif adapter->dmac is not disabled */ 8053 } else if (hw->mac.type == e1000_82580) { 8054 u32 reg = rd32(E1000_PCIEMISC); 8055 8056 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8057 wr32(E1000_DMACR, 0); 8058 } 8059} 8060 8061/** 8062 * igb_read_i2c_byte - Reads 8 bit word over I2C 8063 * @hw: pointer to hardware structure 8064 * @byte_offset: byte offset to read 8065 * @dev_addr: device address 8066 * @data: value read 8067 * 8068 * Performs byte read operation over I2C interface at 8069 * a specified device address. 8070 **/ 8071s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8072 u8 dev_addr, u8 *data) 8073{ 8074 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8075 struct i2c_client *this_client = adapter->i2c_client; 8076 s32 status; 8077 u16 swfw_mask = 0; 8078 8079 if (!this_client) 8080 return E1000_ERR_I2C; 8081 8082 swfw_mask = E1000_SWFW_PHY0_SM; 8083 8084 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 8085 != E1000_SUCCESS) 8086 return E1000_ERR_SWFW_SYNC; 8087 8088 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8089 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8090 8091 if (status < 0) 8092 return E1000_ERR_I2C; 8093 else { 8094 *data = status; 8095 return E1000_SUCCESS; 8096 } 8097} 8098 8099/** 8100 * igb_write_i2c_byte - Writes 8 bit word over I2C 8101 * @hw: pointer to hardware structure 8102 * @byte_offset: byte offset to write 8103 * @dev_addr: device address 8104 * @data: value to write 8105 * 8106 * Performs byte write operation over I2C interface at 8107 * a specified device address. 8108 **/ 8109s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8110 u8 dev_addr, u8 data) 8111{ 8112 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8113 struct i2c_client *this_client = adapter->i2c_client; 8114 s32 status; 8115 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8116 8117 if (!this_client) 8118 return E1000_ERR_I2C; 8119 8120 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) 8121 return E1000_ERR_SWFW_SYNC; 8122 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8123 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8124 8125 if (status) 8126 return E1000_ERR_I2C; 8127 else 8128 return E1000_SUCCESS; 8129 8130} 8131 8132int igb_reinit_queues(struct igb_adapter *adapter) 8133{ 8134 struct net_device *netdev = adapter->netdev; 8135 struct pci_dev *pdev = adapter->pdev; 8136 int err = 0; 8137 8138 if (netif_running(netdev)) 8139 igb_close(netdev); 8140 8141 igb_reset_interrupt_capability(adapter); 8142 8143 if (igb_init_interrupt_scheme(adapter, true)) { 8144 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8145 return -ENOMEM; 8146 } 8147 8148 if (netif_running(netdev)) 8149 err = igb_open(netdev); 8150 8151 return err; 8152} 8153/* igb_main.c */ 8154