igb_main.c revision a57fe23e240b95282e60d643cd8ada3d2a66d8c6
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30#include <linux/module.h> 31#include <linux/types.h> 32#include <linux/init.h> 33#include <linux/bitops.h> 34#include <linux/vmalloc.h> 35#include <linux/pagemap.h> 36#include <linux/netdevice.h> 37#include <linux/ipv6.h> 38#include <linux/slab.h> 39#include <net/checksum.h> 40#include <net/ip6_checksum.h> 41#include <linux/net_tstamp.h> 42#include <linux/mii.h> 43#include <linux/ethtool.h> 44#include <linux/if.h> 45#include <linux/if_vlan.h> 46#include <linux/pci.h> 47#include <linux/pci-aspm.h> 48#include <linux/delay.h> 49#include <linux/interrupt.h> 50#include <linux/ip.h> 51#include <linux/tcp.h> 52#include <linux/sctp.h> 53#include <linux/if_ether.h> 54#include <linux/aer.h> 55#include <linux/prefetch.h> 56#include <linux/pm_runtime.h> 57#ifdef CONFIG_IGB_DCA 58#include <linux/dca.h> 59#endif 60#include "igb.h" 61 62#define MAJ 4 63#define MIN 0 64#define BUILD 1 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 66__stringify(BUILD) "-k" 67char igb_driver_name[] = "igb"; 68char igb_driver_version[] = DRV_VERSION; 69static const char igb_driver_string[] = 70 "Intel(R) Gigabit Ethernet Network Driver"; 71static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation."; 72 73static const struct e1000_info *igb_info_tbl[] = { 74 [board_82575] = &e1000_82575_info, 75}; 76 77static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 108 /* required last entry */ 109 {0, } 110}; 111 112MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 113 114void igb_reset(struct igb_adapter *); 115static int igb_setup_all_tx_resources(struct igb_adapter *); 116static int igb_setup_all_rx_resources(struct igb_adapter *); 117static void igb_free_all_tx_resources(struct igb_adapter *); 118static void igb_free_all_rx_resources(struct igb_adapter *); 119static void igb_setup_mrqc(struct igb_adapter *); 120static int igb_probe(struct pci_dev *, const struct pci_device_id *); 121static void __devexit igb_remove(struct pci_dev *pdev); 122static int igb_sw_init(struct igb_adapter *); 123static int igb_open(struct net_device *); 124static int igb_close(struct net_device *); 125static void igb_configure_tx(struct igb_adapter *); 126static void igb_configure_rx(struct igb_adapter *); 127static void igb_clean_all_tx_rings(struct igb_adapter *); 128static void igb_clean_all_rx_rings(struct igb_adapter *); 129static void igb_clean_tx_ring(struct igb_ring *); 130static void igb_clean_rx_ring(struct igb_ring *); 131static void igb_set_rx_mode(struct net_device *); 132static void igb_update_phy_info(unsigned long); 133static void igb_watchdog(unsigned long); 134static void igb_watchdog_task(struct work_struct *); 135static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 136static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 137 struct rtnl_link_stats64 *stats); 138static int igb_change_mtu(struct net_device *, int); 139static int igb_set_mac(struct net_device *, void *); 140static void igb_set_uta(struct igb_adapter *adapter); 141static irqreturn_t igb_intr(int irq, void *); 142static irqreturn_t igb_intr_msi(int irq, void *); 143static irqreturn_t igb_msix_other(int irq, void *); 144static irqreturn_t igb_msix_ring(int irq, void *); 145#ifdef CONFIG_IGB_DCA 146static void igb_update_dca(struct igb_q_vector *); 147static void igb_setup_dca(struct igb_adapter *); 148#endif /* CONFIG_IGB_DCA */ 149static int igb_poll(struct napi_struct *, int); 150static bool igb_clean_tx_irq(struct igb_q_vector *); 151static bool igb_clean_rx_irq(struct igb_q_vector *, int); 152static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 153static void igb_tx_timeout(struct net_device *); 154static void igb_reset_task(struct work_struct *); 155static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); 156static int igb_vlan_rx_add_vid(struct net_device *, u16); 157static int igb_vlan_rx_kill_vid(struct net_device *, u16); 158static void igb_restore_vlan(struct igb_adapter *); 159static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 160static void igb_ping_all_vfs(struct igb_adapter *); 161static void igb_msg_task(struct igb_adapter *); 162static void igb_vmm_control(struct igb_adapter *); 163static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 164static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 165static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 166static int igb_ndo_set_vf_vlan(struct net_device *netdev, 167 int vf, u16 vlan, u8 qos); 168static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 169static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 170 struct ifla_vf_info *ivi); 171static void igb_check_vf_rate_limit(struct igb_adapter *); 172 173#ifdef CONFIG_PCI_IOV 174static int igb_vf_configure(struct igb_adapter *adapter, int vf); 175static bool igb_vfs_are_assigned(struct igb_adapter *adapter); 176#endif 177 178#ifdef CONFIG_PM 179#ifdef CONFIG_PM_SLEEP 180static int igb_suspend(struct device *); 181#endif 182static int igb_resume(struct device *); 183#ifdef CONFIG_PM_RUNTIME 184static int igb_runtime_suspend(struct device *dev); 185static int igb_runtime_resume(struct device *dev); 186static int igb_runtime_idle(struct device *dev); 187#endif 188static const struct dev_pm_ops igb_pm_ops = { 189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 191 igb_runtime_idle) 192}; 193#endif 194static void igb_shutdown(struct pci_dev *); 195#ifdef CONFIG_IGB_DCA 196static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 197static struct notifier_block dca_notifier = { 198 .notifier_call = igb_notify_dca, 199 .next = NULL, 200 .priority = 0 201}; 202#endif 203#ifdef CONFIG_NET_POLL_CONTROLLER 204/* for netdump / net console */ 205static void igb_netpoll(struct net_device *); 206#endif 207#ifdef CONFIG_PCI_IOV 208static unsigned int max_vfs = 0; 209module_param(max_vfs, uint, 0); 210MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " 211 "per physical function"); 212#endif /* CONFIG_PCI_IOV */ 213 214static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 215 pci_channel_state_t); 216static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 217static void igb_io_resume(struct pci_dev *); 218 219static struct pci_error_handlers igb_err_handler = { 220 .error_detected = igb_io_error_detected, 221 .slot_reset = igb_io_slot_reset, 222 .resume = igb_io_resume, 223}; 224 225static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 226 227static struct pci_driver igb_driver = { 228 .name = igb_driver_name, 229 .id_table = igb_pci_tbl, 230 .probe = igb_probe, 231 .remove = __devexit_p(igb_remove), 232#ifdef CONFIG_PM 233 .driver.pm = &igb_pm_ops, 234#endif 235 .shutdown = igb_shutdown, 236 .err_handler = &igb_err_handler 237}; 238 239MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 240MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 241MODULE_LICENSE("GPL"); 242MODULE_VERSION(DRV_VERSION); 243 244#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 245static int debug = -1; 246module_param(debug, int, 0); 247MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 248 249struct igb_reg_info { 250 u32 ofs; 251 char *name; 252}; 253 254static const struct igb_reg_info igb_reg_info_tbl[] = { 255 256 /* General Registers */ 257 {E1000_CTRL, "CTRL"}, 258 {E1000_STATUS, "STATUS"}, 259 {E1000_CTRL_EXT, "CTRL_EXT"}, 260 261 /* Interrupt Registers */ 262 {E1000_ICR, "ICR"}, 263 264 /* RX Registers */ 265 {E1000_RCTL, "RCTL"}, 266 {E1000_RDLEN(0), "RDLEN"}, 267 {E1000_RDH(0), "RDH"}, 268 {E1000_RDT(0), "RDT"}, 269 {E1000_RXDCTL(0), "RXDCTL"}, 270 {E1000_RDBAL(0), "RDBAL"}, 271 {E1000_RDBAH(0), "RDBAH"}, 272 273 /* TX Registers */ 274 {E1000_TCTL, "TCTL"}, 275 {E1000_TDBAL(0), "TDBAL"}, 276 {E1000_TDBAH(0), "TDBAH"}, 277 {E1000_TDLEN(0), "TDLEN"}, 278 {E1000_TDH(0), "TDH"}, 279 {E1000_TDT(0), "TDT"}, 280 {E1000_TXDCTL(0), "TXDCTL"}, 281 {E1000_TDFH, "TDFH"}, 282 {E1000_TDFT, "TDFT"}, 283 {E1000_TDFHS, "TDFHS"}, 284 {E1000_TDFPC, "TDFPC"}, 285 286 /* List Terminator */ 287 {} 288}; 289 290/* 291 * igb_regdump - register printout routine 292 */ 293static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 294{ 295 int n = 0; 296 char rname[16]; 297 u32 regs[8]; 298 299 switch (reginfo->ofs) { 300 case E1000_RDLEN(0): 301 for (n = 0; n < 4; n++) 302 regs[n] = rd32(E1000_RDLEN(n)); 303 break; 304 case E1000_RDH(0): 305 for (n = 0; n < 4; n++) 306 regs[n] = rd32(E1000_RDH(n)); 307 break; 308 case E1000_RDT(0): 309 for (n = 0; n < 4; n++) 310 regs[n] = rd32(E1000_RDT(n)); 311 break; 312 case E1000_RXDCTL(0): 313 for (n = 0; n < 4; n++) 314 regs[n] = rd32(E1000_RXDCTL(n)); 315 break; 316 case E1000_RDBAL(0): 317 for (n = 0; n < 4; n++) 318 regs[n] = rd32(E1000_RDBAL(n)); 319 break; 320 case E1000_RDBAH(0): 321 for (n = 0; n < 4; n++) 322 regs[n] = rd32(E1000_RDBAH(n)); 323 break; 324 case E1000_TDBAL(0): 325 for (n = 0; n < 4; n++) 326 regs[n] = rd32(E1000_RDBAL(n)); 327 break; 328 case E1000_TDBAH(0): 329 for (n = 0; n < 4; n++) 330 regs[n] = rd32(E1000_TDBAH(n)); 331 break; 332 case E1000_TDLEN(0): 333 for (n = 0; n < 4; n++) 334 regs[n] = rd32(E1000_TDLEN(n)); 335 break; 336 case E1000_TDH(0): 337 for (n = 0; n < 4; n++) 338 regs[n] = rd32(E1000_TDH(n)); 339 break; 340 case E1000_TDT(0): 341 for (n = 0; n < 4; n++) 342 regs[n] = rd32(E1000_TDT(n)); 343 break; 344 case E1000_TXDCTL(0): 345 for (n = 0; n < 4; n++) 346 regs[n] = rd32(E1000_TXDCTL(n)); 347 break; 348 default: 349 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 350 return; 351 } 352 353 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 354 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 355 regs[2], regs[3]); 356} 357 358/* 359 * igb_dump - Print registers, tx-rings and rx-rings 360 */ 361static void igb_dump(struct igb_adapter *adapter) 362{ 363 struct net_device *netdev = adapter->netdev; 364 struct e1000_hw *hw = &adapter->hw; 365 struct igb_reg_info *reginfo; 366 struct igb_ring *tx_ring; 367 union e1000_adv_tx_desc *tx_desc; 368 struct my_u0 { u64 a; u64 b; } *u0; 369 struct igb_ring *rx_ring; 370 union e1000_adv_rx_desc *rx_desc; 371 u32 staterr; 372 u16 i, n; 373 374 if (!netif_msg_hw(adapter)) 375 return; 376 377 /* Print netdevice Info */ 378 if (netdev) { 379 dev_info(&adapter->pdev->dev, "Net device Info\n"); 380 pr_info("Device Name state trans_start " 381 "last_rx\n"); 382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 383 netdev->state, netdev->trans_start, netdev->last_rx); 384 } 385 386 /* Print Registers */ 387 dev_info(&adapter->pdev->dev, "Register Dump\n"); 388 pr_info(" Register Name Value\n"); 389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 390 reginfo->name; reginfo++) { 391 igb_regdump(hw, reginfo); 392 } 393 394 /* Print TX Ring Summary */ 395 if (!netdev || !netif_running(netdev)) 396 goto exit; 397 398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 400 for (n = 0; n < adapter->num_tx_queues; n++) { 401 struct igb_tx_buffer *buffer_info; 402 tx_ring = adapter->tx_ring[n]; 403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 405 n, tx_ring->next_to_use, tx_ring->next_to_clean, 406 (u64)buffer_info->dma, 407 buffer_info->length, 408 buffer_info->next_to_watch, 409 (u64)buffer_info->time_stamp); 410 } 411 412 /* Print TX Rings */ 413 if (!netif_msg_tx_done(adapter)) 414 goto rx_ring_summary; 415 416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 417 418 /* Transmit Descriptor Formats 419 * 420 * Advanced Transmit Descriptor 421 * +--------------------------------------------------------------+ 422 * 0 | Buffer Address [63:0] | 423 * +--------------------------------------------------------------+ 424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 425 * +--------------------------------------------------------------+ 426 * 63 46 45 40 39 38 36 35 32 31 24 15 0 427 */ 428 429 for (n = 0; n < adapter->num_tx_queues; n++) { 430 tx_ring = adapter->tx_ring[n]; 431 pr_info("------------------------------------\n"); 432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 433 pr_info("------------------------------------\n"); 434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] " 435 "[bi->dma ] leng ntw timestamp " 436 "bi->skb\n"); 437 438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 439 const char *next_desc; 440 struct igb_tx_buffer *buffer_info; 441 tx_desc = IGB_TX_DESC(tx_ring, i); 442 buffer_info = &tx_ring->tx_buffer_info[i]; 443 u0 = (struct my_u0 *)tx_desc; 444 if (i == tx_ring->next_to_use && 445 i == tx_ring->next_to_clean) 446 next_desc = " NTC/U"; 447 else if (i == tx_ring->next_to_use) 448 next_desc = " NTU"; 449 else if (i == tx_ring->next_to_clean) 450 next_desc = " NTC"; 451 else 452 next_desc = ""; 453 454 pr_info("T [0x%03X] %016llX %016llX %016llX" 455 " %04X %p %016llX %p%s\n", i, 456 le64_to_cpu(u0->a), 457 le64_to_cpu(u0->b), 458 (u64)buffer_info->dma, 459 buffer_info->length, 460 buffer_info->next_to_watch, 461 (u64)buffer_info->time_stamp, 462 buffer_info->skb, next_desc); 463 464 if (netif_msg_pktdata(adapter) && buffer_info->skb) 465 print_hex_dump(KERN_INFO, "", 466 DUMP_PREFIX_ADDRESS, 467 16, 1, buffer_info->skb->data, 468 buffer_info->length, true); 469 } 470 } 471 472 /* Print RX Rings Summary */ 473rx_ring_summary: 474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 475 pr_info("Queue [NTU] [NTC]\n"); 476 for (n = 0; n < adapter->num_rx_queues; n++) { 477 rx_ring = adapter->rx_ring[n]; 478 pr_info(" %5d %5X %5X\n", 479 n, rx_ring->next_to_use, rx_ring->next_to_clean); 480 } 481 482 /* Print RX Rings */ 483 if (!netif_msg_rx_status(adapter)) 484 goto exit; 485 486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 487 488 /* Advanced Receive Descriptor (Read) Format 489 * 63 1 0 490 * +-----------------------------------------------------+ 491 * 0 | Packet Buffer Address [63:1] |A0/NSE| 492 * +----------------------------------------------+------+ 493 * 8 | Header Buffer Address [63:1] | DD | 494 * +-----------------------------------------------------+ 495 * 496 * 497 * Advanced Receive Descriptor (Write-Back) Format 498 * 499 * 63 48 47 32 31 30 21 20 17 16 4 3 0 500 * +------------------------------------------------------+ 501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 502 * | Checksum Ident | | | | Type | Type | 503 * +------------------------------------------------------+ 504 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 505 * +------------------------------------------------------+ 506 * 63 48 47 32 31 20 19 0 507 */ 508 509 for (n = 0; n < adapter->num_rx_queues; n++) { 510 rx_ring = adapter->rx_ring[n]; 511 pr_info("------------------------------------\n"); 512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 513 pr_info("------------------------------------\n"); 514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] " 515 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 516 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----" 517 "----------- [bi->skb] <-- Adv Rx Write-Back format\n"); 518 519 for (i = 0; i < rx_ring->count; i++) { 520 const char *next_desc; 521 struct igb_rx_buffer *buffer_info; 522 buffer_info = &rx_ring->rx_buffer_info[i]; 523 rx_desc = IGB_RX_DESC(rx_ring, i); 524 u0 = (struct my_u0 *)rx_desc; 525 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 526 527 if (i == rx_ring->next_to_use) 528 next_desc = " NTU"; 529 else if (i == rx_ring->next_to_clean) 530 next_desc = " NTC"; 531 else 532 next_desc = ""; 533 534 if (staterr & E1000_RXD_STAT_DD) { 535 /* Descriptor Done */ 536 pr_info("%s[0x%03X] %016llX %016llX -------" 537 "--------- %p%s\n", "RWB", i, 538 le64_to_cpu(u0->a), 539 le64_to_cpu(u0->b), 540 buffer_info->skb, next_desc); 541 } else { 542 pr_info("%s[0x%03X] %016llX %016llX %016llX" 543 " %p%s\n", "R ", i, 544 le64_to_cpu(u0->a), 545 le64_to_cpu(u0->b), 546 (u64)buffer_info->dma, 547 buffer_info->skb, next_desc); 548 549 if (netif_msg_pktdata(adapter) && 550 buffer_info->dma && buffer_info->skb) { 551 print_hex_dump(KERN_INFO, "", 552 DUMP_PREFIX_ADDRESS, 553 16, 1, buffer_info->skb->data, 554 IGB_RX_HDR_LEN, true); 555 print_hex_dump(KERN_INFO, "", 556 DUMP_PREFIX_ADDRESS, 557 16, 1, 558 page_address(buffer_info->page) + 559 buffer_info->page_offset, 560 PAGE_SIZE/2, true); 561 } 562 } 563 } 564 } 565 566exit: 567 return; 568} 569 570/** 571 * igb_get_hw_dev - return device 572 * used by hardware layer to print debugging information 573 **/ 574struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 575{ 576 struct igb_adapter *adapter = hw->back; 577 return adapter->netdev; 578} 579 580/** 581 * igb_init_module - Driver Registration Routine 582 * 583 * igb_init_module is the first routine called when the driver is 584 * loaded. All it does is register with the PCI subsystem. 585 **/ 586static int __init igb_init_module(void) 587{ 588 int ret; 589 pr_info("%s - version %s\n", 590 igb_driver_string, igb_driver_version); 591 592 pr_info("%s\n", igb_copyright); 593 594#ifdef CONFIG_IGB_DCA 595 dca_register_notify(&dca_notifier); 596#endif 597 ret = pci_register_driver(&igb_driver); 598 return ret; 599} 600 601module_init(igb_init_module); 602 603/** 604 * igb_exit_module - Driver Exit Cleanup Routine 605 * 606 * igb_exit_module is called just before the driver is removed 607 * from memory. 608 **/ 609static void __exit igb_exit_module(void) 610{ 611#ifdef CONFIG_IGB_DCA 612 dca_unregister_notify(&dca_notifier); 613#endif 614 pci_unregister_driver(&igb_driver); 615} 616 617module_exit(igb_exit_module); 618 619#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 620/** 621 * igb_cache_ring_register - Descriptor ring to register mapping 622 * @adapter: board private structure to initialize 623 * 624 * Once we know the feature-set enabled for the device, we'll cache 625 * the register offset the descriptor ring is assigned to. 626 **/ 627static void igb_cache_ring_register(struct igb_adapter *adapter) 628{ 629 int i = 0, j = 0; 630 u32 rbase_offset = adapter->vfs_allocated_count; 631 632 switch (adapter->hw.mac.type) { 633 case e1000_82576: 634 /* The queues are allocated for virtualization such that VF 0 635 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 636 * In order to avoid collision we start at the first free queue 637 * and continue consuming queues in the same sequence 638 */ 639 if (adapter->vfs_allocated_count) { 640 for (; i < adapter->rss_queues; i++) 641 adapter->rx_ring[i]->reg_idx = rbase_offset + 642 Q_IDX_82576(i); 643 } 644 case e1000_82575: 645 case e1000_82580: 646 case e1000_i350: 647 case e1000_i210: 648 case e1000_i211: 649 default: 650 for (; i < adapter->num_rx_queues; i++) 651 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 652 for (; j < adapter->num_tx_queues; j++) 653 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 654 break; 655 } 656} 657 658static void igb_free_queues(struct igb_adapter *adapter) 659{ 660 int i; 661 662 for (i = 0; i < adapter->num_tx_queues; i++) { 663 kfree(adapter->tx_ring[i]); 664 adapter->tx_ring[i] = NULL; 665 } 666 for (i = 0; i < adapter->num_rx_queues; i++) { 667 kfree(adapter->rx_ring[i]); 668 adapter->rx_ring[i] = NULL; 669 } 670 adapter->num_rx_queues = 0; 671 adapter->num_tx_queues = 0; 672} 673 674/** 675 * igb_alloc_queues - Allocate memory for all rings 676 * @adapter: board private structure to initialize 677 * 678 * We allocate one ring per queue at run-time since we don't know the 679 * number of queues at compile-time. 680 **/ 681static int igb_alloc_queues(struct igb_adapter *adapter) 682{ 683 struct igb_ring *ring; 684 int i; 685 686 for (i = 0; i < adapter->num_tx_queues; i++) { 687 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL); 688 if (!ring) 689 goto err; 690 ring->count = adapter->tx_ring_count; 691 ring->queue_index = i; 692 ring->dev = &adapter->pdev->dev; 693 ring->netdev = adapter->netdev; 694 /* For 82575, context index must be unique per ring. */ 695 if (adapter->hw.mac.type == e1000_82575) 696 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 697 adapter->tx_ring[i] = ring; 698 } 699 700 for (i = 0; i < adapter->num_rx_queues; i++) { 701 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL); 702 if (!ring) 703 goto err; 704 ring->count = adapter->rx_ring_count; 705 ring->queue_index = i; 706 ring->dev = &adapter->pdev->dev; 707 ring->netdev = adapter->netdev; 708 /* set flag indicating ring supports SCTP checksum offload */ 709 if (adapter->hw.mac.type >= e1000_82576) 710 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 711 712 /* 713 * On i350, i210, and i211, loopback VLAN packets 714 * have the tag byte-swapped. 715 * */ 716 if (adapter->hw.mac.type >= e1000_i350) 717 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 718 719 adapter->rx_ring[i] = ring; 720 } 721 722 igb_cache_ring_register(adapter); 723 724 return 0; 725 726err: 727 igb_free_queues(adapter); 728 729 return -ENOMEM; 730} 731 732/** 733 * igb_write_ivar - configure ivar for given MSI-X vector 734 * @hw: pointer to the HW structure 735 * @msix_vector: vector number we are allocating to a given ring 736 * @index: row index of IVAR register to write within IVAR table 737 * @offset: column offset of in IVAR, should be multiple of 8 738 * 739 * This function is intended to handle the writing of the IVAR register 740 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 741 * each containing an cause allocation for an Rx and Tx ring, and a 742 * variable number of rows depending on the number of queues supported. 743 **/ 744static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 745 int index, int offset) 746{ 747 u32 ivar = array_rd32(E1000_IVAR0, index); 748 749 /* clear any bits that are currently set */ 750 ivar &= ~((u32)0xFF << offset); 751 752 /* write vector and valid bit */ 753 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 754 755 array_wr32(E1000_IVAR0, index, ivar); 756} 757 758#define IGB_N0_QUEUE -1 759static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 760{ 761 struct igb_adapter *adapter = q_vector->adapter; 762 struct e1000_hw *hw = &adapter->hw; 763 int rx_queue = IGB_N0_QUEUE; 764 int tx_queue = IGB_N0_QUEUE; 765 u32 msixbm = 0; 766 767 if (q_vector->rx.ring) 768 rx_queue = q_vector->rx.ring->reg_idx; 769 if (q_vector->tx.ring) 770 tx_queue = q_vector->tx.ring->reg_idx; 771 772 switch (hw->mac.type) { 773 case e1000_82575: 774 /* The 82575 assigns vectors using a bitmask, which matches the 775 bitmask for the EICR/EIMS/EIMC registers. To assign one 776 or more queues to a vector, we write the appropriate bits 777 into the MSIXBM register for that vector. */ 778 if (rx_queue > IGB_N0_QUEUE) 779 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 780 if (tx_queue > IGB_N0_QUEUE) 781 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 782 if (!adapter->msix_entries && msix_vector == 0) 783 msixbm |= E1000_EIMS_OTHER; 784 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 785 q_vector->eims_value = msixbm; 786 break; 787 case e1000_82576: 788 /* 789 * 82576 uses a table that essentially consists of 2 columns 790 * with 8 rows. The ordering is column-major so we use the 791 * lower 3 bits as the row index, and the 4th bit as the 792 * column offset. 793 */ 794 if (rx_queue > IGB_N0_QUEUE) 795 igb_write_ivar(hw, msix_vector, 796 rx_queue & 0x7, 797 (rx_queue & 0x8) << 1); 798 if (tx_queue > IGB_N0_QUEUE) 799 igb_write_ivar(hw, msix_vector, 800 tx_queue & 0x7, 801 ((tx_queue & 0x8) << 1) + 8); 802 q_vector->eims_value = 1 << msix_vector; 803 break; 804 case e1000_82580: 805 case e1000_i350: 806 case e1000_i210: 807 case e1000_i211: 808 /* 809 * On 82580 and newer adapters the scheme is similar to 82576 810 * however instead of ordering column-major we have things 811 * ordered row-major. So we traverse the table by using 812 * bit 0 as the column offset, and the remaining bits as the 813 * row index. 814 */ 815 if (rx_queue > IGB_N0_QUEUE) 816 igb_write_ivar(hw, msix_vector, 817 rx_queue >> 1, 818 (rx_queue & 0x1) << 4); 819 if (tx_queue > IGB_N0_QUEUE) 820 igb_write_ivar(hw, msix_vector, 821 tx_queue >> 1, 822 ((tx_queue & 0x1) << 4) + 8); 823 q_vector->eims_value = 1 << msix_vector; 824 break; 825 default: 826 BUG(); 827 break; 828 } 829 830 /* add q_vector eims value to global eims_enable_mask */ 831 adapter->eims_enable_mask |= q_vector->eims_value; 832 833 /* configure q_vector to set itr on first interrupt */ 834 q_vector->set_itr = 1; 835} 836 837/** 838 * igb_configure_msix - Configure MSI-X hardware 839 * 840 * igb_configure_msix sets up the hardware to properly 841 * generate MSI-X interrupts. 842 **/ 843static void igb_configure_msix(struct igb_adapter *adapter) 844{ 845 u32 tmp; 846 int i, vector = 0; 847 struct e1000_hw *hw = &adapter->hw; 848 849 adapter->eims_enable_mask = 0; 850 851 /* set vector for other causes, i.e. link changes */ 852 switch (hw->mac.type) { 853 case e1000_82575: 854 tmp = rd32(E1000_CTRL_EXT); 855 /* enable MSI-X PBA support*/ 856 tmp |= E1000_CTRL_EXT_PBA_CLR; 857 858 /* Auto-Mask interrupts upon ICR read. */ 859 tmp |= E1000_CTRL_EXT_EIAME; 860 tmp |= E1000_CTRL_EXT_IRCA; 861 862 wr32(E1000_CTRL_EXT, tmp); 863 864 /* enable msix_other interrupt */ 865 array_wr32(E1000_MSIXBM(0), vector++, 866 E1000_EIMS_OTHER); 867 adapter->eims_other = E1000_EIMS_OTHER; 868 869 break; 870 871 case e1000_82576: 872 case e1000_82580: 873 case e1000_i350: 874 case e1000_i210: 875 case e1000_i211: 876 /* Turn on MSI-X capability first, or our settings 877 * won't stick. And it will take days to debug. */ 878 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 879 E1000_GPIE_PBA | E1000_GPIE_EIAME | 880 E1000_GPIE_NSICR); 881 882 /* enable msix_other interrupt */ 883 adapter->eims_other = 1 << vector; 884 tmp = (vector++ | E1000_IVAR_VALID) << 8; 885 886 wr32(E1000_IVAR_MISC, tmp); 887 break; 888 default: 889 /* do nothing, since nothing else supports MSI-X */ 890 break; 891 } /* switch (hw->mac.type) */ 892 893 adapter->eims_enable_mask |= adapter->eims_other; 894 895 for (i = 0; i < adapter->num_q_vectors; i++) 896 igb_assign_vector(adapter->q_vector[i], vector++); 897 898 wrfl(); 899} 900 901/** 902 * igb_request_msix - Initialize MSI-X interrupts 903 * 904 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 905 * kernel. 906 **/ 907static int igb_request_msix(struct igb_adapter *adapter) 908{ 909 struct net_device *netdev = adapter->netdev; 910 struct e1000_hw *hw = &adapter->hw; 911 int i, err = 0, vector = 0; 912 913 err = request_irq(adapter->msix_entries[vector].vector, 914 igb_msix_other, 0, netdev->name, adapter); 915 if (err) 916 goto out; 917 vector++; 918 919 for (i = 0; i < adapter->num_q_vectors; i++) { 920 struct igb_q_vector *q_vector = adapter->q_vector[i]; 921 922 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 923 924 if (q_vector->rx.ring && q_vector->tx.ring) 925 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 926 q_vector->rx.ring->queue_index); 927 else if (q_vector->tx.ring) 928 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 929 q_vector->tx.ring->queue_index); 930 else if (q_vector->rx.ring) 931 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 932 q_vector->rx.ring->queue_index); 933 else 934 sprintf(q_vector->name, "%s-unused", netdev->name); 935 936 err = request_irq(adapter->msix_entries[vector].vector, 937 igb_msix_ring, 0, q_vector->name, 938 q_vector); 939 if (err) 940 goto out; 941 vector++; 942 } 943 944 igb_configure_msix(adapter); 945 return 0; 946out: 947 return err; 948} 949 950static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 951{ 952 if (adapter->msix_entries) { 953 pci_disable_msix(adapter->pdev); 954 kfree(adapter->msix_entries); 955 adapter->msix_entries = NULL; 956 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 957 pci_disable_msi(adapter->pdev); 958 } 959} 960 961/** 962 * igb_free_q_vectors - Free memory allocated for interrupt vectors 963 * @adapter: board private structure to initialize 964 * 965 * This function frees the memory allocated to the q_vectors. In addition if 966 * NAPI is enabled it will delete any references to the NAPI struct prior 967 * to freeing the q_vector. 968 **/ 969static void igb_free_q_vectors(struct igb_adapter *adapter) 970{ 971 int v_idx; 972 973 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 974 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 975 adapter->q_vector[v_idx] = NULL; 976 if (!q_vector) 977 continue; 978 netif_napi_del(&q_vector->napi); 979 kfree(q_vector); 980 } 981 adapter->num_q_vectors = 0; 982} 983 984/** 985 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 986 * 987 * This function resets the device so that it has 0 rx queues, tx queues, and 988 * MSI-X interrupts allocated. 989 */ 990static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 991{ 992 igb_free_queues(adapter); 993 igb_free_q_vectors(adapter); 994 igb_reset_interrupt_capability(adapter); 995} 996 997/** 998 * igb_set_interrupt_capability - set MSI or MSI-X if supported 999 * 1000 * Attempt to configure interrupts using the best available 1001 * capabilities of the hardware and kernel. 1002 **/ 1003static int igb_set_interrupt_capability(struct igb_adapter *adapter) 1004{ 1005 int err; 1006 int numvecs, i; 1007 1008 /* Number of supported queues. */ 1009 adapter->num_rx_queues = adapter->rss_queues; 1010 if (adapter->vfs_allocated_count) 1011 adapter->num_tx_queues = 1; 1012 else 1013 adapter->num_tx_queues = adapter->rss_queues; 1014 1015 /* start with one vector for every rx queue */ 1016 numvecs = adapter->num_rx_queues; 1017 1018 /* if tx handler is separate add 1 for every tx queue */ 1019 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1020 numvecs += adapter->num_tx_queues; 1021 1022 /* store the number of vectors reserved for queues */ 1023 adapter->num_q_vectors = numvecs; 1024 1025 /* add 1 vector for link status interrupts */ 1026 numvecs++; 1027 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), 1028 GFP_KERNEL); 1029 1030 if (!adapter->msix_entries) 1031 goto msi_only; 1032 1033 for (i = 0; i < numvecs; i++) 1034 adapter->msix_entries[i].entry = i; 1035 1036 err = pci_enable_msix(adapter->pdev, 1037 adapter->msix_entries, 1038 numvecs); 1039 if (err == 0) 1040 goto out; 1041 1042 igb_reset_interrupt_capability(adapter); 1043 1044 /* If we can't do MSI-X, try MSI */ 1045msi_only: 1046#ifdef CONFIG_PCI_IOV 1047 /* disable SR-IOV for non MSI-X configurations */ 1048 if (adapter->vf_data) { 1049 struct e1000_hw *hw = &adapter->hw; 1050 /* disable iov and allow time for transactions to clear */ 1051 pci_disable_sriov(adapter->pdev); 1052 msleep(500); 1053 1054 kfree(adapter->vf_data); 1055 adapter->vf_data = NULL; 1056 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1057 wrfl(); 1058 msleep(100); 1059 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1060 } 1061#endif 1062 adapter->vfs_allocated_count = 0; 1063 adapter->rss_queues = 1; 1064 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1065 adapter->num_rx_queues = 1; 1066 adapter->num_tx_queues = 1; 1067 adapter->num_q_vectors = 1; 1068 if (!pci_enable_msi(adapter->pdev)) 1069 adapter->flags |= IGB_FLAG_HAS_MSI; 1070out: 1071 /* Notify the stack of the (possibly) reduced queue counts. */ 1072 rtnl_lock(); 1073 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); 1074 err = netif_set_real_num_rx_queues(adapter->netdev, 1075 adapter->num_rx_queues); 1076 rtnl_unlock(); 1077 return err; 1078} 1079 1080/** 1081 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1082 * @adapter: board private structure to initialize 1083 * 1084 * We allocate one q_vector per queue interrupt. If allocation fails we 1085 * return -ENOMEM. 1086 **/ 1087static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1088{ 1089 struct igb_q_vector *q_vector; 1090 struct e1000_hw *hw = &adapter->hw; 1091 int v_idx; 1092 1093 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 1094 q_vector = kzalloc(sizeof(struct igb_q_vector), 1095 GFP_KERNEL); 1096 if (!q_vector) 1097 goto err_out; 1098 q_vector->adapter = adapter; 1099 q_vector->itr_register = hw->hw_addr + E1000_EITR(0); 1100 q_vector->itr_val = IGB_START_ITR; 1101 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64); 1102 adapter->q_vector[v_idx] = q_vector; 1103 } 1104 1105 return 0; 1106 1107err_out: 1108 igb_free_q_vectors(adapter); 1109 return -ENOMEM; 1110} 1111 1112static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter, 1113 int ring_idx, int v_idx) 1114{ 1115 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1116 1117 q_vector->rx.ring = adapter->rx_ring[ring_idx]; 1118 q_vector->rx.ring->q_vector = q_vector; 1119 q_vector->rx.count++; 1120 q_vector->itr_val = adapter->rx_itr_setting; 1121 if (q_vector->itr_val && q_vector->itr_val <= 3) 1122 q_vector->itr_val = IGB_START_ITR; 1123} 1124 1125static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter, 1126 int ring_idx, int v_idx) 1127{ 1128 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1129 1130 q_vector->tx.ring = adapter->tx_ring[ring_idx]; 1131 q_vector->tx.ring->q_vector = q_vector; 1132 q_vector->tx.count++; 1133 q_vector->itr_val = adapter->tx_itr_setting; 1134 q_vector->tx.work_limit = adapter->tx_work_limit; 1135 if (q_vector->itr_val && q_vector->itr_val <= 3) 1136 q_vector->itr_val = IGB_START_ITR; 1137} 1138 1139/** 1140 * igb_map_ring_to_vector - maps allocated queues to vectors 1141 * 1142 * This function maps the recently allocated queues to vectors. 1143 **/ 1144static int igb_map_ring_to_vector(struct igb_adapter *adapter) 1145{ 1146 int i; 1147 int v_idx = 0; 1148 1149 if ((adapter->num_q_vectors < adapter->num_rx_queues) || 1150 (adapter->num_q_vectors < adapter->num_tx_queues)) 1151 return -ENOMEM; 1152 1153 if (adapter->num_q_vectors >= 1154 (adapter->num_rx_queues + adapter->num_tx_queues)) { 1155 for (i = 0; i < adapter->num_rx_queues; i++) 1156 igb_map_rx_ring_to_vector(adapter, i, v_idx++); 1157 for (i = 0; i < adapter->num_tx_queues; i++) 1158 igb_map_tx_ring_to_vector(adapter, i, v_idx++); 1159 } else { 1160 for (i = 0; i < adapter->num_rx_queues; i++) { 1161 if (i < adapter->num_tx_queues) 1162 igb_map_tx_ring_to_vector(adapter, i, v_idx); 1163 igb_map_rx_ring_to_vector(adapter, i, v_idx++); 1164 } 1165 for (; i < adapter->num_tx_queues; i++) 1166 igb_map_tx_ring_to_vector(adapter, i, v_idx++); 1167 } 1168 return 0; 1169} 1170 1171/** 1172 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1173 * 1174 * This function initializes the interrupts and allocates all of the queues. 1175 **/ 1176static int igb_init_interrupt_scheme(struct igb_adapter *adapter) 1177{ 1178 struct pci_dev *pdev = adapter->pdev; 1179 int err; 1180 1181 err = igb_set_interrupt_capability(adapter); 1182 if (err) 1183 return err; 1184 1185 err = igb_alloc_q_vectors(adapter); 1186 if (err) { 1187 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1188 goto err_alloc_q_vectors; 1189 } 1190 1191 err = igb_alloc_queues(adapter); 1192 if (err) { 1193 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 1194 goto err_alloc_queues; 1195 } 1196 1197 err = igb_map_ring_to_vector(adapter); 1198 if (err) { 1199 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n"); 1200 goto err_map_queues; 1201 } 1202 1203 1204 return 0; 1205err_map_queues: 1206 igb_free_queues(adapter); 1207err_alloc_queues: 1208 igb_free_q_vectors(adapter); 1209err_alloc_q_vectors: 1210 igb_reset_interrupt_capability(adapter); 1211 return err; 1212} 1213 1214/** 1215 * igb_request_irq - initialize interrupts 1216 * 1217 * Attempts to configure interrupts using the best available 1218 * capabilities of the hardware and kernel. 1219 **/ 1220static int igb_request_irq(struct igb_adapter *adapter) 1221{ 1222 struct net_device *netdev = adapter->netdev; 1223 struct pci_dev *pdev = adapter->pdev; 1224 int err = 0; 1225 1226 if (adapter->msix_entries) { 1227 err = igb_request_msix(adapter); 1228 if (!err) 1229 goto request_done; 1230 /* fall back to MSI */ 1231 igb_clear_interrupt_scheme(adapter); 1232 if (!pci_enable_msi(pdev)) 1233 adapter->flags |= IGB_FLAG_HAS_MSI; 1234 igb_free_all_tx_resources(adapter); 1235 igb_free_all_rx_resources(adapter); 1236 adapter->num_tx_queues = 1; 1237 adapter->num_rx_queues = 1; 1238 adapter->num_q_vectors = 1; 1239 err = igb_alloc_q_vectors(adapter); 1240 if (err) { 1241 dev_err(&pdev->dev, 1242 "Unable to allocate memory for vectors\n"); 1243 goto request_done; 1244 } 1245 err = igb_alloc_queues(adapter); 1246 if (err) { 1247 dev_err(&pdev->dev, 1248 "Unable to allocate memory for queues\n"); 1249 igb_free_q_vectors(adapter); 1250 goto request_done; 1251 } 1252 igb_setup_all_tx_resources(adapter); 1253 igb_setup_all_rx_resources(adapter); 1254 } 1255 1256 igb_assign_vector(adapter->q_vector[0], 0); 1257 1258 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1259 err = request_irq(pdev->irq, igb_intr_msi, 0, 1260 netdev->name, adapter); 1261 if (!err) 1262 goto request_done; 1263 1264 /* fall back to legacy interrupts */ 1265 igb_reset_interrupt_capability(adapter); 1266 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1267 } 1268 1269 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1270 netdev->name, adapter); 1271 1272 if (err) 1273 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1274 err); 1275 1276request_done: 1277 return err; 1278} 1279 1280static void igb_free_irq(struct igb_adapter *adapter) 1281{ 1282 if (adapter->msix_entries) { 1283 int vector = 0, i; 1284 1285 free_irq(adapter->msix_entries[vector++].vector, adapter); 1286 1287 for (i = 0; i < adapter->num_q_vectors; i++) 1288 free_irq(adapter->msix_entries[vector++].vector, 1289 adapter->q_vector[i]); 1290 } else { 1291 free_irq(adapter->pdev->irq, adapter); 1292 } 1293} 1294 1295/** 1296 * igb_irq_disable - Mask off interrupt generation on the NIC 1297 * @adapter: board private structure 1298 **/ 1299static void igb_irq_disable(struct igb_adapter *adapter) 1300{ 1301 struct e1000_hw *hw = &adapter->hw; 1302 1303 /* 1304 * we need to be careful when disabling interrupts. The VFs are also 1305 * mapped into these registers and so clearing the bits can cause 1306 * issues on the VF drivers so we only need to clear what we set 1307 */ 1308 if (adapter->msix_entries) { 1309 u32 regval = rd32(E1000_EIAM); 1310 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1311 wr32(E1000_EIMC, adapter->eims_enable_mask); 1312 regval = rd32(E1000_EIAC); 1313 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1314 } 1315 1316 wr32(E1000_IAM, 0); 1317 wr32(E1000_IMC, ~0); 1318 wrfl(); 1319 if (adapter->msix_entries) { 1320 int i; 1321 for (i = 0; i < adapter->num_q_vectors; i++) 1322 synchronize_irq(adapter->msix_entries[i].vector); 1323 } else { 1324 synchronize_irq(adapter->pdev->irq); 1325 } 1326} 1327 1328/** 1329 * igb_irq_enable - Enable default interrupt generation settings 1330 * @adapter: board private structure 1331 **/ 1332static void igb_irq_enable(struct igb_adapter *adapter) 1333{ 1334 struct e1000_hw *hw = &adapter->hw; 1335 1336 if (adapter->msix_entries) { 1337 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1338 u32 regval = rd32(E1000_EIAC); 1339 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1340 regval = rd32(E1000_EIAM); 1341 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1342 wr32(E1000_EIMS, adapter->eims_enable_mask); 1343 if (adapter->vfs_allocated_count) { 1344 wr32(E1000_MBVFIMR, 0xFF); 1345 ims |= E1000_IMS_VMMB; 1346 } 1347 wr32(E1000_IMS, ims); 1348 } else { 1349 wr32(E1000_IMS, IMS_ENABLE_MASK | 1350 E1000_IMS_DRSTA); 1351 wr32(E1000_IAM, IMS_ENABLE_MASK | 1352 E1000_IMS_DRSTA); 1353 } 1354} 1355 1356static void igb_update_mng_vlan(struct igb_adapter *adapter) 1357{ 1358 struct e1000_hw *hw = &adapter->hw; 1359 u16 vid = adapter->hw.mng_cookie.vlan_id; 1360 u16 old_vid = adapter->mng_vlan_id; 1361 1362 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1363 /* add VID to filter table */ 1364 igb_vfta_set(hw, vid, true); 1365 adapter->mng_vlan_id = vid; 1366 } else { 1367 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1368 } 1369 1370 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1371 (vid != old_vid) && 1372 !test_bit(old_vid, adapter->active_vlans)) { 1373 /* remove VID from filter table */ 1374 igb_vfta_set(hw, old_vid, false); 1375 } 1376} 1377 1378/** 1379 * igb_release_hw_control - release control of the h/w to f/w 1380 * @adapter: address of board private structure 1381 * 1382 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1383 * For ASF and Pass Through versions of f/w this means that the 1384 * driver is no longer loaded. 1385 * 1386 **/ 1387static void igb_release_hw_control(struct igb_adapter *adapter) 1388{ 1389 struct e1000_hw *hw = &adapter->hw; 1390 u32 ctrl_ext; 1391 1392 /* Let firmware take over control of h/w */ 1393 ctrl_ext = rd32(E1000_CTRL_EXT); 1394 wr32(E1000_CTRL_EXT, 1395 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1396} 1397 1398/** 1399 * igb_get_hw_control - get control of the h/w from f/w 1400 * @adapter: address of board private structure 1401 * 1402 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1403 * For ASF and Pass Through versions of f/w this means that 1404 * the driver is loaded. 1405 * 1406 **/ 1407static void igb_get_hw_control(struct igb_adapter *adapter) 1408{ 1409 struct e1000_hw *hw = &adapter->hw; 1410 u32 ctrl_ext; 1411 1412 /* Let firmware know the driver has taken over */ 1413 ctrl_ext = rd32(E1000_CTRL_EXT); 1414 wr32(E1000_CTRL_EXT, 1415 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1416} 1417 1418/** 1419 * igb_configure - configure the hardware for RX and TX 1420 * @adapter: private board structure 1421 **/ 1422static void igb_configure(struct igb_adapter *adapter) 1423{ 1424 struct net_device *netdev = adapter->netdev; 1425 int i; 1426 1427 igb_get_hw_control(adapter); 1428 igb_set_rx_mode(netdev); 1429 1430 igb_restore_vlan(adapter); 1431 1432 igb_setup_tctl(adapter); 1433 igb_setup_mrqc(adapter); 1434 igb_setup_rctl(adapter); 1435 1436 igb_configure_tx(adapter); 1437 igb_configure_rx(adapter); 1438 1439 igb_rx_fifo_flush_82575(&adapter->hw); 1440 1441 /* call igb_desc_unused which always leaves 1442 * at least 1 descriptor unused to make sure 1443 * next_to_use != next_to_clean */ 1444 for (i = 0; i < adapter->num_rx_queues; i++) { 1445 struct igb_ring *ring = adapter->rx_ring[i]; 1446 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1447 } 1448} 1449 1450/** 1451 * igb_power_up_link - Power up the phy/serdes link 1452 * @adapter: address of board private structure 1453 **/ 1454void igb_power_up_link(struct igb_adapter *adapter) 1455{ 1456 igb_reset_phy(&adapter->hw); 1457 1458 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1459 igb_power_up_phy_copper(&adapter->hw); 1460 else 1461 igb_power_up_serdes_link_82575(&adapter->hw); 1462} 1463 1464/** 1465 * igb_power_down_link - Power down the phy/serdes link 1466 * @adapter: address of board private structure 1467 */ 1468static void igb_power_down_link(struct igb_adapter *adapter) 1469{ 1470 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1471 igb_power_down_phy_copper_82575(&adapter->hw); 1472 else 1473 igb_shutdown_serdes_link_82575(&adapter->hw); 1474} 1475 1476/** 1477 * igb_up - Open the interface and prepare it to handle traffic 1478 * @adapter: board private structure 1479 **/ 1480int igb_up(struct igb_adapter *adapter) 1481{ 1482 struct e1000_hw *hw = &adapter->hw; 1483 int i; 1484 1485 /* hardware has been reset, we need to reload some things */ 1486 igb_configure(adapter); 1487 1488 clear_bit(__IGB_DOWN, &adapter->state); 1489 1490 for (i = 0; i < adapter->num_q_vectors; i++) 1491 napi_enable(&(adapter->q_vector[i]->napi)); 1492 1493 if (adapter->msix_entries) 1494 igb_configure_msix(adapter); 1495 else 1496 igb_assign_vector(adapter->q_vector[0], 0); 1497 1498 /* Clear any pending interrupts. */ 1499 rd32(E1000_ICR); 1500 igb_irq_enable(adapter); 1501 1502 /* notify VFs that reset has been completed */ 1503 if (adapter->vfs_allocated_count) { 1504 u32 reg_data = rd32(E1000_CTRL_EXT); 1505 reg_data |= E1000_CTRL_EXT_PFRSTD; 1506 wr32(E1000_CTRL_EXT, reg_data); 1507 } 1508 1509 netif_tx_start_all_queues(adapter->netdev); 1510 1511 /* start the watchdog. */ 1512 hw->mac.get_link_status = 1; 1513 schedule_work(&adapter->watchdog_task); 1514 1515 return 0; 1516} 1517 1518void igb_down(struct igb_adapter *adapter) 1519{ 1520 struct net_device *netdev = adapter->netdev; 1521 struct e1000_hw *hw = &adapter->hw; 1522 u32 tctl, rctl; 1523 int i; 1524 1525 /* signal that we're down so the interrupt handler does not 1526 * reschedule our watchdog timer */ 1527 set_bit(__IGB_DOWN, &adapter->state); 1528 1529 /* disable receives in the hardware */ 1530 rctl = rd32(E1000_RCTL); 1531 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1532 /* flush and sleep below */ 1533 1534 netif_tx_stop_all_queues(netdev); 1535 1536 /* disable transmits in the hardware */ 1537 tctl = rd32(E1000_TCTL); 1538 tctl &= ~E1000_TCTL_EN; 1539 wr32(E1000_TCTL, tctl); 1540 /* flush both disables and wait for them to finish */ 1541 wrfl(); 1542 msleep(10); 1543 1544 for (i = 0; i < adapter->num_q_vectors; i++) 1545 napi_disable(&(adapter->q_vector[i]->napi)); 1546 1547 igb_irq_disable(adapter); 1548 1549 del_timer_sync(&adapter->watchdog_timer); 1550 del_timer_sync(&adapter->phy_info_timer); 1551 1552 netif_carrier_off(netdev); 1553 1554 /* record the stats before reset*/ 1555 spin_lock(&adapter->stats64_lock); 1556 igb_update_stats(adapter, &adapter->stats64); 1557 spin_unlock(&adapter->stats64_lock); 1558 1559 adapter->link_speed = 0; 1560 adapter->link_duplex = 0; 1561 1562 if (!pci_channel_offline(adapter->pdev)) 1563 igb_reset(adapter); 1564 igb_clean_all_tx_rings(adapter); 1565 igb_clean_all_rx_rings(adapter); 1566#ifdef CONFIG_IGB_DCA 1567 1568 /* since we reset the hardware DCA settings were cleared */ 1569 igb_setup_dca(adapter); 1570#endif 1571} 1572 1573void igb_reinit_locked(struct igb_adapter *adapter) 1574{ 1575 WARN_ON(in_interrupt()); 1576 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1577 msleep(1); 1578 igb_down(adapter); 1579 igb_up(adapter); 1580 clear_bit(__IGB_RESETTING, &adapter->state); 1581} 1582 1583void igb_reset(struct igb_adapter *adapter) 1584{ 1585 struct pci_dev *pdev = adapter->pdev; 1586 struct e1000_hw *hw = &adapter->hw; 1587 struct e1000_mac_info *mac = &hw->mac; 1588 struct e1000_fc_info *fc = &hw->fc; 1589 u32 pba = 0, tx_space, min_tx_space, min_rx_space; 1590 u16 hwm; 1591 1592 /* Repartition Pba for greater than 9k mtu 1593 * To take effect CTRL.RST is required. 1594 */ 1595 switch (mac->type) { 1596 case e1000_i350: 1597 case e1000_82580: 1598 pba = rd32(E1000_RXPBS); 1599 pba = igb_rxpbs_adjust_82580(pba); 1600 break; 1601 case e1000_82576: 1602 pba = rd32(E1000_RXPBS); 1603 pba &= E1000_RXPBS_SIZE_MASK_82576; 1604 break; 1605 case e1000_82575: 1606 case e1000_i210: 1607 case e1000_i211: 1608 default: 1609 pba = E1000_PBA_34K; 1610 break; 1611 } 1612 1613 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1614 (mac->type < e1000_82576)) { 1615 /* adjust PBA for jumbo frames */ 1616 wr32(E1000_PBA, pba); 1617 1618 /* To maintain wire speed transmits, the Tx FIFO should be 1619 * large enough to accommodate two full transmit packets, 1620 * rounded up to the next 1KB and expressed in KB. Likewise, 1621 * the Rx FIFO should be large enough to accommodate at least 1622 * one full receive packet and is similarly rounded up and 1623 * expressed in KB. */ 1624 pba = rd32(E1000_PBA); 1625 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1626 tx_space = pba >> 16; 1627 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1628 pba &= 0xffff; 1629 /* the tx fifo also stores 16 bytes of information about the tx 1630 * but don't include ethernet FCS because hardware appends it */ 1631 min_tx_space = (adapter->max_frame_size + 1632 sizeof(union e1000_adv_tx_desc) - 1633 ETH_FCS_LEN) * 2; 1634 min_tx_space = ALIGN(min_tx_space, 1024); 1635 min_tx_space >>= 10; 1636 /* software strips receive CRC, so leave room for it */ 1637 min_rx_space = adapter->max_frame_size; 1638 min_rx_space = ALIGN(min_rx_space, 1024); 1639 min_rx_space >>= 10; 1640 1641 /* If current Tx allocation is less than the min Tx FIFO size, 1642 * and the min Tx FIFO size is less than the current Rx FIFO 1643 * allocation, take space away from current Rx allocation */ 1644 if (tx_space < min_tx_space && 1645 ((min_tx_space - tx_space) < pba)) { 1646 pba = pba - (min_tx_space - tx_space); 1647 1648 /* if short on rx space, rx wins and must trump tx 1649 * adjustment */ 1650 if (pba < min_rx_space) 1651 pba = min_rx_space; 1652 } 1653 wr32(E1000_PBA, pba); 1654 } 1655 1656 /* flow control settings */ 1657 /* The high water mark must be low enough to fit one full frame 1658 * (or the size used for early receive) above it in the Rx FIFO. 1659 * Set it to the lower of: 1660 * - 90% of the Rx FIFO size, or 1661 * - the full Rx FIFO size minus one full frame */ 1662 hwm = min(((pba << 10) * 9 / 10), 1663 ((pba << 10) - 2 * adapter->max_frame_size)); 1664 1665 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ 1666 fc->low_water = fc->high_water - 16; 1667 fc->pause_time = 0xFFFF; 1668 fc->send_xon = 1; 1669 fc->current_mode = fc->requested_mode; 1670 1671 /* disable receive for all VFs and wait one second */ 1672 if (adapter->vfs_allocated_count) { 1673 int i; 1674 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1675 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1676 1677 /* ping all the active vfs to let them know we are going down */ 1678 igb_ping_all_vfs(adapter); 1679 1680 /* disable transmits and receives */ 1681 wr32(E1000_VFRE, 0); 1682 wr32(E1000_VFTE, 0); 1683 } 1684 1685 /* Allow time for pending master requests to run */ 1686 hw->mac.ops.reset_hw(hw); 1687 wr32(E1000_WUC, 0); 1688 1689 if (hw->mac.ops.init_hw(hw)) 1690 dev_err(&pdev->dev, "Hardware Error\n"); 1691 1692 /* 1693 * Flow control settings reset on hardware reset, so guarantee flow 1694 * control is off when forcing speed. 1695 */ 1696 if (!hw->mac.autoneg) 1697 igb_force_mac_fc(hw); 1698 1699 igb_init_dmac(adapter, pba); 1700 if (!netif_running(adapter->netdev)) 1701 igb_power_down_link(adapter); 1702 1703 igb_update_mng_vlan(adapter); 1704 1705 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 1706 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 1707 1708#ifdef CONFIG_IGB_PTP 1709 /* Re-enable PTP, where applicable. */ 1710 igb_ptp_reset(adapter); 1711#endif /* CONFIG_IGB_PTP */ 1712 1713 igb_get_phy_info(hw); 1714} 1715 1716static netdev_features_t igb_fix_features(struct net_device *netdev, 1717 netdev_features_t features) 1718{ 1719 /* 1720 * Since there is no support for separate rx/tx vlan accel 1721 * enable/disable make sure tx flag is always in same state as rx. 1722 */ 1723 if (features & NETIF_F_HW_VLAN_RX) 1724 features |= NETIF_F_HW_VLAN_TX; 1725 else 1726 features &= ~NETIF_F_HW_VLAN_TX; 1727 1728 return features; 1729} 1730 1731static int igb_set_features(struct net_device *netdev, 1732 netdev_features_t features) 1733{ 1734 netdev_features_t changed = netdev->features ^ features; 1735 struct igb_adapter *adapter = netdev_priv(netdev); 1736 1737 if (changed & NETIF_F_HW_VLAN_RX) 1738 igb_vlan_mode(netdev, features); 1739 1740 if (!(changed & NETIF_F_RXALL)) 1741 return 0; 1742 1743 netdev->features = features; 1744 1745 if (netif_running(netdev)) 1746 igb_reinit_locked(adapter); 1747 else 1748 igb_reset(adapter); 1749 1750 return 0; 1751} 1752 1753static const struct net_device_ops igb_netdev_ops = { 1754 .ndo_open = igb_open, 1755 .ndo_stop = igb_close, 1756 .ndo_start_xmit = igb_xmit_frame, 1757 .ndo_get_stats64 = igb_get_stats64, 1758 .ndo_set_rx_mode = igb_set_rx_mode, 1759 .ndo_set_mac_address = igb_set_mac, 1760 .ndo_change_mtu = igb_change_mtu, 1761 .ndo_do_ioctl = igb_ioctl, 1762 .ndo_tx_timeout = igb_tx_timeout, 1763 .ndo_validate_addr = eth_validate_addr, 1764 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 1765 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 1766 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 1767 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 1768 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, 1769 .ndo_get_vf_config = igb_ndo_get_vf_config, 1770#ifdef CONFIG_NET_POLL_CONTROLLER 1771 .ndo_poll_controller = igb_netpoll, 1772#endif 1773 .ndo_fix_features = igb_fix_features, 1774 .ndo_set_features = igb_set_features, 1775}; 1776 1777/** 1778 * igb_set_fw_version - Configure version string for ethtool 1779 * @adapter: adapter struct 1780 * 1781 **/ 1782void igb_set_fw_version(struct igb_adapter *adapter) 1783{ 1784 struct e1000_hw *hw = &adapter->hw; 1785 u16 eeprom_verh, eeprom_verl, comb_verh, comb_verl, comb_offset; 1786 u16 major, build, patch, fw_version; 1787 u32 etrack_id; 1788 1789 hw->nvm.ops.read(hw, 5, 1, &fw_version); 1790 if (adapter->hw.mac.type != e1000_i211) { 1791 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh); 1792 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl); 1793 etrack_id = (eeprom_verh << IGB_ETRACK_SHIFT) | eeprom_verl; 1794 1795 /* combo image version needs to be found */ 1796 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset); 1797 if ((comb_offset != 0x0) && 1798 (comb_offset != IGB_NVM_VER_INVALID)) { 1799 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset 1800 + 1), 1, &comb_verh); 1801 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset), 1802 1, &comb_verl); 1803 1804 /* Only display Option Rom if it exists and is valid */ 1805 if ((comb_verh && comb_verl) && 1806 ((comb_verh != IGB_NVM_VER_INVALID) && 1807 (comb_verl != IGB_NVM_VER_INVALID))) { 1808 major = comb_verl >> IGB_COMB_VER_SHFT; 1809 build = (comb_verl << IGB_COMB_VER_SHFT) | 1810 (comb_verh >> IGB_COMB_VER_SHFT); 1811 patch = comb_verh & IGB_COMB_VER_MASK; 1812 snprintf(adapter->fw_version, 1813 sizeof(adapter->fw_version), 1814 "%d.%d%d, 0x%08x, %d.%d.%d", 1815 (fw_version & IGB_MAJOR_MASK) >> 1816 IGB_MAJOR_SHIFT, 1817 (fw_version & IGB_MINOR_MASK) >> 1818 IGB_MINOR_SHIFT, 1819 (fw_version & IGB_BUILD_MASK), 1820 etrack_id, major, build, patch); 1821 goto out; 1822 } 1823 } 1824 snprintf(adapter->fw_version, sizeof(adapter->fw_version), 1825 "%d.%d%d, 0x%08x", 1826 (fw_version & IGB_MAJOR_MASK) >> IGB_MAJOR_SHIFT, 1827 (fw_version & IGB_MINOR_MASK) >> IGB_MINOR_SHIFT, 1828 (fw_version & IGB_BUILD_MASK), etrack_id); 1829 } else { 1830 snprintf(adapter->fw_version, sizeof(adapter->fw_version), 1831 "%d.%d%d", 1832 (fw_version & IGB_MAJOR_MASK) >> IGB_MAJOR_SHIFT, 1833 (fw_version & IGB_MINOR_MASK) >> IGB_MINOR_SHIFT, 1834 (fw_version & IGB_BUILD_MASK)); 1835 } 1836out: 1837 return; 1838} 1839 1840/** 1841 * igb_probe - Device Initialization Routine 1842 * @pdev: PCI device information struct 1843 * @ent: entry in igb_pci_tbl 1844 * 1845 * Returns 0 on success, negative on failure 1846 * 1847 * igb_probe initializes an adapter identified by a pci_dev structure. 1848 * The OS initialization, configuring of the adapter private structure, 1849 * and a hardware reset occur. 1850 **/ 1851static int __devinit igb_probe(struct pci_dev *pdev, 1852 const struct pci_device_id *ent) 1853{ 1854 struct net_device *netdev; 1855 struct igb_adapter *adapter; 1856 struct e1000_hw *hw; 1857 u16 eeprom_data = 0; 1858 s32 ret_val; 1859 static int global_quad_port_a; /* global quad port a indication */ 1860 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 1861 unsigned long mmio_start, mmio_len; 1862 int err, pci_using_dac; 1863 u16 eeprom_apme_mask = IGB_EEPROM_APME; 1864 u8 part_str[E1000_PBANUM_LENGTH]; 1865 1866 /* Catch broken hardware that put the wrong VF device ID in 1867 * the PCIe SR-IOV capability. 1868 */ 1869 if (pdev->is_virtfn) { 1870 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 1871 pci_name(pdev), pdev->vendor, pdev->device); 1872 return -EINVAL; 1873 } 1874 1875 err = pci_enable_device_mem(pdev); 1876 if (err) 1877 return err; 1878 1879 pci_using_dac = 0; 1880 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 1881 if (!err) { 1882 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 1883 if (!err) 1884 pci_using_dac = 1; 1885 } else { 1886 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1887 if (err) { 1888 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 1889 if (err) { 1890 dev_err(&pdev->dev, "No usable DMA " 1891 "configuration, aborting\n"); 1892 goto err_dma; 1893 } 1894 } 1895 } 1896 1897 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 1898 IORESOURCE_MEM), 1899 igb_driver_name); 1900 if (err) 1901 goto err_pci_reg; 1902 1903 pci_enable_pcie_error_reporting(pdev); 1904 1905 pci_set_master(pdev); 1906 pci_save_state(pdev); 1907 1908 err = -ENOMEM; 1909 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 1910 IGB_MAX_TX_QUEUES); 1911 if (!netdev) 1912 goto err_alloc_etherdev; 1913 1914 SET_NETDEV_DEV(netdev, &pdev->dev); 1915 1916 pci_set_drvdata(pdev, netdev); 1917 adapter = netdev_priv(netdev); 1918 adapter->netdev = netdev; 1919 adapter->pdev = pdev; 1920 hw = &adapter->hw; 1921 hw->back = adapter; 1922 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 1923 1924 mmio_start = pci_resource_start(pdev, 0); 1925 mmio_len = pci_resource_len(pdev, 0); 1926 1927 err = -EIO; 1928 hw->hw_addr = ioremap(mmio_start, mmio_len); 1929 if (!hw->hw_addr) 1930 goto err_ioremap; 1931 1932 netdev->netdev_ops = &igb_netdev_ops; 1933 igb_set_ethtool_ops(netdev); 1934 netdev->watchdog_timeo = 5 * HZ; 1935 1936 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 1937 1938 netdev->mem_start = mmio_start; 1939 netdev->mem_end = mmio_start + mmio_len; 1940 1941 /* PCI config space info */ 1942 hw->vendor_id = pdev->vendor; 1943 hw->device_id = pdev->device; 1944 hw->revision_id = pdev->revision; 1945 hw->subsystem_vendor_id = pdev->subsystem_vendor; 1946 hw->subsystem_device_id = pdev->subsystem_device; 1947 1948 /* Copy the default MAC, PHY and NVM function pointers */ 1949 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 1950 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 1951 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 1952 /* Initialize skew-specific constants */ 1953 err = ei->get_invariants(hw); 1954 if (err) 1955 goto err_sw_init; 1956 1957 /* setup the private structure */ 1958 err = igb_sw_init(adapter); 1959 if (err) 1960 goto err_sw_init; 1961 1962 igb_get_bus_info_pcie(hw); 1963 1964 hw->phy.autoneg_wait_to_complete = false; 1965 1966 /* Copper options */ 1967 if (hw->phy.media_type == e1000_media_type_copper) { 1968 hw->phy.mdix = AUTO_ALL_MODES; 1969 hw->phy.disable_polarity_correction = false; 1970 hw->phy.ms_type = e1000_ms_hw_default; 1971 } 1972 1973 if (igb_check_reset_block(hw)) 1974 dev_info(&pdev->dev, 1975 "PHY reset is blocked due to SOL/IDER session.\n"); 1976 1977 /* 1978 * features is initialized to 0 in allocation, it might have bits 1979 * set by igb_sw_init so we should use an or instead of an 1980 * assignment. 1981 */ 1982 netdev->features |= NETIF_F_SG | 1983 NETIF_F_IP_CSUM | 1984 NETIF_F_IPV6_CSUM | 1985 NETIF_F_TSO | 1986 NETIF_F_TSO6 | 1987 NETIF_F_RXHASH | 1988 NETIF_F_RXCSUM | 1989 NETIF_F_HW_VLAN_RX | 1990 NETIF_F_HW_VLAN_TX; 1991 1992 /* copy netdev features into list of user selectable features */ 1993 netdev->hw_features |= netdev->features; 1994 netdev->hw_features |= NETIF_F_RXALL; 1995 1996 /* set this bit last since it cannot be part of hw_features */ 1997 netdev->features |= NETIF_F_HW_VLAN_FILTER; 1998 1999 netdev->vlan_features |= NETIF_F_TSO | 2000 NETIF_F_TSO6 | 2001 NETIF_F_IP_CSUM | 2002 NETIF_F_IPV6_CSUM | 2003 NETIF_F_SG; 2004 2005 netdev->priv_flags |= IFF_SUPP_NOFCS; 2006 2007 if (pci_using_dac) { 2008 netdev->features |= NETIF_F_HIGHDMA; 2009 netdev->vlan_features |= NETIF_F_HIGHDMA; 2010 } 2011 2012 if (hw->mac.type >= e1000_82576) { 2013 netdev->hw_features |= NETIF_F_SCTP_CSUM; 2014 netdev->features |= NETIF_F_SCTP_CSUM; 2015 } 2016 2017 netdev->priv_flags |= IFF_UNICAST_FLT; 2018 2019 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2020 2021 /* before reading the NVM, reset the controller to put the device in a 2022 * known good starting state */ 2023 hw->mac.ops.reset_hw(hw); 2024 2025 /* 2026 * make sure the NVM is good , i211 parts have special NVM that 2027 * doesn't contain a checksum 2028 */ 2029 if (hw->mac.type != e1000_i211) { 2030 if (hw->nvm.ops.validate(hw) < 0) { 2031 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2032 err = -EIO; 2033 goto err_eeprom; 2034 } 2035 } 2036 2037 /* copy the MAC address out of the NVM */ 2038 if (hw->mac.ops.read_mac_addr(hw)) 2039 dev_err(&pdev->dev, "NVM Read Error\n"); 2040 2041 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2042 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); 2043 2044 if (!is_valid_ether_addr(netdev->perm_addr)) { 2045 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2046 err = -EIO; 2047 goto err_eeprom; 2048 } 2049 2050 /* get firmware version for ethtool -i */ 2051 igb_set_fw_version(adapter); 2052 2053 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2054 (unsigned long) adapter); 2055 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2056 (unsigned long) adapter); 2057 2058 INIT_WORK(&adapter->reset_task, igb_reset_task); 2059 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2060 2061 /* Initialize link properties that are user-changeable */ 2062 adapter->fc_autoneg = true; 2063 hw->mac.autoneg = true; 2064 hw->phy.autoneg_advertised = 0x2f; 2065 2066 hw->fc.requested_mode = e1000_fc_default; 2067 hw->fc.current_mode = e1000_fc_default; 2068 2069 igb_validate_mdi_setting(hw); 2070 2071 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, 2072 * enable the ACPI Magic Packet filter 2073 */ 2074 2075 if (hw->bus.func == 0) 2076 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 2077 else if (hw->mac.type >= e1000_82580) 2078 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2079 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2080 &eeprom_data); 2081 else if (hw->bus.func == 1) 2082 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2083 2084 if (eeprom_data & eeprom_apme_mask) 2085 adapter->eeprom_wol |= E1000_WUFC_MAG; 2086 2087 /* now that we have the eeprom settings, apply the special cases where 2088 * the eeprom may be wrong or the board simply won't support wake on 2089 * lan on a particular port */ 2090 switch (pdev->device) { 2091 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2092 adapter->eeprom_wol = 0; 2093 break; 2094 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2095 case E1000_DEV_ID_82576_FIBER: 2096 case E1000_DEV_ID_82576_SERDES: 2097 /* Wake events only supported on port A for dual fiber 2098 * regardless of eeprom setting */ 2099 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2100 adapter->eeprom_wol = 0; 2101 break; 2102 case E1000_DEV_ID_82576_QUAD_COPPER: 2103 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2104 /* if quad port adapter, disable WoL on all but port A */ 2105 if (global_quad_port_a != 0) 2106 adapter->eeprom_wol = 0; 2107 else 2108 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2109 /* Reset for multiple quad port adapters */ 2110 if (++global_quad_port_a == 4) 2111 global_quad_port_a = 0; 2112 break; 2113 } 2114 2115 /* initialize the wol settings based on the eeprom settings */ 2116 adapter->wol = adapter->eeprom_wol; 2117 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2118 2119 /* reset the hardware with the new settings */ 2120 igb_reset(adapter); 2121 2122 /* let the f/w know that the h/w is now under the control of the 2123 * driver. */ 2124 igb_get_hw_control(adapter); 2125 2126 strcpy(netdev->name, "eth%d"); 2127 err = register_netdev(netdev); 2128 if (err) 2129 goto err_register; 2130 2131 /* carrier off reporting is important to ethtool even BEFORE open */ 2132 netif_carrier_off(netdev); 2133 2134#ifdef CONFIG_IGB_DCA 2135 if (dca_add_requester(&pdev->dev) == 0) { 2136 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2137 dev_info(&pdev->dev, "DCA enabled\n"); 2138 igb_setup_dca(adapter); 2139 } 2140 2141#endif 2142 2143#ifdef CONFIG_IGB_PTP 2144 /* do hw tstamp init after resetting */ 2145 igb_ptp_init(adapter); 2146#endif /* CONFIG_IGB_PTP */ 2147 2148 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2149 /* print bus type/speed/width info */ 2150 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2151 netdev->name, 2152 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2153 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2154 "unknown"), 2155 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 2156 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" : 2157 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" : 2158 "unknown"), 2159 netdev->dev_addr); 2160 2161 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH); 2162 if (ret_val) 2163 strcpy(part_str, "Unknown"); 2164 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2165 dev_info(&pdev->dev, 2166 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2167 adapter->msix_entries ? "MSI-X" : 2168 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2169 adapter->num_rx_queues, adapter->num_tx_queues); 2170 switch (hw->mac.type) { 2171 case e1000_i350: 2172 case e1000_i210: 2173 case e1000_i211: 2174 igb_set_eee_i350(hw); 2175 break; 2176 default: 2177 break; 2178 } 2179 2180 pm_runtime_put_noidle(&pdev->dev); 2181 return 0; 2182 2183err_register: 2184 igb_release_hw_control(adapter); 2185err_eeprom: 2186 if (!igb_check_reset_block(hw)) 2187 igb_reset_phy(hw); 2188 2189 if (hw->flash_address) 2190 iounmap(hw->flash_address); 2191err_sw_init: 2192 igb_clear_interrupt_scheme(adapter); 2193 iounmap(hw->hw_addr); 2194err_ioremap: 2195 free_netdev(netdev); 2196err_alloc_etherdev: 2197 pci_release_selected_regions(pdev, 2198 pci_select_bars(pdev, IORESOURCE_MEM)); 2199err_pci_reg: 2200err_dma: 2201 pci_disable_device(pdev); 2202 return err; 2203} 2204 2205/** 2206 * igb_remove - Device Removal Routine 2207 * @pdev: PCI device information struct 2208 * 2209 * igb_remove is called by the PCI subsystem to alert the driver 2210 * that it should release a PCI device. The could be caused by a 2211 * Hot-Plug event, or because the driver is going to be removed from 2212 * memory. 2213 **/ 2214static void __devexit igb_remove(struct pci_dev *pdev) 2215{ 2216 struct net_device *netdev = pci_get_drvdata(pdev); 2217 struct igb_adapter *adapter = netdev_priv(netdev); 2218 struct e1000_hw *hw = &adapter->hw; 2219 2220 pm_runtime_get_noresume(&pdev->dev); 2221#ifdef CONFIG_IGB_PTP 2222 igb_ptp_stop(adapter); 2223#endif /* CONFIG_IGB_PTP */ 2224 2225 /* 2226 * The watchdog timer may be rescheduled, so explicitly 2227 * disable watchdog from being rescheduled. 2228 */ 2229 set_bit(__IGB_DOWN, &adapter->state); 2230 del_timer_sync(&adapter->watchdog_timer); 2231 del_timer_sync(&adapter->phy_info_timer); 2232 2233 cancel_work_sync(&adapter->reset_task); 2234 cancel_work_sync(&adapter->watchdog_task); 2235 2236#ifdef CONFIG_IGB_DCA 2237 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2238 dev_info(&pdev->dev, "DCA disabled\n"); 2239 dca_remove_requester(&pdev->dev); 2240 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2241 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2242 } 2243#endif 2244 2245 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2246 * would have already happened in close and is redundant. */ 2247 igb_release_hw_control(adapter); 2248 2249 unregister_netdev(netdev); 2250 2251 igb_clear_interrupt_scheme(adapter); 2252 2253#ifdef CONFIG_PCI_IOV 2254 /* reclaim resources allocated to VFs */ 2255 if (adapter->vf_data) { 2256 /* disable iov and allow time for transactions to clear */ 2257 if (igb_vfs_are_assigned(adapter)) { 2258 dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n"); 2259 } else { 2260 pci_disable_sriov(pdev); 2261 msleep(500); 2262 } 2263 2264 kfree(adapter->vf_data); 2265 adapter->vf_data = NULL; 2266 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2267 wrfl(); 2268 msleep(100); 2269 dev_info(&pdev->dev, "IOV Disabled\n"); 2270 } 2271#endif 2272 2273 iounmap(hw->hw_addr); 2274 if (hw->flash_address) 2275 iounmap(hw->flash_address); 2276 pci_release_selected_regions(pdev, 2277 pci_select_bars(pdev, IORESOURCE_MEM)); 2278 2279 kfree(adapter->shadow_vfta); 2280 free_netdev(netdev); 2281 2282 pci_disable_pcie_error_reporting(pdev); 2283 2284 pci_disable_device(pdev); 2285} 2286 2287/** 2288 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2289 * @adapter: board private structure to initialize 2290 * 2291 * This function initializes the vf specific data storage and then attempts to 2292 * allocate the VFs. The reason for ordering it this way is because it is much 2293 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2294 * the memory for the VFs. 2295 **/ 2296static void __devinit igb_probe_vfs(struct igb_adapter * adapter) 2297{ 2298#ifdef CONFIG_PCI_IOV 2299 struct pci_dev *pdev = adapter->pdev; 2300 struct e1000_hw *hw = &adapter->hw; 2301 int old_vfs = pci_num_vf(adapter->pdev); 2302 int i; 2303 2304 /* Virtualization features not supported on i210 family. */ 2305 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2306 return; 2307 2308 if (old_vfs) { 2309 dev_info(&pdev->dev, "%d pre-allocated VFs found - override " 2310 "max_vfs setting of %d\n", old_vfs, max_vfs); 2311 adapter->vfs_allocated_count = old_vfs; 2312 } 2313 2314 if (!adapter->vfs_allocated_count) 2315 return; 2316 2317 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2318 sizeof(struct vf_data_storage), GFP_KERNEL); 2319 2320 /* if allocation failed then we do not support SR-IOV */ 2321 if (!adapter->vf_data) { 2322 adapter->vfs_allocated_count = 0; 2323 dev_err(&pdev->dev, "Unable to allocate memory for VF " 2324 "Data Storage\n"); 2325 goto out; 2326 } 2327 2328 if (!old_vfs) { 2329 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) 2330 goto err_out; 2331 } 2332 dev_info(&pdev->dev, "%d VFs allocated\n", 2333 adapter->vfs_allocated_count); 2334 for (i = 0; i < adapter->vfs_allocated_count; i++) 2335 igb_vf_configure(adapter, i); 2336 2337 /* DMA Coalescing is not supported in IOV mode. */ 2338 adapter->flags &= ~IGB_FLAG_DMAC; 2339 goto out; 2340err_out: 2341 kfree(adapter->vf_data); 2342 adapter->vf_data = NULL; 2343 adapter->vfs_allocated_count = 0; 2344out: 2345 return; 2346#endif /* CONFIG_PCI_IOV */ 2347} 2348 2349/** 2350 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2351 * @adapter: board private structure to initialize 2352 * 2353 * igb_sw_init initializes the Adapter private data structure. 2354 * Fields are initialized based on PCI device information and 2355 * OS network device settings (MTU size). 2356 **/ 2357static int __devinit igb_sw_init(struct igb_adapter *adapter) 2358{ 2359 struct e1000_hw *hw = &adapter->hw; 2360 struct net_device *netdev = adapter->netdev; 2361 struct pci_dev *pdev = adapter->pdev; 2362 u32 max_rss_queues; 2363 2364 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2365 2366 /* set default ring sizes */ 2367 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2368 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2369 2370 /* set default ITR values */ 2371 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2372 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2373 2374 /* set default work limits */ 2375 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2376 2377 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2378 VLAN_HLEN; 2379 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2380 2381 spin_lock_init(&adapter->stats64_lock); 2382#ifdef CONFIG_PCI_IOV 2383 switch (hw->mac.type) { 2384 case e1000_82576: 2385 case e1000_i350: 2386 if (max_vfs > 7) { 2387 dev_warn(&pdev->dev, 2388 "Maximum of 7 VFs per PF, using max\n"); 2389 adapter->vfs_allocated_count = 7; 2390 } else 2391 adapter->vfs_allocated_count = max_vfs; 2392 break; 2393 default: 2394 break; 2395 } 2396#endif /* CONFIG_PCI_IOV */ 2397 2398 /* Determine the maximum number of RSS queues supported. */ 2399 switch (hw->mac.type) { 2400 case e1000_i211: 2401 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2402 break; 2403 case e1000_82575: 2404 case e1000_i210: 2405 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2406 break; 2407 case e1000_i350: 2408 /* I350 cannot do RSS and SR-IOV at the same time */ 2409 if (!!adapter->vfs_allocated_count) { 2410 max_rss_queues = 1; 2411 break; 2412 } 2413 /* fall through */ 2414 case e1000_82576: 2415 if (!!adapter->vfs_allocated_count) { 2416 max_rss_queues = 2; 2417 break; 2418 } 2419 /* fall through */ 2420 case e1000_82580: 2421 default: 2422 max_rss_queues = IGB_MAX_RX_QUEUES; 2423 break; 2424 } 2425 2426 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2427 2428 /* Determine if we need to pair queues. */ 2429 switch (hw->mac.type) { 2430 case e1000_82575: 2431 case e1000_i211: 2432 /* Device supports enough interrupts without queue pairing. */ 2433 break; 2434 case e1000_82576: 2435 /* 2436 * If VFs are going to be allocated with RSS queues then we 2437 * should pair the queues in order to conserve interrupts due 2438 * to limited supply. 2439 */ 2440 if ((adapter->rss_queues > 1) && 2441 (adapter->vfs_allocated_count > 6)) 2442 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2443 /* fall through */ 2444 case e1000_82580: 2445 case e1000_i350: 2446 case e1000_i210: 2447 default: 2448 /* 2449 * If rss_queues > half of max_rss_queues, pair the queues in 2450 * order to conserve interrupts due to limited supply. 2451 */ 2452 if (adapter->rss_queues > (max_rss_queues / 2)) 2453 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2454 break; 2455 } 2456 2457 /* Setup and initialize a copy of the hw vlan table array */ 2458 adapter->shadow_vfta = kzalloc(sizeof(u32) * 2459 E1000_VLAN_FILTER_TBL_SIZE, 2460 GFP_ATOMIC); 2461 2462 /* This call may decrease the number of queues */ 2463 if (igb_init_interrupt_scheme(adapter)) { 2464 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2465 return -ENOMEM; 2466 } 2467 2468 igb_probe_vfs(adapter); 2469 2470 /* Explicitly disable IRQ since the NIC can be in any state. */ 2471 igb_irq_disable(adapter); 2472 2473 if (hw->mac.type >= e1000_i350) 2474 adapter->flags &= ~IGB_FLAG_DMAC; 2475 2476 set_bit(__IGB_DOWN, &adapter->state); 2477 return 0; 2478} 2479 2480/** 2481 * igb_open - Called when a network interface is made active 2482 * @netdev: network interface device structure 2483 * 2484 * Returns 0 on success, negative value on failure 2485 * 2486 * The open entry point is called when a network interface is made 2487 * active by the system (IFF_UP). At this point all resources needed 2488 * for transmit and receive operations are allocated, the interrupt 2489 * handler is registered with the OS, the watchdog timer is started, 2490 * and the stack is notified that the interface is ready. 2491 **/ 2492static int __igb_open(struct net_device *netdev, bool resuming) 2493{ 2494 struct igb_adapter *adapter = netdev_priv(netdev); 2495 struct e1000_hw *hw = &adapter->hw; 2496 struct pci_dev *pdev = adapter->pdev; 2497 int err; 2498 int i; 2499 2500 /* disallow open during test */ 2501 if (test_bit(__IGB_TESTING, &adapter->state)) { 2502 WARN_ON(resuming); 2503 return -EBUSY; 2504 } 2505 2506 if (!resuming) 2507 pm_runtime_get_sync(&pdev->dev); 2508 2509 netif_carrier_off(netdev); 2510 2511 /* allocate transmit descriptors */ 2512 err = igb_setup_all_tx_resources(adapter); 2513 if (err) 2514 goto err_setup_tx; 2515 2516 /* allocate receive descriptors */ 2517 err = igb_setup_all_rx_resources(adapter); 2518 if (err) 2519 goto err_setup_rx; 2520 2521 igb_power_up_link(adapter); 2522 2523 /* before we allocate an interrupt, we must be ready to handle it. 2524 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 2525 * as soon as we call pci_request_irq, so we have to setup our 2526 * clean_rx handler before we do so. */ 2527 igb_configure(adapter); 2528 2529 err = igb_request_irq(adapter); 2530 if (err) 2531 goto err_req_irq; 2532 2533 /* From here on the code is the same as igb_up() */ 2534 clear_bit(__IGB_DOWN, &adapter->state); 2535 2536 for (i = 0; i < adapter->num_q_vectors; i++) 2537 napi_enable(&(adapter->q_vector[i]->napi)); 2538 2539 /* Clear any pending interrupts. */ 2540 rd32(E1000_ICR); 2541 2542 igb_irq_enable(adapter); 2543 2544 /* notify VFs that reset has been completed */ 2545 if (adapter->vfs_allocated_count) { 2546 u32 reg_data = rd32(E1000_CTRL_EXT); 2547 reg_data |= E1000_CTRL_EXT_PFRSTD; 2548 wr32(E1000_CTRL_EXT, reg_data); 2549 } 2550 2551 netif_tx_start_all_queues(netdev); 2552 2553 if (!resuming) 2554 pm_runtime_put(&pdev->dev); 2555 2556 /* start the watchdog. */ 2557 hw->mac.get_link_status = 1; 2558 schedule_work(&adapter->watchdog_task); 2559 2560 return 0; 2561 2562err_req_irq: 2563 igb_release_hw_control(adapter); 2564 igb_power_down_link(adapter); 2565 igb_free_all_rx_resources(adapter); 2566err_setup_rx: 2567 igb_free_all_tx_resources(adapter); 2568err_setup_tx: 2569 igb_reset(adapter); 2570 if (!resuming) 2571 pm_runtime_put(&pdev->dev); 2572 2573 return err; 2574} 2575 2576static int igb_open(struct net_device *netdev) 2577{ 2578 return __igb_open(netdev, false); 2579} 2580 2581/** 2582 * igb_close - Disables a network interface 2583 * @netdev: network interface device structure 2584 * 2585 * Returns 0, this is not allowed to fail 2586 * 2587 * The close entry point is called when an interface is de-activated 2588 * by the OS. The hardware is still under the driver's control, but 2589 * needs to be disabled. A global MAC reset is issued to stop the 2590 * hardware, and all transmit and receive resources are freed. 2591 **/ 2592static int __igb_close(struct net_device *netdev, bool suspending) 2593{ 2594 struct igb_adapter *adapter = netdev_priv(netdev); 2595 struct pci_dev *pdev = adapter->pdev; 2596 2597 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 2598 2599 if (!suspending) 2600 pm_runtime_get_sync(&pdev->dev); 2601 2602 igb_down(adapter); 2603 igb_free_irq(adapter); 2604 2605 igb_free_all_tx_resources(adapter); 2606 igb_free_all_rx_resources(adapter); 2607 2608 if (!suspending) 2609 pm_runtime_put_sync(&pdev->dev); 2610 return 0; 2611} 2612 2613static int igb_close(struct net_device *netdev) 2614{ 2615 return __igb_close(netdev, false); 2616} 2617 2618/** 2619 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 2620 * @tx_ring: tx descriptor ring (for a specific queue) to setup 2621 * 2622 * Return 0 on success, negative on failure 2623 **/ 2624int igb_setup_tx_resources(struct igb_ring *tx_ring) 2625{ 2626 struct device *dev = tx_ring->dev; 2627 int size; 2628 2629 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 2630 2631 tx_ring->tx_buffer_info = vzalloc(size); 2632 if (!tx_ring->tx_buffer_info) 2633 goto err; 2634 2635 /* round up to nearest 4K */ 2636 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 2637 tx_ring->size = ALIGN(tx_ring->size, 4096); 2638 2639 tx_ring->desc = dma_alloc_coherent(dev, 2640 tx_ring->size, 2641 &tx_ring->dma, 2642 GFP_KERNEL); 2643 if (!tx_ring->desc) 2644 goto err; 2645 2646 tx_ring->next_to_use = 0; 2647 tx_ring->next_to_clean = 0; 2648 2649 return 0; 2650 2651err: 2652 vfree(tx_ring->tx_buffer_info); 2653 tx_ring->tx_buffer_info = NULL; 2654 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 2655 return -ENOMEM; 2656} 2657 2658/** 2659 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 2660 * (Descriptors) for all queues 2661 * @adapter: board private structure 2662 * 2663 * Return 0 on success, negative on failure 2664 **/ 2665static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 2666{ 2667 struct pci_dev *pdev = adapter->pdev; 2668 int i, err = 0; 2669 2670 for (i = 0; i < adapter->num_tx_queues; i++) { 2671 err = igb_setup_tx_resources(adapter->tx_ring[i]); 2672 if (err) { 2673 dev_err(&pdev->dev, 2674 "Allocation for Tx Queue %u failed\n", i); 2675 for (i--; i >= 0; i--) 2676 igb_free_tx_resources(adapter->tx_ring[i]); 2677 break; 2678 } 2679 } 2680 2681 return err; 2682} 2683 2684/** 2685 * igb_setup_tctl - configure the transmit control registers 2686 * @adapter: Board private structure 2687 **/ 2688void igb_setup_tctl(struct igb_adapter *adapter) 2689{ 2690 struct e1000_hw *hw = &adapter->hw; 2691 u32 tctl; 2692 2693 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 2694 wr32(E1000_TXDCTL(0), 0); 2695 2696 /* Program the Transmit Control Register */ 2697 tctl = rd32(E1000_TCTL); 2698 tctl &= ~E1000_TCTL_CT; 2699 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2700 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2701 2702 igb_config_collision_dist(hw); 2703 2704 /* Enable transmits */ 2705 tctl |= E1000_TCTL_EN; 2706 2707 wr32(E1000_TCTL, tctl); 2708} 2709 2710/** 2711 * igb_configure_tx_ring - Configure transmit ring after Reset 2712 * @adapter: board private structure 2713 * @ring: tx ring to configure 2714 * 2715 * Configure a transmit ring after a reset. 2716 **/ 2717void igb_configure_tx_ring(struct igb_adapter *adapter, 2718 struct igb_ring *ring) 2719{ 2720 struct e1000_hw *hw = &adapter->hw; 2721 u32 txdctl = 0; 2722 u64 tdba = ring->dma; 2723 int reg_idx = ring->reg_idx; 2724 2725 /* disable the queue */ 2726 wr32(E1000_TXDCTL(reg_idx), 0); 2727 wrfl(); 2728 mdelay(10); 2729 2730 wr32(E1000_TDLEN(reg_idx), 2731 ring->count * sizeof(union e1000_adv_tx_desc)); 2732 wr32(E1000_TDBAL(reg_idx), 2733 tdba & 0x00000000ffffffffULL); 2734 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 2735 2736 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 2737 wr32(E1000_TDH(reg_idx), 0); 2738 writel(0, ring->tail); 2739 2740 txdctl |= IGB_TX_PTHRESH; 2741 txdctl |= IGB_TX_HTHRESH << 8; 2742 txdctl |= IGB_TX_WTHRESH << 16; 2743 2744 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 2745 wr32(E1000_TXDCTL(reg_idx), txdctl); 2746} 2747 2748/** 2749 * igb_configure_tx - Configure transmit Unit after Reset 2750 * @adapter: board private structure 2751 * 2752 * Configure the Tx unit of the MAC after a reset. 2753 **/ 2754static void igb_configure_tx(struct igb_adapter *adapter) 2755{ 2756 int i; 2757 2758 for (i = 0; i < adapter->num_tx_queues; i++) 2759 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 2760} 2761 2762/** 2763 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 2764 * @rx_ring: rx descriptor ring (for a specific queue) to setup 2765 * 2766 * Returns 0 on success, negative on failure 2767 **/ 2768int igb_setup_rx_resources(struct igb_ring *rx_ring) 2769{ 2770 struct device *dev = rx_ring->dev; 2771 int size; 2772 2773 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 2774 2775 rx_ring->rx_buffer_info = vzalloc(size); 2776 if (!rx_ring->rx_buffer_info) 2777 goto err; 2778 2779 2780 /* Round up to nearest 4K */ 2781 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 2782 rx_ring->size = ALIGN(rx_ring->size, 4096); 2783 2784 rx_ring->desc = dma_alloc_coherent(dev, 2785 rx_ring->size, 2786 &rx_ring->dma, 2787 GFP_KERNEL); 2788 if (!rx_ring->desc) 2789 goto err; 2790 2791 rx_ring->next_to_clean = 0; 2792 rx_ring->next_to_use = 0; 2793 2794 return 0; 2795 2796err: 2797 vfree(rx_ring->rx_buffer_info); 2798 rx_ring->rx_buffer_info = NULL; 2799 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 2800 return -ENOMEM; 2801} 2802 2803/** 2804 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 2805 * (Descriptors) for all queues 2806 * @adapter: board private structure 2807 * 2808 * Return 0 on success, negative on failure 2809 **/ 2810static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 2811{ 2812 struct pci_dev *pdev = adapter->pdev; 2813 int i, err = 0; 2814 2815 for (i = 0; i < adapter->num_rx_queues; i++) { 2816 err = igb_setup_rx_resources(adapter->rx_ring[i]); 2817 if (err) { 2818 dev_err(&pdev->dev, 2819 "Allocation for Rx Queue %u failed\n", i); 2820 for (i--; i >= 0; i--) 2821 igb_free_rx_resources(adapter->rx_ring[i]); 2822 break; 2823 } 2824 } 2825 2826 return err; 2827} 2828 2829/** 2830 * igb_setup_mrqc - configure the multiple receive queue control registers 2831 * @adapter: Board private structure 2832 **/ 2833static void igb_setup_mrqc(struct igb_adapter *adapter) 2834{ 2835 struct e1000_hw *hw = &adapter->hw; 2836 u32 mrqc, rxcsum; 2837 u32 j, num_rx_queues, shift = 0; 2838 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, 2839 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, 2840 0xA32DCB77, 0x0CF23080, 0x3BB7426A, 2841 0xFA01ACBE }; 2842 2843 /* Fill out hash function seeds */ 2844 for (j = 0; j < 10; j++) 2845 wr32(E1000_RSSRK(j), rsskey[j]); 2846 2847 num_rx_queues = adapter->rss_queues; 2848 2849 switch (hw->mac.type) { 2850 case e1000_82575: 2851 shift = 6; 2852 break; 2853 case e1000_82576: 2854 /* 82576 supports 2 RSS queues for SR-IOV */ 2855 if (adapter->vfs_allocated_count) { 2856 shift = 3; 2857 num_rx_queues = 2; 2858 } 2859 break; 2860 default: 2861 break; 2862 } 2863 2864 /* 2865 * Populate the indirection table 4 entries at a time. To do this 2866 * we are generating the results for n and n+2 and then interleaving 2867 * those with the results with n+1 and n+3. 2868 */ 2869 for (j = 0; j < 32; j++) { 2870 /* first pass generates n and n+2 */ 2871 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues; 2872 u32 reta = (base & 0x07800780) >> (7 - shift); 2873 2874 /* second pass generates n+1 and n+3 */ 2875 base += 0x00010001 * num_rx_queues; 2876 reta |= (base & 0x07800780) << (1 + shift); 2877 2878 wr32(E1000_RETA(j), reta); 2879 } 2880 2881 /* 2882 * Disable raw packet checksumming so that RSS hash is placed in 2883 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 2884 * offloads as they are enabled by default 2885 */ 2886 rxcsum = rd32(E1000_RXCSUM); 2887 rxcsum |= E1000_RXCSUM_PCSD; 2888 2889 if (adapter->hw.mac.type >= e1000_82576) 2890 /* Enable Receive Checksum Offload for SCTP */ 2891 rxcsum |= E1000_RXCSUM_CRCOFL; 2892 2893 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 2894 wr32(E1000_RXCSUM, rxcsum); 2895 /* 2896 * Generate RSS hash based on TCP port numbers and/or 2897 * IPv4/v6 src and dst addresses since UDP cannot be 2898 * hashed reliably due to IP fragmentation 2899 */ 2900 2901 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 2902 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2903 E1000_MRQC_RSS_FIELD_IPV6 | 2904 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2905 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 2906 2907 /* If VMDq is enabled then we set the appropriate mode for that, else 2908 * we default to RSS so that an RSS hash is calculated per packet even 2909 * if we are only using one queue */ 2910 if (adapter->vfs_allocated_count) { 2911 if (hw->mac.type > e1000_82575) { 2912 /* Set the default pool for the PF's first queue */ 2913 u32 vtctl = rd32(E1000_VT_CTL); 2914 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 2915 E1000_VT_CTL_DISABLE_DEF_POOL); 2916 vtctl |= adapter->vfs_allocated_count << 2917 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 2918 wr32(E1000_VT_CTL, vtctl); 2919 } 2920 if (adapter->rss_queues > 1) 2921 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 2922 else 2923 mrqc |= E1000_MRQC_ENABLE_VMDQ; 2924 } else { 2925 if (hw->mac.type != e1000_i211) 2926 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 2927 } 2928 igb_vmm_control(adapter); 2929 2930 wr32(E1000_MRQC, mrqc); 2931} 2932 2933/** 2934 * igb_setup_rctl - configure the receive control registers 2935 * @adapter: Board private structure 2936 **/ 2937void igb_setup_rctl(struct igb_adapter *adapter) 2938{ 2939 struct e1000_hw *hw = &adapter->hw; 2940 u32 rctl; 2941 2942 rctl = rd32(E1000_RCTL); 2943 2944 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2945 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 2946 2947 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 2948 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2949 2950 /* 2951 * enable stripping of CRC. It's unlikely this will break BMC 2952 * redirection as it did with e1000. Newer features require 2953 * that the HW strips the CRC. 2954 */ 2955 rctl |= E1000_RCTL_SECRC; 2956 2957 /* disable store bad packets and clear size bits. */ 2958 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 2959 2960 /* enable LPE to prevent packets larger than max_frame_size */ 2961 rctl |= E1000_RCTL_LPE; 2962 2963 /* disable queue 0 to prevent tail write w/o re-config */ 2964 wr32(E1000_RXDCTL(0), 0); 2965 2966 /* Attention!!! For SR-IOV PF driver operations you must enable 2967 * queue drop for all VF and PF queues to prevent head of line blocking 2968 * if an un-trusted VF does not provide descriptors to hardware. 2969 */ 2970 if (adapter->vfs_allocated_count) { 2971 /* set all queue drop enable bits */ 2972 wr32(E1000_QDE, ALL_QUEUES); 2973 } 2974 2975 /* This is useful for sniffing bad packets. */ 2976 if (adapter->netdev->features & NETIF_F_RXALL) { 2977 /* UPE and MPE will be handled by normal PROMISC logic 2978 * in e1000e_set_rx_mode */ 2979 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 2980 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 2981 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 2982 2983 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 2984 E1000_RCTL_DPF | /* Allow filtered pause */ 2985 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 2986 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 2987 * and that breaks VLANs. 2988 */ 2989 } 2990 2991 wr32(E1000_RCTL, rctl); 2992} 2993 2994static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 2995 int vfn) 2996{ 2997 struct e1000_hw *hw = &adapter->hw; 2998 u32 vmolr; 2999 3000 /* if it isn't the PF check to see if VFs are enabled and 3001 * increase the size to support vlan tags */ 3002 if (vfn < adapter->vfs_allocated_count && 3003 adapter->vf_data[vfn].vlans_enabled) 3004 size += VLAN_TAG_SIZE; 3005 3006 vmolr = rd32(E1000_VMOLR(vfn)); 3007 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3008 vmolr |= size | E1000_VMOLR_LPE; 3009 wr32(E1000_VMOLR(vfn), vmolr); 3010 3011 return 0; 3012} 3013 3014/** 3015 * igb_rlpml_set - set maximum receive packet size 3016 * @adapter: board private structure 3017 * 3018 * Configure maximum receivable packet size. 3019 **/ 3020static void igb_rlpml_set(struct igb_adapter *adapter) 3021{ 3022 u32 max_frame_size = adapter->max_frame_size; 3023 struct e1000_hw *hw = &adapter->hw; 3024 u16 pf_id = adapter->vfs_allocated_count; 3025 3026 if (pf_id) { 3027 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3028 /* 3029 * If we're in VMDQ or SR-IOV mode, then set global RLPML 3030 * to our max jumbo frame size, in case we need to enable 3031 * jumbo frames on one of the rings later. 3032 * This will not pass over-length frames into the default 3033 * queue because it's gated by the VMOLR.RLPML. 3034 */ 3035 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3036 } 3037 3038 wr32(E1000_RLPML, max_frame_size); 3039} 3040 3041static inline void igb_set_vmolr(struct igb_adapter *adapter, 3042 int vfn, bool aupe) 3043{ 3044 struct e1000_hw *hw = &adapter->hw; 3045 u32 vmolr; 3046 3047 /* 3048 * This register exists only on 82576 and newer so if we are older then 3049 * we should exit and do nothing 3050 */ 3051 if (hw->mac.type < e1000_82576) 3052 return; 3053 3054 vmolr = rd32(E1000_VMOLR(vfn)); 3055 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3056 if (aupe) 3057 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3058 else 3059 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3060 3061 /* clear all bits that might not be set */ 3062 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3063 3064 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3065 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3066 /* 3067 * for VMDq only allow the VFs and pool 0 to accept broadcast and 3068 * multicast packets 3069 */ 3070 if (vfn <= adapter->vfs_allocated_count) 3071 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3072 3073 wr32(E1000_VMOLR(vfn), vmolr); 3074} 3075 3076/** 3077 * igb_configure_rx_ring - Configure a receive ring after Reset 3078 * @adapter: board private structure 3079 * @ring: receive ring to be configured 3080 * 3081 * Configure the Rx unit of the MAC after a reset. 3082 **/ 3083void igb_configure_rx_ring(struct igb_adapter *adapter, 3084 struct igb_ring *ring) 3085{ 3086 struct e1000_hw *hw = &adapter->hw; 3087 u64 rdba = ring->dma; 3088 int reg_idx = ring->reg_idx; 3089 u32 srrctl = 0, rxdctl = 0; 3090 3091 /* disable the queue */ 3092 wr32(E1000_RXDCTL(reg_idx), 0); 3093 3094 /* Set DMA base address registers */ 3095 wr32(E1000_RDBAL(reg_idx), 3096 rdba & 0x00000000ffffffffULL); 3097 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3098 wr32(E1000_RDLEN(reg_idx), 3099 ring->count * sizeof(union e1000_adv_rx_desc)); 3100 3101 /* initialize head and tail */ 3102 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3103 wr32(E1000_RDH(reg_idx), 0); 3104 writel(0, ring->tail); 3105 3106 /* set descriptor configuration */ 3107 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3108#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384 3109 srrctl |= IGB_RXBUFFER_16384 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3110#else 3111 srrctl |= (PAGE_SIZE / 2) >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3112#endif 3113 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS; 3114#ifdef CONFIG_IGB_PTP 3115 if (hw->mac.type >= e1000_82580) 3116 srrctl |= E1000_SRRCTL_TIMESTAMP; 3117#endif /* CONFIG_IGB_PTP */ 3118 /* Only set Drop Enable if we are supporting multiple queues */ 3119 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3120 srrctl |= E1000_SRRCTL_DROP_EN; 3121 3122 wr32(E1000_SRRCTL(reg_idx), srrctl); 3123 3124 /* set filtering for VMDQ pools */ 3125 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3126 3127 rxdctl |= IGB_RX_PTHRESH; 3128 rxdctl |= IGB_RX_HTHRESH << 8; 3129 rxdctl |= IGB_RX_WTHRESH << 16; 3130 3131 /* enable receive descriptor fetching */ 3132 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3133 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3134} 3135 3136/** 3137 * igb_configure_rx - Configure receive Unit after Reset 3138 * @adapter: board private structure 3139 * 3140 * Configure the Rx unit of the MAC after a reset. 3141 **/ 3142static void igb_configure_rx(struct igb_adapter *adapter) 3143{ 3144 int i; 3145 3146 /* set UTA to appropriate mode */ 3147 igb_set_uta(adapter); 3148 3149 /* set the correct pool for the PF default MAC address in entry 0 */ 3150 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3151 adapter->vfs_allocated_count); 3152 3153 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3154 * the Base and Length of the Rx Descriptor Ring */ 3155 for (i = 0; i < adapter->num_rx_queues; i++) 3156 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3157} 3158 3159/** 3160 * igb_free_tx_resources - Free Tx Resources per Queue 3161 * @tx_ring: Tx descriptor ring for a specific queue 3162 * 3163 * Free all transmit software resources 3164 **/ 3165void igb_free_tx_resources(struct igb_ring *tx_ring) 3166{ 3167 igb_clean_tx_ring(tx_ring); 3168 3169 vfree(tx_ring->tx_buffer_info); 3170 tx_ring->tx_buffer_info = NULL; 3171 3172 /* if not set, then don't free */ 3173 if (!tx_ring->desc) 3174 return; 3175 3176 dma_free_coherent(tx_ring->dev, tx_ring->size, 3177 tx_ring->desc, tx_ring->dma); 3178 3179 tx_ring->desc = NULL; 3180} 3181 3182/** 3183 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3184 * @adapter: board private structure 3185 * 3186 * Free all transmit software resources 3187 **/ 3188static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3189{ 3190 int i; 3191 3192 for (i = 0; i < adapter->num_tx_queues; i++) 3193 igb_free_tx_resources(adapter->tx_ring[i]); 3194} 3195 3196void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3197 struct igb_tx_buffer *tx_buffer) 3198{ 3199 if (tx_buffer->skb) { 3200 dev_kfree_skb_any(tx_buffer->skb); 3201 if (tx_buffer->dma) 3202 dma_unmap_single(ring->dev, 3203 tx_buffer->dma, 3204 tx_buffer->length, 3205 DMA_TO_DEVICE); 3206 } else if (tx_buffer->dma) { 3207 dma_unmap_page(ring->dev, 3208 tx_buffer->dma, 3209 tx_buffer->length, 3210 DMA_TO_DEVICE); 3211 } 3212 tx_buffer->next_to_watch = NULL; 3213 tx_buffer->skb = NULL; 3214 tx_buffer->dma = 0; 3215 /* buffer_info must be completely set up in the transmit path */ 3216} 3217 3218/** 3219 * igb_clean_tx_ring - Free Tx Buffers 3220 * @tx_ring: ring to be cleaned 3221 **/ 3222static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3223{ 3224 struct igb_tx_buffer *buffer_info; 3225 unsigned long size; 3226 u16 i; 3227 3228 if (!tx_ring->tx_buffer_info) 3229 return; 3230 /* Free all the Tx ring sk_buffs */ 3231 3232 for (i = 0; i < tx_ring->count; i++) { 3233 buffer_info = &tx_ring->tx_buffer_info[i]; 3234 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3235 } 3236 3237 netdev_tx_reset_queue(txring_txq(tx_ring)); 3238 3239 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3240 memset(tx_ring->tx_buffer_info, 0, size); 3241 3242 /* Zero out the descriptor ring */ 3243 memset(tx_ring->desc, 0, tx_ring->size); 3244 3245 tx_ring->next_to_use = 0; 3246 tx_ring->next_to_clean = 0; 3247} 3248 3249/** 3250 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3251 * @adapter: board private structure 3252 **/ 3253static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3254{ 3255 int i; 3256 3257 for (i = 0; i < adapter->num_tx_queues; i++) 3258 igb_clean_tx_ring(adapter->tx_ring[i]); 3259} 3260 3261/** 3262 * igb_free_rx_resources - Free Rx Resources 3263 * @rx_ring: ring to clean the resources from 3264 * 3265 * Free all receive software resources 3266 **/ 3267void igb_free_rx_resources(struct igb_ring *rx_ring) 3268{ 3269 igb_clean_rx_ring(rx_ring); 3270 3271 vfree(rx_ring->rx_buffer_info); 3272 rx_ring->rx_buffer_info = NULL; 3273 3274 /* if not set, then don't free */ 3275 if (!rx_ring->desc) 3276 return; 3277 3278 dma_free_coherent(rx_ring->dev, rx_ring->size, 3279 rx_ring->desc, rx_ring->dma); 3280 3281 rx_ring->desc = NULL; 3282} 3283 3284/** 3285 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3286 * @adapter: board private structure 3287 * 3288 * Free all receive software resources 3289 **/ 3290static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3291{ 3292 int i; 3293 3294 for (i = 0; i < adapter->num_rx_queues; i++) 3295 igb_free_rx_resources(adapter->rx_ring[i]); 3296} 3297 3298/** 3299 * igb_clean_rx_ring - Free Rx Buffers per Queue 3300 * @rx_ring: ring to free buffers from 3301 **/ 3302static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3303{ 3304 unsigned long size; 3305 u16 i; 3306 3307 if (!rx_ring->rx_buffer_info) 3308 return; 3309 3310 /* Free all the Rx ring sk_buffs */ 3311 for (i = 0; i < rx_ring->count; i++) { 3312 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3313 if (buffer_info->dma) { 3314 dma_unmap_single(rx_ring->dev, 3315 buffer_info->dma, 3316 IGB_RX_HDR_LEN, 3317 DMA_FROM_DEVICE); 3318 buffer_info->dma = 0; 3319 } 3320 3321 if (buffer_info->skb) { 3322 dev_kfree_skb(buffer_info->skb); 3323 buffer_info->skb = NULL; 3324 } 3325 if (buffer_info->page_dma) { 3326 dma_unmap_page(rx_ring->dev, 3327 buffer_info->page_dma, 3328 PAGE_SIZE / 2, 3329 DMA_FROM_DEVICE); 3330 buffer_info->page_dma = 0; 3331 } 3332 if (buffer_info->page) { 3333 put_page(buffer_info->page); 3334 buffer_info->page = NULL; 3335 buffer_info->page_offset = 0; 3336 } 3337 } 3338 3339 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3340 memset(rx_ring->rx_buffer_info, 0, size); 3341 3342 /* Zero out the descriptor ring */ 3343 memset(rx_ring->desc, 0, rx_ring->size); 3344 3345 rx_ring->next_to_clean = 0; 3346 rx_ring->next_to_use = 0; 3347} 3348 3349/** 3350 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3351 * @adapter: board private structure 3352 **/ 3353static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3354{ 3355 int i; 3356 3357 for (i = 0; i < adapter->num_rx_queues; i++) 3358 igb_clean_rx_ring(adapter->rx_ring[i]); 3359} 3360 3361/** 3362 * igb_set_mac - Change the Ethernet Address of the NIC 3363 * @netdev: network interface device structure 3364 * @p: pointer to an address structure 3365 * 3366 * Returns 0 on success, negative on failure 3367 **/ 3368static int igb_set_mac(struct net_device *netdev, void *p) 3369{ 3370 struct igb_adapter *adapter = netdev_priv(netdev); 3371 struct e1000_hw *hw = &adapter->hw; 3372 struct sockaddr *addr = p; 3373 3374 if (!is_valid_ether_addr(addr->sa_data)) 3375 return -EADDRNOTAVAIL; 3376 3377 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3378 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3379 3380 /* set the correct pool for the new PF MAC address in entry 0 */ 3381 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3382 adapter->vfs_allocated_count); 3383 3384 return 0; 3385} 3386 3387/** 3388 * igb_write_mc_addr_list - write multicast addresses to MTA 3389 * @netdev: network interface device structure 3390 * 3391 * Writes multicast address list to the MTA hash table. 3392 * Returns: -ENOMEM on failure 3393 * 0 on no addresses written 3394 * X on writing X addresses to MTA 3395 **/ 3396static int igb_write_mc_addr_list(struct net_device *netdev) 3397{ 3398 struct igb_adapter *adapter = netdev_priv(netdev); 3399 struct e1000_hw *hw = &adapter->hw; 3400 struct netdev_hw_addr *ha; 3401 u8 *mta_list; 3402 int i; 3403 3404 if (netdev_mc_empty(netdev)) { 3405 /* nothing to program, so clear mc list */ 3406 igb_update_mc_addr_list(hw, NULL, 0); 3407 igb_restore_vf_multicasts(adapter); 3408 return 0; 3409 } 3410 3411 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3412 if (!mta_list) 3413 return -ENOMEM; 3414 3415 /* The shared function expects a packed array of only addresses. */ 3416 i = 0; 3417 netdev_for_each_mc_addr(ha, netdev) 3418 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3419 3420 igb_update_mc_addr_list(hw, mta_list, i); 3421 kfree(mta_list); 3422 3423 return netdev_mc_count(netdev); 3424} 3425 3426/** 3427 * igb_write_uc_addr_list - write unicast addresses to RAR table 3428 * @netdev: network interface device structure 3429 * 3430 * Writes unicast address list to the RAR table. 3431 * Returns: -ENOMEM on failure/insufficient address space 3432 * 0 on no addresses written 3433 * X on writing X addresses to the RAR table 3434 **/ 3435static int igb_write_uc_addr_list(struct net_device *netdev) 3436{ 3437 struct igb_adapter *adapter = netdev_priv(netdev); 3438 struct e1000_hw *hw = &adapter->hw; 3439 unsigned int vfn = adapter->vfs_allocated_count; 3440 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3441 int count = 0; 3442 3443 /* return ENOMEM indicating insufficient memory for addresses */ 3444 if (netdev_uc_count(netdev) > rar_entries) 3445 return -ENOMEM; 3446 3447 if (!netdev_uc_empty(netdev) && rar_entries) { 3448 struct netdev_hw_addr *ha; 3449 3450 netdev_for_each_uc_addr(ha, netdev) { 3451 if (!rar_entries) 3452 break; 3453 igb_rar_set_qsel(adapter, ha->addr, 3454 rar_entries--, 3455 vfn); 3456 count++; 3457 } 3458 } 3459 /* write the addresses in reverse order to avoid write combining */ 3460 for (; rar_entries > 0 ; rar_entries--) { 3461 wr32(E1000_RAH(rar_entries), 0); 3462 wr32(E1000_RAL(rar_entries), 0); 3463 } 3464 wrfl(); 3465 3466 return count; 3467} 3468 3469/** 3470 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3471 * @netdev: network interface device structure 3472 * 3473 * The set_rx_mode entry point is called whenever the unicast or multicast 3474 * address lists or the network interface flags are updated. This routine is 3475 * responsible for configuring the hardware for proper unicast, multicast, 3476 * promiscuous mode, and all-multi behavior. 3477 **/ 3478static void igb_set_rx_mode(struct net_device *netdev) 3479{ 3480 struct igb_adapter *adapter = netdev_priv(netdev); 3481 struct e1000_hw *hw = &adapter->hw; 3482 unsigned int vfn = adapter->vfs_allocated_count; 3483 u32 rctl, vmolr = 0; 3484 int count; 3485 3486 /* Check for Promiscuous and All Multicast modes */ 3487 rctl = rd32(E1000_RCTL); 3488 3489 /* clear the effected bits */ 3490 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 3491 3492 if (netdev->flags & IFF_PROMISC) { 3493 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3494 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 3495 } else { 3496 if (netdev->flags & IFF_ALLMULTI) { 3497 rctl |= E1000_RCTL_MPE; 3498 vmolr |= E1000_VMOLR_MPME; 3499 } else { 3500 /* 3501 * Write addresses to the MTA, if the attempt fails 3502 * then we should just turn on promiscuous mode so 3503 * that we can at least receive multicast traffic 3504 */ 3505 count = igb_write_mc_addr_list(netdev); 3506 if (count < 0) { 3507 rctl |= E1000_RCTL_MPE; 3508 vmolr |= E1000_VMOLR_MPME; 3509 } else if (count) { 3510 vmolr |= E1000_VMOLR_ROMPE; 3511 } 3512 } 3513 /* 3514 * Write addresses to available RAR registers, if there is not 3515 * sufficient space to store all the addresses then enable 3516 * unicast promiscuous mode 3517 */ 3518 count = igb_write_uc_addr_list(netdev); 3519 if (count < 0) { 3520 rctl |= E1000_RCTL_UPE; 3521 vmolr |= E1000_VMOLR_ROPE; 3522 } 3523 rctl |= E1000_RCTL_VFE; 3524 } 3525 wr32(E1000_RCTL, rctl); 3526 3527 /* 3528 * In order to support SR-IOV and eventually VMDq it is necessary to set 3529 * the VMOLR to enable the appropriate modes. Without this workaround 3530 * we will have issues with VLAN tag stripping not being done for frames 3531 * that are only arriving because we are the default pool 3532 */ 3533 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 3534 return; 3535 3536 vmolr |= rd32(E1000_VMOLR(vfn)) & 3537 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 3538 wr32(E1000_VMOLR(vfn), vmolr); 3539 igb_restore_vf_multicasts(adapter); 3540} 3541 3542static void igb_check_wvbr(struct igb_adapter *adapter) 3543{ 3544 struct e1000_hw *hw = &adapter->hw; 3545 u32 wvbr = 0; 3546 3547 switch (hw->mac.type) { 3548 case e1000_82576: 3549 case e1000_i350: 3550 if (!(wvbr = rd32(E1000_WVBR))) 3551 return; 3552 break; 3553 default: 3554 break; 3555 } 3556 3557 adapter->wvbr |= wvbr; 3558} 3559 3560#define IGB_STAGGERED_QUEUE_OFFSET 8 3561 3562static void igb_spoof_check(struct igb_adapter *adapter) 3563{ 3564 int j; 3565 3566 if (!adapter->wvbr) 3567 return; 3568 3569 for(j = 0; j < adapter->vfs_allocated_count; j++) { 3570 if (adapter->wvbr & (1 << j) || 3571 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 3572 dev_warn(&adapter->pdev->dev, 3573 "Spoof event(s) detected on VF %d\n", j); 3574 adapter->wvbr &= 3575 ~((1 << j) | 3576 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 3577 } 3578 } 3579} 3580 3581/* Need to wait a few seconds after link up to get diagnostic information from 3582 * the phy */ 3583static void igb_update_phy_info(unsigned long data) 3584{ 3585 struct igb_adapter *adapter = (struct igb_adapter *) data; 3586 igb_get_phy_info(&adapter->hw); 3587} 3588 3589/** 3590 * igb_has_link - check shared code for link and determine up/down 3591 * @adapter: pointer to driver private info 3592 **/ 3593bool igb_has_link(struct igb_adapter *adapter) 3594{ 3595 struct e1000_hw *hw = &adapter->hw; 3596 bool link_active = false; 3597 s32 ret_val = 0; 3598 3599 /* get_link_status is set on LSC (link status) interrupt or 3600 * rx sequence error interrupt. get_link_status will stay 3601 * false until the e1000_check_for_link establishes link 3602 * for copper adapters ONLY 3603 */ 3604 switch (hw->phy.media_type) { 3605 case e1000_media_type_copper: 3606 if (hw->mac.get_link_status) { 3607 ret_val = hw->mac.ops.check_for_link(hw); 3608 link_active = !hw->mac.get_link_status; 3609 } else { 3610 link_active = true; 3611 } 3612 break; 3613 case e1000_media_type_internal_serdes: 3614 ret_val = hw->mac.ops.check_for_link(hw); 3615 link_active = hw->mac.serdes_has_link; 3616 break; 3617 default: 3618 case e1000_media_type_unknown: 3619 break; 3620 } 3621 3622 return link_active; 3623} 3624 3625static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 3626{ 3627 bool ret = false; 3628 u32 ctrl_ext, thstat; 3629 3630 /* check for thermal sensor event on i350 copper only */ 3631 if (hw->mac.type == e1000_i350) { 3632 thstat = rd32(E1000_THSTAT); 3633 ctrl_ext = rd32(E1000_CTRL_EXT); 3634 3635 if ((hw->phy.media_type == e1000_media_type_copper) && 3636 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3637 ret = !!(thstat & event); 3638 } 3639 } 3640 3641 return ret; 3642} 3643 3644/** 3645 * igb_watchdog - Timer Call-back 3646 * @data: pointer to adapter cast into an unsigned long 3647 **/ 3648static void igb_watchdog(unsigned long data) 3649{ 3650 struct igb_adapter *adapter = (struct igb_adapter *)data; 3651 /* Do the rest outside of interrupt context */ 3652 schedule_work(&adapter->watchdog_task); 3653} 3654 3655static void igb_watchdog_task(struct work_struct *work) 3656{ 3657 struct igb_adapter *adapter = container_of(work, 3658 struct igb_adapter, 3659 watchdog_task); 3660 struct e1000_hw *hw = &adapter->hw; 3661 struct net_device *netdev = adapter->netdev; 3662 u32 link; 3663 int i; 3664 3665 link = igb_has_link(adapter); 3666 if (link) { 3667 /* Cancel scheduled suspend requests. */ 3668 pm_runtime_resume(netdev->dev.parent); 3669 3670 if (!netif_carrier_ok(netdev)) { 3671 u32 ctrl; 3672 hw->mac.ops.get_speed_and_duplex(hw, 3673 &adapter->link_speed, 3674 &adapter->link_duplex); 3675 3676 ctrl = rd32(E1000_CTRL); 3677 /* Links status message must follow this format */ 3678 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s " 3679 "Duplex, Flow Control: %s\n", 3680 netdev->name, 3681 adapter->link_speed, 3682 adapter->link_duplex == FULL_DUPLEX ? 3683 "Full" : "Half", 3684 (ctrl & E1000_CTRL_TFCE) && 3685 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 3686 (ctrl & E1000_CTRL_RFCE) ? "RX" : 3687 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 3688 3689 /* check for thermal sensor event */ 3690 if (igb_thermal_sensor_event(hw, 3691 E1000_THSTAT_LINK_THROTTLE)) { 3692 netdev_info(netdev, "The network adapter link " 3693 "speed was downshifted because it " 3694 "overheated\n"); 3695 } 3696 3697 /* adjust timeout factor according to speed/duplex */ 3698 adapter->tx_timeout_factor = 1; 3699 switch (adapter->link_speed) { 3700 case SPEED_10: 3701 adapter->tx_timeout_factor = 14; 3702 break; 3703 case SPEED_100: 3704 /* maybe add some timeout factor ? */ 3705 break; 3706 } 3707 3708 netif_carrier_on(netdev); 3709 3710 igb_ping_all_vfs(adapter); 3711 igb_check_vf_rate_limit(adapter); 3712 3713 /* link state has changed, schedule phy info update */ 3714 if (!test_bit(__IGB_DOWN, &adapter->state)) 3715 mod_timer(&adapter->phy_info_timer, 3716 round_jiffies(jiffies + 2 * HZ)); 3717 } 3718 } else { 3719 if (netif_carrier_ok(netdev)) { 3720 adapter->link_speed = 0; 3721 adapter->link_duplex = 0; 3722 3723 /* check for thermal sensor event */ 3724 if (igb_thermal_sensor_event(hw, 3725 E1000_THSTAT_PWR_DOWN)) { 3726 netdev_err(netdev, "The network adapter was " 3727 "stopped because it overheated\n"); 3728 } 3729 3730 /* Links status message must follow this format */ 3731 printk(KERN_INFO "igb: %s NIC Link is Down\n", 3732 netdev->name); 3733 netif_carrier_off(netdev); 3734 3735 igb_ping_all_vfs(adapter); 3736 3737 /* link state has changed, schedule phy info update */ 3738 if (!test_bit(__IGB_DOWN, &adapter->state)) 3739 mod_timer(&adapter->phy_info_timer, 3740 round_jiffies(jiffies + 2 * HZ)); 3741 3742 pm_schedule_suspend(netdev->dev.parent, 3743 MSEC_PER_SEC * 5); 3744 } 3745 } 3746 3747 spin_lock(&adapter->stats64_lock); 3748 igb_update_stats(adapter, &adapter->stats64); 3749 spin_unlock(&adapter->stats64_lock); 3750 3751 for (i = 0; i < adapter->num_tx_queues; i++) { 3752 struct igb_ring *tx_ring = adapter->tx_ring[i]; 3753 if (!netif_carrier_ok(netdev)) { 3754 /* We've lost link, so the controller stops DMA, 3755 * but we've got queued Tx work that's never going 3756 * to get done, so reset controller to flush Tx. 3757 * (Do the reset outside of interrupt context). */ 3758 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 3759 adapter->tx_timeout_count++; 3760 schedule_work(&adapter->reset_task); 3761 /* return immediately since reset is imminent */ 3762 return; 3763 } 3764 } 3765 3766 /* Force detection of hung controller every watchdog period */ 3767 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 3768 } 3769 3770 /* Cause software interrupt to ensure rx ring is cleaned */ 3771 if (adapter->msix_entries) { 3772 u32 eics = 0; 3773 for (i = 0; i < adapter->num_q_vectors; i++) 3774 eics |= adapter->q_vector[i]->eims_value; 3775 wr32(E1000_EICS, eics); 3776 } else { 3777 wr32(E1000_ICS, E1000_ICS_RXDMT0); 3778 } 3779 3780 igb_spoof_check(adapter); 3781 3782 /* Reset the timer */ 3783 if (!test_bit(__IGB_DOWN, &adapter->state)) 3784 mod_timer(&adapter->watchdog_timer, 3785 round_jiffies(jiffies + 2 * HZ)); 3786} 3787 3788enum latency_range { 3789 lowest_latency = 0, 3790 low_latency = 1, 3791 bulk_latency = 2, 3792 latency_invalid = 255 3793}; 3794 3795/** 3796 * igb_update_ring_itr - update the dynamic ITR value based on packet size 3797 * 3798 * Stores a new ITR value based on strictly on packet size. This 3799 * algorithm is less sophisticated than that used in igb_update_itr, 3800 * due to the difficulty of synchronizing statistics across multiple 3801 * receive rings. The divisors and thresholds used by this function 3802 * were determined based on theoretical maximum wire speed and testing 3803 * data, in order to minimize response time while increasing bulk 3804 * throughput. 3805 * This functionality is controlled by the InterruptThrottleRate module 3806 * parameter (see igb_param.c) 3807 * NOTE: This function is called only when operating in a multiqueue 3808 * receive environment. 3809 * @q_vector: pointer to q_vector 3810 **/ 3811static void igb_update_ring_itr(struct igb_q_vector *q_vector) 3812{ 3813 int new_val = q_vector->itr_val; 3814 int avg_wire_size = 0; 3815 struct igb_adapter *adapter = q_vector->adapter; 3816 unsigned int packets; 3817 3818 /* For non-gigabit speeds, just fix the interrupt rate at 4000 3819 * ints/sec - ITR timer value of 120 ticks. 3820 */ 3821 if (adapter->link_speed != SPEED_1000) { 3822 new_val = IGB_4K_ITR; 3823 goto set_itr_val; 3824 } 3825 3826 packets = q_vector->rx.total_packets; 3827 if (packets) 3828 avg_wire_size = q_vector->rx.total_bytes / packets; 3829 3830 packets = q_vector->tx.total_packets; 3831 if (packets) 3832 avg_wire_size = max_t(u32, avg_wire_size, 3833 q_vector->tx.total_bytes / packets); 3834 3835 /* if avg_wire_size isn't set no work was done */ 3836 if (!avg_wire_size) 3837 goto clear_counts; 3838 3839 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 3840 avg_wire_size += 24; 3841 3842 /* Don't starve jumbo frames */ 3843 avg_wire_size = min(avg_wire_size, 3000); 3844 3845 /* Give a little boost to mid-size frames */ 3846 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 3847 new_val = avg_wire_size / 3; 3848 else 3849 new_val = avg_wire_size / 2; 3850 3851 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 3852 if (new_val < IGB_20K_ITR && 3853 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 3854 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 3855 new_val = IGB_20K_ITR; 3856 3857set_itr_val: 3858 if (new_val != q_vector->itr_val) { 3859 q_vector->itr_val = new_val; 3860 q_vector->set_itr = 1; 3861 } 3862clear_counts: 3863 q_vector->rx.total_bytes = 0; 3864 q_vector->rx.total_packets = 0; 3865 q_vector->tx.total_bytes = 0; 3866 q_vector->tx.total_packets = 0; 3867} 3868 3869/** 3870 * igb_update_itr - update the dynamic ITR value based on statistics 3871 * Stores a new ITR value based on packets and byte 3872 * counts during the last interrupt. The advantage of per interrupt 3873 * computation is faster updates and more accurate ITR for the current 3874 * traffic pattern. Constants in this function were computed 3875 * based on theoretical maximum wire speed and thresholds were set based 3876 * on testing data as well as attempting to minimize response time 3877 * while increasing bulk throughput. 3878 * this functionality is controlled by the InterruptThrottleRate module 3879 * parameter (see igb_param.c) 3880 * NOTE: These calculations are only valid when operating in a single- 3881 * queue environment. 3882 * @q_vector: pointer to q_vector 3883 * @ring_container: ring info to update the itr for 3884 **/ 3885static void igb_update_itr(struct igb_q_vector *q_vector, 3886 struct igb_ring_container *ring_container) 3887{ 3888 unsigned int packets = ring_container->total_packets; 3889 unsigned int bytes = ring_container->total_bytes; 3890 u8 itrval = ring_container->itr; 3891 3892 /* no packets, exit with status unchanged */ 3893 if (packets == 0) 3894 return; 3895 3896 switch (itrval) { 3897 case lowest_latency: 3898 /* handle TSO and jumbo frames */ 3899 if (bytes/packets > 8000) 3900 itrval = bulk_latency; 3901 else if ((packets < 5) && (bytes > 512)) 3902 itrval = low_latency; 3903 break; 3904 case low_latency: /* 50 usec aka 20000 ints/s */ 3905 if (bytes > 10000) { 3906 /* this if handles the TSO accounting */ 3907 if (bytes/packets > 8000) { 3908 itrval = bulk_latency; 3909 } else if ((packets < 10) || ((bytes/packets) > 1200)) { 3910 itrval = bulk_latency; 3911 } else if ((packets > 35)) { 3912 itrval = lowest_latency; 3913 } 3914 } else if (bytes/packets > 2000) { 3915 itrval = bulk_latency; 3916 } else if (packets <= 2 && bytes < 512) { 3917 itrval = lowest_latency; 3918 } 3919 break; 3920 case bulk_latency: /* 250 usec aka 4000 ints/s */ 3921 if (bytes > 25000) { 3922 if (packets > 35) 3923 itrval = low_latency; 3924 } else if (bytes < 1500) { 3925 itrval = low_latency; 3926 } 3927 break; 3928 } 3929 3930 /* clear work counters since we have the values we need */ 3931 ring_container->total_bytes = 0; 3932 ring_container->total_packets = 0; 3933 3934 /* write updated itr to ring container */ 3935 ring_container->itr = itrval; 3936} 3937 3938static void igb_set_itr(struct igb_q_vector *q_vector) 3939{ 3940 struct igb_adapter *adapter = q_vector->adapter; 3941 u32 new_itr = q_vector->itr_val; 3942 u8 current_itr = 0; 3943 3944 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 3945 if (adapter->link_speed != SPEED_1000) { 3946 current_itr = 0; 3947 new_itr = IGB_4K_ITR; 3948 goto set_itr_now; 3949 } 3950 3951 igb_update_itr(q_vector, &q_vector->tx); 3952 igb_update_itr(q_vector, &q_vector->rx); 3953 3954 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 3955 3956 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 3957 if (current_itr == lowest_latency && 3958 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 3959 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 3960 current_itr = low_latency; 3961 3962 switch (current_itr) { 3963 /* counts and packets in update_itr are dependent on these numbers */ 3964 case lowest_latency: 3965 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 3966 break; 3967 case low_latency: 3968 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 3969 break; 3970 case bulk_latency: 3971 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 3972 break; 3973 default: 3974 break; 3975 } 3976 3977set_itr_now: 3978 if (new_itr != q_vector->itr_val) { 3979 /* this attempts to bias the interrupt rate towards Bulk 3980 * by adding intermediate steps when interrupt rate is 3981 * increasing */ 3982 new_itr = new_itr > q_vector->itr_val ? 3983 max((new_itr * q_vector->itr_val) / 3984 (new_itr + (q_vector->itr_val >> 2)), 3985 new_itr) : 3986 new_itr; 3987 /* Don't write the value here; it resets the adapter's 3988 * internal timer, and causes us to delay far longer than 3989 * we should between interrupts. Instead, we write the ITR 3990 * value at the beginning of the next interrupt so the timing 3991 * ends up being correct. 3992 */ 3993 q_vector->itr_val = new_itr; 3994 q_vector->set_itr = 1; 3995 } 3996} 3997 3998static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 3999 u32 type_tucmd, u32 mss_l4len_idx) 4000{ 4001 struct e1000_adv_tx_context_desc *context_desc; 4002 u16 i = tx_ring->next_to_use; 4003 4004 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4005 4006 i++; 4007 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4008 4009 /* set bits to identify this as an advanced context descriptor */ 4010 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4011 4012 /* For 82575, context index must be unique per ring. */ 4013 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4014 mss_l4len_idx |= tx_ring->reg_idx << 4; 4015 4016 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4017 context_desc->seqnum_seed = 0; 4018 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4019 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4020} 4021 4022static int igb_tso(struct igb_ring *tx_ring, 4023 struct igb_tx_buffer *first, 4024 u8 *hdr_len) 4025{ 4026 struct sk_buff *skb = first->skb; 4027 u32 vlan_macip_lens, type_tucmd; 4028 u32 mss_l4len_idx, l4len; 4029 4030 if (!skb_is_gso(skb)) 4031 return 0; 4032 4033 if (skb_header_cloned(skb)) { 4034 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 4035 if (err) 4036 return err; 4037 } 4038 4039 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4040 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4041 4042 if (first->protocol == __constant_htons(ETH_P_IP)) { 4043 struct iphdr *iph = ip_hdr(skb); 4044 iph->tot_len = 0; 4045 iph->check = 0; 4046 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4047 iph->daddr, 0, 4048 IPPROTO_TCP, 4049 0); 4050 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4051 first->tx_flags |= IGB_TX_FLAGS_TSO | 4052 IGB_TX_FLAGS_CSUM | 4053 IGB_TX_FLAGS_IPV4; 4054 } else if (skb_is_gso_v6(skb)) { 4055 ipv6_hdr(skb)->payload_len = 0; 4056 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4057 &ipv6_hdr(skb)->daddr, 4058 0, IPPROTO_TCP, 0); 4059 first->tx_flags |= IGB_TX_FLAGS_TSO | 4060 IGB_TX_FLAGS_CSUM; 4061 } 4062 4063 /* compute header lengths */ 4064 l4len = tcp_hdrlen(skb); 4065 *hdr_len = skb_transport_offset(skb) + l4len; 4066 4067 /* update gso size and bytecount with header size */ 4068 first->gso_segs = skb_shinfo(skb)->gso_segs; 4069 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4070 4071 /* MSS L4LEN IDX */ 4072 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4073 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4074 4075 /* VLAN MACLEN IPLEN */ 4076 vlan_macip_lens = skb_network_header_len(skb); 4077 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4078 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4079 4080 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4081 4082 return 1; 4083} 4084 4085static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4086{ 4087 struct sk_buff *skb = first->skb; 4088 u32 vlan_macip_lens = 0; 4089 u32 mss_l4len_idx = 0; 4090 u32 type_tucmd = 0; 4091 4092 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4093 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4094 return; 4095 } else { 4096 u8 l4_hdr = 0; 4097 switch (first->protocol) { 4098 case __constant_htons(ETH_P_IP): 4099 vlan_macip_lens |= skb_network_header_len(skb); 4100 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4101 l4_hdr = ip_hdr(skb)->protocol; 4102 break; 4103 case __constant_htons(ETH_P_IPV6): 4104 vlan_macip_lens |= skb_network_header_len(skb); 4105 l4_hdr = ipv6_hdr(skb)->nexthdr; 4106 break; 4107 default: 4108 if (unlikely(net_ratelimit())) { 4109 dev_warn(tx_ring->dev, 4110 "partial checksum but proto=%x!\n", 4111 first->protocol); 4112 } 4113 break; 4114 } 4115 4116 switch (l4_hdr) { 4117 case IPPROTO_TCP: 4118 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4119 mss_l4len_idx = tcp_hdrlen(skb) << 4120 E1000_ADVTXD_L4LEN_SHIFT; 4121 break; 4122 case IPPROTO_SCTP: 4123 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4124 mss_l4len_idx = sizeof(struct sctphdr) << 4125 E1000_ADVTXD_L4LEN_SHIFT; 4126 break; 4127 case IPPROTO_UDP: 4128 mss_l4len_idx = sizeof(struct udphdr) << 4129 E1000_ADVTXD_L4LEN_SHIFT; 4130 break; 4131 default: 4132 if (unlikely(net_ratelimit())) { 4133 dev_warn(tx_ring->dev, 4134 "partial checksum but l4 proto=%x!\n", 4135 l4_hdr); 4136 } 4137 break; 4138 } 4139 4140 /* update TX checksum flag */ 4141 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4142 } 4143 4144 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4145 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4146 4147 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4148} 4149 4150static __le32 igb_tx_cmd_type(u32 tx_flags) 4151{ 4152 /* set type for advanced descriptor with frame checksum insertion */ 4153 __le32 cmd_type = cpu_to_le32(E1000_ADVTXD_DTYP_DATA | 4154 E1000_ADVTXD_DCMD_IFCS | 4155 E1000_ADVTXD_DCMD_DEXT); 4156 4157 /* set HW vlan bit if vlan is present */ 4158 if (tx_flags & IGB_TX_FLAGS_VLAN) 4159 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_VLE); 4160 4161#ifdef CONFIG_IGB_PTP 4162 /* set timestamp bit if present */ 4163 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) 4164 cmd_type |= cpu_to_le32(E1000_ADVTXD_MAC_TSTAMP); 4165#endif /* CONFIG_IGB_PTP */ 4166 4167 /* set segmentation bits for TSO */ 4168 if (tx_flags & IGB_TX_FLAGS_TSO) 4169 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_TSE); 4170 4171 return cmd_type; 4172} 4173 4174static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4175 union e1000_adv_tx_desc *tx_desc, 4176 u32 tx_flags, unsigned int paylen) 4177{ 4178 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4179 4180 /* 82575 requires a unique index per ring if any offload is enabled */ 4181 if ((tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_VLAN)) && 4182 test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4183 olinfo_status |= tx_ring->reg_idx << 4; 4184 4185 /* insert L4 checksum */ 4186 if (tx_flags & IGB_TX_FLAGS_CSUM) { 4187 olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 4188 4189 /* insert IPv4 checksum */ 4190 if (tx_flags & IGB_TX_FLAGS_IPV4) 4191 olinfo_status |= E1000_TXD_POPTS_IXSM << 8; 4192 } 4193 4194 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4195} 4196 4197/* 4198 * The largest size we can write to the descriptor is 65535. In order to 4199 * maintain a power of two alignment we have to limit ourselves to 32K. 4200 */ 4201#define IGB_MAX_TXD_PWR 15 4202#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) 4203 4204static void igb_tx_map(struct igb_ring *tx_ring, 4205 struct igb_tx_buffer *first, 4206 const u8 hdr_len) 4207{ 4208 struct sk_buff *skb = first->skb; 4209 struct igb_tx_buffer *tx_buffer_info; 4210 union e1000_adv_tx_desc *tx_desc; 4211 dma_addr_t dma; 4212 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 4213 unsigned int data_len = skb->data_len; 4214 unsigned int size = skb_headlen(skb); 4215 unsigned int paylen = skb->len - hdr_len; 4216 __le32 cmd_type; 4217 u32 tx_flags = first->tx_flags; 4218 u16 i = tx_ring->next_to_use; 4219 4220 tx_desc = IGB_TX_DESC(tx_ring, i); 4221 4222 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, paylen); 4223 cmd_type = igb_tx_cmd_type(tx_flags); 4224 4225 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4226 if (dma_mapping_error(tx_ring->dev, dma)) 4227 goto dma_error; 4228 4229 /* record length, and DMA address */ 4230 first->length = size; 4231 first->dma = dma; 4232 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4233 4234 for (;;) { 4235 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4236 tx_desc->read.cmd_type_len = 4237 cmd_type | cpu_to_le32(IGB_MAX_DATA_PER_TXD); 4238 4239 i++; 4240 tx_desc++; 4241 if (i == tx_ring->count) { 4242 tx_desc = IGB_TX_DESC(tx_ring, 0); 4243 i = 0; 4244 } 4245 4246 dma += IGB_MAX_DATA_PER_TXD; 4247 size -= IGB_MAX_DATA_PER_TXD; 4248 4249 tx_desc->read.olinfo_status = 0; 4250 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4251 } 4252 4253 if (likely(!data_len)) 4254 break; 4255 4256 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); 4257 4258 i++; 4259 tx_desc++; 4260 if (i == tx_ring->count) { 4261 tx_desc = IGB_TX_DESC(tx_ring, 0); 4262 i = 0; 4263 } 4264 4265 size = skb_frag_size(frag); 4266 data_len -= size; 4267 4268 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4269 size, DMA_TO_DEVICE); 4270 if (dma_mapping_error(tx_ring->dev, dma)) 4271 goto dma_error; 4272 4273 tx_buffer_info = &tx_ring->tx_buffer_info[i]; 4274 tx_buffer_info->length = size; 4275 tx_buffer_info->dma = dma; 4276 4277 tx_desc->read.olinfo_status = 0; 4278 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4279 4280 frag++; 4281 } 4282 4283 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4284 4285 /* write last descriptor with RS and EOP bits */ 4286 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IGB_TXD_DCMD); 4287 if (unlikely(skb->no_fcs)) 4288 cmd_type &= ~(cpu_to_le32(E1000_ADVTXD_DCMD_IFCS)); 4289 tx_desc->read.cmd_type_len = cmd_type; 4290 4291 /* set the timestamp */ 4292 first->time_stamp = jiffies; 4293 4294 /* 4295 * Force memory writes to complete before letting h/w know there 4296 * are new descriptors to fetch. (Only applicable for weak-ordered 4297 * memory model archs, such as IA-64). 4298 * 4299 * We also need this memory barrier to make certain all of the 4300 * status bits have been updated before next_to_watch is written. 4301 */ 4302 wmb(); 4303 4304 /* set next_to_watch value indicating a packet is present */ 4305 first->next_to_watch = tx_desc; 4306 4307 i++; 4308 if (i == tx_ring->count) 4309 i = 0; 4310 4311 tx_ring->next_to_use = i; 4312 4313 writel(i, tx_ring->tail); 4314 4315 /* we need this if more than one processor can write to our tail 4316 * at a time, it syncronizes IO on IA64/Altix systems */ 4317 mmiowb(); 4318 4319 return; 4320 4321dma_error: 4322 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4323 4324 /* clear dma mappings for failed tx_buffer_info map */ 4325 for (;;) { 4326 tx_buffer_info = &tx_ring->tx_buffer_info[i]; 4327 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info); 4328 if (tx_buffer_info == first) 4329 break; 4330 if (i == 0) 4331 i = tx_ring->count; 4332 i--; 4333 } 4334 4335 tx_ring->next_to_use = i; 4336} 4337 4338static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4339{ 4340 struct net_device *netdev = tx_ring->netdev; 4341 4342 netif_stop_subqueue(netdev, tx_ring->queue_index); 4343 4344 /* Herbert's original patch had: 4345 * smp_mb__after_netif_stop_queue(); 4346 * but since that doesn't exist yet, just open code it. */ 4347 smp_mb(); 4348 4349 /* We need to check again in a case another CPU has just 4350 * made room available. */ 4351 if (igb_desc_unused(tx_ring) < size) 4352 return -EBUSY; 4353 4354 /* A reprieve! */ 4355 netif_wake_subqueue(netdev, tx_ring->queue_index); 4356 4357 u64_stats_update_begin(&tx_ring->tx_syncp2); 4358 tx_ring->tx_stats.restart_queue2++; 4359 u64_stats_update_end(&tx_ring->tx_syncp2); 4360 4361 return 0; 4362} 4363 4364static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4365{ 4366 if (igb_desc_unused(tx_ring) >= size) 4367 return 0; 4368 return __igb_maybe_stop_tx(tx_ring, size); 4369} 4370 4371netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4372 struct igb_ring *tx_ring) 4373{ 4374#ifdef CONFIG_IGB_PTP 4375 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 4376#endif /* CONFIG_IGB_PTP */ 4377 struct igb_tx_buffer *first; 4378 int tso; 4379 u32 tx_flags = 0; 4380 __be16 protocol = vlan_get_protocol(skb); 4381 u8 hdr_len = 0; 4382 4383 /* need: 1 descriptor per page, 4384 * + 2 desc gap to keep tail from touching head, 4385 * + 1 desc for skb->data, 4386 * + 1 desc for context descriptor, 4387 * otherwise try next time */ 4388 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) { 4389 /* this is a hard error */ 4390 return NETDEV_TX_BUSY; 4391 } 4392 4393 /* record the location of the first descriptor for this packet */ 4394 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 4395 first->skb = skb; 4396 first->bytecount = skb->len; 4397 first->gso_segs = 1; 4398 4399#ifdef CONFIG_IGB_PTP 4400 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4401 !(adapter->ptp_tx_skb))) { 4402 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4403 tx_flags |= IGB_TX_FLAGS_TSTAMP; 4404 4405 adapter->ptp_tx_skb = skb_get(skb); 4406 if (adapter->hw.mac.type == e1000_82576) 4407 schedule_work(&adapter->ptp_tx_work); 4408 } 4409#endif /* CONFIG_IGB_PTP */ 4410 4411 if (vlan_tx_tag_present(skb)) { 4412 tx_flags |= IGB_TX_FLAGS_VLAN; 4413 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 4414 } 4415 4416 /* record initial flags and protocol */ 4417 first->tx_flags = tx_flags; 4418 first->protocol = protocol; 4419 4420 tso = igb_tso(tx_ring, first, &hdr_len); 4421 if (tso < 0) 4422 goto out_drop; 4423 else if (!tso) 4424 igb_tx_csum(tx_ring, first); 4425 4426 igb_tx_map(tx_ring, first, hdr_len); 4427 4428 /* Make sure there is space in the ring for the next send. */ 4429 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4); 4430 4431 return NETDEV_TX_OK; 4432 4433out_drop: 4434 igb_unmap_and_free_tx_resource(tx_ring, first); 4435 4436 return NETDEV_TX_OK; 4437} 4438 4439static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 4440 struct sk_buff *skb) 4441{ 4442 unsigned int r_idx = skb->queue_mapping; 4443 4444 if (r_idx >= adapter->num_tx_queues) 4445 r_idx = r_idx % adapter->num_tx_queues; 4446 4447 return adapter->tx_ring[r_idx]; 4448} 4449 4450static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 4451 struct net_device *netdev) 4452{ 4453 struct igb_adapter *adapter = netdev_priv(netdev); 4454 4455 if (test_bit(__IGB_DOWN, &adapter->state)) { 4456 dev_kfree_skb_any(skb); 4457 return NETDEV_TX_OK; 4458 } 4459 4460 if (skb->len <= 0) { 4461 dev_kfree_skb_any(skb); 4462 return NETDEV_TX_OK; 4463 } 4464 4465 /* 4466 * The minimum packet size with TCTL.PSP set is 17 so pad the skb 4467 * in order to meet this minimum size requirement. 4468 */ 4469 if (skb->len < 17) { 4470 if (skb_padto(skb, 17)) 4471 return NETDEV_TX_OK; 4472 skb->len = 17; 4473 } 4474 4475 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 4476} 4477 4478/** 4479 * igb_tx_timeout - Respond to a Tx Hang 4480 * @netdev: network interface device structure 4481 **/ 4482static void igb_tx_timeout(struct net_device *netdev) 4483{ 4484 struct igb_adapter *adapter = netdev_priv(netdev); 4485 struct e1000_hw *hw = &adapter->hw; 4486 4487 /* Do the reset outside of interrupt context */ 4488 adapter->tx_timeout_count++; 4489 4490 if (hw->mac.type >= e1000_82580) 4491 hw->dev_spec._82575.global_device_reset = true; 4492 4493 schedule_work(&adapter->reset_task); 4494 wr32(E1000_EICS, 4495 (adapter->eims_enable_mask & ~adapter->eims_other)); 4496} 4497 4498static void igb_reset_task(struct work_struct *work) 4499{ 4500 struct igb_adapter *adapter; 4501 adapter = container_of(work, struct igb_adapter, reset_task); 4502 4503 igb_dump(adapter); 4504 netdev_err(adapter->netdev, "Reset adapter\n"); 4505 igb_reinit_locked(adapter); 4506} 4507 4508/** 4509 * igb_get_stats64 - Get System Network Statistics 4510 * @netdev: network interface device structure 4511 * @stats: rtnl_link_stats64 pointer 4512 * 4513 **/ 4514static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 4515 struct rtnl_link_stats64 *stats) 4516{ 4517 struct igb_adapter *adapter = netdev_priv(netdev); 4518 4519 spin_lock(&adapter->stats64_lock); 4520 igb_update_stats(adapter, &adapter->stats64); 4521 memcpy(stats, &adapter->stats64, sizeof(*stats)); 4522 spin_unlock(&adapter->stats64_lock); 4523 4524 return stats; 4525} 4526 4527/** 4528 * igb_change_mtu - Change the Maximum Transfer Unit 4529 * @netdev: network interface device structure 4530 * @new_mtu: new value for maximum frame size 4531 * 4532 * Returns 0 on success, negative on failure 4533 **/ 4534static int igb_change_mtu(struct net_device *netdev, int new_mtu) 4535{ 4536 struct igb_adapter *adapter = netdev_priv(netdev); 4537 struct pci_dev *pdev = adapter->pdev; 4538 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 4539 4540 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 4541 dev_err(&pdev->dev, "Invalid MTU setting\n"); 4542 return -EINVAL; 4543 } 4544 4545#define MAX_STD_JUMBO_FRAME_SIZE 9238 4546 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 4547 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 4548 return -EINVAL; 4549 } 4550 4551 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 4552 msleep(1); 4553 4554 /* igb_down has a dependency on max_frame_size */ 4555 adapter->max_frame_size = max_frame; 4556 4557 if (netif_running(netdev)) 4558 igb_down(adapter); 4559 4560 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 4561 netdev->mtu, new_mtu); 4562 netdev->mtu = new_mtu; 4563 4564 if (netif_running(netdev)) 4565 igb_up(adapter); 4566 else 4567 igb_reset(adapter); 4568 4569 clear_bit(__IGB_RESETTING, &adapter->state); 4570 4571 return 0; 4572} 4573 4574/** 4575 * igb_update_stats - Update the board statistics counters 4576 * @adapter: board private structure 4577 **/ 4578 4579void igb_update_stats(struct igb_adapter *adapter, 4580 struct rtnl_link_stats64 *net_stats) 4581{ 4582 struct e1000_hw *hw = &adapter->hw; 4583 struct pci_dev *pdev = adapter->pdev; 4584 u32 reg, mpc; 4585 u16 phy_tmp; 4586 int i; 4587 u64 bytes, packets; 4588 unsigned int start; 4589 u64 _bytes, _packets; 4590 4591#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF 4592 4593 /* 4594 * Prevent stats update while adapter is being reset, or if the pci 4595 * connection is down. 4596 */ 4597 if (adapter->link_speed == 0) 4598 return; 4599 if (pci_channel_offline(pdev)) 4600 return; 4601 4602 bytes = 0; 4603 packets = 0; 4604 for (i = 0; i < adapter->num_rx_queues; i++) { 4605 u32 rqdpc = rd32(E1000_RQDPC(i)); 4606 struct igb_ring *ring = adapter->rx_ring[i]; 4607 4608 if (rqdpc) { 4609 ring->rx_stats.drops += rqdpc; 4610 net_stats->rx_fifo_errors += rqdpc; 4611 } 4612 4613 do { 4614 start = u64_stats_fetch_begin_bh(&ring->rx_syncp); 4615 _bytes = ring->rx_stats.bytes; 4616 _packets = ring->rx_stats.packets; 4617 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); 4618 bytes += _bytes; 4619 packets += _packets; 4620 } 4621 4622 net_stats->rx_bytes = bytes; 4623 net_stats->rx_packets = packets; 4624 4625 bytes = 0; 4626 packets = 0; 4627 for (i = 0; i < adapter->num_tx_queues; i++) { 4628 struct igb_ring *ring = adapter->tx_ring[i]; 4629 do { 4630 start = u64_stats_fetch_begin_bh(&ring->tx_syncp); 4631 _bytes = ring->tx_stats.bytes; 4632 _packets = ring->tx_stats.packets; 4633 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); 4634 bytes += _bytes; 4635 packets += _packets; 4636 } 4637 net_stats->tx_bytes = bytes; 4638 net_stats->tx_packets = packets; 4639 4640 /* read stats registers */ 4641 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 4642 adapter->stats.gprc += rd32(E1000_GPRC); 4643 adapter->stats.gorc += rd32(E1000_GORCL); 4644 rd32(E1000_GORCH); /* clear GORCL */ 4645 adapter->stats.bprc += rd32(E1000_BPRC); 4646 adapter->stats.mprc += rd32(E1000_MPRC); 4647 adapter->stats.roc += rd32(E1000_ROC); 4648 4649 adapter->stats.prc64 += rd32(E1000_PRC64); 4650 adapter->stats.prc127 += rd32(E1000_PRC127); 4651 adapter->stats.prc255 += rd32(E1000_PRC255); 4652 adapter->stats.prc511 += rd32(E1000_PRC511); 4653 adapter->stats.prc1023 += rd32(E1000_PRC1023); 4654 adapter->stats.prc1522 += rd32(E1000_PRC1522); 4655 adapter->stats.symerrs += rd32(E1000_SYMERRS); 4656 adapter->stats.sec += rd32(E1000_SEC); 4657 4658 mpc = rd32(E1000_MPC); 4659 adapter->stats.mpc += mpc; 4660 net_stats->rx_fifo_errors += mpc; 4661 adapter->stats.scc += rd32(E1000_SCC); 4662 adapter->stats.ecol += rd32(E1000_ECOL); 4663 adapter->stats.mcc += rd32(E1000_MCC); 4664 adapter->stats.latecol += rd32(E1000_LATECOL); 4665 adapter->stats.dc += rd32(E1000_DC); 4666 adapter->stats.rlec += rd32(E1000_RLEC); 4667 adapter->stats.xonrxc += rd32(E1000_XONRXC); 4668 adapter->stats.xontxc += rd32(E1000_XONTXC); 4669 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 4670 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 4671 adapter->stats.fcruc += rd32(E1000_FCRUC); 4672 adapter->stats.gptc += rd32(E1000_GPTC); 4673 adapter->stats.gotc += rd32(E1000_GOTCL); 4674 rd32(E1000_GOTCH); /* clear GOTCL */ 4675 adapter->stats.rnbc += rd32(E1000_RNBC); 4676 adapter->stats.ruc += rd32(E1000_RUC); 4677 adapter->stats.rfc += rd32(E1000_RFC); 4678 adapter->stats.rjc += rd32(E1000_RJC); 4679 adapter->stats.tor += rd32(E1000_TORH); 4680 adapter->stats.tot += rd32(E1000_TOTH); 4681 adapter->stats.tpr += rd32(E1000_TPR); 4682 4683 adapter->stats.ptc64 += rd32(E1000_PTC64); 4684 adapter->stats.ptc127 += rd32(E1000_PTC127); 4685 adapter->stats.ptc255 += rd32(E1000_PTC255); 4686 adapter->stats.ptc511 += rd32(E1000_PTC511); 4687 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 4688 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 4689 4690 adapter->stats.mptc += rd32(E1000_MPTC); 4691 adapter->stats.bptc += rd32(E1000_BPTC); 4692 4693 adapter->stats.tpt += rd32(E1000_TPT); 4694 adapter->stats.colc += rd32(E1000_COLC); 4695 4696 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 4697 /* read internal phy specific stats */ 4698 reg = rd32(E1000_CTRL_EXT); 4699 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 4700 adapter->stats.rxerrc += rd32(E1000_RXERRC); 4701 4702 /* this stat has invalid values on i210/i211 */ 4703 if ((hw->mac.type != e1000_i210) && 4704 (hw->mac.type != e1000_i211)) 4705 adapter->stats.tncrs += rd32(E1000_TNCRS); 4706 } 4707 4708 adapter->stats.tsctc += rd32(E1000_TSCTC); 4709 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 4710 4711 adapter->stats.iac += rd32(E1000_IAC); 4712 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 4713 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 4714 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 4715 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 4716 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 4717 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 4718 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 4719 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 4720 4721 /* Fill out the OS statistics structure */ 4722 net_stats->multicast = adapter->stats.mprc; 4723 net_stats->collisions = adapter->stats.colc; 4724 4725 /* Rx Errors */ 4726 4727 /* RLEC on some newer hardware can be incorrect so build 4728 * our own version based on RUC and ROC */ 4729 net_stats->rx_errors = adapter->stats.rxerrc + 4730 adapter->stats.crcerrs + adapter->stats.algnerrc + 4731 adapter->stats.ruc + adapter->stats.roc + 4732 adapter->stats.cexterr; 4733 net_stats->rx_length_errors = adapter->stats.ruc + 4734 adapter->stats.roc; 4735 net_stats->rx_crc_errors = adapter->stats.crcerrs; 4736 net_stats->rx_frame_errors = adapter->stats.algnerrc; 4737 net_stats->rx_missed_errors = adapter->stats.mpc; 4738 4739 /* Tx Errors */ 4740 net_stats->tx_errors = adapter->stats.ecol + 4741 adapter->stats.latecol; 4742 net_stats->tx_aborted_errors = adapter->stats.ecol; 4743 net_stats->tx_window_errors = adapter->stats.latecol; 4744 net_stats->tx_carrier_errors = adapter->stats.tncrs; 4745 4746 /* Tx Dropped needs to be maintained elsewhere */ 4747 4748 /* Phy Stats */ 4749 if (hw->phy.media_type == e1000_media_type_copper) { 4750 if ((adapter->link_speed == SPEED_1000) && 4751 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 4752 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; 4753 adapter->phy_stats.idle_errors += phy_tmp; 4754 } 4755 } 4756 4757 /* Management Stats */ 4758 adapter->stats.mgptc += rd32(E1000_MGTPTC); 4759 adapter->stats.mgprc += rd32(E1000_MGTPRC); 4760 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 4761 4762 /* OS2BMC Stats */ 4763 reg = rd32(E1000_MANC); 4764 if (reg & E1000_MANC_EN_BMC2OS) { 4765 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 4766 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 4767 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 4768 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 4769 } 4770} 4771 4772static irqreturn_t igb_msix_other(int irq, void *data) 4773{ 4774 struct igb_adapter *adapter = data; 4775 struct e1000_hw *hw = &adapter->hw; 4776 u32 icr = rd32(E1000_ICR); 4777 /* reading ICR causes bit 31 of EICR to be cleared */ 4778 4779 if (icr & E1000_ICR_DRSTA) 4780 schedule_work(&adapter->reset_task); 4781 4782 if (icr & E1000_ICR_DOUTSYNC) { 4783 /* HW is reporting DMA is out of sync */ 4784 adapter->stats.doosync++; 4785 /* The DMA Out of Sync is also indication of a spoof event 4786 * in IOV mode. Check the Wrong VM Behavior register to 4787 * see if it is really a spoof event. */ 4788 igb_check_wvbr(adapter); 4789 } 4790 4791 /* Check for a mailbox event */ 4792 if (icr & E1000_ICR_VMMB) 4793 igb_msg_task(adapter); 4794 4795 if (icr & E1000_ICR_LSC) { 4796 hw->mac.get_link_status = 1; 4797 /* guard against interrupt when we're going down */ 4798 if (!test_bit(__IGB_DOWN, &adapter->state)) 4799 mod_timer(&adapter->watchdog_timer, jiffies + 1); 4800 } 4801 4802#ifdef CONFIG_IGB_PTP 4803 if (icr & E1000_ICR_TS) { 4804 u32 tsicr = rd32(E1000_TSICR); 4805 4806 if (tsicr & E1000_TSICR_TXTS) { 4807 /* acknowledge the interrupt */ 4808 wr32(E1000_TSICR, E1000_TSICR_TXTS); 4809 /* retrieve hardware timestamp */ 4810 schedule_work(&adapter->ptp_tx_work); 4811 } 4812 } 4813#endif /* CONFIG_IGB_PTP */ 4814 4815 wr32(E1000_EIMS, adapter->eims_other); 4816 4817 return IRQ_HANDLED; 4818} 4819 4820static void igb_write_itr(struct igb_q_vector *q_vector) 4821{ 4822 struct igb_adapter *adapter = q_vector->adapter; 4823 u32 itr_val = q_vector->itr_val & 0x7FFC; 4824 4825 if (!q_vector->set_itr) 4826 return; 4827 4828 if (!itr_val) 4829 itr_val = 0x4; 4830 4831 if (adapter->hw.mac.type == e1000_82575) 4832 itr_val |= itr_val << 16; 4833 else 4834 itr_val |= E1000_EITR_CNT_IGNR; 4835 4836 writel(itr_val, q_vector->itr_register); 4837 q_vector->set_itr = 0; 4838} 4839 4840static irqreturn_t igb_msix_ring(int irq, void *data) 4841{ 4842 struct igb_q_vector *q_vector = data; 4843 4844 /* Write the ITR value calculated from the previous interrupt. */ 4845 igb_write_itr(q_vector); 4846 4847 napi_schedule(&q_vector->napi); 4848 4849 return IRQ_HANDLED; 4850} 4851 4852#ifdef CONFIG_IGB_DCA 4853static void igb_update_dca(struct igb_q_vector *q_vector) 4854{ 4855 struct igb_adapter *adapter = q_vector->adapter; 4856 struct e1000_hw *hw = &adapter->hw; 4857 int cpu = get_cpu(); 4858 4859 if (q_vector->cpu == cpu) 4860 goto out_no_update; 4861 4862 if (q_vector->tx.ring) { 4863 int q = q_vector->tx.ring->reg_idx; 4864 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q)); 4865 if (hw->mac.type == e1000_82575) { 4866 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK; 4867 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); 4868 } else { 4869 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576; 4870 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << 4871 E1000_DCA_TXCTRL_CPUID_SHIFT; 4872 } 4873 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN; 4874 wr32(E1000_DCA_TXCTRL(q), dca_txctrl); 4875 } 4876 if (q_vector->rx.ring) { 4877 int q = q_vector->rx.ring->reg_idx; 4878 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q)); 4879 if (hw->mac.type == e1000_82575) { 4880 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK; 4881 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); 4882 } else { 4883 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576; 4884 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << 4885 E1000_DCA_RXCTRL_CPUID_SHIFT; 4886 } 4887 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN; 4888 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN; 4889 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN; 4890 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl); 4891 } 4892 q_vector->cpu = cpu; 4893out_no_update: 4894 put_cpu(); 4895} 4896 4897static void igb_setup_dca(struct igb_adapter *adapter) 4898{ 4899 struct e1000_hw *hw = &adapter->hw; 4900 int i; 4901 4902 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 4903 return; 4904 4905 /* Always use CB2 mode, difference is masked in the CB driver. */ 4906 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 4907 4908 for (i = 0; i < adapter->num_q_vectors; i++) { 4909 adapter->q_vector[i]->cpu = -1; 4910 igb_update_dca(adapter->q_vector[i]); 4911 } 4912} 4913 4914static int __igb_notify_dca(struct device *dev, void *data) 4915{ 4916 struct net_device *netdev = dev_get_drvdata(dev); 4917 struct igb_adapter *adapter = netdev_priv(netdev); 4918 struct pci_dev *pdev = adapter->pdev; 4919 struct e1000_hw *hw = &adapter->hw; 4920 unsigned long event = *(unsigned long *)data; 4921 4922 switch (event) { 4923 case DCA_PROVIDER_ADD: 4924 /* if already enabled, don't do it again */ 4925 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 4926 break; 4927 if (dca_add_requester(dev) == 0) { 4928 adapter->flags |= IGB_FLAG_DCA_ENABLED; 4929 dev_info(&pdev->dev, "DCA enabled\n"); 4930 igb_setup_dca(adapter); 4931 break; 4932 } 4933 /* Fall Through since DCA is disabled. */ 4934 case DCA_PROVIDER_REMOVE: 4935 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 4936 /* without this a class_device is left 4937 * hanging around in the sysfs model */ 4938 dca_remove_requester(dev); 4939 dev_info(&pdev->dev, "DCA disabled\n"); 4940 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 4941 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 4942 } 4943 break; 4944 } 4945 4946 return 0; 4947} 4948 4949static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 4950 void *p) 4951{ 4952 int ret_val; 4953 4954 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 4955 __igb_notify_dca); 4956 4957 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 4958} 4959#endif /* CONFIG_IGB_DCA */ 4960 4961#ifdef CONFIG_PCI_IOV 4962static int igb_vf_configure(struct igb_adapter *adapter, int vf) 4963{ 4964 unsigned char mac_addr[ETH_ALEN]; 4965 4966 eth_random_addr(mac_addr); 4967 igb_set_vf_mac(adapter, vf, mac_addr); 4968 4969 return 0; 4970} 4971 4972static bool igb_vfs_are_assigned(struct igb_adapter *adapter) 4973{ 4974 struct pci_dev *pdev = adapter->pdev; 4975 struct pci_dev *vfdev; 4976 int dev_id; 4977 4978 switch (adapter->hw.mac.type) { 4979 case e1000_82576: 4980 dev_id = IGB_82576_VF_DEV_ID; 4981 break; 4982 case e1000_i350: 4983 dev_id = IGB_I350_VF_DEV_ID; 4984 break; 4985 default: 4986 return false; 4987 } 4988 4989 /* loop through all the VFs to see if we own any that are assigned */ 4990 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL); 4991 while (vfdev) { 4992 /* if we don't own it we don't care */ 4993 if (vfdev->is_virtfn && vfdev->physfn == pdev) { 4994 /* if it is assigned we cannot release it */ 4995 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) 4996 return true; 4997 } 4998 4999 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev); 5000 } 5001 5002 return false; 5003} 5004 5005#endif 5006static void igb_ping_all_vfs(struct igb_adapter *adapter) 5007{ 5008 struct e1000_hw *hw = &adapter->hw; 5009 u32 ping; 5010 int i; 5011 5012 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5013 ping = E1000_PF_CONTROL_MSG; 5014 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5015 ping |= E1000_VT_MSGTYPE_CTS; 5016 igb_write_mbx(hw, &ping, 1, i); 5017 } 5018} 5019 5020static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5021{ 5022 struct e1000_hw *hw = &adapter->hw; 5023 u32 vmolr = rd32(E1000_VMOLR(vf)); 5024 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5025 5026 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5027 IGB_VF_FLAG_MULTI_PROMISC); 5028 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5029 5030 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5031 vmolr |= E1000_VMOLR_MPME; 5032 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5033 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5034 } else { 5035 /* 5036 * if we have hashes and we are clearing a multicast promisc 5037 * flag we need to write the hashes to the MTA as this step 5038 * was previously skipped 5039 */ 5040 if (vf_data->num_vf_mc_hashes > 30) { 5041 vmolr |= E1000_VMOLR_MPME; 5042 } else if (vf_data->num_vf_mc_hashes) { 5043 int j; 5044 vmolr |= E1000_VMOLR_ROMPE; 5045 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5046 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5047 } 5048 } 5049 5050 wr32(E1000_VMOLR(vf), vmolr); 5051 5052 /* there are flags left unprocessed, likely not supported */ 5053 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5054 return -EINVAL; 5055 5056 return 0; 5057 5058} 5059 5060static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5061 u32 *msgbuf, u32 vf) 5062{ 5063 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5064 u16 *hash_list = (u16 *)&msgbuf[1]; 5065 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5066 int i; 5067 5068 /* salt away the number of multicast addresses assigned 5069 * to this VF for later use to restore when the PF multi cast 5070 * list changes 5071 */ 5072 vf_data->num_vf_mc_hashes = n; 5073 5074 /* only up to 30 hash values supported */ 5075 if (n > 30) 5076 n = 30; 5077 5078 /* store the hashes for later use */ 5079 for (i = 0; i < n; i++) 5080 vf_data->vf_mc_hashes[i] = hash_list[i]; 5081 5082 /* Flush and reset the mta with the new values */ 5083 igb_set_rx_mode(adapter->netdev); 5084 5085 return 0; 5086} 5087 5088static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5089{ 5090 struct e1000_hw *hw = &adapter->hw; 5091 struct vf_data_storage *vf_data; 5092 int i, j; 5093 5094 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5095 u32 vmolr = rd32(E1000_VMOLR(i)); 5096 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5097 5098 vf_data = &adapter->vf_data[i]; 5099 5100 if ((vf_data->num_vf_mc_hashes > 30) || 5101 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5102 vmolr |= E1000_VMOLR_MPME; 5103 } else if (vf_data->num_vf_mc_hashes) { 5104 vmolr |= E1000_VMOLR_ROMPE; 5105 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5106 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5107 } 5108 wr32(E1000_VMOLR(i), vmolr); 5109 } 5110} 5111 5112static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5113{ 5114 struct e1000_hw *hw = &adapter->hw; 5115 u32 pool_mask, reg, vid; 5116 int i; 5117 5118 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5119 5120 /* Find the vlan filter for this id */ 5121 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5122 reg = rd32(E1000_VLVF(i)); 5123 5124 /* remove the vf from the pool */ 5125 reg &= ~pool_mask; 5126 5127 /* if pool is empty then remove entry from vfta */ 5128 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5129 (reg & E1000_VLVF_VLANID_ENABLE)) { 5130 reg = 0; 5131 vid = reg & E1000_VLVF_VLANID_MASK; 5132 igb_vfta_set(hw, vid, false); 5133 } 5134 5135 wr32(E1000_VLVF(i), reg); 5136 } 5137 5138 adapter->vf_data[vf].vlans_enabled = 0; 5139} 5140 5141static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5142{ 5143 struct e1000_hw *hw = &adapter->hw; 5144 u32 reg, i; 5145 5146 /* The vlvf table only exists on 82576 hardware and newer */ 5147 if (hw->mac.type < e1000_82576) 5148 return -1; 5149 5150 /* we only need to do this if VMDq is enabled */ 5151 if (!adapter->vfs_allocated_count) 5152 return -1; 5153 5154 /* Find the vlan filter for this id */ 5155 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5156 reg = rd32(E1000_VLVF(i)); 5157 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5158 vid == (reg & E1000_VLVF_VLANID_MASK)) 5159 break; 5160 } 5161 5162 if (add) { 5163 if (i == E1000_VLVF_ARRAY_SIZE) { 5164 /* Did not find a matching VLAN ID entry that was 5165 * enabled. Search for a free filter entry, i.e. 5166 * one without the enable bit set 5167 */ 5168 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5169 reg = rd32(E1000_VLVF(i)); 5170 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5171 break; 5172 } 5173 } 5174 if (i < E1000_VLVF_ARRAY_SIZE) { 5175 /* Found an enabled/available entry */ 5176 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5177 5178 /* if !enabled we need to set this up in vfta */ 5179 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5180 /* add VID to filter table */ 5181 igb_vfta_set(hw, vid, true); 5182 reg |= E1000_VLVF_VLANID_ENABLE; 5183 } 5184 reg &= ~E1000_VLVF_VLANID_MASK; 5185 reg |= vid; 5186 wr32(E1000_VLVF(i), reg); 5187 5188 /* do not modify RLPML for PF devices */ 5189 if (vf >= adapter->vfs_allocated_count) 5190 return 0; 5191 5192 if (!adapter->vf_data[vf].vlans_enabled) { 5193 u32 size; 5194 reg = rd32(E1000_VMOLR(vf)); 5195 size = reg & E1000_VMOLR_RLPML_MASK; 5196 size += 4; 5197 reg &= ~E1000_VMOLR_RLPML_MASK; 5198 reg |= size; 5199 wr32(E1000_VMOLR(vf), reg); 5200 } 5201 5202 adapter->vf_data[vf].vlans_enabled++; 5203 } 5204 } else { 5205 if (i < E1000_VLVF_ARRAY_SIZE) { 5206 /* remove vf from the pool */ 5207 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5208 /* if pool is empty then remove entry from vfta */ 5209 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5210 reg = 0; 5211 igb_vfta_set(hw, vid, false); 5212 } 5213 wr32(E1000_VLVF(i), reg); 5214 5215 /* do not modify RLPML for PF devices */ 5216 if (vf >= adapter->vfs_allocated_count) 5217 return 0; 5218 5219 adapter->vf_data[vf].vlans_enabled--; 5220 if (!adapter->vf_data[vf].vlans_enabled) { 5221 u32 size; 5222 reg = rd32(E1000_VMOLR(vf)); 5223 size = reg & E1000_VMOLR_RLPML_MASK; 5224 size -= 4; 5225 reg &= ~E1000_VMOLR_RLPML_MASK; 5226 reg |= size; 5227 wr32(E1000_VMOLR(vf), reg); 5228 } 5229 } 5230 } 5231 return 0; 5232} 5233 5234static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5235{ 5236 struct e1000_hw *hw = &adapter->hw; 5237 5238 if (vid) 5239 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5240 else 5241 wr32(E1000_VMVIR(vf), 0); 5242} 5243 5244static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5245 int vf, u16 vlan, u8 qos) 5246{ 5247 int err = 0; 5248 struct igb_adapter *adapter = netdev_priv(netdev); 5249 5250 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5251 return -EINVAL; 5252 if (vlan || qos) { 5253 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5254 if (err) 5255 goto out; 5256 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5257 igb_set_vmolr(adapter, vf, !vlan); 5258 adapter->vf_data[vf].pf_vlan = vlan; 5259 adapter->vf_data[vf].pf_qos = qos; 5260 dev_info(&adapter->pdev->dev, 5261 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5262 if (test_bit(__IGB_DOWN, &adapter->state)) { 5263 dev_warn(&adapter->pdev->dev, 5264 "The VF VLAN has been set," 5265 " but the PF device is not up.\n"); 5266 dev_warn(&adapter->pdev->dev, 5267 "Bring the PF device up before" 5268 " attempting to use the VF device.\n"); 5269 } 5270 } else { 5271 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5272 false, vf); 5273 igb_set_vmvir(adapter, vlan, vf); 5274 igb_set_vmolr(adapter, vf, true); 5275 adapter->vf_data[vf].pf_vlan = 0; 5276 adapter->vf_data[vf].pf_qos = 0; 5277 } 5278out: 5279 return err; 5280} 5281 5282static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5283{ 5284 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5285 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5286 5287 return igb_vlvf_set(adapter, vid, add, vf); 5288} 5289 5290static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 5291{ 5292 /* clear flags - except flag that indicates PF has set the MAC */ 5293 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 5294 adapter->vf_data[vf].last_nack = jiffies; 5295 5296 /* reset offloads to defaults */ 5297 igb_set_vmolr(adapter, vf, true); 5298 5299 /* reset vlans for device */ 5300 igb_clear_vf_vfta(adapter, vf); 5301 if (adapter->vf_data[vf].pf_vlan) 5302 igb_ndo_set_vf_vlan(adapter->netdev, vf, 5303 adapter->vf_data[vf].pf_vlan, 5304 adapter->vf_data[vf].pf_qos); 5305 else 5306 igb_clear_vf_vfta(adapter, vf); 5307 5308 /* reset multicast table array for vf */ 5309 adapter->vf_data[vf].num_vf_mc_hashes = 0; 5310 5311 /* Flush and reset the mta with the new values */ 5312 igb_set_rx_mode(adapter->netdev); 5313} 5314 5315static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 5316{ 5317 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5318 5319 /* generate a new mac address as we were hotplug removed/added */ 5320 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 5321 eth_random_addr(vf_mac); 5322 5323 /* process remaining reset events */ 5324 igb_vf_reset(adapter, vf); 5325} 5326 5327static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 5328{ 5329 struct e1000_hw *hw = &adapter->hw; 5330 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5331 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 5332 u32 reg, msgbuf[3]; 5333 u8 *addr = (u8 *)(&msgbuf[1]); 5334 5335 /* process all the same items cleared in a function level reset */ 5336 igb_vf_reset(adapter, vf); 5337 5338 /* set vf mac address */ 5339 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 5340 5341 /* enable transmit and receive for vf */ 5342 reg = rd32(E1000_VFTE); 5343 wr32(E1000_VFTE, reg | (1 << vf)); 5344 reg = rd32(E1000_VFRE); 5345 wr32(E1000_VFRE, reg | (1 << vf)); 5346 5347 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 5348 5349 /* reply to reset with ack and vf mac address */ 5350 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 5351 memcpy(addr, vf_mac, 6); 5352 igb_write_mbx(hw, msgbuf, 3, vf); 5353} 5354 5355static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 5356{ 5357 /* 5358 * The VF MAC Address is stored in a packed array of bytes 5359 * starting at the second 32 bit word of the msg array 5360 */ 5361 unsigned char *addr = (char *)&msg[1]; 5362 int err = -1; 5363 5364 if (is_valid_ether_addr(addr)) 5365 err = igb_set_vf_mac(adapter, vf, addr); 5366 5367 return err; 5368} 5369 5370static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 5371{ 5372 struct e1000_hw *hw = &adapter->hw; 5373 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5374 u32 msg = E1000_VT_MSGTYPE_NACK; 5375 5376 /* if device isn't clear to send it shouldn't be reading either */ 5377 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 5378 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 5379 igb_write_mbx(hw, &msg, 1, vf); 5380 vf_data->last_nack = jiffies; 5381 } 5382} 5383 5384static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 5385{ 5386 struct pci_dev *pdev = adapter->pdev; 5387 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 5388 struct e1000_hw *hw = &adapter->hw; 5389 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5390 s32 retval; 5391 5392 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 5393 5394 if (retval) { 5395 /* if receive failed revoke VF CTS stats and restart init */ 5396 dev_err(&pdev->dev, "Error receiving message from VF\n"); 5397 vf_data->flags &= ~IGB_VF_FLAG_CTS; 5398 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 5399 return; 5400 goto out; 5401 } 5402 5403 /* this is a message we already processed, do nothing */ 5404 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 5405 return; 5406 5407 /* 5408 * until the vf completes a reset it should not be 5409 * allowed to start any configuration. 5410 */ 5411 5412 if (msgbuf[0] == E1000_VF_RESET) { 5413 igb_vf_reset_msg(adapter, vf); 5414 return; 5415 } 5416 5417 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 5418 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 5419 return; 5420 retval = -1; 5421 goto out; 5422 } 5423 5424 switch ((msgbuf[0] & 0xFFFF)) { 5425 case E1000_VF_SET_MAC_ADDR: 5426 retval = -EINVAL; 5427 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 5428 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 5429 else 5430 dev_warn(&pdev->dev, 5431 "VF %d attempted to override administratively " 5432 "set MAC address\nReload the VF driver to " 5433 "resume operations\n", vf); 5434 break; 5435 case E1000_VF_SET_PROMISC: 5436 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 5437 break; 5438 case E1000_VF_SET_MULTICAST: 5439 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 5440 break; 5441 case E1000_VF_SET_LPE: 5442 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 5443 break; 5444 case E1000_VF_SET_VLAN: 5445 retval = -1; 5446 if (vf_data->pf_vlan) 5447 dev_warn(&pdev->dev, 5448 "VF %d attempted to override administratively " 5449 "set VLAN tag\nReload the VF driver to " 5450 "resume operations\n", vf); 5451 else 5452 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 5453 break; 5454 default: 5455 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 5456 retval = -1; 5457 break; 5458 } 5459 5460 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 5461out: 5462 /* notify the VF of the results of what it sent us */ 5463 if (retval) 5464 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 5465 else 5466 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 5467 5468 igb_write_mbx(hw, msgbuf, 1, vf); 5469} 5470 5471static void igb_msg_task(struct igb_adapter *adapter) 5472{ 5473 struct e1000_hw *hw = &adapter->hw; 5474 u32 vf; 5475 5476 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 5477 /* process any reset requests */ 5478 if (!igb_check_for_rst(hw, vf)) 5479 igb_vf_reset_event(adapter, vf); 5480 5481 /* process any messages pending */ 5482 if (!igb_check_for_msg(hw, vf)) 5483 igb_rcv_msg_from_vf(adapter, vf); 5484 5485 /* process any acks */ 5486 if (!igb_check_for_ack(hw, vf)) 5487 igb_rcv_ack_from_vf(adapter, vf); 5488 } 5489} 5490 5491/** 5492 * igb_set_uta - Set unicast filter table address 5493 * @adapter: board private structure 5494 * 5495 * The unicast table address is a register array of 32-bit registers. 5496 * The table is meant to be used in a way similar to how the MTA is used 5497 * however due to certain limitations in the hardware it is necessary to 5498 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 5499 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 5500 **/ 5501static void igb_set_uta(struct igb_adapter *adapter) 5502{ 5503 struct e1000_hw *hw = &adapter->hw; 5504 int i; 5505 5506 /* The UTA table only exists on 82576 hardware and newer */ 5507 if (hw->mac.type < e1000_82576) 5508 return; 5509 5510 /* we only need to do this if VMDq is enabled */ 5511 if (!adapter->vfs_allocated_count) 5512 return; 5513 5514 for (i = 0; i < hw->mac.uta_reg_count; i++) 5515 array_wr32(E1000_UTA, i, ~0); 5516} 5517 5518/** 5519 * igb_intr_msi - Interrupt Handler 5520 * @irq: interrupt number 5521 * @data: pointer to a network interface device structure 5522 **/ 5523static irqreturn_t igb_intr_msi(int irq, void *data) 5524{ 5525 struct igb_adapter *adapter = data; 5526 struct igb_q_vector *q_vector = adapter->q_vector[0]; 5527 struct e1000_hw *hw = &adapter->hw; 5528 /* read ICR disables interrupts using IAM */ 5529 u32 icr = rd32(E1000_ICR); 5530 5531 igb_write_itr(q_vector); 5532 5533 if (icr & E1000_ICR_DRSTA) 5534 schedule_work(&adapter->reset_task); 5535 5536 if (icr & E1000_ICR_DOUTSYNC) { 5537 /* HW is reporting DMA is out of sync */ 5538 adapter->stats.doosync++; 5539 } 5540 5541 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 5542 hw->mac.get_link_status = 1; 5543 if (!test_bit(__IGB_DOWN, &adapter->state)) 5544 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5545 } 5546 5547#ifdef CONFIG_IGB_PTP 5548 if (icr & E1000_ICR_TS) { 5549 u32 tsicr = rd32(E1000_TSICR); 5550 5551 if (tsicr & E1000_TSICR_TXTS) { 5552 /* acknowledge the interrupt */ 5553 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5554 /* retrieve hardware timestamp */ 5555 schedule_work(&adapter->ptp_tx_work); 5556 } 5557 } 5558#endif /* CONFIG_IGB_PTP */ 5559 5560 napi_schedule(&q_vector->napi); 5561 5562 return IRQ_HANDLED; 5563} 5564 5565/** 5566 * igb_intr - Legacy Interrupt Handler 5567 * @irq: interrupt number 5568 * @data: pointer to a network interface device structure 5569 **/ 5570static irqreturn_t igb_intr(int irq, void *data) 5571{ 5572 struct igb_adapter *adapter = data; 5573 struct igb_q_vector *q_vector = adapter->q_vector[0]; 5574 struct e1000_hw *hw = &adapter->hw; 5575 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 5576 * need for the IMC write */ 5577 u32 icr = rd32(E1000_ICR); 5578 5579 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 5580 * not set, then the adapter didn't send an interrupt */ 5581 if (!(icr & E1000_ICR_INT_ASSERTED)) 5582 return IRQ_NONE; 5583 5584 igb_write_itr(q_vector); 5585 5586 if (icr & E1000_ICR_DRSTA) 5587 schedule_work(&adapter->reset_task); 5588 5589 if (icr & E1000_ICR_DOUTSYNC) { 5590 /* HW is reporting DMA is out of sync */ 5591 adapter->stats.doosync++; 5592 } 5593 5594 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 5595 hw->mac.get_link_status = 1; 5596 /* guard against interrupt when we're going down */ 5597 if (!test_bit(__IGB_DOWN, &adapter->state)) 5598 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5599 } 5600 5601#ifdef CONFIG_IGB_PTP 5602 if (icr & E1000_ICR_TS) { 5603 u32 tsicr = rd32(E1000_TSICR); 5604 5605 if (tsicr & E1000_TSICR_TXTS) { 5606 /* acknowledge the interrupt */ 5607 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5608 /* retrieve hardware timestamp */ 5609 schedule_work(&adapter->ptp_tx_work); 5610 } 5611 } 5612#endif /* CONFIG_IGB_PTP */ 5613 5614 napi_schedule(&q_vector->napi); 5615 5616 return IRQ_HANDLED; 5617} 5618 5619static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 5620{ 5621 struct igb_adapter *adapter = q_vector->adapter; 5622 struct e1000_hw *hw = &adapter->hw; 5623 5624 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 5625 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 5626 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 5627 igb_set_itr(q_vector); 5628 else 5629 igb_update_ring_itr(q_vector); 5630 } 5631 5632 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5633 if (adapter->msix_entries) 5634 wr32(E1000_EIMS, q_vector->eims_value); 5635 else 5636 igb_irq_enable(adapter); 5637 } 5638} 5639 5640/** 5641 * igb_poll - NAPI Rx polling callback 5642 * @napi: napi polling structure 5643 * @budget: count of how many packets we should handle 5644 **/ 5645static int igb_poll(struct napi_struct *napi, int budget) 5646{ 5647 struct igb_q_vector *q_vector = container_of(napi, 5648 struct igb_q_vector, 5649 napi); 5650 bool clean_complete = true; 5651 5652#ifdef CONFIG_IGB_DCA 5653 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 5654 igb_update_dca(q_vector); 5655#endif 5656 if (q_vector->tx.ring) 5657 clean_complete = igb_clean_tx_irq(q_vector); 5658 5659 if (q_vector->rx.ring) 5660 clean_complete &= igb_clean_rx_irq(q_vector, budget); 5661 5662 /* If all work not completed, return budget and keep polling */ 5663 if (!clean_complete) 5664 return budget; 5665 5666 /* If not enough Rx work done, exit the polling mode */ 5667 napi_complete(napi); 5668 igb_ring_irq_enable(q_vector); 5669 5670 return 0; 5671} 5672 5673/** 5674 * igb_clean_tx_irq - Reclaim resources after transmit completes 5675 * @q_vector: pointer to q_vector containing needed info 5676 * 5677 * returns true if ring is completely cleaned 5678 **/ 5679static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 5680{ 5681 struct igb_adapter *adapter = q_vector->adapter; 5682 struct igb_ring *tx_ring = q_vector->tx.ring; 5683 struct igb_tx_buffer *tx_buffer; 5684 union e1000_adv_tx_desc *tx_desc; 5685 unsigned int total_bytes = 0, total_packets = 0; 5686 unsigned int budget = q_vector->tx.work_limit; 5687 unsigned int i = tx_ring->next_to_clean; 5688 5689 if (test_bit(__IGB_DOWN, &adapter->state)) 5690 return true; 5691 5692 tx_buffer = &tx_ring->tx_buffer_info[i]; 5693 tx_desc = IGB_TX_DESC(tx_ring, i); 5694 i -= tx_ring->count; 5695 5696 do { 5697 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 5698 5699 /* if next_to_watch is not set then there is no work pending */ 5700 if (!eop_desc) 5701 break; 5702 5703 /* prevent any other reads prior to eop_desc */ 5704 rmb(); 5705 5706 /* if DD is not set pending work has not been completed */ 5707 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 5708 break; 5709 5710 /* clear next_to_watch to prevent false hangs */ 5711 tx_buffer->next_to_watch = NULL; 5712 5713 /* update the statistics for this packet */ 5714 total_bytes += tx_buffer->bytecount; 5715 total_packets += tx_buffer->gso_segs; 5716 5717 /* free the skb */ 5718 dev_kfree_skb_any(tx_buffer->skb); 5719 tx_buffer->skb = NULL; 5720 5721 /* unmap skb header data */ 5722 dma_unmap_single(tx_ring->dev, 5723 tx_buffer->dma, 5724 tx_buffer->length, 5725 DMA_TO_DEVICE); 5726 5727 /* clear last DMA location and unmap remaining buffers */ 5728 while (tx_desc != eop_desc) { 5729 tx_buffer->dma = 0; 5730 5731 tx_buffer++; 5732 tx_desc++; 5733 i++; 5734 if (unlikely(!i)) { 5735 i -= tx_ring->count; 5736 tx_buffer = tx_ring->tx_buffer_info; 5737 tx_desc = IGB_TX_DESC(tx_ring, 0); 5738 } 5739 5740 /* unmap any remaining paged data */ 5741 if (tx_buffer->dma) { 5742 dma_unmap_page(tx_ring->dev, 5743 tx_buffer->dma, 5744 tx_buffer->length, 5745 DMA_TO_DEVICE); 5746 } 5747 } 5748 5749 /* clear last DMA location */ 5750 tx_buffer->dma = 0; 5751 5752 /* move us one more past the eop_desc for start of next pkt */ 5753 tx_buffer++; 5754 tx_desc++; 5755 i++; 5756 if (unlikely(!i)) { 5757 i -= tx_ring->count; 5758 tx_buffer = tx_ring->tx_buffer_info; 5759 tx_desc = IGB_TX_DESC(tx_ring, 0); 5760 } 5761 5762 /* issue prefetch for next Tx descriptor */ 5763 prefetch(tx_desc); 5764 5765 /* update budget accounting */ 5766 budget--; 5767 } while (likely(budget)); 5768 5769 netdev_tx_completed_queue(txring_txq(tx_ring), 5770 total_packets, total_bytes); 5771 i += tx_ring->count; 5772 tx_ring->next_to_clean = i; 5773 u64_stats_update_begin(&tx_ring->tx_syncp); 5774 tx_ring->tx_stats.bytes += total_bytes; 5775 tx_ring->tx_stats.packets += total_packets; 5776 u64_stats_update_end(&tx_ring->tx_syncp); 5777 q_vector->tx.total_bytes += total_bytes; 5778 q_vector->tx.total_packets += total_packets; 5779 5780 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 5781 struct e1000_hw *hw = &adapter->hw; 5782 5783 /* Detect a transmit hang in hardware, this serializes the 5784 * check with the clearing of time_stamp and movement of i */ 5785 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5786 if (tx_buffer->next_to_watch && 5787 time_after(jiffies, tx_buffer->time_stamp + 5788 (adapter->tx_timeout_factor * HZ)) && 5789 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 5790 5791 /* detected Tx unit hang */ 5792 dev_err(tx_ring->dev, 5793 "Detected Tx Unit Hang\n" 5794 " Tx Queue <%d>\n" 5795 " TDH <%x>\n" 5796 " TDT <%x>\n" 5797 " next_to_use <%x>\n" 5798 " next_to_clean <%x>\n" 5799 "buffer_info[next_to_clean]\n" 5800 " time_stamp <%lx>\n" 5801 " next_to_watch <%p>\n" 5802 " jiffies <%lx>\n" 5803 " desc.status <%x>\n", 5804 tx_ring->queue_index, 5805 rd32(E1000_TDH(tx_ring->reg_idx)), 5806 readl(tx_ring->tail), 5807 tx_ring->next_to_use, 5808 tx_ring->next_to_clean, 5809 tx_buffer->time_stamp, 5810 tx_buffer->next_to_watch, 5811 jiffies, 5812 tx_buffer->next_to_watch->wb.status); 5813 netif_stop_subqueue(tx_ring->netdev, 5814 tx_ring->queue_index); 5815 5816 /* we are about to reset, no point in enabling stuff */ 5817 return true; 5818 } 5819 } 5820 5821 if (unlikely(total_packets && 5822 netif_carrier_ok(tx_ring->netdev) && 5823 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) { 5824 /* Make sure that anybody stopping the queue after this 5825 * sees the new next_to_clean. 5826 */ 5827 smp_mb(); 5828 if (__netif_subqueue_stopped(tx_ring->netdev, 5829 tx_ring->queue_index) && 5830 !(test_bit(__IGB_DOWN, &adapter->state))) { 5831 netif_wake_subqueue(tx_ring->netdev, 5832 tx_ring->queue_index); 5833 5834 u64_stats_update_begin(&tx_ring->tx_syncp); 5835 tx_ring->tx_stats.restart_queue++; 5836 u64_stats_update_end(&tx_ring->tx_syncp); 5837 } 5838 } 5839 5840 return !!budget; 5841} 5842 5843static inline void igb_rx_checksum(struct igb_ring *ring, 5844 union e1000_adv_rx_desc *rx_desc, 5845 struct sk_buff *skb) 5846{ 5847 skb_checksum_none_assert(skb); 5848 5849 /* Ignore Checksum bit is set */ 5850 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 5851 return; 5852 5853 /* Rx checksum disabled via ethtool */ 5854 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 5855 return; 5856 5857 /* TCP/UDP checksum error bit is set */ 5858 if (igb_test_staterr(rx_desc, 5859 E1000_RXDEXT_STATERR_TCPE | 5860 E1000_RXDEXT_STATERR_IPE)) { 5861 /* 5862 * work around errata with sctp packets where the TCPE aka 5863 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 5864 * packets, (aka let the stack check the crc32c) 5865 */ 5866 if (!((skb->len == 60) && 5867 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 5868 u64_stats_update_begin(&ring->rx_syncp); 5869 ring->rx_stats.csum_err++; 5870 u64_stats_update_end(&ring->rx_syncp); 5871 } 5872 /* let the stack verify checksum errors */ 5873 return; 5874 } 5875 /* It must be a TCP or UDP packet with a valid checksum */ 5876 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 5877 E1000_RXD_STAT_UDPCS)) 5878 skb->ip_summed = CHECKSUM_UNNECESSARY; 5879 5880 dev_dbg(ring->dev, "cksum success: bits %08X\n", 5881 le32_to_cpu(rx_desc->wb.upper.status_error)); 5882} 5883 5884static inline void igb_rx_hash(struct igb_ring *ring, 5885 union e1000_adv_rx_desc *rx_desc, 5886 struct sk_buff *skb) 5887{ 5888 if (ring->netdev->features & NETIF_F_RXHASH) 5889 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); 5890} 5891 5892static void igb_rx_vlan(struct igb_ring *ring, 5893 union e1000_adv_rx_desc *rx_desc, 5894 struct sk_buff *skb) 5895{ 5896 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 5897 u16 vid; 5898 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 5899 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags)) 5900 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 5901 else 5902 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 5903 5904 __vlan_hwaccel_put_tag(skb, vid); 5905 } 5906} 5907 5908static inline u16 igb_get_hlen(union e1000_adv_rx_desc *rx_desc) 5909{ 5910 /* HW will not DMA in data larger than the given buffer, even if it 5911 * parses the (NFS, of course) header to be larger. In that case, it 5912 * fills the header buffer and spills the rest into the page. 5913 */ 5914 u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) & 5915 E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT; 5916 if (hlen > IGB_RX_HDR_LEN) 5917 hlen = IGB_RX_HDR_LEN; 5918 return hlen; 5919} 5920 5921static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, int budget) 5922{ 5923 struct igb_ring *rx_ring = q_vector->rx.ring; 5924 union e1000_adv_rx_desc *rx_desc; 5925 const int current_node = numa_node_id(); 5926 unsigned int total_bytes = 0, total_packets = 0; 5927 u16 cleaned_count = igb_desc_unused(rx_ring); 5928 u16 i = rx_ring->next_to_clean; 5929 5930 rx_desc = IGB_RX_DESC(rx_ring, i); 5931 5932 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) { 5933 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 5934 struct sk_buff *skb = buffer_info->skb; 5935 union e1000_adv_rx_desc *next_rxd; 5936 5937 buffer_info->skb = NULL; 5938 prefetch(skb->data); 5939 5940 i++; 5941 if (i == rx_ring->count) 5942 i = 0; 5943 5944 next_rxd = IGB_RX_DESC(rx_ring, i); 5945 prefetch(next_rxd); 5946 5947 /* 5948 * This memory barrier is needed to keep us from reading 5949 * any other fields out of the rx_desc until we know the 5950 * RXD_STAT_DD bit is set 5951 */ 5952 rmb(); 5953 5954 if (!skb_is_nonlinear(skb)) { 5955 __skb_put(skb, igb_get_hlen(rx_desc)); 5956 dma_unmap_single(rx_ring->dev, buffer_info->dma, 5957 IGB_RX_HDR_LEN, 5958 DMA_FROM_DEVICE); 5959 buffer_info->dma = 0; 5960 } 5961 5962 if (rx_desc->wb.upper.length) { 5963 u16 length = le16_to_cpu(rx_desc->wb.upper.length); 5964 5965 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, 5966 buffer_info->page, 5967 buffer_info->page_offset, 5968 length); 5969 5970 skb->len += length; 5971 skb->data_len += length; 5972 skb->truesize += PAGE_SIZE / 2; 5973 5974 if ((page_count(buffer_info->page) != 1) || 5975 (page_to_nid(buffer_info->page) != current_node)) 5976 buffer_info->page = NULL; 5977 else 5978 get_page(buffer_info->page); 5979 5980 dma_unmap_page(rx_ring->dev, buffer_info->page_dma, 5981 PAGE_SIZE / 2, DMA_FROM_DEVICE); 5982 buffer_info->page_dma = 0; 5983 } 5984 5985 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)) { 5986 struct igb_rx_buffer *next_buffer; 5987 next_buffer = &rx_ring->rx_buffer_info[i]; 5988 buffer_info->skb = next_buffer->skb; 5989 buffer_info->dma = next_buffer->dma; 5990 next_buffer->skb = skb; 5991 next_buffer->dma = 0; 5992 goto next_desc; 5993 } 5994 5995 if (unlikely((igb_test_staterr(rx_desc, 5996 E1000_RXDEXT_ERR_FRAME_ERR_MASK)) 5997 && !(rx_ring->netdev->features & NETIF_F_RXALL))) { 5998 dev_kfree_skb_any(skb); 5999 goto next_desc; 6000 } 6001 6002#ifdef CONFIG_IGB_PTP 6003 igb_ptp_rx_hwtstamp(q_vector, rx_desc, skb); 6004#endif /* CONFIG_IGB_PTP */ 6005 igb_rx_hash(rx_ring, rx_desc, skb); 6006 igb_rx_checksum(rx_ring, rx_desc, skb); 6007 igb_rx_vlan(rx_ring, rx_desc, skb); 6008 6009 total_bytes += skb->len; 6010 total_packets++; 6011 6012 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6013 6014 napi_gro_receive(&q_vector->napi, skb); 6015 6016 budget--; 6017next_desc: 6018 if (!budget) 6019 break; 6020 6021 cleaned_count++; 6022 /* return some buffers to hardware, one at a time is too slow */ 6023 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6024 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6025 cleaned_count = 0; 6026 } 6027 6028 /* use prefetched values */ 6029 rx_desc = next_rxd; 6030 } 6031 6032 rx_ring->next_to_clean = i; 6033 u64_stats_update_begin(&rx_ring->rx_syncp); 6034 rx_ring->rx_stats.packets += total_packets; 6035 rx_ring->rx_stats.bytes += total_bytes; 6036 u64_stats_update_end(&rx_ring->rx_syncp); 6037 q_vector->rx.total_packets += total_packets; 6038 q_vector->rx.total_bytes += total_bytes; 6039 6040 if (cleaned_count) 6041 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6042 6043 return !!budget; 6044} 6045 6046static bool igb_alloc_mapped_skb(struct igb_ring *rx_ring, 6047 struct igb_rx_buffer *bi) 6048{ 6049 struct sk_buff *skb = bi->skb; 6050 dma_addr_t dma = bi->dma; 6051 6052 if (dma) 6053 return true; 6054 6055 if (likely(!skb)) { 6056 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 6057 IGB_RX_HDR_LEN); 6058 bi->skb = skb; 6059 if (!skb) { 6060 rx_ring->rx_stats.alloc_failed++; 6061 return false; 6062 } 6063 6064 /* initialize skb for ring */ 6065 skb_record_rx_queue(skb, rx_ring->queue_index); 6066 } 6067 6068 dma = dma_map_single(rx_ring->dev, skb->data, 6069 IGB_RX_HDR_LEN, DMA_FROM_DEVICE); 6070 6071 if (dma_mapping_error(rx_ring->dev, dma)) { 6072 rx_ring->rx_stats.alloc_failed++; 6073 return false; 6074 } 6075 6076 bi->dma = dma; 6077 return true; 6078} 6079 6080static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 6081 struct igb_rx_buffer *bi) 6082{ 6083 struct page *page = bi->page; 6084 dma_addr_t page_dma = bi->page_dma; 6085 unsigned int page_offset = bi->page_offset ^ (PAGE_SIZE / 2); 6086 6087 if (page_dma) 6088 return true; 6089 6090 if (!page) { 6091 page = __skb_alloc_page(GFP_ATOMIC, bi->skb); 6092 bi->page = page; 6093 if (unlikely(!page)) { 6094 rx_ring->rx_stats.alloc_failed++; 6095 return false; 6096 } 6097 } 6098 6099 page_dma = dma_map_page(rx_ring->dev, page, 6100 page_offset, PAGE_SIZE / 2, 6101 DMA_FROM_DEVICE); 6102 6103 if (dma_mapping_error(rx_ring->dev, page_dma)) { 6104 rx_ring->rx_stats.alloc_failed++; 6105 return false; 6106 } 6107 6108 bi->page_dma = page_dma; 6109 bi->page_offset = page_offset; 6110 return true; 6111} 6112 6113/** 6114 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 6115 * @adapter: address of board private structure 6116 **/ 6117void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 6118{ 6119 union e1000_adv_rx_desc *rx_desc; 6120 struct igb_rx_buffer *bi; 6121 u16 i = rx_ring->next_to_use; 6122 6123 rx_desc = IGB_RX_DESC(rx_ring, i); 6124 bi = &rx_ring->rx_buffer_info[i]; 6125 i -= rx_ring->count; 6126 6127 while (cleaned_count--) { 6128 if (!igb_alloc_mapped_skb(rx_ring, bi)) 6129 break; 6130 6131 /* Refresh the desc even if buffer_addrs didn't change 6132 * because each write-back erases this info. */ 6133 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma); 6134 6135 if (!igb_alloc_mapped_page(rx_ring, bi)) 6136 break; 6137 6138 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma); 6139 6140 rx_desc++; 6141 bi++; 6142 i++; 6143 if (unlikely(!i)) { 6144 rx_desc = IGB_RX_DESC(rx_ring, 0); 6145 bi = rx_ring->rx_buffer_info; 6146 i -= rx_ring->count; 6147 } 6148 6149 /* clear the hdr_addr for the next_to_use descriptor */ 6150 rx_desc->read.hdr_addr = 0; 6151 } 6152 6153 i += rx_ring->count; 6154 6155 if (rx_ring->next_to_use != i) { 6156 rx_ring->next_to_use = i; 6157 6158 /* Force memory writes to complete before letting h/w 6159 * know there are new descriptors to fetch. (Only 6160 * applicable for weak-ordered memory model archs, 6161 * such as IA-64). */ 6162 wmb(); 6163 writel(i, rx_ring->tail); 6164 } 6165} 6166 6167/** 6168 * igb_mii_ioctl - 6169 * @netdev: 6170 * @ifreq: 6171 * @cmd: 6172 **/ 6173static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6174{ 6175 struct igb_adapter *adapter = netdev_priv(netdev); 6176 struct mii_ioctl_data *data = if_mii(ifr); 6177 6178 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6179 return -EOPNOTSUPP; 6180 6181 switch (cmd) { 6182 case SIOCGMIIPHY: 6183 data->phy_id = adapter->hw.phy.addr; 6184 break; 6185 case SIOCGMIIREG: 6186 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 6187 &data->val_out)) 6188 return -EIO; 6189 break; 6190 case SIOCSMIIREG: 6191 default: 6192 return -EOPNOTSUPP; 6193 } 6194 return 0; 6195} 6196 6197/** 6198 * igb_ioctl - 6199 * @netdev: 6200 * @ifreq: 6201 * @cmd: 6202 **/ 6203static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6204{ 6205 switch (cmd) { 6206 case SIOCGMIIPHY: 6207 case SIOCGMIIREG: 6208 case SIOCSMIIREG: 6209 return igb_mii_ioctl(netdev, ifr, cmd); 6210#ifdef CONFIG_IGB_PTP 6211 case SIOCSHWTSTAMP: 6212 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd); 6213#endif /* CONFIG_IGB_PTP */ 6214 default: 6215 return -EOPNOTSUPP; 6216 } 6217} 6218 6219s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 6220{ 6221 struct igb_adapter *adapter = hw->back; 6222 u16 cap_offset; 6223 6224 cap_offset = adapter->pdev->pcie_cap; 6225 if (!cap_offset) 6226 return -E1000_ERR_CONFIG; 6227 6228 pci_read_config_word(adapter->pdev, cap_offset + reg, value); 6229 6230 return 0; 6231} 6232 6233s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 6234{ 6235 struct igb_adapter *adapter = hw->back; 6236 u16 cap_offset; 6237 6238 cap_offset = adapter->pdev->pcie_cap; 6239 if (!cap_offset) 6240 return -E1000_ERR_CONFIG; 6241 6242 pci_write_config_word(adapter->pdev, cap_offset + reg, *value); 6243 6244 return 0; 6245} 6246 6247static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 6248{ 6249 struct igb_adapter *adapter = netdev_priv(netdev); 6250 struct e1000_hw *hw = &adapter->hw; 6251 u32 ctrl, rctl; 6252 bool enable = !!(features & NETIF_F_HW_VLAN_RX); 6253 6254 if (enable) { 6255 /* enable VLAN tag insert/strip */ 6256 ctrl = rd32(E1000_CTRL); 6257 ctrl |= E1000_CTRL_VME; 6258 wr32(E1000_CTRL, ctrl); 6259 6260 /* Disable CFI check */ 6261 rctl = rd32(E1000_RCTL); 6262 rctl &= ~E1000_RCTL_CFIEN; 6263 wr32(E1000_RCTL, rctl); 6264 } else { 6265 /* disable VLAN tag insert/strip */ 6266 ctrl = rd32(E1000_CTRL); 6267 ctrl &= ~E1000_CTRL_VME; 6268 wr32(E1000_CTRL, ctrl); 6269 } 6270 6271 igb_rlpml_set(adapter); 6272} 6273 6274static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) 6275{ 6276 struct igb_adapter *adapter = netdev_priv(netdev); 6277 struct e1000_hw *hw = &adapter->hw; 6278 int pf_id = adapter->vfs_allocated_count; 6279 6280 /* attempt to add filter to vlvf array */ 6281 igb_vlvf_set(adapter, vid, true, pf_id); 6282 6283 /* add the filter since PF can receive vlans w/o entry in vlvf */ 6284 igb_vfta_set(hw, vid, true); 6285 6286 set_bit(vid, adapter->active_vlans); 6287 6288 return 0; 6289} 6290 6291static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) 6292{ 6293 struct igb_adapter *adapter = netdev_priv(netdev); 6294 struct e1000_hw *hw = &adapter->hw; 6295 int pf_id = adapter->vfs_allocated_count; 6296 s32 err; 6297 6298 /* remove vlan from VLVF table array */ 6299 err = igb_vlvf_set(adapter, vid, false, pf_id); 6300 6301 /* if vid was not present in VLVF just remove it from table */ 6302 if (err) 6303 igb_vfta_set(hw, vid, false); 6304 6305 clear_bit(vid, adapter->active_vlans); 6306 6307 return 0; 6308} 6309 6310static void igb_restore_vlan(struct igb_adapter *adapter) 6311{ 6312 u16 vid; 6313 6314 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 6315 6316 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 6317 igb_vlan_rx_add_vid(adapter->netdev, vid); 6318} 6319 6320int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 6321{ 6322 struct pci_dev *pdev = adapter->pdev; 6323 struct e1000_mac_info *mac = &adapter->hw.mac; 6324 6325 mac->autoneg = 0; 6326 6327 /* Make sure dplx is at most 1 bit and lsb of speed is not set 6328 * for the switch() below to work */ 6329 if ((spd & 1) || (dplx & ~1)) 6330 goto err_inval; 6331 6332 /* Fiber NIC's only allow 1000 Gbps Full duplex */ 6333 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) && 6334 spd != SPEED_1000 && 6335 dplx != DUPLEX_FULL) 6336 goto err_inval; 6337 6338 switch (spd + dplx) { 6339 case SPEED_10 + DUPLEX_HALF: 6340 mac->forced_speed_duplex = ADVERTISE_10_HALF; 6341 break; 6342 case SPEED_10 + DUPLEX_FULL: 6343 mac->forced_speed_duplex = ADVERTISE_10_FULL; 6344 break; 6345 case SPEED_100 + DUPLEX_HALF: 6346 mac->forced_speed_duplex = ADVERTISE_100_HALF; 6347 break; 6348 case SPEED_100 + DUPLEX_FULL: 6349 mac->forced_speed_duplex = ADVERTISE_100_FULL; 6350 break; 6351 case SPEED_1000 + DUPLEX_FULL: 6352 mac->autoneg = 1; 6353 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 6354 break; 6355 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 6356 default: 6357 goto err_inval; 6358 } 6359 6360 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 6361 adapter->hw.phy.mdix = AUTO_ALL_MODES; 6362 6363 return 0; 6364 6365err_inval: 6366 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 6367 return -EINVAL; 6368} 6369 6370static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 6371 bool runtime) 6372{ 6373 struct net_device *netdev = pci_get_drvdata(pdev); 6374 struct igb_adapter *adapter = netdev_priv(netdev); 6375 struct e1000_hw *hw = &adapter->hw; 6376 u32 ctrl, rctl, status; 6377 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 6378#ifdef CONFIG_PM 6379 int retval = 0; 6380#endif 6381 6382 netif_device_detach(netdev); 6383 6384 if (netif_running(netdev)) 6385 __igb_close(netdev, true); 6386 6387 igb_clear_interrupt_scheme(adapter); 6388 6389#ifdef CONFIG_PM 6390 retval = pci_save_state(pdev); 6391 if (retval) 6392 return retval; 6393#endif 6394 6395 status = rd32(E1000_STATUS); 6396 if (status & E1000_STATUS_LU) 6397 wufc &= ~E1000_WUFC_LNKC; 6398 6399 if (wufc) { 6400 igb_setup_rctl(adapter); 6401 igb_set_rx_mode(netdev); 6402 6403 /* turn on all-multi mode if wake on multicast is enabled */ 6404 if (wufc & E1000_WUFC_MC) { 6405 rctl = rd32(E1000_RCTL); 6406 rctl |= E1000_RCTL_MPE; 6407 wr32(E1000_RCTL, rctl); 6408 } 6409 6410 ctrl = rd32(E1000_CTRL); 6411 /* advertise wake from D3Cold */ 6412 #define E1000_CTRL_ADVD3WUC 0x00100000 6413 /* phy power management enable */ 6414 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 6415 ctrl |= E1000_CTRL_ADVD3WUC; 6416 wr32(E1000_CTRL, ctrl); 6417 6418 /* Allow time for pending master requests to run */ 6419 igb_disable_pcie_master(hw); 6420 6421 wr32(E1000_WUC, E1000_WUC_PME_EN); 6422 wr32(E1000_WUFC, wufc); 6423 } else { 6424 wr32(E1000_WUC, 0); 6425 wr32(E1000_WUFC, 0); 6426 } 6427 6428 *enable_wake = wufc || adapter->en_mng_pt; 6429 if (!*enable_wake) 6430 igb_power_down_link(adapter); 6431 else 6432 igb_power_up_link(adapter); 6433 6434 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6435 * would have already happened in close and is redundant. */ 6436 igb_release_hw_control(adapter); 6437 6438 pci_disable_device(pdev); 6439 6440 return 0; 6441} 6442 6443#ifdef CONFIG_PM 6444#ifdef CONFIG_PM_SLEEP 6445static int igb_suspend(struct device *dev) 6446{ 6447 int retval; 6448 bool wake; 6449 struct pci_dev *pdev = to_pci_dev(dev); 6450 6451 retval = __igb_shutdown(pdev, &wake, 0); 6452 if (retval) 6453 return retval; 6454 6455 if (wake) { 6456 pci_prepare_to_sleep(pdev); 6457 } else { 6458 pci_wake_from_d3(pdev, false); 6459 pci_set_power_state(pdev, PCI_D3hot); 6460 } 6461 6462 return 0; 6463} 6464#endif /* CONFIG_PM_SLEEP */ 6465 6466static int igb_resume(struct device *dev) 6467{ 6468 struct pci_dev *pdev = to_pci_dev(dev); 6469 struct net_device *netdev = pci_get_drvdata(pdev); 6470 struct igb_adapter *adapter = netdev_priv(netdev); 6471 struct e1000_hw *hw = &adapter->hw; 6472 u32 err; 6473 6474 pci_set_power_state(pdev, PCI_D0); 6475 pci_restore_state(pdev); 6476 pci_save_state(pdev); 6477 6478 err = pci_enable_device_mem(pdev); 6479 if (err) { 6480 dev_err(&pdev->dev, 6481 "igb: Cannot enable PCI device from suspend\n"); 6482 return err; 6483 } 6484 pci_set_master(pdev); 6485 6486 pci_enable_wake(pdev, PCI_D3hot, 0); 6487 pci_enable_wake(pdev, PCI_D3cold, 0); 6488 6489 if (igb_init_interrupt_scheme(adapter)) { 6490 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 6491 return -ENOMEM; 6492 } 6493 6494 igb_reset(adapter); 6495 6496 /* let the f/w know that the h/w is now under the control of the 6497 * driver. */ 6498 igb_get_hw_control(adapter); 6499 6500 wr32(E1000_WUS, ~0); 6501 6502 if (netdev->flags & IFF_UP) { 6503 err = __igb_open(netdev, true); 6504 if (err) 6505 return err; 6506 } 6507 6508 netif_device_attach(netdev); 6509 return 0; 6510} 6511 6512#ifdef CONFIG_PM_RUNTIME 6513static int igb_runtime_idle(struct device *dev) 6514{ 6515 struct pci_dev *pdev = to_pci_dev(dev); 6516 struct net_device *netdev = pci_get_drvdata(pdev); 6517 struct igb_adapter *adapter = netdev_priv(netdev); 6518 6519 if (!igb_has_link(adapter)) 6520 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 6521 6522 return -EBUSY; 6523} 6524 6525static int igb_runtime_suspend(struct device *dev) 6526{ 6527 struct pci_dev *pdev = to_pci_dev(dev); 6528 int retval; 6529 bool wake; 6530 6531 retval = __igb_shutdown(pdev, &wake, 1); 6532 if (retval) 6533 return retval; 6534 6535 if (wake) { 6536 pci_prepare_to_sleep(pdev); 6537 } else { 6538 pci_wake_from_d3(pdev, false); 6539 pci_set_power_state(pdev, PCI_D3hot); 6540 } 6541 6542 return 0; 6543} 6544 6545static int igb_runtime_resume(struct device *dev) 6546{ 6547 return igb_resume(dev); 6548} 6549#endif /* CONFIG_PM_RUNTIME */ 6550#endif 6551 6552static void igb_shutdown(struct pci_dev *pdev) 6553{ 6554 bool wake; 6555 6556 __igb_shutdown(pdev, &wake, 0); 6557 6558 if (system_state == SYSTEM_POWER_OFF) { 6559 pci_wake_from_d3(pdev, wake); 6560 pci_set_power_state(pdev, PCI_D3hot); 6561 } 6562} 6563 6564#ifdef CONFIG_NET_POLL_CONTROLLER 6565/* 6566 * Polling 'interrupt' - used by things like netconsole to send skbs 6567 * without having to re-enable interrupts. It's not called while 6568 * the interrupt routine is executing. 6569 */ 6570static void igb_netpoll(struct net_device *netdev) 6571{ 6572 struct igb_adapter *adapter = netdev_priv(netdev); 6573 struct e1000_hw *hw = &adapter->hw; 6574 struct igb_q_vector *q_vector; 6575 int i; 6576 6577 for (i = 0; i < adapter->num_q_vectors; i++) { 6578 q_vector = adapter->q_vector[i]; 6579 if (adapter->msix_entries) 6580 wr32(E1000_EIMC, q_vector->eims_value); 6581 else 6582 igb_irq_disable(adapter); 6583 napi_schedule(&q_vector->napi); 6584 } 6585} 6586#endif /* CONFIG_NET_POLL_CONTROLLER */ 6587 6588/** 6589 * igb_io_error_detected - called when PCI error is detected 6590 * @pdev: Pointer to PCI device 6591 * @state: The current pci connection state 6592 * 6593 * This function is called after a PCI bus error affecting 6594 * this device has been detected. 6595 */ 6596static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 6597 pci_channel_state_t state) 6598{ 6599 struct net_device *netdev = pci_get_drvdata(pdev); 6600 struct igb_adapter *adapter = netdev_priv(netdev); 6601 6602 netif_device_detach(netdev); 6603 6604 if (state == pci_channel_io_perm_failure) 6605 return PCI_ERS_RESULT_DISCONNECT; 6606 6607 if (netif_running(netdev)) 6608 igb_down(adapter); 6609 pci_disable_device(pdev); 6610 6611 /* Request a slot slot reset. */ 6612 return PCI_ERS_RESULT_NEED_RESET; 6613} 6614 6615/** 6616 * igb_io_slot_reset - called after the pci bus has been reset. 6617 * @pdev: Pointer to PCI device 6618 * 6619 * Restart the card from scratch, as if from a cold-boot. Implementation 6620 * resembles the first-half of the igb_resume routine. 6621 */ 6622static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 6623{ 6624 struct net_device *netdev = pci_get_drvdata(pdev); 6625 struct igb_adapter *adapter = netdev_priv(netdev); 6626 struct e1000_hw *hw = &adapter->hw; 6627 pci_ers_result_t result; 6628 int err; 6629 6630 if (pci_enable_device_mem(pdev)) { 6631 dev_err(&pdev->dev, 6632 "Cannot re-enable PCI device after reset.\n"); 6633 result = PCI_ERS_RESULT_DISCONNECT; 6634 } else { 6635 pci_set_master(pdev); 6636 pci_restore_state(pdev); 6637 pci_save_state(pdev); 6638 6639 pci_enable_wake(pdev, PCI_D3hot, 0); 6640 pci_enable_wake(pdev, PCI_D3cold, 0); 6641 6642 igb_reset(adapter); 6643 wr32(E1000_WUS, ~0); 6644 result = PCI_ERS_RESULT_RECOVERED; 6645 } 6646 6647 err = pci_cleanup_aer_uncorrect_error_status(pdev); 6648 if (err) { 6649 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status " 6650 "failed 0x%0x\n", err); 6651 /* non-fatal, continue */ 6652 } 6653 6654 return result; 6655} 6656 6657/** 6658 * igb_io_resume - called when traffic can start flowing again. 6659 * @pdev: Pointer to PCI device 6660 * 6661 * This callback is called when the error recovery driver tells us that 6662 * its OK to resume normal operation. Implementation resembles the 6663 * second-half of the igb_resume routine. 6664 */ 6665static void igb_io_resume(struct pci_dev *pdev) 6666{ 6667 struct net_device *netdev = pci_get_drvdata(pdev); 6668 struct igb_adapter *adapter = netdev_priv(netdev); 6669 6670 if (netif_running(netdev)) { 6671 if (igb_up(adapter)) { 6672 dev_err(&pdev->dev, "igb_up failed after reset\n"); 6673 return; 6674 } 6675 } 6676 6677 netif_device_attach(netdev); 6678 6679 /* let the f/w know that the h/w is now under the control of the 6680 * driver. */ 6681 igb_get_hw_control(adapter); 6682} 6683 6684static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 6685 u8 qsel) 6686{ 6687 u32 rar_low, rar_high; 6688 struct e1000_hw *hw = &adapter->hw; 6689 6690 /* HW expects these in little endian so we reverse the byte order 6691 * from network order (big endian) to little endian 6692 */ 6693 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 6694 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 6695 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 6696 6697 /* Indicate to hardware the Address is Valid. */ 6698 rar_high |= E1000_RAH_AV; 6699 6700 if (hw->mac.type == e1000_82575) 6701 rar_high |= E1000_RAH_POOL_1 * qsel; 6702 else 6703 rar_high |= E1000_RAH_POOL_1 << qsel; 6704 6705 wr32(E1000_RAL(index), rar_low); 6706 wrfl(); 6707 wr32(E1000_RAH(index), rar_high); 6708 wrfl(); 6709} 6710 6711static int igb_set_vf_mac(struct igb_adapter *adapter, 6712 int vf, unsigned char *mac_addr) 6713{ 6714 struct e1000_hw *hw = &adapter->hw; 6715 /* VF MAC addresses start at end of receive addresses and moves 6716 * torwards the first, as a result a collision should not be possible */ 6717 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 6718 6719 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 6720 6721 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 6722 6723 return 0; 6724} 6725 6726static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 6727{ 6728 struct igb_adapter *adapter = netdev_priv(netdev); 6729 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 6730 return -EINVAL; 6731 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 6732 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 6733 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this" 6734 " change effective."); 6735 if (test_bit(__IGB_DOWN, &adapter->state)) { 6736 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set," 6737 " but the PF device is not up.\n"); 6738 dev_warn(&adapter->pdev->dev, "Bring the PF device up before" 6739 " attempting to use the VF device.\n"); 6740 } 6741 return igb_set_vf_mac(adapter, vf, mac); 6742} 6743 6744static int igb_link_mbps(int internal_link_speed) 6745{ 6746 switch (internal_link_speed) { 6747 case SPEED_100: 6748 return 100; 6749 case SPEED_1000: 6750 return 1000; 6751 default: 6752 return 0; 6753 } 6754} 6755 6756static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 6757 int link_speed) 6758{ 6759 int rf_dec, rf_int; 6760 u32 bcnrc_val; 6761 6762 if (tx_rate != 0) { 6763 /* Calculate the rate factor values to set */ 6764 rf_int = link_speed / tx_rate; 6765 rf_dec = (link_speed - (rf_int * tx_rate)); 6766 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate; 6767 6768 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 6769 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) & 6770 E1000_RTTBCNRC_RF_INT_MASK); 6771 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 6772 } else { 6773 bcnrc_val = 0; 6774 } 6775 6776 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 6777 /* 6778 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 6779 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 6780 */ 6781 wr32(E1000_RTTBCNRM, 0x14); 6782 wr32(E1000_RTTBCNRC, bcnrc_val); 6783} 6784 6785static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 6786{ 6787 int actual_link_speed, i; 6788 bool reset_rate = false; 6789 6790 /* VF TX rate limit was not set or not supported */ 6791 if ((adapter->vf_rate_link_speed == 0) || 6792 (adapter->hw.mac.type != e1000_82576)) 6793 return; 6794 6795 actual_link_speed = igb_link_mbps(adapter->link_speed); 6796 if (actual_link_speed != adapter->vf_rate_link_speed) { 6797 reset_rate = true; 6798 adapter->vf_rate_link_speed = 0; 6799 dev_info(&adapter->pdev->dev, 6800 "Link speed has been changed. VF Transmit " 6801 "rate is disabled\n"); 6802 } 6803 6804 for (i = 0; i < adapter->vfs_allocated_count; i++) { 6805 if (reset_rate) 6806 adapter->vf_data[i].tx_rate = 0; 6807 6808 igb_set_vf_rate_limit(&adapter->hw, i, 6809 adapter->vf_data[i].tx_rate, 6810 actual_link_speed); 6811 } 6812} 6813 6814static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) 6815{ 6816 struct igb_adapter *adapter = netdev_priv(netdev); 6817 struct e1000_hw *hw = &adapter->hw; 6818 int actual_link_speed; 6819 6820 if (hw->mac.type != e1000_82576) 6821 return -EOPNOTSUPP; 6822 6823 actual_link_speed = igb_link_mbps(adapter->link_speed); 6824 if ((vf >= adapter->vfs_allocated_count) || 6825 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 6826 (tx_rate < 0) || (tx_rate > actual_link_speed)) 6827 return -EINVAL; 6828 6829 adapter->vf_rate_link_speed = actual_link_speed; 6830 adapter->vf_data[vf].tx_rate = (u16)tx_rate; 6831 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); 6832 6833 return 0; 6834} 6835 6836static int igb_ndo_get_vf_config(struct net_device *netdev, 6837 int vf, struct ifla_vf_info *ivi) 6838{ 6839 struct igb_adapter *adapter = netdev_priv(netdev); 6840 if (vf >= adapter->vfs_allocated_count) 6841 return -EINVAL; 6842 ivi->vf = vf; 6843 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 6844 ivi->tx_rate = adapter->vf_data[vf].tx_rate; 6845 ivi->vlan = adapter->vf_data[vf].pf_vlan; 6846 ivi->qos = adapter->vf_data[vf].pf_qos; 6847 return 0; 6848} 6849 6850static void igb_vmm_control(struct igb_adapter *adapter) 6851{ 6852 struct e1000_hw *hw = &adapter->hw; 6853 u32 reg; 6854 6855 switch (hw->mac.type) { 6856 case e1000_82575: 6857 case e1000_i210: 6858 case e1000_i211: 6859 default: 6860 /* replication is not supported for 82575 */ 6861 return; 6862 case e1000_82576: 6863 /* notify HW that the MAC is adding vlan tags */ 6864 reg = rd32(E1000_DTXCTL); 6865 reg |= E1000_DTXCTL_VLAN_ADDED; 6866 wr32(E1000_DTXCTL, reg); 6867 case e1000_82580: 6868 /* enable replication vlan tag stripping */ 6869 reg = rd32(E1000_RPLOLR); 6870 reg |= E1000_RPLOLR_STRVLAN; 6871 wr32(E1000_RPLOLR, reg); 6872 case e1000_i350: 6873 /* none of the above registers are supported by i350 */ 6874 break; 6875 } 6876 6877 if (adapter->vfs_allocated_count) { 6878 igb_vmdq_set_loopback_pf(hw, true); 6879 igb_vmdq_set_replication_pf(hw, true); 6880 igb_vmdq_set_anti_spoofing_pf(hw, true, 6881 adapter->vfs_allocated_count); 6882 } else { 6883 igb_vmdq_set_loopback_pf(hw, false); 6884 igb_vmdq_set_replication_pf(hw, false); 6885 } 6886} 6887 6888static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 6889{ 6890 struct e1000_hw *hw = &adapter->hw; 6891 u32 dmac_thr; 6892 u16 hwm; 6893 6894 if (hw->mac.type > e1000_82580) { 6895 if (adapter->flags & IGB_FLAG_DMAC) { 6896 u32 reg; 6897 6898 /* force threshold to 0. */ 6899 wr32(E1000_DMCTXTH, 0); 6900 6901 /* 6902 * DMA Coalescing high water mark needs to be greater 6903 * than the Rx threshold. Set hwm to PBA - max frame 6904 * size in 16B units, capping it at PBA - 6KB. 6905 */ 6906 hwm = 64 * pba - adapter->max_frame_size / 16; 6907 if (hwm < 64 * (pba - 6)) 6908 hwm = 64 * (pba - 6); 6909 reg = rd32(E1000_FCRTC); 6910 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 6911 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 6912 & E1000_FCRTC_RTH_COAL_MASK); 6913 wr32(E1000_FCRTC, reg); 6914 6915 /* 6916 * Set the DMA Coalescing Rx threshold to PBA - 2 * max 6917 * frame size, capping it at PBA - 10KB. 6918 */ 6919 dmac_thr = pba - adapter->max_frame_size / 512; 6920 if (dmac_thr < pba - 10) 6921 dmac_thr = pba - 10; 6922 reg = rd32(E1000_DMACR); 6923 reg &= ~E1000_DMACR_DMACTHR_MASK; 6924 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 6925 & E1000_DMACR_DMACTHR_MASK); 6926 6927 /* transition to L0x or L1 if available..*/ 6928 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 6929 6930 /* watchdog timer= +-1000 usec in 32usec intervals */ 6931 reg |= (1000 >> 5); 6932 6933 /* Disable BMC-to-OS Watchdog Enable */ 6934 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 6935 wr32(E1000_DMACR, reg); 6936 6937 /* 6938 * no lower threshold to disable 6939 * coalescing(smart fifb)-UTRESH=0 6940 */ 6941 wr32(E1000_DMCRTRH, 0); 6942 6943 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 6944 6945 wr32(E1000_DMCTLX, reg); 6946 6947 /* 6948 * free space in tx packet buffer to wake from 6949 * DMA coal 6950 */ 6951 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 6952 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 6953 6954 /* 6955 * make low power state decision controlled 6956 * by DMA coal 6957 */ 6958 reg = rd32(E1000_PCIEMISC); 6959 reg &= ~E1000_PCIEMISC_LX_DECISION; 6960 wr32(E1000_PCIEMISC, reg); 6961 } /* endif adapter->dmac is not disabled */ 6962 } else if (hw->mac.type == e1000_82580) { 6963 u32 reg = rd32(E1000_PCIEMISC); 6964 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 6965 wr32(E1000_DMACR, 0); 6966 } 6967} 6968 6969/* igb_main.c */ 6970