igb_main.c revision cbc8e55f6fdae27b667051b36040f66768ef79f2
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2012 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 29 30#include <linux/module.h> 31#include <linux/types.h> 32#include <linux/init.h> 33#include <linux/bitops.h> 34#include <linux/vmalloc.h> 35#include <linux/pagemap.h> 36#include <linux/netdevice.h> 37#include <linux/ipv6.h> 38#include <linux/slab.h> 39#include <net/checksum.h> 40#include <net/ip6_checksum.h> 41#include <linux/net_tstamp.h> 42#include <linux/mii.h> 43#include <linux/ethtool.h> 44#include <linux/if.h> 45#include <linux/if_vlan.h> 46#include <linux/pci.h> 47#include <linux/pci-aspm.h> 48#include <linux/delay.h> 49#include <linux/interrupt.h> 50#include <linux/ip.h> 51#include <linux/tcp.h> 52#include <linux/sctp.h> 53#include <linux/if_ether.h> 54#include <linux/aer.h> 55#include <linux/prefetch.h> 56#include <linux/pm_runtime.h> 57#ifdef CONFIG_IGB_DCA 58#include <linux/dca.h> 59#endif 60#include "igb.h" 61 62#define MAJ 4 63#define MIN 0 64#define BUILD 1 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 66__stringify(BUILD) "-k" 67char igb_driver_name[] = "igb"; 68char igb_driver_version[] = DRV_VERSION; 69static const char igb_driver_string[] = 70 "Intel(R) Gigabit Ethernet Network Driver"; 71static const char igb_copyright[] = "Copyright (c) 2007-2012 Intel Corporation."; 72 73static const struct e1000_info *igb_info_tbl[] = { 74 [board_82575] = &e1000_82575_info, 75}; 76 77static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 108 /* required last entry */ 109 {0, } 110}; 111 112MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 113 114void igb_reset(struct igb_adapter *); 115static int igb_setup_all_tx_resources(struct igb_adapter *); 116static int igb_setup_all_rx_resources(struct igb_adapter *); 117static void igb_free_all_tx_resources(struct igb_adapter *); 118static void igb_free_all_rx_resources(struct igb_adapter *); 119static void igb_setup_mrqc(struct igb_adapter *); 120static int igb_probe(struct pci_dev *, const struct pci_device_id *); 121static void __devexit igb_remove(struct pci_dev *pdev); 122static int igb_sw_init(struct igb_adapter *); 123static int igb_open(struct net_device *); 124static int igb_close(struct net_device *); 125static void igb_configure_tx(struct igb_adapter *); 126static void igb_configure_rx(struct igb_adapter *); 127static void igb_clean_all_tx_rings(struct igb_adapter *); 128static void igb_clean_all_rx_rings(struct igb_adapter *); 129static void igb_clean_tx_ring(struct igb_ring *); 130static void igb_clean_rx_ring(struct igb_ring *); 131static void igb_set_rx_mode(struct net_device *); 132static void igb_update_phy_info(unsigned long); 133static void igb_watchdog(unsigned long); 134static void igb_watchdog_task(struct work_struct *); 135static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 136static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 137 struct rtnl_link_stats64 *stats); 138static int igb_change_mtu(struct net_device *, int); 139static int igb_set_mac(struct net_device *, void *); 140static void igb_set_uta(struct igb_adapter *adapter); 141static irqreturn_t igb_intr(int irq, void *); 142static irqreturn_t igb_intr_msi(int irq, void *); 143static irqreturn_t igb_msix_other(int irq, void *); 144static irqreturn_t igb_msix_ring(int irq, void *); 145#ifdef CONFIG_IGB_DCA 146static void igb_update_dca(struct igb_q_vector *); 147static void igb_setup_dca(struct igb_adapter *); 148#endif /* CONFIG_IGB_DCA */ 149static int igb_poll(struct napi_struct *, int); 150static bool igb_clean_tx_irq(struct igb_q_vector *); 151static bool igb_clean_rx_irq(struct igb_q_vector *, int); 152static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 153static void igb_tx_timeout(struct net_device *); 154static void igb_reset_task(struct work_struct *); 155static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); 156static int igb_vlan_rx_add_vid(struct net_device *, u16); 157static int igb_vlan_rx_kill_vid(struct net_device *, u16); 158static void igb_restore_vlan(struct igb_adapter *); 159static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 160static void igb_ping_all_vfs(struct igb_adapter *); 161static void igb_msg_task(struct igb_adapter *); 162static void igb_vmm_control(struct igb_adapter *); 163static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 164static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 165static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 166static int igb_ndo_set_vf_vlan(struct net_device *netdev, 167 int vf, u16 vlan, u8 qos); 168static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 169static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 170 struct ifla_vf_info *ivi); 171static void igb_check_vf_rate_limit(struct igb_adapter *); 172 173#ifdef CONFIG_PCI_IOV 174static int igb_vf_configure(struct igb_adapter *adapter, int vf); 175static bool igb_vfs_are_assigned(struct igb_adapter *adapter); 176#endif 177 178#ifdef CONFIG_PM 179#ifdef CONFIG_PM_SLEEP 180static int igb_suspend(struct device *); 181#endif 182static int igb_resume(struct device *); 183#ifdef CONFIG_PM_RUNTIME 184static int igb_runtime_suspend(struct device *dev); 185static int igb_runtime_resume(struct device *dev); 186static int igb_runtime_idle(struct device *dev); 187#endif 188static const struct dev_pm_ops igb_pm_ops = { 189 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 190 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 191 igb_runtime_idle) 192}; 193#endif 194static void igb_shutdown(struct pci_dev *); 195#ifdef CONFIG_IGB_DCA 196static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 197static struct notifier_block dca_notifier = { 198 .notifier_call = igb_notify_dca, 199 .next = NULL, 200 .priority = 0 201}; 202#endif 203#ifdef CONFIG_NET_POLL_CONTROLLER 204/* for netdump / net console */ 205static void igb_netpoll(struct net_device *); 206#endif 207#ifdef CONFIG_PCI_IOV 208static unsigned int max_vfs = 0; 209module_param(max_vfs, uint, 0); 210MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " 211 "per physical function"); 212#endif /* CONFIG_PCI_IOV */ 213 214static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 215 pci_channel_state_t); 216static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 217static void igb_io_resume(struct pci_dev *); 218 219static const struct pci_error_handlers igb_err_handler = { 220 .error_detected = igb_io_error_detected, 221 .slot_reset = igb_io_slot_reset, 222 .resume = igb_io_resume, 223}; 224 225static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 226 227static struct pci_driver igb_driver = { 228 .name = igb_driver_name, 229 .id_table = igb_pci_tbl, 230 .probe = igb_probe, 231 .remove = __devexit_p(igb_remove), 232#ifdef CONFIG_PM 233 .driver.pm = &igb_pm_ops, 234#endif 235 .shutdown = igb_shutdown, 236 .err_handler = &igb_err_handler 237}; 238 239MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 240MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 241MODULE_LICENSE("GPL"); 242MODULE_VERSION(DRV_VERSION); 243 244#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 245static int debug = -1; 246module_param(debug, int, 0); 247MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 248 249struct igb_reg_info { 250 u32 ofs; 251 char *name; 252}; 253 254static const struct igb_reg_info igb_reg_info_tbl[] = { 255 256 /* General Registers */ 257 {E1000_CTRL, "CTRL"}, 258 {E1000_STATUS, "STATUS"}, 259 {E1000_CTRL_EXT, "CTRL_EXT"}, 260 261 /* Interrupt Registers */ 262 {E1000_ICR, "ICR"}, 263 264 /* RX Registers */ 265 {E1000_RCTL, "RCTL"}, 266 {E1000_RDLEN(0), "RDLEN"}, 267 {E1000_RDH(0), "RDH"}, 268 {E1000_RDT(0), "RDT"}, 269 {E1000_RXDCTL(0), "RXDCTL"}, 270 {E1000_RDBAL(0), "RDBAL"}, 271 {E1000_RDBAH(0), "RDBAH"}, 272 273 /* TX Registers */ 274 {E1000_TCTL, "TCTL"}, 275 {E1000_TDBAL(0), "TDBAL"}, 276 {E1000_TDBAH(0), "TDBAH"}, 277 {E1000_TDLEN(0), "TDLEN"}, 278 {E1000_TDH(0), "TDH"}, 279 {E1000_TDT(0), "TDT"}, 280 {E1000_TXDCTL(0), "TXDCTL"}, 281 {E1000_TDFH, "TDFH"}, 282 {E1000_TDFT, "TDFT"}, 283 {E1000_TDFHS, "TDFHS"}, 284 {E1000_TDFPC, "TDFPC"}, 285 286 /* List Terminator */ 287 {} 288}; 289 290/* 291 * igb_regdump - register printout routine 292 */ 293static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 294{ 295 int n = 0; 296 char rname[16]; 297 u32 regs[8]; 298 299 switch (reginfo->ofs) { 300 case E1000_RDLEN(0): 301 for (n = 0; n < 4; n++) 302 regs[n] = rd32(E1000_RDLEN(n)); 303 break; 304 case E1000_RDH(0): 305 for (n = 0; n < 4; n++) 306 regs[n] = rd32(E1000_RDH(n)); 307 break; 308 case E1000_RDT(0): 309 for (n = 0; n < 4; n++) 310 regs[n] = rd32(E1000_RDT(n)); 311 break; 312 case E1000_RXDCTL(0): 313 for (n = 0; n < 4; n++) 314 regs[n] = rd32(E1000_RXDCTL(n)); 315 break; 316 case E1000_RDBAL(0): 317 for (n = 0; n < 4; n++) 318 regs[n] = rd32(E1000_RDBAL(n)); 319 break; 320 case E1000_RDBAH(0): 321 for (n = 0; n < 4; n++) 322 regs[n] = rd32(E1000_RDBAH(n)); 323 break; 324 case E1000_TDBAL(0): 325 for (n = 0; n < 4; n++) 326 regs[n] = rd32(E1000_RDBAL(n)); 327 break; 328 case E1000_TDBAH(0): 329 for (n = 0; n < 4; n++) 330 regs[n] = rd32(E1000_TDBAH(n)); 331 break; 332 case E1000_TDLEN(0): 333 for (n = 0; n < 4; n++) 334 regs[n] = rd32(E1000_TDLEN(n)); 335 break; 336 case E1000_TDH(0): 337 for (n = 0; n < 4; n++) 338 regs[n] = rd32(E1000_TDH(n)); 339 break; 340 case E1000_TDT(0): 341 for (n = 0; n < 4; n++) 342 regs[n] = rd32(E1000_TDT(n)); 343 break; 344 case E1000_TXDCTL(0): 345 for (n = 0; n < 4; n++) 346 regs[n] = rd32(E1000_TXDCTL(n)); 347 break; 348 default: 349 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 350 return; 351 } 352 353 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 354 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 355 regs[2], regs[3]); 356} 357 358/* 359 * igb_dump - Print registers, tx-rings and rx-rings 360 */ 361static void igb_dump(struct igb_adapter *adapter) 362{ 363 struct net_device *netdev = adapter->netdev; 364 struct e1000_hw *hw = &adapter->hw; 365 struct igb_reg_info *reginfo; 366 struct igb_ring *tx_ring; 367 union e1000_adv_tx_desc *tx_desc; 368 struct my_u0 { u64 a; u64 b; } *u0; 369 struct igb_ring *rx_ring; 370 union e1000_adv_rx_desc *rx_desc; 371 u32 staterr; 372 u16 i, n; 373 374 if (!netif_msg_hw(adapter)) 375 return; 376 377 /* Print netdevice Info */ 378 if (netdev) { 379 dev_info(&adapter->pdev->dev, "Net device Info\n"); 380 pr_info("Device Name state trans_start " 381 "last_rx\n"); 382 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 383 netdev->state, netdev->trans_start, netdev->last_rx); 384 } 385 386 /* Print Registers */ 387 dev_info(&adapter->pdev->dev, "Register Dump\n"); 388 pr_info(" Register Name Value\n"); 389 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 390 reginfo->name; reginfo++) { 391 igb_regdump(hw, reginfo); 392 } 393 394 /* Print TX Ring Summary */ 395 if (!netdev || !netif_running(netdev)) 396 goto exit; 397 398 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 399 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 400 for (n = 0; n < adapter->num_tx_queues; n++) { 401 struct igb_tx_buffer *buffer_info; 402 tx_ring = adapter->tx_ring[n]; 403 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 404 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 405 n, tx_ring->next_to_use, tx_ring->next_to_clean, 406 (u64)dma_unmap_addr(buffer_info, dma), 407 dma_unmap_len(buffer_info, len), 408 buffer_info->next_to_watch, 409 (u64)buffer_info->time_stamp); 410 } 411 412 /* Print TX Rings */ 413 if (!netif_msg_tx_done(adapter)) 414 goto rx_ring_summary; 415 416 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 417 418 /* Transmit Descriptor Formats 419 * 420 * Advanced Transmit Descriptor 421 * +--------------------------------------------------------------+ 422 * 0 | Buffer Address [63:0] | 423 * +--------------------------------------------------------------+ 424 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 425 * +--------------------------------------------------------------+ 426 * 63 46 45 40 39 38 36 35 32 31 24 15 0 427 */ 428 429 for (n = 0; n < adapter->num_tx_queues; n++) { 430 tx_ring = adapter->tx_ring[n]; 431 pr_info("------------------------------------\n"); 432 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 433 pr_info("------------------------------------\n"); 434 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] " 435 "[bi->dma ] leng ntw timestamp " 436 "bi->skb\n"); 437 438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 439 const char *next_desc; 440 struct igb_tx_buffer *buffer_info; 441 tx_desc = IGB_TX_DESC(tx_ring, i); 442 buffer_info = &tx_ring->tx_buffer_info[i]; 443 u0 = (struct my_u0 *)tx_desc; 444 if (i == tx_ring->next_to_use && 445 i == tx_ring->next_to_clean) 446 next_desc = " NTC/U"; 447 else if (i == tx_ring->next_to_use) 448 next_desc = " NTU"; 449 else if (i == tx_ring->next_to_clean) 450 next_desc = " NTC"; 451 else 452 next_desc = ""; 453 454 pr_info("T [0x%03X] %016llX %016llX %016llX" 455 " %04X %p %016llX %p%s\n", i, 456 le64_to_cpu(u0->a), 457 le64_to_cpu(u0->b), 458 (u64)dma_unmap_addr(buffer_info, dma), 459 dma_unmap_len(buffer_info, len), 460 buffer_info->next_to_watch, 461 (u64)buffer_info->time_stamp, 462 buffer_info->skb, next_desc); 463 464 if (netif_msg_pktdata(adapter) && buffer_info->skb) 465 print_hex_dump(KERN_INFO, "", 466 DUMP_PREFIX_ADDRESS, 467 16, 1, buffer_info->skb->data, 468 dma_unmap_len(buffer_info, len), 469 true); 470 } 471 } 472 473 /* Print RX Rings Summary */ 474rx_ring_summary: 475 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 476 pr_info("Queue [NTU] [NTC]\n"); 477 for (n = 0; n < adapter->num_rx_queues; n++) { 478 rx_ring = adapter->rx_ring[n]; 479 pr_info(" %5d %5X %5X\n", 480 n, rx_ring->next_to_use, rx_ring->next_to_clean); 481 } 482 483 /* Print RX Rings */ 484 if (!netif_msg_rx_status(adapter)) 485 goto exit; 486 487 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 488 489 /* Advanced Receive Descriptor (Read) Format 490 * 63 1 0 491 * +-----------------------------------------------------+ 492 * 0 | Packet Buffer Address [63:1] |A0/NSE| 493 * +----------------------------------------------+------+ 494 * 8 | Header Buffer Address [63:1] | DD | 495 * +-----------------------------------------------------+ 496 * 497 * 498 * Advanced Receive Descriptor (Write-Back) Format 499 * 500 * 63 48 47 32 31 30 21 20 17 16 4 3 0 501 * +------------------------------------------------------+ 502 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 503 * | Checksum Ident | | | | Type | Type | 504 * +------------------------------------------------------+ 505 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 506 * +------------------------------------------------------+ 507 * 63 48 47 32 31 20 19 0 508 */ 509 510 for (n = 0; n < adapter->num_rx_queues; n++) { 511 rx_ring = adapter->rx_ring[n]; 512 pr_info("------------------------------------\n"); 513 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 514 pr_info("------------------------------------\n"); 515 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] " 516 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 517 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----" 518 "----------- [bi->skb] <-- Adv Rx Write-Back format\n"); 519 520 for (i = 0; i < rx_ring->count; i++) { 521 const char *next_desc; 522 struct igb_rx_buffer *buffer_info; 523 buffer_info = &rx_ring->rx_buffer_info[i]; 524 rx_desc = IGB_RX_DESC(rx_ring, i); 525 u0 = (struct my_u0 *)rx_desc; 526 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 527 528 if (i == rx_ring->next_to_use) 529 next_desc = " NTU"; 530 else if (i == rx_ring->next_to_clean) 531 next_desc = " NTC"; 532 else 533 next_desc = ""; 534 535 if (staterr & E1000_RXD_STAT_DD) { 536 /* Descriptor Done */ 537 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 538 "RWB", i, 539 le64_to_cpu(u0->a), 540 le64_to_cpu(u0->b), 541 next_desc); 542 } else { 543 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 544 "R ", i, 545 le64_to_cpu(u0->a), 546 le64_to_cpu(u0->b), 547 (u64)buffer_info->dma, 548 next_desc); 549 550 if (netif_msg_pktdata(adapter) && 551 buffer_info->dma && buffer_info->page) { 552 print_hex_dump(KERN_INFO, "", 553 DUMP_PREFIX_ADDRESS, 554 16, 1, 555 page_address(buffer_info->page) + 556 buffer_info->page_offset, 557 PAGE_SIZE/2, true); 558 } 559 } 560 } 561 } 562 563exit: 564 return; 565} 566 567/** 568 * igb_get_hw_dev - return device 569 * used by hardware layer to print debugging information 570 **/ 571struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 572{ 573 struct igb_adapter *adapter = hw->back; 574 return adapter->netdev; 575} 576 577/** 578 * igb_init_module - Driver Registration Routine 579 * 580 * igb_init_module is the first routine called when the driver is 581 * loaded. All it does is register with the PCI subsystem. 582 **/ 583static int __init igb_init_module(void) 584{ 585 int ret; 586 pr_info("%s - version %s\n", 587 igb_driver_string, igb_driver_version); 588 589 pr_info("%s\n", igb_copyright); 590 591#ifdef CONFIG_IGB_DCA 592 dca_register_notify(&dca_notifier); 593#endif 594 ret = pci_register_driver(&igb_driver); 595 return ret; 596} 597 598module_init(igb_init_module); 599 600/** 601 * igb_exit_module - Driver Exit Cleanup Routine 602 * 603 * igb_exit_module is called just before the driver is removed 604 * from memory. 605 **/ 606static void __exit igb_exit_module(void) 607{ 608#ifdef CONFIG_IGB_DCA 609 dca_unregister_notify(&dca_notifier); 610#endif 611 pci_unregister_driver(&igb_driver); 612} 613 614module_exit(igb_exit_module); 615 616#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 617/** 618 * igb_cache_ring_register - Descriptor ring to register mapping 619 * @adapter: board private structure to initialize 620 * 621 * Once we know the feature-set enabled for the device, we'll cache 622 * the register offset the descriptor ring is assigned to. 623 **/ 624static void igb_cache_ring_register(struct igb_adapter *adapter) 625{ 626 int i = 0, j = 0; 627 u32 rbase_offset = adapter->vfs_allocated_count; 628 629 switch (adapter->hw.mac.type) { 630 case e1000_82576: 631 /* The queues are allocated for virtualization such that VF 0 632 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 633 * In order to avoid collision we start at the first free queue 634 * and continue consuming queues in the same sequence 635 */ 636 if (adapter->vfs_allocated_count) { 637 for (; i < adapter->rss_queues; i++) 638 adapter->rx_ring[i]->reg_idx = rbase_offset + 639 Q_IDX_82576(i); 640 } 641 case e1000_82575: 642 case e1000_82580: 643 case e1000_i350: 644 case e1000_i210: 645 case e1000_i211: 646 default: 647 for (; i < adapter->num_rx_queues; i++) 648 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 649 for (; j < adapter->num_tx_queues; j++) 650 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 651 break; 652 } 653} 654 655static void igb_free_queues(struct igb_adapter *adapter) 656{ 657 int i; 658 659 for (i = 0; i < adapter->num_tx_queues; i++) { 660 kfree(adapter->tx_ring[i]); 661 adapter->tx_ring[i] = NULL; 662 } 663 for (i = 0; i < adapter->num_rx_queues; i++) { 664 kfree(adapter->rx_ring[i]); 665 adapter->rx_ring[i] = NULL; 666 } 667 adapter->num_rx_queues = 0; 668 adapter->num_tx_queues = 0; 669} 670 671/** 672 * igb_alloc_queues - Allocate memory for all rings 673 * @adapter: board private structure to initialize 674 * 675 * We allocate one ring per queue at run-time since we don't know the 676 * number of queues at compile-time. 677 **/ 678static int igb_alloc_queues(struct igb_adapter *adapter) 679{ 680 struct igb_ring *ring; 681 int i; 682 683 for (i = 0; i < adapter->num_tx_queues; i++) { 684 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL); 685 if (!ring) 686 goto err; 687 ring->count = adapter->tx_ring_count; 688 ring->queue_index = i; 689 ring->dev = &adapter->pdev->dev; 690 ring->netdev = adapter->netdev; 691 /* For 82575, context index must be unique per ring. */ 692 if (adapter->hw.mac.type == e1000_82575) 693 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 694 adapter->tx_ring[i] = ring; 695 } 696 697 for (i = 0; i < adapter->num_rx_queues; i++) { 698 ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL); 699 if (!ring) 700 goto err; 701 ring->count = adapter->rx_ring_count; 702 ring->queue_index = i; 703 ring->dev = &adapter->pdev->dev; 704 ring->netdev = adapter->netdev; 705 /* set flag indicating ring supports SCTP checksum offload */ 706 if (adapter->hw.mac.type >= e1000_82576) 707 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 708 709 /* 710 * On i350, i210, and i211, loopback VLAN packets 711 * have the tag byte-swapped. 712 * */ 713 if (adapter->hw.mac.type >= e1000_i350) 714 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 715 716 adapter->rx_ring[i] = ring; 717 } 718 719 igb_cache_ring_register(adapter); 720 721 return 0; 722 723err: 724 igb_free_queues(adapter); 725 726 return -ENOMEM; 727} 728 729/** 730 * igb_write_ivar - configure ivar for given MSI-X vector 731 * @hw: pointer to the HW structure 732 * @msix_vector: vector number we are allocating to a given ring 733 * @index: row index of IVAR register to write within IVAR table 734 * @offset: column offset of in IVAR, should be multiple of 8 735 * 736 * This function is intended to handle the writing of the IVAR register 737 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 738 * each containing an cause allocation for an Rx and Tx ring, and a 739 * variable number of rows depending on the number of queues supported. 740 **/ 741static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 742 int index, int offset) 743{ 744 u32 ivar = array_rd32(E1000_IVAR0, index); 745 746 /* clear any bits that are currently set */ 747 ivar &= ~((u32)0xFF << offset); 748 749 /* write vector and valid bit */ 750 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 751 752 array_wr32(E1000_IVAR0, index, ivar); 753} 754 755#define IGB_N0_QUEUE -1 756static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 757{ 758 struct igb_adapter *adapter = q_vector->adapter; 759 struct e1000_hw *hw = &adapter->hw; 760 int rx_queue = IGB_N0_QUEUE; 761 int tx_queue = IGB_N0_QUEUE; 762 u32 msixbm = 0; 763 764 if (q_vector->rx.ring) 765 rx_queue = q_vector->rx.ring->reg_idx; 766 if (q_vector->tx.ring) 767 tx_queue = q_vector->tx.ring->reg_idx; 768 769 switch (hw->mac.type) { 770 case e1000_82575: 771 /* The 82575 assigns vectors using a bitmask, which matches the 772 bitmask for the EICR/EIMS/EIMC registers. To assign one 773 or more queues to a vector, we write the appropriate bits 774 into the MSIXBM register for that vector. */ 775 if (rx_queue > IGB_N0_QUEUE) 776 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 777 if (tx_queue > IGB_N0_QUEUE) 778 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 779 if (!adapter->msix_entries && msix_vector == 0) 780 msixbm |= E1000_EIMS_OTHER; 781 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 782 q_vector->eims_value = msixbm; 783 break; 784 case e1000_82576: 785 /* 786 * 82576 uses a table that essentially consists of 2 columns 787 * with 8 rows. The ordering is column-major so we use the 788 * lower 3 bits as the row index, and the 4th bit as the 789 * column offset. 790 */ 791 if (rx_queue > IGB_N0_QUEUE) 792 igb_write_ivar(hw, msix_vector, 793 rx_queue & 0x7, 794 (rx_queue & 0x8) << 1); 795 if (tx_queue > IGB_N0_QUEUE) 796 igb_write_ivar(hw, msix_vector, 797 tx_queue & 0x7, 798 ((tx_queue & 0x8) << 1) + 8); 799 q_vector->eims_value = 1 << msix_vector; 800 break; 801 case e1000_82580: 802 case e1000_i350: 803 case e1000_i210: 804 case e1000_i211: 805 /* 806 * On 82580 and newer adapters the scheme is similar to 82576 807 * however instead of ordering column-major we have things 808 * ordered row-major. So we traverse the table by using 809 * bit 0 as the column offset, and the remaining bits as the 810 * row index. 811 */ 812 if (rx_queue > IGB_N0_QUEUE) 813 igb_write_ivar(hw, msix_vector, 814 rx_queue >> 1, 815 (rx_queue & 0x1) << 4); 816 if (tx_queue > IGB_N0_QUEUE) 817 igb_write_ivar(hw, msix_vector, 818 tx_queue >> 1, 819 ((tx_queue & 0x1) << 4) + 8); 820 q_vector->eims_value = 1 << msix_vector; 821 break; 822 default: 823 BUG(); 824 break; 825 } 826 827 /* add q_vector eims value to global eims_enable_mask */ 828 adapter->eims_enable_mask |= q_vector->eims_value; 829 830 /* configure q_vector to set itr on first interrupt */ 831 q_vector->set_itr = 1; 832} 833 834/** 835 * igb_configure_msix - Configure MSI-X hardware 836 * 837 * igb_configure_msix sets up the hardware to properly 838 * generate MSI-X interrupts. 839 **/ 840static void igb_configure_msix(struct igb_adapter *adapter) 841{ 842 u32 tmp; 843 int i, vector = 0; 844 struct e1000_hw *hw = &adapter->hw; 845 846 adapter->eims_enable_mask = 0; 847 848 /* set vector for other causes, i.e. link changes */ 849 switch (hw->mac.type) { 850 case e1000_82575: 851 tmp = rd32(E1000_CTRL_EXT); 852 /* enable MSI-X PBA support*/ 853 tmp |= E1000_CTRL_EXT_PBA_CLR; 854 855 /* Auto-Mask interrupts upon ICR read. */ 856 tmp |= E1000_CTRL_EXT_EIAME; 857 tmp |= E1000_CTRL_EXT_IRCA; 858 859 wr32(E1000_CTRL_EXT, tmp); 860 861 /* enable msix_other interrupt */ 862 array_wr32(E1000_MSIXBM(0), vector++, 863 E1000_EIMS_OTHER); 864 adapter->eims_other = E1000_EIMS_OTHER; 865 866 break; 867 868 case e1000_82576: 869 case e1000_82580: 870 case e1000_i350: 871 case e1000_i210: 872 case e1000_i211: 873 /* Turn on MSI-X capability first, or our settings 874 * won't stick. And it will take days to debug. */ 875 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 876 E1000_GPIE_PBA | E1000_GPIE_EIAME | 877 E1000_GPIE_NSICR); 878 879 /* enable msix_other interrupt */ 880 adapter->eims_other = 1 << vector; 881 tmp = (vector++ | E1000_IVAR_VALID) << 8; 882 883 wr32(E1000_IVAR_MISC, tmp); 884 break; 885 default: 886 /* do nothing, since nothing else supports MSI-X */ 887 break; 888 } /* switch (hw->mac.type) */ 889 890 adapter->eims_enable_mask |= adapter->eims_other; 891 892 for (i = 0; i < adapter->num_q_vectors; i++) 893 igb_assign_vector(adapter->q_vector[i], vector++); 894 895 wrfl(); 896} 897 898/** 899 * igb_request_msix - Initialize MSI-X interrupts 900 * 901 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 902 * kernel. 903 **/ 904static int igb_request_msix(struct igb_adapter *adapter) 905{ 906 struct net_device *netdev = adapter->netdev; 907 struct e1000_hw *hw = &adapter->hw; 908 int i, err = 0, vector = 0; 909 910 err = request_irq(adapter->msix_entries[vector].vector, 911 igb_msix_other, 0, netdev->name, adapter); 912 if (err) 913 goto out; 914 vector++; 915 916 for (i = 0; i < adapter->num_q_vectors; i++) { 917 struct igb_q_vector *q_vector = adapter->q_vector[i]; 918 919 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 920 921 if (q_vector->rx.ring && q_vector->tx.ring) 922 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 923 q_vector->rx.ring->queue_index); 924 else if (q_vector->tx.ring) 925 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 926 q_vector->tx.ring->queue_index); 927 else if (q_vector->rx.ring) 928 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 929 q_vector->rx.ring->queue_index); 930 else 931 sprintf(q_vector->name, "%s-unused", netdev->name); 932 933 err = request_irq(adapter->msix_entries[vector].vector, 934 igb_msix_ring, 0, q_vector->name, 935 q_vector); 936 if (err) 937 goto out; 938 vector++; 939 } 940 941 igb_configure_msix(adapter); 942 return 0; 943out: 944 return err; 945} 946 947static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 948{ 949 if (adapter->msix_entries) { 950 pci_disable_msix(adapter->pdev); 951 kfree(adapter->msix_entries); 952 adapter->msix_entries = NULL; 953 } else if (adapter->flags & IGB_FLAG_HAS_MSI) { 954 pci_disable_msi(adapter->pdev); 955 } 956} 957 958/** 959 * igb_free_q_vectors - Free memory allocated for interrupt vectors 960 * @adapter: board private structure to initialize 961 * 962 * This function frees the memory allocated to the q_vectors. In addition if 963 * NAPI is enabled it will delete any references to the NAPI struct prior 964 * to freeing the q_vector. 965 **/ 966static void igb_free_q_vectors(struct igb_adapter *adapter) 967{ 968 int v_idx; 969 970 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 971 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 972 adapter->q_vector[v_idx] = NULL; 973 if (!q_vector) 974 continue; 975 netif_napi_del(&q_vector->napi); 976 kfree(q_vector); 977 } 978 adapter->num_q_vectors = 0; 979} 980 981/** 982 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 983 * 984 * This function resets the device so that it has 0 rx queues, tx queues, and 985 * MSI-X interrupts allocated. 986 */ 987static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 988{ 989 igb_free_queues(adapter); 990 igb_free_q_vectors(adapter); 991 igb_reset_interrupt_capability(adapter); 992} 993 994/** 995 * igb_set_interrupt_capability - set MSI or MSI-X if supported 996 * 997 * Attempt to configure interrupts using the best available 998 * capabilities of the hardware and kernel. 999 **/ 1000static int igb_set_interrupt_capability(struct igb_adapter *adapter) 1001{ 1002 int err; 1003 int numvecs, i; 1004 1005 /* Number of supported queues. */ 1006 adapter->num_rx_queues = adapter->rss_queues; 1007 if (adapter->vfs_allocated_count) 1008 adapter->num_tx_queues = 1; 1009 else 1010 adapter->num_tx_queues = adapter->rss_queues; 1011 1012 /* start with one vector for every rx queue */ 1013 numvecs = adapter->num_rx_queues; 1014 1015 /* if tx handler is separate add 1 for every tx queue */ 1016 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1017 numvecs += adapter->num_tx_queues; 1018 1019 /* store the number of vectors reserved for queues */ 1020 adapter->num_q_vectors = numvecs; 1021 1022 /* add 1 vector for link status interrupts */ 1023 numvecs++; 1024 adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry), 1025 GFP_KERNEL); 1026 1027 if (!adapter->msix_entries) 1028 goto msi_only; 1029 1030 for (i = 0; i < numvecs; i++) 1031 adapter->msix_entries[i].entry = i; 1032 1033 err = pci_enable_msix(adapter->pdev, 1034 adapter->msix_entries, 1035 numvecs); 1036 if (err == 0) 1037 goto out; 1038 1039 igb_reset_interrupt_capability(adapter); 1040 1041 /* If we can't do MSI-X, try MSI */ 1042msi_only: 1043#ifdef CONFIG_PCI_IOV 1044 /* disable SR-IOV for non MSI-X configurations */ 1045 if (adapter->vf_data) { 1046 struct e1000_hw *hw = &adapter->hw; 1047 /* disable iov and allow time for transactions to clear */ 1048 pci_disable_sriov(adapter->pdev); 1049 msleep(500); 1050 1051 kfree(adapter->vf_data); 1052 adapter->vf_data = NULL; 1053 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1054 wrfl(); 1055 msleep(100); 1056 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1057 } 1058#endif 1059 adapter->vfs_allocated_count = 0; 1060 adapter->rss_queues = 1; 1061 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1062 adapter->num_rx_queues = 1; 1063 adapter->num_tx_queues = 1; 1064 adapter->num_q_vectors = 1; 1065 if (!pci_enable_msi(adapter->pdev)) 1066 adapter->flags |= IGB_FLAG_HAS_MSI; 1067out: 1068 /* Notify the stack of the (possibly) reduced queue counts. */ 1069 rtnl_lock(); 1070 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues); 1071 err = netif_set_real_num_rx_queues(adapter->netdev, 1072 adapter->num_rx_queues); 1073 rtnl_unlock(); 1074 return err; 1075} 1076 1077/** 1078 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1079 * @adapter: board private structure to initialize 1080 * 1081 * We allocate one q_vector per queue interrupt. If allocation fails we 1082 * return -ENOMEM. 1083 **/ 1084static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1085{ 1086 struct igb_q_vector *q_vector; 1087 struct e1000_hw *hw = &adapter->hw; 1088 int v_idx; 1089 1090 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) { 1091 q_vector = kzalloc(sizeof(struct igb_q_vector), 1092 GFP_KERNEL); 1093 if (!q_vector) 1094 goto err_out; 1095 q_vector->adapter = adapter; 1096 q_vector->itr_register = hw->hw_addr + E1000_EITR(0); 1097 q_vector->itr_val = IGB_START_ITR; 1098 netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64); 1099 adapter->q_vector[v_idx] = q_vector; 1100 } 1101 1102 return 0; 1103 1104err_out: 1105 igb_free_q_vectors(adapter); 1106 return -ENOMEM; 1107} 1108 1109static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter, 1110 int ring_idx, int v_idx) 1111{ 1112 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1113 1114 q_vector->rx.ring = adapter->rx_ring[ring_idx]; 1115 q_vector->rx.ring->q_vector = q_vector; 1116 q_vector->rx.count++; 1117 q_vector->itr_val = adapter->rx_itr_setting; 1118 if (q_vector->itr_val && q_vector->itr_val <= 3) 1119 q_vector->itr_val = IGB_START_ITR; 1120} 1121 1122static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter, 1123 int ring_idx, int v_idx) 1124{ 1125 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1126 1127 q_vector->tx.ring = adapter->tx_ring[ring_idx]; 1128 q_vector->tx.ring->q_vector = q_vector; 1129 q_vector->tx.count++; 1130 q_vector->itr_val = adapter->tx_itr_setting; 1131 q_vector->tx.work_limit = adapter->tx_work_limit; 1132 if (q_vector->itr_val && q_vector->itr_val <= 3) 1133 q_vector->itr_val = IGB_START_ITR; 1134} 1135 1136/** 1137 * igb_map_ring_to_vector - maps allocated queues to vectors 1138 * 1139 * This function maps the recently allocated queues to vectors. 1140 **/ 1141static int igb_map_ring_to_vector(struct igb_adapter *adapter) 1142{ 1143 int i; 1144 int v_idx = 0; 1145 1146 if ((adapter->num_q_vectors < adapter->num_rx_queues) || 1147 (adapter->num_q_vectors < adapter->num_tx_queues)) 1148 return -ENOMEM; 1149 1150 if (adapter->num_q_vectors >= 1151 (adapter->num_rx_queues + adapter->num_tx_queues)) { 1152 for (i = 0; i < adapter->num_rx_queues; i++) 1153 igb_map_rx_ring_to_vector(adapter, i, v_idx++); 1154 for (i = 0; i < adapter->num_tx_queues; i++) 1155 igb_map_tx_ring_to_vector(adapter, i, v_idx++); 1156 } else { 1157 for (i = 0; i < adapter->num_rx_queues; i++) { 1158 if (i < adapter->num_tx_queues) 1159 igb_map_tx_ring_to_vector(adapter, i, v_idx); 1160 igb_map_rx_ring_to_vector(adapter, i, v_idx++); 1161 } 1162 for (; i < adapter->num_tx_queues; i++) 1163 igb_map_tx_ring_to_vector(adapter, i, v_idx++); 1164 } 1165 return 0; 1166} 1167 1168/** 1169 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1170 * 1171 * This function initializes the interrupts and allocates all of the queues. 1172 **/ 1173static int igb_init_interrupt_scheme(struct igb_adapter *adapter) 1174{ 1175 struct pci_dev *pdev = adapter->pdev; 1176 int err; 1177 1178 err = igb_set_interrupt_capability(adapter); 1179 if (err) 1180 return err; 1181 1182 err = igb_alloc_q_vectors(adapter); 1183 if (err) { 1184 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1185 goto err_alloc_q_vectors; 1186 } 1187 1188 err = igb_alloc_queues(adapter); 1189 if (err) { 1190 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 1191 goto err_alloc_queues; 1192 } 1193 1194 err = igb_map_ring_to_vector(adapter); 1195 if (err) { 1196 dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n"); 1197 goto err_map_queues; 1198 } 1199 1200 1201 return 0; 1202err_map_queues: 1203 igb_free_queues(adapter); 1204err_alloc_queues: 1205 igb_free_q_vectors(adapter); 1206err_alloc_q_vectors: 1207 igb_reset_interrupt_capability(adapter); 1208 return err; 1209} 1210 1211/** 1212 * igb_request_irq - initialize interrupts 1213 * 1214 * Attempts to configure interrupts using the best available 1215 * capabilities of the hardware and kernel. 1216 **/ 1217static int igb_request_irq(struct igb_adapter *adapter) 1218{ 1219 struct net_device *netdev = adapter->netdev; 1220 struct pci_dev *pdev = adapter->pdev; 1221 int err = 0; 1222 1223 if (adapter->msix_entries) { 1224 err = igb_request_msix(adapter); 1225 if (!err) 1226 goto request_done; 1227 /* fall back to MSI */ 1228 igb_clear_interrupt_scheme(adapter); 1229 if (!pci_enable_msi(pdev)) 1230 adapter->flags |= IGB_FLAG_HAS_MSI; 1231 igb_free_all_tx_resources(adapter); 1232 igb_free_all_rx_resources(adapter); 1233 adapter->num_tx_queues = 1; 1234 adapter->num_rx_queues = 1; 1235 adapter->num_q_vectors = 1; 1236 err = igb_alloc_q_vectors(adapter); 1237 if (err) { 1238 dev_err(&pdev->dev, 1239 "Unable to allocate memory for vectors\n"); 1240 goto request_done; 1241 } 1242 err = igb_alloc_queues(adapter); 1243 if (err) { 1244 dev_err(&pdev->dev, 1245 "Unable to allocate memory for queues\n"); 1246 igb_free_q_vectors(adapter); 1247 goto request_done; 1248 } 1249 igb_setup_all_tx_resources(adapter); 1250 igb_setup_all_rx_resources(adapter); 1251 } 1252 1253 igb_assign_vector(adapter->q_vector[0], 0); 1254 1255 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1256 err = request_irq(pdev->irq, igb_intr_msi, 0, 1257 netdev->name, adapter); 1258 if (!err) 1259 goto request_done; 1260 1261 /* fall back to legacy interrupts */ 1262 igb_reset_interrupt_capability(adapter); 1263 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1264 } 1265 1266 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1267 netdev->name, adapter); 1268 1269 if (err) 1270 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1271 err); 1272 1273request_done: 1274 return err; 1275} 1276 1277static void igb_free_irq(struct igb_adapter *adapter) 1278{ 1279 if (adapter->msix_entries) { 1280 int vector = 0, i; 1281 1282 free_irq(adapter->msix_entries[vector++].vector, adapter); 1283 1284 for (i = 0; i < adapter->num_q_vectors; i++) 1285 free_irq(adapter->msix_entries[vector++].vector, 1286 adapter->q_vector[i]); 1287 } else { 1288 free_irq(adapter->pdev->irq, adapter); 1289 } 1290} 1291 1292/** 1293 * igb_irq_disable - Mask off interrupt generation on the NIC 1294 * @adapter: board private structure 1295 **/ 1296static void igb_irq_disable(struct igb_adapter *adapter) 1297{ 1298 struct e1000_hw *hw = &adapter->hw; 1299 1300 /* 1301 * we need to be careful when disabling interrupts. The VFs are also 1302 * mapped into these registers and so clearing the bits can cause 1303 * issues on the VF drivers so we only need to clear what we set 1304 */ 1305 if (adapter->msix_entries) { 1306 u32 regval = rd32(E1000_EIAM); 1307 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1308 wr32(E1000_EIMC, adapter->eims_enable_mask); 1309 regval = rd32(E1000_EIAC); 1310 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1311 } 1312 1313 wr32(E1000_IAM, 0); 1314 wr32(E1000_IMC, ~0); 1315 wrfl(); 1316 if (adapter->msix_entries) { 1317 int i; 1318 for (i = 0; i < adapter->num_q_vectors; i++) 1319 synchronize_irq(adapter->msix_entries[i].vector); 1320 } else { 1321 synchronize_irq(adapter->pdev->irq); 1322 } 1323} 1324 1325/** 1326 * igb_irq_enable - Enable default interrupt generation settings 1327 * @adapter: board private structure 1328 **/ 1329static void igb_irq_enable(struct igb_adapter *adapter) 1330{ 1331 struct e1000_hw *hw = &adapter->hw; 1332 1333 if (adapter->msix_entries) { 1334 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1335 u32 regval = rd32(E1000_EIAC); 1336 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1337 regval = rd32(E1000_EIAM); 1338 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1339 wr32(E1000_EIMS, adapter->eims_enable_mask); 1340 if (adapter->vfs_allocated_count) { 1341 wr32(E1000_MBVFIMR, 0xFF); 1342 ims |= E1000_IMS_VMMB; 1343 } 1344 wr32(E1000_IMS, ims); 1345 } else { 1346 wr32(E1000_IMS, IMS_ENABLE_MASK | 1347 E1000_IMS_DRSTA); 1348 wr32(E1000_IAM, IMS_ENABLE_MASK | 1349 E1000_IMS_DRSTA); 1350 } 1351} 1352 1353static void igb_update_mng_vlan(struct igb_adapter *adapter) 1354{ 1355 struct e1000_hw *hw = &adapter->hw; 1356 u16 vid = adapter->hw.mng_cookie.vlan_id; 1357 u16 old_vid = adapter->mng_vlan_id; 1358 1359 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1360 /* add VID to filter table */ 1361 igb_vfta_set(hw, vid, true); 1362 adapter->mng_vlan_id = vid; 1363 } else { 1364 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1365 } 1366 1367 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1368 (vid != old_vid) && 1369 !test_bit(old_vid, adapter->active_vlans)) { 1370 /* remove VID from filter table */ 1371 igb_vfta_set(hw, old_vid, false); 1372 } 1373} 1374 1375/** 1376 * igb_release_hw_control - release control of the h/w to f/w 1377 * @adapter: address of board private structure 1378 * 1379 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1380 * For ASF and Pass Through versions of f/w this means that the 1381 * driver is no longer loaded. 1382 * 1383 **/ 1384static void igb_release_hw_control(struct igb_adapter *adapter) 1385{ 1386 struct e1000_hw *hw = &adapter->hw; 1387 u32 ctrl_ext; 1388 1389 /* Let firmware take over control of h/w */ 1390 ctrl_ext = rd32(E1000_CTRL_EXT); 1391 wr32(E1000_CTRL_EXT, 1392 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1393} 1394 1395/** 1396 * igb_get_hw_control - get control of the h/w from f/w 1397 * @adapter: address of board private structure 1398 * 1399 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1400 * For ASF and Pass Through versions of f/w this means that 1401 * the driver is loaded. 1402 * 1403 **/ 1404static void igb_get_hw_control(struct igb_adapter *adapter) 1405{ 1406 struct e1000_hw *hw = &adapter->hw; 1407 u32 ctrl_ext; 1408 1409 /* Let firmware know the driver has taken over */ 1410 ctrl_ext = rd32(E1000_CTRL_EXT); 1411 wr32(E1000_CTRL_EXT, 1412 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1413} 1414 1415/** 1416 * igb_configure - configure the hardware for RX and TX 1417 * @adapter: private board structure 1418 **/ 1419static void igb_configure(struct igb_adapter *adapter) 1420{ 1421 struct net_device *netdev = adapter->netdev; 1422 int i; 1423 1424 igb_get_hw_control(adapter); 1425 igb_set_rx_mode(netdev); 1426 1427 igb_restore_vlan(adapter); 1428 1429 igb_setup_tctl(adapter); 1430 igb_setup_mrqc(adapter); 1431 igb_setup_rctl(adapter); 1432 1433 igb_configure_tx(adapter); 1434 igb_configure_rx(adapter); 1435 1436 igb_rx_fifo_flush_82575(&adapter->hw); 1437 1438 /* call igb_desc_unused which always leaves 1439 * at least 1 descriptor unused to make sure 1440 * next_to_use != next_to_clean */ 1441 for (i = 0; i < adapter->num_rx_queues; i++) { 1442 struct igb_ring *ring = adapter->rx_ring[i]; 1443 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1444 } 1445} 1446 1447/** 1448 * igb_power_up_link - Power up the phy/serdes link 1449 * @adapter: address of board private structure 1450 **/ 1451void igb_power_up_link(struct igb_adapter *adapter) 1452{ 1453 igb_reset_phy(&adapter->hw); 1454 1455 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1456 igb_power_up_phy_copper(&adapter->hw); 1457 else 1458 igb_power_up_serdes_link_82575(&adapter->hw); 1459} 1460 1461/** 1462 * igb_power_down_link - Power down the phy/serdes link 1463 * @adapter: address of board private structure 1464 */ 1465static void igb_power_down_link(struct igb_adapter *adapter) 1466{ 1467 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1468 igb_power_down_phy_copper_82575(&adapter->hw); 1469 else 1470 igb_shutdown_serdes_link_82575(&adapter->hw); 1471} 1472 1473/** 1474 * igb_up - Open the interface and prepare it to handle traffic 1475 * @adapter: board private structure 1476 **/ 1477int igb_up(struct igb_adapter *adapter) 1478{ 1479 struct e1000_hw *hw = &adapter->hw; 1480 int i; 1481 1482 /* hardware has been reset, we need to reload some things */ 1483 igb_configure(adapter); 1484 1485 clear_bit(__IGB_DOWN, &adapter->state); 1486 1487 for (i = 0; i < adapter->num_q_vectors; i++) 1488 napi_enable(&(adapter->q_vector[i]->napi)); 1489 1490 if (adapter->msix_entries) 1491 igb_configure_msix(adapter); 1492 else 1493 igb_assign_vector(adapter->q_vector[0], 0); 1494 1495 /* Clear any pending interrupts. */ 1496 rd32(E1000_ICR); 1497 igb_irq_enable(adapter); 1498 1499 /* notify VFs that reset has been completed */ 1500 if (adapter->vfs_allocated_count) { 1501 u32 reg_data = rd32(E1000_CTRL_EXT); 1502 reg_data |= E1000_CTRL_EXT_PFRSTD; 1503 wr32(E1000_CTRL_EXT, reg_data); 1504 } 1505 1506 netif_tx_start_all_queues(adapter->netdev); 1507 1508 /* start the watchdog. */ 1509 hw->mac.get_link_status = 1; 1510 schedule_work(&adapter->watchdog_task); 1511 1512 return 0; 1513} 1514 1515void igb_down(struct igb_adapter *adapter) 1516{ 1517 struct net_device *netdev = adapter->netdev; 1518 struct e1000_hw *hw = &adapter->hw; 1519 u32 tctl, rctl; 1520 int i; 1521 1522 /* signal that we're down so the interrupt handler does not 1523 * reschedule our watchdog timer */ 1524 set_bit(__IGB_DOWN, &adapter->state); 1525 1526 /* disable receives in the hardware */ 1527 rctl = rd32(E1000_RCTL); 1528 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1529 /* flush and sleep below */ 1530 1531 netif_tx_stop_all_queues(netdev); 1532 1533 /* disable transmits in the hardware */ 1534 tctl = rd32(E1000_TCTL); 1535 tctl &= ~E1000_TCTL_EN; 1536 wr32(E1000_TCTL, tctl); 1537 /* flush both disables and wait for them to finish */ 1538 wrfl(); 1539 msleep(10); 1540 1541 for (i = 0; i < adapter->num_q_vectors; i++) 1542 napi_disable(&(adapter->q_vector[i]->napi)); 1543 1544 igb_irq_disable(adapter); 1545 1546 del_timer_sync(&adapter->watchdog_timer); 1547 del_timer_sync(&adapter->phy_info_timer); 1548 1549 netif_carrier_off(netdev); 1550 1551 /* record the stats before reset*/ 1552 spin_lock(&adapter->stats64_lock); 1553 igb_update_stats(adapter, &adapter->stats64); 1554 spin_unlock(&adapter->stats64_lock); 1555 1556 adapter->link_speed = 0; 1557 adapter->link_duplex = 0; 1558 1559 if (!pci_channel_offline(adapter->pdev)) 1560 igb_reset(adapter); 1561 igb_clean_all_tx_rings(adapter); 1562 igb_clean_all_rx_rings(adapter); 1563#ifdef CONFIG_IGB_DCA 1564 1565 /* since we reset the hardware DCA settings were cleared */ 1566 igb_setup_dca(adapter); 1567#endif 1568} 1569 1570void igb_reinit_locked(struct igb_adapter *adapter) 1571{ 1572 WARN_ON(in_interrupt()); 1573 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1574 msleep(1); 1575 igb_down(adapter); 1576 igb_up(adapter); 1577 clear_bit(__IGB_RESETTING, &adapter->state); 1578} 1579 1580void igb_reset(struct igb_adapter *adapter) 1581{ 1582 struct pci_dev *pdev = adapter->pdev; 1583 struct e1000_hw *hw = &adapter->hw; 1584 struct e1000_mac_info *mac = &hw->mac; 1585 struct e1000_fc_info *fc = &hw->fc; 1586 u32 pba = 0, tx_space, min_tx_space, min_rx_space; 1587 u16 hwm; 1588 1589 /* Repartition Pba for greater than 9k mtu 1590 * To take effect CTRL.RST is required. 1591 */ 1592 switch (mac->type) { 1593 case e1000_i350: 1594 case e1000_82580: 1595 pba = rd32(E1000_RXPBS); 1596 pba = igb_rxpbs_adjust_82580(pba); 1597 break; 1598 case e1000_82576: 1599 pba = rd32(E1000_RXPBS); 1600 pba &= E1000_RXPBS_SIZE_MASK_82576; 1601 break; 1602 case e1000_82575: 1603 case e1000_i210: 1604 case e1000_i211: 1605 default: 1606 pba = E1000_PBA_34K; 1607 break; 1608 } 1609 1610 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1611 (mac->type < e1000_82576)) { 1612 /* adjust PBA for jumbo frames */ 1613 wr32(E1000_PBA, pba); 1614 1615 /* To maintain wire speed transmits, the Tx FIFO should be 1616 * large enough to accommodate two full transmit packets, 1617 * rounded up to the next 1KB and expressed in KB. Likewise, 1618 * the Rx FIFO should be large enough to accommodate at least 1619 * one full receive packet and is similarly rounded up and 1620 * expressed in KB. */ 1621 pba = rd32(E1000_PBA); 1622 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1623 tx_space = pba >> 16; 1624 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1625 pba &= 0xffff; 1626 /* the tx fifo also stores 16 bytes of information about the tx 1627 * but don't include ethernet FCS because hardware appends it */ 1628 min_tx_space = (adapter->max_frame_size + 1629 sizeof(union e1000_adv_tx_desc) - 1630 ETH_FCS_LEN) * 2; 1631 min_tx_space = ALIGN(min_tx_space, 1024); 1632 min_tx_space >>= 10; 1633 /* software strips receive CRC, so leave room for it */ 1634 min_rx_space = adapter->max_frame_size; 1635 min_rx_space = ALIGN(min_rx_space, 1024); 1636 min_rx_space >>= 10; 1637 1638 /* If current Tx allocation is less than the min Tx FIFO size, 1639 * and the min Tx FIFO size is less than the current Rx FIFO 1640 * allocation, take space away from current Rx allocation */ 1641 if (tx_space < min_tx_space && 1642 ((min_tx_space - tx_space) < pba)) { 1643 pba = pba - (min_tx_space - tx_space); 1644 1645 /* if short on rx space, rx wins and must trump tx 1646 * adjustment */ 1647 if (pba < min_rx_space) 1648 pba = min_rx_space; 1649 } 1650 wr32(E1000_PBA, pba); 1651 } 1652 1653 /* flow control settings */ 1654 /* The high water mark must be low enough to fit one full frame 1655 * (or the size used for early receive) above it in the Rx FIFO. 1656 * Set it to the lower of: 1657 * - 90% of the Rx FIFO size, or 1658 * - the full Rx FIFO size minus one full frame */ 1659 hwm = min(((pba << 10) * 9 / 10), 1660 ((pba << 10) - 2 * adapter->max_frame_size)); 1661 1662 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */ 1663 fc->low_water = fc->high_water - 16; 1664 fc->pause_time = 0xFFFF; 1665 fc->send_xon = 1; 1666 fc->current_mode = fc->requested_mode; 1667 1668 /* disable receive for all VFs and wait one second */ 1669 if (adapter->vfs_allocated_count) { 1670 int i; 1671 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1672 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1673 1674 /* ping all the active vfs to let them know we are going down */ 1675 igb_ping_all_vfs(adapter); 1676 1677 /* disable transmits and receives */ 1678 wr32(E1000_VFRE, 0); 1679 wr32(E1000_VFTE, 0); 1680 } 1681 1682 /* Allow time for pending master requests to run */ 1683 hw->mac.ops.reset_hw(hw); 1684 wr32(E1000_WUC, 0); 1685 1686 if (hw->mac.ops.init_hw(hw)) 1687 dev_err(&pdev->dev, "Hardware Error\n"); 1688 1689 /* 1690 * Flow control settings reset on hardware reset, so guarantee flow 1691 * control is off when forcing speed. 1692 */ 1693 if (!hw->mac.autoneg) 1694 igb_force_mac_fc(hw); 1695 1696 igb_init_dmac(adapter, pba); 1697 if (!netif_running(adapter->netdev)) 1698 igb_power_down_link(adapter); 1699 1700 igb_update_mng_vlan(adapter); 1701 1702 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 1703 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 1704 1705#ifdef CONFIG_IGB_PTP 1706 /* Re-enable PTP, where applicable. */ 1707 igb_ptp_reset(adapter); 1708#endif /* CONFIG_IGB_PTP */ 1709 1710 igb_get_phy_info(hw); 1711} 1712 1713static netdev_features_t igb_fix_features(struct net_device *netdev, 1714 netdev_features_t features) 1715{ 1716 /* 1717 * Since there is no support for separate rx/tx vlan accel 1718 * enable/disable make sure tx flag is always in same state as rx. 1719 */ 1720 if (features & NETIF_F_HW_VLAN_RX) 1721 features |= NETIF_F_HW_VLAN_TX; 1722 else 1723 features &= ~NETIF_F_HW_VLAN_TX; 1724 1725 return features; 1726} 1727 1728static int igb_set_features(struct net_device *netdev, 1729 netdev_features_t features) 1730{ 1731 netdev_features_t changed = netdev->features ^ features; 1732 struct igb_adapter *adapter = netdev_priv(netdev); 1733 1734 if (changed & NETIF_F_HW_VLAN_RX) 1735 igb_vlan_mode(netdev, features); 1736 1737 if (!(changed & NETIF_F_RXALL)) 1738 return 0; 1739 1740 netdev->features = features; 1741 1742 if (netif_running(netdev)) 1743 igb_reinit_locked(adapter); 1744 else 1745 igb_reset(adapter); 1746 1747 return 0; 1748} 1749 1750static const struct net_device_ops igb_netdev_ops = { 1751 .ndo_open = igb_open, 1752 .ndo_stop = igb_close, 1753 .ndo_start_xmit = igb_xmit_frame, 1754 .ndo_get_stats64 = igb_get_stats64, 1755 .ndo_set_rx_mode = igb_set_rx_mode, 1756 .ndo_set_mac_address = igb_set_mac, 1757 .ndo_change_mtu = igb_change_mtu, 1758 .ndo_do_ioctl = igb_ioctl, 1759 .ndo_tx_timeout = igb_tx_timeout, 1760 .ndo_validate_addr = eth_validate_addr, 1761 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 1762 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 1763 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 1764 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 1765 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, 1766 .ndo_get_vf_config = igb_ndo_get_vf_config, 1767#ifdef CONFIG_NET_POLL_CONTROLLER 1768 .ndo_poll_controller = igb_netpoll, 1769#endif 1770 .ndo_fix_features = igb_fix_features, 1771 .ndo_set_features = igb_set_features, 1772}; 1773 1774/** 1775 * igb_set_fw_version - Configure version string for ethtool 1776 * @adapter: adapter struct 1777 * 1778 **/ 1779void igb_set_fw_version(struct igb_adapter *adapter) 1780{ 1781 struct e1000_hw *hw = &adapter->hw; 1782 u16 eeprom_verh, eeprom_verl, comb_verh, comb_verl, comb_offset; 1783 u16 major, build, patch, fw_version; 1784 u32 etrack_id; 1785 1786 hw->nvm.ops.read(hw, 5, 1, &fw_version); 1787 if (adapter->hw.mac.type != e1000_i211) { 1788 hw->nvm.ops.read(hw, NVM_ETRACK_WORD, 1, &eeprom_verh); 1789 hw->nvm.ops.read(hw, (NVM_ETRACK_WORD + 1), 1, &eeprom_verl); 1790 etrack_id = (eeprom_verh << IGB_ETRACK_SHIFT) | eeprom_verl; 1791 1792 /* combo image version needs to be found */ 1793 hw->nvm.ops.read(hw, NVM_COMB_VER_PTR, 1, &comb_offset); 1794 if ((comb_offset != 0x0) && 1795 (comb_offset != IGB_NVM_VER_INVALID)) { 1796 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset 1797 + 1), 1, &comb_verh); 1798 hw->nvm.ops.read(hw, (NVM_COMB_VER_OFF + comb_offset), 1799 1, &comb_verl); 1800 1801 /* Only display Option Rom if it exists and is valid */ 1802 if ((comb_verh && comb_verl) && 1803 ((comb_verh != IGB_NVM_VER_INVALID) && 1804 (comb_verl != IGB_NVM_VER_INVALID))) { 1805 major = comb_verl >> IGB_COMB_VER_SHFT; 1806 build = (comb_verl << IGB_COMB_VER_SHFT) | 1807 (comb_verh >> IGB_COMB_VER_SHFT); 1808 patch = comb_verh & IGB_COMB_VER_MASK; 1809 snprintf(adapter->fw_version, 1810 sizeof(adapter->fw_version), 1811 "%d.%d%d, 0x%08x, %d.%d.%d", 1812 (fw_version & IGB_MAJOR_MASK) >> 1813 IGB_MAJOR_SHIFT, 1814 (fw_version & IGB_MINOR_MASK) >> 1815 IGB_MINOR_SHIFT, 1816 (fw_version & IGB_BUILD_MASK), 1817 etrack_id, major, build, patch); 1818 goto out; 1819 } 1820 } 1821 snprintf(adapter->fw_version, sizeof(adapter->fw_version), 1822 "%d.%d%d, 0x%08x", 1823 (fw_version & IGB_MAJOR_MASK) >> IGB_MAJOR_SHIFT, 1824 (fw_version & IGB_MINOR_MASK) >> IGB_MINOR_SHIFT, 1825 (fw_version & IGB_BUILD_MASK), etrack_id); 1826 } else { 1827 snprintf(adapter->fw_version, sizeof(adapter->fw_version), 1828 "%d.%d%d", 1829 (fw_version & IGB_MAJOR_MASK) >> IGB_MAJOR_SHIFT, 1830 (fw_version & IGB_MINOR_MASK) >> IGB_MINOR_SHIFT, 1831 (fw_version & IGB_BUILD_MASK)); 1832 } 1833out: 1834 return; 1835} 1836 1837/** 1838 * igb_probe - Device Initialization Routine 1839 * @pdev: PCI device information struct 1840 * @ent: entry in igb_pci_tbl 1841 * 1842 * Returns 0 on success, negative on failure 1843 * 1844 * igb_probe initializes an adapter identified by a pci_dev structure. 1845 * The OS initialization, configuring of the adapter private structure, 1846 * and a hardware reset occur. 1847 **/ 1848static int __devinit igb_probe(struct pci_dev *pdev, 1849 const struct pci_device_id *ent) 1850{ 1851 struct net_device *netdev; 1852 struct igb_adapter *adapter; 1853 struct e1000_hw *hw; 1854 u16 eeprom_data = 0; 1855 s32 ret_val; 1856 static int global_quad_port_a; /* global quad port a indication */ 1857 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 1858 unsigned long mmio_start, mmio_len; 1859 int err, pci_using_dac; 1860 u16 eeprom_apme_mask = IGB_EEPROM_APME; 1861 u8 part_str[E1000_PBANUM_LENGTH]; 1862 1863 /* Catch broken hardware that put the wrong VF device ID in 1864 * the PCIe SR-IOV capability. 1865 */ 1866 if (pdev->is_virtfn) { 1867 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 1868 pci_name(pdev), pdev->vendor, pdev->device); 1869 return -EINVAL; 1870 } 1871 1872 err = pci_enable_device_mem(pdev); 1873 if (err) 1874 return err; 1875 1876 pci_using_dac = 0; 1877 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); 1878 if (!err) { 1879 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); 1880 if (!err) 1881 pci_using_dac = 1; 1882 } else { 1883 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 1884 if (err) { 1885 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); 1886 if (err) { 1887 dev_err(&pdev->dev, "No usable DMA " 1888 "configuration, aborting\n"); 1889 goto err_dma; 1890 } 1891 } 1892 } 1893 1894 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 1895 IORESOURCE_MEM), 1896 igb_driver_name); 1897 if (err) 1898 goto err_pci_reg; 1899 1900 pci_enable_pcie_error_reporting(pdev); 1901 1902 pci_set_master(pdev); 1903 pci_save_state(pdev); 1904 1905 err = -ENOMEM; 1906 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 1907 IGB_MAX_TX_QUEUES); 1908 if (!netdev) 1909 goto err_alloc_etherdev; 1910 1911 SET_NETDEV_DEV(netdev, &pdev->dev); 1912 1913 pci_set_drvdata(pdev, netdev); 1914 adapter = netdev_priv(netdev); 1915 adapter->netdev = netdev; 1916 adapter->pdev = pdev; 1917 hw = &adapter->hw; 1918 hw->back = adapter; 1919 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 1920 1921 mmio_start = pci_resource_start(pdev, 0); 1922 mmio_len = pci_resource_len(pdev, 0); 1923 1924 err = -EIO; 1925 hw->hw_addr = ioremap(mmio_start, mmio_len); 1926 if (!hw->hw_addr) 1927 goto err_ioremap; 1928 1929 netdev->netdev_ops = &igb_netdev_ops; 1930 igb_set_ethtool_ops(netdev); 1931 netdev->watchdog_timeo = 5 * HZ; 1932 1933 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 1934 1935 netdev->mem_start = mmio_start; 1936 netdev->mem_end = mmio_start + mmio_len; 1937 1938 /* PCI config space info */ 1939 hw->vendor_id = pdev->vendor; 1940 hw->device_id = pdev->device; 1941 hw->revision_id = pdev->revision; 1942 hw->subsystem_vendor_id = pdev->subsystem_vendor; 1943 hw->subsystem_device_id = pdev->subsystem_device; 1944 1945 /* Copy the default MAC, PHY and NVM function pointers */ 1946 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 1947 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 1948 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 1949 /* Initialize skew-specific constants */ 1950 err = ei->get_invariants(hw); 1951 if (err) 1952 goto err_sw_init; 1953 1954 /* setup the private structure */ 1955 err = igb_sw_init(adapter); 1956 if (err) 1957 goto err_sw_init; 1958 1959 igb_get_bus_info_pcie(hw); 1960 1961 hw->phy.autoneg_wait_to_complete = false; 1962 1963 /* Copper options */ 1964 if (hw->phy.media_type == e1000_media_type_copper) { 1965 hw->phy.mdix = AUTO_ALL_MODES; 1966 hw->phy.disable_polarity_correction = false; 1967 hw->phy.ms_type = e1000_ms_hw_default; 1968 } 1969 1970 if (igb_check_reset_block(hw)) 1971 dev_info(&pdev->dev, 1972 "PHY reset is blocked due to SOL/IDER session.\n"); 1973 1974 /* 1975 * features is initialized to 0 in allocation, it might have bits 1976 * set by igb_sw_init so we should use an or instead of an 1977 * assignment. 1978 */ 1979 netdev->features |= NETIF_F_SG | 1980 NETIF_F_IP_CSUM | 1981 NETIF_F_IPV6_CSUM | 1982 NETIF_F_TSO | 1983 NETIF_F_TSO6 | 1984 NETIF_F_RXHASH | 1985 NETIF_F_RXCSUM | 1986 NETIF_F_HW_VLAN_RX | 1987 NETIF_F_HW_VLAN_TX; 1988 1989 /* copy netdev features into list of user selectable features */ 1990 netdev->hw_features |= netdev->features; 1991 netdev->hw_features |= NETIF_F_RXALL; 1992 1993 /* set this bit last since it cannot be part of hw_features */ 1994 netdev->features |= NETIF_F_HW_VLAN_FILTER; 1995 1996 netdev->vlan_features |= NETIF_F_TSO | 1997 NETIF_F_TSO6 | 1998 NETIF_F_IP_CSUM | 1999 NETIF_F_IPV6_CSUM | 2000 NETIF_F_SG; 2001 2002 netdev->priv_flags |= IFF_SUPP_NOFCS; 2003 2004 if (pci_using_dac) { 2005 netdev->features |= NETIF_F_HIGHDMA; 2006 netdev->vlan_features |= NETIF_F_HIGHDMA; 2007 } 2008 2009 if (hw->mac.type >= e1000_82576) { 2010 netdev->hw_features |= NETIF_F_SCTP_CSUM; 2011 netdev->features |= NETIF_F_SCTP_CSUM; 2012 } 2013 2014 netdev->priv_flags |= IFF_UNICAST_FLT; 2015 2016 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2017 2018 /* before reading the NVM, reset the controller to put the device in a 2019 * known good starting state */ 2020 hw->mac.ops.reset_hw(hw); 2021 2022 /* 2023 * make sure the NVM is good , i211 parts have special NVM that 2024 * doesn't contain a checksum 2025 */ 2026 if (hw->mac.type != e1000_i211) { 2027 if (hw->nvm.ops.validate(hw) < 0) { 2028 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2029 err = -EIO; 2030 goto err_eeprom; 2031 } 2032 } 2033 2034 /* copy the MAC address out of the NVM */ 2035 if (hw->mac.ops.read_mac_addr(hw)) 2036 dev_err(&pdev->dev, "NVM Read Error\n"); 2037 2038 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2039 memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len); 2040 2041 if (!is_valid_ether_addr(netdev->perm_addr)) { 2042 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2043 err = -EIO; 2044 goto err_eeprom; 2045 } 2046 2047 /* get firmware version for ethtool -i */ 2048 igb_set_fw_version(adapter); 2049 2050 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2051 (unsigned long) adapter); 2052 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2053 (unsigned long) adapter); 2054 2055 INIT_WORK(&adapter->reset_task, igb_reset_task); 2056 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2057 2058 /* Initialize link properties that are user-changeable */ 2059 adapter->fc_autoneg = true; 2060 hw->mac.autoneg = true; 2061 hw->phy.autoneg_advertised = 0x2f; 2062 2063 hw->fc.requested_mode = e1000_fc_default; 2064 hw->fc.current_mode = e1000_fc_default; 2065 2066 igb_validate_mdi_setting(hw); 2067 2068 /* Initial Wake on LAN setting If APM wake is enabled in the EEPROM, 2069 * enable the ACPI Magic Packet filter 2070 */ 2071 2072 if (hw->bus.func == 0) 2073 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data); 2074 else if (hw->mac.type >= e1000_82580) 2075 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2076 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2077 &eeprom_data); 2078 else if (hw->bus.func == 1) 2079 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2080 2081 if (eeprom_data & eeprom_apme_mask) 2082 adapter->eeprom_wol |= E1000_WUFC_MAG; 2083 2084 /* now that we have the eeprom settings, apply the special cases where 2085 * the eeprom may be wrong or the board simply won't support wake on 2086 * lan on a particular port */ 2087 switch (pdev->device) { 2088 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2089 adapter->eeprom_wol = 0; 2090 break; 2091 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2092 case E1000_DEV_ID_82576_FIBER: 2093 case E1000_DEV_ID_82576_SERDES: 2094 /* Wake events only supported on port A for dual fiber 2095 * regardless of eeprom setting */ 2096 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2097 adapter->eeprom_wol = 0; 2098 break; 2099 case E1000_DEV_ID_82576_QUAD_COPPER: 2100 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2101 /* if quad port adapter, disable WoL on all but port A */ 2102 if (global_quad_port_a != 0) 2103 adapter->eeprom_wol = 0; 2104 else 2105 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2106 /* Reset for multiple quad port adapters */ 2107 if (++global_quad_port_a == 4) 2108 global_quad_port_a = 0; 2109 break; 2110 } 2111 2112 /* initialize the wol settings based on the eeprom settings */ 2113 adapter->wol = adapter->eeprom_wol; 2114 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol); 2115 2116 /* reset the hardware with the new settings */ 2117 igb_reset(adapter); 2118 2119 /* let the f/w know that the h/w is now under the control of the 2120 * driver. */ 2121 igb_get_hw_control(adapter); 2122 2123 strcpy(netdev->name, "eth%d"); 2124 err = register_netdev(netdev); 2125 if (err) 2126 goto err_register; 2127 2128 /* carrier off reporting is important to ethtool even BEFORE open */ 2129 netif_carrier_off(netdev); 2130 2131#ifdef CONFIG_IGB_DCA 2132 if (dca_add_requester(&pdev->dev) == 0) { 2133 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2134 dev_info(&pdev->dev, "DCA enabled\n"); 2135 igb_setup_dca(adapter); 2136 } 2137 2138#endif 2139 2140#ifdef CONFIG_IGB_PTP 2141 /* do hw tstamp init after resetting */ 2142 igb_ptp_init(adapter); 2143#endif /* CONFIG_IGB_PTP */ 2144 2145 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2146 /* print bus type/speed/width info */ 2147 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2148 netdev->name, 2149 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2150 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2151 "unknown"), 2152 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" : 2153 (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" : 2154 (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" : 2155 "unknown"), 2156 netdev->dev_addr); 2157 2158 ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH); 2159 if (ret_val) 2160 strcpy(part_str, "Unknown"); 2161 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2162 dev_info(&pdev->dev, 2163 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2164 adapter->msix_entries ? "MSI-X" : 2165 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2166 adapter->num_rx_queues, adapter->num_tx_queues); 2167 switch (hw->mac.type) { 2168 case e1000_i350: 2169 case e1000_i210: 2170 case e1000_i211: 2171 igb_set_eee_i350(hw); 2172 break; 2173 default: 2174 break; 2175 } 2176 2177 pm_runtime_put_noidle(&pdev->dev); 2178 return 0; 2179 2180err_register: 2181 igb_release_hw_control(adapter); 2182err_eeprom: 2183 if (!igb_check_reset_block(hw)) 2184 igb_reset_phy(hw); 2185 2186 if (hw->flash_address) 2187 iounmap(hw->flash_address); 2188err_sw_init: 2189 igb_clear_interrupt_scheme(adapter); 2190 iounmap(hw->hw_addr); 2191err_ioremap: 2192 free_netdev(netdev); 2193err_alloc_etherdev: 2194 pci_release_selected_regions(pdev, 2195 pci_select_bars(pdev, IORESOURCE_MEM)); 2196err_pci_reg: 2197err_dma: 2198 pci_disable_device(pdev); 2199 return err; 2200} 2201 2202/** 2203 * igb_remove - Device Removal Routine 2204 * @pdev: PCI device information struct 2205 * 2206 * igb_remove is called by the PCI subsystem to alert the driver 2207 * that it should release a PCI device. The could be caused by a 2208 * Hot-Plug event, or because the driver is going to be removed from 2209 * memory. 2210 **/ 2211static void __devexit igb_remove(struct pci_dev *pdev) 2212{ 2213 struct net_device *netdev = pci_get_drvdata(pdev); 2214 struct igb_adapter *adapter = netdev_priv(netdev); 2215 struct e1000_hw *hw = &adapter->hw; 2216 2217 pm_runtime_get_noresume(&pdev->dev); 2218#ifdef CONFIG_IGB_PTP 2219 igb_ptp_stop(adapter); 2220#endif /* CONFIG_IGB_PTP */ 2221 2222 /* 2223 * The watchdog timer may be rescheduled, so explicitly 2224 * disable watchdog from being rescheduled. 2225 */ 2226 set_bit(__IGB_DOWN, &adapter->state); 2227 del_timer_sync(&adapter->watchdog_timer); 2228 del_timer_sync(&adapter->phy_info_timer); 2229 2230 cancel_work_sync(&adapter->reset_task); 2231 cancel_work_sync(&adapter->watchdog_task); 2232 2233#ifdef CONFIG_IGB_DCA 2234 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2235 dev_info(&pdev->dev, "DCA disabled\n"); 2236 dca_remove_requester(&pdev->dev); 2237 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2238 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2239 } 2240#endif 2241 2242 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2243 * would have already happened in close and is redundant. */ 2244 igb_release_hw_control(adapter); 2245 2246 unregister_netdev(netdev); 2247 2248 igb_clear_interrupt_scheme(adapter); 2249 2250#ifdef CONFIG_PCI_IOV 2251 /* reclaim resources allocated to VFs */ 2252 if (adapter->vf_data) { 2253 /* disable iov and allow time for transactions to clear */ 2254 if (igb_vfs_are_assigned(adapter)) { 2255 dev_info(&pdev->dev, "Unloading driver while VFs are assigned - VFs will not be deallocated\n"); 2256 } else { 2257 pci_disable_sriov(pdev); 2258 msleep(500); 2259 } 2260 2261 kfree(adapter->vf_data); 2262 adapter->vf_data = NULL; 2263 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2264 wrfl(); 2265 msleep(100); 2266 dev_info(&pdev->dev, "IOV Disabled\n"); 2267 } 2268#endif 2269 2270 iounmap(hw->hw_addr); 2271 if (hw->flash_address) 2272 iounmap(hw->flash_address); 2273 pci_release_selected_regions(pdev, 2274 pci_select_bars(pdev, IORESOURCE_MEM)); 2275 2276 kfree(adapter->shadow_vfta); 2277 free_netdev(netdev); 2278 2279 pci_disable_pcie_error_reporting(pdev); 2280 2281 pci_disable_device(pdev); 2282} 2283 2284/** 2285 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2286 * @adapter: board private structure to initialize 2287 * 2288 * This function initializes the vf specific data storage and then attempts to 2289 * allocate the VFs. The reason for ordering it this way is because it is much 2290 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2291 * the memory for the VFs. 2292 **/ 2293static void __devinit igb_probe_vfs(struct igb_adapter * adapter) 2294{ 2295#ifdef CONFIG_PCI_IOV 2296 struct pci_dev *pdev = adapter->pdev; 2297 struct e1000_hw *hw = &adapter->hw; 2298 int old_vfs = pci_num_vf(adapter->pdev); 2299 int i; 2300 2301 /* Virtualization features not supported on i210 family. */ 2302 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2303 return; 2304 2305 if (old_vfs) { 2306 dev_info(&pdev->dev, "%d pre-allocated VFs found - override " 2307 "max_vfs setting of %d\n", old_vfs, max_vfs); 2308 adapter->vfs_allocated_count = old_vfs; 2309 } 2310 2311 if (!adapter->vfs_allocated_count) 2312 return; 2313 2314 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2315 sizeof(struct vf_data_storage), GFP_KERNEL); 2316 2317 /* if allocation failed then we do not support SR-IOV */ 2318 if (!adapter->vf_data) { 2319 adapter->vfs_allocated_count = 0; 2320 dev_err(&pdev->dev, "Unable to allocate memory for VF " 2321 "Data Storage\n"); 2322 goto out; 2323 } 2324 2325 if (!old_vfs) { 2326 if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) 2327 goto err_out; 2328 } 2329 dev_info(&pdev->dev, "%d VFs allocated\n", 2330 adapter->vfs_allocated_count); 2331 for (i = 0; i < adapter->vfs_allocated_count; i++) 2332 igb_vf_configure(adapter, i); 2333 2334 /* DMA Coalescing is not supported in IOV mode. */ 2335 adapter->flags &= ~IGB_FLAG_DMAC; 2336 goto out; 2337err_out: 2338 kfree(adapter->vf_data); 2339 adapter->vf_data = NULL; 2340 adapter->vfs_allocated_count = 0; 2341out: 2342 return; 2343#endif /* CONFIG_PCI_IOV */ 2344} 2345 2346/** 2347 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2348 * @adapter: board private structure to initialize 2349 * 2350 * igb_sw_init initializes the Adapter private data structure. 2351 * Fields are initialized based on PCI device information and 2352 * OS network device settings (MTU size). 2353 **/ 2354static int __devinit igb_sw_init(struct igb_adapter *adapter) 2355{ 2356 struct e1000_hw *hw = &adapter->hw; 2357 struct net_device *netdev = adapter->netdev; 2358 struct pci_dev *pdev = adapter->pdev; 2359 u32 max_rss_queues; 2360 2361 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2362 2363 /* set default ring sizes */ 2364 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2365 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2366 2367 /* set default ITR values */ 2368 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2369 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2370 2371 /* set default work limits */ 2372 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2373 2374 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2375 VLAN_HLEN; 2376 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2377 2378 spin_lock_init(&adapter->stats64_lock); 2379#ifdef CONFIG_PCI_IOV 2380 switch (hw->mac.type) { 2381 case e1000_82576: 2382 case e1000_i350: 2383 if (max_vfs > 7) { 2384 dev_warn(&pdev->dev, 2385 "Maximum of 7 VFs per PF, using max\n"); 2386 adapter->vfs_allocated_count = 7; 2387 } else 2388 adapter->vfs_allocated_count = max_vfs; 2389 break; 2390 default: 2391 break; 2392 } 2393#endif /* CONFIG_PCI_IOV */ 2394 2395 /* Determine the maximum number of RSS queues supported. */ 2396 switch (hw->mac.type) { 2397 case e1000_i211: 2398 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2399 break; 2400 case e1000_82575: 2401 case e1000_i210: 2402 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2403 break; 2404 case e1000_i350: 2405 /* I350 cannot do RSS and SR-IOV at the same time */ 2406 if (!!adapter->vfs_allocated_count) { 2407 max_rss_queues = 1; 2408 break; 2409 } 2410 /* fall through */ 2411 case e1000_82576: 2412 if (!!adapter->vfs_allocated_count) { 2413 max_rss_queues = 2; 2414 break; 2415 } 2416 /* fall through */ 2417 case e1000_82580: 2418 default: 2419 max_rss_queues = IGB_MAX_RX_QUEUES; 2420 break; 2421 } 2422 2423 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2424 2425 /* Determine if we need to pair queues. */ 2426 switch (hw->mac.type) { 2427 case e1000_82575: 2428 case e1000_i211: 2429 /* Device supports enough interrupts without queue pairing. */ 2430 break; 2431 case e1000_82576: 2432 /* 2433 * If VFs are going to be allocated with RSS queues then we 2434 * should pair the queues in order to conserve interrupts due 2435 * to limited supply. 2436 */ 2437 if ((adapter->rss_queues > 1) && 2438 (adapter->vfs_allocated_count > 6)) 2439 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2440 /* fall through */ 2441 case e1000_82580: 2442 case e1000_i350: 2443 case e1000_i210: 2444 default: 2445 /* 2446 * If rss_queues > half of max_rss_queues, pair the queues in 2447 * order to conserve interrupts due to limited supply. 2448 */ 2449 if (adapter->rss_queues > (max_rss_queues / 2)) 2450 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2451 break; 2452 } 2453 2454 /* Setup and initialize a copy of the hw vlan table array */ 2455 adapter->shadow_vfta = kzalloc(sizeof(u32) * 2456 E1000_VLAN_FILTER_TBL_SIZE, 2457 GFP_ATOMIC); 2458 2459 /* This call may decrease the number of queues */ 2460 if (igb_init_interrupt_scheme(adapter)) { 2461 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2462 return -ENOMEM; 2463 } 2464 2465 igb_probe_vfs(adapter); 2466 2467 /* Explicitly disable IRQ since the NIC can be in any state. */ 2468 igb_irq_disable(adapter); 2469 2470 if (hw->mac.type >= e1000_i350) 2471 adapter->flags &= ~IGB_FLAG_DMAC; 2472 2473 set_bit(__IGB_DOWN, &adapter->state); 2474 return 0; 2475} 2476 2477/** 2478 * igb_open - Called when a network interface is made active 2479 * @netdev: network interface device structure 2480 * 2481 * Returns 0 on success, negative value on failure 2482 * 2483 * The open entry point is called when a network interface is made 2484 * active by the system (IFF_UP). At this point all resources needed 2485 * for transmit and receive operations are allocated, the interrupt 2486 * handler is registered with the OS, the watchdog timer is started, 2487 * and the stack is notified that the interface is ready. 2488 **/ 2489static int __igb_open(struct net_device *netdev, bool resuming) 2490{ 2491 struct igb_adapter *adapter = netdev_priv(netdev); 2492 struct e1000_hw *hw = &adapter->hw; 2493 struct pci_dev *pdev = adapter->pdev; 2494 int err; 2495 int i; 2496 2497 /* disallow open during test */ 2498 if (test_bit(__IGB_TESTING, &adapter->state)) { 2499 WARN_ON(resuming); 2500 return -EBUSY; 2501 } 2502 2503 if (!resuming) 2504 pm_runtime_get_sync(&pdev->dev); 2505 2506 netif_carrier_off(netdev); 2507 2508 /* allocate transmit descriptors */ 2509 err = igb_setup_all_tx_resources(adapter); 2510 if (err) 2511 goto err_setup_tx; 2512 2513 /* allocate receive descriptors */ 2514 err = igb_setup_all_rx_resources(adapter); 2515 if (err) 2516 goto err_setup_rx; 2517 2518 igb_power_up_link(adapter); 2519 2520 /* before we allocate an interrupt, we must be ready to handle it. 2521 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 2522 * as soon as we call pci_request_irq, so we have to setup our 2523 * clean_rx handler before we do so. */ 2524 igb_configure(adapter); 2525 2526 err = igb_request_irq(adapter); 2527 if (err) 2528 goto err_req_irq; 2529 2530 /* From here on the code is the same as igb_up() */ 2531 clear_bit(__IGB_DOWN, &adapter->state); 2532 2533 for (i = 0; i < adapter->num_q_vectors; i++) 2534 napi_enable(&(adapter->q_vector[i]->napi)); 2535 2536 /* Clear any pending interrupts. */ 2537 rd32(E1000_ICR); 2538 2539 igb_irq_enable(adapter); 2540 2541 /* notify VFs that reset has been completed */ 2542 if (adapter->vfs_allocated_count) { 2543 u32 reg_data = rd32(E1000_CTRL_EXT); 2544 reg_data |= E1000_CTRL_EXT_PFRSTD; 2545 wr32(E1000_CTRL_EXT, reg_data); 2546 } 2547 2548 netif_tx_start_all_queues(netdev); 2549 2550 if (!resuming) 2551 pm_runtime_put(&pdev->dev); 2552 2553 /* start the watchdog. */ 2554 hw->mac.get_link_status = 1; 2555 schedule_work(&adapter->watchdog_task); 2556 2557 return 0; 2558 2559err_req_irq: 2560 igb_release_hw_control(adapter); 2561 igb_power_down_link(adapter); 2562 igb_free_all_rx_resources(adapter); 2563err_setup_rx: 2564 igb_free_all_tx_resources(adapter); 2565err_setup_tx: 2566 igb_reset(adapter); 2567 if (!resuming) 2568 pm_runtime_put(&pdev->dev); 2569 2570 return err; 2571} 2572 2573static int igb_open(struct net_device *netdev) 2574{ 2575 return __igb_open(netdev, false); 2576} 2577 2578/** 2579 * igb_close - Disables a network interface 2580 * @netdev: network interface device structure 2581 * 2582 * Returns 0, this is not allowed to fail 2583 * 2584 * The close entry point is called when an interface is de-activated 2585 * by the OS. The hardware is still under the driver's control, but 2586 * needs to be disabled. A global MAC reset is issued to stop the 2587 * hardware, and all transmit and receive resources are freed. 2588 **/ 2589static int __igb_close(struct net_device *netdev, bool suspending) 2590{ 2591 struct igb_adapter *adapter = netdev_priv(netdev); 2592 struct pci_dev *pdev = adapter->pdev; 2593 2594 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 2595 2596 if (!suspending) 2597 pm_runtime_get_sync(&pdev->dev); 2598 2599 igb_down(adapter); 2600 igb_free_irq(adapter); 2601 2602 igb_free_all_tx_resources(adapter); 2603 igb_free_all_rx_resources(adapter); 2604 2605 if (!suspending) 2606 pm_runtime_put_sync(&pdev->dev); 2607 return 0; 2608} 2609 2610static int igb_close(struct net_device *netdev) 2611{ 2612 return __igb_close(netdev, false); 2613} 2614 2615/** 2616 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 2617 * @tx_ring: tx descriptor ring (for a specific queue) to setup 2618 * 2619 * Return 0 on success, negative on failure 2620 **/ 2621int igb_setup_tx_resources(struct igb_ring *tx_ring) 2622{ 2623 struct device *dev = tx_ring->dev; 2624 int size; 2625 2626 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 2627 2628 tx_ring->tx_buffer_info = vzalloc(size); 2629 if (!tx_ring->tx_buffer_info) 2630 goto err; 2631 2632 /* round up to nearest 4K */ 2633 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 2634 tx_ring->size = ALIGN(tx_ring->size, 4096); 2635 2636 tx_ring->desc = dma_alloc_coherent(dev, 2637 tx_ring->size, 2638 &tx_ring->dma, 2639 GFP_KERNEL); 2640 if (!tx_ring->desc) 2641 goto err; 2642 2643 tx_ring->next_to_use = 0; 2644 tx_ring->next_to_clean = 0; 2645 2646 return 0; 2647 2648err: 2649 vfree(tx_ring->tx_buffer_info); 2650 tx_ring->tx_buffer_info = NULL; 2651 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 2652 return -ENOMEM; 2653} 2654 2655/** 2656 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 2657 * (Descriptors) for all queues 2658 * @adapter: board private structure 2659 * 2660 * Return 0 on success, negative on failure 2661 **/ 2662static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 2663{ 2664 struct pci_dev *pdev = adapter->pdev; 2665 int i, err = 0; 2666 2667 for (i = 0; i < adapter->num_tx_queues; i++) { 2668 err = igb_setup_tx_resources(adapter->tx_ring[i]); 2669 if (err) { 2670 dev_err(&pdev->dev, 2671 "Allocation for Tx Queue %u failed\n", i); 2672 for (i--; i >= 0; i--) 2673 igb_free_tx_resources(adapter->tx_ring[i]); 2674 break; 2675 } 2676 } 2677 2678 return err; 2679} 2680 2681/** 2682 * igb_setup_tctl - configure the transmit control registers 2683 * @adapter: Board private structure 2684 **/ 2685void igb_setup_tctl(struct igb_adapter *adapter) 2686{ 2687 struct e1000_hw *hw = &adapter->hw; 2688 u32 tctl; 2689 2690 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 2691 wr32(E1000_TXDCTL(0), 0); 2692 2693 /* Program the Transmit Control Register */ 2694 tctl = rd32(E1000_TCTL); 2695 tctl &= ~E1000_TCTL_CT; 2696 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 2697 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 2698 2699 igb_config_collision_dist(hw); 2700 2701 /* Enable transmits */ 2702 tctl |= E1000_TCTL_EN; 2703 2704 wr32(E1000_TCTL, tctl); 2705} 2706 2707/** 2708 * igb_configure_tx_ring - Configure transmit ring after Reset 2709 * @adapter: board private structure 2710 * @ring: tx ring to configure 2711 * 2712 * Configure a transmit ring after a reset. 2713 **/ 2714void igb_configure_tx_ring(struct igb_adapter *adapter, 2715 struct igb_ring *ring) 2716{ 2717 struct e1000_hw *hw = &adapter->hw; 2718 u32 txdctl = 0; 2719 u64 tdba = ring->dma; 2720 int reg_idx = ring->reg_idx; 2721 2722 /* disable the queue */ 2723 wr32(E1000_TXDCTL(reg_idx), 0); 2724 wrfl(); 2725 mdelay(10); 2726 2727 wr32(E1000_TDLEN(reg_idx), 2728 ring->count * sizeof(union e1000_adv_tx_desc)); 2729 wr32(E1000_TDBAL(reg_idx), 2730 tdba & 0x00000000ffffffffULL); 2731 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 2732 2733 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 2734 wr32(E1000_TDH(reg_idx), 0); 2735 writel(0, ring->tail); 2736 2737 txdctl |= IGB_TX_PTHRESH; 2738 txdctl |= IGB_TX_HTHRESH << 8; 2739 txdctl |= IGB_TX_WTHRESH << 16; 2740 2741 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 2742 wr32(E1000_TXDCTL(reg_idx), txdctl); 2743} 2744 2745/** 2746 * igb_configure_tx - Configure transmit Unit after Reset 2747 * @adapter: board private structure 2748 * 2749 * Configure the Tx unit of the MAC after a reset. 2750 **/ 2751static void igb_configure_tx(struct igb_adapter *adapter) 2752{ 2753 int i; 2754 2755 for (i = 0; i < adapter->num_tx_queues; i++) 2756 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 2757} 2758 2759/** 2760 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 2761 * @rx_ring: rx descriptor ring (for a specific queue) to setup 2762 * 2763 * Returns 0 on success, negative on failure 2764 **/ 2765int igb_setup_rx_resources(struct igb_ring *rx_ring) 2766{ 2767 struct device *dev = rx_ring->dev; 2768 int size; 2769 2770 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 2771 2772 rx_ring->rx_buffer_info = vzalloc(size); 2773 if (!rx_ring->rx_buffer_info) 2774 goto err; 2775 2776 2777 /* Round up to nearest 4K */ 2778 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 2779 rx_ring->size = ALIGN(rx_ring->size, 4096); 2780 2781 rx_ring->desc = dma_alloc_coherent(dev, 2782 rx_ring->size, 2783 &rx_ring->dma, 2784 GFP_KERNEL); 2785 if (!rx_ring->desc) 2786 goto err; 2787 2788 rx_ring->next_to_alloc = 0; 2789 rx_ring->next_to_clean = 0; 2790 rx_ring->next_to_use = 0; 2791 2792 return 0; 2793 2794err: 2795 vfree(rx_ring->rx_buffer_info); 2796 rx_ring->rx_buffer_info = NULL; 2797 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 2798 return -ENOMEM; 2799} 2800 2801/** 2802 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 2803 * (Descriptors) for all queues 2804 * @adapter: board private structure 2805 * 2806 * Return 0 on success, negative on failure 2807 **/ 2808static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 2809{ 2810 struct pci_dev *pdev = adapter->pdev; 2811 int i, err = 0; 2812 2813 for (i = 0; i < adapter->num_rx_queues; i++) { 2814 err = igb_setup_rx_resources(adapter->rx_ring[i]); 2815 if (err) { 2816 dev_err(&pdev->dev, 2817 "Allocation for Rx Queue %u failed\n", i); 2818 for (i--; i >= 0; i--) 2819 igb_free_rx_resources(adapter->rx_ring[i]); 2820 break; 2821 } 2822 } 2823 2824 return err; 2825} 2826 2827/** 2828 * igb_setup_mrqc - configure the multiple receive queue control registers 2829 * @adapter: Board private structure 2830 **/ 2831static void igb_setup_mrqc(struct igb_adapter *adapter) 2832{ 2833 struct e1000_hw *hw = &adapter->hw; 2834 u32 mrqc, rxcsum; 2835 u32 j, num_rx_queues, shift = 0; 2836 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, 2837 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, 2838 0xA32DCB77, 0x0CF23080, 0x3BB7426A, 2839 0xFA01ACBE }; 2840 2841 /* Fill out hash function seeds */ 2842 for (j = 0; j < 10; j++) 2843 wr32(E1000_RSSRK(j), rsskey[j]); 2844 2845 num_rx_queues = adapter->rss_queues; 2846 2847 switch (hw->mac.type) { 2848 case e1000_82575: 2849 shift = 6; 2850 break; 2851 case e1000_82576: 2852 /* 82576 supports 2 RSS queues for SR-IOV */ 2853 if (adapter->vfs_allocated_count) { 2854 shift = 3; 2855 num_rx_queues = 2; 2856 } 2857 break; 2858 default: 2859 break; 2860 } 2861 2862 /* 2863 * Populate the indirection table 4 entries at a time. To do this 2864 * we are generating the results for n and n+2 and then interleaving 2865 * those with the results with n+1 and n+3. 2866 */ 2867 for (j = 0; j < 32; j++) { 2868 /* first pass generates n and n+2 */ 2869 u32 base = ((j * 0x00040004) + 0x00020000) * num_rx_queues; 2870 u32 reta = (base & 0x07800780) >> (7 - shift); 2871 2872 /* second pass generates n+1 and n+3 */ 2873 base += 0x00010001 * num_rx_queues; 2874 reta |= (base & 0x07800780) << (1 + shift); 2875 2876 wr32(E1000_RETA(j), reta); 2877 } 2878 2879 /* 2880 * Disable raw packet checksumming so that RSS hash is placed in 2881 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 2882 * offloads as they are enabled by default 2883 */ 2884 rxcsum = rd32(E1000_RXCSUM); 2885 rxcsum |= E1000_RXCSUM_PCSD; 2886 2887 if (adapter->hw.mac.type >= e1000_82576) 2888 /* Enable Receive Checksum Offload for SCTP */ 2889 rxcsum |= E1000_RXCSUM_CRCOFL; 2890 2891 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 2892 wr32(E1000_RXCSUM, rxcsum); 2893 /* 2894 * Generate RSS hash based on TCP port numbers and/or 2895 * IPv4/v6 src and dst addresses since UDP cannot be 2896 * hashed reliably due to IP fragmentation 2897 */ 2898 2899 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 2900 E1000_MRQC_RSS_FIELD_IPV4_TCP | 2901 E1000_MRQC_RSS_FIELD_IPV6 | 2902 E1000_MRQC_RSS_FIELD_IPV6_TCP | 2903 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 2904 2905 /* If VMDq is enabled then we set the appropriate mode for that, else 2906 * we default to RSS so that an RSS hash is calculated per packet even 2907 * if we are only using one queue */ 2908 if (adapter->vfs_allocated_count) { 2909 if (hw->mac.type > e1000_82575) { 2910 /* Set the default pool for the PF's first queue */ 2911 u32 vtctl = rd32(E1000_VT_CTL); 2912 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 2913 E1000_VT_CTL_DISABLE_DEF_POOL); 2914 vtctl |= adapter->vfs_allocated_count << 2915 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 2916 wr32(E1000_VT_CTL, vtctl); 2917 } 2918 if (adapter->rss_queues > 1) 2919 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 2920 else 2921 mrqc |= E1000_MRQC_ENABLE_VMDQ; 2922 } else { 2923 if (hw->mac.type != e1000_i211) 2924 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 2925 } 2926 igb_vmm_control(adapter); 2927 2928 wr32(E1000_MRQC, mrqc); 2929} 2930 2931/** 2932 * igb_setup_rctl - configure the receive control registers 2933 * @adapter: Board private structure 2934 **/ 2935void igb_setup_rctl(struct igb_adapter *adapter) 2936{ 2937 struct e1000_hw *hw = &adapter->hw; 2938 u32 rctl; 2939 2940 rctl = rd32(E1000_RCTL); 2941 2942 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 2943 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 2944 2945 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 2946 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 2947 2948 /* 2949 * enable stripping of CRC. It's unlikely this will break BMC 2950 * redirection as it did with e1000. Newer features require 2951 * that the HW strips the CRC. 2952 */ 2953 rctl |= E1000_RCTL_SECRC; 2954 2955 /* disable store bad packets and clear size bits. */ 2956 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 2957 2958 /* enable LPE to prevent packets larger than max_frame_size */ 2959 rctl |= E1000_RCTL_LPE; 2960 2961 /* disable queue 0 to prevent tail write w/o re-config */ 2962 wr32(E1000_RXDCTL(0), 0); 2963 2964 /* Attention!!! For SR-IOV PF driver operations you must enable 2965 * queue drop for all VF and PF queues to prevent head of line blocking 2966 * if an un-trusted VF does not provide descriptors to hardware. 2967 */ 2968 if (adapter->vfs_allocated_count) { 2969 /* set all queue drop enable bits */ 2970 wr32(E1000_QDE, ALL_QUEUES); 2971 } 2972 2973 /* This is useful for sniffing bad packets. */ 2974 if (adapter->netdev->features & NETIF_F_RXALL) { 2975 /* UPE and MPE will be handled by normal PROMISC logic 2976 * in e1000e_set_rx_mode */ 2977 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 2978 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 2979 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 2980 2981 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 2982 E1000_RCTL_DPF | /* Allow filtered pause */ 2983 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 2984 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 2985 * and that breaks VLANs. 2986 */ 2987 } 2988 2989 wr32(E1000_RCTL, rctl); 2990} 2991 2992static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 2993 int vfn) 2994{ 2995 struct e1000_hw *hw = &adapter->hw; 2996 u32 vmolr; 2997 2998 /* if it isn't the PF check to see if VFs are enabled and 2999 * increase the size to support vlan tags */ 3000 if (vfn < adapter->vfs_allocated_count && 3001 adapter->vf_data[vfn].vlans_enabled) 3002 size += VLAN_TAG_SIZE; 3003 3004 vmolr = rd32(E1000_VMOLR(vfn)); 3005 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3006 vmolr |= size | E1000_VMOLR_LPE; 3007 wr32(E1000_VMOLR(vfn), vmolr); 3008 3009 return 0; 3010} 3011 3012/** 3013 * igb_rlpml_set - set maximum receive packet size 3014 * @adapter: board private structure 3015 * 3016 * Configure maximum receivable packet size. 3017 **/ 3018static void igb_rlpml_set(struct igb_adapter *adapter) 3019{ 3020 u32 max_frame_size = adapter->max_frame_size; 3021 struct e1000_hw *hw = &adapter->hw; 3022 u16 pf_id = adapter->vfs_allocated_count; 3023 3024 if (pf_id) { 3025 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3026 /* 3027 * If we're in VMDQ or SR-IOV mode, then set global RLPML 3028 * to our max jumbo frame size, in case we need to enable 3029 * jumbo frames on one of the rings later. 3030 * This will not pass over-length frames into the default 3031 * queue because it's gated by the VMOLR.RLPML. 3032 */ 3033 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3034 } 3035 3036 wr32(E1000_RLPML, max_frame_size); 3037} 3038 3039static inline void igb_set_vmolr(struct igb_adapter *adapter, 3040 int vfn, bool aupe) 3041{ 3042 struct e1000_hw *hw = &adapter->hw; 3043 u32 vmolr; 3044 3045 /* 3046 * This register exists only on 82576 and newer so if we are older then 3047 * we should exit and do nothing 3048 */ 3049 if (hw->mac.type < e1000_82576) 3050 return; 3051 3052 vmolr = rd32(E1000_VMOLR(vfn)); 3053 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3054 if (aupe) 3055 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3056 else 3057 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3058 3059 /* clear all bits that might not be set */ 3060 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3061 3062 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3063 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3064 /* 3065 * for VMDq only allow the VFs and pool 0 to accept broadcast and 3066 * multicast packets 3067 */ 3068 if (vfn <= adapter->vfs_allocated_count) 3069 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3070 3071 wr32(E1000_VMOLR(vfn), vmolr); 3072} 3073 3074/** 3075 * igb_configure_rx_ring - Configure a receive ring after Reset 3076 * @adapter: board private structure 3077 * @ring: receive ring to be configured 3078 * 3079 * Configure the Rx unit of the MAC after a reset. 3080 **/ 3081void igb_configure_rx_ring(struct igb_adapter *adapter, 3082 struct igb_ring *ring) 3083{ 3084 struct e1000_hw *hw = &adapter->hw; 3085 u64 rdba = ring->dma; 3086 int reg_idx = ring->reg_idx; 3087 u32 srrctl = 0, rxdctl = 0; 3088 3089 /* disable the queue */ 3090 wr32(E1000_RXDCTL(reg_idx), 0); 3091 3092 /* Set DMA base address registers */ 3093 wr32(E1000_RDBAL(reg_idx), 3094 rdba & 0x00000000ffffffffULL); 3095 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3096 wr32(E1000_RDLEN(reg_idx), 3097 ring->count * sizeof(union e1000_adv_rx_desc)); 3098 3099 /* initialize head and tail */ 3100 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3101 wr32(E1000_RDH(reg_idx), 0); 3102 writel(0, ring->tail); 3103 3104 /* set descriptor configuration */ 3105 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3106#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384 3107 srrctl |= IGB_RXBUFFER_16384 >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3108#else 3109 srrctl |= (PAGE_SIZE / 2) >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3110#endif 3111 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3112#ifdef CONFIG_IGB_PTP 3113 if (hw->mac.type >= e1000_82580) 3114 srrctl |= E1000_SRRCTL_TIMESTAMP; 3115#endif /* CONFIG_IGB_PTP */ 3116 /* Only set Drop Enable if we are supporting multiple queues */ 3117 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3118 srrctl |= E1000_SRRCTL_DROP_EN; 3119 3120 wr32(E1000_SRRCTL(reg_idx), srrctl); 3121 3122 /* set filtering for VMDQ pools */ 3123 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3124 3125 rxdctl |= IGB_RX_PTHRESH; 3126 rxdctl |= IGB_RX_HTHRESH << 8; 3127 rxdctl |= IGB_RX_WTHRESH << 16; 3128 3129 /* enable receive descriptor fetching */ 3130 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3131 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3132} 3133 3134/** 3135 * igb_configure_rx - Configure receive Unit after Reset 3136 * @adapter: board private structure 3137 * 3138 * Configure the Rx unit of the MAC after a reset. 3139 **/ 3140static void igb_configure_rx(struct igb_adapter *adapter) 3141{ 3142 int i; 3143 3144 /* set UTA to appropriate mode */ 3145 igb_set_uta(adapter); 3146 3147 /* set the correct pool for the PF default MAC address in entry 0 */ 3148 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3149 adapter->vfs_allocated_count); 3150 3151 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3152 * the Base and Length of the Rx Descriptor Ring */ 3153 for (i = 0; i < adapter->num_rx_queues; i++) 3154 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3155} 3156 3157/** 3158 * igb_free_tx_resources - Free Tx Resources per Queue 3159 * @tx_ring: Tx descriptor ring for a specific queue 3160 * 3161 * Free all transmit software resources 3162 **/ 3163void igb_free_tx_resources(struct igb_ring *tx_ring) 3164{ 3165 igb_clean_tx_ring(tx_ring); 3166 3167 vfree(tx_ring->tx_buffer_info); 3168 tx_ring->tx_buffer_info = NULL; 3169 3170 /* if not set, then don't free */ 3171 if (!tx_ring->desc) 3172 return; 3173 3174 dma_free_coherent(tx_ring->dev, tx_ring->size, 3175 tx_ring->desc, tx_ring->dma); 3176 3177 tx_ring->desc = NULL; 3178} 3179 3180/** 3181 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3182 * @adapter: board private structure 3183 * 3184 * Free all transmit software resources 3185 **/ 3186static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3187{ 3188 int i; 3189 3190 for (i = 0; i < adapter->num_tx_queues; i++) 3191 igb_free_tx_resources(adapter->tx_ring[i]); 3192} 3193 3194void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3195 struct igb_tx_buffer *tx_buffer) 3196{ 3197 if (tx_buffer->skb) { 3198 dev_kfree_skb_any(tx_buffer->skb); 3199 if (dma_unmap_len(tx_buffer, len)) 3200 dma_unmap_single(ring->dev, 3201 dma_unmap_addr(tx_buffer, dma), 3202 dma_unmap_len(tx_buffer, len), 3203 DMA_TO_DEVICE); 3204 } else if (dma_unmap_len(tx_buffer, len)) { 3205 dma_unmap_page(ring->dev, 3206 dma_unmap_addr(tx_buffer, dma), 3207 dma_unmap_len(tx_buffer, len), 3208 DMA_TO_DEVICE); 3209 } 3210 tx_buffer->next_to_watch = NULL; 3211 tx_buffer->skb = NULL; 3212 dma_unmap_len_set(tx_buffer, len, 0); 3213 /* buffer_info must be completely set up in the transmit path */ 3214} 3215 3216/** 3217 * igb_clean_tx_ring - Free Tx Buffers 3218 * @tx_ring: ring to be cleaned 3219 **/ 3220static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3221{ 3222 struct igb_tx_buffer *buffer_info; 3223 unsigned long size; 3224 u16 i; 3225 3226 if (!tx_ring->tx_buffer_info) 3227 return; 3228 /* Free all the Tx ring sk_buffs */ 3229 3230 for (i = 0; i < tx_ring->count; i++) { 3231 buffer_info = &tx_ring->tx_buffer_info[i]; 3232 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3233 } 3234 3235 netdev_tx_reset_queue(txring_txq(tx_ring)); 3236 3237 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3238 memset(tx_ring->tx_buffer_info, 0, size); 3239 3240 /* Zero out the descriptor ring */ 3241 memset(tx_ring->desc, 0, tx_ring->size); 3242 3243 tx_ring->next_to_use = 0; 3244 tx_ring->next_to_clean = 0; 3245} 3246 3247/** 3248 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3249 * @adapter: board private structure 3250 **/ 3251static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3252{ 3253 int i; 3254 3255 for (i = 0; i < adapter->num_tx_queues; i++) 3256 igb_clean_tx_ring(adapter->tx_ring[i]); 3257} 3258 3259/** 3260 * igb_free_rx_resources - Free Rx Resources 3261 * @rx_ring: ring to clean the resources from 3262 * 3263 * Free all receive software resources 3264 **/ 3265void igb_free_rx_resources(struct igb_ring *rx_ring) 3266{ 3267 igb_clean_rx_ring(rx_ring); 3268 3269 vfree(rx_ring->rx_buffer_info); 3270 rx_ring->rx_buffer_info = NULL; 3271 3272 /* if not set, then don't free */ 3273 if (!rx_ring->desc) 3274 return; 3275 3276 dma_free_coherent(rx_ring->dev, rx_ring->size, 3277 rx_ring->desc, rx_ring->dma); 3278 3279 rx_ring->desc = NULL; 3280} 3281 3282/** 3283 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3284 * @adapter: board private structure 3285 * 3286 * Free all receive software resources 3287 **/ 3288static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3289{ 3290 int i; 3291 3292 for (i = 0; i < adapter->num_rx_queues; i++) 3293 igb_free_rx_resources(adapter->rx_ring[i]); 3294} 3295 3296/** 3297 * igb_clean_rx_ring - Free Rx Buffers per Queue 3298 * @rx_ring: ring to free buffers from 3299 **/ 3300static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3301{ 3302 unsigned long size; 3303 u16 i; 3304 3305 if (rx_ring->skb) 3306 dev_kfree_skb(rx_ring->skb); 3307 rx_ring->skb = NULL; 3308 3309 if (!rx_ring->rx_buffer_info) 3310 return; 3311 3312 /* Free all the Rx ring sk_buffs */ 3313 for (i = 0; i < rx_ring->count; i++) { 3314 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3315 3316 if (!buffer_info->page) 3317 continue; 3318 3319 dma_unmap_page(rx_ring->dev, 3320 buffer_info->dma, 3321 PAGE_SIZE, 3322 DMA_FROM_DEVICE); 3323 __free_page(buffer_info->page); 3324 3325 buffer_info->page = NULL; 3326 } 3327 3328 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3329 memset(rx_ring->rx_buffer_info, 0, size); 3330 3331 /* Zero out the descriptor ring */ 3332 memset(rx_ring->desc, 0, rx_ring->size); 3333 3334 rx_ring->next_to_alloc = 0; 3335 rx_ring->next_to_clean = 0; 3336 rx_ring->next_to_use = 0; 3337} 3338 3339/** 3340 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3341 * @adapter: board private structure 3342 **/ 3343static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3344{ 3345 int i; 3346 3347 for (i = 0; i < adapter->num_rx_queues; i++) 3348 igb_clean_rx_ring(adapter->rx_ring[i]); 3349} 3350 3351/** 3352 * igb_set_mac - Change the Ethernet Address of the NIC 3353 * @netdev: network interface device structure 3354 * @p: pointer to an address structure 3355 * 3356 * Returns 0 on success, negative on failure 3357 **/ 3358static int igb_set_mac(struct net_device *netdev, void *p) 3359{ 3360 struct igb_adapter *adapter = netdev_priv(netdev); 3361 struct e1000_hw *hw = &adapter->hw; 3362 struct sockaddr *addr = p; 3363 3364 if (!is_valid_ether_addr(addr->sa_data)) 3365 return -EADDRNOTAVAIL; 3366 3367 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3368 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3369 3370 /* set the correct pool for the new PF MAC address in entry 0 */ 3371 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3372 adapter->vfs_allocated_count); 3373 3374 return 0; 3375} 3376 3377/** 3378 * igb_write_mc_addr_list - write multicast addresses to MTA 3379 * @netdev: network interface device structure 3380 * 3381 * Writes multicast address list to the MTA hash table. 3382 * Returns: -ENOMEM on failure 3383 * 0 on no addresses written 3384 * X on writing X addresses to MTA 3385 **/ 3386static int igb_write_mc_addr_list(struct net_device *netdev) 3387{ 3388 struct igb_adapter *adapter = netdev_priv(netdev); 3389 struct e1000_hw *hw = &adapter->hw; 3390 struct netdev_hw_addr *ha; 3391 u8 *mta_list; 3392 int i; 3393 3394 if (netdev_mc_empty(netdev)) { 3395 /* nothing to program, so clear mc list */ 3396 igb_update_mc_addr_list(hw, NULL, 0); 3397 igb_restore_vf_multicasts(adapter); 3398 return 0; 3399 } 3400 3401 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3402 if (!mta_list) 3403 return -ENOMEM; 3404 3405 /* The shared function expects a packed array of only addresses. */ 3406 i = 0; 3407 netdev_for_each_mc_addr(ha, netdev) 3408 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3409 3410 igb_update_mc_addr_list(hw, mta_list, i); 3411 kfree(mta_list); 3412 3413 return netdev_mc_count(netdev); 3414} 3415 3416/** 3417 * igb_write_uc_addr_list - write unicast addresses to RAR table 3418 * @netdev: network interface device structure 3419 * 3420 * Writes unicast address list to the RAR table. 3421 * Returns: -ENOMEM on failure/insufficient address space 3422 * 0 on no addresses written 3423 * X on writing X addresses to the RAR table 3424 **/ 3425static int igb_write_uc_addr_list(struct net_device *netdev) 3426{ 3427 struct igb_adapter *adapter = netdev_priv(netdev); 3428 struct e1000_hw *hw = &adapter->hw; 3429 unsigned int vfn = adapter->vfs_allocated_count; 3430 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3431 int count = 0; 3432 3433 /* return ENOMEM indicating insufficient memory for addresses */ 3434 if (netdev_uc_count(netdev) > rar_entries) 3435 return -ENOMEM; 3436 3437 if (!netdev_uc_empty(netdev) && rar_entries) { 3438 struct netdev_hw_addr *ha; 3439 3440 netdev_for_each_uc_addr(ha, netdev) { 3441 if (!rar_entries) 3442 break; 3443 igb_rar_set_qsel(adapter, ha->addr, 3444 rar_entries--, 3445 vfn); 3446 count++; 3447 } 3448 } 3449 /* write the addresses in reverse order to avoid write combining */ 3450 for (; rar_entries > 0 ; rar_entries--) { 3451 wr32(E1000_RAH(rar_entries), 0); 3452 wr32(E1000_RAL(rar_entries), 0); 3453 } 3454 wrfl(); 3455 3456 return count; 3457} 3458 3459/** 3460 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3461 * @netdev: network interface device structure 3462 * 3463 * The set_rx_mode entry point is called whenever the unicast or multicast 3464 * address lists or the network interface flags are updated. This routine is 3465 * responsible for configuring the hardware for proper unicast, multicast, 3466 * promiscuous mode, and all-multi behavior. 3467 **/ 3468static void igb_set_rx_mode(struct net_device *netdev) 3469{ 3470 struct igb_adapter *adapter = netdev_priv(netdev); 3471 struct e1000_hw *hw = &adapter->hw; 3472 unsigned int vfn = adapter->vfs_allocated_count; 3473 u32 rctl, vmolr = 0; 3474 int count; 3475 3476 /* Check for Promiscuous and All Multicast modes */ 3477 rctl = rd32(E1000_RCTL); 3478 3479 /* clear the effected bits */ 3480 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 3481 3482 if (netdev->flags & IFF_PROMISC) { 3483 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 3484 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 3485 } else { 3486 if (netdev->flags & IFF_ALLMULTI) { 3487 rctl |= E1000_RCTL_MPE; 3488 vmolr |= E1000_VMOLR_MPME; 3489 } else { 3490 /* 3491 * Write addresses to the MTA, if the attempt fails 3492 * then we should just turn on promiscuous mode so 3493 * that we can at least receive multicast traffic 3494 */ 3495 count = igb_write_mc_addr_list(netdev); 3496 if (count < 0) { 3497 rctl |= E1000_RCTL_MPE; 3498 vmolr |= E1000_VMOLR_MPME; 3499 } else if (count) { 3500 vmolr |= E1000_VMOLR_ROMPE; 3501 } 3502 } 3503 /* 3504 * Write addresses to available RAR registers, if there is not 3505 * sufficient space to store all the addresses then enable 3506 * unicast promiscuous mode 3507 */ 3508 count = igb_write_uc_addr_list(netdev); 3509 if (count < 0) { 3510 rctl |= E1000_RCTL_UPE; 3511 vmolr |= E1000_VMOLR_ROPE; 3512 } 3513 rctl |= E1000_RCTL_VFE; 3514 } 3515 wr32(E1000_RCTL, rctl); 3516 3517 /* 3518 * In order to support SR-IOV and eventually VMDq it is necessary to set 3519 * the VMOLR to enable the appropriate modes. Without this workaround 3520 * we will have issues with VLAN tag stripping not being done for frames 3521 * that are only arriving because we are the default pool 3522 */ 3523 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 3524 return; 3525 3526 vmolr |= rd32(E1000_VMOLR(vfn)) & 3527 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 3528 wr32(E1000_VMOLR(vfn), vmolr); 3529 igb_restore_vf_multicasts(adapter); 3530} 3531 3532static void igb_check_wvbr(struct igb_adapter *adapter) 3533{ 3534 struct e1000_hw *hw = &adapter->hw; 3535 u32 wvbr = 0; 3536 3537 switch (hw->mac.type) { 3538 case e1000_82576: 3539 case e1000_i350: 3540 if (!(wvbr = rd32(E1000_WVBR))) 3541 return; 3542 break; 3543 default: 3544 break; 3545 } 3546 3547 adapter->wvbr |= wvbr; 3548} 3549 3550#define IGB_STAGGERED_QUEUE_OFFSET 8 3551 3552static void igb_spoof_check(struct igb_adapter *adapter) 3553{ 3554 int j; 3555 3556 if (!adapter->wvbr) 3557 return; 3558 3559 for(j = 0; j < adapter->vfs_allocated_count; j++) { 3560 if (adapter->wvbr & (1 << j) || 3561 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 3562 dev_warn(&adapter->pdev->dev, 3563 "Spoof event(s) detected on VF %d\n", j); 3564 adapter->wvbr &= 3565 ~((1 << j) | 3566 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 3567 } 3568 } 3569} 3570 3571/* Need to wait a few seconds after link up to get diagnostic information from 3572 * the phy */ 3573static void igb_update_phy_info(unsigned long data) 3574{ 3575 struct igb_adapter *adapter = (struct igb_adapter *) data; 3576 igb_get_phy_info(&adapter->hw); 3577} 3578 3579/** 3580 * igb_has_link - check shared code for link and determine up/down 3581 * @adapter: pointer to driver private info 3582 **/ 3583bool igb_has_link(struct igb_adapter *adapter) 3584{ 3585 struct e1000_hw *hw = &adapter->hw; 3586 bool link_active = false; 3587 s32 ret_val = 0; 3588 3589 /* get_link_status is set on LSC (link status) interrupt or 3590 * rx sequence error interrupt. get_link_status will stay 3591 * false until the e1000_check_for_link establishes link 3592 * for copper adapters ONLY 3593 */ 3594 switch (hw->phy.media_type) { 3595 case e1000_media_type_copper: 3596 if (hw->mac.get_link_status) { 3597 ret_val = hw->mac.ops.check_for_link(hw); 3598 link_active = !hw->mac.get_link_status; 3599 } else { 3600 link_active = true; 3601 } 3602 break; 3603 case e1000_media_type_internal_serdes: 3604 ret_val = hw->mac.ops.check_for_link(hw); 3605 link_active = hw->mac.serdes_has_link; 3606 break; 3607 default: 3608 case e1000_media_type_unknown: 3609 break; 3610 } 3611 3612 return link_active; 3613} 3614 3615static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 3616{ 3617 bool ret = false; 3618 u32 ctrl_ext, thstat; 3619 3620 /* check for thermal sensor event on i350 copper only */ 3621 if (hw->mac.type == e1000_i350) { 3622 thstat = rd32(E1000_THSTAT); 3623 ctrl_ext = rd32(E1000_CTRL_EXT); 3624 3625 if ((hw->phy.media_type == e1000_media_type_copper) && 3626 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) { 3627 ret = !!(thstat & event); 3628 } 3629 } 3630 3631 return ret; 3632} 3633 3634/** 3635 * igb_watchdog - Timer Call-back 3636 * @data: pointer to adapter cast into an unsigned long 3637 **/ 3638static void igb_watchdog(unsigned long data) 3639{ 3640 struct igb_adapter *adapter = (struct igb_adapter *)data; 3641 /* Do the rest outside of interrupt context */ 3642 schedule_work(&adapter->watchdog_task); 3643} 3644 3645static void igb_watchdog_task(struct work_struct *work) 3646{ 3647 struct igb_adapter *adapter = container_of(work, 3648 struct igb_adapter, 3649 watchdog_task); 3650 struct e1000_hw *hw = &adapter->hw; 3651 struct net_device *netdev = adapter->netdev; 3652 u32 link; 3653 int i; 3654 3655 link = igb_has_link(adapter); 3656 if (link) { 3657 /* Cancel scheduled suspend requests. */ 3658 pm_runtime_resume(netdev->dev.parent); 3659 3660 if (!netif_carrier_ok(netdev)) { 3661 u32 ctrl; 3662 hw->mac.ops.get_speed_and_duplex(hw, 3663 &adapter->link_speed, 3664 &adapter->link_duplex); 3665 3666 ctrl = rd32(E1000_CTRL); 3667 /* Links status message must follow this format */ 3668 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s " 3669 "Duplex, Flow Control: %s\n", 3670 netdev->name, 3671 adapter->link_speed, 3672 adapter->link_duplex == FULL_DUPLEX ? 3673 "Full" : "Half", 3674 (ctrl & E1000_CTRL_TFCE) && 3675 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 3676 (ctrl & E1000_CTRL_RFCE) ? "RX" : 3677 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 3678 3679 /* check for thermal sensor event */ 3680 if (igb_thermal_sensor_event(hw, 3681 E1000_THSTAT_LINK_THROTTLE)) { 3682 netdev_info(netdev, "The network adapter link " 3683 "speed was downshifted because it " 3684 "overheated\n"); 3685 } 3686 3687 /* adjust timeout factor according to speed/duplex */ 3688 adapter->tx_timeout_factor = 1; 3689 switch (adapter->link_speed) { 3690 case SPEED_10: 3691 adapter->tx_timeout_factor = 14; 3692 break; 3693 case SPEED_100: 3694 /* maybe add some timeout factor ? */ 3695 break; 3696 } 3697 3698 netif_carrier_on(netdev); 3699 3700 igb_ping_all_vfs(adapter); 3701 igb_check_vf_rate_limit(adapter); 3702 3703 /* link state has changed, schedule phy info update */ 3704 if (!test_bit(__IGB_DOWN, &adapter->state)) 3705 mod_timer(&adapter->phy_info_timer, 3706 round_jiffies(jiffies + 2 * HZ)); 3707 } 3708 } else { 3709 if (netif_carrier_ok(netdev)) { 3710 adapter->link_speed = 0; 3711 adapter->link_duplex = 0; 3712 3713 /* check for thermal sensor event */ 3714 if (igb_thermal_sensor_event(hw, 3715 E1000_THSTAT_PWR_DOWN)) { 3716 netdev_err(netdev, "The network adapter was " 3717 "stopped because it overheated\n"); 3718 } 3719 3720 /* Links status message must follow this format */ 3721 printk(KERN_INFO "igb: %s NIC Link is Down\n", 3722 netdev->name); 3723 netif_carrier_off(netdev); 3724 3725 igb_ping_all_vfs(adapter); 3726 3727 /* link state has changed, schedule phy info update */ 3728 if (!test_bit(__IGB_DOWN, &adapter->state)) 3729 mod_timer(&adapter->phy_info_timer, 3730 round_jiffies(jiffies + 2 * HZ)); 3731 3732 pm_schedule_suspend(netdev->dev.parent, 3733 MSEC_PER_SEC * 5); 3734 } 3735 } 3736 3737 spin_lock(&adapter->stats64_lock); 3738 igb_update_stats(adapter, &adapter->stats64); 3739 spin_unlock(&adapter->stats64_lock); 3740 3741 for (i = 0; i < adapter->num_tx_queues; i++) { 3742 struct igb_ring *tx_ring = adapter->tx_ring[i]; 3743 if (!netif_carrier_ok(netdev)) { 3744 /* We've lost link, so the controller stops DMA, 3745 * but we've got queued Tx work that's never going 3746 * to get done, so reset controller to flush Tx. 3747 * (Do the reset outside of interrupt context). */ 3748 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 3749 adapter->tx_timeout_count++; 3750 schedule_work(&adapter->reset_task); 3751 /* return immediately since reset is imminent */ 3752 return; 3753 } 3754 } 3755 3756 /* Force detection of hung controller every watchdog period */ 3757 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 3758 } 3759 3760 /* Cause software interrupt to ensure rx ring is cleaned */ 3761 if (adapter->msix_entries) { 3762 u32 eics = 0; 3763 for (i = 0; i < adapter->num_q_vectors; i++) 3764 eics |= adapter->q_vector[i]->eims_value; 3765 wr32(E1000_EICS, eics); 3766 } else { 3767 wr32(E1000_ICS, E1000_ICS_RXDMT0); 3768 } 3769 3770 igb_spoof_check(adapter); 3771 3772 /* Reset the timer */ 3773 if (!test_bit(__IGB_DOWN, &adapter->state)) 3774 mod_timer(&adapter->watchdog_timer, 3775 round_jiffies(jiffies + 2 * HZ)); 3776} 3777 3778enum latency_range { 3779 lowest_latency = 0, 3780 low_latency = 1, 3781 bulk_latency = 2, 3782 latency_invalid = 255 3783}; 3784 3785/** 3786 * igb_update_ring_itr - update the dynamic ITR value based on packet size 3787 * 3788 * Stores a new ITR value based on strictly on packet size. This 3789 * algorithm is less sophisticated than that used in igb_update_itr, 3790 * due to the difficulty of synchronizing statistics across multiple 3791 * receive rings. The divisors and thresholds used by this function 3792 * were determined based on theoretical maximum wire speed and testing 3793 * data, in order to minimize response time while increasing bulk 3794 * throughput. 3795 * This functionality is controlled by the InterruptThrottleRate module 3796 * parameter (see igb_param.c) 3797 * NOTE: This function is called only when operating in a multiqueue 3798 * receive environment. 3799 * @q_vector: pointer to q_vector 3800 **/ 3801static void igb_update_ring_itr(struct igb_q_vector *q_vector) 3802{ 3803 int new_val = q_vector->itr_val; 3804 int avg_wire_size = 0; 3805 struct igb_adapter *adapter = q_vector->adapter; 3806 unsigned int packets; 3807 3808 /* For non-gigabit speeds, just fix the interrupt rate at 4000 3809 * ints/sec - ITR timer value of 120 ticks. 3810 */ 3811 if (adapter->link_speed != SPEED_1000) { 3812 new_val = IGB_4K_ITR; 3813 goto set_itr_val; 3814 } 3815 3816 packets = q_vector->rx.total_packets; 3817 if (packets) 3818 avg_wire_size = q_vector->rx.total_bytes / packets; 3819 3820 packets = q_vector->tx.total_packets; 3821 if (packets) 3822 avg_wire_size = max_t(u32, avg_wire_size, 3823 q_vector->tx.total_bytes / packets); 3824 3825 /* if avg_wire_size isn't set no work was done */ 3826 if (!avg_wire_size) 3827 goto clear_counts; 3828 3829 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 3830 avg_wire_size += 24; 3831 3832 /* Don't starve jumbo frames */ 3833 avg_wire_size = min(avg_wire_size, 3000); 3834 3835 /* Give a little boost to mid-size frames */ 3836 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 3837 new_val = avg_wire_size / 3; 3838 else 3839 new_val = avg_wire_size / 2; 3840 3841 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 3842 if (new_val < IGB_20K_ITR && 3843 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 3844 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 3845 new_val = IGB_20K_ITR; 3846 3847set_itr_val: 3848 if (new_val != q_vector->itr_val) { 3849 q_vector->itr_val = new_val; 3850 q_vector->set_itr = 1; 3851 } 3852clear_counts: 3853 q_vector->rx.total_bytes = 0; 3854 q_vector->rx.total_packets = 0; 3855 q_vector->tx.total_bytes = 0; 3856 q_vector->tx.total_packets = 0; 3857} 3858 3859/** 3860 * igb_update_itr - update the dynamic ITR value based on statistics 3861 * Stores a new ITR value based on packets and byte 3862 * counts during the last interrupt. The advantage of per interrupt 3863 * computation is faster updates and more accurate ITR for the current 3864 * traffic pattern. Constants in this function were computed 3865 * based on theoretical maximum wire speed and thresholds were set based 3866 * on testing data as well as attempting to minimize response time 3867 * while increasing bulk throughput. 3868 * this functionality is controlled by the InterruptThrottleRate module 3869 * parameter (see igb_param.c) 3870 * NOTE: These calculations are only valid when operating in a single- 3871 * queue environment. 3872 * @q_vector: pointer to q_vector 3873 * @ring_container: ring info to update the itr for 3874 **/ 3875static void igb_update_itr(struct igb_q_vector *q_vector, 3876 struct igb_ring_container *ring_container) 3877{ 3878 unsigned int packets = ring_container->total_packets; 3879 unsigned int bytes = ring_container->total_bytes; 3880 u8 itrval = ring_container->itr; 3881 3882 /* no packets, exit with status unchanged */ 3883 if (packets == 0) 3884 return; 3885 3886 switch (itrval) { 3887 case lowest_latency: 3888 /* handle TSO and jumbo frames */ 3889 if (bytes/packets > 8000) 3890 itrval = bulk_latency; 3891 else if ((packets < 5) && (bytes > 512)) 3892 itrval = low_latency; 3893 break; 3894 case low_latency: /* 50 usec aka 20000 ints/s */ 3895 if (bytes > 10000) { 3896 /* this if handles the TSO accounting */ 3897 if (bytes/packets > 8000) { 3898 itrval = bulk_latency; 3899 } else if ((packets < 10) || ((bytes/packets) > 1200)) { 3900 itrval = bulk_latency; 3901 } else if ((packets > 35)) { 3902 itrval = lowest_latency; 3903 } 3904 } else if (bytes/packets > 2000) { 3905 itrval = bulk_latency; 3906 } else if (packets <= 2 && bytes < 512) { 3907 itrval = lowest_latency; 3908 } 3909 break; 3910 case bulk_latency: /* 250 usec aka 4000 ints/s */ 3911 if (bytes > 25000) { 3912 if (packets > 35) 3913 itrval = low_latency; 3914 } else if (bytes < 1500) { 3915 itrval = low_latency; 3916 } 3917 break; 3918 } 3919 3920 /* clear work counters since we have the values we need */ 3921 ring_container->total_bytes = 0; 3922 ring_container->total_packets = 0; 3923 3924 /* write updated itr to ring container */ 3925 ring_container->itr = itrval; 3926} 3927 3928static void igb_set_itr(struct igb_q_vector *q_vector) 3929{ 3930 struct igb_adapter *adapter = q_vector->adapter; 3931 u32 new_itr = q_vector->itr_val; 3932 u8 current_itr = 0; 3933 3934 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 3935 if (adapter->link_speed != SPEED_1000) { 3936 current_itr = 0; 3937 new_itr = IGB_4K_ITR; 3938 goto set_itr_now; 3939 } 3940 3941 igb_update_itr(q_vector, &q_vector->tx); 3942 igb_update_itr(q_vector, &q_vector->rx); 3943 3944 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 3945 3946 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 3947 if (current_itr == lowest_latency && 3948 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 3949 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 3950 current_itr = low_latency; 3951 3952 switch (current_itr) { 3953 /* counts and packets in update_itr are dependent on these numbers */ 3954 case lowest_latency: 3955 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 3956 break; 3957 case low_latency: 3958 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 3959 break; 3960 case bulk_latency: 3961 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 3962 break; 3963 default: 3964 break; 3965 } 3966 3967set_itr_now: 3968 if (new_itr != q_vector->itr_val) { 3969 /* this attempts to bias the interrupt rate towards Bulk 3970 * by adding intermediate steps when interrupt rate is 3971 * increasing */ 3972 new_itr = new_itr > q_vector->itr_val ? 3973 max((new_itr * q_vector->itr_val) / 3974 (new_itr + (q_vector->itr_val >> 2)), 3975 new_itr) : 3976 new_itr; 3977 /* Don't write the value here; it resets the adapter's 3978 * internal timer, and causes us to delay far longer than 3979 * we should between interrupts. Instead, we write the ITR 3980 * value at the beginning of the next interrupt so the timing 3981 * ends up being correct. 3982 */ 3983 q_vector->itr_val = new_itr; 3984 q_vector->set_itr = 1; 3985 } 3986} 3987 3988static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 3989 u32 type_tucmd, u32 mss_l4len_idx) 3990{ 3991 struct e1000_adv_tx_context_desc *context_desc; 3992 u16 i = tx_ring->next_to_use; 3993 3994 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 3995 3996 i++; 3997 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 3998 3999 /* set bits to identify this as an advanced context descriptor */ 4000 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4001 4002 /* For 82575, context index must be unique per ring. */ 4003 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4004 mss_l4len_idx |= tx_ring->reg_idx << 4; 4005 4006 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4007 context_desc->seqnum_seed = 0; 4008 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4009 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4010} 4011 4012static int igb_tso(struct igb_ring *tx_ring, 4013 struct igb_tx_buffer *first, 4014 u8 *hdr_len) 4015{ 4016 struct sk_buff *skb = first->skb; 4017 u32 vlan_macip_lens, type_tucmd; 4018 u32 mss_l4len_idx, l4len; 4019 4020 if (!skb_is_gso(skb)) 4021 return 0; 4022 4023 if (skb_header_cloned(skb)) { 4024 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 4025 if (err) 4026 return err; 4027 } 4028 4029 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4030 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4031 4032 if (first->protocol == __constant_htons(ETH_P_IP)) { 4033 struct iphdr *iph = ip_hdr(skb); 4034 iph->tot_len = 0; 4035 iph->check = 0; 4036 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4037 iph->daddr, 0, 4038 IPPROTO_TCP, 4039 0); 4040 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4041 first->tx_flags |= IGB_TX_FLAGS_TSO | 4042 IGB_TX_FLAGS_CSUM | 4043 IGB_TX_FLAGS_IPV4; 4044 } else if (skb_is_gso_v6(skb)) { 4045 ipv6_hdr(skb)->payload_len = 0; 4046 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4047 &ipv6_hdr(skb)->daddr, 4048 0, IPPROTO_TCP, 0); 4049 first->tx_flags |= IGB_TX_FLAGS_TSO | 4050 IGB_TX_FLAGS_CSUM; 4051 } 4052 4053 /* compute header lengths */ 4054 l4len = tcp_hdrlen(skb); 4055 *hdr_len = skb_transport_offset(skb) + l4len; 4056 4057 /* update gso size and bytecount with header size */ 4058 first->gso_segs = skb_shinfo(skb)->gso_segs; 4059 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4060 4061 /* MSS L4LEN IDX */ 4062 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4063 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4064 4065 /* VLAN MACLEN IPLEN */ 4066 vlan_macip_lens = skb_network_header_len(skb); 4067 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4068 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4069 4070 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4071 4072 return 1; 4073} 4074 4075static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4076{ 4077 struct sk_buff *skb = first->skb; 4078 u32 vlan_macip_lens = 0; 4079 u32 mss_l4len_idx = 0; 4080 u32 type_tucmd = 0; 4081 4082 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4083 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4084 return; 4085 } else { 4086 u8 l4_hdr = 0; 4087 switch (first->protocol) { 4088 case __constant_htons(ETH_P_IP): 4089 vlan_macip_lens |= skb_network_header_len(skb); 4090 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4091 l4_hdr = ip_hdr(skb)->protocol; 4092 break; 4093 case __constant_htons(ETH_P_IPV6): 4094 vlan_macip_lens |= skb_network_header_len(skb); 4095 l4_hdr = ipv6_hdr(skb)->nexthdr; 4096 break; 4097 default: 4098 if (unlikely(net_ratelimit())) { 4099 dev_warn(tx_ring->dev, 4100 "partial checksum but proto=%x!\n", 4101 first->protocol); 4102 } 4103 break; 4104 } 4105 4106 switch (l4_hdr) { 4107 case IPPROTO_TCP: 4108 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4109 mss_l4len_idx = tcp_hdrlen(skb) << 4110 E1000_ADVTXD_L4LEN_SHIFT; 4111 break; 4112 case IPPROTO_SCTP: 4113 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4114 mss_l4len_idx = sizeof(struct sctphdr) << 4115 E1000_ADVTXD_L4LEN_SHIFT; 4116 break; 4117 case IPPROTO_UDP: 4118 mss_l4len_idx = sizeof(struct udphdr) << 4119 E1000_ADVTXD_L4LEN_SHIFT; 4120 break; 4121 default: 4122 if (unlikely(net_ratelimit())) { 4123 dev_warn(tx_ring->dev, 4124 "partial checksum but l4 proto=%x!\n", 4125 l4_hdr); 4126 } 4127 break; 4128 } 4129 4130 /* update TX checksum flag */ 4131 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4132 } 4133 4134 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4135 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4136 4137 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4138} 4139 4140static __le32 igb_tx_cmd_type(u32 tx_flags) 4141{ 4142 /* set type for advanced descriptor with frame checksum insertion */ 4143 __le32 cmd_type = cpu_to_le32(E1000_ADVTXD_DTYP_DATA | 4144 E1000_ADVTXD_DCMD_IFCS | 4145 E1000_ADVTXD_DCMD_DEXT); 4146 4147 /* set HW vlan bit if vlan is present */ 4148 if (tx_flags & IGB_TX_FLAGS_VLAN) 4149 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_VLE); 4150 4151#ifdef CONFIG_IGB_PTP 4152 /* set timestamp bit if present */ 4153 if (unlikely(tx_flags & IGB_TX_FLAGS_TSTAMP)) 4154 cmd_type |= cpu_to_le32(E1000_ADVTXD_MAC_TSTAMP); 4155#endif /* CONFIG_IGB_PTP */ 4156 4157 /* set segmentation bits for TSO */ 4158 if (tx_flags & IGB_TX_FLAGS_TSO) 4159 cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_TSE); 4160 4161 return cmd_type; 4162} 4163 4164static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4165 union e1000_adv_tx_desc *tx_desc, 4166 u32 tx_flags, unsigned int paylen) 4167{ 4168 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4169 4170 /* 82575 requires a unique index per ring if any offload is enabled */ 4171 if ((tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_VLAN)) && 4172 test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4173 olinfo_status |= tx_ring->reg_idx << 4; 4174 4175 /* insert L4 checksum */ 4176 if (tx_flags & IGB_TX_FLAGS_CSUM) { 4177 olinfo_status |= E1000_TXD_POPTS_TXSM << 8; 4178 4179 /* insert IPv4 checksum */ 4180 if (tx_flags & IGB_TX_FLAGS_IPV4) 4181 olinfo_status |= E1000_TXD_POPTS_IXSM << 8; 4182 } 4183 4184 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4185} 4186 4187/* 4188 * The largest size we can write to the descriptor is 65535. In order to 4189 * maintain a power of two alignment we have to limit ourselves to 32K. 4190 */ 4191#define IGB_MAX_TXD_PWR 15 4192#define IGB_MAX_DATA_PER_TXD (1<<IGB_MAX_TXD_PWR) 4193 4194static void igb_tx_map(struct igb_ring *tx_ring, 4195 struct igb_tx_buffer *first, 4196 const u8 hdr_len) 4197{ 4198 struct sk_buff *skb = first->skb; 4199 struct igb_tx_buffer *tx_buffer; 4200 union e1000_adv_tx_desc *tx_desc; 4201 dma_addr_t dma; 4202 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 4203 unsigned int data_len = skb->data_len; 4204 unsigned int size = skb_headlen(skb); 4205 unsigned int paylen = skb->len - hdr_len; 4206 __le32 cmd_type; 4207 u32 tx_flags = first->tx_flags; 4208 u16 i = tx_ring->next_to_use; 4209 4210 tx_desc = IGB_TX_DESC(tx_ring, i); 4211 4212 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, paylen); 4213 cmd_type = igb_tx_cmd_type(tx_flags); 4214 4215 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4216 if (dma_mapping_error(tx_ring->dev, dma)) 4217 goto dma_error; 4218 4219 /* record length, and DMA address */ 4220 dma_unmap_len_set(first, len, size); 4221 dma_unmap_addr_set(first, dma, dma); 4222 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4223 4224 for (;;) { 4225 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4226 tx_desc->read.cmd_type_len = 4227 cmd_type | cpu_to_le32(IGB_MAX_DATA_PER_TXD); 4228 4229 i++; 4230 tx_desc++; 4231 if (i == tx_ring->count) { 4232 tx_desc = IGB_TX_DESC(tx_ring, 0); 4233 i = 0; 4234 } 4235 4236 dma += IGB_MAX_DATA_PER_TXD; 4237 size -= IGB_MAX_DATA_PER_TXD; 4238 4239 tx_desc->read.olinfo_status = 0; 4240 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4241 } 4242 4243 if (likely(!data_len)) 4244 break; 4245 4246 tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size); 4247 4248 i++; 4249 tx_desc++; 4250 if (i == tx_ring->count) { 4251 tx_desc = IGB_TX_DESC(tx_ring, 0); 4252 i = 0; 4253 } 4254 4255 size = skb_frag_size(frag); 4256 data_len -= size; 4257 4258 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4259 size, DMA_TO_DEVICE); 4260 if (dma_mapping_error(tx_ring->dev, dma)) 4261 goto dma_error; 4262 4263 tx_buffer = &tx_ring->tx_buffer_info[i]; 4264 dma_unmap_len_set(tx_buffer, len, size); 4265 dma_unmap_addr_set(tx_buffer, dma, dma); 4266 4267 tx_desc->read.olinfo_status = 0; 4268 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4269 4270 frag++; 4271 } 4272 4273 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4274 4275 /* write last descriptor with RS and EOP bits */ 4276 cmd_type |= cpu_to_le32(size) | cpu_to_le32(IGB_TXD_DCMD); 4277 if (unlikely(skb->no_fcs)) 4278 cmd_type &= ~(cpu_to_le32(E1000_ADVTXD_DCMD_IFCS)); 4279 tx_desc->read.cmd_type_len = cmd_type; 4280 4281 /* set the timestamp */ 4282 first->time_stamp = jiffies; 4283 4284 /* 4285 * Force memory writes to complete before letting h/w know there 4286 * are new descriptors to fetch. (Only applicable for weak-ordered 4287 * memory model archs, such as IA-64). 4288 * 4289 * We also need this memory barrier to make certain all of the 4290 * status bits have been updated before next_to_watch is written. 4291 */ 4292 wmb(); 4293 4294 /* set next_to_watch value indicating a packet is present */ 4295 first->next_to_watch = tx_desc; 4296 4297 i++; 4298 if (i == tx_ring->count) 4299 i = 0; 4300 4301 tx_ring->next_to_use = i; 4302 4303 writel(i, tx_ring->tail); 4304 4305 /* we need this if more than one processor can write to our tail 4306 * at a time, it syncronizes IO on IA64/Altix systems */ 4307 mmiowb(); 4308 4309 return; 4310 4311dma_error: 4312 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4313 4314 /* clear dma mappings for failed tx_buffer_info map */ 4315 for (;;) { 4316 tx_buffer = &tx_ring->tx_buffer_info[i]; 4317 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4318 if (tx_buffer == first) 4319 break; 4320 if (i == 0) 4321 i = tx_ring->count; 4322 i--; 4323 } 4324 4325 tx_ring->next_to_use = i; 4326} 4327 4328static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4329{ 4330 struct net_device *netdev = tx_ring->netdev; 4331 4332 netif_stop_subqueue(netdev, tx_ring->queue_index); 4333 4334 /* Herbert's original patch had: 4335 * smp_mb__after_netif_stop_queue(); 4336 * but since that doesn't exist yet, just open code it. */ 4337 smp_mb(); 4338 4339 /* We need to check again in a case another CPU has just 4340 * made room available. */ 4341 if (igb_desc_unused(tx_ring) < size) 4342 return -EBUSY; 4343 4344 /* A reprieve! */ 4345 netif_wake_subqueue(netdev, tx_ring->queue_index); 4346 4347 u64_stats_update_begin(&tx_ring->tx_syncp2); 4348 tx_ring->tx_stats.restart_queue2++; 4349 u64_stats_update_end(&tx_ring->tx_syncp2); 4350 4351 return 0; 4352} 4353 4354static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4355{ 4356 if (igb_desc_unused(tx_ring) >= size) 4357 return 0; 4358 return __igb_maybe_stop_tx(tx_ring, size); 4359} 4360 4361netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4362 struct igb_ring *tx_ring) 4363{ 4364#ifdef CONFIG_IGB_PTP 4365 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 4366#endif /* CONFIG_IGB_PTP */ 4367 struct igb_tx_buffer *first; 4368 int tso; 4369 u32 tx_flags = 0; 4370 __be16 protocol = vlan_get_protocol(skb); 4371 u8 hdr_len = 0; 4372 4373 /* need: 1 descriptor per page, 4374 * + 2 desc gap to keep tail from touching head, 4375 * + 1 desc for skb->data, 4376 * + 1 desc for context descriptor, 4377 * otherwise try next time */ 4378 if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) { 4379 /* this is a hard error */ 4380 return NETDEV_TX_BUSY; 4381 } 4382 4383 /* record the location of the first descriptor for this packet */ 4384 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 4385 first->skb = skb; 4386 first->bytecount = skb->len; 4387 first->gso_segs = 1; 4388 4389#ifdef CONFIG_IGB_PTP 4390 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4391 !(adapter->ptp_tx_skb))) { 4392 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4393 tx_flags |= IGB_TX_FLAGS_TSTAMP; 4394 4395 adapter->ptp_tx_skb = skb_get(skb); 4396 if (adapter->hw.mac.type == e1000_82576) 4397 schedule_work(&adapter->ptp_tx_work); 4398 } 4399#endif /* CONFIG_IGB_PTP */ 4400 4401 if (vlan_tx_tag_present(skb)) { 4402 tx_flags |= IGB_TX_FLAGS_VLAN; 4403 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 4404 } 4405 4406 /* record initial flags and protocol */ 4407 first->tx_flags = tx_flags; 4408 first->protocol = protocol; 4409 4410 tso = igb_tso(tx_ring, first, &hdr_len); 4411 if (tso < 0) 4412 goto out_drop; 4413 else if (!tso) 4414 igb_tx_csum(tx_ring, first); 4415 4416 igb_tx_map(tx_ring, first, hdr_len); 4417 4418 /* Make sure there is space in the ring for the next send. */ 4419 igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4); 4420 4421 return NETDEV_TX_OK; 4422 4423out_drop: 4424 igb_unmap_and_free_tx_resource(tx_ring, first); 4425 4426 return NETDEV_TX_OK; 4427} 4428 4429static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 4430 struct sk_buff *skb) 4431{ 4432 unsigned int r_idx = skb->queue_mapping; 4433 4434 if (r_idx >= adapter->num_tx_queues) 4435 r_idx = r_idx % adapter->num_tx_queues; 4436 4437 return adapter->tx_ring[r_idx]; 4438} 4439 4440static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 4441 struct net_device *netdev) 4442{ 4443 struct igb_adapter *adapter = netdev_priv(netdev); 4444 4445 if (test_bit(__IGB_DOWN, &adapter->state)) { 4446 dev_kfree_skb_any(skb); 4447 return NETDEV_TX_OK; 4448 } 4449 4450 if (skb->len <= 0) { 4451 dev_kfree_skb_any(skb); 4452 return NETDEV_TX_OK; 4453 } 4454 4455 /* 4456 * The minimum packet size with TCTL.PSP set is 17 so pad the skb 4457 * in order to meet this minimum size requirement. 4458 */ 4459 if (unlikely(skb->len < 17)) { 4460 if (skb_pad(skb, 17 - skb->len)) 4461 return NETDEV_TX_OK; 4462 skb->len = 17; 4463 skb_set_tail_pointer(skb, 17); 4464 } 4465 4466 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 4467} 4468 4469/** 4470 * igb_tx_timeout - Respond to a Tx Hang 4471 * @netdev: network interface device structure 4472 **/ 4473static void igb_tx_timeout(struct net_device *netdev) 4474{ 4475 struct igb_adapter *adapter = netdev_priv(netdev); 4476 struct e1000_hw *hw = &adapter->hw; 4477 4478 /* Do the reset outside of interrupt context */ 4479 adapter->tx_timeout_count++; 4480 4481 if (hw->mac.type >= e1000_82580) 4482 hw->dev_spec._82575.global_device_reset = true; 4483 4484 schedule_work(&adapter->reset_task); 4485 wr32(E1000_EICS, 4486 (adapter->eims_enable_mask & ~adapter->eims_other)); 4487} 4488 4489static void igb_reset_task(struct work_struct *work) 4490{ 4491 struct igb_adapter *adapter; 4492 adapter = container_of(work, struct igb_adapter, reset_task); 4493 4494 igb_dump(adapter); 4495 netdev_err(adapter->netdev, "Reset adapter\n"); 4496 igb_reinit_locked(adapter); 4497} 4498 4499/** 4500 * igb_get_stats64 - Get System Network Statistics 4501 * @netdev: network interface device structure 4502 * @stats: rtnl_link_stats64 pointer 4503 * 4504 **/ 4505static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 4506 struct rtnl_link_stats64 *stats) 4507{ 4508 struct igb_adapter *adapter = netdev_priv(netdev); 4509 4510 spin_lock(&adapter->stats64_lock); 4511 igb_update_stats(adapter, &adapter->stats64); 4512 memcpy(stats, &adapter->stats64, sizeof(*stats)); 4513 spin_unlock(&adapter->stats64_lock); 4514 4515 return stats; 4516} 4517 4518/** 4519 * igb_change_mtu - Change the Maximum Transfer Unit 4520 * @netdev: network interface device structure 4521 * @new_mtu: new value for maximum frame size 4522 * 4523 * Returns 0 on success, negative on failure 4524 **/ 4525static int igb_change_mtu(struct net_device *netdev, int new_mtu) 4526{ 4527 struct igb_adapter *adapter = netdev_priv(netdev); 4528 struct pci_dev *pdev = adapter->pdev; 4529 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 4530 4531 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 4532 dev_err(&pdev->dev, "Invalid MTU setting\n"); 4533 return -EINVAL; 4534 } 4535 4536#define MAX_STD_JUMBO_FRAME_SIZE 9238 4537 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 4538 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 4539 return -EINVAL; 4540 } 4541 4542 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 4543 msleep(1); 4544 4545 /* igb_down has a dependency on max_frame_size */ 4546 adapter->max_frame_size = max_frame; 4547 4548 if (netif_running(netdev)) 4549 igb_down(adapter); 4550 4551 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 4552 netdev->mtu, new_mtu); 4553 netdev->mtu = new_mtu; 4554 4555 if (netif_running(netdev)) 4556 igb_up(adapter); 4557 else 4558 igb_reset(adapter); 4559 4560 clear_bit(__IGB_RESETTING, &adapter->state); 4561 4562 return 0; 4563} 4564 4565/** 4566 * igb_update_stats - Update the board statistics counters 4567 * @adapter: board private structure 4568 **/ 4569 4570void igb_update_stats(struct igb_adapter *adapter, 4571 struct rtnl_link_stats64 *net_stats) 4572{ 4573 struct e1000_hw *hw = &adapter->hw; 4574 struct pci_dev *pdev = adapter->pdev; 4575 u32 reg, mpc; 4576 u16 phy_tmp; 4577 int i; 4578 u64 bytes, packets; 4579 unsigned int start; 4580 u64 _bytes, _packets; 4581 4582#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF 4583 4584 /* 4585 * Prevent stats update while adapter is being reset, or if the pci 4586 * connection is down. 4587 */ 4588 if (adapter->link_speed == 0) 4589 return; 4590 if (pci_channel_offline(pdev)) 4591 return; 4592 4593 bytes = 0; 4594 packets = 0; 4595 for (i = 0; i < adapter->num_rx_queues; i++) { 4596 u32 rqdpc = rd32(E1000_RQDPC(i)); 4597 struct igb_ring *ring = adapter->rx_ring[i]; 4598 4599 if (rqdpc) { 4600 ring->rx_stats.drops += rqdpc; 4601 net_stats->rx_fifo_errors += rqdpc; 4602 } 4603 4604 do { 4605 start = u64_stats_fetch_begin_bh(&ring->rx_syncp); 4606 _bytes = ring->rx_stats.bytes; 4607 _packets = ring->rx_stats.packets; 4608 } while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start)); 4609 bytes += _bytes; 4610 packets += _packets; 4611 } 4612 4613 net_stats->rx_bytes = bytes; 4614 net_stats->rx_packets = packets; 4615 4616 bytes = 0; 4617 packets = 0; 4618 for (i = 0; i < adapter->num_tx_queues; i++) { 4619 struct igb_ring *ring = adapter->tx_ring[i]; 4620 do { 4621 start = u64_stats_fetch_begin_bh(&ring->tx_syncp); 4622 _bytes = ring->tx_stats.bytes; 4623 _packets = ring->tx_stats.packets; 4624 } while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start)); 4625 bytes += _bytes; 4626 packets += _packets; 4627 } 4628 net_stats->tx_bytes = bytes; 4629 net_stats->tx_packets = packets; 4630 4631 /* read stats registers */ 4632 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 4633 adapter->stats.gprc += rd32(E1000_GPRC); 4634 adapter->stats.gorc += rd32(E1000_GORCL); 4635 rd32(E1000_GORCH); /* clear GORCL */ 4636 adapter->stats.bprc += rd32(E1000_BPRC); 4637 adapter->stats.mprc += rd32(E1000_MPRC); 4638 adapter->stats.roc += rd32(E1000_ROC); 4639 4640 adapter->stats.prc64 += rd32(E1000_PRC64); 4641 adapter->stats.prc127 += rd32(E1000_PRC127); 4642 adapter->stats.prc255 += rd32(E1000_PRC255); 4643 adapter->stats.prc511 += rd32(E1000_PRC511); 4644 adapter->stats.prc1023 += rd32(E1000_PRC1023); 4645 adapter->stats.prc1522 += rd32(E1000_PRC1522); 4646 adapter->stats.symerrs += rd32(E1000_SYMERRS); 4647 adapter->stats.sec += rd32(E1000_SEC); 4648 4649 mpc = rd32(E1000_MPC); 4650 adapter->stats.mpc += mpc; 4651 net_stats->rx_fifo_errors += mpc; 4652 adapter->stats.scc += rd32(E1000_SCC); 4653 adapter->stats.ecol += rd32(E1000_ECOL); 4654 adapter->stats.mcc += rd32(E1000_MCC); 4655 adapter->stats.latecol += rd32(E1000_LATECOL); 4656 adapter->stats.dc += rd32(E1000_DC); 4657 adapter->stats.rlec += rd32(E1000_RLEC); 4658 adapter->stats.xonrxc += rd32(E1000_XONRXC); 4659 adapter->stats.xontxc += rd32(E1000_XONTXC); 4660 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 4661 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 4662 adapter->stats.fcruc += rd32(E1000_FCRUC); 4663 adapter->stats.gptc += rd32(E1000_GPTC); 4664 adapter->stats.gotc += rd32(E1000_GOTCL); 4665 rd32(E1000_GOTCH); /* clear GOTCL */ 4666 adapter->stats.rnbc += rd32(E1000_RNBC); 4667 adapter->stats.ruc += rd32(E1000_RUC); 4668 adapter->stats.rfc += rd32(E1000_RFC); 4669 adapter->stats.rjc += rd32(E1000_RJC); 4670 adapter->stats.tor += rd32(E1000_TORH); 4671 adapter->stats.tot += rd32(E1000_TOTH); 4672 adapter->stats.tpr += rd32(E1000_TPR); 4673 4674 adapter->stats.ptc64 += rd32(E1000_PTC64); 4675 adapter->stats.ptc127 += rd32(E1000_PTC127); 4676 adapter->stats.ptc255 += rd32(E1000_PTC255); 4677 adapter->stats.ptc511 += rd32(E1000_PTC511); 4678 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 4679 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 4680 4681 adapter->stats.mptc += rd32(E1000_MPTC); 4682 adapter->stats.bptc += rd32(E1000_BPTC); 4683 4684 adapter->stats.tpt += rd32(E1000_TPT); 4685 adapter->stats.colc += rd32(E1000_COLC); 4686 4687 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 4688 /* read internal phy specific stats */ 4689 reg = rd32(E1000_CTRL_EXT); 4690 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 4691 adapter->stats.rxerrc += rd32(E1000_RXERRC); 4692 4693 /* this stat has invalid values on i210/i211 */ 4694 if ((hw->mac.type != e1000_i210) && 4695 (hw->mac.type != e1000_i211)) 4696 adapter->stats.tncrs += rd32(E1000_TNCRS); 4697 } 4698 4699 adapter->stats.tsctc += rd32(E1000_TSCTC); 4700 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 4701 4702 adapter->stats.iac += rd32(E1000_IAC); 4703 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 4704 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 4705 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 4706 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 4707 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 4708 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 4709 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 4710 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 4711 4712 /* Fill out the OS statistics structure */ 4713 net_stats->multicast = adapter->stats.mprc; 4714 net_stats->collisions = adapter->stats.colc; 4715 4716 /* Rx Errors */ 4717 4718 /* RLEC on some newer hardware can be incorrect so build 4719 * our own version based on RUC and ROC */ 4720 net_stats->rx_errors = adapter->stats.rxerrc + 4721 adapter->stats.crcerrs + adapter->stats.algnerrc + 4722 adapter->stats.ruc + adapter->stats.roc + 4723 adapter->stats.cexterr; 4724 net_stats->rx_length_errors = adapter->stats.ruc + 4725 adapter->stats.roc; 4726 net_stats->rx_crc_errors = adapter->stats.crcerrs; 4727 net_stats->rx_frame_errors = adapter->stats.algnerrc; 4728 net_stats->rx_missed_errors = adapter->stats.mpc; 4729 4730 /* Tx Errors */ 4731 net_stats->tx_errors = adapter->stats.ecol + 4732 adapter->stats.latecol; 4733 net_stats->tx_aborted_errors = adapter->stats.ecol; 4734 net_stats->tx_window_errors = adapter->stats.latecol; 4735 net_stats->tx_carrier_errors = adapter->stats.tncrs; 4736 4737 /* Tx Dropped needs to be maintained elsewhere */ 4738 4739 /* Phy Stats */ 4740 if (hw->phy.media_type == e1000_media_type_copper) { 4741 if ((adapter->link_speed == SPEED_1000) && 4742 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 4743 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; 4744 adapter->phy_stats.idle_errors += phy_tmp; 4745 } 4746 } 4747 4748 /* Management Stats */ 4749 adapter->stats.mgptc += rd32(E1000_MGTPTC); 4750 adapter->stats.mgprc += rd32(E1000_MGTPRC); 4751 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 4752 4753 /* OS2BMC Stats */ 4754 reg = rd32(E1000_MANC); 4755 if (reg & E1000_MANC_EN_BMC2OS) { 4756 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 4757 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 4758 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 4759 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 4760 } 4761} 4762 4763static irqreturn_t igb_msix_other(int irq, void *data) 4764{ 4765 struct igb_adapter *adapter = data; 4766 struct e1000_hw *hw = &adapter->hw; 4767 u32 icr = rd32(E1000_ICR); 4768 /* reading ICR causes bit 31 of EICR to be cleared */ 4769 4770 if (icr & E1000_ICR_DRSTA) 4771 schedule_work(&adapter->reset_task); 4772 4773 if (icr & E1000_ICR_DOUTSYNC) { 4774 /* HW is reporting DMA is out of sync */ 4775 adapter->stats.doosync++; 4776 /* The DMA Out of Sync is also indication of a spoof event 4777 * in IOV mode. Check the Wrong VM Behavior register to 4778 * see if it is really a spoof event. */ 4779 igb_check_wvbr(adapter); 4780 } 4781 4782 /* Check for a mailbox event */ 4783 if (icr & E1000_ICR_VMMB) 4784 igb_msg_task(adapter); 4785 4786 if (icr & E1000_ICR_LSC) { 4787 hw->mac.get_link_status = 1; 4788 /* guard against interrupt when we're going down */ 4789 if (!test_bit(__IGB_DOWN, &adapter->state)) 4790 mod_timer(&adapter->watchdog_timer, jiffies + 1); 4791 } 4792 4793#ifdef CONFIG_IGB_PTP 4794 if (icr & E1000_ICR_TS) { 4795 u32 tsicr = rd32(E1000_TSICR); 4796 4797 if (tsicr & E1000_TSICR_TXTS) { 4798 /* acknowledge the interrupt */ 4799 wr32(E1000_TSICR, E1000_TSICR_TXTS); 4800 /* retrieve hardware timestamp */ 4801 schedule_work(&adapter->ptp_tx_work); 4802 } 4803 } 4804#endif /* CONFIG_IGB_PTP */ 4805 4806 wr32(E1000_EIMS, adapter->eims_other); 4807 4808 return IRQ_HANDLED; 4809} 4810 4811static void igb_write_itr(struct igb_q_vector *q_vector) 4812{ 4813 struct igb_adapter *adapter = q_vector->adapter; 4814 u32 itr_val = q_vector->itr_val & 0x7FFC; 4815 4816 if (!q_vector->set_itr) 4817 return; 4818 4819 if (!itr_val) 4820 itr_val = 0x4; 4821 4822 if (adapter->hw.mac.type == e1000_82575) 4823 itr_val |= itr_val << 16; 4824 else 4825 itr_val |= E1000_EITR_CNT_IGNR; 4826 4827 writel(itr_val, q_vector->itr_register); 4828 q_vector->set_itr = 0; 4829} 4830 4831static irqreturn_t igb_msix_ring(int irq, void *data) 4832{ 4833 struct igb_q_vector *q_vector = data; 4834 4835 /* Write the ITR value calculated from the previous interrupt. */ 4836 igb_write_itr(q_vector); 4837 4838 napi_schedule(&q_vector->napi); 4839 4840 return IRQ_HANDLED; 4841} 4842 4843#ifdef CONFIG_IGB_DCA 4844static void igb_update_dca(struct igb_q_vector *q_vector) 4845{ 4846 struct igb_adapter *adapter = q_vector->adapter; 4847 struct e1000_hw *hw = &adapter->hw; 4848 int cpu = get_cpu(); 4849 4850 if (q_vector->cpu == cpu) 4851 goto out_no_update; 4852 4853 if (q_vector->tx.ring) { 4854 int q = q_vector->tx.ring->reg_idx; 4855 u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q)); 4856 if (hw->mac.type == e1000_82575) { 4857 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK; 4858 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); 4859 } else { 4860 dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576; 4861 dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << 4862 E1000_DCA_TXCTRL_CPUID_SHIFT; 4863 } 4864 dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN; 4865 wr32(E1000_DCA_TXCTRL(q), dca_txctrl); 4866 } 4867 if (q_vector->rx.ring) { 4868 int q = q_vector->rx.ring->reg_idx; 4869 u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q)); 4870 if (hw->mac.type == e1000_82575) { 4871 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK; 4872 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu); 4873 } else { 4874 dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576; 4875 dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) << 4876 E1000_DCA_RXCTRL_CPUID_SHIFT; 4877 } 4878 dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN; 4879 dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN; 4880 dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN; 4881 wr32(E1000_DCA_RXCTRL(q), dca_rxctrl); 4882 } 4883 q_vector->cpu = cpu; 4884out_no_update: 4885 put_cpu(); 4886} 4887 4888static void igb_setup_dca(struct igb_adapter *adapter) 4889{ 4890 struct e1000_hw *hw = &adapter->hw; 4891 int i; 4892 4893 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 4894 return; 4895 4896 /* Always use CB2 mode, difference is masked in the CB driver. */ 4897 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 4898 4899 for (i = 0; i < adapter->num_q_vectors; i++) { 4900 adapter->q_vector[i]->cpu = -1; 4901 igb_update_dca(adapter->q_vector[i]); 4902 } 4903} 4904 4905static int __igb_notify_dca(struct device *dev, void *data) 4906{ 4907 struct net_device *netdev = dev_get_drvdata(dev); 4908 struct igb_adapter *adapter = netdev_priv(netdev); 4909 struct pci_dev *pdev = adapter->pdev; 4910 struct e1000_hw *hw = &adapter->hw; 4911 unsigned long event = *(unsigned long *)data; 4912 4913 switch (event) { 4914 case DCA_PROVIDER_ADD: 4915 /* if already enabled, don't do it again */ 4916 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 4917 break; 4918 if (dca_add_requester(dev) == 0) { 4919 adapter->flags |= IGB_FLAG_DCA_ENABLED; 4920 dev_info(&pdev->dev, "DCA enabled\n"); 4921 igb_setup_dca(adapter); 4922 break; 4923 } 4924 /* Fall Through since DCA is disabled. */ 4925 case DCA_PROVIDER_REMOVE: 4926 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 4927 /* without this a class_device is left 4928 * hanging around in the sysfs model */ 4929 dca_remove_requester(dev); 4930 dev_info(&pdev->dev, "DCA disabled\n"); 4931 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 4932 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 4933 } 4934 break; 4935 } 4936 4937 return 0; 4938} 4939 4940static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 4941 void *p) 4942{ 4943 int ret_val; 4944 4945 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 4946 __igb_notify_dca); 4947 4948 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 4949} 4950#endif /* CONFIG_IGB_DCA */ 4951 4952#ifdef CONFIG_PCI_IOV 4953static int igb_vf_configure(struct igb_adapter *adapter, int vf) 4954{ 4955 unsigned char mac_addr[ETH_ALEN]; 4956 4957 eth_random_addr(mac_addr); 4958 igb_set_vf_mac(adapter, vf, mac_addr); 4959 4960 return 0; 4961} 4962 4963static bool igb_vfs_are_assigned(struct igb_adapter *adapter) 4964{ 4965 struct pci_dev *pdev = adapter->pdev; 4966 struct pci_dev *vfdev; 4967 int dev_id; 4968 4969 switch (adapter->hw.mac.type) { 4970 case e1000_82576: 4971 dev_id = IGB_82576_VF_DEV_ID; 4972 break; 4973 case e1000_i350: 4974 dev_id = IGB_I350_VF_DEV_ID; 4975 break; 4976 default: 4977 return false; 4978 } 4979 4980 /* loop through all the VFs to see if we own any that are assigned */ 4981 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, NULL); 4982 while (vfdev) { 4983 /* if we don't own it we don't care */ 4984 if (vfdev->is_virtfn && vfdev->physfn == pdev) { 4985 /* if it is assigned we cannot release it */ 4986 if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) 4987 return true; 4988 } 4989 4990 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, dev_id, vfdev); 4991 } 4992 4993 return false; 4994} 4995 4996#endif 4997static void igb_ping_all_vfs(struct igb_adapter *adapter) 4998{ 4999 struct e1000_hw *hw = &adapter->hw; 5000 u32 ping; 5001 int i; 5002 5003 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5004 ping = E1000_PF_CONTROL_MSG; 5005 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5006 ping |= E1000_VT_MSGTYPE_CTS; 5007 igb_write_mbx(hw, &ping, 1, i); 5008 } 5009} 5010 5011static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5012{ 5013 struct e1000_hw *hw = &adapter->hw; 5014 u32 vmolr = rd32(E1000_VMOLR(vf)); 5015 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5016 5017 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5018 IGB_VF_FLAG_MULTI_PROMISC); 5019 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5020 5021 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5022 vmolr |= E1000_VMOLR_MPME; 5023 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5024 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5025 } else { 5026 /* 5027 * if we have hashes and we are clearing a multicast promisc 5028 * flag we need to write the hashes to the MTA as this step 5029 * was previously skipped 5030 */ 5031 if (vf_data->num_vf_mc_hashes > 30) { 5032 vmolr |= E1000_VMOLR_MPME; 5033 } else if (vf_data->num_vf_mc_hashes) { 5034 int j; 5035 vmolr |= E1000_VMOLR_ROMPE; 5036 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5037 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5038 } 5039 } 5040 5041 wr32(E1000_VMOLR(vf), vmolr); 5042 5043 /* there are flags left unprocessed, likely not supported */ 5044 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5045 return -EINVAL; 5046 5047 return 0; 5048 5049} 5050 5051static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5052 u32 *msgbuf, u32 vf) 5053{ 5054 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5055 u16 *hash_list = (u16 *)&msgbuf[1]; 5056 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5057 int i; 5058 5059 /* salt away the number of multicast addresses assigned 5060 * to this VF for later use to restore when the PF multi cast 5061 * list changes 5062 */ 5063 vf_data->num_vf_mc_hashes = n; 5064 5065 /* only up to 30 hash values supported */ 5066 if (n > 30) 5067 n = 30; 5068 5069 /* store the hashes for later use */ 5070 for (i = 0; i < n; i++) 5071 vf_data->vf_mc_hashes[i] = hash_list[i]; 5072 5073 /* Flush and reset the mta with the new values */ 5074 igb_set_rx_mode(adapter->netdev); 5075 5076 return 0; 5077} 5078 5079static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5080{ 5081 struct e1000_hw *hw = &adapter->hw; 5082 struct vf_data_storage *vf_data; 5083 int i, j; 5084 5085 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5086 u32 vmolr = rd32(E1000_VMOLR(i)); 5087 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5088 5089 vf_data = &adapter->vf_data[i]; 5090 5091 if ((vf_data->num_vf_mc_hashes > 30) || 5092 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5093 vmolr |= E1000_VMOLR_MPME; 5094 } else if (vf_data->num_vf_mc_hashes) { 5095 vmolr |= E1000_VMOLR_ROMPE; 5096 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5097 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5098 } 5099 wr32(E1000_VMOLR(i), vmolr); 5100 } 5101} 5102 5103static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5104{ 5105 struct e1000_hw *hw = &adapter->hw; 5106 u32 pool_mask, reg, vid; 5107 int i; 5108 5109 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5110 5111 /* Find the vlan filter for this id */ 5112 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5113 reg = rd32(E1000_VLVF(i)); 5114 5115 /* remove the vf from the pool */ 5116 reg &= ~pool_mask; 5117 5118 /* if pool is empty then remove entry from vfta */ 5119 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5120 (reg & E1000_VLVF_VLANID_ENABLE)) { 5121 reg = 0; 5122 vid = reg & E1000_VLVF_VLANID_MASK; 5123 igb_vfta_set(hw, vid, false); 5124 } 5125 5126 wr32(E1000_VLVF(i), reg); 5127 } 5128 5129 adapter->vf_data[vf].vlans_enabled = 0; 5130} 5131 5132static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5133{ 5134 struct e1000_hw *hw = &adapter->hw; 5135 u32 reg, i; 5136 5137 /* The vlvf table only exists on 82576 hardware and newer */ 5138 if (hw->mac.type < e1000_82576) 5139 return -1; 5140 5141 /* we only need to do this if VMDq is enabled */ 5142 if (!adapter->vfs_allocated_count) 5143 return -1; 5144 5145 /* Find the vlan filter for this id */ 5146 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5147 reg = rd32(E1000_VLVF(i)); 5148 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5149 vid == (reg & E1000_VLVF_VLANID_MASK)) 5150 break; 5151 } 5152 5153 if (add) { 5154 if (i == E1000_VLVF_ARRAY_SIZE) { 5155 /* Did not find a matching VLAN ID entry that was 5156 * enabled. Search for a free filter entry, i.e. 5157 * one without the enable bit set 5158 */ 5159 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5160 reg = rd32(E1000_VLVF(i)); 5161 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5162 break; 5163 } 5164 } 5165 if (i < E1000_VLVF_ARRAY_SIZE) { 5166 /* Found an enabled/available entry */ 5167 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5168 5169 /* if !enabled we need to set this up in vfta */ 5170 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5171 /* add VID to filter table */ 5172 igb_vfta_set(hw, vid, true); 5173 reg |= E1000_VLVF_VLANID_ENABLE; 5174 } 5175 reg &= ~E1000_VLVF_VLANID_MASK; 5176 reg |= vid; 5177 wr32(E1000_VLVF(i), reg); 5178 5179 /* do not modify RLPML for PF devices */ 5180 if (vf >= adapter->vfs_allocated_count) 5181 return 0; 5182 5183 if (!adapter->vf_data[vf].vlans_enabled) { 5184 u32 size; 5185 reg = rd32(E1000_VMOLR(vf)); 5186 size = reg & E1000_VMOLR_RLPML_MASK; 5187 size += 4; 5188 reg &= ~E1000_VMOLR_RLPML_MASK; 5189 reg |= size; 5190 wr32(E1000_VMOLR(vf), reg); 5191 } 5192 5193 adapter->vf_data[vf].vlans_enabled++; 5194 } 5195 } else { 5196 if (i < E1000_VLVF_ARRAY_SIZE) { 5197 /* remove vf from the pool */ 5198 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5199 /* if pool is empty then remove entry from vfta */ 5200 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5201 reg = 0; 5202 igb_vfta_set(hw, vid, false); 5203 } 5204 wr32(E1000_VLVF(i), reg); 5205 5206 /* do not modify RLPML for PF devices */ 5207 if (vf >= adapter->vfs_allocated_count) 5208 return 0; 5209 5210 adapter->vf_data[vf].vlans_enabled--; 5211 if (!adapter->vf_data[vf].vlans_enabled) { 5212 u32 size; 5213 reg = rd32(E1000_VMOLR(vf)); 5214 size = reg & E1000_VMOLR_RLPML_MASK; 5215 size -= 4; 5216 reg &= ~E1000_VMOLR_RLPML_MASK; 5217 reg |= size; 5218 wr32(E1000_VMOLR(vf), reg); 5219 } 5220 } 5221 } 5222 return 0; 5223} 5224 5225static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5226{ 5227 struct e1000_hw *hw = &adapter->hw; 5228 5229 if (vid) 5230 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5231 else 5232 wr32(E1000_VMVIR(vf), 0); 5233} 5234 5235static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5236 int vf, u16 vlan, u8 qos) 5237{ 5238 int err = 0; 5239 struct igb_adapter *adapter = netdev_priv(netdev); 5240 5241 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5242 return -EINVAL; 5243 if (vlan || qos) { 5244 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5245 if (err) 5246 goto out; 5247 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5248 igb_set_vmolr(adapter, vf, !vlan); 5249 adapter->vf_data[vf].pf_vlan = vlan; 5250 adapter->vf_data[vf].pf_qos = qos; 5251 dev_info(&adapter->pdev->dev, 5252 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5253 if (test_bit(__IGB_DOWN, &adapter->state)) { 5254 dev_warn(&adapter->pdev->dev, 5255 "The VF VLAN has been set," 5256 " but the PF device is not up.\n"); 5257 dev_warn(&adapter->pdev->dev, 5258 "Bring the PF device up before" 5259 " attempting to use the VF device.\n"); 5260 } 5261 } else { 5262 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5263 false, vf); 5264 igb_set_vmvir(adapter, vlan, vf); 5265 igb_set_vmolr(adapter, vf, true); 5266 adapter->vf_data[vf].pf_vlan = 0; 5267 adapter->vf_data[vf].pf_qos = 0; 5268 } 5269out: 5270 return err; 5271} 5272 5273static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5274{ 5275 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5276 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5277 5278 return igb_vlvf_set(adapter, vid, add, vf); 5279} 5280 5281static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 5282{ 5283 /* clear flags - except flag that indicates PF has set the MAC */ 5284 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 5285 adapter->vf_data[vf].last_nack = jiffies; 5286 5287 /* reset offloads to defaults */ 5288 igb_set_vmolr(adapter, vf, true); 5289 5290 /* reset vlans for device */ 5291 igb_clear_vf_vfta(adapter, vf); 5292 if (adapter->vf_data[vf].pf_vlan) 5293 igb_ndo_set_vf_vlan(adapter->netdev, vf, 5294 adapter->vf_data[vf].pf_vlan, 5295 adapter->vf_data[vf].pf_qos); 5296 else 5297 igb_clear_vf_vfta(adapter, vf); 5298 5299 /* reset multicast table array for vf */ 5300 adapter->vf_data[vf].num_vf_mc_hashes = 0; 5301 5302 /* Flush and reset the mta with the new values */ 5303 igb_set_rx_mode(adapter->netdev); 5304} 5305 5306static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 5307{ 5308 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5309 5310 /* generate a new mac address as we were hotplug removed/added */ 5311 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 5312 eth_random_addr(vf_mac); 5313 5314 /* process remaining reset events */ 5315 igb_vf_reset(adapter, vf); 5316} 5317 5318static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 5319{ 5320 struct e1000_hw *hw = &adapter->hw; 5321 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5322 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 5323 u32 reg, msgbuf[3]; 5324 u8 *addr = (u8 *)(&msgbuf[1]); 5325 5326 /* process all the same items cleared in a function level reset */ 5327 igb_vf_reset(adapter, vf); 5328 5329 /* set vf mac address */ 5330 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 5331 5332 /* enable transmit and receive for vf */ 5333 reg = rd32(E1000_VFTE); 5334 wr32(E1000_VFTE, reg | (1 << vf)); 5335 reg = rd32(E1000_VFRE); 5336 wr32(E1000_VFRE, reg | (1 << vf)); 5337 5338 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 5339 5340 /* reply to reset with ack and vf mac address */ 5341 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 5342 memcpy(addr, vf_mac, 6); 5343 igb_write_mbx(hw, msgbuf, 3, vf); 5344} 5345 5346static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 5347{ 5348 /* 5349 * The VF MAC Address is stored in a packed array of bytes 5350 * starting at the second 32 bit word of the msg array 5351 */ 5352 unsigned char *addr = (char *)&msg[1]; 5353 int err = -1; 5354 5355 if (is_valid_ether_addr(addr)) 5356 err = igb_set_vf_mac(adapter, vf, addr); 5357 5358 return err; 5359} 5360 5361static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 5362{ 5363 struct e1000_hw *hw = &adapter->hw; 5364 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5365 u32 msg = E1000_VT_MSGTYPE_NACK; 5366 5367 /* if device isn't clear to send it shouldn't be reading either */ 5368 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 5369 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 5370 igb_write_mbx(hw, &msg, 1, vf); 5371 vf_data->last_nack = jiffies; 5372 } 5373} 5374 5375static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 5376{ 5377 struct pci_dev *pdev = adapter->pdev; 5378 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 5379 struct e1000_hw *hw = &adapter->hw; 5380 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5381 s32 retval; 5382 5383 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 5384 5385 if (retval) { 5386 /* if receive failed revoke VF CTS stats and restart init */ 5387 dev_err(&pdev->dev, "Error receiving message from VF\n"); 5388 vf_data->flags &= ~IGB_VF_FLAG_CTS; 5389 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 5390 return; 5391 goto out; 5392 } 5393 5394 /* this is a message we already processed, do nothing */ 5395 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 5396 return; 5397 5398 /* 5399 * until the vf completes a reset it should not be 5400 * allowed to start any configuration. 5401 */ 5402 5403 if (msgbuf[0] == E1000_VF_RESET) { 5404 igb_vf_reset_msg(adapter, vf); 5405 return; 5406 } 5407 5408 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 5409 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 5410 return; 5411 retval = -1; 5412 goto out; 5413 } 5414 5415 switch ((msgbuf[0] & 0xFFFF)) { 5416 case E1000_VF_SET_MAC_ADDR: 5417 retval = -EINVAL; 5418 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 5419 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 5420 else 5421 dev_warn(&pdev->dev, 5422 "VF %d attempted to override administratively " 5423 "set MAC address\nReload the VF driver to " 5424 "resume operations\n", vf); 5425 break; 5426 case E1000_VF_SET_PROMISC: 5427 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 5428 break; 5429 case E1000_VF_SET_MULTICAST: 5430 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 5431 break; 5432 case E1000_VF_SET_LPE: 5433 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 5434 break; 5435 case E1000_VF_SET_VLAN: 5436 retval = -1; 5437 if (vf_data->pf_vlan) 5438 dev_warn(&pdev->dev, 5439 "VF %d attempted to override administratively " 5440 "set VLAN tag\nReload the VF driver to " 5441 "resume operations\n", vf); 5442 else 5443 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 5444 break; 5445 default: 5446 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 5447 retval = -1; 5448 break; 5449 } 5450 5451 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 5452out: 5453 /* notify the VF of the results of what it sent us */ 5454 if (retval) 5455 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 5456 else 5457 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 5458 5459 igb_write_mbx(hw, msgbuf, 1, vf); 5460} 5461 5462static void igb_msg_task(struct igb_adapter *adapter) 5463{ 5464 struct e1000_hw *hw = &adapter->hw; 5465 u32 vf; 5466 5467 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 5468 /* process any reset requests */ 5469 if (!igb_check_for_rst(hw, vf)) 5470 igb_vf_reset_event(adapter, vf); 5471 5472 /* process any messages pending */ 5473 if (!igb_check_for_msg(hw, vf)) 5474 igb_rcv_msg_from_vf(adapter, vf); 5475 5476 /* process any acks */ 5477 if (!igb_check_for_ack(hw, vf)) 5478 igb_rcv_ack_from_vf(adapter, vf); 5479 } 5480} 5481 5482/** 5483 * igb_set_uta - Set unicast filter table address 5484 * @adapter: board private structure 5485 * 5486 * The unicast table address is a register array of 32-bit registers. 5487 * The table is meant to be used in a way similar to how the MTA is used 5488 * however due to certain limitations in the hardware it is necessary to 5489 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 5490 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 5491 **/ 5492static void igb_set_uta(struct igb_adapter *adapter) 5493{ 5494 struct e1000_hw *hw = &adapter->hw; 5495 int i; 5496 5497 /* The UTA table only exists on 82576 hardware and newer */ 5498 if (hw->mac.type < e1000_82576) 5499 return; 5500 5501 /* we only need to do this if VMDq is enabled */ 5502 if (!adapter->vfs_allocated_count) 5503 return; 5504 5505 for (i = 0; i < hw->mac.uta_reg_count; i++) 5506 array_wr32(E1000_UTA, i, ~0); 5507} 5508 5509/** 5510 * igb_intr_msi - Interrupt Handler 5511 * @irq: interrupt number 5512 * @data: pointer to a network interface device structure 5513 **/ 5514static irqreturn_t igb_intr_msi(int irq, void *data) 5515{ 5516 struct igb_adapter *adapter = data; 5517 struct igb_q_vector *q_vector = adapter->q_vector[0]; 5518 struct e1000_hw *hw = &adapter->hw; 5519 /* read ICR disables interrupts using IAM */ 5520 u32 icr = rd32(E1000_ICR); 5521 5522 igb_write_itr(q_vector); 5523 5524 if (icr & E1000_ICR_DRSTA) 5525 schedule_work(&adapter->reset_task); 5526 5527 if (icr & E1000_ICR_DOUTSYNC) { 5528 /* HW is reporting DMA is out of sync */ 5529 adapter->stats.doosync++; 5530 } 5531 5532 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 5533 hw->mac.get_link_status = 1; 5534 if (!test_bit(__IGB_DOWN, &adapter->state)) 5535 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5536 } 5537 5538#ifdef CONFIG_IGB_PTP 5539 if (icr & E1000_ICR_TS) { 5540 u32 tsicr = rd32(E1000_TSICR); 5541 5542 if (tsicr & E1000_TSICR_TXTS) { 5543 /* acknowledge the interrupt */ 5544 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5545 /* retrieve hardware timestamp */ 5546 schedule_work(&adapter->ptp_tx_work); 5547 } 5548 } 5549#endif /* CONFIG_IGB_PTP */ 5550 5551 napi_schedule(&q_vector->napi); 5552 5553 return IRQ_HANDLED; 5554} 5555 5556/** 5557 * igb_intr - Legacy Interrupt Handler 5558 * @irq: interrupt number 5559 * @data: pointer to a network interface device structure 5560 **/ 5561static irqreturn_t igb_intr(int irq, void *data) 5562{ 5563 struct igb_adapter *adapter = data; 5564 struct igb_q_vector *q_vector = adapter->q_vector[0]; 5565 struct e1000_hw *hw = &adapter->hw; 5566 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 5567 * need for the IMC write */ 5568 u32 icr = rd32(E1000_ICR); 5569 5570 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 5571 * not set, then the adapter didn't send an interrupt */ 5572 if (!(icr & E1000_ICR_INT_ASSERTED)) 5573 return IRQ_NONE; 5574 5575 igb_write_itr(q_vector); 5576 5577 if (icr & E1000_ICR_DRSTA) 5578 schedule_work(&adapter->reset_task); 5579 5580 if (icr & E1000_ICR_DOUTSYNC) { 5581 /* HW is reporting DMA is out of sync */ 5582 adapter->stats.doosync++; 5583 } 5584 5585 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 5586 hw->mac.get_link_status = 1; 5587 /* guard against interrupt when we're going down */ 5588 if (!test_bit(__IGB_DOWN, &adapter->state)) 5589 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5590 } 5591 5592#ifdef CONFIG_IGB_PTP 5593 if (icr & E1000_ICR_TS) { 5594 u32 tsicr = rd32(E1000_TSICR); 5595 5596 if (tsicr & E1000_TSICR_TXTS) { 5597 /* acknowledge the interrupt */ 5598 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5599 /* retrieve hardware timestamp */ 5600 schedule_work(&adapter->ptp_tx_work); 5601 } 5602 } 5603#endif /* CONFIG_IGB_PTP */ 5604 5605 napi_schedule(&q_vector->napi); 5606 5607 return IRQ_HANDLED; 5608} 5609 5610static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 5611{ 5612 struct igb_adapter *adapter = q_vector->adapter; 5613 struct e1000_hw *hw = &adapter->hw; 5614 5615 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 5616 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 5617 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 5618 igb_set_itr(q_vector); 5619 else 5620 igb_update_ring_itr(q_vector); 5621 } 5622 5623 if (!test_bit(__IGB_DOWN, &adapter->state)) { 5624 if (adapter->msix_entries) 5625 wr32(E1000_EIMS, q_vector->eims_value); 5626 else 5627 igb_irq_enable(adapter); 5628 } 5629} 5630 5631/** 5632 * igb_poll - NAPI Rx polling callback 5633 * @napi: napi polling structure 5634 * @budget: count of how many packets we should handle 5635 **/ 5636static int igb_poll(struct napi_struct *napi, int budget) 5637{ 5638 struct igb_q_vector *q_vector = container_of(napi, 5639 struct igb_q_vector, 5640 napi); 5641 bool clean_complete = true; 5642 5643#ifdef CONFIG_IGB_DCA 5644 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 5645 igb_update_dca(q_vector); 5646#endif 5647 if (q_vector->tx.ring) 5648 clean_complete = igb_clean_tx_irq(q_vector); 5649 5650 if (q_vector->rx.ring) 5651 clean_complete &= igb_clean_rx_irq(q_vector, budget); 5652 5653 /* If all work not completed, return budget and keep polling */ 5654 if (!clean_complete) 5655 return budget; 5656 5657 /* If not enough Rx work done, exit the polling mode */ 5658 napi_complete(napi); 5659 igb_ring_irq_enable(q_vector); 5660 5661 return 0; 5662} 5663 5664/** 5665 * igb_clean_tx_irq - Reclaim resources after transmit completes 5666 * @q_vector: pointer to q_vector containing needed info 5667 * 5668 * returns true if ring is completely cleaned 5669 **/ 5670static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 5671{ 5672 struct igb_adapter *adapter = q_vector->adapter; 5673 struct igb_ring *tx_ring = q_vector->tx.ring; 5674 struct igb_tx_buffer *tx_buffer; 5675 union e1000_adv_tx_desc *tx_desc; 5676 unsigned int total_bytes = 0, total_packets = 0; 5677 unsigned int budget = q_vector->tx.work_limit; 5678 unsigned int i = tx_ring->next_to_clean; 5679 5680 if (test_bit(__IGB_DOWN, &adapter->state)) 5681 return true; 5682 5683 tx_buffer = &tx_ring->tx_buffer_info[i]; 5684 tx_desc = IGB_TX_DESC(tx_ring, i); 5685 i -= tx_ring->count; 5686 5687 do { 5688 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 5689 5690 /* if next_to_watch is not set then there is no work pending */ 5691 if (!eop_desc) 5692 break; 5693 5694 /* prevent any other reads prior to eop_desc */ 5695 rmb(); 5696 5697 /* if DD is not set pending work has not been completed */ 5698 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 5699 break; 5700 5701 /* clear next_to_watch to prevent false hangs */ 5702 tx_buffer->next_to_watch = NULL; 5703 5704 /* update the statistics for this packet */ 5705 total_bytes += tx_buffer->bytecount; 5706 total_packets += tx_buffer->gso_segs; 5707 5708 /* free the skb */ 5709 dev_kfree_skb_any(tx_buffer->skb); 5710 5711 /* unmap skb header data */ 5712 dma_unmap_single(tx_ring->dev, 5713 dma_unmap_addr(tx_buffer, dma), 5714 dma_unmap_len(tx_buffer, len), 5715 DMA_TO_DEVICE); 5716 5717 /* clear tx_buffer data */ 5718 tx_buffer->skb = NULL; 5719 dma_unmap_len_set(tx_buffer, len, 0); 5720 5721 /* clear last DMA location and unmap remaining buffers */ 5722 while (tx_desc != eop_desc) { 5723 tx_buffer++; 5724 tx_desc++; 5725 i++; 5726 if (unlikely(!i)) { 5727 i -= tx_ring->count; 5728 tx_buffer = tx_ring->tx_buffer_info; 5729 tx_desc = IGB_TX_DESC(tx_ring, 0); 5730 } 5731 5732 /* unmap any remaining paged data */ 5733 if (dma_unmap_len(tx_buffer, len)) { 5734 dma_unmap_page(tx_ring->dev, 5735 dma_unmap_addr(tx_buffer, dma), 5736 dma_unmap_len(tx_buffer, len), 5737 DMA_TO_DEVICE); 5738 dma_unmap_len_set(tx_buffer, len, 0); 5739 } 5740 } 5741 5742 /* move us one more past the eop_desc for start of next pkt */ 5743 tx_buffer++; 5744 tx_desc++; 5745 i++; 5746 if (unlikely(!i)) { 5747 i -= tx_ring->count; 5748 tx_buffer = tx_ring->tx_buffer_info; 5749 tx_desc = IGB_TX_DESC(tx_ring, 0); 5750 } 5751 5752 /* issue prefetch for next Tx descriptor */ 5753 prefetch(tx_desc); 5754 5755 /* update budget accounting */ 5756 budget--; 5757 } while (likely(budget)); 5758 5759 netdev_tx_completed_queue(txring_txq(tx_ring), 5760 total_packets, total_bytes); 5761 i += tx_ring->count; 5762 tx_ring->next_to_clean = i; 5763 u64_stats_update_begin(&tx_ring->tx_syncp); 5764 tx_ring->tx_stats.bytes += total_bytes; 5765 tx_ring->tx_stats.packets += total_packets; 5766 u64_stats_update_end(&tx_ring->tx_syncp); 5767 q_vector->tx.total_bytes += total_bytes; 5768 q_vector->tx.total_packets += total_packets; 5769 5770 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 5771 struct e1000_hw *hw = &adapter->hw; 5772 5773 /* Detect a transmit hang in hardware, this serializes the 5774 * check with the clearing of time_stamp and movement of i */ 5775 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 5776 if (tx_buffer->next_to_watch && 5777 time_after(jiffies, tx_buffer->time_stamp + 5778 (adapter->tx_timeout_factor * HZ)) && 5779 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 5780 5781 /* detected Tx unit hang */ 5782 dev_err(tx_ring->dev, 5783 "Detected Tx Unit Hang\n" 5784 " Tx Queue <%d>\n" 5785 " TDH <%x>\n" 5786 " TDT <%x>\n" 5787 " next_to_use <%x>\n" 5788 " next_to_clean <%x>\n" 5789 "buffer_info[next_to_clean]\n" 5790 " time_stamp <%lx>\n" 5791 " next_to_watch <%p>\n" 5792 " jiffies <%lx>\n" 5793 " desc.status <%x>\n", 5794 tx_ring->queue_index, 5795 rd32(E1000_TDH(tx_ring->reg_idx)), 5796 readl(tx_ring->tail), 5797 tx_ring->next_to_use, 5798 tx_ring->next_to_clean, 5799 tx_buffer->time_stamp, 5800 tx_buffer->next_to_watch, 5801 jiffies, 5802 tx_buffer->next_to_watch->wb.status); 5803 netif_stop_subqueue(tx_ring->netdev, 5804 tx_ring->queue_index); 5805 5806 /* we are about to reset, no point in enabling stuff */ 5807 return true; 5808 } 5809 } 5810 5811 if (unlikely(total_packets && 5812 netif_carrier_ok(tx_ring->netdev) && 5813 igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) { 5814 /* Make sure that anybody stopping the queue after this 5815 * sees the new next_to_clean. 5816 */ 5817 smp_mb(); 5818 if (__netif_subqueue_stopped(tx_ring->netdev, 5819 tx_ring->queue_index) && 5820 !(test_bit(__IGB_DOWN, &adapter->state))) { 5821 netif_wake_subqueue(tx_ring->netdev, 5822 tx_ring->queue_index); 5823 5824 u64_stats_update_begin(&tx_ring->tx_syncp); 5825 tx_ring->tx_stats.restart_queue++; 5826 u64_stats_update_end(&tx_ring->tx_syncp); 5827 } 5828 } 5829 5830 return !!budget; 5831} 5832 5833/** 5834 * igb_reuse_rx_page - page flip buffer and store it back on the ring 5835 * @rx_ring: rx descriptor ring to store buffers on 5836 * @old_buff: donor buffer to have page reused 5837 * 5838 * Synchronizes page for reuse by the adapter 5839 **/ 5840static void igb_reuse_rx_page(struct igb_ring *rx_ring, 5841 struct igb_rx_buffer *old_buff) 5842{ 5843 struct igb_rx_buffer *new_buff; 5844 u16 nta = rx_ring->next_to_alloc; 5845 5846 new_buff = &rx_ring->rx_buffer_info[nta]; 5847 5848 /* update, and store next to alloc */ 5849 nta++; 5850 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 5851 5852 /* transfer page from old buffer to new buffer */ 5853 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); 5854 5855 /* sync the buffer for use by the device */ 5856 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 5857 old_buff->page_offset, 5858 PAGE_SIZE / 2, 5859 DMA_FROM_DEVICE); 5860} 5861 5862/** 5863 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 5864 * @rx_ring: rx descriptor ring to transact packets on 5865 * @rx_buffer: buffer containing page to add 5866 * @rx_desc: descriptor containing length of buffer written by hardware 5867 * @skb: sk_buff to place the data into 5868 * 5869 * This function will add the data contained in rx_buffer->page to the skb. 5870 * This is done either through a direct copy if the data in the buffer is 5871 * less than the skb header size, otherwise it will just attach the page as 5872 * a frag to the skb. 5873 * 5874 * The function will then update the page offset if necessary and return 5875 * true if the buffer can be reused by the adapter. 5876 **/ 5877static bool igb_add_rx_frag(struct igb_ring *rx_ring, 5878 struct igb_rx_buffer *rx_buffer, 5879 union e1000_adv_rx_desc *rx_desc, 5880 struct sk_buff *skb) 5881{ 5882 struct page *page = rx_buffer->page; 5883 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 5884 5885 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { 5886 unsigned char *va = page_address(page) + rx_buffer->page_offset; 5887 5888#ifdef CONFIG_IGB_PTP 5889 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 5890 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 5891 va += IGB_TS_HDR_LEN; 5892 size -= IGB_TS_HDR_LEN; 5893 } 5894 5895#endif 5896 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 5897 5898 /* we can reuse buffer as-is, just make sure it is local */ 5899 if (likely(page_to_nid(page) == numa_node_id())) 5900 return true; 5901 5902 /* this page cannot be reused so discard it */ 5903 put_page(page); 5904 return false; 5905 } 5906 5907 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 5908 rx_buffer->page_offset, size, PAGE_SIZE / 2); 5909 5910 /* avoid re-using remote pages */ 5911 if (unlikely(page_to_nid(page) != numa_node_id())) 5912 return false; 5913 5914 /* if we are only owner of page we can reuse it */ 5915 if (unlikely(page_count(page) != 1)) 5916 return false; 5917 5918 /* flip page offset to other buffer */ 5919 rx_buffer->page_offset ^= PAGE_SIZE / 2; 5920 5921 /* 5922 * since we are the only owner of the page and we need to 5923 * increment it, just set the value to 2 in order to avoid 5924 * an unnecessary locked operation 5925 */ 5926 atomic_set(&page->_count, 2); 5927 5928 return true; 5929} 5930 5931static inline void igb_rx_checksum(struct igb_ring *ring, 5932 union e1000_adv_rx_desc *rx_desc, 5933 struct sk_buff *skb) 5934{ 5935 skb_checksum_none_assert(skb); 5936 5937 /* Ignore Checksum bit is set */ 5938 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 5939 return; 5940 5941 /* Rx checksum disabled via ethtool */ 5942 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 5943 return; 5944 5945 /* TCP/UDP checksum error bit is set */ 5946 if (igb_test_staterr(rx_desc, 5947 E1000_RXDEXT_STATERR_TCPE | 5948 E1000_RXDEXT_STATERR_IPE)) { 5949 /* 5950 * work around errata with sctp packets where the TCPE aka 5951 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 5952 * packets, (aka let the stack check the crc32c) 5953 */ 5954 if (!((skb->len == 60) && 5955 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 5956 u64_stats_update_begin(&ring->rx_syncp); 5957 ring->rx_stats.csum_err++; 5958 u64_stats_update_end(&ring->rx_syncp); 5959 } 5960 /* let the stack verify checksum errors */ 5961 return; 5962 } 5963 /* It must be a TCP or UDP packet with a valid checksum */ 5964 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 5965 E1000_RXD_STAT_UDPCS)) 5966 skb->ip_summed = CHECKSUM_UNNECESSARY; 5967 5968 dev_dbg(ring->dev, "cksum success: bits %08X\n", 5969 le32_to_cpu(rx_desc->wb.upper.status_error)); 5970} 5971 5972static inline void igb_rx_hash(struct igb_ring *ring, 5973 union e1000_adv_rx_desc *rx_desc, 5974 struct sk_buff *skb) 5975{ 5976 if (ring->netdev->features & NETIF_F_RXHASH) 5977 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss); 5978} 5979 5980/** 5981 * igb_get_headlen - determine size of header for LRO/GRO 5982 * @data: pointer to the start of the headers 5983 * @max_len: total length of section to find headers in 5984 * 5985 * This function is meant to determine the length of headers that will 5986 * be recognized by hardware for LRO, and GRO offloads. The main 5987 * motivation of doing this is to only perform one pull for IPv4 TCP 5988 * packets so that we can do basic things like calculating the gso_size 5989 * based on the average data per packet. 5990 **/ 5991static unsigned int igb_get_headlen(unsigned char *data, 5992 unsigned int max_len) 5993{ 5994 union { 5995 unsigned char *network; 5996 /* l2 headers */ 5997 struct ethhdr *eth; 5998 struct vlan_hdr *vlan; 5999 /* l3 headers */ 6000 struct iphdr *ipv4; 6001 struct ipv6hdr *ipv6; 6002 } hdr; 6003 __be16 protocol; 6004 u8 nexthdr = 0; /* default to not TCP */ 6005 u8 hlen; 6006 6007 /* this should never happen, but better safe than sorry */ 6008 if (max_len < ETH_HLEN) 6009 return max_len; 6010 6011 /* initialize network frame pointer */ 6012 hdr.network = data; 6013 6014 /* set first protocol and move network header forward */ 6015 protocol = hdr.eth->h_proto; 6016 hdr.network += ETH_HLEN; 6017 6018 /* handle any vlan tag if present */ 6019 if (protocol == __constant_htons(ETH_P_8021Q)) { 6020 if ((hdr.network - data) > (max_len - VLAN_HLEN)) 6021 return max_len; 6022 6023 protocol = hdr.vlan->h_vlan_encapsulated_proto; 6024 hdr.network += VLAN_HLEN; 6025 } 6026 6027 /* handle L3 protocols */ 6028 if (protocol == __constant_htons(ETH_P_IP)) { 6029 if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) 6030 return max_len; 6031 6032 /* access ihl as a u8 to avoid unaligned access on ia64 */ 6033 hlen = (hdr.network[0] & 0x0F) << 2; 6034 6035 /* verify hlen meets minimum size requirements */ 6036 if (hlen < sizeof(struct iphdr)) 6037 return hdr.network - data; 6038 6039 /* record next protocol */ 6040 nexthdr = hdr.ipv4->protocol; 6041 hdr.network += hlen; 6042 } else if (protocol == __constant_htons(ETH_P_IPV6)) { 6043 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) 6044 return max_len; 6045 6046 /* record next protocol */ 6047 nexthdr = hdr.ipv6->nexthdr; 6048 hdr.network += sizeof(struct ipv6hdr); 6049 } else { 6050 return hdr.network - data; 6051 } 6052 6053 /* finally sort out TCP */ 6054 if (nexthdr == IPPROTO_TCP) { 6055 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) 6056 return max_len; 6057 6058 /* access doff as a u8 to avoid unaligned access on ia64 */ 6059 hlen = (hdr.network[12] & 0xF0) >> 2; 6060 6061 /* verify hlen meets minimum size requirements */ 6062 if (hlen < sizeof(struct tcphdr)) 6063 return hdr.network - data; 6064 6065 hdr.network += hlen; 6066 } else if (nexthdr == IPPROTO_UDP) { 6067 if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) 6068 return max_len; 6069 6070 hdr.network += sizeof(struct udphdr); 6071 } 6072 6073 /* 6074 * If everything has gone correctly hdr.network should be the 6075 * data section of the packet and will be the end of the header. 6076 * If not then it probably represents the end of the last recognized 6077 * header. 6078 */ 6079 if ((hdr.network - data) < max_len) 6080 return hdr.network - data; 6081 else 6082 return max_len; 6083} 6084 6085/** 6086 * igb_pull_tail - igb specific version of skb_pull_tail 6087 * @rx_ring: rx descriptor ring packet is being transacted on 6088 * @rx_desc: pointer to the EOP Rx descriptor 6089 * @skb: pointer to current skb being adjusted 6090 * 6091 * This function is an igb specific version of __pskb_pull_tail. The 6092 * main difference between this version and the original function is that 6093 * this function can make several assumptions about the state of things 6094 * that allow for significant optimizations versus the standard function. 6095 * As a result we can do things like drop a frag and maintain an accurate 6096 * truesize for the skb. 6097 */ 6098static void igb_pull_tail(struct igb_ring *rx_ring, 6099 union e1000_adv_rx_desc *rx_desc, 6100 struct sk_buff *skb) 6101{ 6102 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6103 unsigned char *va; 6104 unsigned int pull_len; 6105 6106 /* 6107 * it is valid to use page_address instead of kmap since we are 6108 * working with pages allocated out of the lomem pool per 6109 * alloc_page(GFP_ATOMIC) 6110 */ 6111 va = skb_frag_address(frag); 6112 6113#ifdef CONFIG_IGB_PTP 6114 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6115 /* retrieve timestamp from buffer */ 6116 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6117 6118 /* update pointers to remove timestamp header */ 6119 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); 6120 frag->page_offset += IGB_TS_HDR_LEN; 6121 skb->data_len -= IGB_TS_HDR_LEN; 6122 skb->len -= IGB_TS_HDR_LEN; 6123 6124 /* move va to start of packet data */ 6125 va += IGB_TS_HDR_LEN; 6126 } 6127 6128#endif 6129 /* 6130 * we need the header to contain the greater of either ETH_HLEN or 6131 * 60 bytes if the skb->len is less than 60 for skb_pad. 6132 */ 6133 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); 6134 6135 /* align pull length to size of long to optimize memcpy performance */ 6136 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 6137 6138 /* update all of the pointers */ 6139 skb_frag_size_sub(frag, pull_len); 6140 frag->page_offset += pull_len; 6141 skb->data_len -= pull_len; 6142 skb->tail += pull_len; 6143} 6144 6145/** 6146 * igb_cleanup_headers - Correct corrupted or empty headers 6147 * @rx_ring: rx descriptor ring packet is being transacted on 6148 * @rx_desc: pointer to the EOP Rx descriptor 6149 * @skb: pointer to current skb being fixed 6150 * 6151 * Address the case where we are pulling data in on pages only 6152 * and as such no data is present in the skb header. 6153 * 6154 * In addition if skb is not at least 60 bytes we need to pad it so that 6155 * it is large enough to qualify as a valid Ethernet frame. 6156 * 6157 * Returns true if an error was encountered and skb was freed. 6158 **/ 6159static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6160 union e1000_adv_rx_desc *rx_desc, 6161 struct sk_buff *skb) 6162{ 6163 6164 if (unlikely((igb_test_staterr(rx_desc, 6165 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6166 struct net_device *netdev = rx_ring->netdev; 6167 if (!(netdev->features & NETIF_F_RXALL)) { 6168 dev_kfree_skb_any(skb); 6169 return true; 6170 } 6171 } 6172 6173 /* place header in linear portion of buffer */ 6174 if (skb_is_nonlinear(skb)) 6175 igb_pull_tail(rx_ring, rx_desc, skb); 6176 6177 /* if skb_pad returns an error the skb was freed */ 6178 if (unlikely(skb->len < 60)) { 6179 int pad_len = 60 - skb->len; 6180 6181 if (skb_pad(skb, pad_len)) 6182 return true; 6183 __skb_put(skb, pad_len); 6184 } 6185 6186 return false; 6187} 6188 6189/** 6190 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6191 * @rx_ring: rx descriptor ring packet is being transacted on 6192 * @rx_desc: pointer to the EOP Rx descriptor 6193 * @skb: pointer to current skb being populated 6194 * 6195 * This function checks the ring, descriptor, and packet information in 6196 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6197 * other fields within the skb. 6198 **/ 6199static void igb_process_skb_fields(struct igb_ring *rx_ring, 6200 union e1000_adv_rx_desc *rx_desc, 6201 struct sk_buff *skb) 6202{ 6203 struct net_device *dev = rx_ring->netdev; 6204 6205 igb_rx_hash(rx_ring, rx_desc, skb); 6206 6207 igb_rx_checksum(rx_ring, rx_desc, skb); 6208 6209#ifdef CONFIG_IGB_PTP 6210 igb_ptp_rx_hwtstamp(rx_ring->q_vector, rx_desc, skb); 6211#endif /* CONFIG_IGB_PTP */ 6212 6213 if ((dev->features & NETIF_F_HW_VLAN_RX) && 6214 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6215 u16 vid; 6216 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6217 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6218 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6219 else 6220 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6221 6222 __vlan_hwaccel_put_tag(skb, vid); 6223 } 6224 6225 skb_record_rx_queue(skb, rx_ring->queue_index); 6226 6227 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6228} 6229 6230static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, int budget) 6231{ 6232 struct igb_ring *rx_ring = q_vector->rx.ring; 6233 union e1000_adv_rx_desc *rx_desc; 6234 struct sk_buff *skb = rx_ring->skb; 6235 unsigned int total_bytes = 0, total_packets = 0; 6236 u16 cleaned_count = igb_desc_unused(rx_ring); 6237 u16 i = rx_ring->next_to_clean; 6238 6239 rx_desc = IGB_RX_DESC(rx_ring, i); 6240 6241 while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) { 6242 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 6243 struct page *page; 6244 union e1000_adv_rx_desc *next_rxd; 6245 6246 i++; 6247 if (i == rx_ring->count) 6248 i = 0; 6249 6250 next_rxd = IGB_RX_DESC(rx_ring, i); 6251 prefetch(next_rxd); 6252 6253 /* 6254 * This memory barrier is needed to keep us from reading 6255 * any other fields out of the rx_desc until we know the 6256 * RXD_STAT_DD bit is set 6257 */ 6258 rmb(); 6259 6260 page = buffer_info->page; 6261 prefetchw(page); 6262 6263 if (likely(!skb)) { 6264 void *page_addr = page_address(page) + 6265 buffer_info->page_offset; 6266 6267 /* prefetch first cache line of first page */ 6268 prefetch(page_addr); 6269#if L1_CACHE_BYTES < 128 6270 prefetch(page_addr + L1_CACHE_BYTES); 6271#endif 6272 6273 /* allocate a skb to store the frags */ 6274 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 6275 IGB_RX_HDR_LEN); 6276 if (unlikely(!skb)) { 6277 rx_ring->rx_stats.alloc_failed++; 6278 break; 6279 } 6280 6281 /* 6282 * we will be copying header into skb->data in 6283 * pskb_may_pull so it is in our interest to prefetch 6284 * it now to avoid a possible cache miss 6285 */ 6286 prefetchw(skb->data); 6287 } 6288 6289 /* we are reusing so sync this buffer for CPU use */ 6290 dma_sync_single_range_for_cpu(rx_ring->dev, 6291 buffer_info->dma, 6292 buffer_info->page_offset, 6293 PAGE_SIZE / 2, 6294 DMA_FROM_DEVICE); 6295 6296 /* pull page into skb */ 6297 if (igb_add_rx_frag(rx_ring, buffer_info, rx_desc, skb)) { 6298 /* hand second half of page back to the ring */ 6299 igb_reuse_rx_page(rx_ring, buffer_info); 6300 } else { 6301 /* we are not reusing the buffer so unmap it */ 6302 dma_unmap_page(rx_ring->dev, buffer_info->dma, 6303 PAGE_SIZE, DMA_FROM_DEVICE); 6304 } 6305 6306 /* clear contents of buffer_info */ 6307 buffer_info->page = NULL; 6308 6309 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)) 6310 goto next_desc; 6311 6312 /* verify the packet layout is correct */ 6313 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 6314 skb = NULL; 6315 continue; 6316 } 6317 6318 /* probably a little skewed due to removing CRC */ 6319 total_bytes += skb->len; 6320 total_packets++; 6321 6322 /* populate checksum, timestamp, VLAN, and protocol */ 6323 igb_process_skb_fields(rx_ring, rx_desc, skb); 6324 6325 napi_gro_receive(&q_vector->napi, skb); 6326 6327 /* reset skb pointer */ 6328 skb = NULL; 6329 6330 budget--; 6331next_desc: 6332 if (!budget) 6333 break; 6334 6335 cleaned_count++; 6336 /* return some buffers to hardware, one at a time is too slow */ 6337 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6338 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6339 cleaned_count = 0; 6340 } 6341 6342 /* use prefetched values */ 6343 rx_desc = next_rxd; 6344 } 6345 6346 /* place incomplete frames back on ring for completion */ 6347 rx_ring->skb = skb; 6348 6349 rx_ring->next_to_clean = i; 6350 u64_stats_update_begin(&rx_ring->rx_syncp); 6351 rx_ring->rx_stats.packets += total_packets; 6352 rx_ring->rx_stats.bytes += total_bytes; 6353 u64_stats_update_end(&rx_ring->rx_syncp); 6354 q_vector->rx.total_packets += total_packets; 6355 q_vector->rx.total_bytes += total_bytes; 6356 6357 if (cleaned_count) 6358 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6359 6360 return !!budget; 6361} 6362 6363static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 6364 struct igb_rx_buffer *bi) 6365{ 6366 struct page *page = bi->page; 6367 dma_addr_t dma; 6368 6369 /* since we are recycling buffers we should seldom need to alloc */ 6370 if (likely(page)) 6371 return true; 6372 6373 /* alloc new page for storage */ 6374 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); 6375 if (unlikely(!page)) { 6376 rx_ring->rx_stats.alloc_failed++; 6377 return false; 6378 } 6379 6380 /* map page for use */ 6381 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 6382 6383 /* 6384 * if mapping failed free memory back to system since 6385 * there isn't much point in holding memory we can't use 6386 */ 6387 if (dma_mapping_error(rx_ring->dev, dma)) { 6388 __free_page(page); 6389 6390 rx_ring->rx_stats.alloc_failed++; 6391 return false; 6392 } 6393 6394 bi->dma = dma; 6395 bi->page = page; 6396 bi->page_offset = 0; 6397 6398 return true; 6399} 6400 6401/** 6402 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 6403 * @adapter: address of board private structure 6404 **/ 6405void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 6406{ 6407 union e1000_adv_rx_desc *rx_desc; 6408 struct igb_rx_buffer *bi; 6409 u16 i = rx_ring->next_to_use; 6410 6411 /* nothing to do */ 6412 if (!cleaned_count) 6413 return; 6414 6415 rx_desc = IGB_RX_DESC(rx_ring, i); 6416 bi = &rx_ring->rx_buffer_info[i]; 6417 i -= rx_ring->count; 6418 6419 do { 6420 if (!igb_alloc_mapped_page(rx_ring, bi)) 6421 break; 6422 6423 /* 6424 * Refresh the desc even if buffer_addrs didn't change 6425 * because each write-back erases this info. 6426 */ 6427 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 6428 6429 rx_desc++; 6430 bi++; 6431 i++; 6432 if (unlikely(!i)) { 6433 rx_desc = IGB_RX_DESC(rx_ring, 0); 6434 bi = rx_ring->rx_buffer_info; 6435 i -= rx_ring->count; 6436 } 6437 6438 /* clear the hdr_addr for the next_to_use descriptor */ 6439 rx_desc->read.hdr_addr = 0; 6440 6441 cleaned_count--; 6442 } while (cleaned_count); 6443 6444 i += rx_ring->count; 6445 6446 if (rx_ring->next_to_use != i) { 6447 /* record the next descriptor to use */ 6448 rx_ring->next_to_use = i; 6449 6450 /* update next to alloc since we have filled the ring */ 6451 rx_ring->next_to_alloc = i; 6452 6453 /* 6454 * Force memory writes to complete before letting h/w 6455 * know there are new descriptors to fetch. (Only 6456 * applicable for weak-ordered memory model archs, 6457 * such as IA-64). 6458 */ 6459 wmb(); 6460 writel(i, rx_ring->tail); 6461 } 6462} 6463 6464/** 6465 * igb_mii_ioctl - 6466 * @netdev: 6467 * @ifreq: 6468 * @cmd: 6469 **/ 6470static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6471{ 6472 struct igb_adapter *adapter = netdev_priv(netdev); 6473 struct mii_ioctl_data *data = if_mii(ifr); 6474 6475 if (adapter->hw.phy.media_type != e1000_media_type_copper) 6476 return -EOPNOTSUPP; 6477 6478 switch (cmd) { 6479 case SIOCGMIIPHY: 6480 data->phy_id = adapter->hw.phy.addr; 6481 break; 6482 case SIOCGMIIREG: 6483 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 6484 &data->val_out)) 6485 return -EIO; 6486 break; 6487 case SIOCSMIIREG: 6488 default: 6489 return -EOPNOTSUPP; 6490 } 6491 return 0; 6492} 6493 6494/** 6495 * igb_ioctl - 6496 * @netdev: 6497 * @ifreq: 6498 * @cmd: 6499 **/ 6500static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 6501{ 6502 switch (cmd) { 6503 case SIOCGMIIPHY: 6504 case SIOCGMIIREG: 6505 case SIOCSMIIREG: 6506 return igb_mii_ioctl(netdev, ifr, cmd); 6507#ifdef CONFIG_IGB_PTP 6508 case SIOCSHWTSTAMP: 6509 return igb_ptp_hwtstamp_ioctl(netdev, ifr, cmd); 6510#endif /* CONFIG_IGB_PTP */ 6511 default: 6512 return -EOPNOTSUPP; 6513 } 6514} 6515 6516s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 6517{ 6518 struct igb_adapter *adapter = hw->back; 6519 6520 if (pcie_capability_read_word(adapter->pdev, reg, value)) 6521 return -E1000_ERR_CONFIG; 6522 6523 return 0; 6524} 6525 6526s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 6527{ 6528 struct igb_adapter *adapter = hw->back; 6529 6530 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 6531 return -E1000_ERR_CONFIG; 6532 6533 return 0; 6534} 6535 6536static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 6537{ 6538 struct igb_adapter *adapter = netdev_priv(netdev); 6539 struct e1000_hw *hw = &adapter->hw; 6540 u32 ctrl, rctl; 6541 bool enable = !!(features & NETIF_F_HW_VLAN_RX); 6542 6543 if (enable) { 6544 /* enable VLAN tag insert/strip */ 6545 ctrl = rd32(E1000_CTRL); 6546 ctrl |= E1000_CTRL_VME; 6547 wr32(E1000_CTRL, ctrl); 6548 6549 /* Disable CFI check */ 6550 rctl = rd32(E1000_RCTL); 6551 rctl &= ~E1000_RCTL_CFIEN; 6552 wr32(E1000_RCTL, rctl); 6553 } else { 6554 /* disable VLAN tag insert/strip */ 6555 ctrl = rd32(E1000_CTRL); 6556 ctrl &= ~E1000_CTRL_VME; 6557 wr32(E1000_CTRL, ctrl); 6558 } 6559 6560 igb_rlpml_set(adapter); 6561} 6562 6563static int igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid) 6564{ 6565 struct igb_adapter *adapter = netdev_priv(netdev); 6566 struct e1000_hw *hw = &adapter->hw; 6567 int pf_id = adapter->vfs_allocated_count; 6568 6569 /* attempt to add filter to vlvf array */ 6570 igb_vlvf_set(adapter, vid, true, pf_id); 6571 6572 /* add the filter since PF can receive vlans w/o entry in vlvf */ 6573 igb_vfta_set(hw, vid, true); 6574 6575 set_bit(vid, adapter->active_vlans); 6576 6577 return 0; 6578} 6579 6580static int igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid) 6581{ 6582 struct igb_adapter *adapter = netdev_priv(netdev); 6583 struct e1000_hw *hw = &adapter->hw; 6584 int pf_id = adapter->vfs_allocated_count; 6585 s32 err; 6586 6587 /* remove vlan from VLVF table array */ 6588 err = igb_vlvf_set(adapter, vid, false, pf_id); 6589 6590 /* if vid was not present in VLVF just remove it from table */ 6591 if (err) 6592 igb_vfta_set(hw, vid, false); 6593 6594 clear_bit(vid, adapter->active_vlans); 6595 6596 return 0; 6597} 6598 6599static void igb_restore_vlan(struct igb_adapter *adapter) 6600{ 6601 u16 vid; 6602 6603 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 6604 6605 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 6606 igb_vlan_rx_add_vid(adapter->netdev, vid); 6607} 6608 6609int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 6610{ 6611 struct pci_dev *pdev = adapter->pdev; 6612 struct e1000_mac_info *mac = &adapter->hw.mac; 6613 6614 mac->autoneg = 0; 6615 6616 /* Make sure dplx is at most 1 bit and lsb of speed is not set 6617 * for the switch() below to work */ 6618 if ((spd & 1) || (dplx & ~1)) 6619 goto err_inval; 6620 6621 /* Fiber NIC's only allow 1000 Gbps Full duplex */ 6622 if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) && 6623 spd != SPEED_1000 && 6624 dplx != DUPLEX_FULL) 6625 goto err_inval; 6626 6627 switch (spd + dplx) { 6628 case SPEED_10 + DUPLEX_HALF: 6629 mac->forced_speed_duplex = ADVERTISE_10_HALF; 6630 break; 6631 case SPEED_10 + DUPLEX_FULL: 6632 mac->forced_speed_duplex = ADVERTISE_10_FULL; 6633 break; 6634 case SPEED_100 + DUPLEX_HALF: 6635 mac->forced_speed_duplex = ADVERTISE_100_HALF; 6636 break; 6637 case SPEED_100 + DUPLEX_FULL: 6638 mac->forced_speed_duplex = ADVERTISE_100_FULL; 6639 break; 6640 case SPEED_1000 + DUPLEX_FULL: 6641 mac->autoneg = 1; 6642 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 6643 break; 6644 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 6645 default: 6646 goto err_inval; 6647 } 6648 6649 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 6650 adapter->hw.phy.mdix = AUTO_ALL_MODES; 6651 6652 return 0; 6653 6654err_inval: 6655 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 6656 return -EINVAL; 6657} 6658 6659static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 6660 bool runtime) 6661{ 6662 struct net_device *netdev = pci_get_drvdata(pdev); 6663 struct igb_adapter *adapter = netdev_priv(netdev); 6664 struct e1000_hw *hw = &adapter->hw; 6665 u32 ctrl, rctl, status; 6666 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 6667#ifdef CONFIG_PM 6668 int retval = 0; 6669#endif 6670 6671 netif_device_detach(netdev); 6672 6673 if (netif_running(netdev)) 6674 __igb_close(netdev, true); 6675 6676 igb_clear_interrupt_scheme(adapter); 6677 6678#ifdef CONFIG_PM 6679 retval = pci_save_state(pdev); 6680 if (retval) 6681 return retval; 6682#endif 6683 6684 status = rd32(E1000_STATUS); 6685 if (status & E1000_STATUS_LU) 6686 wufc &= ~E1000_WUFC_LNKC; 6687 6688 if (wufc) { 6689 igb_setup_rctl(adapter); 6690 igb_set_rx_mode(netdev); 6691 6692 /* turn on all-multi mode if wake on multicast is enabled */ 6693 if (wufc & E1000_WUFC_MC) { 6694 rctl = rd32(E1000_RCTL); 6695 rctl |= E1000_RCTL_MPE; 6696 wr32(E1000_RCTL, rctl); 6697 } 6698 6699 ctrl = rd32(E1000_CTRL); 6700 /* advertise wake from D3Cold */ 6701 #define E1000_CTRL_ADVD3WUC 0x00100000 6702 /* phy power management enable */ 6703 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 6704 ctrl |= E1000_CTRL_ADVD3WUC; 6705 wr32(E1000_CTRL, ctrl); 6706 6707 /* Allow time for pending master requests to run */ 6708 igb_disable_pcie_master(hw); 6709 6710 wr32(E1000_WUC, E1000_WUC_PME_EN); 6711 wr32(E1000_WUFC, wufc); 6712 } else { 6713 wr32(E1000_WUC, 0); 6714 wr32(E1000_WUFC, 0); 6715 } 6716 6717 *enable_wake = wufc || adapter->en_mng_pt; 6718 if (!*enable_wake) 6719 igb_power_down_link(adapter); 6720 else 6721 igb_power_up_link(adapter); 6722 6723 /* Release control of h/w to f/w. If f/w is AMT enabled, this 6724 * would have already happened in close and is redundant. */ 6725 igb_release_hw_control(adapter); 6726 6727 pci_disable_device(pdev); 6728 6729 return 0; 6730} 6731 6732#ifdef CONFIG_PM 6733#ifdef CONFIG_PM_SLEEP 6734static int igb_suspend(struct device *dev) 6735{ 6736 int retval; 6737 bool wake; 6738 struct pci_dev *pdev = to_pci_dev(dev); 6739 6740 retval = __igb_shutdown(pdev, &wake, 0); 6741 if (retval) 6742 return retval; 6743 6744 if (wake) { 6745 pci_prepare_to_sleep(pdev); 6746 } else { 6747 pci_wake_from_d3(pdev, false); 6748 pci_set_power_state(pdev, PCI_D3hot); 6749 } 6750 6751 return 0; 6752} 6753#endif /* CONFIG_PM_SLEEP */ 6754 6755static int igb_resume(struct device *dev) 6756{ 6757 struct pci_dev *pdev = to_pci_dev(dev); 6758 struct net_device *netdev = pci_get_drvdata(pdev); 6759 struct igb_adapter *adapter = netdev_priv(netdev); 6760 struct e1000_hw *hw = &adapter->hw; 6761 u32 err; 6762 6763 pci_set_power_state(pdev, PCI_D0); 6764 pci_restore_state(pdev); 6765 pci_save_state(pdev); 6766 6767 err = pci_enable_device_mem(pdev); 6768 if (err) { 6769 dev_err(&pdev->dev, 6770 "igb: Cannot enable PCI device from suspend\n"); 6771 return err; 6772 } 6773 pci_set_master(pdev); 6774 6775 pci_enable_wake(pdev, PCI_D3hot, 0); 6776 pci_enable_wake(pdev, PCI_D3cold, 0); 6777 6778 if (igb_init_interrupt_scheme(adapter)) { 6779 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 6780 return -ENOMEM; 6781 } 6782 6783 igb_reset(adapter); 6784 6785 /* let the f/w know that the h/w is now under the control of the 6786 * driver. */ 6787 igb_get_hw_control(adapter); 6788 6789 wr32(E1000_WUS, ~0); 6790 6791 if (netdev->flags & IFF_UP) { 6792 err = __igb_open(netdev, true); 6793 if (err) 6794 return err; 6795 } 6796 6797 netif_device_attach(netdev); 6798 return 0; 6799} 6800 6801#ifdef CONFIG_PM_RUNTIME 6802static int igb_runtime_idle(struct device *dev) 6803{ 6804 struct pci_dev *pdev = to_pci_dev(dev); 6805 struct net_device *netdev = pci_get_drvdata(pdev); 6806 struct igb_adapter *adapter = netdev_priv(netdev); 6807 6808 if (!igb_has_link(adapter)) 6809 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 6810 6811 return -EBUSY; 6812} 6813 6814static int igb_runtime_suspend(struct device *dev) 6815{ 6816 struct pci_dev *pdev = to_pci_dev(dev); 6817 int retval; 6818 bool wake; 6819 6820 retval = __igb_shutdown(pdev, &wake, 1); 6821 if (retval) 6822 return retval; 6823 6824 if (wake) { 6825 pci_prepare_to_sleep(pdev); 6826 } else { 6827 pci_wake_from_d3(pdev, false); 6828 pci_set_power_state(pdev, PCI_D3hot); 6829 } 6830 6831 return 0; 6832} 6833 6834static int igb_runtime_resume(struct device *dev) 6835{ 6836 return igb_resume(dev); 6837} 6838#endif /* CONFIG_PM_RUNTIME */ 6839#endif 6840 6841static void igb_shutdown(struct pci_dev *pdev) 6842{ 6843 bool wake; 6844 6845 __igb_shutdown(pdev, &wake, 0); 6846 6847 if (system_state == SYSTEM_POWER_OFF) { 6848 pci_wake_from_d3(pdev, wake); 6849 pci_set_power_state(pdev, PCI_D3hot); 6850 } 6851} 6852 6853#ifdef CONFIG_NET_POLL_CONTROLLER 6854/* 6855 * Polling 'interrupt' - used by things like netconsole to send skbs 6856 * without having to re-enable interrupts. It's not called while 6857 * the interrupt routine is executing. 6858 */ 6859static void igb_netpoll(struct net_device *netdev) 6860{ 6861 struct igb_adapter *adapter = netdev_priv(netdev); 6862 struct e1000_hw *hw = &adapter->hw; 6863 struct igb_q_vector *q_vector; 6864 int i; 6865 6866 for (i = 0; i < adapter->num_q_vectors; i++) { 6867 q_vector = adapter->q_vector[i]; 6868 if (adapter->msix_entries) 6869 wr32(E1000_EIMC, q_vector->eims_value); 6870 else 6871 igb_irq_disable(adapter); 6872 napi_schedule(&q_vector->napi); 6873 } 6874} 6875#endif /* CONFIG_NET_POLL_CONTROLLER */ 6876 6877/** 6878 * igb_io_error_detected - called when PCI error is detected 6879 * @pdev: Pointer to PCI device 6880 * @state: The current pci connection state 6881 * 6882 * This function is called after a PCI bus error affecting 6883 * this device has been detected. 6884 */ 6885static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 6886 pci_channel_state_t state) 6887{ 6888 struct net_device *netdev = pci_get_drvdata(pdev); 6889 struct igb_adapter *adapter = netdev_priv(netdev); 6890 6891 netif_device_detach(netdev); 6892 6893 if (state == pci_channel_io_perm_failure) 6894 return PCI_ERS_RESULT_DISCONNECT; 6895 6896 if (netif_running(netdev)) 6897 igb_down(adapter); 6898 pci_disable_device(pdev); 6899 6900 /* Request a slot slot reset. */ 6901 return PCI_ERS_RESULT_NEED_RESET; 6902} 6903 6904/** 6905 * igb_io_slot_reset - called after the pci bus has been reset. 6906 * @pdev: Pointer to PCI device 6907 * 6908 * Restart the card from scratch, as if from a cold-boot. Implementation 6909 * resembles the first-half of the igb_resume routine. 6910 */ 6911static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 6912{ 6913 struct net_device *netdev = pci_get_drvdata(pdev); 6914 struct igb_adapter *adapter = netdev_priv(netdev); 6915 struct e1000_hw *hw = &adapter->hw; 6916 pci_ers_result_t result; 6917 int err; 6918 6919 if (pci_enable_device_mem(pdev)) { 6920 dev_err(&pdev->dev, 6921 "Cannot re-enable PCI device after reset.\n"); 6922 result = PCI_ERS_RESULT_DISCONNECT; 6923 } else { 6924 pci_set_master(pdev); 6925 pci_restore_state(pdev); 6926 pci_save_state(pdev); 6927 6928 pci_enable_wake(pdev, PCI_D3hot, 0); 6929 pci_enable_wake(pdev, PCI_D3cold, 0); 6930 6931 igb_reset(adapter); 6932 wr32(E1000_WUS, ~0); 6933 result = PCI_ERS_RESULT_RECOVERED; 6934 } 6935 6936 err = pci_cleanup_aer_uncorrect_error_status(pdev); 6937 if (err) { 6938 dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status " 6939 "failed 0x%0x\n", err); 6940 /* non-fatal, continue */ 6941 } 6942 6943 return result; 6944} 6945 6946/** 6947 * igb_io_resume - called when traffic can start flowing again. 6948 * @pdev: Pointer to PCI device 6949 * 6950 * This callback is called when the error recovery driver tells us that 6951 * its OK to resume normal operation. Implementation resembles the 6952 * second-half of the igb_resume routine. 6953 */ 6954static void igb_io_resume(struct pci_dev *pdev) 6955{ 6956 struct net_device *netdev = pci_get_drvdata(pdev); 6957 struct igb_adapter *adapter = netdev_priv(netdev); 6958 6959 if (netif_running(netdev)) { 6960 if (igb_up(adapter)) { 6961 dev_err(&pdev->dev, "igb_up failed after reset\n"); 6962 return; 6963 } 6964 } 6965 6966 netif_device_attach(netdev); 6967 6968 /* let the f/w know that the h/w is now under the control of the 6969 * driver. */ 6970 igb_get_hw_control(adapter); 6971} 6972 6973static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 6974 u8 qsel) 6975{ 6976 u32 rar_low, rar_high; 6977 struct e1000_hw *hw = &adapter->hw; 6978 6979 /* HW expects these in little endian so we reverse the byte order 6980 * from network order (big endian) to little endian 6981 */ 6982 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 6983 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 6984 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 6985 6986 /* Indicate to hardware the Address is Valid. */ 6987 rar_high |= E1000_RAH_AV; 6988 6989 if (hw->mac.type == e1000_82575) 6990 rar_high |= E1000_RAH_POOL_1 * qsel; 6991 else 6992 rar_high |= E1000_RAH_POOL_1 << qsel; 6993 6994 wr32(E1000_RAL(index), rar_low); 6995 wrfl(); 6996 wr32(E1000_RAH(index), rar_high); 6997 wrfl(); 6998} 6999 7000static int igb_set_vf_mac(struct igb_adapter *adapter, 7001 int vf, unsigned char *mac_addr) 7002{ 7003 struct e1000_hw *hw = &adapter->hw; 7004 /* VF MAC addresses start at end of receive addresses and moves 7005 * torwards the first, as a result a collision should not be possible */ 7006 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7007 7008 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7009 7010 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7011 7012 return 0; 7013} 7014 7015static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7016{ 7017 struct igb_adapter *adapter = netdev_priv(netdev); 7018 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7019 return -EINVAL; 7020 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7021 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7022 dev_info(&adapter->pdev->dev, "Reload the VF driver to make this" 7023 " change effective."); 7024 if (test_bit(__IGB_DOWN, &adapter->state)) { 7025 dev_warn(&adapter->pdev->dev, "The VF MAC address has been set," 7026 " but the PF device is not up.\n"); 7027 dev_warn(&adapter->pdev->dev, "Bring the PF device up before" 7028 " attempting to use the VF device.\n"); 7029 } 7030 return igb_set_vf_mac(adapter, vf, mac); 7031} 7032 7033static int igb_link_mbps(int internal_link_speed) 7034{ 7035 switch (internal_link_speed) { 7036 case SPEED_100: 7037 return 100; 7038 case SPEED_1000: 7039 return 1000; 7040 default: 7041 return 0; 7042 } 7043} 7044 7045static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7046 int link_speed) 7047{ 7048 int rf_dec, rf_int; 7049 u32 bcnrc_val; 7050 7051 if (tx_rate != 0) { 7052 /* Calculate the rate factor values to set */ 7053 rf_int = link_speed / tx_rate; 7054 rf_dec = (link_speed - (rf_int * tx_rate)); 7055 rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate; 7056 7057 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7058 bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) & 7059 E1000_RTTBCNRC_RF_INT_MASK); 7060 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7061 } else { 7062 bcnrc_val = 0; 7063 } 7064 7065 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7066 /* 7067 * Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7068 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7069 */ 7070 wr32(E1000_RTTBCNRM, 0x14); 7071 wr32(E1000_RTTBCNRC, bcnrc_val); 7072} 7073 7074static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7075{ 7076 int actual_link_speed, i; 7077 bool reset_rate = false; 7078 7079 /* VF TX rate limit was not set or not supported */ 7080 if ((adapter->vf_rate_link_speed == 0) || 7081 (adapter->hw.mac.type != e1000_82576)) 7082 return; 7083 7084 actual_link_speed = igb_link_mbps(adapter->link_speed); 7085 if (actual_link_speed != adapter->vf_rate_link_speed) { 7086 reset_rate = true; 7087 adapter->vf_rate_link_speed = 0; 7088 dev_info(&adapter->pdev->dev, 7089 "Link speed has been changed. VF Transmit " 7090 "rate is disabled\n"); 7091 } 7092 7093 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7094 if (reset_rate) 7095 adapter->vf_data[i].tx_rate = 0; 7096 7097 igb_set_vf_rate_limit(&adapter->hw, i, 7098 adapter->vf_data[i].tx_rate, 7099 actual_link_speed); 7100 } 7101} 7102 7103static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) 7104{ 7105 struct igb_adapter *adapter = netdev_priv(netdev); 7106 struct e1000_hw *hw = &adapter->hw; 7107 int actual_link_speed; 7108 7109 if (hw->mac.type != e1000_82576) 7110 return -EOPNOTSUPP; 7111 7112 actual_link_speed = igb_link_mbps(adapter->link_speed); 7113 if ((vf >= adapter->vfs_allocated_count) || 7114 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7115 (tx_rate < 0) || (tx_rate > actual_link_speed)) 7116 return -EINVAL; 7117 7118 adapter->vf_rate_link_speed = actual_link_speed; 7119 adapter->vf_data[vf].tx_rate = (u16)tx_rate; 7120 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); 7121 7122 return 0; 7123} 7124 7125static int igb_ndo_get_vf_config(struct net_device *netdev, 7126 int vf, struct ifla_vf_info *ivi) 7127{ 7128 struct igb_adapter *adapter = netdev_priv(netdev); 7129 if (vf >= adapter->vfs_allocated_count) 7130 return -EINVAL; 7131 ivi->vf = vf; 7132 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7133 ivi->tx_rate = adapter->vf_data[vf].tx_rate; 7134 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7135 ivi->qos = adapter->vf_data[vf].pf_qos; 7136 return 0; 7137} 7138 7139static void igb_vmm_control(struct igb_adapter *adapter) 7140{ 7141 struct e1000_hw *hw = &adapter->hw; 7142 u32 reg; 7143 7144 switch (hw->mac.type) { 7145 case e1000_82575: 7146 case e1000_i210: 7147 case e1000_i211: 7148 default: 7149 /* replication is not supported for 82575 */ 7150 return; 7151 case e1000_82576: 7152 /* notify HW that the MAC is adding vlan tags */ 7153 reg = rd32(E1000_DTXCTL); 7154 reg |= E1000_DTXCTL_VLAN_ADDED; 7155 wr32(E1000_DTXCTL, reg); 7156 case e1000_82580: 7157 /* enable replication vlan tag stripping */ 7158 reg = rd32(E1000_RPLOLR); 7159 reg |= E1000_RPLOLR_STRVLAN; 7160 wr32(E1000_RPLOLR, reg); 7161 case e1000_i350: 7162 /* none of the above registers are supported by i350 */ 7163 break; 7164 } 7165 7166 if (adapter->vfs_allocated_count) { 7167 igb_vmdq_set_loopback_pf(hw, true); 7168 igb_vmdq_set_replication_pf(hw, true); 7169 igb_vmdq_set_anti_spoofing_pf(hw, true, 7170 adapter->vfs_allocated_count); 7171 } else { 7172 igb_vmdq_set_loopback_pf(hw, false); 7173 igb_vmdq_set_replication_pf(hw, false); 7174 } 7175} 7176 7177static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7178{ 7179 struct e1000_hw *hw = &adapter->hw; 7180 u32 dmac_thr; 7181 u16 hwm; 7182 7183 if (hw->mac.type > e1000_82580) { 7184 if (adapter->flags & IGB_FLAG_DMAC) { 7185 u32 reg; 7186 7187 /* force threshold to 0. */ 7188 wr32(E1000_DMCTXTH, 0); 7189 7190 /* 7191 * DMA Coalescing high water mark needs to be greater 7192 * than the Rx threshold. Set hwm to PBA - max frame 7193 * size in 16B units, capping it at PBA - 6KB. 7194 */ 7195 hwm = 64 * pba - adapter->max_frame_size / 16; 7196 if (hwm < 64 * (pba - 6)) 7197 hwm = 64 * (pba - 6); 7198 reg = rd32(E1000_FCRTC); 7199 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 7200 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 7201 & E1000_FCRTC_RTH_COAL_MASK); 7202 wr32(E1000_FCRTC, reg); 7203 7204 /* 7205 * Set the DMA Coalescing Rx threshold to PBA - 2 * max 7206 * frame size, capping it at PBA - 10KB. 7207 */ 7208 dmac_thr = pba - adapter->max_frame_size / 512; 7209 if (dmac_thr < pba - 10) 7210 dmac_thr = pba - 10; 7211 reg = rd32(E1000_DMACR); 7212 reg &= ~E1000_DMACR_DMACTHR_MASK; 7213 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 7214 & E1000_DMACR_DMACTHR_MASK); 7215 7216 /* transition to L0x or L1 if available..*/ 7217 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 7218 7219 /* watchdog timer= +-1000 usec in 32usec intervals */ 7220 reg |= (1000 >> 5); 7221 7222 /* Disable BMC-to-OS Watchdog Enable */ 7223 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 7224 wr32(E1000_DMACR, reg); 7225 7226 /* 7227 * no lower threshold to disable 7228 * coalescing(smart fifb)-UTRESH=0 7229 */ 7230 wr32(E1000_DMCRTRH, 0); 7231 7232 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 7233 7234 wr32(E1000_DMCTLX, reg); 7235 7236 /* 7237 * free space in tx packet buffer to wake from 7238 * DMA coal 7239 */ 7240 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 7241 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 7242 7243 /* 7244 * make low power state decision controlled 7245 * by DMA coal 7246 */ 7247 reg = rd32(E1000_PCIEMISC); 7248 reg &= ~E1000_PCIEMISC_LX_DECISION; 7249 wr32(E1000_PCIEMISC, reg); 7250 } /* endif adapter->dmac is not disabled */ 7251 } else if (hw->mac.type == e1000_82580) { 7252 u32 reg = rd32(E1000_PCIEMISC); 7253 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 7254 wr32(E1000_DMACR, 0); 7255 } 7256} 7257 7258/* igb_main.c */ 7259