igb_main.c revision d34a15abfe370252de83e14e763cf7fcb8c84585
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25*******************************************************************************/ 26 27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 28 29#include <linux/module.h> 30#include <linux/types.h> 31#include <linux/init.h> 32#include <linux/bitops.h> 33#include <linux/vmalloc.h> 34#include <linux/pagemap.h> 35#include <linux/netdevice.h> 36#include <linux/ipv6.h> 37#include <linux/slab.h> 38#include <net/checksum.h> 39#include <net/ip6_checksum.h> 40#include <linux/net_tstamp.h> 41#include <linux/mii.h> 42#include <linux/ethtool.h> 43#include <linux/if.h> 44#include <linux/if_vlan.h> 45#include <linux/pci.h> 46#include <linux/pci-aspm.h> 47#include <linux/delay.h> 48#include <linux/interrupt.h> 49#include <linux/ip.h> 50#include <linux/tcp.h> 51#include <linux/sctp.h> 52#include <linux/if_ether.h> 53#include <linux/aer.h> 54#include <linux/prefetch.h> 55#include <linux/pm_runtime.h> 56#ifdef CONFIG_IGB_DCA 57#include <linux/dca.h> 58#endif 59#include <linux/i2c.h> 60#include "igb.h" 61 62#define MAJ 5 63#define MIN 0 64#define BUILD 5 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 66__stringify(BUILD) "-k" 67char igb_driver_name[] = "igb"; 68char igb_driver_version[] = DRV_VERSION; 69static const char igb_driver_string[] = 70 "Intel(R) Gigabit Ethernet Network Driver"; 71static const char igb_copyright[] = 72 "Copyright (c) 2007-2014 Intel Corporation."; 73 74static const struct e1000_info *igb_info_tbl[] = { 75 [board_82575] = &e1000_82575_info, 76}; 77 78static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 114 /* required last entry */ 115 {0, } 116}; 117 118MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 119 120void igb_reset(struct igb_adapter *); 121static int igb_setup_all_tx_resources(struct igb_adapter *); 122static int igb_setup_all_rx_resources(struct igb_adapter *); 123static void igb_free_all_tx_resources(struct igb_adapter *); 124static void igb_free_all_rx_resources(struct igb_adapter *); 125static void igb_setup_mrqc(struct igb_adapter *); 126static int igb_probe(struct pci_dev *, const struct pci_device_id *); 127static void igb_remove(struct pci_dev *pdev); 128static int igb_sw_init(struct igb_adapter *); 129static int igb_open(struct net_device *); 130static int igb_close(struct net_device *); 131static void igb_configure(struct igb_adapter *); 132static void igb_configure_tx(struct igb_adapter *); 133static void igb_configure_rx(struct igb_adapter *); 134static void igb_clean_all_tx_rings(struct igb_adapter *); 135static void igb_clean_all_rx_rings(struct igb_adapter *); 136static void igb_clean_tx_ring(struct igb_ring *); 137static void igb_clean_rx_ring(struct igb_ring *); 138static void igb_set_rx_mode(struct net_device *); 139static void igb_update_phy_info(unsigned long); 140static void igb_watchdog(unsigned long); 141static void igb_watchdog_task(struct work_struct *); 142static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 143static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 144 struct rtnl_link_stats64 *stats); 145static int igb_change_mtu(struct net_device *, int); 146static int igb_set_mac(struct net_device *, void *); 147static void igb_set_uta(struct igb_adapter *adapter); 148static irqreturn_t igb_intr(int irq, void *); 149static irqreturn_t igb_intr_msi(int irq, void *); 150static irqreturn_t igb_msix_other(int irq, void *); 151static irqreturn_t igb_msix_ring(int irq, void *); 152#ifdef CONFIG_IGB_DCA 153static void igb_update_dca(struct igb_q_vector *); 154static void igb_setup_dca(struct igb_adapter *); 155#endif /* CONFIG_IGB_DCA */ 156static int igb_poll(struct napi_struct *, int); 157static bool igb_clean_tx_irq(struct igb_q_vector *); 158static bool igb_clean_rx_irq(struct igb_q_vector *, int); 159static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 160static void igb_tx_timeout(struct net_device *); 161static void igb_reset_task(struct work_struct *); 162static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); 163static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 164static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 165static void igb_restore_vlan(struct igb_adapter *); 166static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 167static void igb_ping_all_vfs(struct igb_adapter *); 168static void igb_msg_task(struct igb_adapter *); 169static void igb_vmm_control(struct igb_adapter *); 170static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 171static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 172static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 173static int igb_ndo_set_vf_vlan(struct net_device *netdev, 174 int vf, u16 vlan, u8 qos); 175static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 176static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 177 bool setting); 178static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 179 struct ifla_vf_info *ivi); 180static void igb_check_vf_rate_limit(struct igb_adapter *); 181 182#ifdef CONFIG_PCI_IOV 183static int igb_vf_configure(struct igb_adapter *adapter, int vf); 184static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 185#endif 186 187#ifdef CONFIG_PM 188#ifdef CONFIG_PM_SLEEP 189static int igb_suspend(struct device *); 190#endif 191static int igb_resume(struct device *); 192#ifdef CONFIG_PM_RUNTIME 193static int igb_runtime_suspend(struct device *dev); 194static int igb_runtime_resume(struct device *dev); 195static int igb_runtime_idle(struct device *dev); 196#endif 197static const struct dev_pm_ops igb_pm_ops = { 198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 200 igb_runtime_idle) 201}; 202#endif 203static void igb_shutdown(struct pci_dev *); 204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 205#ifdef CONFIG_IGB_DCA 206static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 207static struct notifier_block dca_notifier = { 208 .notifier_call = igb_notify_dca, 209 .next = NULL, 210 .priority = 0 211}; 212#endif 213#ifdef CONFIG_NET_POLL_CONTROLLER 214/* for netdump / net console */ 215static void igb_netpoll(struct net_device *); 216#endif 217#ifdef CONFIG_PCI_IOV 218static unsigned int max_vfs = 0; 219module_param(max_vfs, uint, 0); 220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 221#endif /* CONFIG_PCI_IOV */ 222 223static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 224 pci_channel_state_t); 225static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 226static void igb_io_resume(struct pci_dev *); 227 228static const struct pci_error_handlers igb_err_handler = { 229 .error_detected = igb_io_error_detected, 230 .slot_reset = igb_io_slot_reset, 231 .resume = igb_io_resume, 232}; 233 234static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 235 236static struct pci_driver igb_driver = { 237 .name = igb_driver_name, 238 .id_table = igb_pci_tbl, 239 .probe = igb_probe, 240 .remove = igb_remove, 241#ifdef CONFIG_PM 242 .driver.pm = &igb_pm_ops, 243#endif 244 .shutdown = igb_shutdown, 245 .sriov_configure = igb_pci_sriov_configure, 246 .err_handler = &igb_err_handler 247}; 248 249MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 250MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 251MODULE_LICENSE("GPL"); 252MODULE_VERSION(DRV_VERSION); 253 254#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 255static int debug = -1; 256module_param(debug, int, 0); 257MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 258 259struct igb_reg_info { 260 u32 ofs; 261 char *name; 262}; 263 264static const struct igb_reg_info igb_reg_info_tbl[] = { 265 266 /* General Registers */ 267 {E1000_CTRL, "CTRL"}, 268 {E1000_STATUS, "STATUS"}, 269 {E1000_CTRL_EXT, "CTRL_EXT"}, 270 271 /* Interrupt Registers */ 272 {E1000_ICR, "ICR"}, 273 274 /* RX Registers */ 275 {E1000_RCTL, "RCTL"}, 276 {E1000_RDLEN(0), "RDLEN"}, 277 {E1000_RDH(0), "RDH"}, 278 {E1000_RDT(0), "RDT"}, 279 {E1000_RXDCTL(0), "RXDCTL"}, 280 {E1000_RDBAL(0), "RDBAL"}, 281 {E1000_RDBAH(0), "RDBAH"}, 282 283 /* TX Registers */ 284 {E1000_TCTL, "TCTL"}, 285 {E1000_TDBAL(0), "TDBAL"}, 286 {E1000_TDBAH(0), "TDBAH"}, 287 {E1000_TDLEN(0), "TDLEN"}, 288 {E1000_TDH(0), "TDH"}, 289 {E1000_TDT(0), "TDT"}, 290 {E1000_TXDCTL(0), "TXDCTL"}, 291 {E1000_TDFH, "TDFH"}, 292 {E1000_TDFT, "TDFT"}, 293 {E1000_TDFHS, "TDFHS"}, 294 {E1000_TDFPC, "TDFPC"}, 295 296 /* List Terminator */ 297 {} 298}; 299 300/* igb_regdump - register printout routine */ 301static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 302{ 303 int n = 0; 304 char rname[16]; 305 u32 regs[8]; 306 307 switch (reginfo->ofs) { 308 case E1000_RDLEN(0): 309 for (n = 0; n < 4; n++) 310 regs[n] = rd32(E1000_RDLEN(n)); 311 break; 312 case E1000_RDH(0): 313 for (n = 0; n < 4; n++) 314 regs[n] = rd32(E1000_RDH(n)); 315 break; 316 case E1000_RDT(0): 317 for (n = 0; n < 4; n++) 318 regs[n] = rd32(E1000_RDT(n)); 319 break; 320 case E1000_RXDCTL(0): 321 for (n = 0; n < 4; n++) 322 regs[n] = rd32(E1000_RXDCTL(n)); 323 break; 324 case E1000_RDBAL(0): 325 for (n = 0; n < 4; n++) 326 regs[n] = rd32(E1000_RDBAL(n)); 327 break; 328 case E1000_RDBAH(0): 329 for (n = 0; n < 4; n++) 330 regs[n] = rd32(E1000_RDBAH(n)); 331 break; 332 case E1000_TDBAL(0): 333 for (n = 0; n < 4; n++) 334 regs[n] = rd32(E1000_RDBAL(n)); 335 break; 336 case E1000_TDBAH(0): 337 for (n = 0; n < 4; n++) 338 regs[n] = rd32(E1000_TDBAH(n)); 339 break; 340 case E1000_TDLEN(0): 341 for (n = 0; n < 4; n++) 342 regs[n] = rd32(E1000_TDLEN(n)); 343 break; 344 case E1000_TDH(0): 345 for (n = 0; n < 4; n++) 346 regs[n] = rd32(E1000_TDH(n)); 347 break; 348 case E1000_TDT(0): 349 for (n = 0; n < 4; n++) 350 regs[n] = rd32(E1000_TDT(n)); 351 break; 352 case E1000_TXDCTL(0): 353 for (n = 0; n < 4; n++) 354 regs[n] = rd32(E1000_TXDCTL(n)); 355 break; 356 default: 357 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 358 return; 359 } 360 361 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 362 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 363 regs[2], regs[3]); 364} 365 366/* igb_dump - Print registers, Tx-rings and Rx-rings */ 367static void igb_dump(struct igb_adapter *adapter) 368{ 369 struct net_device *netdev = adapter->netdev; 370 struct e1000_hw *hw = &adapter->hw; 371 struct igb_reg_info *reginfo; 372 struct igb_ring *tx_ring; 373 union e1000_adv_tx_desc *tx_desc; 374 struct my_u0 { u64 a; u64 b; } *u0; 375 struct igb_ring *rx_ring; 376 union e1000_adv_rx_desc *rx_desc; 377 u32 staterr; 378 u16 i, n; 379 380 if (!netif_msg_hw(adapter)) 381 return; 382 383 /* Print netdevice Info */ 384 if (netdev) { 385 dev_info(&adapter->pdev->dev, "Net device Info\n"); 386 pr_info("Device Name state trans_start last_rx\n"); 387 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 388 netdev->state, netdev->trans_start, netdev->last_rx); 389 } 390 391 /* Print Registers */ 392 dev_info(&adapter->pdev->dev, "Register Dump\n"); 393 pr_info(" Register Name Value\n"); 394 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 395 reginfo->name; reginfo++) { 396 igb_regdump(hw, reginfo); 397 } 398 399 /* Print TX Ring Summary */ 400 if (!netdev || !netif_running(netdev)) 401 goto exit; 402 403 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 404 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 405 for (n = 0; n < adapter->num_tx_queues; n++) { 406 struct igb_tx_buffer *buffer_info; 407 tx_ring = adapter->tx_ring[n]; 408 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 409 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 410 n, tx_ring->next_to_use, tx_ring->next_to_clean, 411 (u64)dma_unmap_addr(buffer_info, dma), 412 dma_unmap_len(buffer_info, len), 413 buffer_info->next_to_watch, 414 (u64)buffer_info->time_stamp); 415 } 416 417 /* Print TX Rings */ 418 if (!netif_msg_tx_done(adapter)) 419 goto rx_ring_summary; 420 421 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 422 423 /* Transmit Descriptor Formats 424 * 425 * Advanced Transmit Descriptor 426 * +--------------------------------------------------------------+ 427 * 0 | Buffer Address [63:0] | 428 * +--------------------------------------------------------------+ 429 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 430 * +--------------------------------------------------------------+ 431 * 63 46 45 40 39 38 36 35 32 31 24 15 0 432 */ 433 434 for (n = 0; n < adapter->num_tx_queues; n++) { 435 tx_ring = adapter->tx_ring[n]; 436 pr_info("------------------------------------\n"); 437 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 438 pr_info("------------------------------------\n"); 439 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 440 441 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 442 const char *next_desc; 443 struct igb_tx_buffer *buffer_info; 444 tx_desc = IGB_TX_DESC(tx_ring, i); 445 buffer_info = &tx_ring->tx_buffer_info[i]; 446 u0 = (struct my_u0 *)tx_desc; 447 if (i == tx_ring->next_to_use && 448 i == tx_ring->next_to_clean) 449 next_desc = " NTC/U"; 450 else if (i == tx_ring->next_to_use) 451 next_desc = " NTU"; 452 else if (i == tx_ring->next_to_clean) 453 next_desc = " NTC"; 454 else 455 next_desc = ""; 456 457 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 458 i, le64_to_cpu(u0->a), 459 le64_to_cpu(u0->b), 460 (u64)dma_unmap_addr(buffer_info, dma), 461 dma_unmap_len(buffer_info, len), 462 buffer_info->next_to_watch, 463 (u64)buffer_info->time_stamp, 464 buffer_info->skb, next_desc); 465 466 if (netif_msg_pktdata(adapter) && buffer_info->skb) 467 print_hex_dump(KERN_INFO, "", 468 DUMP_PREFIX_ADDRESS, 469 16, 1, buffer_info->skb->data, 470 dma_unmap_len(buffer_info, len), 471 true); 472 } 473 } 474 475 /* Print RX Rings Summary */ 476rx_ring_summary: 477 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 478 pr_info("Queue [NTU] [NTC]\n"); 479 for (n = 0; n < adapter->num_rx_queues; n++) { 480 rx_ring = adapter->rx_ring[n]; 481 pr_info(" %5d %5X %5X\n", 482 n, rx_ring->next_to_use, rx_ring->next_to_clean); 483 } 484 485 /* Print RX Rings */ 486 if (!netif_msg_rx_status(adapter)) 487 goto exit; 488 489 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 490 491 /* Advanced Receive Descriptor (Read) Format 492 * 63 1 0 493 * +-----------------------------------------------------+ 494 * 0 | Packet Buffer Address [63:1] |A0/NSE| 495 * +----------------------------------------------+------+ 496 * 8 | Header Buffer Address [63:1] | DD | 497 * +-----------------------------------------------------+ 498 * 499 * 500 * Advanced Receive Descriptor (Write-Back) Format 501 * 502 * 63 48 47 32 31 30 21 20 17 16 4 3 0 503 * +------------------------------------------------------+ 504 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 505 * | Checksum Ident | | | | Type | Type | 506 * +------------------------------------------------------+ 507 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 508 * +------------------------------------------------------+ 509 * 63 48 47 32 31 20 19 0 510 */ 511 512 for (n = 0; n < adapter->num_rx_queues; n++) { 513 rx_ring = adapter->rx_ring[n]; 514 pr_info("------------------------------------\n"); 515 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 516 pr_info("------------------------------------\n"); 517 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 518 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 519 520 for (i = 0; i < rx_ring->count; i++) { 521 const char *next_desc; 522 struct igb_rx_buffer *buffer_info; 523 buffer_info = &rx_ring->rx_buffer_info[i]; 524 rx_desc = IGB_RX_DESC(rx_ring, i); 525 u0 = (struct my_u0 *)rx_desc; 526 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 527 528 if (i == rx_ring->next_to_use) 529 next_desc = " NTU"; 530 else if (i == rx_ring->next_to_clean) 531 next_desc = " NTC"; 532 else 533 next_desc = ""; 534 535 if (staterr & E1000_RXD_STAT_DD) { 536 /* Descriptor Done */ 537 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 538 "RWB", i, 539 le64_to_cpu(u0->a), 540 le64_to_cpu(u0->b), 541 next_desc); 542 } else { 543 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 544 "R ", i, 545 le64_to_cpu(u0->a), 546 le64_to_cpu(u0->b), 547 (u64)buffer_info->dma, 548 next_desc); 549 550 if (netif_msg_pktdata(adapter) && 551 buffer_info->dma && buffer_info->page) { 552 print_hex_dump(KERN_INFO, "", 553 DUMP_PREFIX_ADDRESS, 554 16, 1, 555 page_address(buffer_info->page) + 556 buffer_info->page_offset, 557 IGB_RX_BUFSZ, true); 558 } 559 } 560 } 561 } 562 563exit: 564 return; 565} 566 567/** 568 * igb_get_i2c_data - Reads the I2C SDA data bit 569 * @hw: pointer to hardware structure 570 * @i2cctl: Current value of I2CCTL register 571 * 572 * Returns the I2C data bit value 573 **/ 574static int igb_get_i2c_data(void *data) 575{ 576 struct igb_adapter *adapter = (struct igb_adapter *)data; 577 struct e1000_hw *hw = &adapter->hw; 578 s32 i2cctl = rd32(E1000_I2CPARAMS); 579 580 return ((i2cctl & E1000_I2C_DATA_IN) != 0); 581} 582 583/** 584 * igb_set_i2c_data - Sets the I2C data bit 585 * @data: pointer to hardware structure 586 * @state: I2C data value (0 or 1) to set 587 * 588 * Sets the I2C data bit 589 **/ 590static void igb_set_i2c_data(void *data, int state) 591{ 592 struct igb_adapter *adapter = (struct igb_adapter *)data; 593 struct e1000_hw *hw = &adapter->hw; 594 s32 i2cctl = rd32(E1000_I2CPARAMS); 595 596 if (state) 597 i2cctl |= E1000_I2C_DATA_OUT; 598 else 599 i2cctl &= ~E1000_I2C_DATA_OUT; 600 601 i2cctl &= ~E1000_I2C_DATA_OE_N; 602 i2cctl |= E1000_I2C_CLK_OE_N; 603 wr32(E1000_I2CPARAMS, i2cctl); 604 wrfl(); 605 606} 607 608/** 609 * igb_set_i2c_clk - Sets the I2C SCL clock 610 * @data: pointer to hardware structure 611 * @state: state to set clock 612 * 613 * Sets the I2C clock line to state 614 **/ 615static void igb_set_i2c_clk(void *data, int state) 616{ 617 struct igb_adapter *adapter = (struct igb_adapter *)data; 618 struct e1000_hw *hw = &adapter->hw; 619 s32 i2cctl = rd32(E1000_I2CPARAMS); 620 621 if (state) { 622 i2cctl |= E1000_I2C_CLK_OUT; 623 i2cctl &= ~E1000_I2C_CLK_OE_N; 624 } else { 625 i2cctl &= ~E1000_I2C_CLK_OUT; 626 i2cctl &= ~E1000_I2C_CLK_OE_N; 627 } 628 wr32(E1000_I2CPARAMS, i2cctl); 629 wrfl(); 630} 631 632/** 633 * igb_get_i2c_clk - Gets the I2C SCL clock state 634 * @data: pointer to hardware structure 635 * 636 * Gets the I2C clock state 637 **/ 638static int igb_get_i2c_clk(void *data) 639{ 640 struct igb_adapter *adapter = (struct igb_adapter *)data; 641 struct e1000_hw *hw = &adapter->hw; 642 s32 i2cctl = rd32(E1000_I2CPARAMS); 643 644 return ((i2cctl & E1000_I2C_CLK_IN) != 0); 645} 646 647static const struct i2c_algo_bit_data igb_i2c_algo = { 648 .setsda = igb_set_i2c_data, 649 .setscl = igb_set_i2c_clk, 650 .getsda = igb_get_i2c_data, 651 .getscl = igb_get_i2c_clk, 652 .udelay = 5, 653 .timeout = 20, 654}; 655 656/** 657 * igb_get_hw_dev - return device 658 * @hw: pointer to hardware structure 659 * 660 * used by hardware layer to print debugging information 661 **/ 662struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 663{ 664 struct igb_adapter *adapter = hw->back; 665 return adapter->netdev; 666} 667 668/** 669 * igb_init_module - Driver Registration Routine 670 * 671 * igb_init_module is the first routine called when the driver is 672 * loaded. All it does is register with the PCI subsystem. 673 **/ 674static int __init igb_init_module(void) 675{ 676 int ret; 677 pr_info("%s - version %s\n", 678 igb_driver_string, igb_driver_version); 679 680 pr_info("%s\n", igb_copyright); 681 682#ifdef CONFIG_IGB_DCA 683 dca_register_notify(&dca_notifier); 684#endif 685 ret = pci_register_driver(&igb_driver); 686 return ret; 687} 688 689module_init(igb_init_module); 690 691/** 692 * igb_exit_module - Driver Exit Cleanup Routine 693 * 694 * igb_exit_module is called just before the driver is removed 695 * from memory. 696 **/ 697static void __exit igb_exit_module(void) 698{ 699#ifdef CONFIG_IGB_DCA 700 dca_unregister_notify(&dca_notifier); 701#endif 702 pci_unregister_driver(&igb_driver); 703} 704 705module_exit(igb_exit_module); 706 707#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 708/** 709 * igb_cache_ring_register - Descriptor ring to register mapping 710 * @adapter: board private structure to initialize 711 * 712 * Once we know the feature-set enabled for the device, we'll cache 713 * the register offset the descriptor ring is assigned to. 714 **/ 715static void igb_cache_ring_register(struct igb_adapter *adapter) 716{ 717 int i = 0, j = 0; 718 u32 rbase_offset = adapter->vfs_allocated_count; 719 720 switch (adapter->hw.mac.type) { 721 case e1000_82576: 722 /* The queues are allocated for virtualization such that VF 0 723 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 724 * In order to avoid collision we start at the first free queue 725 * and continue consuming queues in the same sequence 726 */ 727 if (adapter->vfs_allocated_count) { 728 for (; i < adapter->rss_queues; i++) 729 adapter->rx_ring[i]->reg_idx = rbase_offset + 730 Q_IDX_82576(i); 731 } 732 case e1000_82575: 733 case e1000_82580: 734 case e1000_i350: 735 case e1000_i354: 736 case e1000_i210: 737 case e1000_i211: 738 default: 739 for (; i < adapter->num_rx_queues; i++) 740 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 741 for (; j < adapter->num_tx_queues; j++) 742 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 743 break; 744 } 745} 746 747u32 igb_rd32(struct e1000_hw *hw, u32 reg) 748{ 749 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 750 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 751 u32 value = 0; 752 753 if (E1000_REMOVED(hw_addr)) 754 return ~value; 755 756 value = readl(&hw_addr[reg]); 757 758 /* reads should not return all F's */ 759 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 760 struct net_device *netdev = igb->netdev; 761 hw->hw_addr = NULL; 762 netif_device_detach(netdev); 763 netdev_err(netdev, "PCIe link lost, device now detached\n"); 764 } 765 766 return value; 767} 768 769/** 770 * igb_write_ivar - configure ivar for given MSI-X vector 771 * @hw: pointer to the HW structure 772 * @msix_vector: vector number we are allocating to a given ring 773 * @index: row index of IVAR register to write within IVAR table 774 * @offset: column offset of in IVAR, should be multiple of 8 775 * 776 * This function is intended to handle the writing of the IVAR register 777 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 778 * each containing an cause allocation for an Rx and Tx ring, and a 779 * variable number of rows depending on the number of queues supported. 780 **/ 781static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 782 int index, int offset) 783{ 784 u32 ivar = array_rd32(E1000_IVAR0, index); 785 786 /* clear any bits that are currently set */ 787 ivar &= ~((u32)0xFF << offset); 788 789 /* write vector and valid bit */ 790 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 791 792 array_wr32(E1000_IVAR0, index, ivar); 793} 794 795#define IGB_N0_QUEUE -1 796static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 797{ 798 struct igb_adapter *adapter = q_vector->adapter; 799 struct e1000_hw *hw = &adapter->hw; 800 int rx_queue = IGB_N0_QUEUE; 801 int tx_queue = IGB_N0_QUEUE; 802 u32 msixbm = 0; 803 804 if (q_vector->rx.ring) 805 rx_queue = q_vector->rx.ring->reg_idx; 806 if (q_vector->tx.ring) 807 tx_queue = q_vector->tx.ring->reg_idx; 808 809 switch (hw->mac.type) { 810 case e1000_82575: 811 /* The 82575 assigns vectors using a bitmask, which matches the 812 * bitmask for the EICR/EIMS/EIMC registers. To assign one 813 * or more queues to a vector, we write the appropriate bits 814 * into the MSIXBM register for that vector. 815 */ 816 if (rx_queue > IGB_N0_QUEUE) 817 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 818 if (tx_queue > IGB_N0_QUEUE) 819 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 820 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 821 msixbm |= E1000_EIMS_OTHER; 822 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 823 q_vector->eims_value = msixbm; 824 break; 825 case e1000_82576: 826 /* 82576 uses a table that essentially consists of 2 columns 827 * with 8 rows. The ordering is column-major so we use the 828 * lower 3 bits as the row index, and the 4th bit as the 829 * column offset. 830 */ 831 if (rx_queue > IGB_N0_QUEUE) 832 igb_write_ivar(hw, msix_vector, 833 rx_queue & 0x7, 834 (rx_queue & 0x8) << 1); 835 if (tx_queue > IGB_N0_QUEUE) 836 igb_write_ivar(hw, msix_vector, 837 tx_queue & 0x7, 838 ((tx_queue & 0x8) << 1) + 8); 839 q_vector->eims_value = 1 << msix_vector; 840 break; 841 case e1000_82580: 842 case e1000_i350: 843 case e1000_i354: 844 case e1000_i210: 845 case e1000_i211: 846 /* On 82580 and newer adapters the scheme is similar to 82576 847 * however instead of ordering column-major we have things 848 * ordered row-major. So we traverse the table by using 849 * bit 0 as the column offset, and the remaining bits as the 850 * row index. 851 */ 852 if (rx_queue > IGB_N0_QUEUE) 853 igb_write_ivar(hw, msix_vector, 854 rx_queue >> 1, 855 (rx_queue & 0x1) << 4); 856 if (tx_queue > IGB_N0_QUEUE) 857 igb_write_ivar(hw, msix_vector, 858 tx_queue >> 1, 859 ((tx_queue & 0x1) << 4) + 8); 860 q_vector->eims_value = 1 << msix_vector; 861 break; 862 default: 863 BUG(); 864 break; 865 } 866 867 /* add q_vector eims value to global eims_enable_mask */ 868 adapter->eims_enable_mask |= q_vector->eims_value; 869 870 /* configure q_vector to set itr on first interrupt */ 871 q_vector->set_itr = 1; 872} 873 874/** 875 * igb_configure_msix - Configure MSI-X hardware 876 * @adapter: board private structure to initialize 877 * 878 * igb_configure_msix sets up the hardware to properly 879 * generate MSI-X interrupts. 880 **/ 881static void igb_configure_msix(struct igb_adapter *adapter) 882{ 883 u32 tmp; 884 int i, vector = 0; 885 struct e1000_hw *hw = &adapter->hw; 886 887 adapter->eims_enable_mask = 0; 888 889 /* set vector for other causes, i.e. link changes */ 890 switch (hw->mac.type) { 891 case e1000_82575: 892 tmp = rd32(E1000_CTRL_EXT); 893 /* enable MSI-X PBA support*/ 894 tmp |= E1000_CTRL_EXT_PBA_CLR; 895 896 /* Auto-Mask interrupts upon ICR read. */ 897 tmp |= E1000_CTRL_EXT_EIAME; 898 tmp |= E1000_CTRL_EXT_IRCA; 899 900 wr32(E1000_CTRL_EXT, tmp); 901 902 /* enable msix_other interrupt */ 903 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 904 adapter->eims_other = E1000_EIMS_OTHER; 905 906 break; 907 908 case e1000_82576: 909 case e1000_82580: 910 case e1000_i350: 911 case e1000_i354: 912 case e1000_i210: 913 case e1000_i211: 914 /* Turn on MSI-X capability first, or our settings 915 * won't stick. And it will take days to debug. 916 */ 917 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 918 E1000_GPIE_PBA | E1000_GPIE_EIAME | 919 E1000_GPIE_NSICR); 920 921 /* enable msix_other interrupt */ 922 adapter->eims_other = 1 << vector; 923 tmp = (vector++ | E1000_IVAR_VALID) << 8; 924 925 wr32(E1000_IVAR_MISC, tmp); 926 break; 927 default: 928 /* do nothing, since nothing else supports MSI-X */ 929 break; 930 } /* switch (hw->mac.type) */ 931 932 adapter->eims_enable_mask |= adapter->eims_other; 933 934 for (i = 0; i < adapter->num_q_vectors; i++) 935 igb_assign_vector(adapter->q_vector[i], vector++); 936 937 wrfl(); 938} 939 940/** 941 * igb_request_msix - Initialize MSI-X interrupts 942 * @adapter: board private structure to initialize 943 * 944 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 945 * kernel. 946 **/ 947static int igb_request_msix(struct igb_adapter *adapter) 948{ 949 struct net_device *netdev = adapter->netdev; 950 struct e1000_hw *hw = &adapter->hw; 951 int i, err = 0, vector = 0, free_vector = 0; 952 953 err = request_irq(adapter->msix_entries[vector].vector, 954 igb_msix_other, 0, netdev->name, adapter); 955 if (err) 956 goto err_out; 957 958 for (i = 0; i < adapter->num_q_vectors; i++) { 959 struct igb_q_vector *q_vector = adapter->q_vector[i]; 960 961 vector++; 962 963 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 964 965 if (q_vector->rx.ring && q_vector->tx.ring) 966 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 967 q_vector->rx.ring->queue_index); 968 else if (q_vector->tx.ring) 969 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 970 q_vector->tx.ring->queue_index); 971 else if (q_vector->rx.ring) 972 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 973 q_vector->rx.ring->queue_index); 974 else 975 sprintf(q_vector->name, "%s-unused", netdev->name); 976 977 err = request_irq(adapter->msix_entries[vector].vector, 978 igb_msix_ring, 0, q_vector->name, 979 q_vector); 980 if (err) 981 goto err_free; 982 } 983 984 igb_configure_msix(adapter); 985 return 0; 986 987err_free: 988 /* free already assigned IRQs */ 989 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 990 991 vector--; 992 for (i = 0; i < vector; i++) { 993 free_irq(adapter->msix_entries[free_vector++].vector, 994 adapter->q_vector[i]); 995 } 996err_out: 997 return err; 998} 999 1000/** 1001 * igb_free_q_vector - Free memory allocated for specific interrupt vector 1002 * @adapter: board private structure to initialize 1003 * @v_idx: Index of vector to be freed 1004 * 1005 * This function frees the memory allocated to the q_vector. 1006 **/ 1007static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1008{ 1009 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1010 1011 adapter->q_vector[v_idx] = NULL; 1012 1013 /* igb_get_stats64() might access the rings on this vector, 1014 * we must wait a grace period before freeing it. 1015 */ 1016 kfree_rcu(q_vector, rcu); 1017} 1018 1019/** 1020 * igb_reset_q_vector - Reset config for interrupt vector 1021 * @adapter: board private structure to initialize 1022 * @v_idx: Index of vector to be reset 1023 * 1024 * If NAPI is enabled it will delete any references to the 1025 * NAPI struct. This is preparation for igb_free_q_vector. 1026 **/ 1027static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1028{ 1029 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1030 1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1032 * allocated. So, q_vector is NULL so we should stop here. 1033 */ 1034 if (!q_vector) 1035 return; 1036 1037 if (q_vector->tx.ring) 1038 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1039 1040 if (q_vector->rx.ring) 1041 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; 1042 1043 netif_napi_del(&q_vector->napi); 1044 1045} 1046 1047static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1048{ 1049 int v_idx = adapter->num_q_vectors; 1050 1051 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1052 pci_disable_msix(adapter->pdev); 1053 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1054 pci_disable_msi(adapter->pdev); 1055 1056 while (v_idx--) 1057 igb_reset_q_vector(adapter, v_idx); 1058} 1059 1060/** 1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1062 * @adapter: board private structure to initialize 1063 * 1064 * This function frees the memory allocated to the q_vectors. In addition if 1065 * NAPI is enabled it will delete any references to the NAPI struct prior 1066 * to freeing the q_vector. 1067 **/ 1068static void igb_free_q_vectors(struct igb_adapter *adapter) 1069{ 1070 int v_idx = adapter->num_q_vectors; 1071 1072 adapter->num_tx_queues = 0; 1073 adapter->num_rx_queues = 0; 1074 adapter->num_q_vectors = 0; 1075 1076 while (v_idx--) { 1077 igb_reset_q_vector(adapter, v_idx); 1078 igb_free_q_vector(adapter, v_idx); 1079 } 1080} 1081 1082/** 1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1084 * @adapter: board private structure to initialize 1085 * 1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1087 * MSI-X interrupts allocated. 1088 */ 1089static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1090{ 1091 igb_free_q_vectors(adapter); 1092 igb_reset_interrupt_capability(adapter); 1093} 1094 1095/** 1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1097 * @adapter: board private structure to initialize 1098 * @msix: boolean value of MSIX capability 1099 * 1100 * Attempt to configure interrupts using the best available 1101 * capabilities of the hardware and kernel. 1102 **/ 1103static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1104{ 1105 int err; 1106 int numvecs, i; 1107 1108 if (!msix) 1109 goto msi_only; 1110 adapter->flags |= IGB_FLAG_HAS_MSIX; 1111 1112 /* Number of supported queues. */ 1113 adapter->num_rx_queues = adapter->rss_queues; 1114 if (adapter->vfs_allocated_count) 1115 adapter->num_tx_queues = 1; 1116 else 1117 adapter->num_tx_queues = adapter->rss_queues; 1118 1119 /* start with one vector for every Rx queue */ 1120 numvecs = adapter->num_rx_queues; 1121 1122 /* if Tx handler is separate add 1 for every Tx queue */ 1123 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1124 numvecs += adapter->num_tx_queues; 1125 1126 /* store the number of vectors reserved for queues */ 1127 adapter->num_q_vectors = numvecs; 1128 1129 /* add 1 vector for link status interrupts */ 1130 numvecs++; 1131 for (i = 0; i < numvecs; i++) 1132 adapter->msix_entries[i].entry = i; 1133 1134 err = pci_enable_msix_range(adapter->pdev, 1135 adapter->msix_entries, 1136 numvecs, 1137 numvecs); 1138 if (err > 0) 1139 return; 1140 1141 igb_reset_interrupt_capability(adapter); 1142 1143 /* If we can't do MSI-X, try MSI */ 1144msi_only: 1145 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1146#ifdef CONFIG_PCI_IOV 1147 /* disable SR-IOV for non MSI-X configurations */ 1148 if (adapter->vf_data) { 1149 struct e1000_hw *hw = &adapter->hw; 1150 /* disable iov and allow time for transactions to clear */ 1151 pci_disable_sriov(adapter->pdev); 1152 msleep(500); 1153 1154 kfree(adapter->vf_data); 1155 adapter->vf_data = NULL; 1156 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1157 wrfl(); 1158 msleep(100); 1159 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1160 } 1161#endif 1162 adapter->vfs_allocated_count = 0; 1163 adapter->rss_queues = 1; 1164 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1165 adapter->num_rx_queues = 1; 1166 adapter->num_tx_queues = 1; 1167 adapter->num_q_vectors = 1; 1168 if (!pci_enable_msi(adapter->pdev)) 1169 adapter->flags |= IGB_FLAG_HAS_MSI; 1170} 1171 1172static void igb_add_ring(struct igb_ring *ring, 1173 struct igb_ring_container *head) 1174{ 1175 head->ring = ring; 1176 head->count++; 1177} 1178 1179/** 1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1181 * @adapter: board private structure to initialize 1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1183 * @v_idx: index of vector in adapter struct 1184 * @txr_count: total number of Tx rings to allocate 1185 * @txr_idx: index of first Tx ring to allocate 1186 * @rxr_count: total number of Rx rings to allocate 1187 * @rxr_idx: index of first Rx ring to allocate 1188 * 1189 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1190 **/ 1191static int igb_alloc_q_vector(struct igb_adapter *adapter, 1192 int v_count, int v_idx, 1193 int txr_count, int txr_idx, 1194 int rxr_count, int rxr_idx) 1195{ 1196 struct igb_q_vector *q_vector; 1197 struct igb_ring *ring; 1198 int ring_count, size; 1199 1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1201 if (txr_count > 1 || rxr_count > 1) 1202 return -ENOMEM; 1203 1204 ring_count = txr_count + rxr_count; 1205 size = sizeof(struct igb_q_vector) + 1206 (sizeof(struct igb_ring) * ring_count); 1207 1208 /* allocate q_vector and rings */ 1209 q_vector = adapter->q_vector[v_idx]; 1210 if (!q_vector) 1211 q_vector = kzalloc(size, GFP_KERNEL); 1212 if (!q_vector) 1213 return -ENOMEM; 1214 1215 /* initialize NAPI */ 1216 netif_napi_add(adapter->netdev, &q_vector->napi, 1217 igb_poll, 64); 1218 1219 /* tie q_vector and adapter together */ 1220 adapter->q_vector[v_idx] = q_vector; 1221 q_vector->adapter = adapter; 1222 1223 /* initialize work limits */ 1224 q_vector->tx.work_limit = adapter->tx_work_limit; 1225 1226 /* initialize ITR configuration */ 1227 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); 1228 q_vector->itr_val = IGB_START_ITR; 1229 1230 /* initialize pointer to rings */ 1231 ring = q_vector->ring; 1232 1233 /* intialize ITR */ 1234 if (rxr_count) { 1235 /* rx or rx/tx vector */ 1236 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1237 q_vector->itr_val = adapter->rx_itr_setting; 1238 } else { 1239 /* tx only vector */ 1240 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1241 q_vector->itr_val = adapter->tx_itr_setting; 1242 } 1243 1244 if (txr_count) { 1245 /* assign generic ring traits */ 1246 ring->dev = &adapter->pdev->dev; 1247 ring->netdev = adapter->netdev; 1248 1249 /* configure backlink on ring */ 1250 ring->q_vector = q_vector; 1251 1252 /* update q_vector Tx values */ 1253 igb_add_ring(ring, &q_vector->tx); 1254 1255 /* For 82575, context index must be unique per ring. */ 1256 if (adapter->hw.mac.type == e1000_82575) 1257 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1258 1259 /* apply Tx specific ring traits */ 1260 ring->count = adapter->tx_ring_count; 1261 ring->queue_index = txr_idx; 1262 1263 u64_stats_init(&ring->tx_syncp); 1264 u64_stats_init(&ring->tx_syncp2); 1265 1266 /* assign ring to adapter */ 1267 adapter->tx_ring[txr_idx] = ring; 1268 1269 /* push pointer to next ring */ 1270 ring++; 1271 } 1272 1273 if (rxr_count) { 1274 /* assign generic ring traits */ 1275 ring->dev = &adapter->pdev->dev; 1276 ring->netdev = adapter->netdev; 1277 1278 /* configure backlink on ring */ 1279 ring->q_vector = q_vector; 1280 1281 /* update q_vector Rx values */ 1282 igb_add_ring(ring, &q_vector->rx); 1283 1284 /* set flag indicating ring supports SCTP checksum offload */ 1285 if (adapter->hw.mac.type >= e1000_82576) 1286 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1287 1288 /* 1289 * On i350, i354, i210, and i211, loopback VLAN packets 1290 * have the tag byte-swapped. 1291 */ 1292 if (adapter->hw.mac.type >= e1000_i350) 1293 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1294 1295 /* apply Rx specific ring traits */ 1296 ring->count = adapter->rx_ring_count; 1297 ring->queue_index = rxr_idx; 1298 1299 u64_stats_init(&ring->rx_syncp); 1300 1301 /* assign ring to adapter */ 1302 adapter->rx_ring[rxr_idx] = ring; 1303 } 1304 1305 return 0; 1306} 1307 1308 1309/** 1310 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1311 * @adapter: board private structure to initialize 1312 * 1313 * We allocate one q_vector per queue interrupt. If allocation fails we 1314 * return -ENOMEM. 1315 **/ 1316static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1317{ 1318 int q_vectors = adapter->num_q_vectors; 1319 int rxr_remaining = adapter->num_rx_queues; 1320 int txr_remaining = adapter->num_tx_queues; 1321 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1322 int err; 1323 1324 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1325 for (; rxr_remaining; v_idx++) { 1326 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1327 0, 0, 1, rxr_idx); 1328 1329 if (err) 1330 goto err_out; 1331 1332 /* update counts and index */ 1333 rxr_remaining--; 1334 rxr_idx++; 1335 } 1336 } 1337 1338 for (; v_idx < q_vectors; v_idx++) { 1339 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1340 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1341 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1342 tqpv, txr_idx, rqpv, rxr_idx); 1343 1344 if (err) 1345 goto err_out; 1346 1347 /* update counts and index */ 1348 rxr_remaining -= rqpv; 1349 txr_remaining -= tqpv; 1350 rxr_idx++; 1351 txr_idx++; 1352 } 1353 1354 return 0; 1355 1356err_out: 1357 adapter->num_tx_queues = 0; 1358 adapter->num_rx_queues = 0; 1359 adapter->num_q_vectors = 0; 1360 1361 while (v_idx--) 1362 igb_free_q_vector(adapter, v_idx); 1363 1364 return -ENOMEM; 1365} 1366 1367/** 1368 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1369 * @adapter: board private structure to initialize 1370 * @msix: boolean value of MSIX capability 1371 * 1372 * This function initializes the interrupts and allocates all of the queues. 1373 **/ 1374static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1375{ 1376 struct pci_dev *pdev = adapter->pdev; 1377 int err; 1378 1379 igb_set_interrupt_capability(adapter, msix); 1380 1381 err = igb_alloc_q_vectors(adapter); 1382 if (err) { 1383 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1384 goto err_alloc_q_vectors; 1385 } 1386 1387 igb_cache_ring_register(adapter); 1388 1389 return 0; 1390 1391err_alloc_q_vectors: 1392 igb_reset_interrupt_capability(adapter); 1393 return err; 1394} 1395 1396/** 1397 * igb_request_irq - initialize interrupts 1398 * @adapter: board private structure to initialize 1399 * 1400 * Attempts to configure interrupts using the best available 1401 * capabilities of the hardware and kernel. 1402 **/ 1403static int igb_request_irq(struct igb_adapter *adapter) 1404{ 1405 struct net_device *netdev = adapter->netdev; 1406 struct pci_dev *pdev = adapter->pdev; 1407 int err = 0; 1408 1409 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1410 err = igb_request_msix(adapter); 1411 if (!err) 1412 goto request_done; 1413 /* fall back to MSI */ 1414 igb_free_all_tx_resources(adapter); 1415 igb_free_all_rx_resources(adapter); 1416 1417 igb_clear_interrupt_scheme(adapter); 1418 err = igb_init_interrupt_scheme(adapter, false); 1419 if (err) 1420 goto request_done; 1421 1422 igb_setup_all_tx_resources(adapter); 1423 igb_setup_all_rx_resources(adapter); 1424 igb_configure(adapter); 1425 } 1426 1427 igb_assign_vector(adapter->q_vector[0], 0); 1428 1429 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1430 err = request_irq(pdev->irq, igb_intr_msi, 0, 1431 netdev->name, adapter); 1432 if (!err) 1433 goto request_done; 1434 1435 /* fall back to legacy interrupts */ 1436 igb_reset_interrupt_capability(adapter); 1437 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1438 } 1439 1440 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1441 netdev->name, adapter); 1442 1443 if (err) 1444 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1445 err); 1446 1447request_done: 1448 return err; 1449} 1450 1451static void igb_free_irq(struct igb_adapter *adapter) 1452{ 1453 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1454 int vector = 0, i; 1455 1456 free_irq(adapter->msix_entries[vector++].vector, adapter); 1457 1458 for (i = 0; i < adapter->num_q_vectors; i++) 1459 free_irq(adapter->msix_entries[vector++].vector, 1460 adapter->q_vector[i]); 1461 } else { 1462 free_irq(adapter->pdev->irq, adapter); 1463 } 1464} 1465 1466/** 1467 * igb_irq_disable - Mask off interrupt generation on the NIC 1468 * @adapter: board private structure 1469 **/ 1470static void igb_irq_disable(struct igb_adapter *adapter) 1471{ 1472 struct e1000_hw *hw = &adapter->hw; 1473 1474 /* we need to be careful when disabling interrupts. The VFs are also 1475 * mapped into these registers and so clearing the bits can cause 1476 * issues on the VF drivers so we only need to clear what we set 1477 */ 1478 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1479 u32 regval = rd32(E1000_EIAM); 1480 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1481 wr32(E1000_EIMC, adapter->eims_enable_mask); 1482 regval = rd32(E1000_EIAC); 1483 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1484 } 1485 1486 wr32(E1000_IAM, 0); 1487 wr32(E1000_IMC, ~0); 1488 wrfl(); 1489 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1490 int i; 1491 for (i = 0; i < adapter->num_q_vectors; i++) 1492 synchronize_irq(adapter->msix_entries[i].vector); 1493 } else { 1494 synchronize_irq(adapter->pdev->irq); 1495 } 1496} 1497 1498/** 1499 * igb_irq_enable - Enable default interrupt generation settings 1500 * @adapter: board private structure 1501 **/ 1502static void igb_irq_enable(struct igb_adapter *adapter) 1503{ 1504 struct e1000_hw *hw = &adapter->hw; 1505 1506 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1507 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1508 u32 regval = rd32(E1000_EIAC); 1509 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1510 regval = rd32(E1000_EIAM); 1511 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1512 wr32(E1000_EIMS, adapter->eims_enable_mask); 1513 if (adapter->vfs_allocated_count) { 1514 wr32(E1000_MBVFIMR, 0xFF); 1515 ims |= E1000_IMS_VMMB; 1516 } 1517 wr32(E1000_IMS, ims); 1518 } else { 1519 wr32(E1000_IMS, IMS_ENABLE_MASK | 1520 E1000_IMS_DRSTA); 1521 wr32(E1000_IAM, IMS_ENABLE_MASK | 1522 E1000_IMS_DRSTA); 1523 } 1524} 1525 1526static void igb_update_mng_vlan(struct igb_adapter *adapter) 1527{ 1528 struct e1000_hw *hw = &adapter->hw; 1529 u16 vid = adapter->hw.mng_cookie.vlan_id; 1530 u16 old_vid = adapter->mng_vlan_id; 1531 1532 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1533 /* add VID to filter table */ 1534 igb_vfta_set(hw, vid, true); 1535 adapter->mng_vlan_id = vid; 1536 } else { 1537 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1538 } 1539 1540 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1541 (vid != old_vid) && 1542 !test_bit(old_vid, adapter->active_vlans)) { 1543 /* remove VID from filter table */ 1544 igb_vfta_set(hw, old_vid, false); 1545 } 1546} 1547 1548/** 1549 * igb_release_hw_control - release control of the h/w to f/w 1550 * @adapter: address of board private structure 1551 * 1552 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1553 * For ASF and Pass Through versions of f/w this means that the 1554 * driver is no longer loaded. 1555 **/ 1556static void igb_release_hw_control(struct igb_adapter *adapter) 1557{ 1558 struct e1000_hw *hw = &adapter->hw; 1559 u32 ctrl_ext; 1560 1561 /* Let firmware take over control of h/w */ 1562 ctrl_ext = rd32(E1000_CTRL_EXT); 1563 wr32(E1000_CTRL_EXT, 1564 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1565} 1566 1567/** 1568 * igb_get_hw_control - get control of the h/w from f/w 1569 * @adapter: address of board private structure 1570 * 1571 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1572 * For ASF and Pass Through versions of f/w this means that 1573 * the driver is loaded. 1574 **/ 1575static void igb_get_hw_control(struct igb_adapter *adapter) 1576{ 1577 struct e1000_hw *hw = &adapter->hw; 1578 u32 ctrl_ext; 1579 1580 /* Let firmware know the driver has taken over */ 1581 ctrl_ext = rd32(E1000_CTRL_EXT); 1582 wr32(E1000_CTRL_EXT, 1583 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1584} 1585 1586/** 1587 * igb_configure - configure the hardware for RX and TX 1588 * @adapter: private board structure 1589 **/ 1590static void igb_configure(struct igb_adapter *adapter) 1591{ 1592 struct net_device *netdev = adapter->netdev; 1593 int i; 1594 1595 igb_get_hw_control(adapter); 1596 igb_set_rx_mode(netdev); 1597 1598 igb_restore_vlan(adapter); 1599 1600 igb_setup_tctl(adapter); 1601 igb_setup_mrqc(adapter); 1602 igb_setup_rctl(adapter); 1603 1604 igb_configure_tx(adapter); 1605 igb_configure_rx(adapter); 1606 1607 igb_rx_fifo_flush_82575(&adapter->hw); 1608 1609 /* call igb_desc_unused which always leaves 1610 * at least 1 descriptor unused to make sure 1611 * next_to_use != next_to_clean 1612 */ 1613 for (i = 0; i < adapter->num_rx_queues; i++) { 1614 struct igb_ring *ring = adapter->rx_ring[i]; 1615 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1616 } 1617} 1618 1619/** 1620 * igb_power_up_link - Power up the phy/serdes link 1621 * @adapter: address of board private structure 1622 **/ 1623void igb_power_up_link(struct igb_adapter *adapter) 1624{ 1625 igb_reset_phy(&adapter->hw); 1626 1627 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1628 igb_power_up_phy_copper(&adapter->hw); 1629 else 1630 igb_power_up_serdes_link_82575(&adapter->hw); 1631} 1632 1633/** 1634 * igb_power_down_link - Power down the phy/serdes link 1635 * @adapter: address of board private structure 1636 */ 1637static void igb_power_down_link(struct igb_adapter *adapter) 1638{ 1639 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1640 igb_power_down_phy_copper_82575(&adapter->hw); 1641 else 1642 igb_shutdown_serdes_link_82575(&adapter->hw); 1643} 1644 1645/** 1646 * Detect and switch function for Media Auto Sense 1647 * @adapter: address of the board private structure 1648 **/ 1649static void igb_check_swap_media(struct igb_adapter *adapter) 1650{ 1651 struct e1000_hw *hw = &adapter->hw; 1652 u32 ctrl_ext, connsw; 1653 bool swap_now = false; 1654 1655 ctrl_ext = rd32(E1000_CTRL_EXT); 1656 connsw = rd32(E1000_CONNSW); 1657 1658 /* need to live swap if current media is copper and we have fiber/serdes 1659 * to go to. 1660 */ 1661 1662 if ((hw->phy.media_type == e1000_media_type_copper) && 1663 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1664 swap_now = true; 1665 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1666 /* copper signal takes time to appear */ 1667 if (adapter->copper_tries < 4) { 1668 adapter->copper_tries++; 1669 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1670 wr32(E1000_CONNSW, connsw); 1671 return; 1672 } else { 1673 adapter->copper_tries = 0; 1674 if ((connsw & E1000_CONNSW_PHYSD) && 1675 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1676 swap_now = true; 1677 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1678 wr32(E1000_CONNSW, connsw); 1679 } 1680 } 1681 } 1682 1683 if (!swap_now) 1684 return; 1685 1686 switch (hw->phy.media_type) { 1687 case e1000_media_type_copper: 1688 netdev_info(adapter->netdev, 1689 "MAS: changing media to fiber/serdes\n"); 1690 ctrl_ext |= 1691 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1692 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1693 adapter->copper_tries = 0; 1694 break; 1695 case e1000_media_type_internal_serdes: 1696 case e1000_media_type_fiber: 1697 netdev_info(adapter->netdev, 1698 "MAS: changing media to copper\n"); 1699 ctrl_ext &= 1700 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1701 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1702 break; 1703 default: 1704 /* shouldn't get here during regular operation */ 1705 netdev_err(adapter->netdev, 1706 "AMS: Invalid media type found, returning\n"); 1707 break; 1708 } 1709 wr32(E1000_CTRL_EXT, ctrl_ext); 1710} 1711 1712/** 1713 * igb_up - Open the interface and prepare it to handle traffic 1714 * @adapter: board private structure 1715 **/ 1716int igb_up(struct igb_adapter *adapter) 1717{ 1718 struct e1000_hw *hw = &adapter->hw; 1719 int i; 1720 1721 /* hardware has been reset, we need to reload some things */ 1722 igb_configure(adapter); 1723 1724 clear_bit(__IGB_DOWN, &adapter->state); 1725 1726 for (i = 0; i < adapter->num_q_vectors; i++) 1727 napi_enable(&(adapter->q_vector[i]->napi)); 1728 1729 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1730 igb_configure_msix(adapter); 1731 else 1732 igb_assign_vector(adapter->q_vector[0], 0); 1733 1734 /* Clear any pending interrupts. */ 1735 rd32(E1000_ICR); 1736 igb_irq_enable(adapter); 1737 1738 /* notify VFs that reset has been completed */ 1739 if (adapter->vfs_allocated_count) { 1740 u32 reg_data = rd32(E1000_CTRL_EXT); 1741 reg_data |= E1000_CTRL_EXT_PFRSTD; 1742 wr32(E1000_CTRL_EXT, reg_data); 1743 } 1744 1745 netif_tx_start_all_queues(adapter->netdev); 1746 1747 /* start the watchdog. */ 1748 hw->mac.get_link_status = 1; 1749 schedule_work(&adapter->watchdog_task); 1750 1751 if ((adapter->flags & IGB_FLAG_EEE) && 1752 (!hw->dev_spec._82575.eee_disable)) 1753 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1754 1755 return 0; 1756} 1757 1758void igb_down(struct igb_adapter *adapter) 1759{ 1760 struct net_device *netdev = adapter->netdev; 1761 struct e1000_hw *hw = &adapter->hw; 1762 u32 tctl, rctl; 1763 int i; 1764 1765 /* signal that we're down so the interrupt handler does not 1766 * reschedule our watchdog timer 1767 */ 1768 set_bit(__IGB_DOWN, &adapter->state); 1769 1770 /* disable receives in the hardware */ 1771 rctl = rd32(E1000_RCTL); 1772 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1773 /* flush and sleep below */ 1774 1775 netif_tx_stop_all_queues(netdev); 1776 1777 /* disable transmits in the hardware */ 1778 tctl = rd32(E1000_TCTL); 1779 tctl &= ~E1000_TCTL_EN; 1780 wr32(E1000_TCTL, tctl); 1781 /* flush both disables and wait for them to finish */ 1782 wrfl(); 1783 msleep(10); 1784 1785 igb_irq_disable(adapter); 1786 1787 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1788 1789 for (i = 0; i < adapter->num_q_vectors; i++) { 1790 napi_synchronize(&(adapter->q_vector[i]->napi)); 1791 napi_disable(&(adapter->q_vector[i]->napi)); 1792 } 1793 1794 1795 del_timer_sync(&adapter->watchdog_timer); 1796 del_timer_sync(&adapter->phy_info_timer); 1797 1798 netif_carrier_off(netdev); 1799 1800 /* record the stats before reset*/ 1801 spin_lock(&adapter->stats64_lock); 1802 igb_update_stats(adapter, &adapter->stats64); 1803 spin_unlock(&adapter->stats64_lock); 1804 1805 adapter->link_speed = 0; 1806 adapter->link_duplex = 0; 1807 1808 if (!pci_channel_offline(adapter->pdev)) 1809 igb_reset(adapter); 1810 igb_clean_all_tx_rings(adapter); 1811 igb_clean_all_rx_rings(adapter); 1812#ifdef CONFIG_IGB_DCA 1813 1814 /* since we reset the hardware DCA settings were cleared */ 1815 igb_setup_dca(adapter); 1816#endif 1817} 1818 1819void igb_reinit_locked(struct igb_adapter *adapter) 1820{ 1821 WARN_ON(in_interrupt()); 1822 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1823 msleep(1); 1824 igb_down(adapter); 1825 igb_up(adapter); 1826 clear_bit(__IGB_RESETTING, &adapter->state); 1827} 1828 1829/** igb_enable_mas - Media Autosense re-enable after swap 1830 * 1831 * @adapter: adapter struct 1832 **/ 1833static s32 igb_enable_mas(struct igb_adapter *adapter) 1834{ 1835 struct e1000_hw *hw = &adapter->hw; 1836 u32 connsw; 1837 s32 ret_val = 0; 1838 1839 connsw = rd32(E1000_CONNSW); 1840 if (!(hw->phy.media_type == e1000_media_type_copper)) 1841 return ret_val; 1842 1843 /* configure for SerDes media detect */ 1844 if (!(connsw & E1000_CONNSW_SERDESD)) { 1845 connsw |= E1000_CONNSW_ENRGSRC; 1846 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1847 wr32(E1000_CONNSW, connsw); 1848 wrfl(); 1849 } else if (connsw & E1000_CONNSW_SERDESD) { 1850 /* already SerDes, no need to enable anything */ 1851 return ret_val; 1852 } else { 1853 netdev_info(adapter->netdev, 1854 "MAS: Unable to configure feature, disabling..\n"); 1855 adapter->flags &= ~IGB_FLAG_MAS_ENABLE; 1856 } 1857 return ret_val; 1858} 1859 1860void igb_reset(struct igb_adapter *adapter) 1861{ 1862 struct pci_dev *pdev = adapter->pdev; 1863 struct e1000_hw *hw = &adapter->hw; 1864 struct e1000_mac_info *mac = &hw->mac; 1865 struct e1000_fc_info *fc = &hw->fc; 1866 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; 1867 1868 /* Repartition Pba for greater than 9k mtu 1869 * To take effect CTRL.RST is required. 1870 */ 1871 switch (mac->type) { 1872 case e1000_i350: 1873 case e1000_i354: 1874 case e1000_82580: 1875 pba = rd32(E1000_RXPBS); 1876 pba = igb_rxpbs_adjust_82580(pba); 1877 break; 1878 case e1000_82576: 1879 pba = rd32(E1000_RXPBS); 1880 pba &= E1000_RXPBS_SIZE_MASK_82576; 1881 break; 1882 case e1000_82575: 1883 case e1000_i210: 1884 case e1000_i211: 1885 default: 1886 pba = E1000_PBA_34K; 1887 break; 1888 } 1889 1890 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1891 (mac->type < e1000_82576)) { 1892 /* adjust PBA for jumbo frames */ 1893 wr32(E1000_PBA, pba); 1894 1895 /* To maintain wire speed transmits, the Tx FIFO should be 1896 * large enough to accommodate two full transmit packets, 1897 * rounded up to the next 1KB and expressed in KB. Likewise, 1898 * the Rx FIFO should be large enough to accommodate at least 1899 * one full receive packet and is similarly rounded up and 1900 * expressed in KB. 1901 */ 1902 pba = rd32(E1000_PBA); 1903 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1904 tx_space = pba >> 16; 1905 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1906 pba &= 0xffff; 1907 /* the Tx fifo also stores 16 bytes of information about the Tx 1908 * but don't include ethernet FCS because hardware appends it 1909 */ 1910 min_tx_space = (adapter->max_frame_size + 1911 sizeof(union e1000_adv_tx_desc) - 1912 ETH_FCS_LEN) * 2; 1913 min_tx_space = ALIGN(min_tx_space, 1024); 1914 min_tx_space >>= 10; 1915 /* software strips receive CRC, so leave room for it */ 1916 min_rx_space = adapter->max_frame_size; 1917 min_rx_space = ALIGN(min_rx_space, 1024); 1918 min_rx_space >>= 10; 1919 1920 /* If current Tx allocation is less than the min Tx FIFO size, 1921 * and the min Tx FIFO size is less than the current Rx FIFO 1922 * allocation, take space away from current Rx allocation 1923 */ 1924 if (tx_space < min_tx_space && 1925 ((min_tx_space - tx_space) < pba)) { 1926 pba = pba - (min_tx_space - tx_space); 1927 1928 /* if short on Rx space, Rx wins and must trump Tx 1929 * adjustment 1930 */ 1931 if (pba < min_rx_space) 1932 pba = min_rx_space; 1933 } 1934 wr32(E1000_PBA, pba); 1935 } 1936 1937 /* flow control settings */ 1938 /* The high water mark must be low enough to fit one full frame 1939 * (or the size used for early receive) above it in the Rx FIFO. 1940 * Set it to the lower of: 1941 * - 90% of the Rx FIFO size, or 1942 * - the full Rx FIFO size minus one full frame 1943 */ 1944 hwm = min(((pba << 10) * 9 / 10), 1945 ((pba << 10) - 2 * adapter->max_frame_size)); 1946 1947 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1948 fc->low_water = fc->high_water - 16; 1949 fc->pause_time = 0xFFFF; 1950 fc->send_xon = 1; 1951 fc->current_mode = fc->requested_mode; 1952 1953 /* disable receive for all VFs and wait one second */ 1954 if (adapter->vfs_allocated_count) { 1955 int i; 1956 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1957 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1958 1959 /* ping all the active vfs to let them know we are going down */ 1960 igb_ping_all_vfs(adapter); 1961 1962 /* disable transmits and receives */ 1963 wr32(E1000_VFRE, 0); 1964 wr32(E1000_VFTE, 0); 1965 } 1966 1967 /* Allow time for pending master requests to run */ 1968 hw->mac.ops.reset_hw(hw); 1969 wr32(E1000_WUC, 0); 1970 1971 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1972 /* need to resetup here after media swap */ 1973 adapter->ei.get_invariants(hw); 1974 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1975 } 1976 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 1977 if (igb_enable_mas(adapter)) 1978 dev_err(&pdev->dev, 1979 "Error enabling Media Auto Sense\n"); 1980 } 1981 if (hw->mac.ops.init_hw(hw)) 1982 dev_err(&pdev->dev, "Hardware Error\n"); 1983 1984 /* Flow control settings reset on hardware reset, so guarantee flow 1985 * control is off when forcing speed. 1986 */ 1987 if (!hw->mac.autoneg) 1988 igb_force_mac_fc(hw); 1989 1990 igb_init_dmac(adapter, pba); 1991#ifdef CONFIG_IGB_HWMON 1992 /* Re-initialize the thermal sensor on i350 devices. */ 1993 if (!test_bit(__IGB_DOWN, &adapter->state)) { 1994 if (mac->type == e1000_i350 && hw->bus.func == 0) { 1995 /* If present, re-initialize the external thermal sensor 1996 * interface. 1997 */ 1998 if (adapter->ets) 1999 mac->ops.init_thermal_sensor_thresh(hw); 2000 } 2001 } 2002#endif 2003 /* Re-establish EEE setting */ 2004 if (hw->phy.media_type == e1000_media_type_copper) { 2005 switch (mac->type) { 2006 case e1000_i350: 2007 case e1000_i210: 2008 case e1000_i211: 2009 igb_set_eee_i350(hw); 2010 break; 2011 case e1000_i354: 2012 igb_set_eee_i354(hw); 2013 break; 2014 default: 2015 break; 2016 } 2017 } 2018 if (!netif_running(adapter->netdev)) 2019 igb_power_down_link(adapter); 2020 2021 igb_update_mng_vlan(adapter); 2022 2023 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2024 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2025 2026 /* Re-enable PTP, where applicable. */ 2027 igb_ptp_reset(adapter); 2028 2029 igb_get_phy_info(hw); 2030} 2031 2032static netdev_features_t igb_fix_features(struct net_device *netdev, 2033 netdev_features_t features) 2034{ 2035 /* Since there is no support for separate Rx/Tx vlan accel 2036 * enable/disable make sure Tx flag is always in same state as Rx. 2037 */ 2038 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2039 features |= NETIF_F_HW_VLAN_CTAG_TX; 2040 else 2041 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2042 2043 return features; 2044} 2045 2046static int igb_set_features(struct net_device *netdev, 2047 netdev_features_t features) 2048{ 2049 netdev_features_t changed = netdev->features ^ features; 2050 struct igb_adapter *adapter = netdev_priv(netdev); 2051 2052 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2053 igb_vlan_mode(netdev, features); 2054 2055 if (!(changed & NETIF_F_RXALL)) 2056 return 0; 2057 2058 netdev->features = features; 2059 2060 if (netif_running(netdev)) 2061 igb_reinit_locked(adapter); 2062 else 2063 igb_reset(adapter); 2064 2065 return 0; 2066} 2067 2068static const struct net_device_ops igb_netdev_ops = { 2069 .ndo_open = igb_open, 2070 .ndo_stop = igb_close, 2071 .ndo_start_xmit = igb_xmit_frame, 2072 .ndo_get_stats64 = igb_get_stats64, 2073 .ndo_set_rx_mode = igb_set_rx_mode, 2074 .ndo_set_mac_address = igb_set_mac, 2075 .ndo_change_mtu = igb_change_mtu, 2076 .ndo_do_ioctl = igb_ioctl, 2077 .ndo_tx_timeout = igb_tx_timeout, 2078 .ndo_validate_addr = eth_validate_addr, 2079 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2080 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2081 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2082 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2083 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, 2084 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2085 .ndo_get_vf_config = igb_ndo_get_vf_config, 2086#ifdef CONFIG_NET_POLL_CONTROLLER 2087 .ndo_poll_controller = igb_netpoll, 2088#endif 2089 .ndo_fix_features = igb_fix_features, 2090 .ndo_set_features = igb_set_features, 2091}; 2092 2093/** 2094 * igb_set_fw_version - Configure version string for ethtool 2095 * @adapter: adapter struct 2096 **/ 2097void igb_set_fw_version(struct igb_adapter *adapter) 2098{ 2099 struct e1000_hw *hw = &adapter->hw; 2100 struct e1000_fw_version fw; 2101 2102 igb_get_fw_version(hw, &fw); 2103 2104 switch (hw->mac.type) { 2105 case e1000_i210: 2106 case e1000_i211: 2107 if (!(igb_get_flash_presence_i210(hw))) { 2108 snprintf(adapter->fw_version, 2109 sizeof(adapter->fw_version), 2110 "%2d.%2d-%d", 2111 fw.invm_major, fw.invm_minor, 2112 fw.invm_img_type); 2113 break; 2114 } 2115 /* fall through */ 2116 default: 2117 /* if option is rom valid, display its version too */ 2118 if (fw.or_valid) { 2119 snprintf(adapter->fw_version, 2120 sizeof(adapter->fw_version), 2121 "%d.%d, 0x%08x, %d.%d.%d", 2122 fw.eep_major, fw.eep_minor, fw.etrack_id, 2123 fw.or_major, fw.or_build, fw.or_patch); 2124 /* no option rom */ 2125 } else if (fw.etrack_id != 0X0000) { 2126 snprintf(adapter->fw_version, 2127 sizeof(adapter->fw_version), 2128 "%d.%d, 0x%08x", 2129 fw.eep_major, fw.eep_minor, fw.etrack_id); 2130 } else { 2131 snprintf(adapter->fw_version, 2132 sizeof(adapter->fw_version), 2133 "%d.%d.%d", 2134 fw.eep_major, fw.eep_minor, fw.eep_build); 2135 } 2136 break; 2137 } 2138 return; 2139} 2140 2141/** 2142 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2143 * 2144 * @adapter: adapter struct 2145 **/ 2146static void igb_init_mas(struct igb_adapter *adapter) 2147{ 2148 struct e1000_hw *hw = &adapter->hw; 2149 u16 eeprom_data; 2150 2151 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2152 switch (hw->bus.func) { 2153 case E1000_FUNC_0: 2154 if (eeprom_data & IGB_MAS_ENABLE_0) { 2155 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2156 netdev_info(adapter->netdev, 2157 "MAS: Enabling Media Autosense for port %d\n", 2158 hw->bus.func); 2159 } 2160 break; 2161 case E1000_FUNC_1: 2162 if (eeprom_data & IGB_MAS_ENABLE_1) { 2163 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2164 netdev_info(adapter->netdev, 2165 "MAS: Enabling Media Autosense for port %d\n", 2166 hw->bus.func); 2167 } 2168 break; 2169 case E1000_FUNC_2: 2170 if (eeprom_data & IGB_MAS_ENABLE_2) { 2171 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2172 netdev_info(adapter->netdev, 2173 "MAS: Enabling Media Autosense for port %d\n", 2174 hw->bus.func); 2175 } 2176 break; 2177 case E1000_FUNC_3: 2178 if (eeprom_data & IGB_MAS_ENABLE_3) { 2179 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2180 netdev_info(adapter->netdev, 2181 "MAS: Enabling Media Autosense for port %d\n", 2182 hw->bus.func); 2183 } 2184 break; 2185 default: 2186 /* Shouldn't get here */ 2187 netdev_err(adapter->netdev, 2188 "MAS: Invalid port configuration, returning\n"); 2189 break; 2190 } 2191} 2192 2193/** 2194 * igb_init_i2c - Init I2C interface 2195 * @adapter: pointer to adapter structure 2196 **/ 2197static s32 igb_init_i2c(struct igb_adapter *adapter) 2198{ 2199 s32 status = E1000_SUCCESS; 2200 2201 /* I2C interface supported on i350 devices */ 2202 if (adapter->hw.mac.type != e1000_i350) 2203 return E1000_SUCCESS; 2204 2205 /* Initialize the i2c bus which is controlled by the registers. 2206 * This bus will use the i2c_algo_bit structue that implements 2207 * the protocol through toggling of the 4 bits in the register. 2208 */ 2209 adapter->i2c_adap.owner = THIS_MODULE; 2210 adapter->i2c_algo = igb_i2c_algo; 2211 adapter->i2c_algo.data = adapter; 2212 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2213 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2214 strlcpy(adapter->i2c_adap.name, "igb BB", 2215 sizeof(adapter->i2c_adap.name)); 2216 status = i2c_bit_add_bus(&adapter->i2c_adap); 2217 return status; 2218} 2219 2220/** 2221 * igb_probe - Device Initialization Routine 2222 * @pdev: PCI device information struct 2223 * @ent: entry in igb_pci_tbl 2224 * 2225 * Returns 0 on success, negative on failure 2226 * 2227 * igb_probe initializes an adapter identified by a pci_dev structure. 2228 * The OS initialization, configuring of the adapter private structure, 2229 * and a hardware reset occur. 2230 **/ 2231static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2232{ 2233 struct net_device *netdev; 2234 struct igb_adapter *adapter; 2235 struct e1000_hw *hw; 2236 u16 eeprom_data = 0; 2237 s32 ret_val; 2238 static int global_quad_port_a; /* global quad port a indication */ 2239 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2240 int err, pci_using_dac; 2241 u8 part_str[E1000_PBANUM_LENGTH]; 2242 2243 /* Catch broken hardware that put the wrong VF device ID in 2244 * the PCIe SR-IOV capability. 2245 */ 2246 if (pdev->is_virtfn) { 2247 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2248 pci_name(pdev), pdev->vendor, pdev->device); 2249 return -EINVAL; 2250 } 2251 2252 err = pci_enable_device_mem(pdev); 2253 if (err) 2254 return err; 2255 2256 pci_using_dac = 0; 2257 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2258 if (!err) { 2259 pci_using_dac = 1; 2260 } else { 2261 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2262 if (err) { 2263 dev_err(&pdev->dev, 2264 "No usable DMA configuration, aborting\n"); 2265 goto err_dma; 2266 } 2267 } 2268 2269 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 2270 IORESOURCE_MEM), 2271 igb_driver_name); 2272 if (err) 2273 goto err_pci_reg; 2274 2275 pci_enable_pcie_error_reporting(pdev); 2276 2277 pci_set_master(pdev); 2278 pci_save_state(pdev); 2279 2280 err = -ENOMEM; 2281 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2282 IGB_MAX_TX_QUEUES); 2283 if (!netdev) 2284 goto err_alloc_etherdev; 2285 2286 SET_NETDEV_DEV(netdev, &pdev->dev); 2287 2288 pci_set_drvdata(pdev, netdev); 2289 adapter = netdev_priv(netdev); 2290 adapter->netdev = netdev; 2291 adapter->pdev = pdev; 2292 hw = &adapter->hw; 2293 hw->back = adapter; 2294 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2295 2296 err = -EIO; 2297 hw->hw_addr = pci_iomap(pdev, 0, 0); 2298 if (!hw->hw_addr) 2299 goto err_ioremap; 2300 2301 netdev->netdev_ops = &igb_netdev_ops; 2302 igb_set_ethtool_ops(netdev); 2303 netdev->watchdog_timeo = 5 * HZ; 2304 2305 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2306 2307 netdev->mem_start = pci_resource_start(pdev, 0); 2308 netdev->mem_end = pci_resource_end(pdev, 0); 2309 2310 /* PCI config space info */ 2311 hw->vendor_id = pdev->vendor; 2312 hw->device_id = pdev->device; 2313 hw->revision_id = pdev->revision; 2314 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2315 hw->subsystem_device_id = pdev->subsystem_device; 2316 2317 /* Copy the default MAC, PHY and NVM function pointers */ 2318 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2319 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2320 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2321 /* Initialize skew-specific constants */ 2322 err = ei->get_invariants(hw); 2323 if (err) 2324 goto err_sw_init; 2325 2326 /* setup the private structure */ 2327 err = igb_sw_init(adapter); 2328 if (err) 2329 goto err_sw_init; 2330 2331 igb_get_bus_info_pcie(hw); 2332 2333 hw->phy.autoneg_wait_to_complete = false; 2334 2335 /* Copper options */ 2336 if (hw->phy.media_type == e1000_media_type_copper) { 2337 hw->phy.mdix = AUTO_ALL_MODES; 2338 hw->phy.disable_polarity_correction = false; 2339 hw->phy.ms_type = e1000_ms_hw_default; 2340 } 2341 2342 if (igb_check_reset_block(hw)) 2343 dev_info(&pdev->dev, 2344 "PHY reset is blocked due to SOL/IDER session.\n"); 2345 2346 /* features is initialized to 0 in allocation, it might have bits 2347 * set by igb_sw_init so we should use an or instead of an 2348 * assignment. 2349 */ 2350 netdev->features |= NETIF_F_SG | 2351 NETIF_F_IP_CSUM | 2352 NETIF_F_IPV6_CSUM | 2353 NETIF_F_TSO | 2354 NETIF_F_TSO6 | 2355 NETIF_F_RXHASH | 2356 NETIF_F_RXCSUM | 2357 NETIF_F_HW_VLAN_CTAG_RX | 2358 NETIF_F_HW_VLAN_CTAG_TX; 2359 2360 /* copy netdev features into list of user selectable features */ 2361 netdev->hw_features |= netdev->features; 2362 netdev->hw_features |= NETIF_F_RXALL; 2363 2364 /* set this bit last since it cannot be part of hw_features */ 2365 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2366 2367 netdev->vlan_features |= NETIF_F_TSO | 2368 NETIF_F_TSO6 | 2369 NETIF_F_IP_CSUM | 2370 NETIF_F_IPV6_CSUM | 2371 NETIF_F_SG; 2372 2373 netdev->priv_flags |= IFF_SUPP_NOFCS; 2374 2375 if (pci_using_dac) { 2376 netdev->features |= NETIF_F_HIGHDMA; 2377 netdev->vlan_features |= NETIF_F_HIGHDMA; 2378 } 2379 2380 if (hw->mac.type >= e1000_82576) { 2381 netdev->hw_features |= NETIF_F_SCTP_CSUM; 2382 netdev->features |= NETIF_F_SCTP_CSUM; 2383 } 2384 2385 netdev->priv_flags |= IFF_UNICAST_FLT; 2386 2387 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2388 2389 /* before reading the NVM, reset the controller to put the device in a 2390 * known good starting state 2391 */ 2392 hw->mac.ops.reset_hw(hw); 2393 2394 /* make sure the NVM is good , i211/i210 parts can have special NVM 2395 * that doesn't contain a checksum 2396 */ 2397 switch (hw->mac.type) { 2398 case e1000_i210: 2399 case e1000_i211: 2400 if (igb_get_flash_presence_i210(hw)) { 2401 if (hw->nvm.ops.validate(hw) < 0) { 2402 dev_err(&pdev->dev, 2403 "The NVM Checksum Is Not Valid\n"); 2404 err = -EIO; 2405 goto err_eeprom; 2406 } 2407 } 2408 break; 2409 default: 2410 if (hw->nvm.ops.validate(hw) < 0) { 2411 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2412 err = -EIO; 2413 goto err_eeprom; 2414 } 2415 break; 2416 } 2417 2418 /* copy the MAC address out of the NVM */ 2419 if (hw->mac.ops.read_mac_addr(hw)) 2420 dev_err(&pdev->dev, "NVM Read Error\n"); 2421 2422 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2423 2424 if (!is_valid_ether_addr(netdev->dev_addr)) { 2425 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2426 err = -EIO; 2427 goto err_eeprom; 2428 } 2429 2430 /* get firmware version for ethtool -i */ 2431 igb_set_fw_version(adapter); 2432 2433 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2434 (unsigned long) adapter); 2435 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2436 (unsigned long) adapter); 2437 2438 INIT_WORK(&adapter->reset_task, igb_reset_task); 2439 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2440 2441 /* Initialize link properties that are user-changeable */ 2442 adapter->fc_autoneg = true; 2443 hw->mac.autoneg = true; 2444 hw->phy.autoneg_advertised = 0x2f; 2445 2446 hw->fc.requested_mode = e1000_fc_default; 2447 hw->fc.current_mode = e1000_fc_default; 2448 2449 igb_validate_mdi_setting(hw); 2450 2451 /* By default, support wake on port A */ 2452 if (hw->bus.func == 0) 2453 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2454 2455 /* Check the NVM for wake support on non-port A ports */ 2456 if (hw->mac.type >= e1000_82580) 2457 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2458 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2459 &eeprom_data); 2460 else if (hw->bus.func == 1) 2461 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2462 2463 if (eeprom_data & IGB_EEPROM_APME) 2464 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2465 2466 /* now that we have the eeprom settings, apply the special cases where 2467 * the eeprom may be wrong or the board simply won't support wake on 2468 * lan on a particular port 2469 */ 2470 switch (pdev->device) { 2471 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2472 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2473 break; 2474 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2475 case E1000_DEV_ID_82576_FIBER: 2476 case E1000_DEV_ID_82576_SERDES: 2477 /* Wake events only supported on port A for dual fiber 2478 * regardless of eeprom setting 2479 */ 2480 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2481 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2482 break; 2483 case E1000_DEV_ID_82576_QUAD_COPPER: 2484 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2485 /* if quad port adapter, disable WoL on all but port A */ 2486 if (global_quad_port_a != 0) 2487 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2488 else 2489 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2490 /* Reset for multiple quad port adapters */ 2491 if (++global_quad_port_a == 4) 2492 global_quad_port_a = 0; 2493 break; 2494 default: 2495 /* If the device can't wake, don't set software support */ 2496 if (!device_can_wakeup(&adapter->pdev->dev)) 2497 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2498 } 2499 2500 /* initialize the wol settings based on the eeprom settings */ 2501 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2502 adapter->wol |= E1000_WUFC_MAG; 2503 2504 /* Some vendors want WoL disabled by default, but still supported */ 2505 if ((hw->mac.type == e1000_i350) && 2506 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2507 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2508 adapter->wol = 0; 2509 } 2510 2511 device_set_wakeup_enable(&adapter->pdev->dev, 2512 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2513 2514 /* reset the hardware with the new settings */ 2515 igb_reset(adapter); 2516 2517 /* Init the I2C interface */ 2518 err = igb_init_i2c(adapter); 2519 if (err) { 2520 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2521 goto err_eeprom; 2522 } 2523 2524 /* let the f/w know that the h/w is now under the control of the 2525 * driver. */ 2526 igb_get_hw_control(adapter); 2527 2528 strcpy(netdev->name, "eth%d"); 2529 err = register_netdev(netdev); 2530 if (err) 2531 goto err_register; 2532 2533 /* carrier off reporting is important to ethtool even BEFORE open */ 2534 netif_carrier_off(netdev); 2535 2536#ifdef CONFIG_IGB_DCA 2537 if (dca_add_requester(&pdev->dev) == 0) { 2538 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2539 dev_info(&pdev->dev, "DCA enabled\n"); 2540 igb_setup_dca(adapter); 2541 } 2542 2543#endif 2544#ifdef CONFIG_IGB_HWMON 2545 /* Initialize the thermal sensor on i350 devices. */ 2546 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2547 u16 ets_word; 2548 2549 /* Read the NVM to determine if this i350 device supports an 2550 * external thermal sensor. 2551 */ 2552 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2553 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2554 adapter->ets = true; 2555 else 2556 adapter->ets = false; 2557 if (igb_sysfs_init(adapter)) 2558 dev_err(&pdev->dev, 2559 "failed to allocate sysfs resources\n"); 2560 } else { 2561 adapter->ets = false; 2562 } 2563#endif 2564 /* Check if Media Autosense is enabled */ 2565 adapter->ei = *ei; 2566 if (hw->dev_spec._82575.mas_capable) 2567 igb_init_mas(adapter); 2568 2569 /* do hw tstamp init after resetting */ 2570 igb_ptp_init(adapter); 2571 2572 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2573 /* print bus type/speed/width info, not applicable to i354 */ 2574 if (hw->mac.type != e1000_i354) { 2575 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2576 netdev->name, 2577 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2578 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2579 "unknown"), 2580 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2581 "Width x4" : 2582 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2583 "Width x2" : 2584 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2585 "Width x1" : "unknown"), netdev->dev_addr); 2586 } 2587 2588 if ((hw->mac.type >= e1000_i210 || 2589 igb_get_flash_presence_i210(hw))) { 2590 ret_val = igb_read_part_string(hw, part_str, 2591 E1000_PBANUM_LENGTH); 2592 } else { 2593 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2594 } 2595 2596 if (ret_val) 2597 strcpy(part_str, "Unknown"); 2598 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2599 dev_info(&pdev->dev, 2600 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2601 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2602 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2603 adapter->num_rx_queues, adapter->num_tx_queues); 2604 if (hw->phy.media_type == e1000_media_type_copper) { 2605 switch (hw->mac.type) { 2606 case e1000_i350: 2607 case e1000_i210: 2608 case e1000_i211: 2609 /* Enable EEE for internal copper PHY devices */ 2610 err = igb_set_eee_i350(hw); 2611 if ((!err) && 2612 (!hw->dev_spec._82575.eee_disable)) { 2613 adapter->eee_advert = 2614 MDIO_EEE_100TX | MDIO_EEE_1000T; 2615 adapter->flags |= IGB_FLAG_EEE; 2616 } 2617 break; 2618 case e1000_i354: 2619 if ((rd32(E1000_CTRL_EXT) & 2620 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2621 err = igb_set_eee_i354(hw); 2622 if ((!err) && 2623 (!hw->dev_spec._82575.eee_disable)) { 2624 adapter->eee_advert = 2625 MDIO_EEE_100TX | MDIO_EEE_1000T; 2626 adapter->flags |= IGB_FLAG_EEE; 2627 } 2628 } 2629 break; 2630 default: 2631 break; 2632 } 2633 } 2634 pm_runtime_put_noidle(&pdev->dev); 2635 return 0; 2636 2637err_register: 2638 igb_release_hw_control(adapter); 2639 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2640err_eeprom: 2641 if (!igb_check_reset_block(hw)) 2642 igb_reset_phy(hw); 2643 2644 if (hw->flash_address) 2645 iounmap(hw->flash_address); 2646err_sw_init: 2647 igb_clear_interrupt_scheme(adapter); 2648 pci_iounmap(pdev, hw->hw_addr); 2649err_ioremap: 2650 free_netdev(netdev); 2651err_alloc_etherdev: 2652 pci_release_selected_regions(pdev, 2653 pci_select_bars(pdev, IORESOURCE_MEM)); 2654err_pci_reg: 2655err_dma: 2656 pci_disable_device(pdev); 2657 return err; 2658} 2659 2660#ifdef CONFIG_PCI_IOV 2661static int igb_disable_sriov(struct pci_dev *pdev) 2662{ 2663 struct net_device *netdev = pci_get_drvdata(pdev); 2664 struct igb_adapter *adapter = netdev_priv(netdev); 2665 struct e1000_hw *hw = &adapter->hw; 2666 2667 /* reclaim resources allocated to VFs */ 2668 if (adapter->vf_data) { 2669 /* disable iov and allow time for transactions to clear */ 2670 if (pci_vfs_assigned(pdev)) { 2671 dev_warn(&pdev->dev, 2672 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2673 return -EPERM; 2674 } else { 2675 pci_disable_sriov(pdev); 2676 msleep(500); 2677 } 2678 2679 kfree(adapter->vf_data); 2680 adapter->vf_data = NULL; 2681 adapter->vfs_allocated_count = 0; 2682 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2683 wrfl(); 2684 msleep(100); 2685 dev_info(&pdev->dev, "IOV Disabled\n"); 2686 2687 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2688 adapter->flags |= IGB_FLAG_DMAC; 2689 } 2690 2691 return 0; 2692} 2693 2694static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2695{ 2696 struct net_device *netdev = pci_get_drvdata(pdev); 2697 struct igb_adapter *adapter = netdev_priv(netdev); 2698 int old_vfs = pci_num_vf(pdev); 2699 int err = 0; 2700 int i; 2701 2702 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2703 err = -EPERM; 2704 goto out; 2705 } 2706 if (!num_vfs) 2707 goto out; 2708 2709 if (old_vfs) { 2710 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2711 old_vfs, max_vfs); 2712 adapter->vfs_allocated_count = old_vfs; 2713 } else 2714 adapter->vfs_allocated_count = num_vfs; 2715 2716 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2717 sizeof(struct vf_data_storage), GFP_KERNEL); 2718 2719 /* if allocation failed then we do not support SR-IOV */ 2720 if (!adapter->vf_data) { 2721 adapter->vfs_allocated_count = 0; 2722 dev_err(&pdev->dev, 2723 "Unable to allocate memory for VF Data Storage\n"); 2724 err = -ENOMEM; 2725 goto out; 2726 } 2727 2728 /* only call pci_enable_sriov() if no VFs are allocated already */ 2729 if (!old_vfs) { 2730 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2731 if (err) 2732 goto err_out; 2733 } 2734 dev_info(&pdev->dev, "%d VFs allocated\n", 2735 adapter->vfs_allocated_count); 2736 for (i = 0; i < adapter->vfs_allocated_count; i++) 2737 igb_vf_configure(adapter, i); 2738 2739 /* DMA Coalescing is not supported in IOV mode. */ 2740 adapter->flags &= ~IGB_FLAG_DMAC; 2741 goto out; 2742 2743err_out: 2744 kfree(adapter->vf_data); 2745 adapter->vf_data = NULL; 2746 adapter->vfs_allocated_count = 0; 2747out: 2748 return err; 2749} 2750 2751#endif 2752/** 2753 * igb_remove_i2c - Cleanup I2C interface 2754 * @adapter: pointer to adapter structure 2755 **/ 2756static void igb_remove_i2c(struct igb_adapter *adapter) 2757{ 2758 /* free the adapter bus structure */ 2759 i2c_del_adapter(&adapter->i2c_adap); 2760} 2761 2762/** 2763 * igb_remove - Device Removal Routine 2764 * @pdev: PCI device information struct 2765 * 2766 * igb_remove is called by the PCI subsystem to alert the driver 2767 * that it should release a PCI device. The could be caused by a 2768 * Hot-Plug event, or because the driver is going to be removed from 2769 * memory. 2770 **/ 2771static void igb_remove(struct pci_dev *pdev) 2772{ 2773 struct net_device *netdev = pci_get_drvdata(pdev); 2774 struct igb_adapter *adapter = netdev_priv(netdev); 2775 struct e1000_hw *hw = &adapter->hw; 2776 2777 pm_runtime_get_noresume(&pdev->dev); 2778#ifdef CONFIG_IGB_HWMON 2779 igb_sysfs_exit(adapter); 2780#endif 2781 igb_remove_i2c(adapter); 2782 igb_ptp_stop(adapter); 2783 /* The watchdog timer may be rescheduled, so explicitly 2784 * disable watchdog from being rescheduled. 2785 */ 2786 set_bit(__IGB_DOWN, &adapter->state); 2787 del_timer_sync(&adapter->watchdog_timer); 2788 del_timer_sync(&adapter->phy_info_timer); 2789 2790 cancel_work_sync(&adapter->reset_task); 2791 cancel_work_sync(&adapter->watchdog_task); 2792 2793#ifdef CONFIG_IGB_DCA 2794 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2795 dev_info(&pdev->dev, "DCA disabled\n"); 2796 dca_remove_requester(&pdev->dev); 2797 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2798 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2799 } 2800#endif 2801 2802 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2803 * would have already happened in close and is redundant. 2804 */ 2805 igb_release_hw_control(adapter); 2806 2807 unregister_netdev(netdev); 2808 2809 igb_clear_interrupt_scheme(adapter); 2810 2811#ifdef CONFIG_PCI_IOV 2812 igb_disable_sriov(pdev); 2813#endif 2814 2815 pci_iounmap(pdev, hw->hw_addr); 2816 if (hw->flash_address) 2817 iounmap(hw->flash_address); 2818 pci_release_selected_regions(pdev, 2819 pci_select_bars(pdev, IORESOURCE_MEM)); 2820 2821 kfree(adapter->shadow_vfta); 2822 free_netdev(netdev); 2823 2824 pci_disable_pcie_error_reporting(pdev); 2825 2826 pci_disable_device(pdev); 2827} 2828 2829/** 2830 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2831 * @adapter: board private structure to initialize 2832 * 2833 * This function initializes the vf specific data storage and then attempts to 2834 * allocate the VFs. The reason for ordering it this way is because it is much 2835 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2836 * the memory for the VFs. 2837 **/ 2838static void igb_probe_vfs(struct igb_adapter *adapter) 2839{ 2840#ifdef CONFIG_PCI_IOV 2841 struct pci_dev *pdev = adapter->pdev; 2842 struct e1000_hw *hw = &adapter->hw; 2843 2844 /* Virtualization features not supported on i210 family. */ 2845 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2846 return; 2847 2848 pci_sriov_set_totalvfs(pdev, 7); 2849 igb_pci_enable_sriov(pdev, max_vfs); 2850 2851#endif /* CONFIG_PCI_IOV */ 2852} 2853 2854static void igb_init_queue_configuration(struct igb_adapter *adapter) 2855{ 2856 struct e1000_hw *hw = &adapter->hw; 2857 u32 max_rss_queues; 2858 2859 /* Determine the maximum number of RSS queues supported. */ 2860 switch (hw->mac.type) { 2861 case e1000_i211: 2862 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2863 break; 2864 case e1000_82575: 2865 case e1000_i210: 2866 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2867 break; 2868 case e1000_i350: 2869 /* I350 cannot do RSS and SR-IOV at the same time */ 2870 if (!!adapter->vfs_allocated_count) { 2871 max_rss_queues = 1; 2872 break; 2873 } 2874 /* fall through */ 2875 case e1000_82576: 2876 if (!!adapter->vfs_allocated_count) { 2877 max_rss_queues = 2; 2878 break; 2879 } 2880 /* fall through */ 2881 case e1000_82580: 2882 case e1000_i354: 2883 default: 2884 max_rss_queues = IGB_MAX_RX_QUEUES; 2885 break; 2886 } 2887 2888 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2889 2890 /* Determine if we need to pair queues. */ 2891 switch (hw->mac.type) { 2892 case e1000_82575: 2893 case e1000_i211: 2894 /* Device supports enough interrupts without queue pairing. */ 2895 break; 2896 case e1000_82576: 2897 /* If VFs are going to be allocated with RSS queues then we 2898 * should pair the queues in order to conserve interrupts due 2899 * to limited supply. 2900 */ 2901 if ((adapter->rss_queues > 1) && 2902 (adapter->vfs_allocated_count > 6)) 2903 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2904 /* fall through */ 2905 case e1000_82580: 2906 case e1000_i350: 2907 case e1000_i354: 2908 case e1000_i210: 2909 default: 2910 /* If rss_queues > half of max_rss_queues, pair the queues in 2911 * order to conserve interrupts due to limited supply. 2912 */ 2913 if (adapter->rss_queues > (max_rss_queues / 2)) 2914 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2915 break; 2916 } 2917} 2918 2919/** 2920 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2921 * @adapter: board private structure to initialize 2922 * 2923 * igb_sw_init initializes the Adapter private data structure. 2924 * Fields are initialized based on PCI device information and 2925 * OS network device settings (MTU size). 2926 **/ 2927static int igb_sw_init(struct igb_adapter *adapter) 2928{ 2929 struct e1000_hw *hw = &adapter->hw; 2930 struct net_device *netdev = adapter->netdev; 2931 struct pci_dev *pdev = adapter->pdev; 2932 2933 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2934 2935 /* set default ring sizes */ 2936 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2937 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2938 2939 /* set default ITR values */ 2940 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2941 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2942 2943 /* set default work limits */ 2944 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2945 2946 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2947 VLAN_HLEN; 2948 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2949 2950 spin_lock_init(&adapter->stats64_lock); 2951#ifdef CONFIG_PCI_IOV 2952 switch (hw->mac.type) { 2953 case e1000_82576: 2954 case e1000_i350: 2955 if (max_vfs > 7) { 2956 dev_warn(&pdev->dev, 2957 "Maximum of 7 VFs per PF, using max\n"); 2958 max_vfs = adapter->vfs_allocated_count = 7; 2959 } else 2960 adapter->vfs_allocated_count = max_vfs; 2961 if (adapter->vfs_allocated_count) 2962 dev_warn(&pdev->dev, 2963 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 2964 break; 2965 default: 2966 break; 2967 } 2968#endif /* CONFIG_PCI_IOV */ 2969 2970 igb_init_queue_configuration(adapter); 2971 2972 /* Setup and initialize a copy of the hw vlan table array */ 2973 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 2974 GFP_ATOMIC); 2975 2976 /* This call may decrease the number of queues */ 2977 if (igb_init_interrupt_scheme(adapter, true)) { 2978 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2979 return -ENOMEM; 2980 } 2981 2982 igb_probe_vfs(adapter); 2983 2984 /* Explicitly disable IRQ since the NIC can be in any state. */ 2985 igb_irq_disable(adapter); 2986 2987 if (hw->mac.type >= e1000_i350) 2988 adapter->flags &= ~IGB_FLAG_DMAC; 2989 2990 set_bit(__IGB_DOWN, &adapter->state); 2991 return 0; 2992} 2993 2994/** 2995 * igb_open - Called when a network interface is made active 2996 * @netdev: network interface device structure 2997 * 2998 * Returns 0 on success, negative value on failure 2999 * 3000 * The open entry point is called when a network interface is made 3001 * active by the system (IFF_UP). At this point all resources needed 3002 * for transmit and receive operations are allocated, the interrupt 3003 * handler is registered with the OS, the watchdog timer is started, 3004 * and the stack is notified that the interface is ready. 3005 **/ 3006static int __igb_open(struct net_device *netdev, bool resuming) 3007{ 3008 struct igb_adapter *adapter = netdev_priv(netdev); 3009 struct e1000_hw *hw = &adapter->hw; 3010 struct pci_dev *pdev = adapter->pdev; 3011 int err; 3012 int i; 3013 3014 /* disallow open during test */ 3015 if (test_bit(__IGB_TESTING, &adapter->state)) { 3016 WARN_ON(resuming); 3017 return -EBUSY; 3018 } 3019 3020 if (!resuming) 3021 pm_runtime_get_sync(&pdev->dev); 3022 3023 netif_carrier_off(netdev); 3024 3025 /* allocate transmit descriptors */ 3026 err = igb_setup_all_tx_resources(adapter); 3027 if (err) 3028 goto err_setup_tx; 3029 3030 /* allocate receive descriptors */ 3031 err = igb_setup_all_rx_resources(adapter); 3032 if (err) 3033 goto err_setup_rx; 3034 3035 igb_power_up_link(adapter); 3036 3037 /* before we allocate an interrupt, we must be ready to handle it. 3038 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3039 * as soon as we call pci_request_irq, so we have to setup our 3040 * clean_rx handler before we do so. 3041 */ 3042 igb_configure(adapter); 3043 3044 err = igb_request_irq(adapter); 3045 if (err) 3046 goto err_req_irq; 3047 3048 /* Notify the stack of the actual queue counts. */ 3049 err = netif_set_real_num_tx_queues(adapter->netdev, 3050 adapter->num_tx_queues); 3051 if (err) 3052 goto err_set_queues; 3053 3054 err = netif_set_real_num_rx_queues(adapter->netdev, 3055 adapter->num_rx_queues); 3056 if (err) 3057 goto err_set_queues; 3058 3059 /* From here on the code is the same as igb_up() */ 3060 clear_bit(__IGB_DOWN, &adapter->state); 3061 3062 for (i = 0; i < adapter->num_q_vectors; i++) 3063 napi_enable(&(adapter->q_vector[i]->napi)); 3064 3065 /* Clear any pending interrupts. */ 3066 rd32(E1000_ICR); 3067 3068 igb_irq_enable(adapter); 3069 3070 /* notify VFs that reset has been completed */ 3071 if (adapter->vfs_allocated_count) { 3072 u32 reg_data = rd32(E1000_CTRL_EXT); 3073 reg_data |= E1000_CTRL_EXT_PFRSTD; 3074 wr32(E1000_CTRL_EXT, reg_data); 3075 } 3076 3077 netif_tx_start_all_queues(netdev); 3078 3079 if (!resuming) 3080 pm_runtime_put(&pdev->dev); 3081 3082 /* start the watchdog. */ 3083 hw->mac.get_link_status = 1; 3084 schedule_work(&adapter->watchdog_task); 3085 3086 return 0; 3087 3088err_set_queues: 3089 igb_free_irq(adapter); 3090err_req_irq: 3091 igb_release_hw_control(adapter); 3092 igb_power_down_link(adapter); 3093 igb_free_all_rx_resources(adapter); 3094err_setup_rx: 3095 igb_free_all_tx_resources(adapter); 3096err_setup_tx: 3097 igb_reset(adapter); 3098 if (!resuming) 3099 pm_runtime_put(&pdev->dev); 3100 3101 return err; 3102} 3103 3104static int igb_open(struct net_device *netdev) 3105{ 3106 return __igb_open(netdev, false); 3107} 3108 3109/** 3110 * igb_close - Disables a network interface 3111 * @netdev: network interface device structure 3112 * 3113 * Returns 0, this is not allowed to fail 3114 * 3115 * The close entry point is called when an interface is de-activated 3116 * by the OS. The hardware is still under the driver's control, but 3117 * needs to be disabled. A global MAC reset is issued to stop the 3118 * hardware, and all transmit and receive resources are freed. 3119 **/ 3120static int __igb_close(struct net_device *netdev, bool suspending) 3121{ 3122 struct igb_adapter *adapter = netdev_priv(netdev); 3123 struct pci_dev *pdev = adapter->pdev; 3124 3125 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3126 3127 if (!suspending) 3128 pm_runtime_get_sync(&pdev->dev); 3129 3130 igb_down(adapter); 3131 igb_free_irq(adapter); 3132 3133 igb_free_all_tx_resources(adapter); 3134 igb_free_all_rx_resources(adapter); 3135 3136 if (!suspending) 3137 pm_runtime_put_sync(&pdev->dev); 3138 return 0; 3139} 3140 3141static int igb_close(struct net_device *netdev) 3142{ 3143 return __igb_close(netdev, false); 3144} 3145 3146/** 3147 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3148 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3149 * 3150 * Return 0 on success, negative on failure 3151 **/ 3152int igb_setup_tx_resources(struct igb_ring *tx_ring) 3153{ 3154 struct device *dev = tx_ring->dev; 3155 int size; 3156 3157 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3158 3159 tx_ring->tx_buffer_info = vzalloc(size); 3160 if (!tx_ring->tx_buffer_info) 3161 goto err; 3162 3163 /* round up to nearest 4K */ 3164 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3165 tx_ring->size = ALIGN(tx_ring->size, 4096); 3166 3167 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3168 &tx_ring->dma, GFP_KERNEL); 3169 if (!tx_ring->desc) 3170 goto err; 3171 3172 tx_ring->next_to_use = 0; 3173 tx_ring->next_to_clean = 0; 3174 3175 return 0; 3176 3177err: 3178 vfree(tx_ring->tx_buffer_info); 3179 tx_ring->tx_buffer_info = NULL; 3180 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3181 return -ENOMEM; 3182} 3183 3184/** 3185 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3186 * (Descriptors) for all queues 3187 * @adapter: board private structure 3188 * 3189 * Return 0 on success, negative on failure 3190 **/ 3191static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3192{ 3193 struct pci_dev *pdev = adapter->pdev; 3194 int i, err = 0; 3195 3196 for (i = 0; i < adapter->num_tx_queues; i++) { 3197 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3198 if (err) { 3199 dev_err(&pdev->dev, 3200 "Allocation for Tx Queue %u failed\n", i); 3201 for (i--; i >= 0; i--) 3202 igb_free_tx_resources(adapter->tx_ring[i]); 3203 break; 3204 } 3205 } 3206 3207 return err; 3208} 3209 3210/** 3211 * igb_setup_tctl - configure the transmit control registers 3212 * @adapter: Board private structure 3213 **/ 3214void igb_setup_tctl(struct igb_adapter *adapter) 3215{ 3216 struct e1000_hw *hw = &adapter->hw; 3217 u32 tctl; 3218 3219 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3220 wr32(E1000_TXDCTL(0), 0); 3221 3222 /* Program the Transmit Control Register */ 3223 tctl = rd32(E1000_TCTL); 3224 tctl &= ~E1000_TCTL_CT; 3225 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3226 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3227 3228 igb_config_collision_dist(hw); 3229 3230 /* Enable transmits */ 3231 tctl |= E1000_TCTL_EN; 3232 3233 wr32(E1000_TCTL, tctl); 3234} 3235 3236/** 3237 * igb_configure_tx_ring - Configure transmit ring after Reset 3238 * @adapter: board private structure 3239 * @ring: tx ring to configure 3240 * 3241 * Configure a transmit ring after a reset. 3242 **/ 3243void igb_configure_tx_ring(struct igb_adapter *adapter, 3244 struct igb_ring *ring) 3245{ 3246 struct e1000_hw *hw = &adapter->hw; 3247 u32 txdctl = 0; 3248 u64 tdba = ring->dma; 3249 int reg_idx = ring->reg_idx; 3250 3251 /* disable the queue */ 3252 wr32(E1000_TXDCTL(reg_idx), 0); 3253 wrfl(); 3254 mdelay(10); 3255 3256 wr32(E1000_TDLEN(reg_idx), 3257 ring->count * sizeof(union e1000_adv_tx_desc)); 3258 wr32(E1000_TDBAL(reg_idx), 3259 tdba & 0x00000000ffffffffULL); 3260 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3261 3262 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 3263 wr32(E1000_TDH(reg_idx), 0); 3264 writel(0, ring->tail); 3265 3266 txdctl |= IGB_TX_PTHRESH; 3267 txdctl |= IGB_TX_HTHRESH << 8; 3268 txdctl |= IGB_TX_WTHRESH << 16; 3269 3270 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3271 wr32(E1000_TXDCTL(reg_idx), txdctl); 3272} 3273 3274/** 3275 * igb_configure_tx - Configure transmit Unit after Reset 3276 * @adapter: board private structure 3277 * 3278 * Configure the Tx unit of the MAC after a reset. 3279 **/ 3280static void igb_configure_tx(struct igb_adapter *adapter) 3281{ 3282 int i; 3283 3284 for (i = 0; i < adapter->num_tx_queues; i++) 3285 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3286} 3287 3288/** 3289 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3290 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3291 * 3292 * Returns 0 on success, negative on failure 3293 **/ 3294int igb_setup_rx_resources(struct igb_ring *rx_ring) 3295{ 3296 struct device *dev = rx_ring->dev; 3297 int size; 3298 3299 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3300 3301 rx_ring->rx_buffer_info = vzalloc(size); 3302 if (!rx_ring->rx_buffer_info) 3303 goto err; 3304 3305 /* Round up to nearest 4K */ 3306 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3307 rx_ring->size = ALIGN(rx_ring->size, 4096); 3308 3309 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3310 &rx_ring->dma, GFP_KERNEL); 3311 if (!rx_ring->desc) 3312 goto err; 3313 3314 rx_ring->next_to_alloc = 0; 3315 rx_ring->next_to_clean = 0; 3316 rx_ring->next_to_use = 0; 3317 3318 return 0; 3319 3320err: 3321 vfree(rx_ring->rx_buffer_info); 3322 rx_ring->rx_buffer_info = NULL; 3323 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3324 return -ENOMEM; 3325} 3326 3327/** 3328 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3329 * (Descriptors) for all queues 3330 * @adapter: board private structure 3331 * 3332 * Return 0 on success, negative on failure 3333 **/ 3334static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3335{ 3336 struct pci_dev *pdev = adapter->pdev; 3337 int i, err = 0; 3338 3339 for (i = 0; i < adapter->num_rx_queues; i++) { 3340 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3341 if (err) { 3342 dev_err(&pdev->dev, 3343 "Allocation for Rx Queue %u failed\n", i); 3344 for (i--; i >= 0; i--) 3345 igb_free_rx_resources(adapter->rx_ring[i]); 3346 break; 3347 } 3348 } 3349 3350 return err; 3351} 3352 3353/** 3354 * igb_setup_mrqc - configure the multiple receive queue control registers 3355 * @adapter: Board private structure 3356 **/ 3357static void igb_setup_mrqc(struct igb_adapter *adapter) 3358{ 3359 struct e1000_hw *hw = &adapter->hw; 3360 u32 mrqc, rxcsum; 3361 u32 j, num_rx_queues; 3362 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, 3363 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, 3364 0xA32DCB77, 0x0CF23080, 0x3BB7426A, 3365 0xFA01ACBE }; 3366 3367 /* Fill out hash function seeds */ 3368 for (j = 0; j < 10; j++) 3369 wr32(E1000_RSSRK(j), rsskey[j]); 3370 3371 num_rx_queues = adapter->rss_queues; 3372 3373 switch (hw->mac.type) { 3374 case e1000_82576: 3375 /* 82576 supports 2 RSS queues for SR-IOV */ 3376 if (adapter->vfs_allocated_count) 3377 num_rx_queues = 2; 3378 break; 3379 default: 3380 break; 3381 } 3382 3383 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3384 for (j = 0; j < IGB_RETA_SIZE; j++) 3385 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE; 3386 adapter->rss_indir_tbl_init = num_rx_queues; 3387 } 3388 igb_write_rss_indir_tbl(adapter); 3389 3390 /* Disable raw packet checksumming so that RSS hash is placed in 3391 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3392 * offloads as they are enabled by default 3393 */ 3394 rxcsum = rd32(E1000_RXCSUM); 3395 rxcsum |= E1000_RXCSUM_PCSD; 3396 3397 if (adapter->hw.mac.type >= e1000_82576) 3398 /* Enable Receive Checksum Offload for SCTP */ 3399 rxcsum |= E1000_RXCSUM_CRCOFL; 3400 3401 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3402 wr32(E1000_RXCSUM, rxcsum); 3403 3404 /* Generate RSS hash based on packet types, TCP/UDP 3405 * port numbers and/or IPv4/v6 src and dst addresses 3406 */ 3407 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3408 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3409 E1000_MRQC_RSS_FIELD_IPV6 | 3410 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3411 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3412 3413 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3414 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3415 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3416 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3417 3418 /* If VMDq is enabled then we set the appropriate mode for that, else 3419 * we default to RSS so that an RSS hash is calculated per packet even 3420 * if we are only using one queue 3421 */ 3422 if (adapter->vfs_allocated_count) { 3423 if (hw->mac.type > e1000_82575) { 3424 /* Set the default pool for the PF's first queue */ 3425 u32 vtctl = rd32(E1000_VT_CTL); 3426 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3427 E1000_VT_CTL_DISABLE_DEF_POOL); 3428 vtctl |= adapter->vfs_allocated_count << 3429 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3430 wr32(E1000_VT_CTL, vtctl); 3431 } 3432 if (adapter->rss_queues > 1) 3433 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 3434 else 3435 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3436 } else { 3437 if (hw->mac.type != e1000_i211) 3438 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 3439 } 3440 igb_vmm_control(adapter); 3441 3442 wr32(E1000_MRQC, mrqc); 3443} 3444 3445/** 3446 * igb_setup_rctl - configure the receive control registers 3447 * @adapter: Board private structure 3448 **/ 3449void igb_setup_rctl(struct igb_adapter *adapter) 3450{ 3451 struct e1000_hw *hw = &adapter->hw; 3452 u32 rctl; 3453 3454 rctl = rd32(E1000_RCTL); 3455 3456 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3457 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3458 3459 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3460 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3461 3462 /* enable stripping of CRC. It's unlikely this will break BMC 3463 * redirection as it did with e1000. Newer features require 3464 * that the HW strips the CRC. 3465 */ 3466 rctl |= E1000_RCTL_SECRC; 3467 3468 /* disable store bad packets and clear size bits. */ 3469 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3470 3471 /* enable LPE to prevent packets larger than max_frame_size */ 3472 rctl |= E1000_RCTL_LPE; 3473 3474 /* disable queue 0 to prevent tail write w/o re-config */ 3475 wr32(E1000_RXDCTL(0), 0); 3476 3477 /* Attention!!! For SR-IOV PF driver operations you must enable 3478 * queue drop for all VF and PF queues to prevent head of line blocking 3479 * if an un-trusted VF does not provide descriptors to hardware. 3480 */ 3481 if (adapter->vfs_allocated_count) { 3482 /* set all queue drop enable bits */ 3483 wr32(E1000_QDE, ALL_QUEUES); 3484 } 3485 3486 /* This is useful for sniffing bad packets. */ 3487 if (adapter->netdev->features & NETIF_F_RXALL) { 3488 /* UPE and MPE will be handled by normal PROMISC logic 3489 * in e1000e_set_rx_mode 3490 */ 3491 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3492 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3493 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3494 3495 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3496 E1000_RCTL_DPF | /* Allow filtered pause */ 3497 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3498 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3499 * and that breaks VLANs. 3500 */ 3501 } 3502 3503 wr32(E1000_RCTL, rctl); 3504} 3505 3506static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3507 int vfn) 3508{ 3509 struct e1000_hw *hw = &adapter->hw; 3510 u32 vmolr; 3511 3512 /* if it isn't the PF check to see if VFs are enabled and 3513 * increase the size to support vlan tags 3514 */ 3515 if (vfn < adapter->vfs_allocated_count && 3516 adapter->vf_data[vfn].vlans_enabled) 3517 size += VLAN_TAG_SIZE; 3518 3519 vmolr = rd32(E1000_VMOLR(vfn)); 3520 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3521 vmolr |= size | E1000_VMOLR_LPE; 3522 wr32(E1000_VMOLR(vfn), vmolr); 3523 3524 return 0; 3525} 3526 3527/** 3528 * igb_rlpml_set - set maximum receive packet size 3529 * @adapter: board private structure 3530 * 3531 * Configure maximum receivable packet size. 3532 **/ 3533static void igb_rlpml_set(struct igb_adapter *adapter) 3534{ 3535 u32 max_frame_size = adapter->max_frame_size; 3536 struct e1000_hw *hw = &adapter->hw; 3537 u16 pf_id = adapter->vfs_allocated_count; 3538 3539 if (pf_id) { 3540 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3541 /* If we're in VMDQ or SR-IOV mode, then set global RLPML 3542 * to our max jumbo frame size, in case we need to enable 3543 * jumbo frames on one of the rings later. 3544 * This will not pass over-length frames into the default 3545 * queue because it's gated by the VMOLR.RLPML. 3546 */ 3547 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3548 } 3549 3550 wr32(E1000_RLPML, max_frame_size); 3551} 3552 3553static inline void igb_set_vmolr(struct igb_adapter *adapter, 3554 int vfn, bool aupe) 3555{ 3556 struct e1000_hw *hw = &adapter->hw; 3557 u32 vmolr; 3558 3559 /* This register exists only on 82576 and newer so if we are older then 3560 * we should exit and do nothing 3561 */ 3562 if (hw->mac.type < e1000_82576) 3563 return; 3564 3565 vmolr = rd32(E1000_VMOLR(vfn)); 3566 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3567 if (hw->mac.type == e1000_i350) { 3568 u32 dvmolr; 3569 3570 dvmolr = rd32(E1000_DVMOLR(vfn)); 3571 dvmolr |= E1000_DVMOLR_STRVLAN; 3572 wr32(E1000_DVMOLR(vfn), dvmolr); 3573 } 3574 if (aupe) 3575 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3576 else 3577 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3578 3579 /* clear all bits that might not be set */ 3580 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3581 3582 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3583 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3584 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3585 * multicast packets 3586 */ 3587 if (vfn <= adapter->vfs_allocated_count) 3588 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3589 3590 wr32(E1000_VMOLR(vfn), vmolr); 3591} 3592 3593/** 3594 * igb_configure_rx_ring - Configure a receive ring after Reset 3595 * @adapter: board private structure 3596 * @ring: receive ring to be configured 3597 * 3598 * Configure the Rx unit of the MAC after a reset. 3599 **/ 3600void igb_configure_rx_ring(struct igb_adapter *adapter, 3601 struct igb_ring *ring) 3602{ 3603 struct e1000_hw *hw = &adapter->hw; 3604 u64 rdba = ring->dma; 3605 int reg_idx = ring->reg_idx; 3606 u32 srrctl = 0, rxdctl = 0; 3607 3608 /* disable the queue */ 3609 wr32(E1000_RXDCTL(reg_idx), 0); 3610 3611 /* Set DMA base address registers */ 3612 wr32(E1000_RDBAL(reg_idx), 3613 rdba & 0x00000000ffffffffULL); 3614 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3615 wr32(E1000_RDLEN(reg_idx), 3616 ring->count * sizeof(union e1000_adv_rx_desc)); 3617 3618 /* initialize head and tail */ 3619 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3620 wr32(E1000_RDH(reg_idx), 0); 3621 writel(0, ring->tail); 3622 3623 /* set descriptor configuration */ 3624 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3625 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3626 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3627 if (hw->mac.type >= e1000_82580) 3628 srrctl |= E1000_SRRCTL_TIMESTAMP; 3629 /* Only set Drop Enable if we are supporting multiple queues */ 3630 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3631 srrctl |= E1000_SRRCTL_DROP_EN; 3632 3633 wr32(E1000_SRRCTL(reg_idx), srrctl); 3634 3635 /* set filtering for VMDQ pools */ 3636 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3637 3638 rxdctl |= IGB_RX_PTHRESH; 3639 rxdctl |= IGB_RX_HTHRESH << 8; 3640 rxdctl |= IGB_RX_WTHRESH << 16; 3641 3642 /* enable receive descriptor fetching */ 3643 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3644 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3645} 3646 3647/** 3648 * igb_configure_rx - Configure receive Unit after Reset 3649 * @adapter: board private structure 3650 * 3651 * Configure the Rx unit of the MAC after a reset. 3652 **/ 3653static void igb_configure_rx(struct igb_adapter *adapter) 3654{ 3655 int i; 3656 3657 /* set UTA to appropriate mode */ 3658 igb_set_uta(adapter); 3659 3660 /* set the correct pool for the PF default MAC address in entry 0 */ 3661 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3662 adapter->vfs_allocated_count); 3663 3664 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3665 * the Base and Length of the Rx Descriptor Ring 3666 */ 3667 for (i = 0; i < adapter->num_rx_queues; i++) 3668 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3669} 3670 3671/** 3672 * igb_free_tx_resources - Free Tx Resources per Queue 3673 * @tx_ring: Tx descriptor ring for a specific queue 3674 * 3675 * Free all transmit software resources 3676 **/ 3677void igb_free_tx_resources(struct igb_ring *tx_ring) 3678{ 3679 igb_clean_tx_ring(tx_ring); 3680 3681 vfree(tx_ring->tx_buffer_info); 3682 tx_ring->tx_buffer_info = NULL; 3683 3684 /* if not set, then don't free */ 3685 if (!tx_ring->desc) 3686 return; 3687 3688 dma_free_coherent(tx_ring->dev, tx_ring->size, 3689 tx_ring->desc, tx_ring->dma); 3690 3691 tx_ring->desc = NULL; 3692} 3693 3694/** 3695 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3696 * @adapter: board private structure 3697 * 3698 * Free all transmit software resources 3699 **/ 3700static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3701{ 3702 int i; 3703 3704 for (i = 0; i < adapter->num_tx_queues; i++) 3705 igb_free_tx_resources(adapter->tx_ring[i]); 3706} 3707 3708void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3709 struct igb_tx_buffer *tx_buffer) 3710{ 3711 if (tx_buffer->skb) { 3712 dev_kfree_skb_any(tx_buffer->skb); 3713 if (dma_unmap_len(tx_buffer, len)) 3714 dma_unmap_single(ring->dev, 3715 dma_unmap_addr(tx_buffer, dma), 3716 dma_unmap_len(tx_buffer, len), 3717 DMA_TO_DEVICE); 3718 } else if (dma_unmap_len(tx_buffer, len)) { 3719 dma_unmap_page(ring->dev, 3720 dma_unmap_addr(tx_buffer, dma), 3721 dma_unmap_len(tx_buffer, len), 3722 DMA_TO_DEVICE); 3723 } 3724 tx_buffer->next_to_watch = NULL; 3725 tx_buffer->skb = NULL; 3726 dma_unmap_len_set(tx_buffer, len, 0); 3727 /* buffer_info must be completely set up in the transmit path */ 3728} 3729 3730/** 3731 * igb_clean_tx_ring - Free Tx Buffers 3732 * @tx_ring: ring to be cleaned 3733 **/ 3734static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3735{ 3736 struct igb_tx_buffer *buffer_info; 3737 unsigned long size; 3738 u16 i; 3739 3740 if (!tx_ring->tx_buffer_info) 3741 return; 3742 /* Free all the Tx ring sk_buffs */ 3743 3744 for (i = 0; i < tx_ring->count; i++) { 3745 buffer_info = &tx_ring->tx_buffer_info[i]; 3746 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3747 } 3748 3749 netdev_tx_reset_queue(txring_txq(tx_ring)); 3750 3751 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3752 memset(tx_ring->tx_buffer_info, 0, size); 3753 3754 /* Zero out the descriptor ring */ 3755 memset(tx_ring->desc, 0, tx_ring->size); 3756 3757 tx_ring->next_to_use = 0; 3758 tx_ring->next_to_clean = 0; 3759} 3760 3761/** 3762 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3763 * @adapter: board private structure 3764 **/ 3765static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3766{ 3767 int i; 3768 3769 for (i = 0; i < adapter->num_tx_queues; i++) 3770 igb_clean_tx_ring(adapter->tx_ring[i]); 3771} 3772 3773/** 3774 * igb_free_rx_resources - Free Rx Resources 3775 * @rx_ring: ring to clean the resources from 3776 * 3777 * Free all receive software resources 3778 **/ 3779void igb_free_rx_resources(struct igb_ring *rx_ring) 3780{ 3781 igb_clean_rx_ring(rx_ring); 3782 3783 vfree(rx_ring->rx_buffer_info); 3784 rx_ring->rx_buffer_info = NULL; 3785 3786 /* if not set, then don't free */ 3787 if (!rx_ring->desc) 3788 return; 3789 3790 dma_free_coherent(rx_ring->dev, rx_ring->size, 3791 rx_ring->desc, rx_ring->dma); 3792 3793 rx_ring->desc = NULL; 3794} 3795 3796/** 3797 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3798 * @adapter: board private structure 3799 * 3800 * Free all receive software resources 3801 **/ 3802static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3803{ 3804 int i; 3805 3806 for (i = 0; i < adapter->num_rx_queues; i++) 3807 igb_free_rx_resources(adapter->rx_ring[i]); 3808} 3809 3810/** 3811 * igb_clean_rx_ring - Free Rx Buffers per Queue 3812 * @rx_ring: ring to free buffers from 3813 **/ 3814static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3815{ 3816 unsigned long size; 3817 u16 i; 3818 3819 if (rx_ring->skb) 3820 dev_kfree_skb(rx_ring->skb); 3821 rx_ring->skb = NULL; 3822 3823 if (!rx_ring->rx_buffer_info) 3824 return; 3825 3826 /* Free all the Rx ring sk_buffs */ 3827 for (i = 0; i < rx_ring->count; i++) { 3828 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3829 3830 if (!buffer_info->page) 3831 continue; 3832 3833 dma_unmap_page(rx_ring->dev, 3834 buffer_info->dma, 3835 PAGE_SIZE, 3836 DMA_FROM_DEVICE); 3837 __free_page(buffer_info->page); 3838 3839 buffer_info->page = NULL; 3840 } 3841 3842 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3843 memset(rx_ring->rx_buffer_info, 0, size); 3844 3845 /* Zero out the descriptor ring */ 3846 memset(rx_ring->desc, 0, rx_ring->size); 3847 3848 rx_ring->next_to_alloc = 0; 3849 rx_ring->next_to_clean = 0; 3850 rx_ring->next_to_use = 0; 3851} 3852 3853/** 3854 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3855 * @adapter: board private structure 3856 **/ 3857static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3858{ 3859 int i; 3860 3861 for (i = 0; i < adapter->num_rx_queues; i++) 3862 igb_clean_rx_ring(adapter->rx_ring[i]); 3863} 3864 3865/** 3866 * igb_set_mac - Change the Ethernet Address of the NIC 3867 * @netdev: network interface device structure 3868 * @p: pointer to an address structure 3869 * 3870 * Returns 0 on success, negative on failure 3871 **/ 3872static int igb_set_mac(struct net_device *netdev, void *p) 3873{ 3874 struct igb_adapter *adapter = netdev_priv(netdev); 3875 struct e1000_hw *hw = &adapter->hw; 3876 struct sockaddr *addr = p; 3877 3878 if (!is_valid_ether_addr(addr->sa_data)) 3879 return -EADDRNOTAVAIL; 3880 3881 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3882 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3883 3884 /* set the correct pool for the new PF MAC address in entry 0 */ 3885 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3886 adapter->vfs_allocated_count); 3887 3888 return 0; 3889} 3890 3891/** 3892 * igb_write_mc_addr_list - write multicast addresses to MTA 3893 * @netdev: network interface device structure 3894 * 3895 * Writes multicast address list to the MTA hash table. 3896 * Returns: -ENOMEM on failure 3897 * 0 on no addresses written 3898 * X on writing X addresses to MTA 3899 **/ 3900static int igb_write_mc_addr_list(struct net_device *netdev) 3901{ 3902 struct igb_adapter *adapter = netdev_priv(netdev); 3903 struct e1000_hw *hw = &adapter->hw; 3904 struct netdev_hw_addr *ha; 3905 u8 *mta_list; 3906 int i; 3907 3908 if (netdev_mc_empty(netdev)) { 3909 /* nothing to program, so clear mc list */ 3910 igb_update_mc_addr_list(hw, NULL, 0); 3911 igb_restore_vf_multicasts(adapter); 3912 return 0; 3913 } 3914 3915 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3916 if (!mta_list) 3917 return -ENOMEM; 3918 3919 /* The shared function expects a packed array of only addresses. */ 3920 i = 0; 3921 netdev_for_each_mc_addr(ha, netdev) 3922 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3923 3924 igb_update_mc_addr_list(hw, mta_list, i); 3925 kfree(mta_list); 3926 3927 return netdev_mc_count(netdev); 3928} 3929 3930/** 3931 * igb_write_uc_addr_list - write unicast addresses to RAR table 3932 * @netdev: network interface device structure 3933 * 3934 * Writes unicast address list to the RAR table. 3935 * Returns: -ENOMEM on failure/insufficient address space 3936 * 0 on no addresses written 3937 * X on writing X addresses to the RAR table 3938 **/ 3939static int igb_write_uc_addr_list(struct net_device *netdev) 3940{ 3941 struct igb_adapter *adapter = netdev_priv(netdev); 3942 struct e1000_hw *hw = &adapter->hw; 3943 unsigned int vfn = adapter->vfs_allocated_count; 3944 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3945 int count = 0; 3946 3947 /* return ENOMEM indicating insufficient memory for addresses */ 3948 if (netdev_uc_count(netdev) > rar_entries) 3949 return -ENOMEM; 3950 3951 if (!netdev_uc_empty(netdev) && rar_entries) { 3952 struct netdev_hw_addr *ha; 3953 3954 netdev_for_each_uc_addr(ha, netdev) { 3955 if (!rar_entries) 3956 break; 3957 igb_rar_set_qsel(adapter, ha->addr, 3958 rar_entries--, 3959 vfn); 3960 count++; 3961 } 3962 } 3963 /* write the addresses in reverse order to avoid write combining */ 3964 for (; rar_entries > 0 ; rar_entries--) { 3965 wr32(E1000_RAH(rar_entries), 0); 3966 wr32(E1000_RAL(rar_entries), 0); 3967 } 3968 wrfl(); 3969 3970 return count; 3971} 3972 3973/** 3974 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3975 * @netdev: network interface device structure 3976 * 3977 * The set_rx_mode entry point is called whenever the unicast or multicast 3978 * address lists or the network interface flags are updated. This routine is 3979 * responsible for configuring the hardware for proper unicast, multicast, 3980 * promiscuous mode, and all-multi behavior. 3981 **/ 3982static void igb_set_rx_mode(struct net_device *netdev) 3983{ 3984 struct igb_adapter *adapter = netdev_priv(netdev); 3985 struct e1000_hw *hw = &adapter->hw; 3986 unsigned int vfn = adapter->vfs_allocated_count; 3987 u32 rctl, vmolr = 0; 3988 int count; 3989 3990 /* Check for Promiscuous and All Multicast modes */ 3991 rctl = rd32(E1000_RCTL); 3992 3993 /* clear the effected bits */ 3994 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 3995 3996 if (netdev->flags & IFF_PROMISC) { 3997 /* retain VLAN HW filtering if in VT mode */ 3998 if (adapter->vfs_allocated_count) 3999 rctl |= E1000_RCTL_VFE; 4000 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 4001 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 4002 } else { 4003 if (netdev->flags & IFF_ALLMULTI) { 4004 rctl |= E1000_RCTL_MPE; 4005 vmolr |= E1000_VMOLR_MPME; 4006 } else { 4007 /* Write addresses to the MTA, if the attempt fails 4008 * then we should just turn on promiscuous mode so 4009 * that we can at least receive multicast traffic 4010 */ 4011 count = igb_write_mc_addr_list(netdev); 4012 if (count < 0) { 4013 rctl |= E1000_RCTL_MPE; 4014 vmolr |= E1000_VMOLR_MPME; 4015 } else if (count) { 4016 vmolr |= E1000_VMOLR_ROMPE; 4017 } 4018 } 4019 /* Write addresses to available RAR registers, if there is not 4020 * sufficient space to store all the addresses then enable 4021 * unicast promiscuous mode 4022 */ 4023 count = igb_write_uc_addr_list(netdev); 4024 if (count < 0) { 4025 rctl |= E1000_RCTL_UPE; 4026 vmolr |= E1000_VMOLR_ROPE; 4027 } 4028 rctl |= E1000_RCTL_VFE; 4029 } 4030 wr32(E1000_RCTL, rctl); 4031 4032 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4033 * the VMOLR to enable the appropriate modes. Without this workaround 4034 * we will have issues with VLAN tag stripping not being done for frames 4035 * that are only arriving because we are the default pool 4036 */ 4037 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4038 return; 4039 4040 vmolr |= rd32(E1000_VMOLR(vfn)) & 4041 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4042 wr32(E1000_VMOLR(vfn), vmolr); 4043 igb_restore_vf_multicasts(adapter); 4044} 4045 4046static void igb_check_wvbr(struct igb_adapter *adapter) 4047{ 4048 struct e1000_hw *hw = &adapter->hw; 4049 u32 wvbr = 0; 4050 4051 switch (hw->mac.type) { 4052 case e1000_82576: 4053 case e1000_i350: 4054 if (!(wvbr = rd32(E1000_WVBR))) 4055 return; 4056 break; 4057 default: 4058 break; 4059 } 4060 4061 adapter->wvbr |= wvbr; 4062} 4063 4064#define IGB_STAGGERED_QUEUE_OFFSET 8 4065 4066static void igb_spoof_check(struct igb_adapter *adapter) 4067{ 4068 int j; 4069 4070 if (!adapter->wvbr) 4071 return; 4072 4073 for(j = 0; j < adapter->vfs_allocated_count; j++) { 4074 if (adapter->wvbr & (1 << j) || 4075 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 4076 dev_warn(&adapter->pdev->dev, 4077 "Spoof event(s) detected on VF %d\n", j); 4078 adapter->wvbr &= 4079 ~((1 << j) | 4080 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 4081 } 4082 } 4083} 4084 4085/* Need to wait a few seconds after link up to get diagnostic information from 4086 * the phy 4087 */ 4088static void igb_update_phy_info(unsigned long data) 4089{ 4090 struct igb_adapter *adapter = (struct igb_adapter *) data; 4091 igb_get_phy_info(&adapter->hw); 4092} 4093 4094/** 4095 * igb_has_link - check shared code for link and determine up/down 4096 * @adapter: pointer to driver private info 4097 **/ 4098bool igb_has_link(struct igb_adapter *adapter) 4099{ 4100 struct e1000_hw *hw = &adapter->hw; 4101 bool link_active = false; 4102 4103 /* get_link_status is set on LSC (link status) interrupt or 4104 * rx sequence error interrupt. get_link_status will stay 4105 * false until the e1000_check_for_link establishes link 4106 * for copper adapters ONLY 4107 */ 4108 switch (hw->phy.media_type) { 4109 case e1000_media_type_copper: 4110 if (!hw->mac.get_link_status) 4111 return true; 4112 case e1000_media_type_internal_serdes: 4113 hw->mac.ops.check_for_link(hw); 4114 link_active = !hw->mac.get_link_status; 4115 break; 4116 default: 4117 case e1000_media_type_unknown: 4118 break; 4119 } 4120 4121 if (((hw->mac.type == e1000_i210) || 4122 (hw->mac.type == e1000_i211)) && 4123 (hw->phy.id == I210_I_PHY_ID)) { 4124 if (!netif_carrier_ok(adapter->netdev)) { 4125 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4126 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4127 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4128 adapter->link_check_timeout = jiffies; 4129 } 4130 } 4131 4132 return link_active; 4133} 4134 4135static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4136{ 4137 bool ret = false; 4138 u32 ctrl_ext, thstat; 4139 4140 /* check for thermal sensor event on i350 copper only */ 4141 if (hw->mac.type == e1000_i350) { 4142 thstat = rd32(E1000_THSTAT); 4143 ctrl_ext = rd32(E1000_CTRL_EXT); 4144 4145 if ((hw->phy.media_type == e1000_media_type_copper) && 4146 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4147 ret = !!(thstat & event); 4148 } 4149 4150 return ret; 4151} 4152 4153/** 4154 * igb_watchdog - Timer Call-back 4155 * @data: pointer to adapter cast into an unsigned long 4156 **/ 4157static void igb_watchdog(unsigned long data) 4158{ 4159 struct igb_adapter *adapter = (struct igb_adapter *)data; 4160 /* Do the rest outside of interrupt context */ 4161 schedule_work(&adapter->watchdog_task); 4162} 4163 4164static void igb_watchdog_task(struct work_struct *work) 4165{ 4166 struct igb_adapter *adapter = container_of(work, 4167 struct igb_adapter, 4168 watchdog_task); 4169 struct e1000_hw *hw = &adapter->hw; 4170 struct e1000_phy_info *phy = &hw->phy; 4171 struct net_device *netdev = adapter->netdev; 4172 u32 link; 4173 int i; 4174 u32 connsw; 4175 4176 link = igb_has_link(adapter); 4177 4178 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4179 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4180 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4181 else 4182 link = false; 4183 } 4184 4185 /* Force link down if we have fiber to swap to */ 4186 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4187 if (hw->phy.media_type == e1000_media_type_copper) { 4188 connsw = rd32(E1000_CONNSW); 4189 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4190 link = 0; 4191 } 4192 } 4193 if (link) { 4194 /* Perform a reset if the media type changed. */ 4195 if (hw->dev_spec._82575.media_changed) { 4196 hw->dev_spec._82575.media_changed = false; 4197 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4198 igb_reset(adapter); 4199 } 4200 /* Cancel scheduled suspend requests. */ 4201 pm_runtime_resume(netdev->dev.parent); 4202 4203 if (!netif_carrier_ok(netdev)) { 4204 u32 ctrl; 4205 hw->mac.ops.get_speed_and_duplex(hw, 4206 &adapter->link_speed, 4207 &adapter->link_duplex); 4208 4209 ctrl = rd32(E1000_CTRL); 4210 /* Links status message must follow this format */ 4211 netdev_info(netdev, 4212 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4213 netdev->name, 4214 adapter->link_speed, 4215 adapter->link_duplex == FULL_DUPLEX ? 4216 "Full" : "Half", 4217 (ctrl & E1000_CTRL_TFCE) && 4218 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4219 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4220 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4221 4222 /* disable EEE if enabled */ 4223 if ((adapter->flags & IGB_FLAG_EEE) && 4224 (adapter->link_duplex == HALF_DUPLEX)) { 4225 dev_info(&adapter->pdev->dev, 4226 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4227 adapter->hw.dev_spec._82575.eee_disable = true; 4228 adapter->flags &= ~IGB_FLAG_EEE; 4229 } 4230 4231 /* check if SmartSpeed worked */ 4232 igb_check_downshift(hw); 4233 if (phy->speed_downgraded) 4234 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4235 4236 /* check for thermal sensor event */ 4237 if (igb_thermal_sensor_event(hw, 4238 E1000_THSTAT_LINK_THROTTLE)) 4239 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 4240 4241 /* adjust timeout factor according to speed/duplex */ 4242 adapter->tx_timeout_factor = 1; 4243 switch (adapter->link_speed) { 4244 case SPEED_10: 4245 adapter->tx_timeout_factor = 14; 4246 break; 4247 case SPEED_100: 4248 /* maybe add some timeout factor ? */ 4249 break; 4250 } 4251 4252 netif_carrier_on(netdev); 4253 4254 igb_ping_all_vfs(adapter); 4255 igb_check_vf_rate_limit(adapter); 4256 4257 /* link state has changed, schedule phy info update */ 4258 if (!test_bit(__IGB_DOWN, &adapter->state)) 4259 mod_timer(&adapter->phy_info_timer, 4260 round_jiffies(jiffies + 2 * HZ)); 4261 } 4262 } else { 4263 if (netif_carrier_ok(netdev)) { 4264 adapter->link_speed = 0; 4265 adapter->link_duplex = 0; 4266 4267 /* check for thermal sensor event */ 4268 if (igb_thermal_sensor_event(hw, 4269 E1000_THSTAT_PWR_DOWN)) { 4270 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 4271 } 4272 4273 /* Links status message must follow this format */ 4274 netdev_info(netdev, "igb: %s NIC Link is Down\n", 4275 netdev->name); 4276 netif_carrier_off(netdev); 4277 4278 igb_ping_all_vfs(adapter); 4279 4280 /* link state has changed, schedule phy info update */ 4281 if (!test_bit(__IGB_DOWN, &adapter->state)) 4282 mod_timer(&adapter->phy_info_timer, 4283 round_jiffies(jiffies + 2 * HZ)); 4284 4285 /* link is down, time to check for alternate media */ 4286 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4287 igb_check_swap_media(adapter); 4288 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4289 schedule_work(&adapter->reset_task); 4290 /* return immediately */ 4291 return; 4292 } 4293 } 4294 pm_schedule_suspend(netdev->dev.parent, 4295 MSEC_PER_SEC * 5); 4296 4297 /* also check for alternate media here */ 4298 } else if (!netif_carrier_ok(netdev) && 4299 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4300 igb_check_swap_media(adapter); 4301 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4302 schedule_work(&adapter->reset_task); 4303 /* return immediately */ 4304 return; 4305 } 4306 } 4307 } 4308 4309 spin_lock(&adapter->stats64_lock); 4310 igb_update_stats(adapter, &adapter->stats64); 4311 spin_unlock(&adapter->stats64_lock); 4312 4313 for (i = 0; i < adapter->num_tx_queues; i++) { 4314 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4315 if (!netif_carrier_ok(netdev)) { 4316 /* We've lost link, so the controller stops DMA, 4317 * but we've got queued Tx work that's never going 4318 * to get done, so reset controller to flush Tx. 4319 * (Do the reset outside of interrupt context). 4320 */ 4321 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4322 adapter->tx_timeout_count++; 4323 schedule_work(&adapter->reset_task); 4324 /* return immediately since reset is imminent */ 4325 return; 4326 } 4327 } 4328 4329 /* Force detection of hung controller every watchdog period */ 4330 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4331 } 4332 4333 /* Cause software interrupt to ensure Rx ring is cleaned */ 4334 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4335 u32 eics = 0; 4336 for (i = 0; i < adapter->num_q_vectors; i++) 4337 eics |= adapter->q_vector[i]->eims_value; 4338 wr32(E1000_EICS, eics); 4339 } else { 4340 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4341 } 4342 4343 igb_spoof_check(adapter); 4344 igb_ptp_rx_hang(adapter); 4345 4346 /* Reset the timer */ 4347 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4348 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4349 mod_timer(&adapter->watchdog_timer, 4350 round_jiffies(jiffies + HZ)); 4351 else 4352 mod_timer(&adapter->watchdog_timer, 4353 round_jiffies(jiffies + 2 * HZ)); 4354 } 4355} 4356 4357enum latency_range { 4358 lowest_latency = 0, 4359 low_latency = 1, 4360 bulk_latency = 2, 4361 latency_invalid = 255 4362}; 4363 4364/** 4365 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4366 * @q_vector: pointer to q_vector 4367 * 4368 * Stores a new ITR value based on strictly on packet size. This 4369 * algorithm is less sophisticated than that used in igb_update_itr, 4370 * due to the difficulty of synchronizing statistics across multiple 4371 * receive rings. The divisors and thresholds used by this function 4372 * were determined based on theoretical maximum wire speed and testing 4373 * data, in order to minimize response time while increasing bulk 4374 * throughput. 4375 * This functionality is controlled by ethtool's coalescing settings. 4376 * NOTE: This function is called only when operating in a multiqueue 4377 * receive environment. 4378 **/ 4379static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4380{ 4381 int new_val = q_vector->itr_val; 4382 int avg_wire_size = 0; 4383 struct igb_adapter *adapter = q_vector->adapter; 4384 unsigned int packets; 4385 4386 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4387 * ints/sec - ITR timer value of 120 ticks. 4388 */ 4389 if (adapter->link_speed != SPEED_1000) { 4390 new_val = IGB_4K_ITR; 4391 goto set_itr_val; 4392 } 4393 4394 packets = q_vector->rx.total_packets; 4395 if (packets) 4396 avg_wire_size = q_vector->rx.total_bytes / packets; 4397 4398 packets = q_vector->tx.total_packets; 4399 if (packets) 4400 avg_wire_size = max_t(u32, avg_wire_size, 4401 q_vector->tx.total_bytes / packets); 4402 4403 /* if avg_wire_size isn't set no work was done */ 4404 if (!avg_wire_size) 4405 goto clear_counts; 4406 4407 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4408 avg_wire_size += 24; 4409 4410 /* Don't starve jumbo frames */ 4411 avg_wire_size = min(avg_wire_size, 3000); 4412 4413 /* Give a little boost to mid-size frames */ 4414 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4415 new_val = avg_wire_size / 3; 4416 else 4417 new_val = avg_wire_size / 2; 4418 4419 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4420 if (new_val < IGB_20K_ITR && 4421 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4422 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4423 new_val = IGB_20K_ITR; 4424 4425set_itr_val: 4426 if (new_val != q_vector->itr_val) { 4427 q_vector->itr_val = new_val; 4428 q_vector->set_itr = 1; 4429 } 4430clear_counts: 4431 q_vector->rx.total_bytes = 0; 4432 q_vector->rx.total_packets = 0; 4433 q_vector->tx.total_bytes = 0; 4434 q_vector->tx.total_packets = 0; 4435} 4436 4437/** 4438 * igb_update_itr - update the dynamic ITR value based on statistics 4439 * @q_vector: pointer to q_vector 4440 * @ring_container: ring info to update the itr for 4441 * 4442 * Stores a new ITR value based on packets and byte 4443 * counts during the last interrupt. The advantage of per interrupt 4444 * computation is faster updates and more accurate ITR for the current 4445 * traffic pattern. Constants in this function were computed 4446 * based on theoretical maximum wire speed and thresholds were set based 4447 * on testing data as well as attempting to minimize response time 4448 * while increasing bulk throughput. 4449 * This functionality is controlled by ethtool's coalescing settings. 4450 * NOTE: These calculations are only valid when operating in a single- 4451 * queue environment. 4452 **/ 4453static void igb_update_itr(struct igb_q_vector *q_vector, 4454 struct igb_ring_container *ring_container) 4455{ 4456 unsigned int packets = ring_container->total_packets; 4457 unsigned int bytes = ring_container->total_bytes; 4458 u8 itrval = ring_container->itr; 4459 4460 /* no packets, exit with status unchanged */ 4461 if (packets == 0) 4462 return; 4463 4464 switch (itrval) { 4465 case lowest_latency: 4466 /* handle TSO and jumbo frames */ 4467 if (bytes/packets > 8000) 4468 itrval = bulk_latency; 4469 else if ((packets < 5) && (bytes > 512)) 4470 itrval = low_latency; 4471 break; 4472 case low_latency: /* 50 usec aka 20000 ints/s */ 4473 if (bytes > 10000) { 4474 /* this if handles the TSO accounting */ 4475 if (bytes/packets > 8000) 4476 itrval = bulk_latency; 4477 else if ((packets < 10) || ((bytes/packets) > 1200)) 4478 itrval = bulk_latency; 4479 else if ((packets > 35)) 4480 itrval = lowest_latency; 4481 } else if (bytes/packets > 2000) { 4482 itrval = bulk_latency; 4483 } else if (packets <= 2 && bytes < 512) { 4484 itrval = lowest_latency; 4485 } 4486 break; 4487 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4488 if (bytes > 25000) { 4489 if (packets > 35) 4490 itrval = low_latency; 4491 } else if (bytes < 1500) { 4492 itrval = low_latency; 4493 } 4494 break; 4495 } 4496 4497 /* clear work counters since we have the values we need */ 4498 ring_container->total_bytes = 0; 4499 ring_container->total_packets = 0; 4500 4501 /* write updated itr to ring container */ 4502 ring_container->itr = itrval; 4503} 4504 4505static void igb_set_itr(struct igb_q_vector *q_vector) 4506{ 4507 struct igb_adapter *adapter = q_vector->adapter; 4508 u32 new_itr = q_vector->itr_val; 4509 u8 current_itr = 0; 4510 4511 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4512 if (adapter->link_speed != SPEED_1000) { 4513 current_itr = 0; 4514 new_itr = IGB_4K_ITR; 4515 goto set_itr_now; 4516 } 4517 4518 igb_update_itr(q_vector, &q_vector->tx); 4519 igb_update_itr(q_vector, &q_vector->rx); 4520 4521 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4522 4523 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4524 if (current_itr == lowest_latency && 4525 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4526 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4527 current_itr = low_latency; 4528 4529 switch (current_itr) { 4530 /* counts and packets in update_itr are dependent on these numbers */ 4531 case lowest_latency: 4532 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4533 break; 4534 case low_latency: 4535 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4536 break; 4537 case bulk_latency: 4538 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4539 break; 4540 default: 4541 break; 4542 } 4543 4544set_itr_now: 4545 if (new_itr != q_vector->itr_val) { 4546 /* this attempts to bias the interrupt rate towards Bulk 4547 * by adding intermediate steps when interrupt rate is 4548 * increasing 4549 */ 4550 new_itr = new_itr > q_vector->itr_val ? 4551 max((new_itr * q_vector->itr_val) / 4552 (new_itr + (q_vector->itr_val >> 2)), 4553 new_itr) : new_itr; 4554 /* Don't write the value here; it resets the adapter's 4555 * internal timer, and causes us to delay far longer than 4556 * we should between interrupts. Instead, we write the ITR 4557 * value at the beginning of the next interrupt so the timing 4558 * ends up being correct. 4559 */ 4560 q_vector->itr_val = new_itr; 4561 q_vector->set_itr = 1; 4562 } 4563} 4564 4565static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4566 u32 type_tucmd, u32 mss_l4len_idx) 4567{ 4568 struct e1000_adv_tx_context_desc *context_desc; 4569 u16 i = tx_ring->next_to_use; 4570 4571 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4572 4573 i++; 4574 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4575 4576 /* set bits to identify this as an advanced context descriptor */ 4577 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4578 4579 /* For 82575, context index must be unique per ring. */ 4580 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4581 mss_l4len_idx |= tx_ring->reg_idx << 4; 4582 4583 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4584 context_desc->seqnum_seed = 0; 4585 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4586 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4587} 4588 4589static int igb_tso(struct igb_ring *tx_ring, 4590 struct igb_tx_buffer *first, 4591 u8 *hdr_len) 4592{ 4593 struct sk_buff *skb = first->skb; 4594 u32 vlan_macip_lens, type_tucmd; 4595 u32 mss_l4len_idx, l4len; 4596 int err; 4597 4598 if (skb->ip_summed != CHECKSUM_PARTIAL) 4599 return 0; 4600 4601 if (!skb_is_gso(skb)) 4602 return 0; 4603 4604 err = skb_cow_head(skb, 0); 4605 if (err < 0) 4606 return err; 4607 4608 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4609 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4610 4611 if (first->protocol == htons(ETH_P_IP)) { 4612 struct iphdr *iph = ip_hdr(skb); 4613 iph->tot_len = 0; 4614 iph->check = 0; 4615 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4616 iph->daddr, 0, 4617 IPPROTO_TCP, 4618 0); 4619 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4620 first->tx_flags |= IGB_TX_FLAGS_TSO | 4621 IGB_TX_FLAGS_CSUM | 4622 IGB_TX_FLAGS_IPV4; 4623 } else if (skb_is_gso_v6(skb)) { 4624 ipv6_hdr(skb)->payload_len = 0; 4625 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4626 &ipv6_hdr(skb)->daddr, 4627 0, IPPROTO_TCP, 0); 4628 first->tx_flags |= IGB_TX_FLAGS_TSO | 4629 IGB_TX_FLAGS_CSUM; 4630 } 4631 4632 /* compute header lengths */ 4633 l4len = tcp_hdrlen(skb); 4634 *hdr_len = skb_transport_offset(skb) + l4len; 4635 4636 /* update gso size and bytecount with header size */ 4637 first->gso_segs = skb_shinfo(skb)->gso_segs; 4638 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4639 4640 /* MSS L4LEN IDX */ 4641 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4642 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4643 4644 /* VLAN MACLEN IPLEN */ 4645 vlan_macip_lens = skb_network_header_len(skb); 4646 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4647 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4648 4649 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4650 4651 return 1; 4652} 4653 4654static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4655{ 4656 struct sk_buff *skb = first->skb; 4657 u32 vlan_macip_lens = 0; 4658 u32 mss_l4len_idx = 0; 4659 u32 type_tucmd = 0; 4660 4661 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4662 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4663 return; 4664 } else { 4665 u8 l4_hdr = 0; 4666 switch (first->protocol) { 4667 case htons(ETH_P_IP): 4668 vlan_macip_lens |= skb_network_header_len(skb); 4669 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4670 l4_hdr = ip_hdr(skb)->protocol; 4671 break; 4672 case htons(ETH_P_IPV6): 4673 vlan_macip_lens |= skb_network_header_len(skb); 4674 l4_hdr = ipv6_hdr(skb)->nexthdr; 4675 break; 4676 default: 4677 if (unlikely(net_ratelimit())) { 4678 dev_warn(tx_ring->dev, 4679 "partial checksum but proto=%x!\n", 4680 first->protocol); 4681 } 4682 break; 4683 } 4684 4685 switch (l4_hdr) { 4686 case IPPROTO_TCP: 4687 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4688 mss_l4len_idx = tcp_hdrlen(skb) << 4689 E1000_ADVTXD_L4LEN_SHIFT; 4690 break; 4691 case IPPROTO_SCTP: 4692 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4693 mss_l4len_idx = sizeof(struct sctphdr) << 4694 E1000_ADVTXD_L4LEN_SHIFT; 4695 break; 4696 case IPPROTO_UDP: 4697 mss_l4len_idx = sizeof(struct udphdr) << 4698 E1000_ADVTXD_L4LEN_SHIFT; 4699 break; 4700 default: 4701 if (unlikely(net_ratelimit())) { 4702 dev_warn(tx_ring->dev, 4703 "partial checksum but l4 proto=%x!\n", 4704 l4_hdr); 4705 } 4706 break; 4707 } 4708 4709 /* update TX checksum flag */ 4710 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4711 } 4712 4713 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4714 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4715 4716 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4717} 4718 4719#define IGB_SET_FLAG(_input, _flag, _result) \ 4720 ((_flag <= _result) ? \ 4721 ((u32)(_input & _flag) * (_result / _flag)) : \ 4722 ((u32)(_input & _flag) / (_flag / _result))) 4723 4724static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 4725{ 4726 /* set type for advanced descriptor with frame checksum insertion */ 4727 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 4728 E1000_ADVTXD_DCMD_DEXT | 4729 E1000_ADVTXD_DCMD_IFCS; 4730 4731 /* set HW vlan bit if vlan is present */ 4732 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 4733 (E1000_ADVTXD_DCMD_VLE)); 4734 4735 /* set segmentation bits for TSO */ 4736 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 4737 (E1000_ADVTXD_DCMD_TSE)); 4738 4739 /* set timestamp bit if present */ 4740 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 4741 (E1000_ADVTXD_MAC_TSTAMP)); 4742 4743 /* insert frame checksum */ 4744 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 4745 4746 return cmd_type; 4747} 4748 4749static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4750 union e1000_adv_tx_desc *tx_desc, 4751 u32 tx_flags, unsigned int paylen) 4752{ 4753 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4754 4755 /* 82575 requires a unique index per ring */ 4756 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4757 olinfo_status |= tx_ring->reg_idx << 4; 4758 4759 /* insert L4 checksum */ 4760 olinfo_status |= IGB_SET_FLAG(tx_flags, 4761 IGB_TX_FLAGS_CSUM, 4762 (E1000_TXD_POPTS_TXSM << 8)); 4763 4764 /* insert IPv4 checksum */ 4765 olinfo_status |= IGB_SET_FLAG(tx_flags, 4766 IGB_TX_FLAGS_IPV4, 4767 (E1000_TXD_POPTS_IXSM << 8)); 4768 4769 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4770} 4771 4772static void igb_tx_map(struct igb_ring *tx_ring, 4773 struct igb_tx_buffer *first, 4774 const u8 hdr_len) 4775{ 4776 struct sk_buff *skb = first->skb; 4777 struct igb_tx_buffer *tx_buffer; 4778 union e1000_adv_tx_desc *tx_desc; 4779 struct skb_frag_struct *frag; 4780 dma_addr_t dma; 4781 unsigned int data_len, size; 4782 u32 tx_flags = first->tx_flags; 4783 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 4784 u16 i = tx_ring->next_to_use; 4785 4786 tx_desc = IGB_TX_DESC(tx_ring, i); 4787 4788 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 4789 4790 size = skb_headlen(skb); 4791 data_len = skb->data_len; 4792 4793 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4794 4795 tx_buffer = first; 4796 4797 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 4798 if (dma_mapping_error(tx_ring->dev, dma)) 4799 goto dma_error; 4800 4801 /* record length, and DMA address */ 4802 dma_unmap_len_set(tx_buffer, len, size); 4803 dma_unmap_addr_set(tx_buffer, dma, dma); 4804 4805 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4806 4807 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4808 tx_desc->read.cmd_type_len = 4809 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 4810 4811 i++; 4812 tx_desc++; 4813 if (i == tx_ring->count) { 4814 tx_desc = IGB_TX_DESC(tx_ring, 0); 4815 i = 0; 4816 } 4817 tx_desc->read.olinfo_status = 0; 4818 4819 dma += IGB_MAX_DATA_PER_TXD; 4820 size -= IGB_MAX_DATA_PER_TXD; 4821 4822 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4823 } 4824 4825 if (likely(!data_len)) 4826 break; 4827 4828 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 4829 4830 i++; 4831 tx_desc++; 4832 if (i == tx_ring->count) { 4833 tx_desc = IGB_TX_DESC(tx_ring, 0); 4834 i = 0; 4835 } 4836 tx_desc->read.olinfo_status = 0; 4837 4838 size = skb_frag_size(frag); 4839 data_len -= size; 4840 4841 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4842 size, DMA_TO_DEVICE); 4843 4844 tx_buffer = &tx_ring->tx_buffer_info[i]; 4845 } 4846 4847 /* write last descriptor with RS and EOP bits */ 4848 cmd_type |= size | IGB_TXD_DCMD; 4849 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 4850 4851 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4852 4853 /* set the timestamp */ 4854 first->time_stamp = jiffies; 4855 4856 /* Force memory writes to complete before letting h/w know there 4857 * are new descriptors to fetch. (Only applicable for weak-ordered 4858 * memory model archs, such as IA-64). 4859 * 4860 * We also need this memory barrier to make certain all of the 4861 * status bits have been updated before next_to_watch is written. 4862 */ 4863 wmb(); 4864 4865 /* set next_to_watch value indicating a packet is present */ 4866 first->next_to_watch = tx_desc; 4867 4868 i++; 4869 if (i == tx_ring->count) 4870 i = 0; 4871 4872 tx_ring->next_to_use = i; 4873 4874 writel(i, tx_ring->tail); 4875 4876 /* we need this if more than one processor can write to our tail 4877 * at a time, it synchronizes IO on IA64/Altix systems 4878 */ 4879 mmiowb(); 4880 4881 return; 4882 4883dma_error: 4884 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4885 4886 /* clear dma mappings for failed tx_buffer_info map */ 4887 for (;;) { 4888 tx_buffer = &tx_ring->tx_buffer_info[i]; 4889 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4890 if (tx_buffer == first) 4891 break; 4892 if (i == 0) 4893 i = tx_ring->count; 4894 i--; 4895 } 4896 4897 tx_ring->next_to_use = i; 4898} 4899 4900static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4901{ 4902 struct net_device *netdev = tx_ring->netdev; 4903 4904 netif_stop_subqueue(netdev, tx_ring->queue_index); 4905 4906 /* Herbert's original patch had: 4907 * smp_mb__after_netif_stop_queue(); 4908 * but since that doesn't exist yet, just open code it. 4909 */ 4910 smp_mb(); 4911 4912 /* We need to check again in a case another CPU has just 4913 * made room available. 4914 */ 4915 if (igb_desc_unused(tx_ring) < size) 4916 return -EBUSY; 4917 4918 /* A reprieve! */ 4919 netif_wake_subqueue(netdev, tx_ring->queue_index); 4920 4921 u64_stats_update_begin(&tx_ring->tx_syncp2); 4922 tx_ring->tx_stats.restart_queue2++; 4923 u64_stats_update_end(&tx_ring->tx_syncp2); 4924 4925 return 0; 4926} 4927 4928static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4929{ 4930 if (igb_desc_unused(tx_ring) >= size) 4931 return 0; 4932 return __igb_maybe_stop_tx(tx_ring, size); 4933} 4934 4935netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4936 struct igb_ring *tx_ring) 4937{ 4938 struct igb_tx_buffer *first; 4939 int tso; 4940 u32 tx_flags = 0; 4941 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 4942 __be16 protocol = vlan_get_protocol(skb); 4943 u8 hdr_len = 0; 4944 4945 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 4946 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 4947 * + 2 desc gap to keep tail from touching head, 4948 * + 1 desc for context descriptor, 4949 * otherwise try next time 4950 */ 4951 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) { 4952 unsigned short f; 4953 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 4954 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 4955 } else { 4956 count += skb_shinfo(skb)->nr_frags; 4957 } 4958 4959 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 4960 /* this is a hard error */ 4961 return NETDEV_TX_BUSY; 4962 } 4963 4964 /* record the location of the first descriptor for this packet */ 4965 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 4966 first->skb = skb; 4967 first->bytecount = skb->len; 4968 first->gso_segs = 1; 4969 4970 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 4971 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 4972 4973 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 4974 &adapter->state)) { 4975 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4976 tx_flags |= IGB_TX_FLAGS_TSTAMP; 4977 4978 adapter->ptp_tx_skb = skb_get(skb); 4979 adapter->ptp_tx_start = jiffies; 4980 if (adapter->hw.mac.type == e1000_82576) 4981 schedule_work(&adapter->ptp_tx_work); 4982 } 4983 } 4984 4985 skb_tx_timestamp(skb); 4986 4987 if (vlan_tx_tag_present(skb)) { 4988 tx_flags |= IGB_TX_FLAGS_VLAN; 4989 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 4990 } 4991 4992 /* record initial flags and protocol */ 4993 first->tx_flags = tx_flags; 4994 first->protocol = protocol; 4995 4996 tso = igb_tso(tx_ring, first, &hdr_len); 4997 if (tso < 0) 4998 goto out_drop; 4999 else if (!tso) 5000 igb_tx_csum(tx_ring, first); 5001 5002 igb_tx_map(tx_ring, first, hdr_len); 5003 5004 /* Make sure there is space in the ring for the next send. */ 5005 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 5006 5007 return NETDEV_TX_OK; 5008 5009out_drop: 5010 igb_unmap_and_free_tx_resource(tx_ring, first); 5011 5012 return NETDEV_TX_OK; 5013} 5014 5015static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5016 struct sk_buff *skb) 5017{ 5018 unsigned int r_idx = skb->queue_mapping; 5019 5020 if (r_idx >= adapter->num_tx_queues) 5021 r_idx = r_idx % adapter->num_tx_queues; 5022 5023 return adapter->tx_ring[r_idx]; 5024} 5025 5026static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5027 struct net_device *netdev) 5028{ 5029 struct igb_adapter *adapter = netdev_priv(netdev); 5030 5031 if (test_bit(__IGB_DOWN, &adapter->state)) { 5032 dev_kfree_skb_any(skb); 5033 return NETDEV_TX_OK; 5034 } 5035 5036 if (skb->len <= 0) { 5037 dev_kfree_skb_any(skb); 5038 return NETDEV_TX_OK; 5039 } 5040 5041 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5042 * in order to meet this minimum size requirement. 5043 */ 5044 if (unlikely(skb->len < 17)) { 5045 if (skb_pad(skb, 17 - skb->len)) 5046 return NETDEV_TX_OK; 5047 skb->len = 17; 5048 skb_set_tail_pointer(skb, 17); 5049 } 5050 5051 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5052} 5053 5054/** 5055 * igb_tx_timeout - Respond to a Tx Hang 5056 * @netdev: network interface device structure 5057 **/ 5058static void igb_tx_timeout(struct net_device *netdev) 5059{ 5060 struct igb_adapter *adapter = netdev_priv(netdev); 5061 struct e1000_hw *hw = &adapter->hw; 5062 5063 /* Do the reset outside of interrupt context */ 5064 adapter->tx_timeout_count++; 5065 5066 if (hw->mac.type >= e1000_82580) 5067 hw->dev_spec._82575.global_device_reset = true; 5068 5069 schedule_work(&adapter->reset_task); 5070 wr32(E1000_EICS, 5071 (adapter->eims_enable_mask & ~adapter->eims_other)); 5072} 5073 5074static void igb_reset_task(struct work_struct *work) 5075{ 5076 struct igb_adapter *adapter; 5077 adapter = container_of(work, struct igb_adapter, reset_task); 5078 5079 igb_dump(adapter); 5080 netdev_err(adapter->netdev, "Reset adapter\n"); 5081 igb_reinit_locked(adapter); 5082} 5083 5084/** 5085 * igb_get_stats64 - Get System Network Statistics 5086 * @netdev: network interface device structure 5087 * @stats: rtnl_link_stats64 pointer 5088 **/ 5089static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 5090 struct rtnl_link_stats64 *stats) 5091{ 5092 struct igb_adapter *adapter = netdev_priv(netdev); 5093 5094 spin_lock(&adapter->stats64_lock); 5095 igb_update_stats(adapter, &adapter->stats64); 5096 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5097 spin_unlock(&adapter->stats64_lock); 5098 5099 return stats; 5100} 5101 5102/** 5103 * igb_change_mtu - Change the Maximum Transfer Unit 5104 * @netdev: network interface device structure 5105 * @new_mtu: new value for maximum frame size 5106 * 5107 * Returns 0 on success, negative on failure 5108 **/ 5109static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5110{ 5111 struct igb_adapter *adapter = netdev_priv(netdev); 5112 struct pci_dev *pdev = adapter->pdev; 5113 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5114 5115 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 5116 dev_err(&pdev->dev, "Invalid MTU setting\n"); 5117 return -EINVAL; 5118 } 5119 5120#define MAX_STD_JUMBO_FRAME_SIZE 9238 5121 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 5122 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 5123 return -EINVAL; 5124 } 5125 5126 /* adjust max frame to be at least the size of a standard frame */ 5127 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5128 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5129 5130 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5131 msleep(1); 5132 5133 /* igb_down has a dependency on max_frame_size */ 5134 adapter->max_frame_size = max_frame; 5135 5136 if (netif_running(netdev)) 5137 igb_down(adapter); 5138 5139 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5140 netdev->mtu, new_mtu); 5141 netdev->mtu = new_mtu; 5142 5143 if (netif_running(netdev)) 5144 igb_up(adapter); 5145 else 5146 igb_reset(adapter); 5147 5148 clear_bit(__IGB_RESETTING, &adapter->state); 5149 5150 return 0; 5151} 5152 5153/** 5154 * igb_update_stats - Update the board statistics counters 5155 * @adapter: board private structure 5156 **/ 5157void igb_update_stats(struct igb_adapter *adapter, 5158 struct rtnl_link_stats64 *net_stats) 5159{ 5160 struct e1000_hw *hw = &adapter->hw; 5161 struct pci_dev *pdev = adapter->pdev; 5162 u32 reg, mpc; 5163 u16 phy_tmp; 5164 int i; 5165 u64 bytes, packets; 5166 unsigned int start; 5167 u64 _bytes, _packets; 5168 5169#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF 5170 5171 /* Prevent stats update while adapter is being reset, or if the pci 5172 * connection is down. 5173 */ 5174 if (adapter->link_speed == 0) 5175 return; 5176 if (pci_channel_offline(pdev)) 5177 return; 5178 5179 bytes = 0; 5180 packets = 0; 5181 5182 rcu_read_lock(); 5183 for (i = 0; i < adapter->num_rx_queues; i++) { 5184 u32 rqdpc = rd32(E1000_RQDPC(i)); 5185 struct igb_ring *ring = adapter->rx_ring[i]; 5186 5187 if (rqdpc) { 5188 ring->rx_stats.drops += rqdpc; 5189 net_stats->rx_fifo_errors += rqdpc; 5190 } 5191 5192 do { 5193 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5194 _bytes = ring->rx_stats.bytes; 5195 _packets = ring->rx_stats.packets; 5196 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5197 bytes += _bytes; 5198 packets += _packets; 5199 } 5200 5201 net_stats->rx_bytes = bytes; 5202 net_stats->rx_packets = packets; 5203 5204 bytes = 0; 5205 packets = 0; 5206 for (i = 0; i < adapter->num_tx_queues; i++) { 5207 struct igb_ring *ring = adapter->tx_ring[i]; 5208 do { 5209 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5210 _bytes = ring->tx_stats.bytes; 5211 _packets = ring->tx_stats.packets; 5212 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5213 bytes += _bytes; 5214 packets += _packets; 5215 } 5216 net_stats->tx_bytes = bytes; 5217 net_stats->tx_packets = packets; 5218 rcu_read_unlock(); 5219 5220 /* read stats registers */ 5221 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5222 adapter->stats.gprc += rd32(E1000_GPRC); 5223 adapter->stats.gorc += rd32(E1000_GORCL); 5224 rd32(E1000_GORCH); /* clear GORCL */ 5225 adapter->stats.bprc += rd32(E1000_BPRC); 5226 adapter->stats.mprc += rd32(E1000_MPRC); 5227 adapter->stats.roc += rd32(E1000_ROC); 5228 5229 adapter->stats.prc64 += rd32(E1000_PRC64); 5230 adapter->stats.prc127 += rd32(E1000_PRC127); 5231 adapter->stats.prc255 += rd32(E1000_PRC255); 5232 adapter->stats.prc511 += rd32(E1000_PRC511); 5233 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5234 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5235 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5236 adapter->stats.sec += rd32(E1000_SEC); 5237 5238 mpc = rd32(E1000_MPC); 5239 adapter->stats.mpc += mpc; 5240 net_stats->rx_fifo_errors += mpc; 5241 adapter->stats.scc += rd32(E1000_SCC); 5242 adapter->stats.ecol += rd32(E1000_ECOL); 5243 adapter->stats.mcc += rd32(E1000_MCC); 5244 adapter->stats.latecol += rd32(E1000_LATECOL); 5245 adapter->stats.dc += rd32(E1000_DC); 5246 adapter->stats.rlec += rd32(E1000_RLEC); 5247 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5248 adapter->stats.xontxc += rd32(E1000_XONTXC); 5249 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5250 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5251 adapter->stats.fcruc += rd32(E1000_FCRUC); 5252 adapter->stats.gptc += rd32(E1000_GPTC); 5253 adapter->stats.gotc += rd32(E1000_GOTCL); 5254 rd32(E1000_GOTCH); /* clear GOTCL */ 5255 adapter->stats.rnbc += rd32(E1000_RNBC); 5256 adapter->stats.ruc += rd32(E1000_RUC); 5257 adapter->stats.rfc += rd32(E1000_RFC); 5258 adapter->stats.rjc += rd32(E1000_RJC); 5259 adapter->stats.tor += rd32(E1000_TORH); 5260 adapter->stats.tot += rd32(E1000_TOTH); 5261 adapter->stats.tpr += rd32(E1000_TPR); 5262 5263 adapter->stats.ptc64 += rd32(E1000_PTC64); 5264 adapter->stats.ptc127 += rd32(E1000_PTC127); 5265 adapter->stats.ptc255 += rd32(E1000_PTC255); 5266 adapter->stats.ptc511 += rd32(E1000_PTC511); 5267 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5268 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5269 5270 adapter->stats.mptc += rd32(E1000_MPTC); 5271 adapter->stats.bptc += rd32(E1000_BPTC); 5272 5273 adapter->stats.tpt += rd32(E1000_TPT); 5274 adapter->stats.colc += rd32(E1000_COLC); 5275 5276 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5277 /* read internal phy specific stats */ 5278 reg = rd32(E1000_CTRL_EXT); 5279 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5280 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5281 5282 /* this stat has invalid values on i210/i211 */ 5283 if ((hw->mac.type != e1000_i210) && 5284 (hw->mac.type != e1000_i211)) 5285 adapter->stats.tncrs += rd32(E1000_TNCRS); 5286 } 5287 5288 adapter->stats.tsctc += rd32(E1000_TSCTC); 5289 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5290 5291 adapter->stats.iac += rd32(E1000_IAC); 5292 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5293 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5294 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5295 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5296 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5297 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5298 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5299 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5300 5301 /* Fill out the OS statistics structure */ 5302 net_stats->multicast = adapter->stats.mprc; 5303 net_stats->collisions = adapter->stats.colc; 5304 5305 /* Rx Errors */ 5306 5307 /* RLEC on some newer hardware can be incorrect so build 5308 * our own version based on RUC and ROC 5309 */ 5310 net_stats->rx_errors = adapter->stats.rxerrc + 5311 adapter->stats.crcerrs + adapter->stats.algnerrc + 5312 adapter->stats.ruc + adapter->stats.roc + 5313 adapter->stats.cexterr; 5314 net_stats->rx_length_errors = adapter->stats.ruc + 5315 adapter->stats.roc; 5316 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5317 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5318 net_stats->rx_missed_errors = adapter->stats.mpc; 5319 5320 /* Tx Errors */ 5321 net_stats->tx_errors = adapter->stats.ecol + 5322 adapter->stats.latecol; 5323 net_stats->tx_aborted_errors = adapter->stats.ecol; 5324 net_stats->tx_window_errors = adapter->stats.latecol; 5325 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5326 5327 /* Tx Dropped needs to be maintained elsewhere */ 5328 5329 /* Phy Stats */ 5330 if (hw->phy.media_type == e1000_media_type_copper) { 5331 if ((adapter->link_speed == SPEED_1000) && 5332 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 5333 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; 5334 adapter->phy_stats.idle_errors += phy_tmp; 5335 } 5336 } 5337 5338 /* Management Stats */ 5339 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5340 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5341 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5342 5343 /* OS2BMC Stats */ 5344 reg = rd32(E1000_MANC); 5345 if (reg & E1000_MANC_EN_BMC2OS) { 5346 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5347 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5348 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5349 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5350 } 5351} 5352 5353static irqreturn_t igb_msix_other(int irq, void *data) 5354{ 5355 struct igb_adapter *adapter = data; 5356 struct e1000_hw *hw = &adapter->hw; 5357 u32 icr = rd32(E1000_ICR); 5358 /* reading ICR causes bit 31 of EICR to be cleared */ 5359 5360 if (icr & E1000_ICR_DRSTA) 5361 schedule_work(&adapter->reset_task); 5362 5363 if (icr & E1000_ICR_DOUTSYNC) { 5364 /* HW is reporting DMA is out of sync */ 5365 adapter->stats.doosync++; 5366 /* The DMA Out of Sync is also indication of a spoof event 5367 * in IOV mode. Check the Wrong VM Behavior register to 5368 * see if it is really a spoof event. 5369 */ 5370 igb_check_wvbr(adapter); 5371 } 5372 5373 /* Check for a mailbox event */ 5374 if (icr & E1000_ICR_VMMB) 5375 igb_msg_task(adapter); 5376 5377 if (icr & E1000_ICR_LSC) { 5378 hw->mac.get_link_status = 1; 5379 /* guard against interrupt when we're going down */ 5380 if (!test_bit(__IGB_DOWN, &adapter->state)) 5381 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5382 } 5383 5384 if (icr & E1000_ICR_TS) { 5385 u32 tsicr = rd32(E1000_TSICR); 5386 5387 if (tsicr & E1000_TSICR_TXTS) { 5388 /* acknowledge the interrupt */ 5389 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5390 /* retrieve hardware timestamp */ 5391 schedule_work(&adapter->ptp_tx_work); 5392 } 5393 } 5394 5395 wr32(E1000_EIMS, adapter->eims_other); 5396 5397 return IRQ_HANDLED; 5398} 5399 5400static void igb_write_itr(struct igb_q_vector *q_vector) 5401{ 5402 struct igb_adapter *adapter = q_vector->adapter; 5403 u32 itr_val = q_vector->itr_val & 0x7FFC; 5404 5405 if (!q_vector->set_itr) 5406 return; 5407 5408 if (!itr_val) 5409 itr_val = 0x4; 5410 5411 if (adapter->hw.mac.type == e1000_82575) 5412 itr_val |= itr_val << 16; 5413 else 5414 itr_val |= E1000_EITR_CNT_IGNR; 5415 5416 writel(itr_val, q_vector->itr_register); 5417 q_vector->set_itr = 0; 5418} 5419 5420static irqreturn_t igb_msix_ring(int irq, void *data) 5421{ 5422 struct igb_q_vector *q_vector = data; 5423 5424 /* Write the ITR value calculated from the previous interrupt. */ 5425 igb_write_itr(q_vector); 5426 5427 napi_schedule(&q_vector->napi); 5428 5429 return IRQ_HANDLED; 5430} 5431 5432#ifdef CONFIG_IGB_DCA 5433static void igb_update_tx_dca(struct igb_adapter *adapter, 5434 struct igb_ring *tx_ring, 5435 int cpu) 5436{ 5437 struct e1000_hw *hw = &adapter->hw; 5438 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5439 5440 if (hw->mac.type != e1000_82575) 5441 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5442 5443 /* We can enable relaxed ordering for reads, but not writes when 5444 * DCA is enabled. This is due to a known issue in some chipsets 5445 * which will cause the DCA tag to be cleared. 5446 */ 5447 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5448 E1000_DCA_TXCTRL_DATA_RRO_EN | 5449 E1000_DCA_TXCTRL_DESC_DCA_EN; 5450 5451 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5452} 5453 5454static void igb_update_rx_dca(struct igb_adapter *adapter, 5455 struct igb_ring *rx_ring, 5456 int cpu) 5457{ 5458 struct e1000_hw *hw = &adapter->hw; 5459 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5460 5461 if (hw->mac.type != e1000_82575) 5462 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5463 5464 /* We can enable relaxed ordering for reads, but not writes when 5465 * DCA is enabled. This is due to a known issue in some chipsets 5466 * which will cause the DCA tag to be cleared. 5467 */ 5468 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5469 E1000_DCA_RXCTRL_DESC_DCA_EN; 5470 5471 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5472} 5473 5474static void igb_update_dca(struct igb_q_vector *q_vector) 5475{ 5476 struct igb_adapter *adapter = q_vector->adapter; 5477 int cpu = get_cpu(); 5478 5479 if (q_vector->cpu == cpu) 5480 goto out_no_update; 5481 5482 if (q_vector->tx.ring) 5483 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5484 5485 if (q_vector->rx.ring) 5486 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5487 5488 q_vector->cpu = cpu; 5489out_no_update: 5490 put_cpu(); 5491} 5492 5493static void igb_setup_dca(struct igb_adapter *adapter) 5494{ 5495 struct e1000_hw *hw = &adapter->hw; 5496 int i; 5497 5498 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5499 return; 5500 5501 /* Always use CB2 mode, difference is masked in the CB driver. */ 5502 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5503 5504 for (i = 0; i < adapter->num_q_vectors; i++) { 5505 adapter->q_vector[i]->cpu = -1; 5506 igb_update_dca(adapter->q_vector[i]); 5507 } 5508} 5509 5510static int __igb_notify_dca(struct device *dev, void *data) 5511{ 5512 struct net_device *netdev = dev_get_drvdata(dev); 5513 struct igb_adapter *adapter = netdev_priv(netdev); 5514 struct pci_dev *pdev = adapter->pdev; 5515 struct e1000_hw *hw = &adapter->hw; 5516 unsigned long event = *(unsigned long *)data; 5517 5518 switch (event) { 5519 case DCA_PROVIDER_ADD: 5520 /* if already enabled, don't do it again */ 5521 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5522 break; 5523 if (dca_add_requester(dev) == 0) { 5524 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5525 dev_info(&pdev->dev, "DCA enabled\n"); 5526 igb_setup_dca(adapter); 5527 break; 5528 } 5529 /* Fall Through since DCA is disabled. */ 5530 case DCA_PROVIDER_REMOVE: 5531 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5532 /* without this a class_device is left 5533 * hanging around in the sysfs model 5534 */ 5535 dca_remove_requester(dev); 5536 dev_info(&pdev->dev, "DCA disabled\n"); 5537 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5538 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5539 } 5540 break; 5541 } 5542 5543 return 0; 5544} 5545 5546static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5547 void *p) 5548{ 5549 int ret_val; 5550 5551 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5552 __igb_notify_dca); 5553 5554 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5555} 5556#endif /* CONFIG_IGB_DCA */ 5557 5558#ifdef CONFIG_PCI_IOV 5559static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5560{ 5561 unsigned char mac_addr[ETH_ALEN]; 5562 5563 eth_zero_addr(mac_addr); 5564 igb_set_vf_mac(adapter, vf, mac_addr); 5565 5566 /* By default spoof check is enabled for all VFs */ 5567 adapter->vf_data[vf].spoofchk_enabled = true; 5568 5569 return 0; 5570} 5571 5572#endif 5573static void igb_ping_all_vfs(struct igb_adapter *adapter) 5574{ 5575 struct e1000_hw *hw = &adapter->hw; 5576 u32 ping; 5577 int i; 5578 5579 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5580 ping = E1000_PF_CONTROL_MSG; 5581 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5582 ping |= E1000_VT_MSGTYPE_CTS; 5583 igb_write_mbx(hw, &ping, 1, i); 5584 } 5585} 5586 5587static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5588{ 5589 struct e1000_hw *hw = &adapter->hw; 5590 u32 vmolr = rd32(E1000_VMOLR(vf)); 5591 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5592 5593 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5594 IGB_VF_FLAG_MULTI_PROMISC); 5595 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5596 5597 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5598 vmolr |= E1000_VMOLR_MPME; 5599 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5600 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5601 } else { 5602 /* if we have hashes and we are clearing a multicast promisc 5603 * flag we need to write the hashes to the MTA as this step 5604 * was previously skipped 5605 */ 5606 if (vf_data->num_vf_mc_hashes > 30) { 5607 vmolr |= E1000_VMOLR_MPME; 5608 } else if (vf_data->num_vf_mc_hashes) { 5609 int j; 5610 vmolr |= E1000_VMOLR_ROMPE; 5611 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5612 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5613 } 5614 } 5615 5616 wr32(E1000_VMOLR(vf), vmolr); 5617 5618 /* there are flags left unprocessed, likely not supported */ 5619 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5620 return -EINVAL; 5621 5622 return 0; 5623} 5624 5625static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5626 u32 *msgbuf, u32 vf) 5627{ 5628 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5629 u16 *hash_list = (u16 *)&msgbuf[1]; 5630 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5631 int i; 5632 5633 /* salt away the number of multicast addresses assigned 5634 * to this VF for later use to restore when the PF multi cast 5635 * list changes 5636 */ 5637 vf_data->num_vf_mc_hashes = n; 5638 5639 /* only up to 30 hash values supported */ 5640 if (n > 30) 5641 n = 30; 5642 5643 /* store the hashes for later use */ 5644 for (i = 0; i < n; i++) 5645 vf_data->vf_mc_hashes[i] = hash_list[i]; 5646 5647 /* Flush and reset the mta with the new values */ 5648 igb_set_rx_mode(adapter->netdev); 5649 5650 return 0; 5651} 5652 5653static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5654{ 5655 struct e1000_hw *hw = &adapter->hw; 5656 struct vf_data_storage *vf_data; 5657 int i, j; 5658 5659 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5660 u32 vmolr = rd32(E1000_VMOLR(i)); 5661 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5662 5663 vf_data = &adapter->vf_data[i]; 5664 5665 if ((vf_data->num_vf_mc_hashes > 30) || 5666 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5667 vmolr |= E1000_VMOLR_MPME; 5668 } else if (vf_data->num_vf_mc_hashes) { 5669 vmolr |= E1000_VMOLR_ROMPE; 5670 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5671 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5672 } 5673 wr32(E1000_VMOLR(i), vmolr); 5674 } 5675} 5676 5677static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5678{ 5679 struct e1000_hw *hw = &adapter->hw; 5680 u32 pool_mask, reg, vid; 5681 int i; 5682 5683 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5684 5685 /* Find the vlan filter for this id */ 5686 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5687 reg = rd32(E1000_VLVF(i)); 5688 5689 /* remove the vf from the pool */ 5690 reg &= ~pool_mask; 5691 5692 /* if pool is empty then remove entry from vfta */ 5693 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5694 (reg & E1000_VLVF_VLANID_ENABLE)) { 5695 reg = 0; 5696 vid = reg & E1000_VLVF_VLANID_MASK; 5697 igb_vfta_set(hw, vid, false); 5698 } 5699 5700 wr32(E1000_VLVF(i), reg); 5701 } 5702 5703 adapter->vf_data[vf].vlans_enabled = 0; 5704} 5705 5706static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5707{ 5708 struct e1000_hw *hw = &adapter->hw; 5709 u32 reg, i; 5710 5711 /* The vlvf table only exists on 82576 hardware and newer */ 5712 if (hw->mac.type < e1000_82576) 5713 return -1; 5714 5715 /* we only need to do this if VMDq is enabled */ 5716 if (!adapter->vfs_allocated_count) 5717 return -1; 5718 5719 /* Find the vlan filter for this id */ 5720 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5721 reg = rd32(E1000_VLVF(i)); 5722 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5723 vid == (reg & E1000_VLVF_VLANID_MASK)) 5724 break; 5725 } 5726 5727 if (add) { 5728 if (i == E1000_VLVF_ARRAY_SIZE) { 5729 /* Did not find a matching VLAN ID entry that was 5730 * enabled. Search for a free filter entry, i.e. 5731 * one without the enable bit set 5732 */ 5733 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5734 reg = rd32(E1000_VLVF(i)); 5735 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5736 break; 5737 } 5738 } 5739 if (i < E1000_VLVF_ARRAY_SIZE) { 5740 /* Found an enabled/available entry */ 5741 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5742 5743 /* if !enabled we need to set this up in vfta */ 5744 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5745 /* add VID to filter table */ 5746 igb_vfta_set(hw, vid, true); 5747 reg |= E1000_VLVF_VLANID_ENABLE; 5748 } 5749 reg &= ~E1000_VLVF_VLANID_MASK; 5750 reg |= vid; 5751 wr32(E1000_VLVF(i), reg); 5752 5753 /* do not modify RLPML for PF devices */ 5754 if (vf >= adapter->vfs_allocated_count) 5755 return 0; 5756 5757 if (!adapter->vf_data[vf].vlans_enabled) { 5758 u32 size; 5759 reg = rd32(E1000_VMOLR(vf)); 5760 size = reg & E1000_VMOLR_RLPML_MASK; 5761 size += 4; 5762 reg &= ~E1000_VMOLR_RLPML_MASK; 5763 reg |= size; 5764 wr32(E1000_VMOLR(vf), reg); 5765 } 5766 5767 adapter->vf_data[vf].vlans_enabled++; 5768 } 5769 } else { 5770 if (i < E1000_VLVF_ARRAY_SIZE) { 5771 /* remove vf from the pool */ 5772 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5773 /* if pool is empty then remove entry from vfta */ 5774 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5775 reg = 0; 5776 igb_vfta_set(hw, vid, false); 5777 } 5778 wr32(E1000_VLVF(i), reg); 5779 5780 /* do not modify RLPML for PF devices */ 5781 if (vf >= adapter->vfs_allocated_count) 5782 return 0; 5783 5784 adapter->vf_data[vf].vlans_enabled--; 5785 if (!adapter->vf_data[vf].vlans_enabled) { 5786 u32 size; 5787 reg = rd32(E1000_VMOLR(vf)); 5788 size = reg & E1000_VMOLR_RLPML_MASK; 5789 size -= 4; 5790 reg &= ~E1000_VMOLR_RLPML_MASK; 5791 reg |= size; 5792 wr32(E1000_VMOLR(vf), reg); 5793 } 5794 } 5795 } 5796 return 0; 5797} 5798 5799static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5800{ 5801 struct e1000_hw *hw = &adapter->hw; 5802 5803 if (vid) 5804 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5805 else 5806 wr32(E1000_VMVIR(vf), 0); 5807} 5808 5809static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5810 int vf, u16 vlan, u8 qos) 5811{ 5812 int err = 0; 5813 struct igb_adapter *adapter = netdev_priv(netdev); 5814 5815 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5816 return -EINVAL; 5817 if (vlan || qos) { 5818 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5819 if (err) 5820 goto out; 5821 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5822 igb_set_vmolr(adapter, vf, !vlan); 5823 adapter->vf_data[vf].pf_vlan = vlan; 5824 adapter->vf_data[vf].pf_qos = qos; 5825 dev_info(&adapter->pdev->dev, 5826 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5827 if (test_bit(__IGB_DOWN, &adapter->state)) { 5828 dev_warn(&adapter->pdev->dev, 5829 "The VF VLAN has been set, but the PF device is not up.\n"); 5830 dev_warn(&adapter->pdev->dev, 5831 "Bring the PF device up before attempting to use the VF device.\n"); 5832 } 5833 } else { 5834 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5835 false, vf); 5836 igb_set_vmvir(adapter, vlan, vf); 5837 igb_set_vmolr(adapter, vf, true); 5838 adapter->vf_data[vf].pf_vlan = 0; 5839 adapter->vf_data[vf].pf_qos = 0; 5840 } 5841out: 5842 return err; 5843} 5844 5845static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid) 5846{ 5847 struct e1000_hw *hw = &adapter->hw; 5848 int i; 5849 u32 reg; 5850 5851 /* Find the vlan filter for this id */ 5852 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5853 reg = rd32(E1000_VLVF(i)); 5854 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5855 vid == (reg & E1000_VLVF_VLANID_MASK)) 5856 break; 5857 } 5858 5859 if (i >= E1000_VLVF_ARRAY_SIZE) 5860 i = -1; 5861 5862 return i; 5863} 5864 5865static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5866{ 5867 struct e1000_hw *hw = &adapter->hw; 5868 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5869 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5870 int err = 0; 5871 5872 /* If in promiscuous mode we need to make sure the PF also has 5873 * the VLAN filter set. 5874 */ 5875 if (add && (adapter->netdev->flags & IFF_PROMISC)) 5876 err = igb_vlvf_set(adapter, vid, add, 5877 adapter->vfs_allocated_count); 5878 if (err) 5879 goto out; 5880 5881 err = igb_vlvf_set(adapter, vid, add, vf); 5882 5883 if (err) 5884 goto out; 5885 5886 /* Go through all the checks to see if the VLAN filter should 5887 * be wiped completely. 5888 */ 5889 if (!add && (adapter->netdev->flags & IFF_PROMISC)) { 5890 u32 vlvf, bits; 5891 5892 int regndx = igb_find_vlvf_entry(adapter, vid); 5893 if (regndx < 0) 5894 goto out; 5895 /* See if any other pools are set for this VLAN filter 5896 * entry other than the PF. 5897 */ 5898 vlvf = bits = rd32(E1000_VLVF(regndx)); 5899 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT + 5900 adapter->vfs_allocated_count); 5901 /* If the filter was removed then ensure PF pool bit 5902 * is cleared if the PF only added itself to the pool 5903 * because the PF is in promiscuous mode. 5904 */ 5905 if ((vlvf & VLAN_VID_MASK) == vid && 5906 !test_bit(vid, adapter->active_vlans) && 5907 !bits) 5908 igb_vlvf_set(adapter, vid, add, 5909 adapter->vfs_allocated_count); 5910 } 5911 5912out: 5913 return err; 5914} 5915 5916static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 5917{ 5918 /* clear flags - except flag that indicates PF has set the MAC */ 5919 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 5920 adapter->vf_data[vf].last_nack = jiffies; 5921 5922 /* reset offloads to defaults */ 5923 igb_set_vmolr(adapter, vf, true); 5924 5925 /* reset vlans for device */ 5926 igb_clear_vf_vfta(adapter, vf); 5927 if (adapter->vf_data[vf].pf_vlan) 5928 igb_ndo_set_vf_vlan(adapter->netdev, vf, 5929 adapter->vf_data[vf].pf_vlan, 5930 adapter->vf_data[vf].pf_qos); 5931 else 5932 igb_clear_vf_vfta(adapter, vf); 5933 5934 /* reset multicast table array for vf */ 5935 adapter->vf_data[vf].num_vf_mc_hashes = 0; 5936 5937 /* Flush and reset the mta with the new values */ 5938 igb_set_rx_mode(adapter->netdev); 5939} 5940 5941static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 5942{ 5943 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5944 5945 /* clear mac address as we were hotplug removed/added */ 5946 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 5947 eth_zero_addr(vf_mac); 5948 5949 /* process remaining reset events */ 5950 igb_vf_reset(adapter, vf); 5951} 5952 5953static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 5954{ 5955 struct e1000_hw *hw = &adapter->hw; 5956 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5957 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 5958 u32 reg, msgbuf[3]; 5959 u8 *addr = (u8 *)(&msgbuf[1]); 5960 5961 /* process all the same items cleared in a function level reset */ 5962 igb_vf_reset(adapter, vf); 5963 5964 /* set vf mac address */ 5965 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 5966 5967 /* enable transmit and receive for vf */ 5968 reg = rd32(E1000_VFTE); 5969 wr32(E1000_VFTE, reg | (1 << vf)); 5970 reg = rd32(E1000_VFRE); 5971 wr32(E1000_VFRE, reg | (1 << vf)); 5972 5973 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 5974 5975 /* reply to reset with ack and vf mac address */ 5976 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 5977 memcpy(addr, vf_mac, ETH_ALEN); 5978 igb_write_mbx(hw, msgbuf, 3, vf); 5979} 5980 5981static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 5982{ 5983 /* The VF MAC Address is stored in a packed array of bytes 5984 * starting at the second 32 bit word of the msg array 5985 */ 5986 unsigned char *addr = (char *)&msg[1]; 5987 int err = -1; 5988 5989 if (is_valid_ether_addr(addr)) 5990 err = igb_set_vf_mac(adapter, vf, addr); 5991 5992 return err; 5993} 5994 5995static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 5996{ 5997 struct e1000_hw *hw = &adapter->hw; 5998 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5999 u32 msg = E1000_VT_MSGTYPE_NACK; 6000 6001 /* if device isn't clear to send it shouldn't be reading either */ 6002 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6003 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6004 igb_write_mbx(hw, &msg, 1, vf); 6005 vf_data->last_nack = jiffies; 6006 } 6007} 6008 6009static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6010{ 6011 struct pci_dev *pdev = adapter->pdev; 6012 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6013 struct e1000_hw *hw = &adapter->hw; 6014 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6015 s32 retval; 6016 6017 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6018 6019 if (retval) { 6020 /* if receive failed revoke VF CTS stats and restart init */ 6021 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6022 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6023 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6024 return; 6025 goto out; 6026 } 6027 6028 /* this is a message we already processed, do nothing */ 6029 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6030 return; 6031 6032 /* until the vf completes a reset it should not be 6033 * allowed to start any configuration. 6034 */ 6035 if (msgbuf[0] == E1000_VF_RESET) { 6036 igb_vf_reset_msg(adapter, vf); 6037 return; 6038 } 6039 6040 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6041 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6042 return; 6043 retval = -1; 6044 goto out; 6045 } 6046 6047 switch ((msgbuf[0] & 0xFFFF)) { 6048 case E1000_VF_SET_MAC_ADDR: 6049 retval = -EINVAL; 6050 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 6051 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6052 else 6053 dev_warn(&pdev->dev, 6054 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6055 vf); 6056 break; 6057 case E1000_VF_SET_PROMISC: 6058 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6059 break; 6060 case E1000_VF_SET_MULTICAST: 6061 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6062 break; 6063 case E1000_VF_SET_LPE: 6064 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6065 break; 6066 case E1000_VF_SET_VLAN: 6067 retval = -1; 6068 if (vf_data->pf_vlan) 6069 dev_warn(&pdev->dev, 6070 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6071 vf); 6072 else 6073 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 6074 break; 6075 default: 6076 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6077 retval = -1; 6078 break; 6079 } 6080 6081 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6082out: 6083 /* notify the VF of the results of what it sent us */ 6084 if (retval) 6085 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6086 else 6087 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6088 6089 igb_write_mbx(hw, msgbuf, 1, vf); 6090} 6091 6092static void igb_msg_task(struct igb_adapter *adapter) 6093{ 6094 struct e1000_hw *hw = &adapter->hw; 6095 u32 vf; 6096 6097 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6098 /* process any reset requests */ 6099 if (!igb_check_for_rst(hw, vf)) 6100 igb_vf_reset_event(adapter, vf); 6101 6102 /* process any messages pending */ 6103 if (!igb_check_for_msg(hw, vf)) 6104 igb_rcv_msg_from_vf(adapter, vf); 6105 6106 /* process any acks */ 6107 if (!igb_check_for_ack(hw, vf)) 6108 igb_rcv_ack_from_vf(adapter, vf); 6109 } 6110} 6111 6112/** 6113 * igb_set_uta - Set unicast filter table address 6114 * @adapter: board private structure 6115 * 6116 * The unicast table address is a register array of 32-bit registers. 6117 * The table is meant to be used in a way similar to how the MTA is used 6118 * however due to certain limitations in the hardware it is necessary to 6119 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6120 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6121 **/ 6122static void igb_set_uta(struct igb_adapter *adapter) 6123{ 6124 struct e1000_hw *hw = &adapter->hw; 6125 int i; 6126 6127 /* The UTA table only exists on 82576 hardware and newer */ 6128 if (hw->mac.type < e1000_82576) 6129 return; 6130 6131 /* we only need to do this if VMDq is enabled */ 6132 if (!adapter->vfs_allocated_count) 6133 return; 6134 6135 for (i = 0; i < hw->mac.uta_reg_count; i++) 6136 array_wr32(E1000_UTA, i, ~0); 6137} 6138 6139/** 6140 * igb_intr_msi - Interrupt Handler 6141 * @irq: interrupt number 6142 * @data: pointer to a network interface device structure 6143 **/ 6144static irqreturn_t igb_intr_msi(int irq, void *data) 6145{ 6146 struct igb_adapter *adapter = data; 6147 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6148 struct e1000_hw *hw = &adapter->hw; 6149 /* read ICR disables interrupts using IAM */ 6150 u32 icr = rd32(E1000_ICR); 6151 6152 igb_write_itr(q_vector); 6153 6154 if (icr & E1000_ICR_DRSTA) 6155 schedule_work(&adapter->reset_task); 6156 6157 if (icr & E1000_ICR_DOUTSYNC) { 6158 /* HW is reporting DMA is out of sync */ 6159 adapter->stats.doosync++; 6160 } 6161 6162 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6163 hw->mac.get_link_status = 1; 6164 if (!test_bit(__IGB_DOWN, &adapter->state)) 6165 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6166 } 6167 6168 if (icr & E1000_ICR_TS) { 6169 u32 tsicr = rd32(E1000_TSICR); 6170 6171 if (tsicr & E1000_TSICR_TXTS) { 6172 /* acknowledge the interrupt */ 6173 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6174 /* retrieve hardware timestamp */ 6175 schedule_work(&adapter->ptp_tx_work); 6176 } 6177 } 6178 6179 napi_schedule(&q_vector->napi); 6180 6181 return IRQ_HANDLED; 6182} 6183 6184/** 6185 * igb_intr - Legacy Interrupt Handler 6186 * @irq: interrupt number 6187 * @data: pointer to a network interface device structure 6188 **/ 6189static irqreturn_t igb_intr(int irq, void *data) 6190{ 6191 struct igb_adapter *adapter = data; 6192 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6193 struct e1000_hw *hw = &adapter->hw; 6194 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6195 * need for the IMC write 6196 */ 6197 u32 icr = rd32(E1000_ICR); 6198 6199 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6200 * not set, then the adapter didn't send an interrupt 6201 */ 6202 if (!(icr & E1000_ICR_INT_ASSERTED)) 6203 return IRQ_NONE; 6204 6205 igb_write_itr(q_vector); 6206 6207 if (icr & E1000_ICR_DRSTA) 6208 schedule_work(&adapter->reset_task); 6209 6210 if (icr & E1000_ICR_DOUTSYNC) { 6211 /* HW is reporting DMA is out of sync */ 6212 adapter->stats.doosync++; 6213 } 6214 6215 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6216 hw->mac.get_link_status = 1; 6217 /* guard against interrupt when we're going down */ 6218 if (!test_bit(__IGB_DOWN, &adapter->state)) 6219 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6220 } 6221 6222 if (icr & E1000_ICR_TS) { 6223 u32 tsicr = rd32(E1000_TSICR); 6224 6225 if (tsicr & E1000_TSICR_TXTS) { 6226 /* acknowledge the interrupt */ 6227 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6228 /* retrieve hardware timestamp */ 6229 schedule_work(&adapter->ptp_tx_work); 6230 } 6231 } 6232 6233 napi_schedule(&q_vector->napi); 6234 6235 return IRQ_HANDLED; 6236} 6237 6238static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6239{ 6240 struct igb_adapter *adapter = q_vector->adapter; 6241 struct e1000_hw *hw = &adapter->hw; 6242 6243 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6244 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6245 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6246 igb_set_itr(q_vector); 6247 else 6248 igb_update_ring_itr(q_vector); 6249 } 6250 6251 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6252 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6253 wr32(E1000_EIMS, q_vector->eims_value); 6254 else 6255 igb_irq_enable(adapter); 6256 } 6257} 6258 6259/** 6260 * igb_poll - NAPI Rx polling callback 6261 * @napi: napi polling structure 6262 * @budget: count of how many packets we should handle 6263 **/ 6264static int igb_poll(struct napi_struct *napi, int budget) 6265{ 6266 struct igb_q_vector *q_vector = container_of(napi, 6267 struct igb_q_vector, 6268 napi); 6269 bool clean_complete = true; 6270 6271#ifdef CONFIG_IGB_DCA 6272 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6273 igb_update_dca(q_vector); 6274#endif 6275 if (q_vector->tx.ring) 6276 clean_complete = igb_clean_tx_irq(q_vector); 6277 6278 if (q_vector->rx.ring) 6279 clean_complete &= igb_clean_rx_irq(q_vector, budget); 6280 6281 /* If all work not completed, return budget and keep polling */ 6282 if (!clean_complete) 6283 return budget; 6284 6285 /* If not enough Rx work done, exit the polling mode */ 6286 napi_complete(napi); 6287 igb_ring_irq_enable(q_vector); 6288 6289 return 0; 6290} 6291 6292/** 6293 * igb_clean_tx_irq - Reclaim resources after transmit completes 6294 * @q_vector: pointer to q_vector containing needed info 6295 * 6296 * returns true if ring is completely cleaned 6297 **/ 6298static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 6299{ 6300 struct igb_adapter *adapter = q_vector->adapter; 6301 struct igb_ring *tx_ring = q_vector->tx.ring; 6302 struct igb_tx_buffer *tx_buffer; 6303 union e1000_adv_tx_desc *tx_desc; 6304 unsigned int total_bytes = 0, total_packets = 0; 6305 unsigned int budget = q_vector->tx.work_limit; 6306 unsigned int i = tx_ring->next_to_clean; 6307 6308 if (test_bit(__IGB_DOWN, &adapter->state)) 6309 return true; 6310 6311 tx_buffer = &tx_ring->tx_buffer_info[i]; 6312 tx_desc = IGB_TX_DESC(tx_ring, i); 6313 i -= tx_ring->count; 6314 6315 do { 6316 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6317 6318 /* if next_to_watch is not set then there is no work pending */ 6319 if (!eop_desc) 6320 break; 6321 6322 /* prevent any other reads prior to eop_desc */ 6323 read_barrier_depends(); 6324 6325 /* if DD is not set pending work has not been completed */ 6326 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6327 break; 6328 6329 /* clear next_to_watch to prevent false hangs */ 6330 tx_buffer->next_to_watch = NULL; 6331 6332 /* update the statistics for this packet */ 6333 total_bytes += tx_buffer->bytecount; 6334 total_packets += tx_buffer->gso_segs; 6335 6336 /* free the skb */ 6337 dev_kfree_skb_any(tx_buffer->skb); 6338 6339 /* unmap skb header data */ 6340 dma_unmap_single(tx_ring->dev, 6341 dma_unmap_addr(tx_buffer, dma), 6342 dma_unmap_len(tx_buffer, len), 6343 DMA_TO_DEVICE); 6344 6345 /* clear tx_buffer data */ 6346 tx_buffer->skb = NULL; 6347 dma_unmap_len_set(tx_buffer, len, 0); 6348 6349 /* clear last DMA location and unmap remaining buffers */ 6350 while (tx_desc != eop_desc) { 6351 tx_buffer++; 6352 tx_desc++; 6353 i++; 6354 if (unlikely(!i)) { 6355 i -= tx_ring->count; 6356 tx_buffer = tx_ring->tx_buffer_info; 6357 tx_desc = IGB_TX_DESC(tx_ring, 0); 6358 } 6359 6360 /* unmap any remaining paged data */ 6361 if (dma_unmap_len(tx_buffer, len)) { 6362 dma_unmap_page(tx_ring->dev, 6363 dma_unmap_addr(tx_buffer, dma), 6364 dma_unmap_len(tx_buffer, len), 6365 DMA_TO_DEVICE); 6366 dma_unmap_len_set(tx_buffer, len, 0); 6367 } 6368 } 6369 6370 /* move us one more past the eop_desc for start of next pkt */ 6371 tx_buffer++; 6372 tx_desc++; 6373 i++; 6374 if (unlikely(!i)) { 6375 i -= tx_ring->count; 6376 tx_buffer = tx_ring->tx_buffer_info; 6377 tx_desc = IGB_TX_DESC(tx_ring, 0); 6378 } 6379 6380 /* issue prefetch for next Tx descriptor */ 6381 prefetch(tx_desc); 6382 6383 /* update budget accounting */ 6384 budget--; 6385 } while (likely(budget)); 6386 6387 netdev_tx_completed_queue(txring_txq(tx_ring), 6388 total_packets, total_bytes); 6389 i += tx_ring->count; 6390 tx_ring->next_to_clean = i; 6391 u64_stats_update_begin(&tx_ring->tx_syncp); 6392 tx_ring->tx_stats.bytes += total_bytes; 6393 tx_ring->tx_stats.packets += total_packets; 6394 u64_stats_update_end(&tx_ring->tx_syncp); 6395 q_vector->tx.total_bytes += total_bytes; 6396 q_vector->tx.total_packets += total_packets; 6397 6398 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6399 struct e1000_hw *hw = &adapter->hw; 6400 6401 /* Detect a transmit hang in hardware, this serializes the 6402 * check with the clearing of time_stamp and movement of i 6403 */ 6404 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6405 if (tx_buffer->next_to_watch && 6406 time_after(jiffies, tx_buffer->time_stamp + 6407 (adapter->tx_timeout_factor * HZ)) && 6408 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6409 6410 /* detected Tx unit hang */ 6411 dev_err(tx_ring->dev, 6412 "Detected Tx Unit Hang\n" 6413 " Tx Queue <%d>\n" 6414 " TDH <%x>\n" 6415 " TDT <%x>\n" 6416 " next_to_use <%x>\n" 6417 " next_to_clean <%x>\n" 6418 "buffer_info[next_to_clean]\n" 6419 " time_stamp <%lx>\n" 6420 " next_to_watch <%p>\n" 6421 " jiffies <%lx>\n" 6422 " desc.status <%x>\n", 6423 tx_ring->queue_index, 6424 rd32(E1000_TDH(tx_ring->reg_idx)), 6425 readl(tx_ring->tail), 6426 tx_ring->next_to_use, 6427 tx_ring->next_to_clean, 6428 tx_buffer->time_stamp, 6429 tx_buffer->next_to_watch, 6430 jiffies, 6431 tx_buffer->next_to_watch->wb.status); 6432 netif_stop_subqueue(tx_ring->netdev, 6433 tx_ring->queue_index); 6434 6435 /* we are about to reset, no point in enabling stuff */ 6436 return true; 6437 } 6438 } 6439 6440#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6441 if (unlikely(total_packets && 6442 netif_carrier_ok(tx_ring->netdev) && 6443 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6444 /* Make sure that anybody stopping the queue after this 6445 * sees the new next_to_clean. 6446 */ 6447 smp_mb(); 6448 if (__netif_subqueue_stopped(tx_ring->netdev, 6449 tx_ring->queue_index) && 6450 !(test_bit(__IGB_DOWN, &adapter->state))) { 6451 netif_wake_subqueue(tx_ring->netdev, 6452 tx_ring->queue_index); 6453 6454 u64_stats_update_begin(&tx_ring->tx_syncp); 6455 tx_ring->tx_stats.restart_queue++; 6456 u64_stats_update_end(&tx_ring->tx_syncp); 6457 } 6458 } 6459 6460 return !!budget; 6461} 6462 6463/** 6464 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6465 * @rx_ring: rx descriptor ring to store buffers on 6466 * @old_buff: donor buffer to have page reused 6467 * 6468 * Synchronizes page for reuse by the adapter 6469 **/ 6470static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6471 struct igb_rx_buffer *old_buff) 6472{ 6473 struct igb_rx_buffer *new_buff; 6474 u16 nta = rx_ring->next_to_alloc; 6475 6476 new_buff = &rx_ring->rx_buffer_info[nta]; 6477 6478 /* update, and store next to alloc */ 6479 nta++; 6480 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6481 6482 /* transfer page from old buffer to new buffer */ 6483 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); 6484 6485 /* sync the buffer for use by the device */ 6486 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 6487 old_buff->page_offset, 6488 IGB_RX_BUFSZ, 6489 DMA_FROM_DEVICE); 6490} 6491 6492static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 6493 struct page *page, 6494 unsigned int truesize) 6495{ 6496 /* avoid re-using remote pages */ 6497 if (unlikely(page_to_nid(page) != numa_node_id())) 6498 return false; 6499 6500#if (PAGE_SIZE < 8192) 6501 /* if we are only owner of page we can reuse it */ 6502 if (unlikely(page_count(page) != 1)) 6503 return false; 6504 6505 /* flip page offset to other buffer */ 6506 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 6507 6508 /* since we are the only owner of the page and we need to 6509 * increment it, just set the value to 2 in order to avoid 6510 * an unnecessary locked operation 6511 */ 6512 atomic_set(&page->_count, 2); 6513#else 6514 /* move offset up to the next cache line */ 6515 rx_buffer->page_offset += truesize; 6516 6517 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 6518 return false; 6519 6520 /* bump ref count on page before it is given to the stack */ 6521 get_page(page); 6522#endif 6523 6524 return true; 6525} 6526 6527/** 6528 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6529 * @rx_ring: rx descriptor ring to transact packets on 6530 * @rx_buffer: buffer containing page to add 6531 * @rx_desc: descriptor containing length of buffer written by hardware 6532 * @skb: sk_buff to place the data into 6533 * 6534 * This function will add the data contained in rx_buffer->page to the skb. 6535 * This is done either through a direct copy if the data in the buffer is 6536 * less than the skb header size, otherwise it will just attach the page as 6537 * a frag to the skb. 6538 * 6539 * The function will then update the page offset if necessary and return 6540 * true if the buffer can be reused by the adapter. 6541 **/ 6542static bool igb_add_rx_frag(struct igb_ring *rx_ring, 6543 struct igb_rx_buffer *rx_buffer, 6544 union e1000_adv_rx_desc *rx_desc, 6545 struct sk_buff *skb) 6546{ 6547 struct page *page = rx_buffer->page; 6548 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 6549#if (PAGE_SIZE < 8192) 6550 unsigned int truesize = IGB_RX_BUFSZ; 6551#else 6552 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 6553#endif 6554 6555 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { 6556 unsigned char *va = page_address(page) + rx_buffer->page_offset; 6557 6558 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6559 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6560 va += IGB_TS_HDR_LEN; 6561 size -= IGB_TS_HDR_LEN; 6562 } 6563 6564 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 6565 6566 /* we can reuse buffer as-is, just make sure it is local */ 6567 if (likely(page_to_nid(page) == numa_node_id())) 6568 return true; 6569 6570 /* this page cannot be reused so discard it */ 6571 put_page(page); 6572 return false; 6573 } 6574 6575 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 6576 rx_buffer->page_offset, size, truesize); 6577 6578 return igb_can_reuse_rx_page(rx_buffer, page, truesize); 6579} 6580 6581static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 6582 union e1000_adv_rx_desc *rx_desc, 6583 struct sk_buff *skb) 6584{ 6585 struct igb_rx_buffer *rx_buffer; 6586 struct page *page; 6587 6588 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 6589 6590 page = rx_buffer->page; 6591 prefetchw(page); 6592 6593 if (likely(!skb)) { 6594 void *page_addr = page_address(page) + 6595 rx_buffer->page_offset; 6596 6597 /* prefetch first cache line of first page */ 6598 prefetch(page_addr); 6599#if L1_CACHE_BYTES < 128 6600 prefetch(page_addr + L1_CACHE_BYTES); 6601#endif 6602 6603 /* allocate a skb to store the frags */ 6604 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 6605 IGB_RX_HDR_LEN); 6606 if (unlikely(!skb)) { 6607 rx_ring->rx_stats.alloc_failed++; 6608 return NULL; 6609 } 6610 6611 /* we will be copying header into skb->data in 6612 * pskb_may_pull so it is in our interest to prefetch 6613 * it now to avoid a possible cache miss 6614 */ 6615 prefetchw(skb->data); 6616 } 6617 6618 /* we are reusing so sync this buffer for CPU use */ 6619 dma_sync_single_range_for_cpu(rx_ring->dev, 6620 rx_buffer->dma, 6621 rx_buffer->page_offset, 6622 IGB_RX_BUFSZ, 6623 DMA_FROM_DEVICE); 6624 6625 /* pull page into skb */ 6626 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 6627 /* hand second half of page back to the ring */ 6628 igb_reuse_rx_page(rx_ring, rx_buffer); 6629 } else { 6630 /* we are not reusing the buffer so unmap it */ 6631 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6632 PAGE_SIZE, DMA_FROM_DEVICE); 6633 } 6634 6635 /* clear contents of rx_buffer */ 6636 rx_buffer->page = NULL; 6637 6638 return skb; 6639} 6640 6641static inline void igb_rx_checksum(struct igb_ring *ring, 6642 union e1000_adv_rx_desc *rx_desc, 6643 struct sk_buff *skb) 6644{ 6645 skb_checksum_none_assert(skb); 6646 6647 /* Ignore Checksum bit is set */ 6648 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6649 return; 6650 6651 /* Rx checksum disabled via ethtool */ 6652 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6653 return; 6654 6655 /* TCP/UDP checksum error bit is set */ 6656 if (igb_test_staterr(rx_desc, 6657 E1000_RXDEXT_STATERR_TCPE | 6658 E1000_RXDEXT_STATERR_IPE)) { 6659 /* work around errata with sctp packets where the TCPE aka 6660 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6661 * packets, (aka let the stack check the crc32c) 6662 */ 6663 if (!((skb->len == 60) && 6664 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6665 u64_stats_update_begin(&ring->rx_syncp); 6666 ring->rx_stats.csum_err++; 6667 u64_stats_update_end(&ring->rx_syncp); 6668 } 6669 /* let the stack verify checksum errors */ 6670 return; 6671 } 6672 /* It must be a TCP or UDP packet with a valid checksum */ 6673 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 6674 E1000_RXD_STAT_UDPCS)) 6675 skb->ip_summed = CHECKSUM_UNNECESSARY; 6676 6677 dev_dbg(ring->dev, "cksum success: bits %08X\n", 6678 le32_to_cpu(rx_desc->wb.upper.status_error)); 6679} 6680 6681static inline void igb_rx_hash(struct igb_ring *ring, 6682 union e1000_adv_rx_desc *rx_desc, 6683 struct sk_buff *skb) 6684{ 6685 if (ring->netdev->features & NETIF_F_RXHASH) 6686 skb_set_hash(skb, 6687 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 6688 PKT_HASH_TYPE_L3); 6689} 6690 6691/** 6692 * igb_is_non_eop - process handling of non-EOP buffers 6693 * @rx_ring: Rx ring being processed 6694 * @rx_desc: Rx descriptor for current buffer 6695 * @skb: current socket buffer containing buffer in progress 6696 * 6697 * This function updates next to clean. If the buffer is an EOP buffer 6698 * this function exits returning false, otherwise it will place the 6699 * sk_buff in the next buffer to be chained and return true indicating 6700 * that this is in fact a non-EOP buffer. 6701 **/ 6702static bool igb_is_non_eop(struct igb_ring *rx_ring, 6703 union e1000_adv_rx_desc *rx_desc) 6704{ 6705 u32 ntc = rx_ring->next_to_clean + 1; 6706 6707 /* fetch, update, and store next to clean */ 6708 ntc = (ntc < rx_ring->count) ? ntc : 0; 6709 rx_ring->next_to_clean = ntc; 6710 6711 prefetch(IGB_RX_DESC(rx_ring, ntc)); 6712 6713 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 6714 return false; 6715 6716 return true; 6717} 6718 6719/** 6720 * igb_get_headlen - determine size of header for LRO/GRO 6721 * @data: pointer to the start of the headers 6722 * @max_len: total length of section to find headers in 6723 * 6724 * This function is meant to determine the length of headers that will 6725 * be recognized by hardware for LRO, and GRO offloads. The main 6726 * motivation of doing this is to only perform one pull for IPv4 TCP 6727 * packets so that we can do basic things like calculating the gso_size 6728 * based on the average data per packet. 6729 **/ 6730static unsigned int igb_get_headlen(unsigned char *data, 6731 unsigned int max_len) 6732{ 6733 union { 6734 unsigned char *network; 6735 /* l2 headers */ 6736 struct ethhdr *eth; 6737 struct vlan_hdr *vlan; 6738 /* l3 headers */ 6739 struct iphdr *ipv4; 6740 struct ipv6hdr *ipv6; 6741 } hdr; 6742 __be16 protocol; 6743 u8 nexthdr = 0; /* default to not TCP */ 6744 u8 hlen; 6745 6746 /* this should never happen, but better safe than sorry */ 6747 if (max_len < ETH_HLEN) 6748 return max_len; 6749 6750 /* initialize network frame pointer */ 6751 hdr.network = data; 6752 6753 /* set first protocol and move network header forward */ 6754 protocol = hdr.eth->h_proto; 6755 hdr.network += ETH_HLEN; 6756 6757 /* handle any vlan tag if present */ 6758 if (protocol == htons(ETH_P_8021Q)) { 6759 if ((hdr.network - data) > (max_len - VLAN_HLEN)) 6760 return max_len; 6761 6762 protocol = hdr.vlan->h_vlan_encapsulated_proto; 6763 hdr.network += VLAN_HLEN; 6764 } 6765 6766 /* handle L3 protocols */ 6767 if (protocol == htons(ETH_P_IP)) { 6768 if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) 6769 return max_len; 6770 6771 /* access ihl as a u8 to avoid unaligned access on ia64 */ 6772 hlen = (hdr.network[0] & 0x0F) << 2; 6773 6774 /* verify hlen meets minimum size requirements */ 6775 if (hlen < sizeof(struct iphdr)) 6776 return hdr.network - data; 6777 6778 /* record next protocol if header is present */ 6779 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET))) 6780 nexthdr = hdr.ipv4->protocol; 6781 } else if (protocol == htons(ETH_P_IPV6)) { 6782 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) 6783 return max_len; 6784 6785 /* record next protocol */ 6786 nexthdr = hdr.ipv6->nexthdr; 6787 hlen = sizeof(struct ipv6hdr); 6788 } else { 6789 return hdr.network - data; 6790 } 6791 6792 /* relocate pointer to start of L4 header */ 6793 hdr.network += hlen; 6794 6795 /* finally sort out TCP */ 6796 if (nexthdr == IPPROTO_TCP) { 6797 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) 6798 return max_len; 6799 6800 /* access doff as a u8 to avoid unaligned access on ia64 */ 6801 hlen = (hdr.network[12] & 0xF0) >> 2; 6802 6803 /* verify hlen meets minimum size requirements */ 6804 if (hlen < sizeof(struct tcphdr)) 6805 return hdr.network - data; 6806 6807 hdr.network += hlen; 6808 } else if (nexthdr == IPPROTO_UDP) { 6809 if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) 6810 return max_len; 6811 6812 hdr.network += sizeof(struct udphdr); 6813 } 6814 6815 /* If everything has gone correctly hdr.network should be the 6816 * data section of the packet and will be the end of the header. 6817 * If not then it probably represents the end of the last recognized 6818 * header. 6819 */ 6820 if ((hdr.network - data) < max_len) 6821 return hdr.network - data; 6822 else 6823 return max_len; 6824} 6825 6826/** 6827 * igb_pull_tail - igb specific version of skb_pull_tail 6828 * @rx_ring: rx descriptor ring packet is being transacted on 6829 * @rx_desc: pointer to the EOP Rx descriptor 6830 * @skb: pointer to current skb being adjusted 6831 * 6832 * This function is an igb specific version of __pskb_pull_tail. The 6833 * main difference between this version and the original function is that 6834 * this function can make several assumptions about the state of things 6835 * that allow for significant optimizations versus the standard function. 6836 * As a result we can do things like drop a frag and maintain an accurate 6837 * truesize for the skb. 6838 */ 6839static void igb_pull_tail(struct igb_ring *rx_ring, 6840 union e1000_adv_rx_desc *rx_desc, 6841 struct sk_buff *skb) 6842{ 6843 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6844 unsigned char *va; 6845 unsigned int pull_len; 6846 6847 /* it is valid to use page_address instead of kmap since we are 6848 * working with pages allocated out of the lomem pool per 6849 * alloc_page(GFP_ATOMIC) 6850 */ 6851 va = skb_frag_address(frag); 6852 6853 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6854 /* retrieve timestamp from buffer */ 6855 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6856 6857 /* update pointers to remove timestamp header */ 6858 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); 6859 frag->page_offset += IGB_TS_HDR_LEN; 6860 skb->data_len -= IGB_TS_HDR_LEN; 6861 skb->len -= IGB_TS_HDR_LEN; 6862 6863 /* move va to start of packet data */ 6864 va += IGB_TS_HDR_LEN; 6865 } 6866 6867 /* we need the header to contain the greater of either ETH_HLEN or 6868 * 60 bytes if the skb->len is less than 60 for skb_pad. 6869 */ 6870 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); 6871 6872 /* align pull length to size of long to optimize memcpy performance */ 6873 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 6874 6875 /* update all of the pointers */ 6876 skb_frag_size_sub(frag, pull_len); 6877 frag->page_offset += pull_len; 6878 skb->data_len -= pull_len; 6879 skb->tail += pull_len; 6880} 6881 6882/** 6883 * igb_cleanup_headers - Correct corrupted or empty headers 6884 * @rx_ring: rx descriptor ring packet is being transacted on 6885 * @rx_desc: pointer to the EOP Rx descriptor 6886 * @skb: pointer to current skb being fixed 6887 * 6888 * Address the case where we are pulling data in on pages only 6889 * and as such no data is present in the skb header. 6890 * 6891 * In addition if skb is not at least 60 bytes we need to pad it so that 6892 * it is large enough to qualify as a valid Ethernet frame. 6893 * 6894 * Returns true if an error was encountered and skb was freed. 6895 **/ 6896static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6897 union e1000_adv_rx_desc *rx_desc, 6898 struct sk_buff *skb) 6899{ 6900 if (unlikely((igb_test_staterr(rx_desc, 6901 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6902 struct net_device *netdev = rx_ring->netdev; 6903 if (!(netdev->features & NETIF_F_RXALL)) { 6904 dev_kfree_skb_any(skb); 6905 return true; 6906 } 6907 } 6908 6909 /* place header in linear portion of buffer */ 6910 if (skb_is_nonlinear(skb)) 6911 igb_pull_tail(rx_ring, rx_desc, skb); 6912 6913 /* if skb_pad returns an error the skb was freed */ 6914 if (unlikely(skb->len < 60)) { 6915 int pad_len = 60 - skb->len; 6916 6917 if (skb_pad(skb, pad_len)) 6918 return true; 6919 __skb_put(skb, pad_len); 6920 } 6921 6922 return false; 6923} 6924 6925/** 6926 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6927 * @rx_ring: rx descriptor ring packet is being transacted on 6928 * @rx_desc: pointer to the EOP Rx descriptor 6929 * @skb: pointer to current skb being populated 6930 * 6931 * This function checks the ring, descriptor, and packet information in 6932 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6933 * other fields within the skb. 6934 **/ 6935static void igb_process_skb_fields(struct igb_ring *rx_ring, 6936 union e1000_adv_rx_desc *rx_desc, 6937 struct sk_buff *skb) 6938{ 6939 struct net_device *dev = rx_ring->netdev; 6940 6941 igb_rx_hash(rx_ring, rx_desc, skb); 6942 6943 igb_rx_checksum(rx_ring, rx_desc, skb); 6944 6945 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 6946 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 6947 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 6948 6949 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 6950 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6951 u16 vid; 6952 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6953 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6954 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6955 else 6956 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6957 6958 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 6959 } 6960 6961 skb_record_rx_queue(skb, rx_ring->queue_index); 6962 6963 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6964} 6965 6966static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 6967{ 6968 struct igb_ring *rx_ring = q_vector->rx.ring; 6969 struct sk_buff *skb = rx_ring->skb; 6970 unsigned int total_bytes = 0, total_packets = 0; 6971 u16 cleaned_count = igb_desc_unused(rx_ring); 6972 6973 while (likely(total_packets < budget)) { 6974 union e1000_adv_rx_desc *rx_desc; 6975 6976 /* return some buffers to hardware, one at a time is too slow */ 6977 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6978 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6979 cleaned_count = 0; 6980 } 6981 6982 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 6983 6984 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) 6985 break; 6986 6987 /* This memory barrier is needed to keep us from reading 6988 * any other fields out of the rx_desc until we know the 6989 * RXD_STAT_DD bit is set 6990 */ 6991 rmb(); 6992 6993 /* retrieve a buffer from the ring */ 6994 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 6995 6996 /* exit if we failed to retrieve a buffer */ 6997 if (!skb) 6998 break; 6999 7000 cleaned_count++; 7001 7002 /* fetch next buffer in frame if non-eop */ 7003 if (igb_is_non_eop(rx_ring, rx_desc)) 7004 continue; 7005 7006 /* verify the packet layout is correct */ 7007 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 7008 skb = NULL; 7009 continue; 7010 } 7011 7012 /* probably a little skewed due to removing CRC */ 7013 total_bytes += skb->len; 7014 7015 /* populate checksum, timestamp, VLAN, and protocol */ 7016 igb_process_skb_fields(rx_ring, rx_desc, skb); 7017 7018 napi_gro_receive(&q_vector->napi, skb); 7019 7020 /* reset skb pointer */ 7021 skb = NULL; 7022 7023 /* update budget accounting */ 7024 total_packets++; 7025 } 7026 7027 /* place incomplete frames back on ring for completion */ 7028 rx_ring->skb = skb; 7029 7030 u64_stats_update_begin(&rx_ring->rx_syncp); 7031 rx_ring->rx_stats.packets += total_packets; 7032 rx_ring->rx_stats.bytes += total_bytes; 7033 u64_stats_update_end(&rx_ring->rx_syncp); 7034 q_vector->rx.total_packets += total_packets; 7035 q_vector->rx.total_bytes += total_bytes; 7036 7037 if (cleaned_count) 7038 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7039 7040 return (total_packets < budget); 7041} 7042 7043static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7044 struct igb_rx_buffer *bi) 7045{ 7046 struct page *page = bi->page; 7047 dma_addr_t dma; 7048 7049 /* since we are recycling buffers we should seldom need to alloc */ 7050 if (likely(page)) 7051 return true; 7052 7053 /* alloc new page for storage */ 7054 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); 7055 if (unlikely(!page)) { 7056 rx_ring->rx_stats.alloc_failed++; 7057 return false; 7058 } 7059 7060 /* map page for use */ 7061 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 7062 7063 /* if mapping failed free memory back to system since 7064 * there isn't much point in holding memory we can't use 7065 */ 7066 if (dma_mapping_error(rx_ring->dev, dma)) { 7067 __free_page(page); 7068 7069 rx_ring->rx_stats.alloc_failed++; 7070 return false; 7071 } 7072 7073 bi->dma = dma; 7074 bi->page = page; 7075 bi->page_offset = 0; 7076 7077 return true; 7078} 7079 7080/** 7081 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7082 * @adapter: address of board private structure 7083 **/ 7084void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7085{ 7086 union e1000_adv_rx_desc *rx_desc; 7087 struct igb_rx_buffer *bi; 7088 u16 i = rx_ring->next_to_use; 7089 7090 /* nothing to do */ 7091 if (!cleaned_count) 7092 return; 7093 7094 rx_desc = IGB_RX_DESC(rx_ring, i); 7095 bi = &rx_ring->rx_buffer_info[i]; 7096 i -= rx_ring->count; 7097 7098 do { 7099 if (!igb_alloc_mapped_page(rx_ring, bi)) 7100 break; 7101 7102 /* Refresh the desc even if buffer_addrs didn't change 7103 * because each write-back erases this info. 7104 */ 7105 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7106 7107 rx_desc++; 7108 bi++; 7109 i++; 7110 if (unlikely(!i)) { 7111 rx_desc = IGB_RX_DESC(rx_ring, 0); 7112 bi = rx_ring->rx_buffer_info; 7113 i -= rx_ring->count; 7114 } 7115 7116 /* clear the hdr_addr for the next_to_use descriptor */ 7117 rx_desc->read.hdr_addr = 0; 7118 7119 cleaned_count--; 7120 } while (cleaned_count); 7121 7122 i += rx_ring->count; 7123 7124 if (rx_ring->next_to_use != i) { 7125 /* record the next descriptor to use */ 7126 rx_ring->next_to_use = i; 7127 7128 /* update next to alloc since we have filled the ring */ 7129 rx_ring->next_to_alloc = i; 7130 7131 /* Force memory writes to complete before letting h/w 7132 * know there are new descriptors to fetch. (Only 7133 * applicable for weak-ordered memory model archs, 7134 * such as IA-64). 7135 */ 7136 wmb(); 7137 writel(i, rx_ring->tail); 7138 } 7139} 7140 7141/** 7142 * igb_mii_ioctl - 7143 * @netdev: 7144 * @ifreq: 7145 * @cmd: 7146 **/ 7147static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7148{ 7149 struct igb_adapter *adapter = netdev_priv(netdev); 7150 struct mii_ioctl_data *data = if_mii(ifr); 7151 7152 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7153 return -EOPNOTSUPP; 7154 7155 switch (cmd) { 7156 case SIOCGMIIPHY: 7157 data->phy_id = adapter->hw.phy.addr; 7158 break; 7159 case SIOCGMIIREG: 7160 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7161 &data->val_out)) 7162 return -EIO; 7163 break; 7164 case SIOCSMIIREG: 7165 default: 7166 return -EOPNOTSUPP; 7167 } 7168 return 0; 7169} 7170 7171/** 7172 * igb_ioctl - 7173 * @netdev: 7174 * @ifreq: 7175 * @cmd: 7176 **/ 7177static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7178{ 7179 switch (cmd) { 7180 case SIOCGMIIPHY: 7181 case SIOCGMIIREG: 7182 case SIOCSMIIREG: 7183 return igb_mii_ioctl(netdev, ifr, cmd); 7184 case SIOCGHWTSTAMP: 7185 return igb_ptp_get_ts_config(netdev, ifr); 7186 case SIOCSHWTSTAMP: 7187 return igb_ptp_set_ts_config(netdev, ifr); 7188 default: 7189 return -EOPNOTSUPP; 7190 } 7191} 7192 7193s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7194{ 7195 struct igb_adapter *adapter = hw->back; 7196 7197 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7198 return -E1000_ERR_CONFIG; 7199 7200 return 0; 7201} 7202 7203s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7204{ 7205 struct igb_adapter *adapter = hw->back; 7206 7207 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7208 return -E1000_ERR_CONFIG; 7209 7210 return 0; 7211} 7212 7213static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7214{ 7215 struct igb_adapter *adapter = netdev_priv(netdev); 7216 struct e1000_hw *hw = &adapter->hw; 7217 u32 ctrl, rctl; 7218 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7219 7220 if (enable) { 7221 /* enable VLAN tag insert/strip */ 7222 ctrl = rd32(E1000_CTRL); 7223 ctrl |= E1000_CTRL_VME; 7224 wr32(E1000_CTRL, ctrl); 7225 7226 /* Disable CFI check */ 7227 rctl = rd32(E1000_RCTL); 7228 rctl &= ~E1000_RCTL_CFIEN; 7229 wr32(E1000_RCTL, rctl); 7230 } else { 7231 /* disable VLAN tag insert/strip */ 7232 ctrl = rd32(E1000_CTRL); 7233 ctrl &= ~E1000_CTRL_VME; 7234 wr32(E1000_CTRL, ctrl); 7235 } 7236 7237 igb_rlpml_set(adapter); 7238} 7239 7240static int igb_vlan_rx_add_vid(struct net_device *netdev, 7241 __be16 proto, u16 vid) 7242{ 7243 struct igb_adapter *adapter = netdev_priv(netdev); 7244 struct e1000_hw *hw = &adapter->hw; 7245 int pf_id = adapter->vfs_allocated_count; 7246 7247 /* attempt to add filter to vlvf array */ 7248 igb_vlvf_set(adapter, vid, true, pf_id); 7249 7250 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7251 igb_vfta_set(hw, vid, true); 7252 7253 set_bit(vid, adapter->active_vlans); 7254 7255 return 0; 7256} 7257 7258static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7259 __be16 proto, u16 vid) 7260{ 7261 struct igb_adapter *adapter = netdev_priv(netdev); 7262 struct e1000_hw *hw = &adapter->hw; 7263 int pf_id = adapter->vfs_allocated_count; 7264 s32 err; 7265 7266 /* remove vlan from VLVF table array */ 7267 err = igb_vlvf_set(adapter, vid, false, pf_id); 7268 7269 /* if vid was not present in VLVF just remove it from table */ 7270 if (err) 7271 igb_vfta_set(hw, vid, false); 7272 7273 clear_bit(vid, adapter->active_vlans); 7274 7275 return 0; 7276} 7277 7278static void igb_restore_vlan(struct igb_adapter *adapter) 7279{ 7280 u16 vid; 7281 7282 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7283 7284 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 7285 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7286} 7287 7288int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7289{ 7290 struct pci_dev *pdev = adapter->pdev; 7291 struct e1000_mac_info *mac = &adapter->hw.mac; 7292 7293 mac->autoneg = 0; 7294 7295 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7296 * for the switch() below to work 7297 */ 7298 if ((spd & 1) || (dplx & ~1)) 7299 goto err_inval; 7300 7301 /* Fiber NIC's only allow 1000 gbps Full duplex 7302 * and 100Mbps Full duplex for 100baseFx sfp 7303 */ 7304 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7305 switch (spd + dplx) { 7306 case SPEED_10 + DUPLEX_HALF: 7307 case SPEED_10 + DUPLEX_FULL: 7308 case SPEED_100 + DUPLEX_HALF: 7309 goto err_inval; 7310 default: 7311 break; 7312 } 7313 } 7314 7315 switch (spd + dplx) { 7316 case SPEED_10 + DUPLEX_HALF: 7317 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7318 break; 7319 case SPEED_10 + DUPLEX_FULL: 7320 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7321 break; 7322 case SPEED_100 + DUPLEX_HALF: 7323 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7324 break; 7325 case SPEED_100 + DUPLEX_FULL: 7326 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7327 break; 7328 case SPEED_1000 + DUPLEX_FULL: 7329 mac->autoneg = 1; 7330 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7331 break; 7332 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7333 default: 7334 goto err_inval; 7335 } 7336 7337 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7338 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7339 7340 return 0; 7341 7342err_inval: 7343 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7344 return -EINVAL; 7345} 7346 7347static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7348 bool runtime) 7349{ 7350 struct net_device *netdev = pci_get_drvdata(pdev); 7351 struct igb_adapter *adapter = netdev_priv(netdev); 7352 struct e1000_hw *hw = &adapter->hw; 7353 u32 ctrl, rctl, status; 7354 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7355#ifdef CONFIG_PM 7356 int retval = 0; 7357#endif 7358 7359 netif_device_detach(netdev); 7360 7361 if (netif_running(netdev)) 7362 __igb_close(netdev, true); 7363 7364 igb_clear_interrupt_scheme(adapter); 7365 7366#ifdef CONFIG_PM 7367 retval = pci_save_state(pdev); 7368 if (retval) 7369 return retval; 7370#endif 7371 7372 status = rd32(E1000_STATUS); 7373 if (status & E1000_STATUS_LU) 7374 wufc &= ~E1000_WUFC_LNKC; 7375 7376 if (wufc) { 7377 igb_setup_rctl(adapter); 7378 igb_set_rx_mode(netdev); 7379 7380 /* turn on all-multi mode if wake on multicast is enabled */ 7381 if (wufc & E1000_WUFC_MC) { 7382 rctl = rd32(E1000_RCTL); 7383 rctl |= E1000_RCTL_MPE; 7384 wr32(E1000_RCTL, rctl); 7385 } 7386 7387 ctrl = rd32(E1000_CTRL); 7388 /* advertise wake from D3Cold */ 7389 #define E1000_CTRL_ADVD3WUC 0x00100000 7390 /* phy power management enable */ 7391 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7392 ctrl |= E1000_CTRL_ADVD3WUC; 7393 wr32(E1000_CTRL, ctrl); 7394 7395 /* Allow time for pending master requests to run */ 7396 igb_disable_pcie_master(hw); 7397 7398 wr32(E1000_WUC, E1000_WUC_PME_EN); 7399 wr32(E1000_WUFC, wufc); 7400 } else { 7401 wr32(E1000_WUC, 0); 7402 wr32(E1000_WUFC, 0); 7403 } 7404 7405 *enable_wake = wufc || adapter->en_mng_pt; 7406 if (!*enable_wake) 7407 igb_power_down_link(adapter); 7408 else 7409 igb_power_up_link(adapter); 7410 7411 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7412 * would have already happened in close and is redundant. 7413 */ 7414 igb_release_hw_control(adapter); 7415 7416 pci_disable_device(pdev); 7417 7418 return 0; 7419} 7420 7421#ifdef CONFIG_PM 7422#ifdef CONFIG_PM_SLEEP 7423static int igb_suspend(struct device *dev) 7424{ 7425 int retval; 7426 bool wake; 7427 struct pci_dev *pdev = to_pci_dev(dev); 7428 7429 retval = __igb_shutdown(pdev, &wake, 0); 7430 if (retval) 7431 return retval; 7432 7433 if (wake) { 7434 pci_prepare_to_sleep(pdev); 7435 } else { 7436 pci_wake_from_d3(pdev, false); 7437 pci_set_power_state(pdev, PCI_D3hot); 7438 } 7439 7440 return 0; 7441} 7442#endif /* CONFIG_PM_SLEEP */ 7443 7444static int igb_resume(struct device *dev) 7445{ 7446 struct pci_dev *pdev = to_pci_dev(dev); 7447 struct net_device *netdev = pci_get_drvdata(pdev); 7448 struct igb_adapter *adapter = netdev_priv(netdev); 7449 struct e1000_hw *hw = &adapter->hw; 7450 u32 err; 7451 7452 pci_set_power_state(pdev, PCI_D0); 7453 pci_restore_state(pdev); 7454 pci_save_state(pdev); 7455 7456 err = pci_enable_device_mem(pdev); 7457 if (err) { 7458 dev_err(&pdev->dev, 7459 "igb: Cannot enable PCI device from suspend\n"); 7460 return err; 7461 } 7462 pci_set_master(pdev); 7463 7464 pci_enable_wake(pdev, PCI_D3hot, 0); 7465 pci_enable_wake(pdev, PCI_D3cold, 0); 7466 7467 if (igb_init_interrupt_scheme(adapter, true)) { 7468 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7469 return -ENOMEM; 7470 } 7471 7472 igb_reset(adapter); 7473 7474 /* let the f/w know that the h/w is now under the control of the 7475 * driver. 7476 */ 7477 igb_get_hw_control(adapter); 7478 7479 wr32(E1000_WUS, ~0); 7480 7481 if (netdev->flags & IFF_UP) { 7482 rtnl_lock(); 7483 err = __igb_open(netdev, true); 7484 rtnl_unlock(); 7485 if (err) 7486 return err; 7487 } 7488 7489 netif_device_attach(netdev); 7490 return 0; 7491} 7492 7493#ifdef CONFIG_PM_RUNTIME 7494static int igb_runtime_idle(struct device *dev) 7495{ 7496 struct pci_dev *pdev = to_pci_dev(dev); 7497 struct net_device *netdev = pci_get_drvdata(pdev); 7498 struct igb_adapter *adapter = netdev_priv(netdev); 7499 7500 if (!igb_has_link(adapter)) 7501 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7502 7503 return -EBUSY; 7504} 7505 7506static int igb_runtime_suspend(struct device *dev) 7507{ 7508 struct pci_dev *pdev = to_pci_dev(dev); 7509 int retval; 7510 bool wake; 7511 7512 retval = __igb_shutdown(pdev, &wake, 1); 7513 if (retval) 7514 return retval; 7515 7516 if (wake) { 7517 pci_prepare_to_sleep(pdev); 7518 } else { 7519 pci_wake_from_d3(pdev, false); 7520 pci_set_power_state(pdev, PCI_D3hot); 7521 } 7522 7523 return 0; 7524} 7525 7526static int igb_runtime_resume(struct device *dev) 7527{ 7528 return igb_resume(dev); 7529} 7530#endif /* CONFIG_PM_RUNTIME */ 7531#endif 7532 7533static void igb_shutdown(struct pci_dev *pdev) 7534{ 7535 bool wake; 7536 7537 __igb_shutdown(pdev, &wake, 0); 7538 7539 if (system_state == SYSTEM_POWER_OFF) { 7540 pci_wake_from_d3(pdev, wake); 7541 pci_set_power_state(pdev, PCI_D3hot); 7542 } 7543} 7544 7545#ifdef CONFIG_PCI_IOV 7546static int igb_sriov_reinit(struct pci_dev *dev) 7547{ 7548 struct net_device *netdev = pci_get_drvdata(dev); 7549 struct igb_adapter *adapter = netdev_priv(netdev); 7550 struct pci_dev *pdev = adapter->pdev; 7551 7552 rtnl_lock(); 7553 7554 if (netif_running(netdev)) 7555 igb_close(netdev); 7556 7557 igb_clear_interrupt_scheme(adapter); 7558 7559 igb_init_queue_configuration(adapter); 7560 7561 if (igb_init_interrupt_scheme(adapter, true)) { 7562 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7563 return -ENOMEM; 7564 } 7565 7566 if (netif_running(netdev)) 7567 igb_open(netdev); 7568 7569 rtnl_unlock(); 7570 7571 return 0; 7572} 7573 7574static int igb_pci_disable_sriov(struct pci_dev *dev) 7575{ 7576 int err = igb_disable_sriov(dev); 7577 7578 if (!err) 7579 err = igb_sriov_reinit(dev); 7580 7581 return err; 7582} 7583 7584static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7585{ 7586 int err = igb_enable_sriov(dev, num_vfs); 7587 7588 if (err) 7589 goto out; 7590 7591 err = igb_sriov_reinit(dev); 7592 if (!err) 7593 return num_vfs; 7594 7595out: 7596 return err; 7597} 7598 7599#endif 7600static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7601{ 7602#ifdef CONFIG_PCI_IOV 7603 if (num_vfs == 0) 7604 return igb_pci_disable_sriov(dev); 7605 else 7606 return igb_pci_enable_sriov(dev, num_vfs); 7607#endif 7608 return 0; 7609} 7610 7611#ifdef CONFIG_NET_POLL_CONTROLLER 7612/* Polling 'interrupt' - used by things like netconsole to send skbs 7613 * without having to re-enable interrupts. It's not called while 7614 * the interrupt routine is executing. 7615 */ 7616static void igb_netpoll(struct net_device *netdev) 7617{ 7618 struct igb_adapter *adapter = netdev_priv(netdev); 7619 struct e1000_hw *hw = &adapter->hw; 7620 struct igb_q_vector *q_vector; 7621 int i; 7622 7623 for (i = 0; i < adapter->num_q_vectors; i++) { 7624 q_vector = adapter->q_vector[i]; 7625 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7626 wr32(E1000_EIMC, q_vector->eims_value); 7627 else 7628 igb_irq_disable(adapter); 7629 napi_schedule(&q_vector->napi); 7630 } 7631} 7632#endif /* CONFIG_NET_POLL_CONTROLLER */ 7633 7634/** 7635 * igb_io_error_detected - called when PCI error is detected 7636 * @pdev: Pointer to PCI device 7637 * @state: The current pci connection state 7638 * 7639 * This function is called after a PCI bus error affecting 7640 * this device has been detected. 7641 **/ 7642static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7643 pci_channel_state_t state) 7644{ 7645 struct net_device *netdev = pci_get_drvdata(pdev); 7646 struct igb_adapter *adapter = netdev_priv(netdev); 7647 7648 netif_device_detach(netdev); 7649 7650 if (state == pci_channel_io_perm_failure) 7651 return PCI_ERS_RESULT_DISCONNECT; 7652 7653 if (netif_running(netdev)) 7654 igb_down(adapter); 7655 pci_disable_device(pdev); 7656 7657 /* Request a slot slot reset. */ 7658 return PCI_ERS_RESULT_NEED_RESET; 7659} 7660 7661/** 7662 * igb_io_slot_reset - called after the pci bus has been reset. 7663 * @pdev: Pointer to PCI device 7664 * 7665 * Restart the card from scratch, as if from a cold-boot. Implementation 7666 * resembles the first-half of the igb_resume routine. 7667 **/ 7668static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 7669{ 7670 struct net_device *netdev = pci_get_drvdata(pdev); 7671 struct igb_adapter *adapter = netdev_priv(netdev); 7672 struct e1000_hw *hw = &adapter->hw; 7673 pci_ers_result_t result; 7674 int err; 7675 7676 if (pci_enable_device_mem(pdev)) { 7677 dev_err(&pdev->dev, 7678 "Cannot re-enable PCI device after reset.\n"); 7679 result = PCI_ERS_RESULT_DISCONNECT; 7680 } else { 7681 pci_set_master(pdev); 7682 pci_restore_state(pdev); 7683 pci_save_state(pdev); 7684 7685 pci_enable_wake(pdev, PCI_D3hot, 0); 7686 pci_enable_wake(pdev, PCI_D3cold, 0); 7687 7688 igb_reset(adapter); 7689 wr32(E1000_WUS, ~0); 7690 result = PCI_ERS_RESULT_RECOVERED; 7691 } 7692 7693 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7694 if (err) { 7695 dev_err(&pdev->dev, 7696 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7697 err); 7698 /* non-fatal, continue */ 7699 } 7700 7701 return result; 7702} 7703 7704/** 7705 * igb_io_resume - called when traffic can start flowing again. 7706 * @pdev: Pointer to PCI device 7707 * 7708 * This callback is called when the error recovery driver tells us that 7709 * its OK to resume normal operation. Implementation resembles the 7710 * second-half of the igb_resume routine. 7711 */ 7712static void igb_io_resume(struct pci_dev *pdev) 7713{ 7714 struct net_device *netdev = pci_get_drvdata(pdev); 7715 struct igb_adapter *adapter = netdev_priv(netdev); 7716 7717 if (netif_running(netdev)) { 7718 if (igb_up(adapter)) { 7719 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7720 return; 7721 } 7722 } 7723 7724 netif_device_attach(netdev); 7725 7726 /* let the f/w know that the h/w is now under the control of the 7727 * driver. 7728 */ 7729 igb_get_hw_control(adapter); 7730} 7731 7732static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7733 u8 qsel) 7734{ 7735 u32 rar_low, rar_high; 7736 struct e1000_hw *hw = &adapter->hw; 7737 7738 /* HW expects these in little endian so we reverse the byte order 7739 * from network order (big endian) to little endian 7740 */ 7741 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 7742 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 7743 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 7744 7745 /* Indicate to hardware the Address is Valid. */ 7746 rar_high |= E1000_RAH_AV; 7747 7748 if (hw->mac.type == e1000_82575) 7749 rar_high |= E1000_RAH_POOL_1 * qsel; 7750 else 7751 rar_high |= E1000_RAH_POOL_1 << qsel; 7752 7753 wr32(E1000_RAL(index), rar_low); 7754 wrfl(); 7755 wr32(E1000_RAH(index), rar_high); 7756 wrfl(); 7757} 7758 7759static int igb_set_vf_mac(struct igb_adapter *adapter, 7760 int vf, unsigned char *mac_addr) 7761{ 7762 struct e1000_hw *hw = &adapter->hw; 7763 /* VF MAC addresses start at end of receive addresses and moves 7764 * towards the first, as a result a collision should not be possible 7765 */ 7766 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7767 7768 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7769 7770 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7771 7772 return 0; 7773} 7774 7775static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7776{ 7777 struct igb_adapter *adapter = netdev_priv(netdev); 7778 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7779 return -EINVAL; 7780 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7781 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7782 dev_info(&adapter->pdev->dev, 7783 "Reload the VF driver to make this change effective."); 7784 if (test_bit(__IGB_DOWN, &adapter->state)) { 7785 dev_warn(&adapter->pdev->dev, 7786 "The VF MAC address has been set, but the PF device is not up.\n"); 7787 dev_warn(&adapter->pdev->dev, 7788 "Bring the PF device up before attempting to use the VF device.\n"); 7789 } 7790 return igb_set_vf_mac(adapter, vf, mac); 7791} 7792 7793static int igb_link_mbps(int internal_link_speed) 7794{ 7795 switch (internal_link_speed) { 7796 case SPEED_100: 7797 return 100; 7798 case SPEED_1000: 7799 return 1000; 7800 default: 7801 return 0; 7802 } 7803} 7804 7805static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7806 int link_speed) 7807{ 7808 int rf_dec, rf_int; 7809 u32 bcnrc_val; 7810 7811 if (tx_rate != 0) { 7812 /* Calculate the rate factor values to set */ 7813 rf_int = link_speed / tx_rate; 7814 rf_dec = (link_speed - (rf_int * tx_rate)); 7815 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / 7816 tx_rate; 7817 7818 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7819 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 7820 E1000_RTTBCNRC_RF_INT_MASK); 7821 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7822 } else { 7823 bcnrc_val = 0; 7824 } 7825 7826 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7827 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7828 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7829 */ 7830 wr32(E1000_RTTBCNRM, 0x14); 7831 wr32(E1000_RTTBCNRC, bcnrc_val); 7832} 7833 7834static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7835{ 7836 int actual_link_speed, i; 7837 bool reset_rate = false; 7838 7839 /* VF TX rate limit was not set or not supported */ 7840 if ((adapter->vf_rate_link_speed == 0) || 7841 (adapter->hw.mac.type != e1000_82576)) 7842 return; 7843 7844 actual_link_speed = igb_link_mbps(adapter->link_speed); 7845 if (actual_link_speed != adapter->vf_rate_link_speed) { 7846 reset_rate = true; 7847 adapter->vf_rate_link_speed = 0; 7848 dev_info(&adapter->pdev->dev, 7849 "Link speed has been changed. VF Transmit rate is disabled\n"); 7850 } 7851 7852 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7853 if (reset_rate) 7854 adapter->vf_data[i].tx_rate = 0; 7855 7856 igb_set_vf_rate_limit(&adapter->hw, i, 7857 adapter->vf_data[i].tx_rate, 7858 actual_link_speed); 7859 } 7860} 7861 7862static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) 7863{ 7864 struct igb_adapter *adapter = netdev_priv(netdev); 7865 struct e1000_hw *hw = &adapter->hw; 7866 int actual_link_speed; 7867 7868 if (hw->mac.type != e1000_82576) 7869 return -EOPNOTSUPP; 7870 7871 actual_link_speed = igb_link_mbps(adapter->link_speed); 7872 if ((vf >= adapter->vfs_allocated_count) || 7873 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7874 (tx_rate < 0) || (tx_rate > actual_link_speed)) 7875 return -EINVAL; 7876 7877 adapter->vf_rate_link_speed = actual_link_speed; 7878 adapter->vf_data[vf].tx_rate = (u16)tx_rate; 7879 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); 7880 7881 return 0; 7882} 7883 7884static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 7885 bool setting) 7886{ 7887 struct igb_adapter *adapter = netdev_priv(netdev); 7888 struct e1000_hw *hw = &adapter->hw; 7889 u32 reg_val, reg_offset; 7890 7891 if (!adapter->vfs_allocated_count) 7892 return -EOPNOTSUPP; 7893 7894 if (vf >= adapter->vfs_allocated_count) 7895 return -EINVAL; 7896 7897 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 7898 reg_val = rd32(reg_offset); 7899 if (setting) 7900 reg_val |= ((1 << vf) | 7901 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7902 else 7903 reg_val &= ~((1 << vf) | 7904 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7905 wr32(reg_offset, reg_val); 7906 7907 adapter->vf_data[vf].spoofchk_enabled = setting; 7908 return E1000_SUCCESS; 7909} 7910 7911static int igb_ndo_get_vf_config(struct net_device *netdev, 7912 int vf, struct ifla_vf_info *ivi) 7913{ 7914 struct igb_adapter *adapter = netdev_priv(netdev); 7915 if (vf >= adapter->vfs_allocated_count) 7916 return -EINVAL; 7917 ivi->vf = vf; 7918 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7919 ivi->tx_rate = adapter->vf_data[vf].tx_rate; 7920 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7921 ivi->qos = adapter->vf_data[vf].pf_qos; 7922 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 7923 return 0; 7924} 7925 7926static void igb_vmm_control(struct igb_adapter *adapter) 7927{ 7928 struct e1000_hw *hw = &adapter->hw; 7929 u32 reg; 7930 7931 switch (hw->mac.type) { 7932 case e1000_82575: 7933 case e1000_i210: 7934 case e1000_i211: 7935 case e1000_i354: 7936 default: 7937 /* replication is not supported for 82575 */ 7938 return; 7939 case e1000_82576: 7940 /* notify HW that the MAC is adding vlan tags */ 7941 reg = rd32(E1000_DTXCTL); 7942 reg |= E1000_DTXCTL_VLAN_ADDED; 7943 wr32(E1000_DTXCTL, reg); 7944 case e1000_82580: 7945 /* enable replication vlan tag stripping */ 7946 reg = rd32(E1000_RPLOLR); 7947 reg |= E1000_RPLOLR_STRVLAN; 7948 wr32(E1000_RPLOLR, reg); 7949 case e1000_i350: 7950 /* none of the above registers are supported by i350 */ 7951 break; 7952 } 7953 7954 if (adapter->vfs_allocated_count) { 7955 igb_vmdq_set_loopback_pf(hw, true); 7956 igb_vmdq_set_replication_pf(hw, true); 7957 igb_vmdq_set_anti_spoofing_pf(hw, true, 7958 adapter->vfs_allocated_count); 7959 } else { 7960 igb_vmdq_set_loopback_pf(hw, false); 7961 igb_vmdq_set_replication_pf(hw, false); 7962 } 7963} 7964 7965static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7966{ 7967 struct e1000_hw *hw = &adapter->hw; 7968 u32 dmac_thr; 7969 u16 hwm; 7970 7971 if (hw->mac.type > e1000_82580) { 7972 if (adapter->flags & IGB_FLAG_DMAC) { 7973 u32 reg; 7974 7975 /* force threshold to 0. */ 7976 wr32(E1000_DMCTXTH, 0); 7977 7978 /* DMA Coalescing high water mark needs to be greater 7979 * than the Rx threshold. Set hwm to PBA - max frame 7980 * size in 16B units, capping it at PBA - 6KB. 7981 */ 7982 hwm = 64 * pba - adapter->max_frame_size / 16; 7983 if (hwm < 64 * (pba - 6)) 7984 hwm = 64 * (pba - 6); 7985 reg = rd32(E1000_FCRTC); 7986 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 7987 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 7988 & E1000_FCRTC_RTH_COAL_MASK); 7989 wr32(E1000_FCRTC, reg); 7990 7991 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 7992 * frame size, capping it at PBA - 10KB. 7993 */ 7994 dmac_thr = pba - adapter->max_frame_size / 512; 7995 if (dmac_thr < pba - 10) 7996 dmac_thr = pba - 10; 7997 reg = rd32(E1000_DMACR); 7998 reg &= ~E1000_DMACR_DMACTHR_MASK; 7999 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 8000 & E1000_DMACR_DMACTHR_MASK); 8001 8002 /* transition to L0x or L1 if available..*/ 8003 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 8004 8005 /* watchdog timer= +-1000 usec in 32usec intervals */ 8006 reg |= (1000 >> 5); 8007 8008 /* Disable BMC-to-OS Watchdog Enable */ 8009 if (hw->mac.type != e1000_i354) 8010 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 8011 8012 wr32(E1000_DMACR, reg); 8013 8014 /* no lower threshold to disable 8015 * coalescing(smart fifb)-UTRESH=0 8016 */ 8017 wr32(E1000_DMCRTRH, 0); 8018 8019 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8020 8021 wr32(E1000_DMCTLX, reg); 8022 8023 /* free space in tx packet buffer to wake from 8024 * DMA coal 8025 */ 8026 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8027 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8028 8029 /* make low power state decision controlled 8030 * by DMA coal 8031 */ 8032 reg = rd32(E1000_PCIEMISC); 8033 reg &= ~E1000_PCIEMISC_LX_DECISION; 8034 wr32(E1000_PCIEMISC, reg); 8035 } /* endif adapter->dmac is not disabled */ 8036 } else if (hw->mac.type == e1000_82580) { 8037 u32 reg = rd32(E1000_PCIEMISC); 8038 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8039 wr32(E1000_DMACR, 0); 8040 } 8041} 8042 8043/** 8044 * igb_read_i2c_byte - Reads 8 bit word over I2C 8045 * @hw: pointer to hardware structure 8046 * @byte_offset: byte offset to read 8047 * @dev_addr: device address 8048 * @data: value read 8049 * 8050 * Performs byte read operation over I2C interface at 8051 * a specified device address. 8052 **/ 8053s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8054 u8 dev_addr, u8 *data) 8055{ 8056 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8057 struct i2c_client *this_client = adapter->i2c_client; 8058 s32 status; 8059 u16 swfw_mask = 0; 8060 8061 if (!this_client) 8062 return E1000_ERR_I2C; 8063 8064 swfw_mask = E1000_SWFW_PHY0_SM; 8065 8066 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 8067 != E1000_SUCCESS) 8068 return E1000_ERR_SWFW_SYNC; 8069 8070 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8071 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8072 8073 if (status < 0) 8074 return E1000_ERR_I2C; 8075 else { 8076 *data = status; 8077 return E1000_SUCCESS; 8078 } 8079} 8080 8081/** 8082 * igb_write_i2c_byte - Writes 8 bit word over I2C 8083 * @hw: pointer to hardware structure 8084 * @byte_offset: byte offset to write 8085 * @dev_addr: device address 8086 * @data: value to write 8087 * 8088 * Performs byte write operation over I2C interface at 8089 * a specified device address. 8090 **/ 8091s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8092 u8 dev_addr, u8 data) 8093{ 8094 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8095 struct i2c_client *this_client = adapter->i2c_client; 8096 s32 status; 8097 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8098 8099 if (!this_client) 8100 return E1000_ERR_I2C; 8101 8102 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) 8103 return E1000_ERR_SWFW_SYNC; 8104 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8105 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8106 8107 if (status) 8108 return E1000_ERR_I2C; 8109 else 8110 return E1000_SUCCESS; 8111 8112} 8113 8114int igb_reinit_queues(struct igb_adapter *adapter) 8115{ 8116 struct net_device *netdev = adapter->netdev; 8117 struct pci_dev *pdev = adapter->pdev; 8118 int err = 0; 8119 8120 if (netif_running(netdev)) 8121 igb_close(netdev); 8122 8123 igb_reset_interrupt_capability(adapter); 8124 8125 if (igb_init_interrupt_scheme(adapter, true)) { 8126 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8127 return -ENOMEM; 8128 } 8129 8130 if (netif_running(netdev)) 8131 err = igb_open(netdev); 8132 8133 return err; 8134} 8135/* igb_main.c */ 8136