igb_main.c revision e52c0f960cbc2c691cbb809ac0bfec2becfe6da9
1/* Intel(R) Gigabit Ethernet Linux driver 2 * Copyright(c) 2007-2014 Intel Corporation. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program; if not, see <http://www.gnu.org/licenses/>. 15 * 16 * The full GNU General Public License is included in this distribution in 17 * the file called "COPYING". 18 * 19 * Contact Information: 20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 22 */ 23 24#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 25 26#include <linux/module.h> 27#include <linux/types.h> 28#include <linux/init.h> 29#include <linux/bitops.h> 30#include <linux/vmalloc.h> 31#include <linux/pagemap.h> 32#include <linux/netdevice.h> 33#include <linux/ipv6.h> 34#include <linux/slab.h> 35#include <net/checksum.h> 36#include <net/ip6_checksum.h> 37#include <linux/net_tstamp.h> 38#include <linux/mii.h> 39#include <linux/ethtool.h> 40#include <linux/if.h> 41#include <linux/if_vlan.h> 42#include <linux/pci.h> 43#include <linux/pci-aspm.h> 44#include <linux/delay.h> 45#include <linux/interrupt.h> 46#include <linux/ip.h> 47#include <linux/tcp.h> 48#include <linux/sctp.h> 49#include <linux/if_ether.h> 50#include <linux/aer.h> 51#include <linux/prefetch.h> 52#include <linux/pm_runtime.h> 53#ifdef CONFIG_IGB_DCA 54#include <linux/dca.h> 55#endif 56#include <linux/i2c.h> 57#include "igb.h" 58 59#define MAJ 5 60#define MIN 0 61#define BUILD 5 62#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 63__stringify(BUILD) "-k" 64char igb_driver_name[] = "igb"; 65char igb_driver_version[] = DRV_VERSION; 66static const char igb_driver_string[] = 67 "Intel(R) Gigabit Ethernet Network Driver"; 68static const char igb_copyright[] = 69 "Copyright (c) 2007-2014 Intel Corporation."; 70 71static const struct e1000_info *igb_info_tbl[] = { 72 [board_82575] = &e1000_82575_info, 73}; 74 75static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { 76 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 77 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 78 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 111 /* required last entry */ 112 {0, } 113}; 114 115MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 116 117void igb_reset(struct igb_adapter *); 118static int igb_setup_all_tx_resources(struct igb_adapter *); 119static int igb_setup_all_rx_resources(struct igb_adapter *); 120static void igb_free_all_tx_resources(struct igb_adapter *); 121static void igb_free_all_rx_resources(struct igb_adapter *); 122static void igb_setup_mrqc(struct igb_adapter *); 123static int igb_probe(struct pci_dev *, const struct pci_device_id *); 124static void igb_remove(struct pci_dev *pdev); 125static int igb_sw_init(struct igb_adapter *); 126static int igb_open(struct net_device *); 127static int igb_close(struct net_device *); 128static void igb_configure(struct igb_adapter *); 129static void igb_configure_tx(struct igb_adapter *); 130static void igb_configure_rx(struct igb_adapter *); 131static void igb_clean_all_tx_rings(struct igb_adapter *); 132static void igb_clean_all_rx_rings(struct igb_adapter *); 133static void igb_clean_tx_ring(struct igb_ring *); 134static void igb_clean_rx_ring(struct igb_ring *); 135static void igb_set_rx_mode(struct net_device *); 136static void igb_update_phy_info(unsigned long); 137static void igb_watchdog(unsigned long); 138static void igb_watchdog_task(struct work_struct *); 139static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 140static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 141 struct rtnl_link_stats64 *stats); 142static int igb_change_mtu(struct net_device *, int); 143static int igb_set_mac(struct net_device *, void *); 144static void igb_set_uta(struct igb_adapter *adapter); 145static irqreturn_t igb_intr(int irq, void *); 146static irqreturn_t igb_intr_msi(int irq, void *); 147static irqreturn_t igb_msix_other(int irq, void *); 148static irqreturn_t igb_msix_ring(int irq, void *); 149#ifdef CONFIG_IGB_DCA 150static void igb_update_dca(struct igb_q_vector *); 151static void igb_setup_dca(struct igb_adapter *); 152#endif /* CONFIG_IGB_DCA */ 153static int igb_poll(struct napi_struct *, int); 154static bool igb_clean_tx_irq(struct igb_q_vector *); 155static bool igb_clean_rx_irq(struct igb_q_vector *, int); 156static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 157static void igb_tx_timeout(struct net_device *); 158static void igb_reset_task(struct work_struct *); 159static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); 160static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 161static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 162static void igb_restore_vlan(struct igb_adapter *); 163static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 164static void igb_ping_all_vfs(struct igb_adapter *); 165static void igb_msg_task(struct igb_adapter *); 166static void igb_vmm_control(struct igb_adapter *); 167static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 168static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 169static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 170static int igb_ndo_set_vf_vlan(struct net_device *netdev, 171 int vf, u16 vlan, u8 qos); 172static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 173static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 174 bool setting); 175static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 176 struct ifla_vf_info *ivi); 177static void igb_check_vf_rate_limit(struct igb_adapter *); 178 179#ifdef CONFIG_PCI_IOV 180static int igb_vf_configure(struct igb_adapter *adapter, int vf); 181static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 182#endif 183 184#ifdef CONFIG_PM 185#ifdef CONFIG_PM_SLEEP 186static int igb_suspend(struct device *); 187#endif 188static int igb_resume(struct device *); 189#ifdef CONFIG_PM_RUNTIME 190static int igb_runtime_suspend(struct device *dev); 191static int igb_runtime_resume(struct device *dev); 192static int igb_runtime_idle(struct device *dev); 193#endif 194static const struct dev_pm_ops igb_pm_ops = { 195 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 196 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 197 igb_runtime_idle) 198}; 199#endif 200static void igb_shutdown(struct pci_dev *); 201static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 202#ifdef CONFIG_IGB_DCA 203static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 204static struct notifier_block dca_notifier = { 205 .notifier_call = igb_notify_dca, 206 .next = NULL, 207 .priority = 0 208}; 209#endif 210#ifdef CONFIG_NET_POLL_CONTROLLER 211/* for netdump / net console */ 212static void igb_netpoll(struct net_device *); 213#endif 214#ifdef CONFIG_PCI_IOV 215static unsigned int max_vfs = 0; 216module_param(max_vfs, uint, 0); 217MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function"); 218#endif /* CONFIG_PCI_IOV */ 219 220static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 221 pci_channel_state_t); 222static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 223static void igb_io_resume(struct pci_dev *); 224 225static const struct pci_error_handlers igb_err_handler = { 226 .error_detected = igb_io_error_detected, 227 .slot_reset = igb_io_slot_reset, 228 .resume = igb_io_resume, 229}; 230 231static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 232 233static struct pci_driver igb_driver = { 234 .name = igb_driver_name, 235 .id_table = igb_pci_tbl, 236 .probe = igb_probe, 237 .remove = igb_remove, 238#ifdef CONFIG_PM 239 .driver.pm = &igb_pm_ops, 240#endif 241 .shutdown = igb_shutdown, 242 .sriov_configure = igb_pci_sriov_configure, 243 .err_handler = &igb_err_handler 244}; 245 246MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 247MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 248MODULE_LICENSE("GPL"); 249MODULE_VERSION(DRV_VERSION); 250 251#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 252static int debug = -1; 253module_param(debug, int, 0); 254MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 255 256struct igb_reg_info { 257 u32 ofs; 258 char *name; 259}; 260 261static const struct igb_reg_info igb_reg_info_tbl[] = { 262 263 /* General Registers */ 264 {E1000_CTRL, "CTRL"}, 265 {E1000_STATUS, "STATUS"}, 266 {E1000_CTRL_EXT, "CTRL_EXT"}, 267 268 /* Interrupt Registers */ 269 {E1000_ICR, "ICR"}, 270 271 /* RX Registers */ 272 {E1000_RCTL, "RCTL"}, 273 {E1000_RDLEN(0), "RDLEN"}, 274 {E1000_RDH(0), "RDH"}, 275 {E1000_RDT(0), "RDT"}, 276 {E1000_RXDCTL(0), "RXDCTL"}, 277 {E1000_RDBAL(0), "RDBAL"}, 278 {E1000_RDBAH(0), "RDBAH"}, 279 280 /* TX Registers */ 281 {E1000_TCTL, "TCTL"}, 282 {E1000_TDBAL(0), "TDBAL"}, 283 {E1000_TDBAH(0), "TDBAH"}, 284 {E1000_TDLEN(0), "TDLEN"}, 285 {E1000_TDH(0), "TDH"}, 286 {E1000_TDT(0), "TDT"}, 287 {E1000_TXDCTL(0), "TXDCTL"}, 288 {E1000_TDFH, "TDFH"}, 289 {E1000_TDFT, "TDFT"}, 290 {E1000_TDFHS, "TDFHS"}, 291 {E1000_TDFPC, "TDFPC"}, 292 293 /* List Terminator */ 294 {} 295}; 296 297/* igb_regdump - register printout routine */ 298static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 299{ 300 int n = 0; 301 char rname[16]; 302 u32 regs[8]; 303 304 switch (reginfo->ofs) { 305 case E1000_RDLEN(0): 306 for (n = 0; n < 4; n++) 307 regs[n] = rd32(E1000_RDLEN(n)); 308 break; 309 case E1000_RDH(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDH(n)); 312 break; 313 case E1000_RDT(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDT(n)); 316 break; 317 case E1000_RXDCTL(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_RXDCTL(n)); 320 break; 321 case E1000_RDBAL(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_RDBAL(n)); 324 break; 325 case E1000_RDBAH(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_RDBAH(n)); 328 break; 329 case E1000_TDBAL(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_RDBAL(n)); 332 break; 333 case E1000_TDBAH(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_TDBAH(n)); 336 break; 337 case E1000_TDLEN(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TDLEN(n)); 340 break; 341 case E1000_TDH(0): 342 for (n = 0; n < 4; n++) 343 regs[n] = rd32(E1000_TDH(n)); 344 break; 345 case E1000_TDT(0): 346 for (n = 0; n < 4; n++) 347 regs[n] = rd32(E1000_TDT(n)); 348 break; 349 case E1000_TXDCTL(0): 350 for (n = 0; n < 4; n++) 351 regs[n] = rd32(E1000_TXDCTL(n)); 352 break; 353 default: 354 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 355 return; 356 } 357 358 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 359 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 360 regs[2], regs[3]); 361} 362 363/* igb_dump - Print registers, Tx-rings and Rx-rings */ 364static void igb_dump(struct igb_adapter *adapter) 365{ 366 struct net_device *netdev = adapter->netdev; 367 struct e1000_hw *hw = &adapter->hw; 368 struct igb_reg_info *reginfo; 369 struct igb_ring *tx_ring; 370 union e1000_adv_tx_desc *tx_desc; 371 struct my_u0 { u64 a; u64 b; } *u0; 372 struct igb_ring *rx_ring; 373 union e1000_adv_rx_desc *rx_desc; 374 u32 staterr; 375 u16 i, n; 376 377 if (!netif_msg_hw(adapter)) 378 return; 379 380 /* Print netdevice Info */ 381 if (netdev) { 382 dev_info(&adapter->pdev->dev, "Net device Info\n"); 383 pr_info("Device Name state trans_start last_rx\n"); 384 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 385 netdev->state, netdev->trans_start, netdev->last_rx); 386 } 387 388 /* Print Registers */ 389 dev_info(&adapter->pdev->dev, "Register Dump\n"); 390 pr_info(" Register Name Value\n"); 391 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 392 reginfo->name; reginfo++) { 393 igb_regdump(hw, reginfo); 394 } 395 396 /* Print TX Ring Summary */ 397 if (!netdev || !netif_running(netdev)) 398 goto exit; 399 400 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 401 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 402 for (n = 0; n < adapter->num_tx_queues; n++) { 403 struct igb_tx_buffer *buffer_info; 404 tx_ring = adapter->tx_ring[n]; 405 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 406 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 407 n, tx_ring->next_to_use, tx_ring->next_to_clean, 408 (u64)dma_unmap_addr(buffer_info, dma), 409 dma_unmap_len(buffer_info, len), 410 buffer_info->next_to_watch, 411 (u64)buffer_info->time_stamp); 412 } 413 414 /* Print TX Rings */ 415 if (!netif_msg_tx_done(adapter)) 416 goto rx_ring_summary; 417 418 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 419 420 /* Transmit Descriptor Formats 421 * 422 * Advanced Transmit Descriptor 423 * +--------------------------------------------------------------+ 424 * 0 | Buffer Address [63:0] | 425 * +--------------------------------------------------------------+ 426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 427 * +--------------------------------------------------------------+ 428 * 63 46 45 40 39 38 36 35 32 31 24 15 0 429 */ 430 431 for (n = 0; n < adapter->num_tx_queues; n++) { 432 tx_ring = adapter->tx_ring[n]; 433 pr_info("------------------------------------\n"); 434 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 435 pr_info("------------------------------------\n"); 436 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] [bi->dma ] leng ntw timestamp bi->skb\n"); 437 438 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 439 const char *next_desc; 440 struct igb_tx_buffer *buffer_info; 441 tx_desc = IGB_TX_DESC(tx_ring, i); 442 buffer_info = &tx_ring->tx_buffer_info[i]; 443 u0 = (struct my_u0 *)tx_desc; 444 if (i == tx_ring->next_to_use && 445 i == tx_ring->next_to_clean) 446 next_desc = " NTC/U"; 447 else if (i == tx_ring->next_to_use) 448 next_desc = " NTU"; 449 else if (i == tx_ring->next_to_clean) 450 next_desc = " NTC"; 451 else 452 next_desc = ""; 453 454 pr_info("T [0x%03X] %016llX %016llX %016llX %04X %p %016llX %p%s\n", 455 i, le64_to_cpu(u0->a), 456 le64_to_cpu(u0->b), 457 (u64)dma_unmap_addr(buffer_info, dma), 458 dma_unmap_len(buffer_info, len), 459 buffer_info->next_to_watch, 460 (u64)buffer_info->time_stamp, 461 buffer_info->skb, next_desc); 462 463 if (netif_msg_pktdata(adapter) && buffer_info->skb) 464 print_hex_dump(KERN_INFO, "", 465 DUMP_PREFIX_ADDRESS, 466 16, 1, buffer_info->skb->data, 467 dma_unmap_len(buffer_info, len), 468 true); 469 } 470 } 471 472 /* Print RX Rings Summary */ 473rx_ring_summary: 474 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 475 pr_info("Queue [NTU] [NTC]\n"); 476 for (n = 0; n < adapter->num_rx_queues; n++) { 477 rx_ring = adapter->rx_ring[n]; 478 pr_info(" %5d %5X %5X\n", 479 n, rx_ring->next_to_use, rx_ring->next_to_clean); 480 } 481 482 /* Print RX Rings */ 483 if (!netif_msg_rx_status(adapter)) 484 goto exit; 485 486 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 487 488 /* Advanced Receive Descriptor (Read) Format 489 * 63 1 0 490 * +-----------------------------------------------------+ 491 * 0 | Packet Buffer Address [63:1] |A0/NSE| 492 * +----------------------------------------------+------+ 493 * 8 | Header Buffer Address [63:1] | DD | 494 * +-----------------------------------------------------+ 495 * 496 * 497 * Advanced Receive Descriptor (Write-Back) Format 498 * 499 * 63 48 47 32 31 30 21 20 17 16 4 3 0 500 * +------------------------------------------------------+ 501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 502 * | Checksum Ident | | | | Type | Type | 503 * +------------------------------------------------------+ 504 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 505 * +------------------------------------------------------+ 506 * 63 48 47 32 31 20 19 0 507 */ 508 509 for (n = 0; n < adapter->num_rx_queues; n++) { 510 rx_ring = adapter->rx_ring[n]; 511 pr_info("------------------------------------\n"); 512 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 513 pr_info("------------------------------------\n"); 514 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] [bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n"); 516 517 for (i = 0; i < rx_ring->count; i++) { 518 const char *next_desc; 519 struct igb_rx_buffer *buffer_info; 520 buffer_info = &rx_ring->rx_buffer_info[i]; 521 rx_desc = IGB_RX_DESC(rx_ring, i); 522 u0 = (struct my_u0 *)rx_desc; 523 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 524 525 if (i == rx_ring->next_to_use) 526 next_desc = " NTU"; 527 else if (i == rx_ring->next_to_clean) 528 next_desc = " NTC"; 529 else 530 next_desc = ""; 531 532 if (staterr & E1000_RXD_STAT_DD) { 533 /* Descriptor Done */ 534 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 535 "RWB", i, 536 le64_to_cpu(u0->a), 537 le64_to_cpu(u0->b), 538 next_desc); 539 } else { 540 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 541 "R ", i, 542 le64_to_cpu(u0->a), 543 le64_to_cpu(u0->b), 544 (u64)buffer_info->dma, 545 next_desc); 546 547 if (netif_msg_pktdata(adapter) && 548 buffer_info->dma && buffer_info->page) { 549 print_hex_dump(KERN_INFO, "", 550 DUMP_PREFIX_ADDRESS, 551 16, 1, 552 page_address(buffer_info->page) + 553 buffer_info->page_offset, 554 IGB_RX_BUFSZ, true); 555 } 556 } 557 } 558 } 559 560exit: 561 return; 562} 563 564/** 565 * igb_get_i2c_data - Reads the I2C SDA data bit 566 * @hw: pointer to hardware structure 567 * @i2cctl: Current value of I2CCTL register 568 * 569 * Returns the I2C data bit value 570 **/ 571static int igb_get_i2c_data(void *data) 572{ 573 struct igb_adapter *adapter = (struct igb_adapter *)data; 574 struct e1000_hw *hw = &adapter->hw; 575 s32 i2cctl = rd32(E1000_I2CPARAMS); 576 577 return ((i2cctl & E1000_I2C_DATA_IN) != 0); 578} 579 580/** 581 * igb_set_i2c_data - Sets the I2C data bit 582 * @data: pointer to hardware structure 583 * @state: I2C data value (0 or 1) to set 584 * 585 * Sets the I2C data bit 586 **/ 587static void igb_set_i2c_data(void *data, int state) 588{ 589 struct igb_adapter *adapter = (struct igb_adapter *)data; 590 struct e1000_hw *hw = &adapter->hw; 591 s32 i2cctl = rd32(E1000_I2CPARAMS); 592 593 if (state) 594 i2cctl |= E1000_I2C_DATA_OUT; 595 else 596 i2cctl &= ~E1000_I2C_DATA_OUT; 597 598 i2cctl &= ~E1000_I2C_DATA_OE_N; 599 i2cctl |= E1000_I2C_CLK_OE_N; 600 wr32(E1000_I2CPARAMS, i2cctl); 601 wrfl(); 602 603} 604 605/** 606 * igb_set_i2c_clk - Sets the I2C SCL clock 607 * @data: pointer to hardware structure 608 * @state: state to set clock 609 * 610 * Sets the I2C clock line to state 611 **/ 612static void igb_set_i2c_clk(void *data, int state) 613{ 614 struct igb_adapter *adapter = (struct igb_adapter *)data; 615 struct e1000_hw *hw = &adapter->hw; 616 s32 i2cctl = rd32(E1000_I2CPARAMS); 617 618 if (state) { 619 i2cctl |= E1000_I2C_CLK_OUT; 620 i2cctl &= ~E1000_I2C_CLK_OE_N; 621 } else { 622 i2cctl &= ~E1000_I2C_CLK_OUT; 623 i2cctl &= ~E1000_I2C_CLK_OE_N; 624 } 625 wr32(E1000_I2CPARAMS, i2cctl); 626 wrfl(); 627} 628 629/** 630 * igb_get_i2c_clk - Gets the I2C SCL clock state 631 * @data: pointer to hardware structure 632 * 633 * Gets the I2C clock state 634 **/ 635static int igb_get_i2c_clk(void *data) 636{ 637 struct igb_adapter *adapter = (struct igb_adapter *)data; 638 struct e1000_hw *hw = &adapter->hw; 639 s32 i2cctl = rd32(E1000_I2CPARAMS); 640 641 return ((i2cctl & E1000_I2C_CLK_IN) != 0); 642} 643 644static const struct i2c_algo_bit_data igb_i2c_algo = { 645 .setsda = igb_set_i2c_data, 646 .setscl = igb_set_i2c_clk, 647 .getsda = igb_get_i2c_data, 648 .getscl = igb_get_i2c_clk, 649 .udelay = 5, 650 .timeout = 20, 651}; 652 653/** 654 * igb_get_hw_dev - return device 655 * @hw: pointer to hardware structure 656 * 657 * used by hardware layer to print debugging information 658 **/ 659struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 660{ 661 struct igb_adapter *adapter = hw->back; 662 return adapter->netdev; 663} 664 665/** 666 * igb_init_module - Driver Registration Routine 667 * 668 * igb_init_module is the first routine called when the driver is 669 * loaded. All it does is register with the PCI subsystem. 670 **/ 671static int __init igb_init_module(void) 672{ 673 int ret; 674 675 pr_info("%s - version %s\n", 676 igb_driver_string, igb_driver_version); 677 pr_info("%s\n", igb_copyright); 678 679#ifdef CONFIG_IGB_DCA 680 dca_register_notify(&dca_notifier); 681#endif 682 ret = pci_register_driver(&igb_driver); 683 return ret; 684} 685 686module_init(igb_init_module); 687 688/** 689 * igb_exit_module - Driver Exit Cleanup Routine 690 * 691 * igb_exit_module is called just before the driver is removed 692 * from memory. 693 **/ 694static void __exit igb_exit_module(void) 695{ 696#ifdef CONFIG_IGB_DCA 697 dca_unregister_notify(&dca_notifier); 698#endif 699 pci_unregister_driver(&igb_driver); 700} 701 702module_exit(igb_exit_module); 703 704#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 705/** 706 * igb_cache_ring_register - Descriptor ring to register mapping 707 * @adapter: board private structure to initialize 708 * 709 * Once we know the feature-set enabled for the device, we'll cache 710 * the register offset the descriptor ring is assigned to. 711 **/ 712static void igb_cache_ring_register(struct igb_adapter *adapter) 713{ 714 int i = 0, j = 0; 715 u32 rbase_offset = adapter->vfs_allocated_count; 716 717 switch (adapter->hw.mac.type) { 718 case e1000_82576: 719 /* The queues are allocated for virtualization such that VF 0 720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 721 * In order to avoid collision we start at the first free queue 722 * and continue consuming queues in the same sequence 723 */ 724 if (adapter->vfs_allocated_count) { 725 for (; i < adapter->rss_queues; i++) 726 adapter->rx_ring[i]->reg_idx = rbase_offset + 727 Q_IDX_82576(i); 728 } 729 case e1000_82575: 730 case e1000_82580: 731 case e1000_i350: 732 case e1000_i354: 733 case e1000_i210: 734 case e1000_i211: 735 default: 736 for (; i < adapter->num_rx_queues; i++) 737 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 738 for (; j < adapter->num_tx_queues; j++) 739 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 740 break; 741 } 742} 743 744u32 igb_rd32(struct e1000_hw *hw, u32 reg) 745{ 746 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 747 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 748 u32 value = 0; 749 750 if (E1000_REMOVED(hw_addr)) 751 return ~value; 752 753 value = readl(&hw_addr[reg]); 754 755 /* reads should not return all F's */ 756 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 757 struct net_device *netdev = igb->netdev; 758 hw->hw_addr = NULL; 759 netif_device_detach(netdev); 760 netdev_err(netdev, "PCIe link lost, device now detached\n"); 761 } 762 763 return value; 764} 765 766/** 767 * igb_write_ivar - configure ivar for given MSI-X vector 768 * @hw: pointer to the HW structure 769 * @msix_vector: vector number we are allocating to a given ring 770 * @index: row index of IVAR register to write within IVAR table 771 * @offset: column offset of in IVAR, should be multiple of 8 772 * 773 * This function is intended to handle the writing of the IVAR register 774 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 775 * each containing an cause allocation for an Rx and Tx ring, and a 776 * variable number of rows depending on the number of queues supported. 777 **/ 778static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 779 int index, int offset) 780{ 781 u32 ivar = array_rd32(E1000_IVAR0, index); 782 783 /* clear any bits that are currently set */ 784 ivar &= ~((u32)0xFF << offset); 785 786 /* write vector and valid bit */ 787 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 788 789 array_wr32(E1000_IVAR0, index, ivar); 790} 791 792#define IGB_N0_QUEUE -1 793static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 794{ 795 struct igb_adapter *adapter = q_vector->adapter; 796 struct e1000_hw *hw = &adapter->hw; 797 int rx_queue = IGB_N0_QUEUE; 798 int tx_queue = IGB_N0_QUEUE; 799 u32 msixbm = 0; 800 801 if (q_vector->rx.ring) 802 rx_queue = q_vector->rx.ring->reg_idx; 803 if (q_vector->tx.ring) 804 tx_queue = q_vector->tx.ring->reg_idx; 805 806 switch (hw->mac.type) { 807 case e1000_82575: 808 /* The 82575 assigns vectors using a bitmask, which matches the 809 * bitmask for the EICR/EIMS/EIMC registers. To assign one 810 * or more queues to a vector, we write the appropriate bits 811 * into the MSIXBM register for that vector. 812 */ 813 if (rx_queue > IGB_N0_QUEUE) 814 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 815 if (tx_queue > IGB_N0_QUEUE) 816 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 817 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 818 msixbm |= E1000_EIMS_OTHER; 819 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 820 q_vector->eims_value = msixbm; 821 break; 822 case e1000_82576: 823 /* 82576 uses a table that essentially consists of 2 columns 824 * with 8 rows. The ordering is column-major so we use the 825 * lower 3 bits as the row index, and the 4th bit as the 826 * column offset. 827 */ 828 if (rx_queue > IGB_N0_QUEUE) 829 igb_write_ivar(hw, msix_vector, 830 rx_queue & 0x7, 831 (rx_queue & 0x8) << 1); 832 if (tx_queue > IGB_N0_QUEUE) 833 igb_write_ivar(hw, msix_vector, 834 tx_queue & 0x7, 835 ((tx_queue & 0x8) << 1) + 8); 836 q_vector->eims_value = 1 << msix_vector; 837 break; 838 case e1000_82580: 839 case e1000_i350: 840 case e1000_i354: 841 case e1000_i210: 842 case e1000_i211: 843 /* On 82580 and newer adapters the scheme is similar to 82576 844 * however instead of ordering column-major we have things 845 * ordered row-major. So we traverse the table by using 846 * bit 0 as the column offset, and the remaining bits as the 847 * row index. 848 */ 849 if (rx_queue > IGB_N0_QUEUE) 850 igb_write_ivar(hw, msix_vector, 851 rx_queue >> 1, 852 (rx_queue & 0x1) << 4); 853 if (tx_queue > IGB_N0_QUEUE) 854 igb_write_ivar(hw, msix_vector, 855 tx_queue >> 1, 856 ((tx_queue & 0x1) << 4) + 8); 857 q_vector->eims_value = 1 << msix_vector; 858 break; 859 default: 860 BUG(); 861 break; 862 } 863 864 /* add q_vector eims value to global eims_enable_mask */ 865 adapter->eims_enable_mask |= q_vector->eims_value; 866 867 /* configure q_vector to set itr on first interrupt */ 868 q_vector->set_itr = 1; 869} 870 871/** 872 * igb_configure_msix - Configure MSI-X hardware 873 * @adapter: board private structure to initialize 874 * 875 * igb_configure_msix sets up the hardware to properly 876 * generate MSI-X interrupts. 877 **/ 878static void igb_configure_msix(struct igb_adapter *adapter) 879{ 880 u32 tmp; 881 int i, vector = 0; 882 struct e1000_hw *hw = &adapter->hw; 883 884 adapter->eims_enable_mask = 0; 885 886 /* set vector for other causes, i.e. link changes */ 887 switch (hw->mac.type) { 888 case e1000_82575: 889 tmp = rd32(E1000_CTRL_EXT); 890 /* enable MSI-X PBA support*/ 891 tmp |= E1000_CTRL_EXT_PBA_CLR; 892 893 /* Auto-Mask interrupts upon ICR read. */ 894 tmp |= E1000_CTRL_EXT_EIAME; 895 tmp |= E1000_CTRL_EXT_IRCA; 896 897 wr32(E1000_CTRL_EXT, tmp); 898 899 /* enable msix_other interrupt */ 900 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 901 adapter->eims_other = E1000_EIMS_OTHER; 902 903 break; 904 905 case e1000_82576: 906 case e1000_82580: 907 case e1000_i350: 908 case e1000_i354: 909 case e1000_i210: 910 case e1000_i211: 911 /* Turn on MSI-X capability first, or our settings 912 * won't stick. And it will take days to debug. 913 */ 914 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 915 E1000_GPIE_PBA | E1000_GPIE_EIAME | 916 E1000_GPIE_NSICR); 917 918 /* enable msix_other interrupt */ 919 adapter->eims_other = 1 << vector; 920 tmp = (vector++ | E1000_IVAR_VALID) << 8; 921 922 wr32(E1000_IVAR_MISC, tmp); 923 break; 924 default: 925 /* do nothing, since nothing else supports MSI-X */ 926 break; 927 } /* switch (hw->mac.type) */ 928 929 adapter->eims_enable_mask |= adapter->eims_other; 930 931 for (i = 0; i < adapter->num_q_vectors; i++) 932 igb_assign_vector(adapter->q_vector[i], vector++); 933 934 wrfl(); 935} 936 937/** 938 * igb_request_msix - Initialize MSI-X interrupts 939 * @adapter: board private structure to initialize 940 * 941 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 942 * kernel. 943 **/ 944static int igb_request_msix(struct igb_adapter *adapter) 945{ 946 struct net_device *netdev = adapter->netdev; 947 struct e1000_hw *hw = &adapter->hw; 948 int i, err = 0, vector = 0, free_vector = 0; 949 950 err = request_irq(adapter->msix_entries[vector].vector, 951 igb_msix_other, 0, netdev->name, adapter); 952 if (err) 953 goto err_out; 954 955 for (i = 0; i < adapter->num_q_vectors; i++) { 956 struct igb_q_vector *q_vector = adapter->q_vector[i]; 957 958 vector++; 959 960 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 961 962 if (q_vector->rx.ring && q_vector->tx.ring) 963 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 964 q_vector->rx.ring->queue_index); 965 else if (q_vector->tx.ring) 966 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 967 q_vector->tx.ring->queue_index); 968 else if (q_vector->rx.ring) 969 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 970 q_vector->rx.ring->queue_index); 971 else 972 sprintf(q_vector->name, "%s-unused", netdev->name); 973 974 err = request_irq(adapter->msix_entries[vector].vector, 975 igb_msix_ring, 0, q_vector->name, 976 q_vector); 977 if (err) 978 goto err_free; 979 } 980 981 igb_configure_msix(adapter); 982 return 0; 983 984err_free: 985 /* free already assigned IRQs */ 986 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 987 988 vector--; 989 for (i = 0; i < vector; i++) { 990 free_irq(adapter->msix_entries[free_vector++].vector, 991 adapter->q_vector[i]); 992 } 993err_out: 994 return err; 995} 996 997/** 998 * igb_free_q_vector - Free memory allocated for specific interrupt vector 999 * @adapter: board private structure to initialize 1000 * @v_idx: Index of vector to be freed 1001 * 1002 * This function frees the memory allocated to the q_vector. 1003 **/ 1004static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1005{ 1006 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1007 1008 adapter->q_vector[v_idx] = NULL; 1009 1010 /* igb_get_stats64() might access the rings on this vector, 1011 * we must wait a grace period before freeing it. 1012 */ 1013 kfree_rcu(q_vector, rcu); 1014} 1015 1016/** 1017 * igb_reset_q_vector - Reset config for interrupt vector 1018 * @adapter: board private structure to initialize 1019 * @v_idx: Index of vector to be reset 1020 * 1021 * If NAPI is enabled it will delete any references to the 1022 * NAPI struct. This is preparation for igb_free_q_vector. 1023 **/ 1024static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1025{ 1026 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1027 1028 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1029 * allocated. So, q_vector is NULL so we should stop here. 1030 */ 1031 if (!q_vector) 1032 return; 1033 1034 if (q_vector->tx.ring) 1035 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1036 1037 if (q_vector->rx.ring) 1038 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; 1039 1040 netif_napi_del(&q_vector->napi); 1041 1042} 1043 1044static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1045{ 1046 int v_idx = adapter->num_q_vectors; 1047 1048 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1049 pci_disable_msix(adapter->pdev); 1050 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1051 pci_disable_msi(adapter->pdev); 1052 1053 while (v_idx--) 1054 igb_reset_q_vector(adapter, v_idx); 1055} 1056 1057/** 1058 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1059 * @adapter: board private structure to initialize 1060 * 1061 * This function frees the memory allocated to the q_vectors. In addition if 1062 * NAPI is enabled it will delete any references to the NAPI struct prior 1063 * to freeing the q_vector. 1064 **/ 1065static void igb_free_q_vectors(struct igb_adapter *adapter) 1066{ 1067 int v_idx = adapter->num_q_vectors; 1068 1069 adapter->num_tx_queues = 0; 1070 adapter->num_rx_queues = 0; 1071 adapter->num_q_vectors = 0; 1072 1073 while (v_idx--) { 1074 igb_reset_q_vector(adapter, v_idx); 1075 igb_free_q_vector(adapter, v_idx); 1076 } 1077} 1078 1079/** 1080 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1081 * @adapter: board private structure to initialize 1082 * 1083 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1084 * MSI-X interrupts allocated. 1085 */ 1086static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1087{ 1088 igb_free_q_vectors(adapter); 1089 igb_reset_interrupt_capability(adapter); 1090} 1091 1092/** 1093 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1094 * @adapter: board private structure to initialize 1095 * @msix: boolean value of MSIX capability 1096 * 1097 * Attempt to configure interrupts using the best available 1098 * capabilities of the hardware and kernel. 1099 **/ 1100static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1101{ 1102 int err; 1103 int numvecs, i; 1104 1105 if (!msix) 1106 goto msi_only; 1107 adapter->flags |= IGB_FLAG_HAS_MSIX; 1108 1109 /* Number of supported queues. */ 1110 adapter->num_rx_queues = adapter->rss_queues; 1111 if (adapter->vfs_allocated_count) 1112 adapter->num_tx_queues = 1; 1113 else 1114 adapter->num_tx_queues = adapter->rss_queues; 1115 1116 /* start with one vector for every Rx queue */ 1117 numvecs = adapter->num_rx_queues; 1118 1119 /* if Tx handler is separate add 1 for every Tx queue */ 1120 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1121 numvecs += adapter->num_tx_queues; 1122 1123 /* store the number of vectors reserved for queues */ 1124 adapter->num_q_vectors = numvecs; 1125 1126 /* add 1 vector for link status interrupts */ 1127 numvecs++; 1128 for (i = 0; i < numvecs; i++) 1129 adapter->msix_entries[i].entry = i; 1130 1131 err = pci_enable_msix_range(adapter->pdev, 1132 adapter->msix_entries, 1133 numvecs, 1134 numvecs); 1135 if (err > 0) 1136 return; 1137 1138 igb_reset_interrupt_capability(adapter); 1139 1140 /* If we can't do MSI-X, try MSI */ 1141msi_only: 1142 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1143#ifdef CONFIG_PCI_IOV 1144 /* disable SR-IOV for non MSI-X configurations */ 1145 if (adapter->vf_data) { 1146 struct e1000_hw *hw = &adapter->hw; 1147 /* disable iov and allow time for transactions to clear */ 1148 pci_disable_sriov(adapter->pdev); 1149 msleep(500); 1150 1151 kfree(adapter->vf_data); 1152 adapter->vf_data = NULL; 1153 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1154 wrfl(); 1155 msleep(100); 1156 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1157 } 1158#endif 1159 adapter->vfs_allocated_count = 0; 1160 adapter->rss_queues = 1; 1161 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1162 adapter->num_rx_queues = 1; 1163 adapter->num_tx_queues = 1; 1164 adapter->num_q_vectors = 1; 1165 if (!pci_enable_msi(adapter->pdev)) 1166 adapter->flags |= IGB_FLAG_HAS_MSI; 1167} 1168 1169static void igb_add_ring(struct igb_ring *ring, 1170 struct igb_ring_container *head) 1171{ 1172 head->ring = ring; 1173 head->count++; 1174} 1175 1176/** 1177 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1178 * @adapter: board private structure to initialize 1179 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1180 * @v_idx: index of vector in adapter struct 1181 * @txr_count: total number of Tx rings to allocate 1182 * @txr_idx: index of first Tx ring to allocate 1183 * @rxr_count: total number of Rx rings to allocate 1184 * @rxr_idx: index of first Rx ring to allocate 1185 * 1186 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1187 **/ 1188static int igb_alloc_q_vector(struct igb_adapter *adapter, 1189 int v_count, int v_idx, 1190 int txr_count, int txr_idx, 1191 int rxr_count, int rxr_idx) 1192{ 1193 struct igb_q_vector *q_vector; 1194 struct igb_ring *ring; 1195 int ring_count, size; 1196 1197 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1198 if (txr_count > 1 || rxr_count > 1) 1199 return -ENOMEM; 1200 1201 ring_count = txr_count + rxr_count; 1202 size = sizeof(struct igb_q_vector) + 1203 (sizeof(struct igb_ring) * ring_count); 1204 1205 /* allocate q_vector and rings */ 1206 q_vector = adapter->q_vector[v_idx]; 1207 if (!q_vector) 1208 q_vector = kzalloc(size, GFP_KERNEL); 1209 if (!q_vector) 1210 return -ENOMEM; 1211 1212 /* initialize NAPI */ 1213 netif_napi_add(adapter->netdev, &q_vector->napi, 1214 igb_poll, 64); 1215 1216 /* tie q_vector and adapter together */ 1217 adapter->q_vector[v_idx] = q_vector; 1218 q_vector->adapter = adapter; 1219 1220 /* initialize work limits */ 1221 q_vector->tx.work_limit = adapter->tx_work_limit; 1222 1223 /* initialize ITR configuration */ 1224 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); 1225 q_vector->itr_val = IGB_START_ITR; 1226 1227 /* initialize pointer to rings */ 1228 ring = q_vector->ring; 1229 1230 /* intialize ITR */ 1231 if (rxr_count) { 1232 /* rx or rx/tx vector */ 1233 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1234 q_vector->itr_val = adapter->rx_itr_setting; 1235 } else { 1236 /* tx only vector */ 1237 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1238 q_vector->itr_val = adapter->tx_itr_setting; 1239 } 1240 1241 if (txr_count) { 1242 /* assign generic ring traits */ 1243 ring->dev = &adapter->pdev->dev; 1244 ring->netdev = adapter->netdev; 1245 1246 /* configure backlink on ring */ 1247 ring->q_vector = q_vector; 1248 1249 /* update q_vector Tx values */ 1250 igb_add_ring(ring, &q_vector->tx); 1251 1252 /* For 82575, context index must be unique per ring. */ 1253 if (adapter->hw.mac.type == e1000_82575) 1254 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1255 1256 /* apply Tx specific ring traits */ 1257 ring->count = adapter->tx_ring_count; 1258 ring->queue_index = txr_idx; 1259 1260 u64_stats_init(&ring->tx_syncp); 1261 u64_stats_init(&ring->tx_syncp2); 1262 1263 /* assign ring to adapter */ 1264 adapter->tx_ring[txr_idx] = ring; 1265 1266 /* push pointer to next ring */ 1267 ring++; 1268 } 1269 1270 if (rxr_count) { 1271 /* assign generic ring traits */ 1272 ring->dev = &adapter->pdev->dev; 1273 ring->netdev = adapter->netdev; 1274 1275 /* configure backlink on ring */ 1276 ring->q_vector = q_vector; 1277 1278 /* update q_vector Rx values */ 1279 igb_add_ring(ring, &q_vector->rx); 1280 1281 /* set flag indicating ring supports SCTP checksum offload */ 1282 if (adapter->hw.mac.type >= e1000_82576) 1283 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1284 1285 /* On i350, i354, i210, and i211, loopback VLAN packets 1286 * have the tag byte-swapped. 1287 */ 1288 if (adapter->hw.mac.type >= e1000_i350) 1289 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1290 1291 /* apply Rx specific ring traits */ 1292 ring->count = adapter->rx_ring_count; 1293 ring->queue_index = rxr_idx; 1294 1295 u64_stats_init(&ring->rx_syncp); 1296 1297 /* assign ring to adapter */ 1298 adapter->rx_ring[rxr_idx] = ring; 1299 } 1300 1301 return 0; 1302} 1303 1304 1305/** 1306 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1307 * @adapter: board private structure to initialize 1308 * 1309 * We allocate one q_vector per queue interrupt. If allocation fails we 1310 * return -ENOMEM. 1311 **/ 1312static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1313{ 1314 int q_vectors = adapter->num_q_vectors; 1315 int rxr_remaining = adapter->num_rx_queues; 1316 int txr_remaining = adapter->num_tx_queues; 1317 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1318 int err; 1319 1320 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1321 for (; rxr_remaining; v_idx++) { 1322 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1323 0, 0, 1, rxr_idx); 1324 1325 if (err) 1326 goto err_out; 1327 1328 /* update counts and index */ 1329 rxr_remaining--; 1330 rxr_idx++; 1331 } 1332 } 1333 1334 for (; v_idx < q_vectors; v_idx++) { 1335 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1336 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1337 1338 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1339 tqpv, txr_idx, rqpv, rxr_idx); 1340 1341 if (err) 1342 goto err_out; 1343 1344 /* update counts and index */ 1345 rxr_remaining -= rqpv; 1346 txr_remaining -= tqpv; 1347 rxr_idx++; 1348 txr_idx++; 1349 } 1350 1351 return 0; 1352 1353err_out: 1354 adapter->num_tx_queues = 0; 1355 adapter->num_rx_queues = 0; 1356 adapter->num_q_vectors = 0; 1357 1358 while (v_idx--) 1359 igb_free_q_vector(adapter, v_idx); 1360 1361 return -ENOMEM; 1362} 1363 1364/** 1365 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1366 * @adapter: board private structure to initialize 1367 * @msix: boolean value of MSIX capability 1368 * 1369 * This function initializes the interrupts and allocates all of the queues. 1370 **/ 1371static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1372{ 1373 struct pci_dev *pdev = adapter->pdev; 1374 int err; 1375 1376 igb_set_interrupt_capability(adapter, msix); 1377 1378 err = igb_alloc_q_vectors(adapter); 1379 if (err) { 1380 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1381 goto err_alloc_q_vectors; 1382 } 1383 1384 igb_cache_ring_register(adapter); 1385 1386 return 0; 1387 1388err_alloc_q_vectors: 1389 igb_reset_interrupt_capability(adapter); 1390 return err; 1391} 1392 1393/** 1394 * igb_request_irq - initialize interrupts 1395 * @adapter: board private structure to initialize 1396 * 1397 * Attempts to configure interrupts using the best available 1398 * capabilities of the hardware and kernel. 1399 **/ 1400static int igb_request_irq(struct igb_adapter *adapter) 1401{ 1402 struct net_device *netdev = adapter->netdev; 1403 struct pci_dev *pdev = adapter->pdev; 1404 int err = 0; 1405 1406 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1407 err = igb_request_msix(adapter); 1408 if (!err) 1409 goto request_done; 1410 /* fall back to MSI */ 1411 igb_free_all_tx_resources(adapter); 1412 igb_free_all_rx_resources(adapter); 1413 1414 igb_clear_interrupt_scheme(adapter); 1415 err = igb_init_interrupt_scheme(adapter, false); 1416 if (err) 1417 goto request_done; 1418 1419 igb_setup_all_tx_resources(adapter); 1420 igb_setup_all_rx_resources(adapter); 1421 igb_configure(adapter); 1422 } 1423 1424 igb_assign_vector(adapter->q_vector[0], 0); 1425 1426 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1427 err = request_irq(pdev->irq, igb_intr_msi, 0, 1428 netdev->name, adapter); 1429 if (!err) 1430 goto request_done; 1431 1432 /* fall back to legacy interrupts */ 1433 igb_reset_interrupt_capability(adapter); 1434 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1435 } 1436 1437 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1438 netdev->name, adapter); 1439 1440 if (err) 1441 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1442 err); 1443 1444request_done: 1445 return err; 1446} 1447 1448static void igb_free_irq(struct igb_adapter *adapter) 1449{ 1450 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1451 int vector = 0, i; 1452 1453 free_irq(adapter->msix_entries[vector++].vector, adapter); 1454 1455 for (i = 0; i < adapter->num_q_vectors; i++) 1456 free_irq(adapter->msix_entries[vector++].vector, 1457 adapter->q_vector[i]); 1458 } else { 1459 free_irq(adapter->pdev->irq, adapter); 1460 } 1461} 1462 1463/** 1464 * igb_irq_disable - Mask off interrupt generation on the NIC 1465 * @adapter: board private structure 1466 **/ 1467static void igb_irq_disable(struct igb_adapter *adapter) 1468{ 1469 struct e1000_hw *hw = &adapter->hw; 1470 1471 /* we need to be careful when disabling interrupts. The VFs are also 1472 * mapped into these registers and so clearing the bits can cause 1473 * issues on the VF drivers so we only need to clear what we set 1474 */ 1475 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1476 u32 regval = rd32(E1000_EIAM); 1477 1478 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1479 wr32(E1000_EIMC, adapter->eims_enable_mask); 1480 regval = rd32(E1000_EIAC); 1481 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1482 } 1483 1484 wr32(E1000_IAM, 0); 1485 wr32(E1000_IMC, ~0); 1486 wrfl(); 1487 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1488 int i; 1489 1490 for (i = 0; i < adapter->num_q_vectors; i++) 1491 synchronize_irq(adapter->msix_entries[i].vector); 1492 } else { 1493 synchronize_irq(adapter->pdev->irq); 1494 } 1495} 1496 1497/** 1498 * igb_irq_enable - Enable default interrupt generation settings 1499 * @adapter: board private structure 1500 **/ 1501static void igb_irq_enable(struct igb_adapter *adapter) 1502{ 1503 struct e1000_hw *hw = &adapter->hw; 1504 1505 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1506 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1507 u32 regval = rd32(E1000_EIAC); 1508 1509 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1510 regval = rd32(E1000_EIAM); 1511 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1512 wr32(E1000_EIMS, adapter->eims_enable_mask); 1513 if (adapter->vfs_allocated_count) { 1514 wr32(E1000_MBVFIMR, 0xFF); 1515 ims |= E1000_IMS_VMMB; 1516 } 1517 wr32(E1000_IMS, ims); 1518 } else { 1519 wr32(E1000_IMS, IMS_ENABLE_MASK | 1520 E1000_IMS_DRSTA); 1521 wr32(E1000_IAM, IMS_ENABLE_MASK | 1522 E1000_IMS_DRSTA); 1523 } 1524} 1525 1526static void igb_update_mng_vlan(struct igb_adapter *adapter) 1527{ 1528 struct e1000_hw *hw = &adapter->hw; 1529 u16 vid = adapter->hw.mng_cookie.vlan_id; 1530 u16 old_vid = adapter->mng_vlan_id; 1531 1532 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1533 /* add VID to filter table */ 1534 igb_vfta_set(hw, vid, true); 1535 adapter->mng_vlan_id = vid; 1536 } else { 1537 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1538 } 1539 1540 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1541 (vid != old_vid) && 1542 !test_bit(old_vid, adapter->active_vlans)) { 1543 /* remove VID from filter table */ 1544 igb_vfta_set(hw, old_vid, false); 1545 } 1546} 1547 1548/** 1549 * igb_release_hw_control - release control of the h/w to f/w 1550 * @adapter: address of board private structure 1551 * 1552 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1553 * For ASF and Pass Through versions of f/w this means that the 1554 * driver is no longer loaded. 1555 **/ 1556static void igb_release_hw_control(struct igb_adapter *adapter) 1557{ 1558 struct e1000_hw *hw = &adapter->hw; 1559 u32 ctrl_ext; 1560 1561 /* Let firmware take over control of h/w */ 1562 ctrl_ext = rd32(E1000_CTRL_EXT); 1563 wr32(E1000_CTRL_EXT, 1564 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1565} 1566 1567/** 1568 * igb_get_hw_control - get control of the h/w from f/w 1569 * @adapter: address of board private structure 1570 * 1571 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1572 * For ASF and Pass Through versions of f/w this means that 1573 * the driver is loaded. 1574 **/ 1575static void igb_get_hw_control(struct igb_adapter *adapter) 1576{ 1577 struct e1000_hw *hw = &adapter->hw; 1578 u32 ctrl_ext; 1579 1580 /* Let firmware know the driver has taken over */ 1581 ctrl_ext = rd32(E1000_CTRL_EXT); 1582 wr32(E1000_CTRL_EXT, 1583 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1584} 1585 1586/** 1587 * igb_configure - configure the hardware for RX and TX 1588 * @adapter: private board structure 1589 **/ 1590static void igb_configure(struct igb_adapter *adapter) 1591{ 1592 struct net_device *netdev = adapter->netdev; 1593 int i; 1594 1595 igb_get_hw_control(adapter); 1596 igb_set_rx_mode(netdev); 1597 1598 igb_restore_vlan(adapter); 1599 1600 igb_setup_tctl(adapter); 1601 igb_setup_mrqc(adapter); 1602 igb_setup_rctl(adapter); 1603 1604 igb_configure_tx(adapter); 1605 igb_configure_rx(adapter); 1606 1607 igb_rx_fifo_flush_82575(&adapter->hw); 1608 1609 /* call igb_desc_unused which always leaves 1610 * at least 1 descriptor unused to make sure 1611 * next_to_use != next_to_clean 1612 */ 1613 for (i = 0; i < adapter->num_rx_queues; i++) { 1614 struct igb_ring *ring = adapter->rx_ring[i]; 1615 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1616 } 1617} 1618 1619/** 1620 * igb_power_up_link - Power up the phy/serdes link 1621 * @adapter: address of board private structure 1622 **/ 1623void igb_power_up_link(struct igb_adapter *adapter) 1624{ 1625 igb_reset_phy(&adapter->hw); 1626 1627 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1628 igb_power_up_phy_copper(&adapter->hw); 1629 else 1630 igb_power_up_serdes_link_82575(&adapter->hw); 1631} 1632 1633/** 1634 * igb_power_down_link - Power down the phy/serdes link 1635 * @adapter: address of board private structure 1636 */ 1637static void igb_power_down_link(struct igb_adapter *adapter) 1638{ 1639 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1640 igb_power_down_phy_copper_82575(&adapter->hw); 1641 else 1642 igb_shutdown_serdes_link_82575(&adapter->hw); 1643} 1644 1645/** 1646 * Detect and switch function for Media Auto Sense 1647 * @adapter: address of the board private structure 1648 **/ 1649static void igb_check_swap_media(struct igb_adapter *adapter) 1650{ 1651 struct e1000_hw *hw = &adapter->hw; 1652 u32 ctrl_ext, connsw; 1653 bool swap_now = false; 1654 1655 ctrl_ext = rd32(E1000_CTRL_EXT); 1656 connsw = rd32(E1000_CONNSW); 1657 1658 /* need to live swap if current media is copper and we have fiber/serdes 1659 * to go to. 1660 */ 1661 1662 if ((hw->phy.media_type == e1000_media_type_copper) && 1663 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1664 swap_now = true; 1665 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1666 /* copper signal takes time to appear */ 1667 if (adapter->copper_tries < 4) { 1668 adapter->copper_tries++; 1669 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1670 wr32(E1000_CONNSW, connsw); 1671 return; 1672 } else { 1673 adapter->copper_tries = 0; 1674 if ((connsw & E1000_CONNSW_PHYSD) && 1675 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1676 swap_now = true; 1677 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1678 wr32(E1000_CONNSW, connsw); 1679 } 1680 } 1681 } 1682 1683 if (!swap_now) 1684 return; 1685 1686 switch (hw->phy.media_type) { 1687 case e1000_media_type_copper: 1688 netdev_info(adapter->netdev, 1689 "MAS: changing media to fiber/serdes\n"); 1690 ctrl_ext |= 1691 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1692 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1693 adapter->copper_tries = 0; 1694 break; 1695 case e1000_media_type_internal_serdes: 1696 case e1000_media_type_fiber: 1697 netdev_info(adapter->netdev, 1698 "MAS: changing media to copper\n"); 1699 ctrl_ext &= 1700 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1701 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1702 break; 1703 default: 1704 /* shouldn't get here during regular operation */ 1705 netdev_err(adapter->netdev, 1706 "AMS: Invalid media type found, returning\n"); 1707 break; 1708 } 1709 wr32(E1000_CTRL_EXT, ctrl_ext); 1710} 1711 1712/** 1713 * igb_up - Open the interface and prepare it to handle traffic 1714 * @adapter: board private structure 1715 **/ 1716int igb_up(struct igb_adapter *adapter) 1717{ 1718 struct e1000_hw *hw = &adapter->hw; 1719 int i; 1720 1721 /* hardware has been reset, we need to reload some things */ 1722 igb_configure(adapter); 1723 1724 clear_bit(__IGB_DOWN, &adapter->state); 1725 1726 for (i = 0; i < adapter->num_q_vectors; i++) 1727 napi_enable(&(adapter->q_vector[i]->napi)); 1728 1729 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1730 igb_configure_msix(adapter); 1731 else 1732 igb_assign_vector(adapter->q_vector[0], 0); 1733 1734 /* Clear any pending interrupts. */ 1735 rd32(E1000_ICR); 1736 igb_irq_enable(adapter); 1737 1738 /* notify VFs that reset has been completed */ 1739 if (adapter->vfs_allocated_count) { 1740 u32 reg_data = rd32(E1000_CTRL_EXT); 1741 1742 reg_data |= E1000_CTRL_EXT_PFRSTD; 1743 wr32(E1000_CTRL_EXT, reg_data); 1744 } 1745 1746 netif_tx_start_all_queues(adapter->netdev); 1747 1748 /* start the watchdog. */ 1749 hw->mac.get_link_status = 1; 1750 schedule_work(&adapter->watchdog_task); 1751 1752 if ((adapter->flags & IGB_FLAG_EEE) && 1753 (!hw->dev_spec._82575.eee_disable)) 1754 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1755 1756 return 0; 1757} 1758 1759void igb_down(struct igb_adapter *adapter) 1760{ 1761 struct net_device *netdev = adapter->netdev; 1762 struct e1000_hw *hw = &adapter->hw; 1763 u32 tctl, rctl; 1764 int i; 1765 1766 /* signal that we're down so the interrupt handler does not 1767 * reschedule our watchdog timer 1768 */ 1769 set_bit(__IGB_DOWN, &adapter->state); 1770 1771 /* disable receives in the hardware */ 1772 rctl = rd32(E1000_RCTL); 1773 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1774 /* flush and sleep below */ 1775 1776 netif_tx_stop_all_queues(netdev); 1777 1778 /* disable transmits in the hardware */ 1779 tctl = rd32(E1000_TCTL); 1780 tctl &= ~E1000_TCTL_EN; 1781 wr32(E1000_TCTL, tctl); 1782 /* flush both disables and wait for them to finish */ 1783 wrfl(); 1784 msleep(10); 1785 1786 igb_irq_disable(adapter); 1787 1788 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1789 1790 for (i = 0; i < adapter->num_q_vectors; i++) { 1791 napi_synchronize(&(adapter->q_vector[i]->napi)); 1792 napi_disable(&(adapter->q_vector[i]->napi)); 1793 } 1794 1795 1796 del_timer_sync(&adapter->watchdog_timer); 1797 del_timer_sync(&adapter->phy_info_timer); 1798 1799 netif_carrier_off(netdev); 1800 1801 /* record the stats before reset*/ 1802 spin_lock(&adapter->stats64_lock); 1803 igb_update_stats(adapter, &adapter->stats64); 1804 spin_unlock(&adapter->stats64_lock); 1805 1806 adapter->link_speed = 0; 1807 adapter->link_duplex = 0; 1808 1809 if (!pci_channel_offline(adapter->pdev)) 1810 igb_reset(adapter); 1811 igb_clean_all_tx_rings(adapter); 1812 igb_clean_all_rx_rings(adapter); 1813#ifdef CONFIG_IGB_DCA 1814 1815 /* since we reset the hardware DCA settings were cleared */ 1816 igb_setup_dca(adapter); 1817#endif 1818} 1819 1820void igb_reinit_locked(struct igb_adapter *adapter) 1821{ 1822 WARN_ON(in_interrupt()); 1823 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1824 msleep(1); 1825 igb_down(adapter); 1826 igb_up(adapter); 1827 clear_bit(__IGB_RESETTING, &adapter->state); 1828} 1829 1830/** igb_enable_mas - Media Autosense re-enable after swap 1831 * 1832 * @adapter: adapter struct 1833 **/ 1834static s32 igb_enable_mas(struct igb_adapter *adapter) 1835{ 1836 struct e1000_hw *hw = &adapter->hw; 1837 u32 connsw; 1838 s32 ret_val = 0; 1839 1840 connsw = rd32(E1000_CONNSW); 1841 if (!(hw->phy.media_type == e1000_media_type_copper)) 1842 return ret_val; 1843 1844 /* configure for SerDes media detect */ 1845 if (!(connsw & E1000_CONNSW_SERDESD)) { 1846 connsw |= E1000_CONNSW_ENRGSRC; 1847 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1848 wr32(E1000_CONNSW, connsw); 1849 wrfl(); 1850 } else if (connsw & E1000_CONNSW_SERDESD) { 1851 /* already SerDes, no need to enable anything */ 1852 return ret_val; 1853 } else { 1854 netdev_info(adapter->netdev, 1855 "MAS: Unable to configure feature, disabling..\n"); 1856 adapter->flags &= ~IGB_FLAG_MAS_ENABLE; 1857 } 1858 return ret_val; 1859} 1860 1861void igb_reset(struct igb_adapter *adapter) 1862{ 1863 struct pci_dev *pdev = adapter->pdev; 1864 struct e1000_hw *hw = &adapter->hw; 1865 struct e1000_mac_info *mac = &hw->mac; 1866 struct e1000_fc_info *fc = &hw->fc; 1867 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; 1868 1869 /* Repartition Pba for greater than 9k mtu 1870 * To take effect CTRL.RST is required. 1871 */ 1872 switch (mac->type) { 1873 case e1000_i350: 1874 case e1000_i354: 1875 case e1000_82580: 1876 pba = rd32(E1000_RXPBS); 1877 pba = igb_rxpbs_adjust_82580(pba); 1878 break; 1879 case e1000_82576: 1880 pba = rd32(E1000_RXPBS); 1881 pba &= E1000_RXPBS_SIZE_MASK_82576; 1882 break; 1883 case e1000_82575: 1884 case e1000_i210: 1885 case e1000_i211: 1886 default: 1887 pba = E1000_PBA_34K; 1888 break; 1889 } 1890 1891 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1892 (mac->type < e1000_82576)) { 1893 /* adjust PBA for jumbo frames */ 1894 wr32(E1000_PBA, pba); 1895 1896 /* To maintain wire speed transmits, the Tx FIFO should be 1897 * large enough to accommodate two full transmit packets, 1898 * rounded up to the next 1KB and expressed in KB. Likewise, 1899 * the Rx FIFO should be large enough to accommodate at least 1900 * one full receive packet and is similarly rounded up and 1901 * expressed in KB. 1902 */ 1903 pba = rd32(E1000_PBA); 1904 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1905 tx_space = pba >> 16; 1906 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1907 pba &= 0xffff; 1908 /* the Tx fifo also stores 16 bytes of information about the Tx 1909 * but don't include ethernet FCS because hardware appends it 1910 */ 1911 min_tx_space = (adapter->max_frame_size + 1912 sizeof(union e1000_adv_tx_desc) - 1913 ETH_FCS_LEN) * 2; 1914 min_tx_space = ALIGN(min_tx_space, 1024); 1915 min_tx_space >>= 10; 1916 /* software strips receive CRC, so leave room for it */ 1917 min_rx_space = adapter->max_frame_size; 1918 min_rx_space = ALIGN(min_rx_space, 1024); 1919 min_rx_space >>= 10; 1920 1921 /* If current Tx allocation is less than the min Tx FIFO size, 1922 * and the min Tx FIFO size is less than the current Rx FIFO 1923 * allocation, take space away from current Rx allocation 1924 */ 1925 if (tx_space < min_tx_space && 1926 ((min_tx_space - tx_space) < pba)) { 1927 pba = pba - (min_tx_space - tx_space); 1928 1929 /* if short on Rx space, Rx wins and must trump Tx 1930 * adjustment 1931 */ 1932 if (pba < min_rx_space) 1933 pba = min_rx_space; 1934 } 1935 wr32(E1000_PBA, pba); 1936 } 1937 1938 /* flow control settings */ 1939 /* The high water mark must be low enough to fit one full frame 1940 * (or the size used for early receive) above it in the Rx FIFO. 1941 * Set it to the lower of: 1942 * - 90% of the Rx FIFO size, or 1943 * - the full Rx FIFO size minus one full frame 1944 */ 1945 hwm = min(((pba << 10) * 9 / 10), 1946 ((pba << 10) - 2 * adapter->max_frame_size)); 1947 1948 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1949 fc->low_water = fc->high_water - 16; 1950 fc->pause_time = 0xFFFF; 1951 fc->send_xon = 1; 1952 fc->current_mode = fc->requested_mode; 1953 1954 /* disable receive for all VFs and wait one second */ 1955 if (adapter->vfs_allocated_count) { 1956 int i; 1957 1958 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1959 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1960 1961 /* ping all the active vfs to let them know we are going down */ 1962 igb_ping_all_vfs(adapter); 1963 1964 /* disable transmits and receives */ 1965 wr32(E1000_VFRE, 0); 1966 wr32(E1000_VFTE, 0); 1967 } 1968 1969 /* Allow time for pending master requests to run */ 1970 hw->mac.ops.reset_hw(hw); 1971 wr32(E1000_WUC, 0); 1972 1973 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1974 /* need to resetup here after media swap */ 1975 adapter->ei.get_invariants(hw); 1976 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1977 } 1978 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 1979 if (igb_enable_mas(adapter)) 1980 dev_err(&pdev->dev, 1981 "Error enabling Media Auto Sense\n"); 1982 } 1983 if (hw->mac.ops.init_hw(hw)) 1984 dev_err(&pdev->dev, "Hardware Error\n"); 1985 1986 /* Flow control settings reset on hardware reset, so guarantee flow 1987 * control is off when forcing speed. 1988 */ 1989 if (!hw->mac.autoneg) 1990 igb_force_mac_fc(hw); 1991 1992 igb_init_dmac(adapter, pba); 1993#ifdef CONFIG_IGB_HWMON 1994 /* Re-initialize the thermal sensor on i350 devices. */ 1995 if (!test_bit(__IGB_DOWN, &adapter->state)) { 1996 if (mac->type == e1000_i350 && hw->bus.func == 0) { 1997 /* If present, re-initialize the external thermal sensor 1998 * interface. 1999 */ 2000 if (adapter->ets) 2001 mac->ops.init_thermal_sensor_thresh(hw); 2002 } 2003 } 2004#endif 2005 /* Re-establish EEE setting */ 2006 if (hw->phy.media_type == e1000_media_type_copper) { 2007 switch (mac->type) { 2008 case e1000_i350: 2009 case e1000_i210: 2010 case e1000_i211: 2011 igb_set_eee_i350(hw); 2012 break; 2013 case e1000_i354: 2014 igb_set_eee_i354(hw); 2015 break; 2016 default: 2017 break; 2018 } 2019 } 2020 if (!netif_running(adapter->netdev)) 2021 igb_power_down_link(adapter); 2022 2023 igb_update_mng_vlan(adapter); 2024 2025 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2026 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2027 2028 /* Re-enable PTP, where applicable. */ 2029 igb_ptp_reset(adapter); 2030 2031 igb_get_phy_info(hw); 2032} 2033 2034static netdev_features_t igb_fix_features(struct net_device *netdev, 2035 netdev_features_t features) 2036{ 2037 /* Since there is no support for separate Rx/Tx vlan accel 2038 * enable/disable make sure Tx flag is always in same state as Rx. 2039 */ 2040 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2041 features |= NETIF_F_HW_VLAN_CTAG_TX; 2042 else 2043 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2044 2045 return features; 2046} 2047 2048static int igb_set_features(struct net_device *netdev, 2049 netdev_features_t features) 2050{ 2051 netdev_features_t changed = netdev->features ^ features; 2052 struct igb_adapter *adapter = netdev_priv(netdev); 2053 2054 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2055 igb_vlan_mode(netdev, features); 2056 2057 if (!(changed & NETIF_F_RXALL)) 2058 return 0; 2059 2060 netdev->features = features; 2061 2062 if (netif_running(netdev)) 2063 igb_reinit_locked(adapter); 2064 else 2065 igb_reset(adapter); 2066 2067 return 0; 2068} 2069 2070static const struct net_device_ops igb_netdev_ops = { 2071 .ndo_open = igb_open, 2072 .ndo_stop = igb_close, 2073 .ndo_start_xmit = igb_xmit_frame, 2074 .ndo_get_stats64 = igb_get_stats64, 2075 .ndo_set_rx_mode = igb_set_rx_mode, 2076 .ndo_set_mac_address = igb_set_mac, 2077 .ndo_change_mtu = igb_change_mtu, 2078 .ndo_do_ioctl = igb_ioctl, 2079 .ndo_tx_timeout = igb_tx_timeout, 2080 .ndo_validate_addr = eth_validate_addr, 2081 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2082 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2083 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2084 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2085 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, 2086 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2087 .ndo_get_vf_config = igb_ndo_get_vf_config, 2088#ifdef CONFIG_NET_POLL_CONTROLLER 2089 .ndo_poll_controller = igb_netpoll, 2090#endif 2091 .ndo_fix_features = igb_fix_features, 2092 .ndo_set_features = igb_set_features, 2093}; 2094 2095/** 2096 * igb_set_fw_version - Configure version string for ethtool 2097 * @adapter: adapter struct 2098 **/ 2099void igb_set_fw_version(struct igb_adapter *adapter) 2100{ 2101 struct e1000_hw *hw = &adapter->hw; 2102 struct e1000_fw_version fw; 2103 2104 igb_get_fw_version(hw, &fw); 2105 2106 switch (hw->mac.type) { 2107 case e1000_i210: 2108 case e1000_i211: 2109 if (!(igb_get_flash_presence_i210(hw))) { 2110 snprintf(adapter->fw_version, 2111 sizeof(adapter->fw_version), 2112 "%2d.%2d-%d", 2113 fw.invm_major, fw.invm_minor, 2114 fw.invm_img_type); 2115 break; 2116 } 2117 /* fall through */ 2118 default: 2119 /* if option is rom valid, display its version too */ 2120 if (fw.or_valid) { 2121 snprintf(adapter->fw_version, 2122 sizeof(adapter->fw_version), 2123 "%d.%d, 0x%08x, %d.%d.%d", 2124 fw.eep_major, fw.eep_minor, fw.etrack_id, 2125 fw.or_major, fw.or_build, fw.or_patch); 2126 /* no option rom */ 2127 } else if (fw.etrack_id != 0X0000) { 2128 snprintf(adapter->fw_version, 2129 sizeof(adapter->fw_version), 2130 "%d.%d, 0x%08x", 2131 fw.eep_major, fw.eep_minor, fw.etrack_id); 2132 } else { 2133 snprintf(adapter->fw_version, 2134 sizeof(adapter->fw_version), 2135 "%d.%d.%d", 2136 fw.eep_major, fw.eep_minor, fw.eep_build); 2137 } 2138 break; 2139 } 2140 return; 2141} 2142 2143/** 2144 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2145 * 2146 * @adapter: adapter struct 2147 **/ 2148static void igb_init_mas(struct igb_adapter *adapter) 2149{ 2150 struct e1000_hw *hw = &adapter->hw; 2151 u16 eeprom_data; 2152 2153 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2154 switch (hw->bus.func) { 2155 case E1000_FUNC_0: 2156 if (eeprom_data & IGB_MAS_ENABLE_0) { 2157 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2158 netdev_info(adapter->netdev, 2159 "MAS: Enabling Media Autosense for port %d\n", 2160 hw->bus.func); 2161 } 2162 break; 2163 case E1000_FUNC_1: 2164 if (eeprom_data & IGB_MAS_ENABLE_1) { 2165 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2166 netdev_info(adapter->netdev, 2167 "MAS: Enabling Media Autosense for port %d\n", 2168 hw->bus.func); 2169 } 2170 break; 2171 case E1000_FUNC_2: 2172 if (eeprom_data & IGB_MAS_ENABLE_2) { 2173 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2174 netdev_info(adapter->netdev, 2175 "MAS: Enabling Media Autosense for port %d\n", 2176 hw->bus.func); 2177 } 2178 break; 2179 case E1000_FUNC_3: 2180 if (eeprom_data & IGB_MAS_ENABLE_3) { 2181 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2182 netdev_info(adapter->netdev, 2183 "MAS: Enabling Media Autosense for port %d\n", 2184 hw->bus.func); 2185 } 2186 break; 2187 default: 2188 /* Shouldn't get here */ 2189 netdev_err(adapter->netdev, 2190 "MAS: Invalid port configuration, returning\n"); 2191 break; 2192 } 2193} 2194 2195/** 2196 * igb_init_i2c - Init I2C interface 2197 * @adapter: pointer to adapter structure 2198 **/ 2199static s32 igb_init_i2c(struct igb_adapter *adapter) 2200{ 2201 s32 status = E1000_SUCCESS; 2202 2203 /* I2C interface supported on i350 devices */ 2204 if (adapter->hw.mac.type != e1000_i350) 2205 return E1000_SUCCESS; 2206 2207 /* Initialize the i2c bus which is controlled by the registers. 2208 * This bus will use the i2c_algo_bit structue that implements 2209 * the protocol through toggling of the 4 bits in the register. 2210 */ 2211 adapter->i2c_adap.owner = THIS_MODULE; 2212 adapter->i2c_algo = igb_i2c_algo; 2213 adapter->i2c_algo.data = adapter; 2214 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2215 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2216 strlcpy(adapter->i2c_adap.name, "igb BB", 2217 sizeof(adapter->i2c_adap.name)); 2218 status = i2c_bit_add_bus(&adapter->i2c_adap); 2219 return status; 2220} 2221 2222/** 2223 * igb_probe - Device Initialization Routine 2224 * @pdev: PCI device information struct 2225 * @ent: entry in igb_pci_tbl 2226 * 2227 * Returns 0 on success, negative on failure 2228 * 2229 * igb_probe initializes an adapter identified by a pci_dev structure. 2230 * The OS initialization, configuring of the adapter private structure, 2231 * and a hardware reset occur. 2232 **/ 2233static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2234{ 2235 struct net_device *netdev; 2236 struct igb_adapter *adapter; 2237 struct e1000_hw *hw; 2238 u16 eeprom_data = 0; 2239 s32 ret_val; 2240 static int global_quad_port_a; /* global quad port a indication */ 2241 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2242 int err, pci_using_dac; 2243 u8 part_str[E1000_PBANUM_LENGTH]; 2244 2245 /* Catch broken hardware that put the wrong VF device ID in 2246 * the PCIe SR-IOV capability. 2247 */ 2248 if (pdev->is_virtfn) { 2249 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2250 pci_name(pdev), pdev->vendor, pdev->device); 2251 return -EINVAL; 2252 } 2253 2254 err = pci_enable_device_mem(pdev); 2255 if (err) 2256 return err; 2257 2258 pci_using_dac = 0; 2259 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2260 if (!err) { 2261 pci_using_dac = 1; 2262 } else { 2263 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2264 if (err) { 2265 dev_err(&pdev->dev, 2266 "No usable DMA configuration, aborting\n"); 2267 goto err_dma; 2268 } 2269 } 2270 2271 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 2272 IORESOURCE_MEM), 2273 igb_driver_name); 2274 if (err) 2275 goto err_pci_reg; 2276 2277 pci_enable_pcie_error_reporting(pdev); 2278 2279 pci_set_master(pdev); 2280 pci_save_state(pdev); 2281 2282 err = -ENOMEM; 2283 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2284 IGB_MAX_TX_QUEUES); 2285 if (!netdev) 2286 goto err_alloc_etherdev; 2287 2288 SET_NETDEV_DEV(netdev, &pdev->dev); 2289 2290 pci_set_drvdata(pdev, netdev); 2291 adapter = netdev_priv(netdev); 2292 adapter->netdev = netdev; 2293 adapter->pdev = pdev; 2294 hw = &adapter->hw; 2295 hw->back = adapter; 2296 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2297 2298 err = -EIO; 2299 hw->hw_addr = pci_iomap(pdev, 0, 0); 2300 if (!hw->hw_addr) 2301 goto err_ioremap; 2302 2303 netdev->netdev_ops = &igb_netdev_ops; 2304 igb_set_ethtool_ops(netdev); 2305 netdev->watchdog_timeo = 5 * HZ; 2306 2307 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2308 2309 netdev->mem_start = pci_resource_start(pdev, 0); 2310 netdev->mem_end = pci_resource_end(pdev, 0); 2311 2312 /* PCI config space info */ 2313 hw->vendor_id = pdev->vendor; 2314 hw->device_id = pdev->device; 2315 hw->revision_id = pdev->revision; 2316 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2317 hw->subsystem_device_id = pdev->subsystem_device; 2318 2319 /* Copy the default MAC, PHY and NVM function pointers */ 2320 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2321 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2322 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2323 /* Initialize skew-specific constants */ 2324 err = ei->get_invariants(hw); 2325 if (err) 2326 goto err_sw_init; 2327 2328 /* setup the private structure */ 2329 err = igb_sw_init(adapter); 2330 if (err) 2331 goto err_sw_init; 2332 2333 igb_get_bus_info_pcie(hw); 2334 2335 hw->phy.autoneg_wait_to_complete = false; 2336 2337 /* Copper options */ 2338 if (hw->phy.media_type == e1000_media_type_copper) { 2339 hw->phy.mdix = AUTO_ALL_MODES; 2340 hw->phy.disable_polarity_correction = false; 2341 hw->phy.ms_type = e1000_ms_hw_default; 2342 } 2343 2344 if (igb_check_reset_block(hw)) 2345 dev_info(&pdev->dev, 2346 "PHY reset is blocked due to SOL/IDER session.\n"); 2347 2348 /* features is initialized to 0 in allocation, it might have bits 2349 * set by igb_sw_init so we should use an or instead of an 2350 * assignment. 2351 */ 2352 netdev->features |= NETIF_F_SG | 2353 NETIF_F_IP_CSUM | 2354 NETIF_F_IPV6_CSUM | 2355 NETIF_F_TSO | 2356 NETIF_F_TSO6 | 2357 NETIF_F_RXHASH | 2358 NETIF_F_RXCSUM | 2359 NETIF_F_HW_VLAN_CTAG_RX | 2360 NETIF_F_HW_VLAN_CTAG_TX; 2361 2362 /* copy netdev features into list of user selectable features */ 2363 netdev->hw_features |= netdev->features; 2364 netdev->hw_features |= NETIF_F_RXALL; 2365 2366 /* set this bit last since it cannot be part of hw_features */ 2367 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2368 2369 netdev->vlan_features |= NETIF_F_TSO | 2370 NETIF_F_TSO6 | 2371 NETIF_F_IP_CSUM | 2372 NETIF_F_IPV6_CSUM | 2373 NETIF_F_SG; 2374 2375 netdev->priv_flags |= IFF_SUPP_NOFCS; 2376 2377 if (pci_using_dac) { 2378 netdev->features |= NETIF_F_HIGHDMA; 2379 netdev->vlan_features |= NETIF_F_HIGHDMA; 2380 } 2381 2382 if (hw->mac.type >= e1000_82576) { 2383 netdev->hw_features |= NETIF_F_SCTP_CSUM; 2384 netdev->features |= NETIF_F_SCTP_CSUM; 2385 } 2386 2387 netdev->priv_flags |= IFF_UNICAST_FLT; 2388 2389 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2390 2391 /* before reading the NVM, reset the controller to put the device in a 2392 * known good starting state 2393 */ 2394 hw->mac.ops.reset_hw(hw); 2395 2396 /* make sure the NVM is good , i211/i210 parts can have special NVM 2397 * that doesn't contain a checksum 2398 */ 2399 switch (hw->mac.type) { 2400 case e1000_i210: 2401 case e1000_i211: 2402 if (igb_get_flash_presence_i210(hw)) { 2403 if (hw->nvm.ops.validate(hw) < 0) { 2404 dev_err(&pdev->dev, 2405 "The NVM Checksum Is Not Valid\n"); 2406 err = -EIO; 2407 goto err_eeprom; 2408 } 2409 } 2410 break; 2411 default: 2412 if (hw->nvm.ops.validate(hw) < 0) { 2413 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2414 err = -EIO; 2415 goto err_eeprom; 2416 } 2417 break; 2418 } 2419 2420 /* copy the MAC address out of the NVM */ 2421 if (hw->mac.ops.read_mac_addr(hw)) 2422 dev_err(&pdev->dev, "NVM Read Error\n"); 2423 2424 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2425 2426 if (!is_valid_ether_addr(netdev->dev_addr)) { 2427 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2428 err = -EIO; 2429 goto err_eeprom; 2430 } 2431 2432 /* get firmware version for ethtool -i */ 2433 igb_set_fw_version(adapter); 2434 2435 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2436 (unsigned long) adapter); 2437 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2438 (unsigned long) adapter); 2439 2440 INIT_WORK(&adapter->reset_task, igb_reset_task); 2441 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2442 2443 /* Initialize link properties that are user-changeable */ 2444 adapter->fc_autoneg = true; 2445 hw->mac.autoneg = true; 2446 hw->phy.autoneg_advertised = 0x2f; 2447 2448 hw->fc.requested_mode = e1000_fc_default; 2449 hw->fc.current_mode = e1000_fc_default; 2450 2451 igb_validate_mdi_setting(hw); 2452 2453 /* By default, support wake on port A */ 2454 if (hw->bus.func == 0) 2455 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2456 2457 /* Check the NVM for wake support on non-port A ports */ 2458 if (hw->mac.type >= e1000_82580) 2459 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2460 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2461 &eeprom_data); 2462 else if (hw->bus.func == 1) 2463 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2464 2465 if (eeprom_data & IGB_EEPROM_APME) 2466 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2467 2468 /* now that we have the eeprom settings, apply the special cases where 2469 * the eeprom may be wrong or the board simply won't support wake on 2470 * lan on a particular port 2471 */ 2472 switch (pdev->device) { 2473 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2474 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2475 break; 2476 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2477 case E1000_DEV_ID_82576_FIBER: 2478 case E1000_DEV_ID_82576_SERDES: 2479 /* Wake events only supported on port A for dual fiber 2480 * regardless of eeprom setting 2481 */ 2482 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2483 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2484 break; 2485 case E1000_DEV_ID_82576_QUAD_COPPER: 2486 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2487 /* if quad port adapter, disable WoL on all but port A */ 2488 if (global_quad_port_a != 0) 2489 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2490 else 2491 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2492 /* Reset for multiple quad port adapters */ 2493 if (++global_quad_port_a == 4) 2494 global_quad_port_a = 0; 2495 break; 2496 default: 2497 /* If the device can't wake, don't set software support */ 2498 if (!device_can_wakeup(&adapter->pdev->dev)) 2499 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2500 } 2501 2502 /* initialize the wol settings based on the eeprom settings */ 2503 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2504 adapter->wol |= E1000_WUFC_MAG; 2505 2506 /* Some vendors want WoL disabled by default, but still supported */ 2507 if ((hw->mac.type == e1000_i350) && 2508 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2509 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2510 adapter->wol = 0; 2511 } 2512 2513 device_set_wakeup_enable(&adapter->pdev->dev, 2514 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2515 2516 /* reset the hardware with the new settings */ 2517 igb_reset(adapter); 2518 2519 /* Init the I2C interface */ 2520 err = igb_init_i2c(adapter); 2521 if (err) { 2522 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2523 goto err_eeprom; 2524 } 2525 2526 /* let the f/w know that the h/w is now under the control of the 2527 * driver. 2528 */ 2529 igb_get_hw_control(adapter); 2530 2531 strcpy(netdev->name, "eth%d"); 2532 err = register_netdev(netdev); 2533 if (err) 2534 goto err_register; 2535 2536 /* carrier off reporting is important to ethtool even BEFORE open */ 2537 netif_carrier_off(netdev); 2538 2539#ifdef CONFIG_IGB_DCA 2540 if (dca_add_requester(&pdev->dev) == 0) { 2541 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2542 dev_info(&pdev->dev, "DCA enabled\n"); 2543 igb_setup_dca(adapter); 2544 } 2545 2546#endif 2547#ifdef CONFIG_IGB_HWMON 2548 /* Initialize the thermal sensor on i350 devices. */ 2549 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2550 u16 ets_word; 2551 2552 /* Read the NVM to determine if this i350 device supports an 2553 * external thermal sensor. 2554 */ 2555 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2556 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2557 adapter->ets = true; 2558 else 2559 adapter->ets = false; 2560 if (igb_sysfs_init(adapter)) 2561 dev_err(&pdev->dev, 2562 "failed to allocate sysfs resources\n"); 2563 } else { 2564 adapter->ets = false; 2565 } 2566#endif 2567 /* Check if Media Autosense is enabled */ 2568 adapter->ei = *ei; 2569 if (hw->dev_spec._82575.mas_capable) 2570 igb_init_mas(adapter); 2571 2572 /* do hw tstamp init after resetting */ 2573 igb_ptp_init(adapter); 2574 2575 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2576 /* print bus type/speed/width info, not applicable to i354 */ 2577 if (hw->mac.type != e1000_i354) { 2578 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2579 netdev->name, 2580 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2581 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2582 "unknown"), 2583 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2584 "Width x4" : 2585 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2586 "Width x2" : 2587 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2588 "Width x1" : "unknown"), netdev->dev_addr); 2589 } 2590 2591 if ((hw->mac.type >= e1000_i210 || 2592 igb_get_flash_presence_i210(hw))) { 2593 ret_val = igb_read_part_string(hw, part_str, 2594 E1000_PBANUM_LENGTH); 2595 } else { 2596 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2597 } 2598 2599 if (ret_val) 2600 strcpy(part_str, "Unknown"); 2601 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2602 dev_info(&pdev->dev, 2603 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2604 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2605 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2606 adapter->num_rx_queues, adapter->num_tx_queues); 2607 if (hw->phy.media_type == e1000_media_type_copper) { 2608 switch (hw->mac.type) { 2609 case e1000_i350: 2610 case e1000_i210: 2611 case e1000_i211: 2612 /* Enable EEE for internal copper PHY devices */ 2613 err = igb_set_eee_i350(hw); 2614 if ((!err) && 2615 (!hw->dev_spec._82575.eee_disable)) { 2616 adapter->eee_advert = 2617 MDIO_EEE_100TX | MDIO_EEE_1000T; 2618 adapter->flags |= IGB_FLAG_EEE; 2619 } 2620 break; 2621 case e1000_i354: 2622 if ((rd32(E1000_CTRL_EXT) & 2623 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2624 err = igb_set_eee_i354(hw); 2625 if ((!err) && 2626 (!hw->dev_spec._82575.eee_disable)) { 2627 adapter->eee_advert = 2628 MDIO_EEE_100TX | MDIO_EEE_1000T; 2629 adapter->flags |= IGB_FLAG_EEE; 2630 } 2631 } 2632 break; 2633 default: 2634 break; 2635 } 2636 } 2637 pm_runtime_put_noidle(&pdev->dev); 2638 return 0; 2639 2640err_register: 2641 igb_release_hw_control(adapter); 2642 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2643err_eeprom: 2644 if (!igb_check_reset_block(hw)) 2645 igb_reset_phy(hw); 2646 2647 if (hw->flash_address) 2648 iounmap(hw->flash_address); 2649err_sw_init: 2650 igb_clear_interrupt_scheme(adapter); 2651 pci_iounmap(pdev, hw->hw_addr); 2652err_ioremap: 2653 free_netdev(netdev); 2654err_alloc_etherdev: 2655 pci_release_selected_regions(pdev, 2656 pci_select_bars(pdev, IORESOURCE_MEM)); 2657err_pci_reg: 2658err_dma: 2659 pci_disable_device(pdev); 2660 return err; 2661} 2662 2663#ifdef CONFIG_PCI_IOV 2664static int igb_disable_sriov(struct pci_dev *pdev) 2665{ 2666 struct net_device *netdev = pci_get_drvdata(pdev); 2667 struct igb_adapter *adapter = netdev_priv(netdev); 2668 struct e1000_hw *hw = &adapter->hw; 2669 2670 /* reclaim resources allocated to VFs */ 2671 if (adapter->vf_data) { 2672 /* disable iov and allow time for transactions to clear */ 2673 if (pci_vfs_assigned(pdev)) { 2674 dev_warn(&pdev->dev, 2675 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2676 return -EPERM; 2677 } else { 2678 pci_disable_sriov(pdev); 2679 msleep(500); 2680 } 2681 2682 kfree(adapter->vf_data); 2683 adapter->vf_data = NULL; 2684 adapter->vfs_allocated_count = 0; 2685 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2686 wrfl(); 2687 msleep(100); 2688 dev_info(&pdev->dev, "IOV Disabled\n"); 2689 2690 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2691 adapter->flags |= IGB_FLAG_DMAC; 2692 } 2693 2694 return 0; 2695} 2696 2697static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2698{ 2699 struct net_device *netdev = pci_get_drvdata(pdev); 2700 struct igb_adapter *adapter = netdev_priv(netdev); 2701 int old_vfs = pci_num_vf(pdev); 2702 int err = 0; 2703 int i; 2704 2705 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2706 err = -EPERM; 2707 goto out; 2708 } 2709 if (!num_vfs) 2710 goto out; 2711 2712 if (old_vfs) { 2713 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2714 old_vfs, max_vfs); 2715 adapter->vfs_allocated_count = old_vfs; 2716 } else 2717 adapter->vfs_allocated_count = num_vfs; 2718 2719 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2720 sizeof(struct vf_data_storage), GFP_KERNEL); 2721 2722 /* if allocation failed then we do not support SR-IOV */ 2723 if (!adapter->vf_data) { 2724 adapter->vfs_allocated_count = 0; 2725 dev_err(&pdev->dev, 2726 "Unable to allocate memory for VF Data Storage\n"); 2727 err = -ENOMEM; 2728 goto out; 2729 } 2730 2731 /* only call pci_enable_sriov() if no VFs are allocated already */ 2732 if (!old_vfs) { 2733 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2734 if (err) 2735 goto err_out; 2736 } 2737 dev_info(&pdev->dev, "%d VFs allocated\n", 2738 adapter->vfs_allocated_count); 2739 for (i = 0; i < adapter->vfs_allocated_count; i++) 2740 igb_vf_configure(adapter, i); 2741 2742 /* DMA Coalescing is not supported in IOV mode. */ 2743 adapter->flags &= ~IGB_FLAG_DMAC; 2744 goto out; 2745 2746err_out: 2747 kfree(adapter->vf_data); 2748 adapter->vf_data = NULL; 2749 adapter->vfs_allocated_count = 0; 2750out: 2751 return err; 2752} 2753 2754#endif 2755/** 2756 * igb_remove_i2c - Cleanup I2C interface 2757 * @adapter: pointer to adapter structure 2758 **/ 2759static void igb_remove_i2c(struct igb_adapter *adapter) 2760{ 2761 /* free the adapter bus structure */ 2762 i2c_del_adapter(&adapter->i2c_adap); 2763} 2764 2765/** 2766 * igb_remove - Device Removal Routine 2767 * @pdev: PCI device information struct 2768 * 2769 * igb_remove is called by the PCI subsystem to alert the driver 2770 * that it should release a PCI device. The could be caused by a 2771 * Hot-Plug event, or because the driver is going to be removed from 2772 * memory. 2773 **/ 2774static void igb_remove(struct pci_dev *pdev) 2775{ 2776 struct net_device *netdev = pci_get_drvdata(pdev); 2777 struct igb_adapter *adapter = netdev_priv(netdev); 2778 struct e1000_hw *hw = &adapter->hw; 2779 2780 pm_runtime_get_noresume(&pdev->dev); 2781#ifdef CONFIG_IGB_HWMON 2782 igb_sysfs_exit(adapter); 2783#endif 2784 igb_remove_i2c(adapter); 2785 igb_ptp_stop(adapter); 2786 /* The watchdog timer may be rescheduled, so explicitly 2787 * disable watchdog from being rescheduled. 2788 */ 2789 set_bit(__IGB_DOWN, &adapter->state); 2790 del_timer_sync(&adapter->watchdog_timer); 2791 del_timer_sync(&adapter->phy_info_timer); 2792 2793 cancel_work_sync(&adapter->reset_task); 2794 cancel_work_sync(&adapter->watchdog_task); 2795 2796#ifdef CONFIG_IGB_DCA 2797 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2798 dev_info(&pdev->dev, "DCA disabled\n"); 2799 dca_remove_requester(&pdev->dev); 2800 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2801 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2802 } 2803#endif 2804 2805 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2806 * would have already happened in close and is redundant. 2807 */ 2808 igb_release_hw_control(adapter); 2809 2810 unregister_netdev(netdev); 2811 2812 igb_clear_interrupt_scheme(adapter); 2813 2814#ifdef CONFIG_PCI_IOV 2815 igb_disable_sriov(pdev); 2816#endif 2817 2818 pci_iounmap(pdev, hw->hw_addr); 2819 if (hw->flash_address) 2820 iounmap(hw->flash_address); 2821 pci_release_selected_regions(pdev, 2822 pci_select_bars(pdev, IORESOURCE_MEM)); 2823 2824 kfree(adapter->shadow_vfta); 2825 free_netdev(netdev); 2826 2827 pci_disable_pcie_error_reporting(pdev); 2828 2829 pci_disable_device(pdev); 2830} 2831 2832/** 2833 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2834 * @adapter: board private structure to initialize 2835 * 2836 * This function initializes the vf specific data storage and then attempts to 2837 * allocate the VFs. The reason for ordering it this way is because it is much 2838 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2839 * the memory for the VFs. 2840 **/ 2841static void igb_probe_vfs(struct igb_adapter *adapter) 2842{ 2843#ifdef CONFIG_PCI_IOV 2844 struct pci_dev *pdev = adapter->pdev; 2845 struct e1000_hw *hw = &adapter->hw; 2846 2847 /* Virtualization features not supported on i210 family. */ 2848 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2849 return; 2850 2851 pci_sriov_set_totalvfs(pdev, 7); 2852 igb_pci_enable_sriov(pdev, max_vfs); 2853 2854#endif /* CONFIG_PCI_IOV */ 2855} 2856 2857static void igb_init_queue_configuration(struct igb_adapter *adapter) 2858{ 2859 struct e1000_hw *hw = &adapter->hw; 2860 u32 max_rss_queues; 2861 2862 /* Determine the maximum number of RSS queues supported. */ 2863 switch (hw->mac.type) { 2864 case e1000_i211: 2865 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2866 break; 2867 case e1000_82575: 2868 case e1000_i210: 2869 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2870 break; 2871 case e1000_i350: 2872 /* I350 cannot do RSS and SR-IOV at the same time */ 2873 if (!!adapter->vfs_allocated_count) { 2874 max_rss_queues = 1; 2875 break; 2876 } 2877 /* fall through */ 2878 case e1000_82576: 2879 if (!!adapter->vfs_allocated_count) { 2880 max_rss_queues = 2; 2881 break; 2882 } 2883 /* fall through */ 2884 case e1000_82580: 2885 case e1000_i354: 2886 default: 2887 max_rss_queues = IGB_MAX_RX_QUEUES; 2888 break; 2889 } 2890 2891 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2892 2893 /* Determine if we need to pair queues. */ 2894 switch (hw->mac.type) { 2895 case e1000_82575: 2896 case e1000_i211: 2897 /* Device supports enough interrupts without queue pairing. */ 2898 break; 2899 case e1000_82576: 2900 /* If VFs are going to be allocated with RSS queues then we 2901 * should pair the queues in order to conserve interrupts due 2902 * to limited supply. 2903 */ 2904 if ((adapter->rss_queues > 1) && 2905 (adapter->vfs_allocated_count > 6)) 2906 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2907 /* fall through */ 2908 case e1000_82580: 2909 case e1000_i350: 2910 case e1000_i354: 2911 case e1000_i210: 2912 default: 2913 /* If rss_queues > half of max_rss_queues, pair the queues in 2914 * order to conserve interrupts due to limited supply. 2915 */ 2916 if (adapter->rss_queues > (max_rss_queues / 2)) 2917 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2918 break; 2919 } 2920} 2921 2922/** 2923 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2924 * @adapter: board private structure to initialize 2925 * 2926 * igb_sw_init initializes the Adapter private data structure. 2927 * Fields are initialized based on PCI device information and 2928 * OS network device settings (MTU size). 2929 **/ 2930static int igb_sw_init(struct igb_adapter *adapter) 2931{ 2932 struct e1000_hw *hw = &adapter->hw; 2933 struct net_device *netdev = adapter->netdev; 2934 struct pci_dev *pdev = adapter->pdev; 2935 2936 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2937 2938 /* set default ring sizes */ 2939 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2940 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2941 2942 /* set default ITR values */ 2943 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2944 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2945 2946 /* set default work limits */ 2947 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2948 2949 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2950 VLAN_HLEN; 2951 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2952 2953 spin_lock_init(&adapter->stats64_lock); 2954#ifdef CONFIG_PCI_IOV 2955 switch (hw->mac.type) { 2956 case e1000_82576: 2957 case e1000_i350: 2958 if (max_vfs > 7) { 2959 dev_warn(&pdev->dev, 2960 "Maximum of 7 VFs per PF, using max\n"); 2961 max_vfs = adapter->vfs_allocated_count = 7; 2962 } else 2963 adapter->vfs_allocated_count = max_vfs; 2964 if (adapter->vfs_allocated_count) 2965 dev_warn(&pdev->dev, 2966 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 2967 break; 2968 default: 2969 break; 2970 } 2971#endif /* CONFIG_PCI_IOV */ 2972 2973 igb_init_queue_configuration(adapter); 2974 2975 /* Setup and initialize a copy of the hw vlan table array */ 2976 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 2977 GFP_ATOMIC); 2978 2979 /* This call may decrease the number of queues */ 2980 if (igb_init_interrupt_scheme(adapter, true)) { 2981 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2982 return -ENOMEM; 2983 } 2984 2985 igb_probe_vfs(adapter); 2986 2987 /* Explicitly disable IRQ since the NIC can be in any state. */ 2988 igb_irq_disable(adapter); 2989 2990 if (hw->mac.type >= e1000_i350) 2991 adapter->flags &= ~IGB_FLAG_DMAC; 2992 2993 set_bit(__IGB_DOWN, &adapter->state); 2994 return 0; 2995} 2996 2997/** 2998 * igb_open - Called when a network interface is made active 2999 * @netdev: network interface device structure 3000 * 3001 * Returns 0 on success, negative value on failure 3002 * 3003 * The open entry point is called when a network interface is made 3004 * active by the system (IFF_UP). At this point all resources needed 3005 * for transmit and receive operations are allocated, the interrupt 3006 * handler is registered with the OS, the watchdog timer is started, 3007 * and the stack is notified that the interface is ready. 3008 **/ 3009static int __igb_open(struct net_device *netdev, bool resuming) 3010{ 3011 struct igb_adapter *adapter = netdev_priv(netdev); 3012 struct e1000_hw *hw = &adapter->hw; 3013 struct pci_dev *pdev = adapter->pdev; 3014 int err; 3015 int i; 3016 3017 /* disallow open during test */ 3018 if (test_bit(__IGB_TESTING, &adapter->state)) { 3019 WARN_ON(resuming); 3020 return -EBUSY; 3021 } 3022 3023 if (!resuming) 3024 pm_runtime_get_sync(&pdev->dev); 3025 3026 netif_carrier_off(netdev); 3027 3028 /* allocate transmit descriptors */ 3029 err = igb_setup_all_tx_resources(adapter); 3030 if (err) 3031 goto err_setup_tx; 3032 3033 /* allocate receive descriptors */ 3034 err = igb_setup_all_rx_resources(adapter); 3035 if (err) 3036 goto err_setup_rx; 3037 3038 igb_power_up_link(adapter); 3039 3040 /* before we allocate an interrupt, we must be ready to handle it. 3041 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3042 * as soon as we call pci_request_irq, so we have to setup our 3043 * clean_rx handler before we do so. 3044 */ 3045 igb_configure(adapter); 3046 3047 err = igb_request_irq(adapter); 3048 if (err) 3049 goto err_req_irq; 3050 3051 /* Notify the stack of the actual queue counts. */ 3052 err = netif_set_real_num_tx_queues(adapter->netdev, 3053 adapter->num_tx_queues); 3054 if (err) 3055 goto err_set_queues; 3056 3057 err = netif_set_real_num_rx_queues(adapter->netdev, 3058 adapter->num_rx_queues); 3059 if (err) 3060 goto err_set_queues; 3061 3062 /* From here on the code is the same as igb_up() */ 3063 clear_bit(__IGB_DOWN, &adapter->state); 3064 3065 for (i = 0; i < adapter->num_q_vectors; i++) 3066 napi_enable(&(adapter->q_vector[i]->napi)); 3067 3068 /* Clear any pending interrupts. */ 3069 rd32(E1000_ICR); 3070 3071 igb_irq_enable(adapter); 3072 3073 /* notify VFs that reset has been completed */ 3074 if (adapter->vfs_allocated_count) { 3075 u32 reg_data = rd32(E1000_CTRL_EXT); 3076 3077 reg_data |= E1000_CTRL_EXT_PFRSTD; 3078 wr32(E1000_CTRL_EXT, reg_data); 3079 } 3080 3081 netif_tx_start_all_queues(netdev); 3082 3083 if (!resuming) 3084 pm_runtime_put(&pdev->dev); 3085 3086 /* start the watchdog. */ 3087 hw->mac.get_link_status = 1; 3088 schedule_work(&adapter->watchdog_task); 3089 3090 return 0; 3091 3092err_set_queues: 3093 igb_free_irq(adapter); 3094err_req_irq: 3095 igb_release_hw_control(adapter); 3096 igb_power_down_link(adapter); 3097 igb_free_all_rx_resources(adapter); 3098err_setup_rx: 3099 igb_free_all_tx_resources(adapter); 3100err_setup_tx: 3101 igb_reset(adapter); 3102 if (!resuming) 3103 pm_runtime_put(&pdev->dev); 3104 3105 return err; 3106} 3107 3108static int igb_open(struct net_device *netdev) 3109{ 3110 return __igb_open(netdev, false); 3111} 3112 3113/** 3114 * igb_close - Disables a network interface 3115 * @netdev: network interface device structure 3116 * 3117 * Returns 0, this is not allowed to fail 3118 * 3119 * The close entry point is called when an interface is de-activated 3120 * by the OS. The hardware is still under the driver's control, but 3121 * needs to be disabled. A global MAC reset is issued to stop the 3122 * hardware, and all transmit and receive resources are freed. 3123 **/ 3124static int __igb_close(struct net_device *netdev, bool suspending) 3125{ 3126 struct igb_adapter *adapter = netdev_priv(netdev); 3127 struct pci_dev *pdev = adapter->pdev; 3128 3129 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3130 3131 if (!suspending) 3132 pm_runtime_get_sync(&pdev->dev); 3133 3134 igb_down(adapter); 3135 igb_free_irq(adapter); 3136 3137 igb_free_all_tx_resources(adapter); 3138 igb_free_all_rx_resources(adapter); 3139 3140 if (!suspending) 3141 pm_runtime_put_sync(&pdev->dev); 3142 return 0; 3143} 3144 3145static int igb_close(struct net_device *netdev) 3146{ 3147 return __igb_close(netdev, false); 3148} 3149 3150/** 3151 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3152 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3153 * 3154 * Return 0 on success, negative on failure 3155 **/ 3156int igb_setup_tx_resources(struct igb_ring *tx_ring) 3157{ 3158 struct device *dev = tx_ring->dev; 3159 int size; 3160 3161 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3162 3163 tx_ring->tx_buffer_info = vzalloc(size); 3164 if (!tx_ring->tx_buffer_info) 3165 goto err; 3166 3167 /* round up to nearest 4K */ 3168 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3169 tx_ring->size = ALIGN(tx_ring->size, 4096); 3170 3171 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3172 &tx_ring->dma, GFP_KERNEL); 3173 if (!tx_ring->desc) 3174 goto err; 3175 3176 tx_ring->next_to_use = 0; 3177 tx_ring->next_to_clean = 0; 3178 3179 return 0; 3180 3181err: 3182 vfree(tx_ring->tx_buffer_info); 3183 tx_ring->tx_buffer_info = NULL; 3184 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3185 return -ENOMEM; 3186} 3187 3188/** 3189 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3190 * (Descriptors) for all queues 3191 * @adapter: board private structure 3192 * 3193 * Return 0 on success, negative on failure 3194 **/ 3195static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3196{ 3197 struct pci_dev *pdev = adapter->pdev; 3198 int i, err = 0; 3199 3200 for (i = 0; i < adapter->num_tx_queues; i++) { 3201 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3202 if (err) { 3203 dev_err(&pdev->dev, 3204 "Allocation for Tx Queue %u failed\n", i); 3205 for (i--; i >= 0; i--) 3206 igb_free_tx_resources(adapter->tx_ring[i]); 3207 break; 3208 } 3209 } 3210 3211 return err; 3212} 3213 3214/** 3215 * igb_setup_tctl - configure the transmit control registers 3216 * @adapter: Board private structure 3217 **/ 3218void igb_setup_tctl(struct igb_adapter *adapter) 3219{ 3220 struct e1000_hw *hw = &adapter->hw; 3221 u32 tctl; 3222 3223 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3224 wr32(E1000_TXDCTL(0), 0); 3225 3226 /* Program the Transmit Control Register */ 3227 tctl = rd32(E1000_TCTL); 3228 tctl &= ~E1000_TCTL_CT; 3229 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3230 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3231 3232 igb_config_collision_dist(hw); 3233 3234 /* Enable transmits */ 3235 tctl |= E1000_TCTL_EN; 3236 3237 wr32(E1000_TCTL, tctl); 3238} 3239 3240/** 3241 * igb_configure_tx_ring - Configure transmit ring after Reset 3242 * @adapter: board private structure 3243 * @ring: tx ring to configure 3244 * 3245 * Configure a transmit ring after a reset. 3246 **/ 3247void igb_configure_tx_ring(struct igb_adapter *adapter, 3248 struct igb_ring *ring) 3249{ 3250 struct e1000_hw *hw = &adapter->hw; 3251 u32 txdctl = 0; 3252 u64 tdba = ring->dma; 3253 int reg_idx = ring->reg_idx; 3254 3255 /* disable the queue */ 3256 wr32(E1000_TXDCTL(reg_idx), 0); 3257 wrfl(); 3258 mdelay(10); 3259 3260 wr32(E1000_TDLEN(reg_idx), 3261 ring->count * sizeof(union e1000_adv_tx_desc)); 3262 wr32(E1000_TDBAL(reg_idx), 3263 tdba & 0x00000000ffffffffULL); 3264 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3265 3266 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 3267 wr32(E1000_TDH(reg_idx), 0); 3268 writel(0, ring->tail); 3269 3270 txdctl |= IGB_TX_PTHRESH; 3271 txdctl |= IGB_TX_HTHRESH << 8; 3272 txdctl |= IGB_TX_WTHRESH << 16; 3273 3274 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3275 wr32(E1000_TXDCTL(reg_idx), txdctl); 3276} 3277 3278/** 3279 * igb_configure_tx - Configure transmit Unit after Reset 3280 * @adapter: board private structure 3281 * 3282 * Configure the Tx unit of the MAC after a reset. 3283 **/ 3284static void igb_configure_tx(struct igb_adapter *adapter) 3285{ 3286 int i; 3287 3288 for (i = 0; i < adapter->num_tx_queues; i++) 3289 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3290} 3291 3292/** 3293 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3294 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3295 * 3296 * Returns 0 on success, negative on failure 3297 **/ 3298int igb_setup_rx_resources(struct igb_ring *rx_ring) 3299{ 3300 struct device *dev = rx_ring->dev; 3301 int size; 3302 3303 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3304 3305 rx_ring->rx_buffer_info = vzalloc(size); 3306 if (!rx_ring->rx_buffer_info) 3307 goto err; 3308 3309 /* Round up to nearest 4K */ 3310 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3311 rx_ring->size = ALIGN(rx_ring->size, 4096); 3312 3313 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3314 &rx_ring->dma, GFP_KERNEL); 3315 if (!rx_ring->desc) 3316 goto err; 3317 3318 rx_ring->next_to_alloc = 0; 3319 rx_ring->next_to_clean = 0; 3320 rx_ring->next_to_use = 0; 3321 3322 return 0; 3323 3324err: 3325 vfree(rx_ring->rx_buffer_info); 3326 rx_ring->rx_buffer_info = NULL; 3327 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3328 return -ENOMEM; 3329} 3330 3331/** 3332 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3333 * (Descriptors) for all queues 3334 * @adapter: board private structure 3335 * 3336 * Return 0 on success, negative on failure 3337 **/ 3338static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3339{ 3340 struct pci_dev *pdev = adapter->pdev; 3341 int i, err = 0; 3342 3343 for (i = 0; i < adapter->num_rx_queues; i++) { 3344 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3345 if (err) { 3346 dev_err(&pdev->dev, 3347 "Allocation for Rx Queue %u failed\n", i); 3348 for (i--; i >= 0; i--) 3349 igb_free_rx_resources(adapter->rx_ring[i]); 3350 break; 3351 } 3352 } 3353 3354 return err; 3355} 3356 3357/** 3358 * igb_setup_mrqc - configure the multiple receive queue control registers 3359 * @adapter: Board private structure 3360 **/ 3361static void igb_setup_mrqc(struct igb_adapter *adapter) 3362{ 3363 struct e1000_hw *hw = &adapter->hw; 3364 u32 mrqc, rxcsum; 3365 u32 j, num_rx_queues; 3366 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, 3367 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, 3368 0xA32DCB77, 0x0CF23080, 0x3BB7426A, 3369 0xFA01ACBE }; 3370 3371 /* Fill out hash function seeds */ 3372 for (j = 0; j < 10; j++) 3373 wr32(E1000_RSSRK(j), rsskey[j]); 3374 3375 num_rx_queues = adapter->rss_queues; 3376 3377 switch (hw->mac.type) { 3378 case e1000_82576: 3379 /* 82576 supports 2 RSS queues for SR-IOV */ 3380 if (adapter->vfs_allocated_count) 3381 num_rx_queues = 2; 3382 break; 3383 default: 3384 break; 3385 } 3386 3387 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3388 for (j = 0; j < IGB_RETA_SIZE; j++) 3389 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE; 3390 adapter->rss_indir_tbl_init = num_rx_queues; 3391 } 3392 igb_write_rss_indir_tbl(adapter); 3393 3394 /* Disable raw packet checksumming so that RSS hash is placed in 3395 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3396 * offloads as they are enabled by default 3397 */ 3398 rxcsum = rd32(E1000_RXCSUM); 3399 rxcsum |= E1000_RXCSUM_PCSD; 3400 3401 if (adapter->hw.mac.type >= e1000_82576) 3402 /* Enable Receive Checksum Offload for SCTP */ 3403 rxcsum |= E1000_RXCSUM_CRCOFL; 3404 3405 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3406 wr32(E1000_RXCSUM, rxcsum); 3407 3408 /* Generate RSS hash based on packet types, TCP/UDP 3409 * port numbers and/or IPv4/v6 src and dst addresses 3410 */ 3411 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3412 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3413 E1000_MRQC_RSS_FIELD_IPV6 | 3414 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3415 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3416 3417 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3418 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3419 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3420 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3421 3422 /* If VMDq is enabled then we set the appropriate mode for that, else 3423 * we default to RSS so that an RSS hash is calculated per packet even 3424 * if we are only using one queue 3425 */ 3426 if (adapter->vfs_allocated_count) { 3427 if (hw->mac.type > e1000_82575) { 3428 /* Set the default pool for the PF's first queue */ 3429 u32 vtctl = rd32(E1000_VT_CTL); 3430 3431 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3432 E1000_VT_CTL_DISABLE_DEF_POOL); 3433 vtctl |= adapter->vfs_allocated_count << 3434 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3435 wr32(E1000_VT_CTL, vtctl); 3436 } 3437 if (adapter->rss_queues > 1) 3438 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 3439 else 3440 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3441 } else { 3442 if (hw->mac.type != e1000_i211) 3443 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 3444 } 3445 igb_vmm_control(adapter); 3446 3447 wr32(E1000_MRQC, mrqc); 3448} 3449 3450/** 3451 * igb_setup_rctl - configure the receive control registers 3452 * @adapter: Board private structure 3453 **/ 3454void igb_setup_rctl(struct igb_adapter *adapter) 3455{ 3456 struct e1000_hw *hw = &adapter->hw; 3457 u32 rctl; 3458 3459 rctl = rd32(E1000_RCTL); 3460 3461 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3462 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3463 3464 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3465 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3466 3467 /* enable stripping of CRC. It's unlikely this will break BMC 3468 * redirection as it did with e1000. Newer features require 3469 * that the HW strips the CRC. 3470 */ 3471 rctl |= E1000_RCTL_SECRC; 3472 3473 /* disable store bad packets and clear size bits. */ 3474 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3475 3476 /* enable LPE to prevent packets larger than max_frame_size */ 3477 rctl |= E1000_RCTL_LPE; 3478 3479 /* disable queue 0 to prevent tail write w/o re-config */ 3480 wr32(E1000_RXDCTL(0), 0); 3481 3482 /* Attention!!! For SR-IOV PF driver operations you must enable 3483 * queue drop for all VF and PF queues to prevent head of line blocking 3484 * if an un-trusted VF does not provide descriptors to hardware. 3485 */ 3486 if (adapter->vfs_allocated_count) { 3487 /* set all queue drop enable bits */ 3488 wr32(E1000_QDE, ALL_QUEUES); 3489 } 3490 3491 /* This is useful for sniffing bad packets. */ 3492 if (adapter->netdev->features & NETIF_F_RXALL) { 3493 /* UPE and MPE will be handled by normal PROMISC logic 3494 * in e1000e_set_rx_mode 3495 */ 3496 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3497 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3498 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3499 3500 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3501 E1000_RCTL_DPF | /* Allow filtered pause */ 3502 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3503 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3504 * and that breaks VLANs. 3505 */ 3506 } 3507 3508 wr32(E1000_RCTL, rctl); 3509} 3510 3511static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3512 int vfn) 3513{ 3514 struct e1000_hw *hw = &adapter->hw; 3515 u32 vmolr; 3516 3517 /* if it isn't the PF check to see if VFs are enabled and 3518 * increase the size to support vlan tags 3519 */ 3520 if (vfn < adapter->vfs_allocated_count && 3521 adapter->vf_data[vfn].vlans_enabled) 3522 size += VLAN_TAG_SIZE; 3523 3524 vmolr = rd32(E1000_VMOLR(vfn)); 3525 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3526 vmolr |= size | E1000_VMOLR_LPE; 3527 wr32(E1000_VMOLR(vfn), vmolr); 3528 3529 return 0; 3530} 3531 3532/** 3533 * igb_rlpml_set - set maximum receive packet size 3534 * @adapter: board private structure 3535 * 3536 * Configure maximum receivable packet size. 3537 **/ 3538static void igb_rlpml_set(struct igb_adapter *adapter) 3539{ 3540 u32 max_frame_size = adapter->max_frame_size; 3541 struct e1000_hw *hw = &adapter->hw; 3542 u16 pf_id = adapter->vfs_allocated_count; 3543 3544 if (pf_id) { 3545 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3546 /* If we're in VMDQ or SR-IOV mode, then set global RLPML 3547 * to our max jumbo frame size, in case we need to enable 3548 * jumbo frames on one of the rings later. 3549 * This will not pass over-length frames into the default 3550 * queue because it's gated by the VMOLR.RLPML. 3551 */ 3552 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3553 } 3554 3555 wr32(E1000_RLPML, max_frame_size); 3556} 3557 3558static inline void igb_set_vmolr(struct igb_adapter *adapter, 3559 int vfn, bool aupe) 3560{ 3561 struct e1000_hw *hw = &adapter->hw; 3562 u32 vmolr; 3563 3564 /* This register exists only on 82576 and newer so if we are older then 3565 * we should exit and do nothing 3566 */ 3567 if (hw->mac.type < e1000_82576) 3568 return; 3569 3570 vmolr = rd32(E1000_VMOLR(vfn)); 3571 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3572 if (hw->mac.type == e1000_i350) { 3573 u32 dvmolr; 3574 3575 dvmolr = rd32(E1000_DVMOLR(vfn)); 3576 dvmolr |= E1000_DVMOLR_STRVLAN; 3577 wr32(E1000_DVMOLR(vfn), dvmolr); 3578 } 3579 if (aupe) 3580 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3581 else 3582 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3583 3584 /* clear all bits that might not be set */ 3585 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3586 3587 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3588 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3589 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3590 * multicast packets 3591 */ 3592 if (vfn <= adapter->vfs_allocated_count) 3593 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3594 3595 wr32(E1000_VMOLR(vfn), vmolr); 3596} 3597 3598/** 3599 * igb_configure_rx_ring - Configure a receive ring after Reset 3600 * @adapter: board private structure 3601 * @ring: receive ring to be configured 3602 * 3603 * Configure the Rx unit of the MAC after a reset. 3604 **/ 3605void igb_configure_rx_ring(struct igb_adapter *adapter, 3606 struct igb_ring *ring) 3607{ 3608 struct e1000_hw *hw = &adapter->hw; 3609 u64 rdba = ring->dma; 3610 int reg_idx = ring->reg_idx; 3611 u32 srrctl = 0, rxdctl = 0; 3612 3613 /* disable the queue */ 3614 wr32(E1000_RXDCTL(reg_idx), 0); 3615 3616 /* Set DMA base address registers */ 3617 wr32(E1000_RDBAL(reg_idx), 3618 rdba & 0x00000000ffffffffULL); 3619 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3620 wr32(E1000_RDLEN(reg_idx), 3621 ring->count * sizeof(union e1000_adv_rx_desc)); 3622 3623 /* initialize head and tail */ 3624 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3625 wr32(E1000_RDH(reg_idx), 0); 3626 writel(0, ring->tail); 3627 3628 /* set descriptor configuration */ 3629 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3630 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3631 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3632 if (hw->mac.type >= e1000_82580) 3633 srrctl |= E1000_SRRCTL_TIMESTAMP; 3634 /* Only set Drop Enable if we are supporting multiple queues */ 3635 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3636 srrctl |= E1000_SRRCTL_DROP_EN; 3637 3638 wr32(E1000_SRRCTL(reg_idx), srrctl); 3639 3640 /* set filtering for VMDQ pools */ 3641 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3642 3643 rxdctl |= IGB_RX_PTHRESH; 3644 rxdctl |= IGB_RX_HTHRESH << 8; 3645 rxdctl |= IGB_RX_WTHRESH << 16; 3646 3647 /* enable receive descriptor fetching */ 3648 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3649 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3650} 3651 3652/** 3653 * igb_configure_rx - Configure receive Unit after Reset 3654 * @adapter: board private structure 3655 * 3656 * Configure the Rx unit of the MAC after a reset. 3657 **/ 3658static void igb_configure_rx(struct igb_adapter *adapter) 3659{ 3660 int i; 3661 3662 /* set UTA to appropriate mode */ 3663 igb_set_uta(adapter); 3664 3665 /* set the correct pool for the PF default MAC address in entry 0 */ 3666 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3667 adapter->vfs_allocated_count); 3668 3669 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3670 * the Base and Length of the Rx Descriptor Ring 3671 */ 3672 for (i = 0; i < adapter->num_rx_queues; i++) 3673 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3674} 3675 3676/** 3677 * igb_free_tx_resources - Free Tx Resources per Queue 3678 * @tx_ring: Tx descriptor ring for a specific queue 3679 * 3680 * Free all transmit software resources 3681 **/ 3682void igb_free_tx_resources(struct igb_ring *tx_ring) 3683{ 3684 igb_clean_tx_ring(tx_ring); 3685 3686 vfree(tx_ring->tx_buffer_info); 3687 tx_ring->tx_buffer_info = NULL; 3688 3689 /* if not set, then don't free */ 3690 if (!tx_ring->desc) 3691 return; 3692 3693 dma_free_coherent(tx_ring->dev, tx_ring->size, 3694 tx_ring->desc, tx_ring->dma); 3695 3696 tx_ring->desc = NULL; 3697} 3698 3699/** 3700 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3701 * @adapter: board private structure 3702 * 3703 * Free all transmit software resources 3704 **/ 3705static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3706{ 3707 int i; 3708 3709 for (i = 0; i < adapter->num_tx_queues; i++) 3710 igb_free_tx_resources(adapter->tx_ring[i]); 3711} 3712 3713void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3714 struct igb_tx_buffer *tx_buffer) 3715{ 3716 if (tx_buffer->skb) { 3717 dev_kfree_skb_any(tx_buffer->skb); 3718 if (dma_unmap_len(tx_buffer, len)) 3719 dma_unmap_single(ring->dev, 3720 dma_unmap_addr(tx_buffer, dma), 3721 dma_unmap_len(tx_buffer, len), 3722 DMA_TO_DEVICE); 3723 } else if (dma_unmap_len(tx_buffer, len)) { 3724 dma_unmap_page(ring->dev, 3725 dma_unmap_addr(tx_buffer, dma), 3726 dma_unmap_len(tx_buffer, len), 3727 DMA_TO_DEVICE); 3728 } 3729 tx_buffer->next_to_watch = NULL; 3730 tx_buffer->skb = NULL; 3731 dma_unmap_len_set(tx_buffer, len, 0); 3732 /* buffer_info must be completely set up in the transmit path */ 3733} 3734 3735/** 3736 * igb_clean_tx_ring - Free Tx Buffers 3737 * @tx_ring: ring to be cleaned 3738 **/ 3739static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3740{ 3741 struct igb_tx_buffer *buffer_info; 3742 unsigned long size; 3743 u16 i; 3744 3745 if (!tx_ring->tx_buffer_info) 3746 return; 3747 /* Free all the Tx ring sk_buffs */ 3748 3749 for (i = 0; i < tx_ring->count; i++) { 3750 buffer_info = &tx_ring->tx_buffer_info[i]; 3751 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3752 } 3753 3754 netdev_tx_reset_queue(txring_txq(tx_ring)); 3755 3756 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3757 memset(tx_ring->tx_buffer_info, 0, size); 3758 3759 /* Zero out the descriptor ring */ 3760 memset(tx_ring->desc, 0, tx_ring->size); 3761 3762 tx_ring->next_to_use = 0; 3763 tx_ring->next_to_clean = 0; 3764} 3765 3766/** 3767 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3768 * @adapter: board private structure 3769 **/ 3770static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3771{ 3772 int i; 3773 3774 for (i = 0; i < adapter->num_tx_queues; i++) 3775 igb_clean_tx_ring(adapter->tx_ring[i]); 3776} 3777 3778/** 3779 * igb_free_rx_resources - Free Rx Resources 3780 * @rx_ring: ring to clean the resources from 3781 * 3782 * Free all receive software resources 3783 **/ 3784void igb_free_rx_resources(struct igb_ring *rx_ring) 3785{ 3786 igb_clean_rx_ring(rx_ring); 3787 3788 vfree(rx_ring->rx_buffer_info); 3789 rx_ring->rx_buffer_info = NULL; 3790 3791 /* if not set, then don't free */ 3792 if (!rx_ring->desc) 3793 return; 3794 3795 dma_free_coherent(rx_ring->dev, rx_ring->size, 3796 rx_ring->desc, rx_ring->dma); 3797 3798 rx_ring->desc = NULL; 3799} 3800 3801/** 3802 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3803 * @adapter: board private structure 3804 * 3805 * Free all receive software resources 3806 **/ 3807static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3808{ 3809 int i; 3810 3811 for (i = 0; i < adapter->num_rx_queues; i++) 3812 igb_free_rx_resources(adapter->rx_ring[i]); 3813} 3814 3815/** 3816 * igb_clean_rx_ring - Free Rx Buffers per Queue 3817 * @rx_ring: ring to free buffers from 3818 **/ 3819static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3820{ 3821 unsigned long size; 3822 u16 i; 3823 3824 if (rx_ring->skb) 3825 dev_kfree_skb(rx_ring->skb); 3826 rx_ring->skb = NULL; 3827 3828 if (!rx_ring->rx_buffer_info) 3829 return; 3830 3831 /* Free all the Rx ring sk_buffs */ 3832 for (i = 0; i < rx_ring->count; i++) { 3833 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3834 3835 if (!buffer_info->page) 3836 continue; 3837 3838 dma_unmap_page(rx_ring->dev, 3839 buffer_info->dma, 3840 PAGE_SIZE, 3841 DMA_FROM_DEVICE); 3842 __free_page(buffer_info->page); 3843 3844 buffer_info->page = NULL; 3845 } 3846 3847 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3848 memset(rx_ring->rx_buffer_info, 0, size); 3849 3850 /* Zero out the descriptor ring */ 3851 memset(rx_ring->desc, 0, rx_ring->size); 3852 3853 rx_ring->next_to_alloc = 0; 3854 rx_ring->next_to_clean = 0; 3855 rx_ring->next_to_use = 0; 3856} 3857 3858/** 3859 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3860 * @adapter: board private structure 3861 **/ 3862static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3863{ 3864 int i; 3865 3866 for (i = 0; i < adapter->num_rx_queues; i++) 3867 igb_clean_rx_ring(adapter->rx_ring[i]); 3868} 3869 3870/** 3871 * igb_set_mac - Change the Ethernet Address of the NIC 3872 * @netdev: network interface device structure 3873 * @p: pointer to an address structure 3874 * 3875 * Returns 0 on success, negative on failure 3876 **/ 3877static int igb_set_mac(struct net_device *netdev, void *p) 3878{ 3879 struct igb_adapter *adapter = netdev_priv(netdev); 3880 struct e1000_hw *hw = &adapter->hw; 3881 struct sockaddr *addr = p; 3882 3883 if (!is_valid_ether_addr(addr->sa_data)) 3884 return -EADDRNOTAVAIL; 3885 3886 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3887 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3888 3889 /* set the correct pool for the new PF MAC address in entry 0 */ 3890 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3891 adapter->vfs_allocated_count); 3892 3893 return 0; 3894} 3895 3896/** 3897 * igb_write_mc_addr_list - write multicast addresses to MTA 3898 * @netdev: network interface device structure 3899 * 3900 * Writes multicast address list to the MTA hash table. 3901 * Returns: -ENOMEM on failure 3902 * 0 on no addresses written 3903 * X on writing X addresses to MTA 3904 **/ 3905static int igb_write_mc_addr_list(struct net_device *netdev) 3906{ 3907 struct igb_adapter *adapter = netdev_priv(netdev); 3908 struct e1000_hw *hw = &adapter->hw; 3909 struct netdev_hw_addr *ha; 3910 u8 *mta_list; 3911 int i; 3912 3913 if (netdev_mc_empty(netdev)) { 3914 /* nothing to program, so clear mc list */ 3915 igb_update_mc_addr_list(hw, NULL, 0); 3916 igb_restore_vf_multicasts(adapter); 3917 return 0; 3918 } 3919 3920 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3921 if (!mta_list) 3922 return -ENOMEM; 3923 3924 /* The shared function expects a packed array of only addresses. */ 3925 i = 0; 3926 netdev_for_each_mc_addr(ha, netdev) 3927 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3928 3929 igb_update_mc_addr_list(hw, mta_list, i); 3930 kfree(mta_list); 3931 3932 return netdev_mc_count(netdev); 3933} 3934 3935/** 3936 * igb_write_uc_addr_list - write unicast addresses to RAR table 3937 * @netdev: network interface device structure 3938 * 3939 * Writes unicast address list to the RAR table. 3940 * Returns: -ENOMEM on failure/insufficient address space 3941 * 0 on no addresses written 3942 * X on writing X addresses to the RAR table 3943 **/ 3944static int igb_write_uc_addr_list(struct net_device *netdev) 3945{ 3946 struct igb_adapter *adapter = netdev_priv(netdev); 3947 struct e1000_hw *hw = &adapter->hw; 3948 unsigned int vfn = adapter->vfs_allocated_count; 3949 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3950 int count = 0; 3951 3952 /* return ENOMEM indicating insufficient memory for addresses */ 3953 if (netdev_uc_count(netdev) > rar_entries) 3954 return -ENOMEM; 3955 3956 if (!netdev_uc_empty(netdev) && rar_entries) { 3957 struct netdev_hw_addr *ha; 3958 3959 netdev_for_each_uc_addr(ha, netdev) { 3960 if (!rar_entries) 3961 break; 3962 igb_rar_set_qsel(adapter, ha->addr, 3963 rar_entries--, 3964 vfn); 3965 count++; 3966 } 3967 } 3968 /* write the addresses in reverse order to avoid write combining */ 3969 for (; rar_entries > 0 ; rar_entries--) { 3970 wr32(E1000_RAH(rar_entries), 0); 3971 wr32(E1000_RAL(rar_entries), 0); 3972 } 3973 wrfl(); 3974 3975 return count; 3976} 3977 3978/** 3979 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3980 * @netdev: network interface device structure 3981 * 3982 * The set_rx_mode entry point is called whenever the unicast or multicast 3983 * address lists or the network interface flags are updated. This routine is 3984 * responsible for configuring the hardware for proper unicast, multicast, 3985 * promiscuous mode, and all-multi behavior. 3986 **/ 3987static void igb_set_rx_mode(struct net_device *netdev) 3988{ 3989 struct igb_adapter *adapter = netdev_priv(netdev); 3990 struct e1000_hw *hw = &adapter->hw; 3991 unsigned int vfn = adapter->vfs_allocated_count; 3992 u32 rctl, vmolr = 0; 3993 int count; 3994 3995 /* Check for Promiscuous and All Multicast modes */ 3996 rctl = rd32(E1000_RCTL); 3997 3998 /* clear the effected bits */ 3999 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 4000 4001 if (netdev->flags & IFF_PROMISC) { 4002 /* retain VLAN HW filtering if in VT mode */ 4003 if (adapter->vfs_allocated_count) 4004 rctl |= E1000_RCTL_VFE; 4005 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 4006 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 4007 } else { 4008 if (netdev->flags & IFF_ALLMULTI) { 4009 rctl |= E1000_RCTL_MPE; 4010 vmolr |= E1000_VMOLR_MPME; 4011 } else { 4012 /* Write addresses to the MTA, if the attempt fails 4013 * then we should just turn on promiscuous mode so 4014 * that we can at least receive multicast traffic 4015 */ 4016 count = igb_write_mc_addr_list(netdev); 4017 if (count < 0) { 4018 rctl |= E1000_RCTL_MPE; 4019 vmolr |= E1000_VMOLR_MPME; 4020 } else if (count) { 4021 vmolr |= E1000_VMOLR_ROMPE; 4022 } 4023 } 4024 /* Write addresses to available RAR registers, if there is not 4025 * sufficient space to store all the addresses then enable 4026 * unicast promiscuous mode 4027 */ 4028 count = igb_write_uc_addr_list(netdev); 4029 if (count < 0) { 4030 rctl |= E1000_RCTL_UPE; 4031 vmolr |= E1000_VMOLR_ROPE; 4032 } 4033 rctl |= E1000_RCTL_VFE; 4034 } 4035 wr32(E1000_RCTL, rctl); 4036 4037 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4038 * the VMOLR to enable the appropriate modes. Without this workaround 4039 * we will have issues with VLAN tag stripping not being done for frames 4040 * that are only arriving because we are the default pool 4041 */ 4042 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4043 return; 4044 4045 vmolr |= rd32(E1000_VMOLR(vfn)) & 4046 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4047 wr32(E1000_VMOLR(vfn), vmolr); 4048 igb_restore_vf_multicasts(adapter); 4049} 4050 4051static void igb_check_wvbr(struct igb_adapter *adapter) 4052{ 4053 struct e1000_hw *hw = &adapter->hw; 4054 u32 wvbr = 0; 4055 4056 switch (hw->mac.type) { 4057 case e1000_82576: 4058 case e1000_i350: 4059 if (!(wvbr = rd32(E1000_WVBR))) 4060 return; 4061 break; 4062 default: 4063 break; 4064 } 4065 4066 adapter->wvbr |= wvbr; 4067} 4068 4069#define IGB_STAGGERED_QUEUE_OFFSET 8 4070 4071static void igb_spoof_check(struct igb_adapter *adapter) 4072{ 4073 int j; 4074 4075 if (!adapter->wvbr) 4076 return; 4077 4078 for (j = 0; j < adapter->vfs_allocated_count; j++) { 4079 if (adapter->wvbr & (1 << j) || 4080 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 4081 dev_warn(&adapter->pdev->dev, 4082 "Spoof event(s) detected on VF %d\n", j); 4083 adapter->wvbr &= 4084 ~((1 << j) | 4085 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 4086 } 4087 } 4088} 4089 4090/* Need to wait a few seconds after link up to get diagnostic information from 4091 * the phy 4092 */ 4093static void igb_update_phy_info(unsigned long data) 4094{ 4095 struct igb_adapter *adapter = (struct igb_adapter *) data; 4096 igb_get_phy_info(&adapter->hw); 4097} 4098 4099/** 4100 * igb_has_link - check shared code for link and determine up/down 4101 * @adapter: pointer to driver private info 4102 **/ 4103bool igb_has_link(struct igb_adapter *adapter) 4104{ 4105 struct e1000_hw *hw = &adapter->hw; 4106 bool link_active = false; 4107 4108 /* get_link_status is set on LSC (link status) interrupt or 4109 * rx sequence error interrupt. get_link_status will stay 4110 * false until the e1000_check_for_link establishes link 4111 * for copper adapters ONLY 4112 */ 4113 switch (hw->phy.media_type) { 4114 case e1000_media_type_copper: 4115 if (!hw->mac.get_link_status) 4116 return true; 4117 case e1000_media_type_internal_serdes: 4118 hw->mac.ops.check_for_link(hw); 4119 link_active = !hw->mac.get_link_status; 4120 break; 4121 default: 4122 case e1000_media_type_unknown: 4123 break; 4124 } 4125 4126 if (((hw->mac.type == e1000_i210) || 4127 (hw->mac.type == e1000_i211)) && 4128 (hw->phy.id == I210_I_PHY_ID)) { 4129 if (!netif_carrier_ok(adapter->netdev)) { 4130 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4131 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4132 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4133 adapter->link_check_timeout = jiffies; 4134 } 4135 } 4136 4137 return link_active; 4138} 4139 4140static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4141{ 4142 bool ret = false; 4143 u32 ctrl_ext, thstat; 4144 4145 /* check for thermal sensor event on i350 copper only */ 4146 if (hw->mac.type == e1000_i350) { 4147 thstat = rd32(E1000_THSTAT); 4148 ctrl_ext = rd32(E1000_CTRL_EXT); 4149 4150 if ((hw->phy.media_type == e1000_media_type_copper) && 4151 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4152 ret = !!(thstat & event); 4153 } 4154 4155 return ret; 4156} 4157 4158/** 4159 * igb_watchdog - Timer Call-back 4160 * @data: pointer to adapter cast into an unsigned long 4161 **/ 4162static void igb_watchdog(unsigned long data) 4163{ 4164 struct igb_adapter *adapter = (struct igb_adapter *)data; 4165 /* Do the rest outside of interrupt context */ 4166 schedule_work(&adapter->watchdog_task); 4167} 4168 4169static void igb_watchdog_task(struct work_struct *work) 4170{ 4171 struct igb_adapter *adapter = container_of(work, 4172 struct igb_adapter, 4173 watchdog_task); 4174 struct e1000_hw *hw = &adapter->hw; 4175 struct e1000_phy_info *phy = &hw->phy; 4176 struct net_device *netdev = adapter->netdev; 4177 u32 link; 4178 int i; 4179 u32 connsw; 4180 4181 link = igb_has_link(adapter); 4182 4183 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4184 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4185 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4186 else 4187 link = false; 4188 } 4189 4190 /* Force link down if we have fiber to swap to */ 4191 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4192 if (hw->phy.media_type == e1000_media_type_copper) { 4193 connsw = rd32(E1000_CONNSW); 4194 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4195 link = 0; 4196 } 4197 } 4198 if (link) { 4199 /* Perform a reset if the media type changed. */ 4200 if (hw->dev_spec._82575.media_changed) { 4201 hw->dev_spec._82575.media_changed = false; 4202 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4203 igb_reset(adapter); 4204 } 4205 /* Cancel scheduled suspend requests. */ 4206 pm_runtime_resume(netdev->dev.parent); 4207 4208 if (!netif_carrier_ok(netdev)) { 4209 u32 ctrl; 4210 4211 hw->mac.ops.get_speed_and_duplex(hw, 4212 &adapter->link_speed, 4213 &adapter->link_duplex); 4214 4215 ctrl = rd32(E1000_CTRL); 4216 /* Links status message must follow this format */ 4217 netdev_info(netdev, 4218 "igb: %s NIC Link is Up %d Mbps %s Duplex, Flow Control: %s\n", 4219 netdev->name, 4220 adapter->link_speed, 4221 adapter->link_duplex == FULL_DUPLEX ? 4222 "Full" : "Half", 4223 (ctrl & E1000_CTRL_TFCE) && 4224 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4225 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4226 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4227 4228 /* disable EEE if enabled */ 4229 if ((adapter->flags & IGB_FLAG_EEE) && 4230 (adapter->link_duplex == HALF_DUPLEX)) { 4231 dev_info(&adapter->pdev->dev, 4232 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4233 adapter->hw.dev_spec._82575.eee_disable = true; 4234 adapter->flags &= ~IGB_FLAG_EEE; 4235 } 4236 4237 /* check if SmartSpeed worked */ 4238 igb_check_downshift(hw); 4239 if (phy->speed_downgraded) 4240 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4241 4242 /* check for thermal sensor event */ 4243 if (igb_thermal_sensor_event(hw, 4244 E1000_THSTAT_LINK_THROTTLE)) 4245 netdev_info(netdev, "The network adapter link speed was downshifted because it overheated\n"); 4246 4247 /* adjust timeout factor according to speed/duplex */ 4248 adapter->tx_timeout_factor = 1; 4249 switch (adapter->link_speed) { 4250 case SPEED_10: 4251 adapter->tx_timeout_factor = 14; 4252 break; 4253 case SPEED_100: 4254 /* maybe add some timeout factor ? */ 4255 break; 4256 } 4257 4258 netif_carrier_on(netdev); 4259 4260 igb_ping_all_vfs(adapter); 4261 igb_check_vf_rate_limit(adapter); 4262 4263 /* link state has changed, schedule phy info update */ 4264 if (!test_bit(__IGB_DOWN, &adapter->state)) 4265 mod_timer(&adapter->phy_info_timer, 4266 round_jiffies(jiffies + 2 * HZ)); 4267 } 4268 } else { 4269 if (netif_carrier_ok(netdev)) { 4270 adapter->link_speed = 0; 4271 adapter->link_duplex = 0; 4272 4273 /* check for thermal sensor event */ 4274 if (igb_thermal_sensor_event(hw, 4275 E1000_THSTAT_PWR_DOWN)) { 4276 netdev_err(netdev, "The network adapter was stopped because it overheated\n"); 4277 } 4278 4279 /* Links status message must follow this format */ 4280 netdev_info(netdev, "igb: %s NIC Link is Down\n", 4281 netdev->name); 4282 netif_carrier_off(netdev); 4283 4284 igb_ping_all_vfs(adapter); 4285 4286 /* link state has changed, schedule phy info update */ 4287 if (!test_bit(__IGB_DOWN, &adapter->state)) 4288 mod_timer(&adapter->phy_info_timer, 4289 round_jiffies(jiffies + 2 * HZ)); 4290 4291 /* link is down, time to check for alternate media */ 4292 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4293 igb_check_swap_media(adapter); 4294 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4295 schedule_work(&adapter->reset_task); 4296 /* return immediately */ 4297 return; 4298 } 4299 } 4300 pm_schedule_suspend(netdev->dev.parent, 4301 MSEC_PER_SEC * 5); 4302 4303 /* also check for alternate media here */ 4304 } else if (!netif_carrier_ok(netdev) && 4305 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4306 igb_check_swap_media(adapter); 4307 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4308 schedule_work(&adapter->reset_task); 4309 /* return immediately */ 4310 return; 4311 } 4312 } 4313 } 4314 4315 spin_lock(&adapter->stats64_lock); 4316 igb_update_stats(adapter, &adapter->stats64); 4317 spin_unlock(&adapter->stats64_lock); 4318 4319 for (i = 0; i < adapter->num_tx_queues; i++) { 4320 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4321 if (!netif_carrier_ok(netdev)) { 4322 /* We've lost link, so the controller stops DMA, 4323 * but we've got queued Tx work that's never going 4324 * to get done, so reset controller to flush Tx. 4325 * (Do the reset outside of interrupt context). 4326 */ 4327 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4328 adapter->tx_timeout_count++; 4329 schedule_work(&adapter->reset_task); 4330 /* return immediately since reset is imminent */ 4331 return; 4332 } 4333 } 4334 4335 /* Force detection of hung controller every watchdog period */ 4336 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4337 } 4338 4339 /* Cause software interrupt to ensure Rx ring is cleaned */ 4340 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4341 u32 eics = 0; 4342 4343 for (i = 0; i < adapter->num_q_vectors; i++) 4344 eics |= adapter->q_vector[i]->eims_value; 4345 wr32(E1000_EICS, eics); 4346 } else { 4347 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4348 } 4349 4350 igb_spoof_check(adapter); 4351 igb_ptp_rx_hang(adapter); 4352 4353 /* Reset the timer */ 4354 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4355 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4356 mod_timer(&adapter->watchdog_timer, 4357 round_jiffies(jiffies + HZ)); 4358 else 4359 mod_timer(&adapter->watchdog_timer, 4360 round_jiffies(jiffies + 2 * HZ)); 4361 } 4362} 4363 4364enum latency_range { 4365 lowest_latency = 0, 4366 low_latency = 1, 4367 bulk_latency = 2, 4368 latency_invalid = 255 4369}; 4370 4371/** 4372 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4373 * @q_vector: pointer to q_vector 4374 * 4375 * Stores a new ITR value based on strictly on packet size. This 4376 * algorithm is less sophisticated than that used in igb_update_itr, 4377 * due to the difficulty of synchronizing statistics across multiple 4378 * receive rings. The divisors and thresholds used by this function 4379 * were determined based on theoretical maximum wire speed and testing 4380 * data, in order to minimize response time while increasing bulk 4381 * throughput. 4382 * This functionality is controlled by ethtool's coalescing settings. 4383 * NOTE: This function is called only when operating in a multiqueue 4384 * receive environment. 4385 **/ 4386static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4387{ 4388 int new_val = q_vector->itr_val; 4389 int avg_wire_size = 0; 4390 struct igb_adapter *adapter = q_vector->adapter; 4391 unsigned int packets; 4392 4393 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4394 * ints/sec - ITR timer value of 120 ticks. 4395 */ 4396 if (adapter->link_speed != SPEED_1000) { 4397 new_val = IGB_4K_ITR; 4398 goto set_itr_val; 4399 } 4400 4401 packets = q_vector->rx.total_packets; 4402 if (packets) 4403 avg_wire_size = q_vector->rx.total_bytes / packets; 4404 4405 packets = q_vector->tx.total_packets; 4406 if (packets) 4407 avg_wire_size = max_t(u32, avg_wire_size, 4408 q_vector->tx.total_bytes / packets); 4409 4410 /* if avg_wire_size isn't set no work was done */ 4411 if (!avg_wire_size) 4412 goto clear_counts; 4413 4414 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4415 avg_wire_size += 24; 4416 4417 /* Don't starve jumbo frames */ 4418 avg_wire_size = min(avg_wire_size, 3000); 4419 4420 /* Give a little boost to mid-size frames */ 4421 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4422 new_val = avg_wire_size / 3; 4423 else 4424 new_val = avg_wire_size / 2; 4425 4426 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4427 if (new_val < IGB_20K_ITR && 4428 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4429 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4430 new_val = IGB_20K_ITR; 4431 4432set_itr_val: 4433 if (new_val != q_vector->itr_val) { 4434 q_vector->itr_val = new_val; 4435 q_vector->set_itr = 1; 4436 } 4437clear_counts: 4438 q_vector->rx.total_bytes = 0; 4439 q_vector->rx.total_packets = 0; 4440 q_vector->tx.total_bytes = 0; 4441 q_vector->tx.total_packets = 0; 4442} 4443 4444/** 4445 * igb_update_itr - update the dynamic ITR value based on statistics 4446 * @q_vector: pointer to q_vector 4447 * @ring_container: ring info to update the itr for 4448 * 4449 * Stores a new ITR value based on packets and byte 4450 * counts during the last interrupt. The advantage of per interrupt 4451 * computation is faster updates and more accurate ITR for the current 4452 * traffic pattern. Constants in this function were computed 4453 * based on theoretical maximum wire speed and thresholds were set based 4454 * on testing data as well as attempting to minimize response time 4455 * while increasing bulk throughput. 4456 * This functionality is controlled by ethtool's coalescing settings. 4457 * NOTE: These calculations are only valid when operating in a single- 4458 * queue environment. 4459 **/ 4460static void igb_update_itr(struct igb_q_vector *q_vector, 4461 struct igb_ring_container *ring_container) 4462{ 4463 unsigned int packets = ring_container->total_packets; 4464 unsigned int bytes = ring_container->total_bytes; 4465 u8 itrval = ring_container->itr; 4466 4467 /* no packets, exit with status unchanged */ 4468 if (packets == 0) 4469 return; 4470 4471 switch (itrval) { 4472 case lowest_latency: 4473 /* handle TSO and jumbo frames */ 4474 if (bytes/packets > 8000) 4475 itrval = bulk_latency; 4476 else if ((packets < 5) && (bytes > 512)) 4477 itrval = low_latency; 4478 break; 4479 case low_latency: /* 50 usec aka 20000 ints/s */ 4480 if (bytes > 10000) { 4481 /* this if handles the TSO accounting */ 4482 if (bytes/packets > 8000) 4483 itrval = bulk_latency; 4484 else if ((packets < 10) || ((bytes/packets) > 1200)) 4485 itrval = bulk_latency; 4486 else if ((packets > 35)) 4487 itrval = lowest_latency; 4488 } else if (bytes/packets > 2000) { 4489 itrval = bulk_latency; 4490 } else if (packets <= 2 && bytes < 512) { 4491 itrval = lowest_latency; 4492 } 4493 break; 4494 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4495 if (bytes > 25000) { 4496 if (packets > 35) 4497 itrval = low_latency; 4498 } else if (bytes < 1500) { 4499 itrval = low_latency; 4500 } 4501 break; 4502 } 4503 4504 /* clear work counters since we have the values we need */ 4505 ring_container->total_bytes = 0; 4506 ring_container->total_packets = 0; 4507 4508 /* write updated itr to ring container */ 4509 ring_container->itr = itrval; 4510} 4511 4512static void igb_set_itr(struct igb_q_vector *q_vector) 4513{ 4514 struct igb_adapter *adapter = q_vector->adapter; 4515 u32 new_itr = q_vector->itr_val; 4516 u8 current_itr = 0; 4517 4518 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4519 if (adapter->link_speed != SPEED_1000) { 4520 current_itr = 0; 4521 new_itr = IGB_4K_ITR; 4522 goto set_itr_now; 4523 } 4524 4525 igb_update_itr(q_vector, &q_vector->tx); 4526 igb_update_itr(q_vector, &q_vector->rx); 4527 4528 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4529 4530 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4531 if (current_itr == lowest_latency && 4532 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4533 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4534 current_itr = low_latency; 4535 4536 switch (current_itr) { 4537 /* counts and packets in update_itr are dependent on these numbers */ 4538 case lowest_latency: 4539 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4540 break; 4541 case low_latency: 4542 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4543 break; 4544 case bulk_latency: 4545 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4546 break; 4547 default: 4548 break; 4549 } 4550 4551set_itr_now: 4552 if (new_itr != q_vector->itr_val) { 4553 /* this attempts to bias the interrupt rate towards Bulk 4554 * by adding intermediate steps when interrupt rate is 4555 * increasing 4556 */ 4557 new_itr = new_itr > q_vector->itr_val ? 4558 max((new_itr * q_vector->itr_val) / 4559 (new_itr + (q_vector->itr_val >> 2)), 4560 new_itr) : new_itr; 4561 /* Don't write the value here; it resets the adapter's 4562 * internal timer, and causes us to delay far longer than 4563 * we should between interrupts. Instead, we write the ITR 4564 * value at the beginning of the next interrupt so the timing 4565 * ends up being correct. 4566 */ 4567 q_vector->itr_val = new_itr; 4568 q_vector->set_itr = 1; 4569 } 4570} 4571 4572static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4573 u32 type_tucmd, u32 mss_l4len_idx) 4574{ 4575 struct e1000_adv_tx_context_desc *context_desc; 4576 u16 i = tx_ring->next_to_use; 4577 4578 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4579 4580 i++; 4581 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4582 4583 /* set bits to identify this as an advanced context descriptor */ 4584 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4585 4586 /* For 82575, context index must be unique per ring. */ 4587 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4588 mss_l4len_idx |= tx_ring->reg_idx << 4; 4589 4590 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4591 context_desc->seqnum_seed = 0; 4592 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4593 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4594} 4595 4596static int igb_tso(struct igb_ring *tx_ring, 4597 struct igb_tx_buffer *first, 4598 u8 *hdr_len) 4599{ 4600 struct sk_buff *skb = first->skb; 4601 u32 vlan_macip_lens, type_tucmd; 4602 u32 mss_l4len_idx, l4len; 4603 int err; 4604 4605 if (skb->ip_summed != CHECKSUM_PARTIAL) 4606 return 0; 4607 4608 if (!skb_is_gso(skb)) 4609 return 0; 4610 4611 err = skb_cow_head(skb, 0); 4612 if (err < 0) 4613 return err; 4614 4615 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4616 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4617 4618 if (first->protocol == htons(ETH_P_IP)) { 4619 struct iphdr *iph = ip_hdr(skb); 4620 iph->tot_len = 0; 4621 iph->check = 0; 4622 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4623 iph->daddr, 0, 4624 IPPROTO_TCP, 4625 0); 4626 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4627 first->tx_flags |= IGB_TX_FLAGS_TSO | 4628 IGB_TX_FLAGS_CSUM | 4629 IGB_TX_FLAGS_IPV4; 4630 } else if (skb_is_gso_v6(skb)) { 4631 ipv6_hdr(skb)->payload_len = 0; 4632 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4633 &ipv6_hdr(skb)->daddr, 4634 0, IPPROTO_TCP, 0); 4635 first->tx_flags |= IGB_TX_FLAGS_TSO | 4636 IGB_TX_FLAGS_CSUM; 4637 } 4638 4639 /* compute header lengths */ 4640 l4len = tcp_hdrlen(skb); 4641 *hdr_len = skb_transport_offset(skb) + l4len; 4642 4643 /* update gso size and bytecount with header size */ 4644 first->gso_segs = skb_shinfo(skb)->gso_segs; 4645 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4646 4647 /* MSS L4LEN IDX */ 4648 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4649 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4650 4651 /* VLAN MACLEN IPLEN */ 4652 vlan_macip_lens = skb_network_header_len(skb); 4653 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4654 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4655 4656 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4657 4658 return 1; 4659} 4660 4661static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4662{ 4663 struct sk_buff *skb = first->skb; 4664 u32 vlan_macip_lens = 0; 4665 u32 mss_l4len_idx = 0; 4666 u32 type_tucmd = 0; 4667 4668 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4669 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4670 return; 4671 } else { 4672 u8 l4_hdr = 0; 4673 4674 switch (first->protocol) { 4675 case htons(ETH_P_IP): 4676 vlan_macip_lens |= skb_network_header_len(skb); 4677 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4678 l4_hdr = ip_hdr(skb)->protocol; 4679 break; 4680 case htons(ETH_P_IPV6): 4681 vlan_macip_lens |= skb_network_header_len(skb); 4682 l4_hdr = ipv6_hdr(skb)->nexthdr; 4683 break; 4684 default: 4685 if (unlikely(net_ratelimit())) { 4686 dev_warn(tx_ring->dev, 4687 "partial checksum but proto=%x!\n", 4688 first->protocol); 4689 } 4690 break; 4691 } 4692 4693 switch (l4_hdr) { 4694 case IPPROTO_TCP: 4695 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4696 mss_l4len_idx = tcp_hdrlen(skb) << 4697 E1000_ADVTXD_L4LEN_SHIFT; 4698 break; 4699 case IPPROTO_SCTP: 4700 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4701 mss_l4len_idx = sizeof(struct sctphdr) << 4702 E1000_ADVTXD_L4LEN_SHIFT; 4703 break; 4704 case IPPROTO_UDP: 4705 mss_l4len_idx = sizeof(struct udphdr) << 4706 E1000_ADVTXD_L4LEN_SHIFT; 4707 break; 4708 default: 4709 if (unlikely(net_ratelimit())) { 4710 dev_warn(tx_ring->dev, 4711 "partial checksum but l4 proto=%x!\n", 4712 l4_hdr); 4713 } 4714 break; 4715 } 4716 4717 /* update TX checksum flag */ 4718 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4719 } 4720 4721 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4722 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4723 4724 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4725} 4726 4727#define IGB_SET_FLAG(_input, _flag, _result) \ 4728 ((_flag <= _result) ? \ 4729 ((u32)(_input & _flag) * (_result / _flag)) : \ 4730 ((u32)(_input & _flag) / (_flag / _result))) 4731 4732static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 4733{ 4734 /* set type for advanced descriptor with frame checksum insertion */ 4735 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 4736 E1000_ADVTXD_DCMD_DEXT | 4737 E1000_ADVTXD_DCMD_IFCS; 4738 4739 /* set HW vlan bit if vlan is present */ 4740 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 4741 (E1000_ADVTXD_DCMD_VLE)); 4742 4743 /* set segmentation bits for TSO */ 4744 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 4745 (E1000_ADVTXD_DCMD_TSE)); 4746 4747 /* set timestamp bit if present */ 4748 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 4749 (E1000_ADVTXD_MAC_TSTAMP)); 4750 4751 /* insert frame checksum */ 4752 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 4753 4754 return cmd_type; 4755} 4756 4757static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4758 union e1000_adv_tx_desc *tx_desc, 4759 u32 tx_flags, unsigned int paylen) 4760{ 4761 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4762 4763 /* 82575 requires a unique index per ring */ 4764 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4765 olinfo_status |= tx_ring->reg_idx << 4; 4766 4767 /* insert L4 checksum */ 4768 olinfo_status |= IGB_SET_FLAG(tx_flags, 4769 IGB_TX_FLAGS_CSUM, 4770 (E1000_TXD_POPTS_TXSM << 8)); 4771 4772 /* insert IPv4 checksum */ 4773 olinfo_status |= IGB_SET_FLAG(tx_flags, 4774 IGB_TX_FLAGS_IPV4, 4775 (E1000_TXD_POPTS_IXSM << 8)); 4776 4777 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4778} 4779 4780static void igb_tx_map(struct igb_ring *tx_ring, 4781 struct igb_tx_buffer *first, 4782 const u8 hdr_len) 4783{ 4784 struct sk_buff *skb = first->skb; 4785 struct igb_tx_buffer *tx_buffer; 4786 union e1000_adv_tx_desc *tx_desc; 4787 struct skb_frag_struct *frag; 4788 dma_addr_t dma; 4789 unsigned int data_len, size; 4790 u32 tx_flags = first->tx_flags; 4791 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 4792 u16 i = tx_ring->next_to_use; 4793 4794 tx_desc = IGB_TX_DESC(tx_ring, i); 4795 4796 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 4797 4798 size = skb_headlen(skb); 4799 data_len = skb->data_len; 4800 4801 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4802 4803 tx_buffer = first; 4804 4805 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 4806 if (dma_mapping_error(tx_ring->dev, dma)) 4807 goto dma_error; 4808 4809 /* record length, and DMA address */ 4810 dma_unmap_len_set(tx_buffer, len, size); 4811 dma_unmap_addr_set(tx_buffer, dma, dma); 4812 4813 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4814 4815 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4816 tx_desc->read.cmd_type_len = 4817 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 4818 4819 i++; 4820 tx_desc++; 4821 if (i == tx_ring->count) { 4822 tx_desc = IGB_TX_DESC(tx_ring, 0); 4823 i = 0; 4824 } 4825 tx_desc->read.olinfo_status = 0; 4826 4827 dma += IGB_MAX_DATA_PER_TXD; 4828 size -= IGB_MAX_DATA_PER_TXD; 4829 4830 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4831 } 4832 4833 if (likely(!data_len)) 4834 break; 4835 4836 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 4837 4838 i++; 4839 tx_desc++; 4840 if (i == tx_ring->count) { 4841 tx_desc = IGB_TX_DESC(tx_ring, 0); 4842 i = 0; 4843 } 4844 tx_desc->read.olinfo_status = 0; 4845 4846 size = skb_frag_size(frag); 4847 data_len -= size; 4848 4849 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4850 size, DMA_TO_DEVICE); 4851 4852 tx_buffer = &tx_ring->tx_buffer_info[i]; 4853 } 4854 4855 /* write last descriptor with RS and EOP bits */ 4856 cmd_type |= size | IGB_TXD_DCMD; 4857 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 4858 4859 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4860 4861 /* set the timestamp */ 4862 first->time_stamp = jiffies; 4863 4864 /* Force memory writes to complete before letting h/w know there 4865 * are new descriptors to fetch. (Only applicable for weak-ordered 4866 * memory model archs, such as IA-64). 4867 * 4868 * We also need this memory barrier to make certain all of the 4869 * status bits have been updated before next_to_watch is written. 4870 */ 4871 wmb(); 4872 4873 /* set next_to_watch value indicating a packet is present */ 4874 first->next_to_watch = tx_desc; 4875 4876 i++; 4877 if (i == tx_ring->count) 4878 i = 0; 4879 4880 tx_ring->next_to_use = i; 4881 4882 writel(i, tx_ring->tail); 4883 4884 /* we need this if more than one processor can write to our tail 4885 * at a time, it synchronizes IO on IA64/Altix systems 4886 */ 4887 mmiowb(); 4888 4889 return; 4890 4891dma_error: 4892 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4893 4894 /* clear dma mappings for failed tx_buffer_info map */ 4895 for (;;) { 4896 tx_buffer = &tx_ring->tx_buffer_info[i]; 4897 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4898 if (tx_buffer == first) 4899 break; 4900 if (i == 0) 4901 i = tx_ring->count; 4902 i--; 4903 } 4904 4905 tx_ring->next_to_use = i; 4906} 4907 4908static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4909{ 4910 struct net_device *netdev = tx_ring->netdev; 4911 4912 netif_stop_subqueue(netdev, tx_ring->queue_index); 4913 4914 /* Herbert's original patch had: 4915 * smp_mb__after_netif_stop_queue(); 4916 * but since that doesn't exist yet, just open code it. 4917 */ 4918 smp_mb(); 4919 4920 /* We need to check again in a case another CPU has just 4921 * made room available. 4922 */ 4923 if (igb_desc_unused(tx_ring) < size) 4924 return -EBUSY; 4925 4926 /* A reprieve! */ 4927 netif_wake_subqueue(netdev, tx_ring->queue_index); 4928 4929 u64_stats_update_begin(&tx_ring->tx_syncp2); 4930 tx_ring->tx_stats.restart_queue2++; 4931 u64_stats_update_end(&tx_ring->tx_syncp2); 4932 4933 return 0; 4934} 4935 4936static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4937{ 4938 if (igb_desc_unused(tx_ring) >= size) 4939 return 0; 4940 return __igb_maybe_stop_tx(tx_ring, size); 4941} 4942 4943netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4944 struct igb_ring *tx_ring) 4945{ 4946 struct igb_tx_buffer *first; 4947 int tso; 4948 u32 tx_flags = 0; 4949 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 4950 __be16 protocol = vlan_get_protocol(skb); 4951 u8 hdr_len = 0; 4952 4953 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 4954 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 4955 * + 2 desc gap to keep tail from touching head, 4956 * + 1 desc for context descriptor, 4957 * otherwise try next time 4958 */ 4959 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) { 4960 unsigned short f; 4961 4962 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 4963 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 4964 } else { 4965 count += skb_shinfo(skb)->nr_frags; 4966 } 4967 4968 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 4969 /* this is a hard error */ 4970 return NETDEV_TX_BUSY; 4971 } 4972 4973 /* record the location of the first descriptor for this packet */ 4974 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 4975 first->skb = skb; 4976 first->bytecount = skb->len; 4977 first->gso_segs = 1; 4978 4979 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 4980 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 4981 4982 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 4983 &adapter->state)) { 4984 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4985 tx_flags |= IGB_TX_FLAGS_TSTAMP; 4986 4987 adapter->ptp_tx_skb = skb_get(skb); 4988 adapter->ptp_tx_start = jiffies; 4989 if (adapter->hw.mac.type == e1000_82576) 4990 schedule_work(&adapter->ptp_tx_work); 4991 } 4992 } 4993 4994 skb_tx_timestamp(skb); 4995 4996 if (vlan_tx_tag_present(skb)) { 4997 tx_flags |= IGB_TX_FLAGS_VLAN; 4998 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 4999 } 5000 5001 /* record initial flags and protocol */ 5002 first->tx_flags = tx_flags; 5003 first->protocol = protocol; 5004 5005 tso = igb_tso(tx_ring, first, &hdr_len); 5006 if (tso < 0) 5007 goto out_drop; 5008 else if (!tso) 5009 igb_tx_csum(tx_ring, first); 5010 5011 igb_tx_map(tx_ring, first, hdr_len); 5012 5013 /* Make sure there is space in the ring for the next send. */ 5014 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 5015 5016 return NETDEV_TX_OK; 5017 5018out_drop: 5019 igb_unmap_and_free_tx_resource(tx_ring, first); 5020 5021 return NETDEV_TX_OK; 5022} 5023 5024static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5025 struct sk_buff *skb) 5026{ 5027 unsigned int r_idx = skb->queue_mapping; 5028 5029 if (r_idx >= adapter->num_tx_queues) 5030 r_idx = r_idx % adapter->num_tx_queues; 5031 5032 return adapter->tx_ring[r_idx]; 5033} 5034 5035static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5036 struct net_device *netdev) 5037{ 5038 struct igb_adapter *adapter = netdev_priv(netdev); 5039 5040 if (test_bit(__IGB_DOWN, &adapter->state)) { 5041 dev_kfree_skb_any(skb); 5042 return NETDEV_TX_OK; 5043 } 5044 5045 if (skb->len <= 0) { 5046 dev_kfree_skb_any(skb); 5047 return NETDEV_TX_OK; 5048 } 5049 5050 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5051 * in order to meet this minimum size requirement. 5052 */ 5053 if (unlikely(skb->len < 17)) { 5054 if (skb_pad(skb, 17 - skb->len)) 5055 return NETDEV_TX_OK; 5056 skb->len = 17; 5057 skb_set_tail_pointer(skb, 17); 5058 } 5059 5060 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5061} 5062 5063/** 5064 * igb_tx_timeout - Respond to a Tx Hang 5065 * @netdev: network interface device structure 5066 **/ 5067static void igb_tx_timeout(struct net_device *netdev) 5068{ 5069 struct igb_adapter *adapter = netdev_priv(netdev); 5070 struct e1000_hw *hw = &adapter->hw; 5071 5072 /* Do the reset outside of interrupt context */ 5073 adapter->tx_timeout_count++; 5074 5075 if (hw->mac.type >= e1000_82580) 5076 hw->dev_spec._82575.global_device_reset = true; 5077 5078 schedule_work(&adapter->reset_task); 5079 wr32(E1000_EICS, 5080 (adapter->eims_enable_mask & ~adapter->eims_other)); 5081} 5082 5083static void igb_reset_task(struct work_struct *work) 5084{ 5085 struct igb_adapter *adapter; 5086 adapter = container_of(work, struct igb_adapter, reset_task); 5087 5088 igb_dump(adapter); 5089 netdev_err(adapter->netdev, "Reset adapter\n"); 5090 igb_reinit_locked(adapter); 5091} 5092 5093/** 5094 * igb_get_stats64 - Get System Network Statistics 5095 * @netdev: network interface device structure 5096 * @stats: rtnl_link_stats64 pointer 5097 **/ 5098static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 5099 struct rtnl_link_stats64 *stats) 5100{ 5101 struct igb_adapter *adapter = netdev_priv(netdev); 5102 5103 spin_lock(&adapter->stats64_lock); 5104 igb_update_stats(adapter, &adapter->stats64); 5105 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5106 spin_unlock(&adapter->stats64_lock); 5107 5108 return stats; 5109} 5110 5111/** 5112 * igb_change_mtu - Change the Maximum Transfer Unit 5113 * @netdev: network interface device structure 5114 * @new_mtu: new value for maximum frame size 5115 * 5116 * Returns 0 on success, negative on failure 5117 **/ 5118static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5119{ 5120 struct igb_adapter *adapter = netdev_priv(netdev); 5121 struct pci_dev *pdev = adapter->pdev; 5122 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5123 5124 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 5125 dev_err(&pdev->dev, "Invalid MTU setting\n"); 5126 return -EINVAL; 5127 } 5128 5129#define MAX_STD_JUMBO_FRAME_SIZE 9238 5130 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 5131 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 5132 return -EINVAL; 5133 } 5134 5135 /* adjust max frame to be at least the size of a standard frame */ 5136 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5137 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5138 5139 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5140 msleep(1); 5141 5142 /* igb_down has a dependency on max_frame_size */ 5143 adapter->max_frame_size = max_frame; 5144 5145 if (netif_running(netdev)) 5146 igb_down(adapter); 5147 5148 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5149 netdev->mtu, new_mtu); 5150 netdev->mtu = new_mtu; 5151 5152 if (netif_running(netdev)) 5153 igb_up(adapter); 5154 else 5155 igb_reset(adapter); 5156 5157 clear_bit(__IGB_RESETTING, &adapter->state); 5158 5159 return 0; 5160} 5161 5162/** 5163 * igb_update_stats - Update the board statistics counters 5164 * @adapter: board private structure 5165 **/ 5166void igb_update_stats(struct igb_adapter *adapter, 5167 struct rtnl_link_stats64 *net_stats) 5168{ 5169 struct e1000_hw *hw = &adapter->hw; 5170 struct pci_dev *pdev = adapter->pdev; 5171 u32 reg, mpc; 5172 u16 phy_tmp; 5173 int i; 5174 u64 bytes, packets; 5175 unsigned int start; 5176 u64 _bytes, _packets; 5177 5178#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF 5179 5180 /* Prevent stats update while adapter is being reset, or if the pci 5181 * connection is down. 5182 */ 5183 if (adapter->link_speed == 0) 5184 return; 5185 if (pci_channel_offline(pdev)) 5186 return; 5187 5188 bytes = 0; 5189 packets = 0; 5190 5191 rcu_read_lock(); 5192 for (i = 0; i < adapter->num_rx_queues; i++) { 5193 struct igb_ring *ring = adapter->rx_ring[i]; 5194 u32 rqdpc = rd32(E1000_RQDPC(i)); 5195 if (hw->mac.type >= e1000_i210) 5196 wr32(E1000_RQDPC(i), 0); 5197 5198 if (rqdpc) { 5199 ring->rx_stats.drops += rqdpc; 5200 net_stats->rx_fifo_errors += rqdpc; 5201 } 5202 5203 do { 5204 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5205 _bytes = ring->rx_stats.bytes; 5206 _packets = ring->rx_stats.packets; 5207 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5208 bytes += _bytes; 5209 packets += _packets; 5210 } 5211 5212 net_stats->rx_bytes = bytes; 5213 net_stats->rx_packets = packets; 5214 5215 bytes = 0; 5216 packets = 0; 5217 for (i = 0; i < adapter->num_tx_queues; i++) { 5218 struct igb_ring *ring = adapter->tx_ring[i]; 5219 do { 5220 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5221 _bytes = ring->tx_stats.bytes; 5222 _packets = ring->tx_stats.packets; 5223 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5224 bytes += _bytes; 5225 packets += _packets; 5226 } 5227 net_stats->tx_bytes = bytes; 5228 net_stats->tx_packets = packets; 5229 rcu_read_unlock(); 5230 5231 /* read stats registers */ 5232 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5233 adapter->stats.gprc += rd32(E1000_GPRC); 5234 adapter->stats.gorc += rd32(E1000_GORCL); 5235 rd32(E1000_GORCH); /* clear GORCL */ 5236 adapter->stats.bprc += rd32(E1000_BPRC); 5237 adapter->stats.mprc += rd32(E1000_MPRC); 5238 adapter->stats.roc += rd32(E1000_ROC); 5239 5240 adapter->stats.prc64 += rd32(E1000_PRC64); 5241 adapter->stats.prc127 += rd32(E1000_PRC127); 5242 adapter->stats.prc255 += rd32(E1000_PRC255); 5243 adapter->stats.prc511 += rd32(E1000_PRC511); 5244 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5245 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5246 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5247 adapter->stats.sec += rd32(E1000_SEC); 5248 5249 mpc = rd32(E1000_MPC); 5250 adapter->stats.mpc += mpc; 5251 net_stats->rx_fifo_errors += mpc; 5252 adapter->stats.scc += rd32(E1000_SCC); 5253 adapter->stats.ecol += rd32(E1000_ECOL); 5254 adapter->stats.mcc += rd32(E1000_MCC); 5255 adapter->stats.latecol += rd32(E1000_LATECOL); 5256 adapter->stats.dc += rd32(E1000_DC); 5257 adapter->stats.rlec += rd32(E1000_RLEC); 5258 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5259 adapter->stats.xontxc += rd32(E1000_XONTXC); 5260 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5261 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5262 adapter->stats.fcruc += rd32(E1000_FCRUC); 5263 adapter->stats.gptc += rd32(E1000_GPTC); 5264 adapter->stats.gotc += rd32(E1000_GOTCL); 5265 rd32(E1000_GOTCH); /* clear GOTCL */ 5266 adapter->stats.rnbc += rd32(E1000_RNBC); 5267 adapter->stats.ruc += rd32(E1000_RUC); 5268 adapter->stats.rfc += rd32(E1000_RFC); 5269 adapter->stats.rjc += rd32(E1000_RJC); 5270 adapter->stats.tor += rd32(E1000_TORH); 5271 adapter->stats.tot += rd32(E1000_TOTH); 5272 adapter->stats.tpr += rd32(E1000_TPR); 5273 5274 adapter->stats.ptc64 += rd32(E1000_PTC64); 5275 adapter->stats.ptc127 += rd32(E1000_PTC127); 5276 adapter->stats.ptc255 += rd32(E1000_PTC255); 5277 adapter->stats.ptc511 += rd32(E1000_PTC511); 5278 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5279 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5280 5281 adapter->stats.mptc += rd32(E1000_MPTC); 5282 adapter->stats.bptc += rd32(E1000_BPTC); 5283 5284 adapter->stats.tpt += rd32(E1000_TPT); 5285 adapter->stats.colc += rd32(E1000_COLC); 5286 5287 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5288 /* read internal phy specific stats */ 5289 reg = rd32(E1000_CTRL_EXT); 5290 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5291 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5292 5293 /* this stat has invalid values on i210/i211 */ 5294 if ((hw->mac.type != e1000_i210) && 5295 (hw->mac.type != e1000_i211)) 5296 adapter->stats.tncrs += rd32(E1000_TNCRS); 5297 } 5298 5299 adapter->stats.tsctc += rd32(E1000_TSCTC); 5300 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5301 5302 adapter->stats.iac += rd32(E1000_IAC); 5303 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5304 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5305 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5306 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5307 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5308 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5309 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5310 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5311 5312 /* Fill out the OS statistics structure */ 5313 net_stats->multicast = adapter->stats.mprc; 5314 net_stats->collisions = adapter->stats.colc; 5315 5316 /* Rx Errors */ 5317 5318 /* RLEC on some newer hardware can be incorrect so build 5319 * our own version based on RUC and ROC 5320 */ 5321 net_stats->rx_errors = adapter->stats.rxerrc + 5322 adapter->stats.crcerrs + adapter->stats.algnerrc + 5323 adapter->stats.ruc + adapter->stats.roc + 5324 adapter->stats.cexterr; 5325 net_stats->rx_length_errors = adapter->stats.ruc + 5326 adapter->stats.roc; 5327 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5328 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5329 net_stats->rx_missed_errors = adapter->stats.mpc; 5330 5331 /* Tx Errors */ 5332 net_stats->tx_errors = adapter->stats.ecol + 5333 adapter->stats.latecol; 5334 net_stats->tx_aborted_errors = adapter->stats.ecol; 5335 net_stats->tx_window_errors = adapter->stats.latecol; 5336 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5337 5338 /* Tx Dropped needs to be maintained elsewhere */ 5339 5340 /* Phy Stats */ 5341 if (hw->phy.media_type == e1000_media_type_copper) { 5342 if ((adapter->link_speed == SPEED_1000) && 5343 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 5344 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; 5345 adapter->phy_stats.idle_errors += phy_tmp; 5346 } 5347 } 5348 5349 /* Management Stats */ 5350 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5351 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5352 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5353 5354 /* OS2BMC Stats */ 5355 reg = rd32(E1000_MANC); 5356 if (reg & E1000_MANC_EN_BMC2OS) { 5357 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5358 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5359 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5360 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5361 } 5362} 5363 5364static irqreturn_t igb_msix_other(int irq, void *data) 5365{ 5366 struct igb_adapter *adapter = data; 5367 struct e1000_hw *hw = &adapter->hw; 5368 u32 icr = rd32(E1000_ICR); 5369 /* reading ICR causes bit 31 of EICR to be cleared */ 5370 5371 if (icr & E1000_ICR_DRSTA) 5372 schedule_work(&adapter->reset_task); 5373 5374 if (icr & E1000_ICR_DOUTSYNC) { 5375 /* HW is reporting DMA is out of sync */ 5376 adapter->stats.doosync++; 5377 /* The DMA Out of Sync is also indication of a spoof event 5378 * in IOV mode. Check the Wrong VM Behavior register to 5379 * see if it is really a spoof event. 5380 */ 5381 igb_check_wvbr(adapter); 5382 } 5383 5384 /* Check for a mailbox event */ 5385 if (icr & E1000_ICR_VMMB) 5386 igb_msg_task(adapter); 5387 5388 if (icr & E1000_ICR_LSC) { 5389 hw->mac.get_link_status = 1; 5390 /* guard against interrupt when we're going down */ 5391 if (!test_bit(__IGB_DOWN, &adapter->state)) 5392 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5393 } 5394 5395 if (icr & E1000_ICR_TS) { 5396 u32 tsicr = rd32(E1000_TSICR); 5397 5398 if (tsicr & E1000_TSICR_TXTS) { 5399 /* acknowledge the interrupt */ 5400 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5401 /* retrieve hardware timestamp */ 5402 schedule_work(&adapter->ptp_tx_work); 5403 } 5404 } 5405 5406 wr32(E1000_EIMS, adapter->eims_other); 5407 5408 return IRQ_HANDLED; 5409} 5410 5411static void igb_write_itr(struct igb_q_vector *q_vector) 5412{ 5413 struct igb_adapter *adapter = q_vector->adapter; 5414 u32 itr_val = q_vector->itr_val & 0x7FFC; 5415 5416 if (!q_vector->set_itr) 5417 return; 5418 5419 if (!itr_val) 5420 itr_val = 0x4; 5421 5422 if (adapter->hw.mac.type == e1000_82575) 5423 itr_val |= itr_val << 16; 5424 else 5425 itr_val |= E1000_EITR_CNT_IGNR; 5426 5427 writel(itr_val, q_vector->itr_register); 5428 q_vector->set_itr = 0; 5429} 5430 5431static irqreturn_t igb_msix_ring(int irq, void *data) 5432{ 5433 struct igb_q_vector *q_vector = data; 5434 5435 /* Write the ITR value calculated from the previous interrupt. */ 5436 igb_write_itr(q_vector); 5437 5438 napi_schedule(&q_vector->napi); 5439 5440 return IRQ_HANDLED; 5441} 5442 5443#ifdef CONFIG_IGB_DCA 5444static void igb_update_tx_dca(struct igb_adapter *adapter, 5445 struct igb_ring *tx_ring, 5446 int cpu) 5447{ 5448 struct e1000_hw *hw = &adapter->hw; 5449 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5450 5451 if (hw->mac.type != e1000_82575) 5452 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5453 5454 /* We can enable relaxed ordering for reads, but not writes when 5455 * DCA is enabled. This is due to a known issue in some chipsets 5456 * which will cause the DCA tag to be cleared. 5457 */ 5458 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5459 E1000_DCA_TXCTRL_DATA_RRO_EN | 5460 E1000_DCA_TXCTRL_DESC_DCA_EN; 5461 5462 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5463} 5464 5465static void igb_update_rx_dca(struct igb_adapter *adapter, 5466 struct igb_ring *rx_ring, 5467 int cpu) 5468{ 5469 struct e1000_hw *hw = &adapter->hw; 5470 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5471 5472 if (hw->mac.type != e1000_82575) 5473 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5474 5475 /* We can enable relaxed ordering for reads, but not writes when 5476 * DCA is enabled. This is due to a known issue in some chipsets 5477 * which will cause the DCA tag to be cleared. 5478 */ 5479 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5480 E1000_DCA_RXCTRL_DESC_DCA_EN; 5481 5482 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5483} 5484 5485static void igb_update_dca(struct igb_q_vector *q_vector) 5486{ 5487 struct igb_adapter *adapter = q_vector->adapter; 5488 int cpu = get_cpu(); 5489 5490 if (q_vector->cpu == cpu) 5491 goto out_no_update; 5492 5493 if (q_vector->tx.ring) 5494 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5495 5496 if (q_vector->rx.ring) 5497 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5498 5499 q_vector->cpu = cpu; 5500out_no_update: 5501 put_cpu(); 5502} 5503 5504static void igb_setup_dca(struct igb_adapter *adapter) 5505{ 5506 struct e1000_hw *hw = &adapter->hw; 5507 int i; 5508 5509 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5510 return; 5511 5512 /* Always use CB2 mode, difference is masked in the CB driver. */ 5513 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5514 5515 for (i = 0; i < adapter->num_q_vectors; i++) { 5516 adapter->q_vector[i]->cpu = -1; 5517 igb_update_dca(adapter->q_vector[i]); 5518 } 5519} 5520 5521static int __igb_notify_dca(struct device *dev, void *data) 5522{ 5523 struct net_device *netdev = dev_get_drvdata(dev); 5524 struct igb_adapter *adapter = netdev_priv(netdev); 5525 struct pci_dev *pdev = adapter->pdev; 5526 struct e1000_hw *hw = &adapter->hw; 5527 unsigned long event = *(unsigned long *)data; 5528 5529 switch (event) { 5530 case DCA_PROVIDER_ADD: 5531 /* if already enabled, don't do it again */ 5532 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5533 break; 5534 if (dca_add_requester(dev) == 0) { 5535 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5536 dev_info(&pdev->dev, "DCA enabled\n"); 5537 igb_setup_dca(adapter); 5538 break; 5539 } 5540 /* Fall Through since DCA is disabled. */ 5541 case DCA_PROVIDER_REMOVE: 5542 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5543 /* without this a class_device is left 5544 * hanging around in the sysfs model 5545 */ 5546 dca_remove_requester(dev); 5547 dev_info(&pdev->dev, "DCA disabled\n"); 5548 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5549 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5550 } 5551 break; 5552 } 5553 5554 return 0; 5555} 5556 5557static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5558 void *p) 5559{ 5560 int ret_val; 5561 5562 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5563 __igb_notify_dca); 5564 5565 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5566} 5567#endif /* CONFIG_IGB_DCA */ 5568 5569#ifdef CONFIG_PCI_IOV 5570static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5571{ 5572 unsigned char mac_addr[ETH_ALEN]; 5573 5574 eth_zero_addr(mac_addr); 5575 igb_set_vf_mac(adapter, vf, mac_addr); 5576 5577 /* By default spoof check is enabled for all VFs */ 5578 adapter->vf_data[vf].spoofchk_enabled = true; 5579 5580 return 0; 5581} 5582 5583#endif 5584static void igb_ping_all_vfs(struct igb_adapter *adapter) 5585{ 5586 struct e1000_hw *hw = &adapter->hw; 5587 u32 ping; 5588 int i; 5589 5590 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5591 ping = E1000_PF_CONTROL_MSG; 5592 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5593 ping |= E1000_VT_MSGTYPE_CTS; 5594 igb_write_mbx(hw, &ping, 1, i); 5595 } 5596} 5597 5598static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5599{ 5600 struct e1000_hw *hw = &adapter->hw; 5601 u32 vmolr = rd32(E1000_VMOLR(vf)); 5602 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5603 5604 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5605 IGB_VF_FLAG_MULTI_PROMISC); 5606 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5607 5608 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5609 vmolr |= E1000_VMOLR_MPME; 5610 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5611 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5612 } else { 5613 /* if we have hashes and we are clearing a multicast promisc 5614 * flag we need to write the hashes to the MTA as this step 5615 * was previously skipped 5616 */ 5617 if (vf_data->num_vf_mc_hashes > 30) { 5618 vmolr |= E1000_VMOLR_MPME; 5619 } else if (vf_data->num_vf_mc_hashes) { 5620 int j; 5621 5622 vmolr |= E1000_VMOLR_ROMPE; 5623 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5624 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5625 } 5626 } 5627 5628 wr32(E1000_VMOLR(vf), vmolr); 5629 5630 /* there are flags left unprocessed, likely not supported */ 5631 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5632 return -EINVAL; 5633 5634 return 0; 5635} 5636 5637static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5638 u32 *msgbuf, u32 vf) 5639{ 5640 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5641 u16 *hash_list = (u16 *)&msgbuf[1]; 5642 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5643 int i; 5644 5645 /* salt away the number of multicast addresses assigned 5646 * to this VF for later use to restore when the PF multi cast 5647 * list changes 5648 */ 5649 vf_data->num_vf_mc_hashes = n; 5650 5651 /* only up to 30 hash values supported */ 5652 if (n > 30) 5653 n = 30; 5654 5655 /* store the hashes for later use */ 5656 for (i = 0; i < n; i++) 5657 vf_data->vf_mc_hashes[i] = hash_list[i]; 5658 5659 /* Flush and reset the mta with the new values */ 5660 igb_set_rx_mode(adapter->netdev); 5661 5662 return 0; 5663} 5664 5665static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5666{ 5667 struct e1000_hw *hw = &adapter->hw; 5668 struct vf_data_storage *vf_data; 5669 int i, j; 5670 5671 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5672 u32 vmolr = rd32(E1000_VMOLR(i)); 5673 5674 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5675 5676 vf_data = &adapter->vf_data[i]; 5677 5678 if ((vf_data->num_vf_mc_hashes > 30) || 5679 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5680 vmolr |= E1000_VMOLR_MPME; 5681 } else if (vf_data->num_vf_mc_hashes) { 5682 vmolr |= E1000_VMOLR_ROMPE; 5683 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5684 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5685 } 5686 wr32(E1000_VMOLR(i), vmolr); 5687 } 5688} 5689 5690static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5691{ 5692 struct e1000_hw *hw = &adapter->hw; 5693 u32 pool_mask, reg, vid; 5694 int i; 5695 5696 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5697 5698 /* Find the vlan filter for this id */ 5699 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5700 reg = rd32(E1000_VLVF(i)); 5701 5702 /* remove the vf from the pool */ 5703 reg &= ~pool_mask; 5704 5705 /* if pool is empty then remove entry from vfta */ 5706 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5707 (reg & E1000_VLVF_VLANID_ENABLE)) { 5708 reg = 0; 5709 vid = reg & E1000_VLVF_VLANID_MASK; 5710 igb_vfta_set(hw, vid, false); 5711 } 5712 5713 wr32(E1000_VLVF(i), reg); 5714 } 5715 5716 adapter->vf_data[vf].vlans_enabled = 0; 5717} 5718 5719static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5720{ 5721 struct e1000_hw *hw = &adapter->hw; 5722 u32 reg, i; 5723 5724 /* The vlvf table only exists on 82576 hardware and newer */ 5725 if (hw->mac.type < e1000_82576) 5726 return -1; 5727 5728 /* we only need to do this if VMDq is enabled */ 5729 if (!adapter->vfs_allocated_count) 5730 return -1; 5731 5732 /* Find the vlan filter for this id */ 5733 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5734 reg = rd32(E1000_VLVF(i)); 5735 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5736 vid == (reg & E1000_VLVF_VLANID_MASK)) 5737 break; 5738 } 5739 5740 if (add) { 5741 if (i == E1000_VLVF_ARRAY_SIZE) { 5742 /* Did not find a matching VLAN ID entry that was 5743 * enabled. Search for a free filter entry, i.e. 5744 * one without the enable bit set 5745 */ 5746 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5747 reg = rd32(E1000_VLVF(i)); 5748 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5749 break; 5750 } 5751 } 5752 if (i < E1000_VLVF_ARRAY_SIZE) { 5753 /* Found an enabled/available entry */ 5754 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5755 5756 /* if !enabled we need to set this up in vfta */ 5757 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5758 /* add VID to filter table */ 5759 igb_vfta_set(hw, vid, true); 5760 reg |= E1000_VLVF_VLANID_ENABLE; 5761 } 5762 reg &= ~E1000_VLVF_VLANID_MASK; 5763 reg |= vid; 5764 wr32(E1000_VLVF(i), reg); 5765 5766 /* do not modify RLPML for PF devices */ 5767 if (vf >= adapter->vfs_allocated_count) 5768 return 0; 5769 5770 if (!adapter->vf_data[vf].vlans_enabled) { 5771 u32 size; 5772 5773 reg = rd32(E1000_VMOLR(vf)); 5774 size = reg & E1000_VMOLR_RLPML_MASK; 5775 size += 4; 5776 reg &= ~E1000_VMOLR_RLPML_MASK; 5777 reg |= size; 5778 wr32(E1000_VMOLR(vf), reg); 5779 } 5780 5781 adapter->vf_data[vf].vlans_enabled++; 5782 } 5783 } else { 5784 if (i < E1000_VLVF_ARRAY_SIZE) { 5785 /* remove vf from the pool */ 5786 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5787 /* if pool is empty then remove entry from vfta */ 5788 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5789 reg = 0; 5790 igb_vfta_set(hw, vid, false); 5791 } 5792 wr32(E1000_VLVF(i), reg); 5793 5794 /* do not modify RLPML for PF devices */ 5795 if (vf >= adapter->vfs_allocated_count) 5796 return 0; 5797 5798 adapter->vf_data[vf].vlans_enabled--; 5799 if (!adapter->vf_data[vf].vlans_enabled) { 5800 u32 size; 5801 5802 reg = rd32(E1000_VMOLR(vf)); 5803 size = reg & E1000_VMOLR_RLPML_MASK; 5804 size -= 4; 5805 reg &= ~E1000_VMOLR_RLPML_MASK; 5806 reg |= size; 5807 wr32(E1000_VMOLR(vf), reg); 5808 } 5809 } 5810 } 5811 return 0; 5812} 5813 5814static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5815{ 5816 struct e1000_hw *hw = &adapter->hw; 5817 5818 if (vid) 5819 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5820 else 5821 wr32(E1000_VMVIR(vf), 0); 5822} 5823 5824static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5825 int vf, u16 vlan, u8 qos) 5826{ 5827 int err = 0; 5828 struct igb_adapter *adapter = netdev_priv(netdev); 5829 5830 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5831 return -EINVAL; 5832 if (vlan || qos) { 5833 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5834 if (err) 5835 goto out; 5836 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5837 igb_set_vmolr(adapter, vf, !vlan); 5838 adapter->vf_data[vf].pf_vlan = vlan; 5839 adapter->vf_data[vf].pf_qos = qos; 5840 dev_info(&adapter->pdev->dev, 5841 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5842 if (test_bit(__IGB_DOWN, &adapter->state)) { 5843 dev_warn(&adapter->pdev->dev, 5844 "The VF VLAN has been set, but the PF device is not up.\n"); 5845 dev_warn(&adapter->pdev->dev, 5846 "Bring the PF device up before attempting to use the VF device.\n"); 5847 } 5848 } else { 5849 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5850 false, vf); 5851 igb_set_vmvir(adapter, vlan, vf); 5852 igb_set_vmolr(adapter, vf, true); 5853 adapter->vf_data[vf].pf_vlan = 0; 5854 adapter->vf_data[vf].pf_qos = 0; 5855 } 5856out: 5857 return err; 5858} 5859 5860static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid) 5861{ 5862 struct e1000_hw *hw = &adapter->hw; 5863 int i; 5864 u32 reg; 5865 5866 /* Find the vlan filter for this id */ 5867 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5868 reg = rd32(E1000_VLVF(i)); 5869 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5870 vid == (reg & E1000_VLVF_VLANID_MASK)) 5871 break; 5872 } 5873 5874 if (i >= E1000_VLVF_ARRAY_SIZE) 5875 i = -1; 5876 5877 return i; 5878} 5879 5880static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5881{ 5882 struct e1000_hw *hw = &adapter->hw; 5883 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5884 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5885 int err = 0; 5886 5887 /* If in promiscuous mode we need to make sure the PF also has 5888 * the VLAN filter set. 5889 */ 5890 if (add && (adapter->netdev->flags & IFF_PROMISC)) 5891 err = igb_vlvf_set(adapter, vid, add, 5892 adapter->vfs_allocated_count); 5893 if (err) 5894 goto out; 5895 5896 err = igb_vlvf_set(adapter, vid, add, vf); 5897 5898 if (err) 5899 goto out; 5900 5901 /* Go through all the checks to see if the VLAN filter should 5902 * be wiped completely. 5903 */ 5904 if (!add && (adapter->netdev->flags & IFF_PROMISC)) { 5905 u32 vlvf, bits; 5906 int regndx = igb_find_vlvf_entry(adapter, vid); 5907 5908 if (regndx < 0) 5909 goto out; 5910 /* See if any other pools are set for this VLAN filter 5911 * entry other than the PF. 5912 */ 5913 vlvf = bits = rd32(E1000_VLVF(regndx)); 5914 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT + 5915 adapter->vfs_allocated_count); 5916 /* If the filter was removed then ensure PF pool bit 5917 * is cleared if the PF only added itself to the pool 5918 * because the PF is in promiscuous mode. 5919 */ 5920 if ((vlvf & VLAN_VID_MASK) == vid && 5921 !test_bit(vid, adapter->active_vlans) && 5922 !bits) 5923 igb_vlvf_set(adapter, vid, add, 5924 adapter->vfs_allocated_count); 5925 } 5926 5927out: 5928 return err; 5929} 5930 5931static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 5932{ 5933 /* clear flags - except flag that indicates PF has set the MAC */ 5934 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 5935 adapter->vf_data[vf].last_nack = jiffies; 5936 5937 /* reset offloads to defaults */ 5938 igb_set_vmolr(adapter, vf, true); 5939 5940 /* reset vlans for device */ 5941 igb_clear_vf_vfta(adapter, vf); 5942 if (adapter->vf_data[vf].pf_vlan) 5943 igb_ndo_set_vf_vlan(adapter->netdev, vf, 5944 adapter->vf_data[vf].pf_vlan, 5945 adapter->vf_data[vf].pf_qos); 5946 else 5947 igb_clear_vf_vfta(adapter, vf); 5948 5949 /* reset multicast table array for vf */ 5950 adapter->vf_data[vf].num_vf_mc_hashes = 0; 5951 5952 /* Flush and reset the mta with the new values */ 5953 igb_set_rx_mode(adapter->netdev); 5954} 5955 5956static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 5957{ 5958 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5959 5960 /* clear mac address as we were hotplug removed/added */ 5961 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 5962 eth_zero_addr(vf_mac); 5963 5964 /* process remaining reset events */ 5965 igb_vf_reset(adapter, vf); 5966} 5967 5968static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 5969{ 5970 struct e1000_hw *hw = &adapter->hw; 5971 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5972 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 5973 u32 reg, msgbuf[3]; 5974 u8 *addr = (u8 *)(&msgbuf[1]); 5975 5976 /* process all the same items cleared in a function level reset */ 5977 igb_vf_reset(adapter, vf); 5978 5979 /* set vf mac address */ 5980 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 5981 5982 /* enable transmit and receive for vf */ 5983 reg = rd32(E1000_VFTE); 5984 wr32(E1000_VFTE, reg | (1 << vf)); 5985 reg = rd32(E1000_VFRE); 5986 wr32(E1000_VFRE, reg | (1 << vf)); 5987 5988 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 5989 5990 /* reply to reset with ack and vf mac address */ 5991 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 5992 memcpy(addr, vf_mac, ETH_ALEN); 5993 igb_write_mbx(hw, msgbuf, 3, vf); 5994} 5995 5996static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 5997{ 5998 /* The VF MAC Address is stored in a packed array of bytes 5999 * starting at the second 32 bit word of the msg array 6000 */ 6001 unsigned char *addr = (char *)&msg[1]; 6002 int err = -1; 6003 6004 if (is_valid_ether_addr(addr)) 6005 err = igb_set_vf_mac(adapter, vf, addr); 6006 6007 return err; 6008} 6009 6010static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 6011{ 6012 struct e1000_hw *hw = &adapter->hw; 6013 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6014 u32 msg = E1000_VT_MSGTYPE_NACK; 6015 6016 /* if device isn't clear to send it shouldn't be reading either */ 6017 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6018 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6019 igb_write_mbx(hw, &msg, 1, vf); 6020 vf_data->last_nack = jiffies; 6021 } 6022} 6023 6024static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6025{ 6026 struct pci_dev *pdev = adapter->pdev; 6027 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6028 struct e1000_hw *hw = &adapter->hw; 6029 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6030 s32 retval; 6031 6032 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6033 6034 if (retval) { 6035 /* if receive failed revoke VF CTS stats and restart init */ 6036 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6037 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6038 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6039 return; 6040 goto out; 6041 } 6042 6043 /* this is a message we already processed, do nothing */ 6044 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6045 return; 6046 6047 /* until the vf completes a reset it should not be 6048 * allowed to start any configuration. 6049 */ 6050 if (msgbuf[0] == E1000_VF_RESET) { 6051 igb_vf_reset_msg(adapter, vf); 6052 return; 6053 } 6054 6055 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6056 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6057 return; 6058 retval = -1; 6059 goto out; 6060 } 6061 6062 switch ((msgbuf[0] & 0xFFFF)) { 6063 case E1000_VF_SET_MAC_ADDR: 6064 retval = -EINVAL; 6065 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 6066 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6067 else 6068 dev_warn(&pdev->dev, 6069 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6070 vf); 6071 break; 6072 case E1000_VF_SET_PROMISC: 6073 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6074 break; 6075 case E1000_VF_SET_MULTICAST: 6076 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6077 break; 6078 case E1000_VF_SET_LPE: 6079 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6080 break; 6081 case E1000_VF_SET_VLAN: 6082 retval = -1; 6083 if (vf_data->pf_vlan) 6084 dev_warn(&pdev->dev, 6085 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6086 vf); 6087 else 6088 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 6089 break; 6090 default: 6091 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6092 retval = -1; 6093 break; 6094 } 6095 6096 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6097out: 6098 /* notify the VF of the results of what it sent us */ 6099 if (retval) 6100 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6101 else 6102 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6103 6104 igb_write_mbx(hw, msgbuf, 1, vf); 6105} 6106 6107static void igb_msg_task(struct igb_adapter *adapter) 6108{ 6109 struct e1000_hw *hw = &adapter->hw; 6110 u32 vf; 6111 6112 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6113 /* process any reset requests */ 6114 if (!igb_check_for_rst(hw, vf)) 6115 igb_vf_reset_event(adapter, vf); 6116 6117 /* process any messages pending */ 6118 if (!igb_check_for_msg(hw, vf)) 6119 igb_rcv_msg_from_vf(adapter, vf); 6120 6121 /* process any acks */ 6122 if (!igb_check_for_ack(hw, vf)) 6123 igb_rcv_ack_from_vf(adapter, vf); 6124 } 6125} 6126 6127/** 6128 * igb_set_uta - Set unicast filter table address 6129 * @adapter: board private structure 6130 * 6131 * The unicast table address is a register array of 32-bit registers. 6132 * The table is meant to be used in a way similar to how the MTA is used 6133 * however due to certain limitations in the hardware it is necessary to 6134 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6135 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6136 **/ 6137static void igb_set_uta(struct igb_adapter *adapter) 6138{ 6139 struct e1000_hw *hw = &adapter->hw; 6140 int i; 6141 6142 /* The UTA table only exists on 82576 hardware and newer */ 6143 if (hw->mac.type < e1000_82576) 6144 return; 6145 6146 /* we only need to do this if VMDq is enabled */ 6147 if (!adapter->vfs_allocated_count) 6148 return; 6149 6150 for (i = 0; i < hw->mac.uta_reg_count; i++) 6151 array_wr32(E1000_UTA, i, ~0); 6152} 6153 6154/** 6155 * igb_intr_msi - Interrupt Handler 6156 * @irq: interrupt number 6157 * @data: pointer to a network interface device structure 6158 **/ 6159static irqreturn_t igb_intr_msi(int irq, void *data) 6160{ 6161 struct igb_adapter *adapter = data; 6162 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6163 struct e1000_hw *hw = &adapter->hw; 6164 /* read ICR disables interrupts using IAM */ 6165 u32 icr = rd32(E1000_ICR); 6166 6167 igb_write_itr(q_vector); 6168 6169 if (icr & E1000_ICR_DRSTA) 6170 schedule_work(&adapter->reset_task); 6171 6172 if (icr & E1000_ICR_DOUTSYNC) { 6173 /* HW is reporting DMA is out of sync */ 6174 adapter->stats.doosync++; 6175 } 6176 6177 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6178 hw->mac.get_link_status = 1; 6179 if (!test_bit(__IGB_DOWN, &adapter->state)) 6180 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6181 } 6182 6183 if (icr & E1000_ICR_TS) { 6184 u32 tsicr = rd32(E1000_TSICR); 6185 6186 if (tsicr & E1000_TSICR_TXTS) { 6187 /* acknowledge the interrupt */ 6188 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6189 /* retrieve hardware timestamp */ 6190 schedule_work(&adapter->ptp_tx_work); 6191 } 6192 } 6193 6194 napi_schedule(&q_vector->napi); 6195 6196 return IRQ_HANDLED; 6197} 6198 6199/** 6200 * igb_intr - Legacy Interrupt Handler 6201 * @irq: interrupt number 6202 * @data: pointer to a network interface device structure 6203 **/ 6204static irqreturn_t igb_intr(int irq, void *data) 6205{ 6206 struct igb_adapter *adapter = data; 6207 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6208 struct e1000_hw *hw = &adapter->hw; 6209 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6210 * need for the IMC write 6211 */ 6212 u32 icr = rd32(E1000_ICR); 6213 6214 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6215 * not set, then the adapter didn't send an interrupt 6216 */ 6217 if (!(icr & E1000_ICR_INT_ASSERTED)) 6218 return IRQ_NONE; 6219 6220 igb_write_itr(q_vector); 6221 6222 if (icr & E1000_ICR_DRSTA) 6223 schedule_work(&adapter->reset_task); 6224 6225 if (icr & E1000_ICR_DOUTSYNC) { 6226 /* HW is reporting DMA is out of sync */ 6227 adapter->stats.doosync++; 6228 } 6229 6230 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6231 hw->mac.get_link_status = 1; 6232 /* guard against interrupt when we're going down */ 6233 if (!test_bit(__IGB_DOWN, &adapter->state)) 6234 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6235 } 6236 6237 if (icr & E1000_ICR_TS) { 6238 u32 tsicr = rd32(E1000_TSICR); 6239 6240 if (tsicr & E1000_TSICR_TXTS) { 6241 /* acknowledge the interrupt */ 6242 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6243 /* retrieve hardware timestamp */ 6244 schedule_work(&adapter->ptp_tx_work); 6245 } 6246 } 6247 6248 napi_schedule(&q_vector->napi); 6249 6250 return IRQ_HANDLED; 6251} 6252 6253static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6254{ 6255 struct igb_adapter *adapter = q_vector->adapter; 6256 struct e1000_hw *hw = &adapter->hw; 6257 6258 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6259 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6260 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6261 igb_set_itr(q_vector); 6262 else 6263 igb_update_ring_itr(q_vector); 6264 } 6265 6266 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6267 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6268 wr32(E1000_EIMS, q_vector->eims_value); 6269 else 6270 igb_irq_enable(adapter); 6271 } 6272} 6273 6274/** 6275 * igb_poll - NAPI Rx polling callback 6276 * @napi: napi polling structure 6277 * @budget: count of how many packets we should handle 6278 **/ 6279static int igb_poll(struct napi_struct *napi, int budget) 6280{ 6281 struct igb_q_vector *q_vector = container_of(napi, 6282 struct igb_q_vector, 6283 napi); 6284 bool clean_complete = true; 6285 6286#ifdef CONFIG_IGB_DCA 6287 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6288 igb_update_dca(q_vector); 6289#endif 6290 if (q_vector->tx.ring) 6291 clean_complete = igb_clean_tx_irq(q_vector); 6292 6293 if (q_vector->rx.ring) 6294 clean_complete &= igb_clean_rx_irq(q_vector, budget); 6295 6296 /* If all work not completed, return budget and keep polling */ 6297 if (!clean_complete) 6298 return budget; 6299 6300 /* If not enough Rx work done, exit the polling mode */ 6301 napi_complete(napi); 6302 igb_ring_irq_enable(q_vector); 6303 6304 return 0; 6305} 6306 6307/** 6308 * igb_clean_tx_irq - Reclaim resources after transmit completes 6309 * @q_vector: pointer to q_vector containing needed info 6310 * 6311 * returns true if ring is completely cleaned 6312 **/ 6313static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 6314{ 6315 struct igb_adapter *adapter = q_vector->adapter; 6316 struct igb_ring *tx_ring = q_vector->tx.ring; 6317 struct igb_tx_buffer *tx_buffer; 6318 union e1000_adv_tx_desc *tx_desc; 6319 unsigned int total_bytes = 0, total_packets = 0; 6320 unsigned int budget = q_vector->tx.work_limit; 6321 unsigned int i = tx_ring->next_to_clean; 6322 6323 if (test_bit(__IGB_DOWN, &adapter->state)) 6324 return true; 6325 6326 tx_buffer = &tx_ring->tx_buffer_info[i]; 6327 tx_desc = IGB_TX_DESC(tx_ring, i); 6328 i -= tx_ring->count; 6329 6330 do { 6331 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6332 6333 /* if next_to_watch is not set then there is no work pending */ 6334 if (!eop_desc) 6335 break; 6336 6337 /* prevent any other reads prior to eop_desc */ 6338 read_barrier_depends(); 6339 6340 /* if DD is not set pending work has not been completed */ 6341 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6342 break; 6343 6344 /* clear next_to_watch to prevent false hangs */ 6345 tx_buffer->next_to_watch = NULL; 6346 6347 /* update the statistics for this packet */ 6348 total_bytes += tx_buffer->bytecount; 6349 total_packets += tx_buffer->gso_segs; 6350 6351 /* free the skb */ 6352 dev_kfree_skb_any(tx_buffer->skb); 6353 6354 /* unmap skb header data */ 6355 dma_unmap_single(tx_ring->dev, 6356 dma_unmap_addr(tx_buffer, dma), 6357 dma_unmap_len(tx_buffer, len), 6358 DMA_TO_DEVICE); 6359 6360 /* clear tx_buffer data */ 6361 tx_buffer->skb = NULL; 6362 dma_unmap_len_set(tx_buffer, len, 0); 6363 6364 /* clear last DMA location and unmap remaining buffers */ 6365 while (tx_desc != eop_desc) { 6366 tx_buffer++; 6367 tx_desc++; 6368 i++; 6369 if (unlikely(!i)) { 6370 i -= tx_ring->count; 6371 tx_buffer = tx_ring->tx_buffer_info; 6372 tx_desc = IGB_TX_DESC(tx_ring, 0); 6373 } 6374 6375 /* unmap any remaining paged data */ 6376 if (dma_unmap_len(tx_buffer, len)) { 6377 dma_unmap_page(tx_ring->dev, 6378 dma_unmap_addr(tx_buffer, dma), 6379 dma_unmap_len(tx_buffer, len), 6380 DMA_TO_DEVICE); 6381 dma_unmap_len_set(tx_buffer, len, 0); 6382 } 6383 } 6384 6385 /* move us one more past the eop_desc for start of next pkt */ 6386 tx_buffer++; 6387 tx_desc++; 6388 i++; 6389 if (unlikely(!i)) { 6390 i -= tx_ring->count; 6391 tx_buffer = tx_ring->tx_buffer_info; 6392 tx_desc = IGB_TX_DESC(tx_ring, 0); 6393 } 6394 6395 /* issue prefetch for next Tx descriptor */ 6396 prefetch(tx_desc); 6397 6398 /* update budget accounting */ 6399 budget--; 6400 } while (likely(budget)); 6401 6402 netdev_tx_completed_queue(txring_txq(tx_ring), 6403 total_packets, total_bytes); 6404 i += tx_ring->count; 6405 tx_ring->next_to_clean = i; 6406 u64_stats_update_begin(&tx_ring->tx_syncp); 6407 tx_ring->tx_stats.bytes += total_bytes; 6408 tx_ring->tx_stats.packets += total_packets; 6409 u64_stats_update_end(&tx_ring->tx_syncp); 6410 q_vector->tx.total_bytes += total_bytes; 6411 q_vector->tx.total_packets += total_packets; 6412 6413 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6414 struct e1000_hw *hw = &adapter->hw; 6415 6416 /* Detect a transmit hang in hardware, this serializes the 6417 * check with the clearing of time_stamp and movement of i 6418 */ 6419 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6420 if (tx_buffer->next_to_watch && 6421 time_after(jiffies, tx_buffer->time_stamp + 6422 (adapter->tx_timeout_factor * HZ)) && 6423 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6424 6425 /* detected Tx unit hang */ 6426 dev_err(tx_ring->dev, 6427 "Detected Tx Unit Hang\n" 6428 " Tx Queue <%d>\n" 6429 " TDH <%x>\n" 6430 " TDT <%x>\n" 6431 " next_to_use <%x>\n" 6432 " next_to_clean <%x>\n" 6433 "buffer_info[next_to_clean]\n" 6434 " time_stamp <%lx>\n" 6435 " next_to_watch <%p>\n" 6436 " jiffies <%lx>\n" 6437 " desc.status <%x>\n", 6438 tx_ring->queue_index, 6439 rd32(E1000_TDH(tx_ring->reg_idx)), 6440 readl(tx_ring->tail), 6441 tx_ring->next_to_use, 6442 tx_ring->next_to_clean, 6443 tx_buffer->time_stamp, 6444 tx_buffer->next_to_watch, 6445 jiffies, 6446 tx_buffer->next_to_watch->wb.status); 6447 netif_stop_subqueue(tx_ring->netdev, 6448 tx_ring->queue_index); 6449 6450 /* we are about to reset, no point in enabling stuff */ 6451 return true; 6452 } 6453 } 6454 6455#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6456 if (unlikely(total_packets && 6457 netif_carrier_ok(tx_ring->netdev) && 6458 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6459 /* Make sure that anybody stopping the queue after this 6460 * sees the new next_to_clean. 6461 */ 6462 smp_mb(); 6463 if (__netif_subqueue_stopped(tx_ring->netdev, 6464 tx_ring->queue_index) && 6465 !(test_bit(__IGB_DOWN, &adapter->state))) { 6466 netif_wake_subqueue(tx_ring->netdev, 6467 tx_ring->queue_index); 6468 6469 u64_stats_update_begin(&tx_ring->tx_syncp); 6470 tx_ring->tx_stats.restart_queue++; 6471 u64_stats_update_end(&tx_ring->tx_syncp); 6472 } 6473 } 6474 6475 return !!budget; 6476} 6477 6478/** 6479 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6480 * @rx_ring: rx descriptor ring to store buffers on 6481 * @old_buff: donor buffer to have page reused 6482 * 6483 * Synchronizes page for reuse by the adapter 6484 **/ 6485static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6486 struct igb_rx_buffer *old_buff) 6487{ 6488 struct igb_rx_buffer *new_buff; 6489 u16 nta = rx_ring->next_to_alloc; 6490 6491 new_buff = &rx_ring->rx_buffer_info[nta]; 6492 6493 /* update, and store next to alloc */ 6494 nta++; 6495 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6496 6497 /* transfer page from old buffer to new buffer */ 6498 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); 6499 6500 /* sync the buffer for use by the device */ 6501 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 6502 old_buff->page_offset, 6503 IGB_RX_BUFSZ, 6504 DMA_FROM_DEVICE); 6505} 6506 6507static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 6508 struct page *page, 6509 unsigned int truesize) 6510{ 6511 /* avoid re-using remote pages */ 6512 if (unlikely(page_to_nid(page) != numa_node_id())) 6513 return false; 6514 6515#if (PAGE_SIZE < 8192) 6516 /* if we are only owner of page we can reuse it */ 6517 if (unlikely(page_count(page) != 1)) 6518 return false; 6519 6520 /* flip page offset to other buffer */ 6521 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 6522 6523 /* since we are the only owner of the page and we need to 6524 * increment it, just set the value to 2 in order to avoid 6525 * an unnecessary locked operation 6526 */ 6527 atomic_set(&page->_count, 2); 6528#else 6529 /* move offset up to the next cache line */ 6530 rx_buffer->page_offset += truesize; 6531 6532 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 6533 return false; 6534 6535 /* bump ref count on page before it is given to the stack */ 6536 get_page(page); 6537#endif 6538 6539 return true; 6540} 6541 6542/** 6543 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6544 * @rx_ring: rx descriptor ring to transact packets on 6545 * @rx_buffer: buffer containing page to add 6546 * @rx_desc: descriptor containing length of buffer written by hardware 6547 * @skb: sk_buff to place the data into 6548 * 6549 * This function will add the data contained in rx_buffer->page to the skb. 6550 * This is done either through a direct copy if the data in the buffer is 6551 * less than the skb header size, otherwise it will just attach the page as 6552 * a frag to the skb. 6553 * 6554 * The function will then update the page offset if necessary and return 6555 * true if the buffer can be reused by the adapter. 6556 **/ 6557static bool igb_add_rx_frag(struct igb_ring *rx_ring, 6558 struct igb_rx_buffer *rx_buffer, 6559 union e1000_adv_rx_desc *rx_desc, 6560 struct sk_buff *skb) 6561{ 6562 struct page *page = rx_buffer->page; 6563 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 6564#if (PAGE_SIZE < 8192) 6565 unsigned int truesize = IGB_RX_BUFSZ; 6566#else 6567 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 6568#endif 6569 6570 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { 6571 unsigned char *va = page_address(page) + rx_buffer->page_offset; 6572 6573 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6574 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6575 va += IGB_TS_HDR_LEN; 6576 size -= IGB_TS_HDR_LEN; 6577 } 6578 6579 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 6580 6581 /* we can reuse buffer as-is, just make sure it is local */ 6582 if (likely(page_to_nid(page) == numa_node_id())) 6583 return true; 6584 6585 /* this page cannot be reused so discard it */ 6586 put_page(page); 6587 return false; 6588 } 6589 6590 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 6591 rx_buffer->page_offset, size, truesize); 6592 6593 return igb_can_reuse_rx_page(rx_buffer, page, truesize); 6594} 6595 6596static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 6597 union e1000_adv_rx_desc *rx_desc, 6598 struct sk_buff *skb) 6599{ 6600 struct igb_rx_buffer *rx_buffer; 6601 struct page *page; 6602 6603 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 6604 6605 page = rx_buffer->page; 6606 prefetchw(page); 6607 6608 if (likely(!skb)) { 6609 void *page_addr = page_address(page) + 6610 rx_buffer->page_offset; 6611 6612 /* prefetch first cache line of first page */ 6613 prefetch(page_addr); 6614#if L1_CACHE_BYTES < 128 6615 prefetch(page_addr + L1_CACHE_BYTES); 6616#endif 6617 6618 /* allocate a skb to store the frags */ 6619 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 6620 IGB_RX_HDR_LEN); 6621 if (unlikely(!skb)) { 6622 rx_ring->rx_stats.alloc_failed++; 6623 return NULL; 6624 } 6625 6626 /* we will be copying header into skb->data in 6627 * pskb_may_pull so it is in our interest to prefetch 6628 * it now to avoid a possible cache miss 6629 */ 6630 prefetchw(skb->data); 6631 } 6632 6633 /* we are reusing so sync this buffer for CPU use */ 6634 dma_sync_single_range_for_cpu(rx_ring->dev, 6635 rx_buffer->dma, 6636 rx_buffer->page_offset, 6637 IGB_RX_BUFSZ, 6638 DMA_FROM_DEVICE); 6639 6640 /* pull page into skb */ 6641 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 6642 /* hand second half of page back to the ring */ 6643 igb_reuse_rx_page(rx_ring, rx_buffer); 6644 } else { 6645 /* we are not reusing the buffer so unmap it */ 6646 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6647 PAGE_SIZE, DMA_FROM_DEVICE); 6648 } 6649 6650 /* clear contents of rx_buffer */ 6651 rx_buffer->page = NULL; 6652 6653 return skb; 6654} 6655 6656static inline void igb_rx_checksum(struct igb_ring *ring, 6657 union e1000_adv_rx_desc *rx_desc, 6658 struct sk_buff *skb) 6659{ 6660 skb_checksum_none_assert(skb); 6661 6662 /* Ignore Checksum bit is set */ 6663 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6664 return; 6665 6666 /* Rx checksum disabled via ethtool */ 6667 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6668 return; 6669 6670 /* TCP/UDP checksum error bit is set */ 6671 if (igb_test_staterr(rx_desc, 6672 E1000_RXDEXT_STATERR_TCPE | 6673 E1000_RXDEXT_STATERR_IPE)) { 6674 /* work around errata with sctp packets where the TCPE aka 6675 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6676 * packets, (aka let the stack check the crc32c) 6677 */ 6678 if (!((skb->len == 60) && 6679 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6680 u64_stats_update_begin(&ring->rx_syncp); 6681 ring->rx_stats.csum_err++; 6682 u64_stats_update_end(&ring->rx_syncp); 6683 } 6684 /* let the stack verify checksum errors */ 6685 return; 6686 } 6687 /* It must be a TCP or UDP packet with a valid checksum */ 6688 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 6689 E1000_RXD_STAT_UDPCS)) 6690 skb->ip_summed = CHECKSUM_UNNECESSARY; 6691 6692 dev_dbg(ring->dev, "cksum success: bits %08X\n", 6693 le32_to_cpu(rx_desc->wb.upper.status_error)); 6694} 6695 6696static inline void igb_rx_hash(struct igb_ring *ring, 6697 union e1000_adv_rx_desc *rx_desc, 6698 struct sk_buff *skb) 6699{ 6700 if (ring->netdev->features & NETIF_F_RXHASH) 6701 skb_set_hash(skb, 6702 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 6703 PKT_HASH_TYPE_L3); 6704} 6705 6706/** 6707 * igb_is_non_eop - process handling of non-EOP buffers 6708 * @rx_ring: Rx ring being processed 6709 * @rx_desc: Rx descriptor for current buffer 6710 * @skb: current socket buffer containing buffer in progress 6711 * 6712 * This function updates next to clean. If the buffer is an EOP buffer 6713 * this function exits returning false, otherwise it will place the 6714 * sk_buff in the next buffer to be chained and return true indicating 6715 * that this is in fact a non-EOP buffer. 6716 **/ 6717static bool igb_is_non_eop(struct igb_ring *rx_ring, 6718 union e1000_adv_rx_desc *rx_desc) 6719{ 6720 u32 ntc = rx_ring->next_to_clean + 1; 6721 6722 /* fetch, update, and store next to clean */ 6723 ntc = (ntc < rx_ring->count) ? ntc : 0; 6724 rx_ring->next_to_clean = ntc; 6725 6726 prefetch(IGB_RX_DESC(rx_ring, ntc)); 6727 6728 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 6729 return false; 6730 6731 return true; 6732} 6733 6734/** 6735 * igb_get_headlen - determine size of header for LRO/GRO 6736 * @data: pointer to the start of the headers 6737 * @max_len: total length of section to find headers in 6738 * 6739 * This function is meant to determine the length of headers that will 6740 * be recognized by hardware for LRO, and GRO offloads. The main 6741 * motivation of doing this is to only perform one pull for IPv4 TCP 6742 * packets so that we can do basic things like calculating the gso_size 6743 * based on the average data per packet. 6744 **/ 6745static unsigned int igb_get_headlen(unsigned char *data, 6746 unsigned int max_len) 6747{ 6748 union { 6749 unsigned char *network; 6750 /* l2 headers */ 6751 struct ethhdr *eth; 6752 struct vlan_hdr *vlan; 6753 /* l3 headers */ 6754 struct iphdr *ipv4; 6755 struct ipv6hdr *ipv6; 6756 } hdr; 6757 __be16 protocol; 6758 u8 nexthdr = 0; /* default to not TCP */ 6759 u8 hlen; 6760 6761 /* this should never happen, but better safe than sorry */ 6762 if (max_len < ETH_HLEN) 6763 return max_len; 6764 6765 /* initialize network frame pointer */ 6766 hdr.network = data; 6767 6768 /* set first protocol and move network header forward */ 6769 protocol = hdr.eth->h_proto; 6770 hdr.network += ETH_HLEN; 6771 6772 /* handle any vlan tag if present */ 6773 if (protocol == htons(ETH_P_8021Q)) { 6774 if ((hdr.network - data) > (max_len - VLAN_HLEN)) 6775 return max_len; 6776 6777 protocol = hdr.vlan->h_vlan_encapsulated_proto; 6778 hdr.network += VLAN_HLEN; 6779 } 6780 6781 /* handle L3 protocols */ 6782 if (protocol == htons(ETH_P_IP)) { 6783 if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) 6784 return max_len; 6785 6786 /* access ihl as a u8 to avoid unaligned access on ia64 */ 6787 hlen = (hdr.network[0] & 0x0F) << 2; 6788 6789 /* verify hlen meets minimum size requirements */ 6790 if (hlen < sizeof(struct iphdr)) 6791 return hdr.network - data; 6792 6793 /* record next protocol if header is present */ 6794 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET))) 6795 nexthdr = hdr.ipv4->protocol; 6796 } else if (protocol == htons(ETH_P_IPV6)) { 6797 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) 6798 return max_len; 6799 6800 /* record next protocol */ 6801 nexthdr = hdr.ipv6->nexthdr; 6802 hlen = sizeof(struct ipv6hdr); 6803 } else { 6804 return hdr.network - data; 6805 } 6806 6807 /* relocate pointer to start of L4 header */ 6808 hdr.network += hlen; 6809 6810 /* finally sort out TCP */ 6811 if (nexthdr == IPPROTO_TCP) { 6812 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) 6813 return max_len; 6814 6815 /* access doff as a u8 to avoid unaligned access on ia64 */ 6816 hlen = (hdr.network[12] & 0xF0) >> 2; 6817 6818 /* verify hlen meets minimum size requirements */ 6819 if (hlen < sizeof(struct tcphdr)) 6820 return hdr.network - data; 6821 6822 hdr.network += hlen; 6823 } else if (nexthdr == IPPROTO_UDP) { 6824 if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) 6825 return max_len; 6826 6827 hdr.network += sizeof(struct udphdr); 6828 } 6829 6830 /* If everything has gone correctly hdr.network should be the 6831 * data section of the packet and will be the end of the header. 6832 * If not then it probably represents the end of the last recognized 6833 * header. 6834 */ 6835 if ((hdr.network - data) < max_len) 6836 return hdr.network - data; 6837 else 6838 return max_len; 6839} 6840 6841/** 6842 * igb_pull_tail - igb specific version of skb_pull_tail 6843 * @rx_ring: rx descriptor ring packet is being transacted on 6844 * @rx_desc: pointer to the EOP Rx descriptor 6845 * @skb: pointer to current skb being adjusted 6846 * 6847 * This function is an igb specific version of __pskb_pull_tail. The 6848 * main difference between this version and the original function is that 6849 * this function can make several assumptions about the state of things 6850 * that allow for significant optimizations versus the standard function. 6851 * As a result we can do things like drop a frag and maintain an accurate 6852 * truesize for the skb. 6853 */ 6854static void igb_pull_tail(struct igb_ring *rx_ring, 6855 union e1000_adv_rx_desc *rx_desc, 6856 struct sk_buff *skb) 6857{ 6858 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6859 unsigned char *va; 6860 unsigned int pull_len; 6861 6862 /* it is valid to use page_address instead of kmap since we are 6863 * working with pages allocated out of the lomem pool per 6864 * alloc_page(GFP_ATOMIC) 6865 */ 6866 va = skb_frag_address(frag); 6867 6868 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6869 /* retrieve timestamp from buffer */ 6870 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6871 6872 /* update pointers to remove timestamp header */ 6873 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); 6874 frag->page_offset += IGB_TS_HDR_LEN; 6875 skb->data_len -= IGB_TS_HDR_LEN; 6876 skb->len -= IGB_TS_HDR_LEN; 6877 6878 /* move va to start of packet data */ 6879 va += IGB_TS_HDR_LEN; 6880 } 6881 6882 /* we need the header to contain the greater of either ETH_HLEN or 6883 * 60 bytes if the skb->len is less than 60 for skb_pad. 6884 */ 6885 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); 6886 6887 /* align pull length to size of long to optimize memcpy performance */ 6888 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 6889 6890 /* update all of the pointers */ 6891 skb_frag_size_sub(frag, pull_len); 6892 frag->page_offset += pull_len; 6893 skb->data_len -= pull_len; 6894 skb->tail += pull_len; 6895} 6896 6897/** 6898 * igb_cleanup_headers - Correct corrupted or empty headers 6899 * @rx_ring: rx descriptor ring packet is being transacted on 6900 * @rx_desc: pointer to the EOP Rx descriptor 6901 * @skb: pointer to current skb being fixed 6902 * 6903 * Address the case where we are pulling data in on pages only 6904 * and as such no data is present in the skb header. 6905 * 6906 * In addition if skb is not at least 60 bytes we need to pad it so that 6907 * it is large enough to qualify as a valid Ethernet frame. 6908 * 6909 * Returns true if an error was encountered and skb was freed. 6910 **/ 6911static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6912 union e1000_adv_rx_desc *rx_desc, 6913 struct sk_buff *skb) 6914{ 6915 if (unlikely((igb_test_staterr(rx_desc, 6916 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6917 struct net_device *netdev = rx_ring->netdev; 6918 if (!(netdev->features & NETIF_F_RXALL)) { 6919 dev_kfree_skb_any(skb); 6920 return true; 6921 } 6922 } 6923 6924 /* place header in linear portion of buffer */ 6925 if (skb_is_nonlinear(skb)) 6926 igb_pull_tail(rx_ring, rx_desc, skb); 6927 6928 /* if skb_pad returns an error the skb was freed */ 6929 if (unlikely(skb->len < 60)) { 6930 int pad_len = 60 - skb->len; 6931 6932 if (skb_pad(skb, pad_len)) 6933 return true; 6934 __skb_put(skb, pad_len); 6935 } 6936 6937 return false; 6938} 6939 6940/** 6941 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6942 * @rx_ring: rx descriptor ring packet is being transacted on 6943 * @rx_desc: pointer to the EOP Rx descriptor 6944 * @skb: pointer to current skb being populated 6945 * 6946 * This function checks the ring, descriptor, and packet information in 6947 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6948 * other fields within the skb. 6949 **/ 6950static void igb_process_skb_fields(struct igb_ring *rx_ring, 6951 union e1000_adv_rx_desc *rx_desc, 6952 struct sk_buff *skb) 6953{ 6954 struct net_device *dev = rx_ring->netdev; 6955 6956 igb_rx_hash(rx_ring, rx_desc, skb); 6957 6958 igb_rx_checksum(rx_ring, rx_desc, skb); 6959 6960 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TS) && 6961 !igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) 6962 igb_ptp_rx_rgtstamp(rx_ring->q_vector, skb); 6963 6964 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 6965 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6966 u16 vid; 6967 6968 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6969 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6970 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6971 else 6972 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6973 6974 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 6975 } 6976 6977 skb_record_rx_queue(skb, rx_ring->queue_index); 6978 6979 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6980} 6981 6982static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 6983{ 6984 struct igb_ring *rx_ring = q_vector->rx.ring; 6985 struct sk_buff *skb = rx_ring->skb; 6986 unsigned int total_bytes = 0, total_packets = 0; 6987 u16 cleaned_count = igb_desc_unused(rx_ring); 6988 6989 while (likely(total_packets < budget)) { 6990 union e1000_adv_rx_desc *rx_desc; 6991 6992 /* return some buffers to hardware, one at a time is too slow */ 6993 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6994 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6995 cleaned_count = 0; 6996 } 6997 6998 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 6999 7000 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) 7001 break; 7002 7003 /* This memory barrier is needed to keep us from reading 7004 * any other fields out of the rx_desc until we know the 7005 * RXD_STAT_DD bit is set 7006 */ 7007 rmb(); 7008 7009 /* retrieve a buffer from the ring */ 7010 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 7011 7012 /* exit if we failed to retrieve a buffer */ 7013 if (!skb) 7014 break; 7015 7016 cleaned_count++; 7017 7018 /* fetch next buffer in frame if non-eop */ 7019 if (igb_is_non_eop(rx_ring, rx_desc)) 7020 continue; 7021 7022 /* verify the packet layout is correct */ 7023 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 7024 skb = NULL; 7025 continue; 7026 } 7027 7028 /* probably a little skewed due to removing CRC */ 7029 total_bytes += skb->len; 7030 7031 /* populate checksum, timestamp, VLAN, and protocol */ 7032 igb_process_skb_fields(rx_ring, rx_desc, skb); 7033 7034 napi_gro_receive(&q_vector->napi, skb); 7035 7036 /* reset skb pointer */ 7037 skb = NULL; 7038 7039 /* update budget accounting */ 7040 total_packets++; 7041 } 7042 7043 /* place incomplete frames back on ring for completion */ 7044 rx_ring->skb = skb; 7045 7046 u64_stats_update_begin(&rx_ring->rx_syncp); 7047 rx_ring->rx_stats.packets += total_packets; 7048 rx_ring->rx_stats.bytes += total_bytes; 7049 u64_stats_update_end(&rx_ring->rx_syncp); 7050 q_vector->rx.total_packets += total_packets; 7051 q_vector->rx.total_bytes += total_bytes; 7052 7053 if (cleaned_count) 7054 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7055 7056 return (total_packets < budget); 7057} 7058 7059static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7060 struct igb_rx_buffer *bi) 7061{ 7062 struct page *page = bi->page; 7063 dma_addr_t dma; 7064 7065 /* since we are recycling buffers we should seldom need to alloc */ 7066 if (likely(page)) 7067 return true; 7068 7069 /* alloc new page for storage */ 7070 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); 7071 if (unlikely(!page)) { 7072 rx_ring->rx_stats.alloc_failed++; 7073 return false; 7074 } 7075 7076 /* map page for use */ 7077 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 7078 7079 /* if mapping failed free memory back to system since 7080 * there isn't much point in holding memory we can't use 7081 */ 7082 if (dma_mapping_error(rx_ring->dev, dma)) { 7083 __free_page(page); 7084 7085 rx_ring->rx_stats.alloc_failed++; 7086 return false; 7087 } 7088 7089 bi->dma = dma; 7090 bi->page = page; 7091 bi->page_offset = 0; 7092 7093 return true; 7094} 7095 7096/** 7097 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7098 * @adapter: address of board private structure 7099 **/ 7100void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7101{ 7102 union e1000_adv_rx_desc *rx_desc; 7103 struct igb_rx_buffer *bi; 7104 u16 i = rx_ring->next_to_use; 7105 7106 /* nothing to do */ 7107 if (!cleaned_count) 7108 return; 7109 7110 rx_desc = IGB_RX_DESC(rx_ring, i); 7111 bi = &rx_ring->rx_buffer_info[i]; 7112 i -= rx_ring->count; 7113 7114 do { 7115 if (!igb_alloc_mapped_page(rx_ring, bi)) 7116 break; 7117 7118 /* Refresh the desc even if buffer_addrs didn't change 7119 * because each write-back erases this info. 7120 */ 7121 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7122 7123 rx_desc++; 7124 bi++; 7125 i++; 7126 if (unlikely(!i)) { 7127 rx_desc = IGB_RX_DESC(rx_ring, 0); 7128 bi = rx_ring->rx_buffer_info; 7129 i -= rx_ring->count; 7130 } 7131 7132 /* clear the hdr_addr for the next_to_use descriptor */ 7133 rx_desc->read.hdr_addr = 0; 7134 7135 cleaned_count--; 7136 } while (cleaned_count); 7137 7138 i += rx_ring->count; 7139 7140 if (rx_ring->next_to_use != i) { 7141 /* record the next descriptor to use */ 7142 rx_ring->next_to_use = i; 7143 7144 /* update next to alloc since we have filled the ring */ 7145 rx_ring->next_to_alloc = i; 7146 7147 /* Force memory writes to complete before letting h/w 7148 * know there are new descriptors to fetch. (Only 7149 * applicable for weak-ordered memory model archs, 7150 * such as IA-64). 7151 */ 7152 wmb(); 7153 writel(i, rx_ring->tail); 7154 } 7155} 7156 7157/** 7158 * igb_mii_ioctl - 7159 * @netdev: 7160 * @ifreq: 7161 * @cmd: 7162 **/ 7163static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7164{ 7165 struct igb_adapter *adapter = netdev_priv(netdev); 7166 struct mii_ioctl_data *data = if_mii(ifr); 7167 7168 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7169 return -EOPNOTSUPP; 7170 7171 switch (cmd) { 7172 case SIOCGMIIPHY: 7173 data->phy_id = adapter->hw.phy.addr; 7174 break; 7175 case SIOCGMIIREG: 7176 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7177 &data->val_out)) 7178 return -EIO; 7179 break; 7180 case SIOCSMIIREG: 7181 default: 7182 return -EOPNOTSUPP; 7183 } 7184 return 0; 7185} 7186 7187/** 7188 * igb_ioctl - 7189 * @netdev: 7190 * @ifreq: 7191 * @cmd: 7192 **/ 7193static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7194{ 7195 switch (cmd) { 7196 case SIOCGMIIPHY: 7197 case SIOCGMIIREG: 7198 case SIOCSMIIREG: 7199 return igb_mii_ioctl(netdev, ifr, cmd); 7200 case SIOCGHWTSTAMP: 7201 return igb_ptp_get_ts_config(netdev, ifr); 7202 case SIOCSHWTSTAMP: 7203 return igb_ptp_set_ts_config(netdev, ifr); 7204 default: 7205 return -EOPNOTSUPP; 7206 } 7207} 7208 7209s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7210{ 7211 struct igb_adapter *adapter = hw->back; 7212 7213 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7214 return -E1000_ERR_CONFIG; 7215 7216 return 0; 7217} 7218 7219s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7220{ 7221 struct igb_adapter *adapter = hw->back; 7222 7223 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7224 return -E1000_ERR_CONFIG; 7225 7226 return 0; 7227} 7228 7229static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7230{ 7231 struct igb_adapter *adapter = netdev_priv(netdev); 7232 struct e1000_hw *hw = &adapter->hw; 7233 u32 ctrl, rctl; 7234 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7235 7236 if (enable) { 7237 /* enable VLAN tag insert/strip */ 7238 ctrl = rd32(E1000_CTRL); 7239 ctrl |= E1000_CTRL_VME; 7240 wr32(E1000_CTRL, ctrl); 7241 7242 /* Disable CFI check */ 7243 rctl = rd32(E1000_RCTL); 7244 rctl &= ~E1000_RCTL_CFIEN; 7245 wr32(E1000_RCTL, rctl); 7246 } else { 7247 /* disable VLAN tag insert/strip */ 7248 ctrl = rd32(E1000_CTRL); 7249 ctrl &= ~E1000_CTRL_VME; 7250 wr32(E1000_CTRL, ctrl); 7251 } 7252 7253 igb_rlpml_set(adapter); 7254} 7255 7256static int igb_vlan_rx_add_vid(struct net_device *netdev, 7257 __be16 proto, u16 vid) 7258{ 7259 struct igb_adapter *adapter = netdev_priv(netdev); 7260 struct e1000_hw *hw = &adapter->hw; 7261 int pf_id = adapter->vfs_allocated_count; 7262 7263 /* attempt to add filter to vlvf array */ 7264 igb_vlvf_set(adapter, vid, true, pf_id); 7265 7266 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7267 igb_vfta_set(hw, vid, true); 7268 7269 set_bit(vid, adapter->active_vlans); 7270 7271 return 0; 7272} 7273 7274static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7275 __be16 proto, u16 vid) 7276{ 7277 struct igb_adapter *adapter = netdev_priv(netdev); 7278 struct e1000_hw *hw = &adapter->hw; 7279 int pf_id = adapter->vfs_allocated_count; 7280 s32 err; 7281 7282 /* remove vlan from VLVF table array */ 7283 err = igb_vlvf_set(adapter, vid, false, pf_id); 7284 7285 /* if vid was not present in VLVF just remove it from table */ 7286 if (err) 7287 igb_vfta_set(hw, vid, false); 7288 7289 clear_bit(vid, adapter->active_vlans); 7290 7291 return 0; 7292} 7293 7294static void igb_restore_vlan(struct igb_adapter *adapter) 7295{ 7296 u16 vid; 7297 7298 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7299 7300 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 7301 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7302} 7303 7304int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7305{ 7306 struct pci_dev *pdev = adapter->pdev; 7307 struct e1000_mac_info *mac = &adapter->hw.mac; 7308 7309 mac->autoneg = 0; 7310 7311 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7312 * for the switch() below to work 7313 */ 7314 if ((spd & 1) || (dplx & ~1)) 7315 goto err_inval; 7316 7317 /* Fiber NIC's only allow 1000 gbps Full duplex 7318 * and 100Mbps Full duplex for 100baseFx sfp 7319 */ 7320 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7321 switch (spd + dplx) { 7322 case SPEED_10 + DUPLEX_HALF: 7323 case SPEED_10 + DUPLEX_FULL: 7324 case SPEED_100 + DUPLEX_HALF: 7325 goto err_inval; 7326 default: 7327 break; 7328 } 7329 } 7330 7331 switch (spd + dplx) { 7332 case SPEED_10 + DUPLEX_HALF: 7333 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7334 break; 7335 case SPEED_10 + DUPLEX_FULL: 7336 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7337 break; 7338 case SPEED_100 + DUPLEX_HALF: 7339 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7340 break; 7341 case SPEED_100 + DUPLEX_FULL: 7342 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7343 break; 7344 case SPEED_1000 + DUPLEX_FULL: 7345 mac->autoneg = 1; 7346 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7347 break; 7348 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7349 default: 7350 goto err_inval; 7351 } 7352 7353 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7354 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7355 7356 return 0; 7357 7358err_inval: 7359 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7360 return -EINVAL; 7361} 7362 7363static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7364 bool runtime) 7365{ 7366 struct net_device *netdev = pci_get_drvdata(pdev); 7367 struct igb_adapter *adapter = netdev_priv(netdev); 7368 struct e1000_hw *hw = &adapter->hw; 7369 u32 ctrl, rctl, status; 7370 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7371#ifdef CONFIG_PM 7372 int retval = 0; 7373#endif 7374 7375 netif_device_detach(netdev); 7376 7377 if (netif_running(netdev)) 7378 __igb_close(netdev, true); 7379 7380 igb_clear_interrupt_scheme(adapter); 7381 7382#ifdef CONFIG_PM 7383 retval = pci_save_state(pdev); 7384 if (retval) 7385 return retval; 7386#endif 7387 7388 status = rd32(E1000_STATUS); 7389 if (status & E1000_STATUS_LU) 7390 wufc &= ~E1000_WUFC_LNKC; 7391 7392 if (wufc) { 7393 igb_setup_rctl(adapter); 7394 igb_set_rx_mode(netdev); 7395 7396 /* turn on all-multi mode if wake on multicast is enabled */ 7397 if (wufc & E1000_WUFC_MC) { 7398 rctl = rd32(E1000_RCTL); 7399 rctl |= E1000_RCTL_MPE; 7400 wr32(E1000_RCTL, rctl); 7401 } 7402 7403 ctrl = rd32(E1000_CTRL); 7404 /* advertise wake from D3Cold */ 7405 #define E1000_CTRL_ADVD3WUC 0x00100000 7406 /* phy power management enable */ 7407 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7408 ctrl |= E1000_CTRL_ADVD3WUC; 7409 wr32(E1000_CTRL, ctrl); 7410 7411 /* Allow time for pending master requests to run */ 7412 igb_disable_pcie_master(hw); 7413 7414 wr32(E1000_WUC, E1000_WUC_PME_EN); 7415 wr32(E1000_WUFC, wufc); 7416 } else { 7417 wr32(E1000_WUC, 0); 7418 wr32(E1000_WUFC, 0); 7419 } 7420 7421 *enable_wake = wufc || adapter->en_mng_pt; 7422 if (!*enable_wake) 7423 igb_power_down_link(adapter); 7424 else 7425 igb_power_up_link(adapter); 7426 7427 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7428 * would have already happened in close and is redundant. 7429 */ 7430 igb_release_hw_control(adapter); 7431 7432 pci_disable_device(pdev); 7433 7434 return 0; 7435} 7436 7437#ifdef CONFIG_PM 7438#ifdef CONFIG_PM_SLEEP 7439static int igb_suspend(struct device *dev) 7440{ 7441 int retval; 7442 bool wake; 7443 struct pci_dev *pdev = to_pci_dev(dev); 7444 7445 retval = __igb_shutdown(pdev, &wake, 0); 7446 if (retval) 7447 return retval; 7448 7449 if (wake) { 7450 pci_prepare_to_sleep(pdev); 7451 } else { 7452 pci_wake_from_d3(pdev, false); 7453 pci_set_power_state(pdev, PCI_D3hot); 7454 } 7455 7456 return 0; 7457} 7458#endif /* CONFIG_PM_SLEEP */ 7459 7460static int igb_resume(struct device *dev) 7461{ 7462 struct pci_dev *pdev = to_pci_dev(dev); 7463 struct net_device *netdev = pci_get_drvdata(pdev); 7464 struct igb_adapter *adapter = netdev_priv(netdev); 7465 struct e1000_hw *hw = &adapter->hw; 7466 u32 err; 7467 7468 pci_set_power_state(pdev, PCI_D0); 7469 pci_restore_state(pdev); 7470 pci_save_state(pdev); 7471 7472 err = pci_enable_device_mem(pdev); 7473 if (err) { 7474 dev_err(&pdev->dev, 7475 "igb: Cannot enable PCI device from suspend\n"); 7476 return err; 7477 } 7478 pci_set_master(pdev); 7479 7480 pci_enable_wake(pdev, PCI_D3hot, 0); 7481 pci_enable_wake(pdev, PCI_D3cold, 0); 7482 7483 if (igb_init_interrupt_scheme(adapter, true)) { 7484 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7485 return -ENOMEM; 7486 } 7487 7488 igb_reset(adapter); 7489 7490 /* let the f/w know that the h/w is now under the control of the 7491 * driver. 7492 */ 7493 igb_get_hw_control(adapter); 7494 7495 wr32(E1000_WUS, ~0); 7496 7497 if (netdev->flags & IFF_UP) { 7498 rtnl_lock(); 7499 err = __igb_open(netdev, true); 7500 rtnl_unlock(); 7501 if (err) 7502 return err; 7503 } 7504 7505 netif_device_attach(netdev); 7506 return 0; 7507} 7508 7509#ifdef CONFIG_PM_RUNTIME 7510static int igb_runtime_idle(struct device *dev) 7511{ 7512 struct pci_dev *pdev = to_pci_dev(dev); 7513 struct net_device *netdev = pci_get_drvdata(pdev); 7514 struct igb_adapter *adapter = netdev_priv(netdev); 7515 7516 if (!igb_has_link(adapter)) 7517 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7518 7519 return -EBUSY; 7520} 7521 7522static int igb_runtime_suspend(struct device *dev) 7523{ 7524 struct pci_dev *pdev = to_pci_dev(dev); 7525 int retval; 7526 bool wake; 7527 7528 retval = __igb_shutdown(pdev, &wake, 1); 7529 if (retval) 7530 return retval; 7531 7532 if (wake) { 7533 pci_prepare_to_sleep(pdev); 7534 } else { 7535 pci_wake_from_d3(pdev, false); 7536 pci_set_power_state(pdev, PCI_D3hot); 7537 } 7538 7539 return 0; 7540} 7541 7542static int igb_runtime_resume(struct device *dev) 7543{ 7544 return igb_resume(dev); 7545} 7546#endif /* CONFIG_PM_RUNTIME */ 7547#endif 7548 7549static void igb_shutdown(struct pci_dev *pdev) 7550{ 7551 bool wake; 7552 7553 __igb_shutdown(pdev, &wake, 0); 7554 7555 if (system_state == SYSTEM_POWER_OFF) { 7556 pci_wake_from_d3(pdev, wake); 7557 pci_set_power_state(pdev, PCI_D3hot); 7558 } 7559} 7560 7561#ifdef CONFIG_PCI_IOV 7562static int igb_sriov_reinit(struct pci_dev *dev) 7563{ 7564 struct net_device *netdev = pci_get_drvdata(dev); 7565 struct igb_adapter *adapter = netdev_priv(netdev); 7566 struct pci_dev *pdev = adapter->pdev; 7567 7568 rtnl_lock(); 7569 7570 if (netif_running(netdev)) 7571 igb_close(netdev); 7572 7573 igb_clear_interrupt_scheme(adapter); 7574 7575 igb_init_queue_configuration(adapter); 7576 7577 if (igb_init_interrupt_scheme(adapter, true)) { 7578 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7579 return -ENOMEM; 7580 } 7581 7582 if (netif_running(netdev)) 7583 igb_open(netdev); 7584 7585 rtnl_unlock(); 7586 7587 return 0; 7588} 7589 7590static int igb_pci_disable_sriov(struct pci_dev *dev) 7591{ 7592 int err = igb_disable_sriov(dev); 7593 7594 if (!err) 7595 err = igb_sriov_reinit(dev); 7596 7597 return err; 7598} 7599 7600static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7601{ 7602 int err = igb_enable_sriov(dev, num_vfs); 7603 7604 if (err) 7605 goto out; 7606 7607 err = igb_sriov_reinit(dev); 7608 if (!err) 7609 return num_vfs; 7610 7611out: 7612 return err; 7613} 7614 7615#endif 7616static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7617{ 7618#ifdef CONFIG_PCI_IOV 7619 if (num_vfs == 0) 7620 return igb_pci_disable_sriov(dev); 7621 else 7622 return igb_pci_enable_sriov(dev, num_vfs); 7623#endif 7624 return 0; 7625} 7626 7627#ifdef CONFIG_NET_POLL_CONTROLLER 7628/* Polling 'interrupt' - used by things like netconsole to send skbs 7629 * without having to re-enable interrupts. It's not called while 7630 * the interrupt routine is executing. 7631 */ 7632static void igb_netpoll(struct net_device *netdev) 7633{ 7634 struct igb_adapter *adapter = netdev_priv(netdev); 7635 struct e1000_hw *hw = &adapter->hw; 7636 struct igb_q_vector *q_vector; 7637 int i; 7638 7639 for (i = 0; i < adapter->num_q_vectors; i++) { 7640 q_vector = adapter->q_vector[i]; 7641 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7642 wr32(E1000_EIMC, q_vector->eims_value); 7643 else 7644 igb_irq_disable(adapter); 7645 napi_schedule(&q_vector->napi); 7646 } 7647} 7648#endif /* CONFIG_NET_POLL_CONTROLLER */ 7649 7650/** 7651 * igb_io_error_detected - called when PCI error is detected 7652 * @pdev: Pointer to PCI device 7653 * @state: The current pci connection state 7654 * 7655 * This function is called after a PCI bus error affecting 7656 * this device has been detected. 7657 **/ 7658static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7659 pci_channel_state_t state) 7660{ 7661 struct net_device *netdev = pci_get_drvdata(pdev); 7662 struct igb_adapter *adapter = netdev_priv(netdev); 7663 7664 netif_device_detach(netdev); 7665 7666 if (state == pci_channel_io_perm_failure) 7667 return PCI_ERS_RESULT_DISCONNECT; 7668 7669 if (netif_running(netdev)) 7670 igb_down(adapter); 7671 pci_disable_device(pdev); 7672 7673 /* Request a slot slot reset. */ 7674 return PCI_ERS_RESULT_NEED_RESET; 7675} 7676 7677/** 7678 * igb_io_slot_reset - called after the pci bus has been reset. 7679 * @pdev: Pointer to PCI device 7680 * 7681 * Restart the card from scratch, as if from a cold-boot. Implementation 7682 * resembles the first-half of the igb_resume routine. 7683 **/ 7684static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 7685{ 7686 struct net_device *netdev = pci_get_drvdata(pdev); 7687 struct igb_adapter *adapter = netdev_priv(netdev); 7688 struct e1000_hw *hw = &adapter->hw; 7689 pci_ers_result_t result; 7690 int err; 7691 7692 if (pci_enable_device_mem(pdev)) { 7693 dev_err(&pdev->dev, 7694 "Cannot re-enable PCI device after reset.\n"); 7695 result = PCI_ERS_RESULT_DISCONNECT; 7696 } else { 7697 pci_set_master(pdev); 7698 pci_restore_state(pdev); 7699 pci_save_state(pdev); 7700 7701 pci_enable_wake(pdev, PCI_D3hot, 0); 7702 pci_enable_wake(pdev, PCI_D3cold, 0); 7703 7704 igb_reset(adapter); 7705 wr32(E1000_WUS, ~0); 7706 result = PCI_ERS_RESULT_RECOVERED; 7707 } 7708 7709 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7710 if (err) { 7711 dev_err(&pdev->dev, 7712 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7713 err); 7714 /* non-fatal, continue */ 7715 } 7716 7717 return result; 7718} 7719 7720/** 7721 * igb_io_resume - called when traffic can start flowing again. 7722 * @pdev: Pointer to PCI device 7723 * 7724 * This callback is called when the error recovery driver tells us that 7725 * its OK to resume normal operation. Implementation resembles the 7726 * second-half of the igb_resume routine. 7727 */ 7728static void igb_io_resume(struct pci_dev *pdev) 7729{ 7730 struct net_device *netdev = pci_get_drvdata(pdev); 7731 struct igb_adapter *adapter = netdev_priv(netdev); 7732 7733 if (netif_running(netdev)) { 7734 if (igb_up(adapter)) { 7735 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7736 return; 7737 } 7738 } 7739 7740 netif_device_attach(netdev); 7741 7742 /* let the f/w know that the h/w is now under the control of the 7743 * driver. 7744 */ 7745 igb_get_hw_control(adapter); 7746} 7747 7748static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7749 u8 qsel) 7750{ 7751 u32 rar_low, rar_high; 7752 struct e1000_hw *hw = &adapter->hw; 7753 7754 /* HW expects these in little endian so we reverse the byte order 7755 * from network order (big endian) to little endian 7756 */ 7757 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 7758 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 7759 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 7760 7761 /* Indicate to hardware the Address is Valid. */ 7762 rar_high |= E1000_RAH_AV; 7763 7764 if (hw->mac.type == e1000_82575) 7765 rar_high |= E1000_RAH_POOL_1 * qsel; 7766 else 7767 rar_high |= E1000_RAH_POOL_1 << qsel; 7768 7769 wr32(E1000_RAL(index), rar_low); 7770 wrfl(); 7771 wr32(E1000_RAH(index), rar_high); 7772 wrfl(); 7773} 7774 7775static int igb_set_vf_mac(struct igb_adapter *adapter, 7776 int vf, unsigned char *mac_addr) 7777{ 7778 struct e1000_hw *hw = &adapter->hw; 7779 /* VF MAC addresses start at end of receive addresses and moves 7780 * towards the first, as a result a collision should not be possible 7781 */ 7782 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7783 7784 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7785 7786 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7787 7788 return 0; 7789} 7790 7791static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7792{ 7793 struct igb_adapter *adapter = netdev_priv(netdev); 7794 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7795 return -EINVAL; 7796 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7797 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7798 dev_info(&adapter->pdev->dev, 7799 "Reload the VF driver to make this change effective."); 7800 if (test_bit(__IGB_DOWN, &adapter->state)) { 7801 dev_warn(&adapter->pdev->dev, 7802 "The VF MAC address has been set, but the PF device is not up.\n"); 7803 dev_warn(&adapter->pdev->dev, 7804 "Bring the PF device up before attempting to use the VF device.\n"); 7805 } 7806 return igb_set_vf_mac(adapter, vf, mac); 7807} 7808 7809static int igb_link_mbps(int internal_link_speed) 7810{ 7811 switch (internal_link_speed) { 7812 case SPEED_100: 7813 return 100; 7814 case SPEED_1000: 7815 return 1000; 7816 default: 7817 return 0; 7818 } 7819} 7820 7821static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7822 int link_speed) 7823{ 7824 int rf_dec, rf_int; 7825 u32 bcnrc_val; 7826 7827 if (tx_rate != 0) { 7828 /* Calculate the rate factor values to set */ 7829 rf_int = link_speed / tx_rate; 7830 rf_dec = (link_speed - (rf_int * tx_rate)); 7831 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / 7832 tx_rate; 7833 7834 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7835 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 7836 E1000_RTTBCNRC_RF_INT_MASK); 7837 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7838 } else { 7839 bcnrc_val = 0; 7840 } 7841 7842 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7843 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7844 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7845 */ 7846 wr32(E1000_RTTBCNRM, 0x14); 7847 wr32(E1000_RTTBCNRC, bcnrc_val); 7848} 7849 7850static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7851{ 7852 int actual_link_speed, i; 7853 bool reset_rate = false; 7854 7855 /* VF TX rate limit was not set or not supported */ 7856 if ((adapter->vf_rate_link_speed == 0) || 7857 (adapter->hw.mac.type != e1000_82576)) 7858 return; 7859 7860 actual_link_speed = igb_link_mbps(adapter->link_speed); 7861 if (actual_link_speed != adapter->vf_rate_link_speed) { 7862 reset_rate = true; 7863 adapter->vf_rate_link_speed = 0; 7864 dev_info(&adapter->pdev->dev, 7865 "Link speed has been changed. VF Transmit rate is disabled\n"); 7866 } 7867 7868 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7869 if (reset_rate) 7870 adapter->vf_data[i].tx_rate = 0; 7871 7872 igb_set_vf_rate_limit(&adapter->hw, i, 7873 adapter->vf_data[i].tx_rate, 7874 actual_link_speed); 7875 } 7876} 7877 7878static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) 7879{ 7880 struct igb_adapter *adapter = netdev_priv(netdev); 7881 struct e1000_hw *hw = &adapter->hw; 7882 int actual_link_speed; 7883 7884 if (hw->mac.type != e1000_82576) 7885 return -EOPNOTSUPP; 7886 7887 actual_link_speed = igb_link_mbps(adapter->link_speed); 7888 if ((vf >= adapter->vfs_allocated_count) || 7889 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7890 (tx_rate < 0) || (tx_rate > actual_link_speed)) 7891 return -EINVAL; 7892 7893 adapter->vf_rate_link_speed = actual_link_speed; 7894 adapter->vf_data[vf].tx_rate = (u16)tx_rate; 7895 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); 7896 7897 return 0; 7898} 7899 7900static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 7901 bool setting) 7902{ 7903 struct igb_adapter *adapter = netdev_priv(netdev); 7904 struct e1000_hw *hw = &adapter->hw; 7905 u32 reg_val, reg_offset; 7906 7907 if (!adapter->vfs_allocated_count) 7908 return -EOPNOTSUPP; 7909 7910 if (vf >= adapter->vfs_allocated_count) 7911 return -EINVAL; 7912 7913 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 7914 reg_val = rd32(reg_offset); 7915 if (setting) 7916 reg_val |= ((1 << vf) | 7917 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7918 else 7919 reg_val &= ~((1 << vf) | 7920 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7921 wr32(reg_offset, reg_val); 7922 7923 adapter->vf_data[vf].spoofchk_enabled = setting; 7924 return E1000_SUCCESS; 7925} 7926 7927static int igb_ndo_get_vf_config(struct net_device *netdev, 7928 int vf, struct ifla_vf_info *ivi) 7929{ 7930 struct igb_adapter *adapter = netdev_priv(netdev); 7931 if (vf >= adapter->vfs_allocated_count) 7932 return -EINVAL; 7933 ivi->vf = vf; 7934 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7935 ivi->tx_rate = adapter->vf_data[vf].tx_rate; 7936 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7937 ivi->qos = adapter->vf_data[vf].pf_qos; 7938 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 7939 return 0; 7940} 7941 7942static void igb_vmm_control(struct igb_adapter *adapter) 7943{ 7944 struct e1000_hw *hw = &adapter->hw; 7945 u32 reg; 7946 7947 switch (hw->mac.type) { 7948 case e1000_82575: 7949 case e1000_i210: 7950 case e1000_i211: 7951 case e1000_i354: 7952 default: 7953 /* replication is not supported for 82575 */ 7954 return; 7955 case e1000_82576: 7956 /* notify HW that the MAC is adding vlan tags */ 7957 reg = rd32(E1000_DTXCTL); 7958 reg |= E1000_DTXCTL_VLAN_ADDED; 7959 wr32(E1000_DTXCTL, reg); 7960 case e1000_82580: 7961 /* enable replication vlan tag stripping */ 7962 reg = rd32(E1000_RPLOLR); 7963 reg |= E1000_RPLOLR_STRVLAN; 7964 wr32(E1000_RPLOLR, reg); 7965 case e1000_i350: 7966 /* none of the above registers are supported by i350 */ 7967 break; 7968 } 7969 7970 if (adapter->vfs_allocated_count) { 7971 igb_vmdq_set_loopback_pf(hw, true); 7972 igb_vmdq_set_replication_pf(hw, true); 7973 igb_vmdq_set_anti_spoofing_pf(hw, true, 7974 adapter->vfs_allocated_count); 7975 } else { 7976 igb_vmdq_set_loopback_pf(hw, false); 7977 igb_vmdq_set_replication_pf(hw, false); 7978 } 7979} 7980 7981static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7982{ 7983 struct e1000_hw *hw = &adapter->hw; 7984 u32 dmac_thr; 7985 u16 hwm; 7986 7987 if (hw->mac.type > e1000_82580) { 7988 if (adapter->flags & IGB_FLAG_DMAC) { 7989 u32 reg; 7990 7991 /* force threshold to 0. */ 7992 wr32(E1000_DMCTXTH, 0); 7993 7994 /* DMA Coalescing high water mark needs to be greater 7995 * than the Rx threshold. Set hwm to PBA - max frame 7996 * size in 16B units, capping it at PBA - 6KB. 7997 */ 7998 hwm = 64 * pba - adapter->max_frame_size / 16; 7999 if (hwm < 64 * (pba - 6)) 8000 hwm = 64 * (pba - 6); 8001 reg = rd32(E1000_FCRTC); 8002 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 8003 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 8004 & E1000_FCRTC_RTH_COAL_MASK); 8005 wr32(E1000_FCRTC, reg); 8006 8007 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 8008 * frame size, capping it at PBA - 10KB. 8009 */ 8010 dmac_thr = pba - adapter->max_frame_size / 512; 8011 if (dmac_thr < pba - 10) 8012 dmac_thr = pba - 10; 8013 reg = rd32(E1000_DMACR); 8014 reg &= ~E1000_DMACR_DMACTHR_MASK; 8015 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 8016 & E1000_DMACR_DMACTHR_MASK); 8017 8018 /* transition to L0x or L1 if available..*/ 8019 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 8020 8021 /* watchdog timer= +-1000 usec in 32usec intervals */ 8022 reg |= (1000 >> 5); 8023 8024 /* Disable BMC-to-OS Watchdog Enable */ 8025 if (hw->mac.type != e1000_i354) 8026 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 8027 8028 wr32(E1000_DMACR, reg); 8029 8030 /* no lower threshold to disable 8031 * coalescing(smart fifb)-UTRESH=0 8032 */ 8033 wr32(E1000_DMCRTRH, 0); 8034 8035 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8036 8037 wr32(E1000_DMCTLX, reg); 8038 8039 /* free space in tx packet buffer to wake from 8040 * DMA coal 8041 */ 8042 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8043 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8044 8045 /* make low power state decision controlled 8046 * by DMA coal 8047 */ 8048 reg = rd32(E1000_PCIEMISC); 8049 reg &= ~E1000_PCIEMISC_LX_DECISION; 8050 wr32(E1000_PCIEMISC, reg); 8051 } /* endif adapter->dmac is not disabled */ 8052 } else if (hw->mac.type == e1000_82580) { 8053 u32 reg = rd32(E1000_PCIEMISC); 8054 8055 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8056 wr32(E1000_DMACR, 0); 8057 } 8058} 8059 8060/** 8061 * igb_read_i2c_byte - Reads 8 bit word over I2C 8062 * @hw: pointer to hardware structure 8063 * @byte_offset: byte offset to read 8064 * @dev_addr: device address 8065 * @data: value read 8066 * 8067 * Performs byte read operation over I2C interface at 8068 * a specified device address. 8069 **/ 8070s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8071 u8 dev_addr, u8 *data) 8072{ 8073 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8074 struct i2c_client *this_client = adapter->i2c_client; 8075 s32 status; 8076 u16 swfw_mask = 0; 8077 8078 if (!this_client) 8079 return E1000_ERR_I2C; 8080 8081 swfw_mask = E1000_SWFW_PHY0_SM; 8082 8083 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 8084 != E1000_SUCCESS) 8085 return E1000_ERR_SWFW_SYNC; 8086 8087 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8088 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8089 8090 if (status < 0) 8091 return E1000_ERR_I2C; 8092 else { 8093 *data = status; 8094 return E1000_SUCCESS; 8095 } 8096} 8097 8098/** 8099 * igb_write_i2c_byte - Writes 8 bit word over I2C 8100 * @hw: pointer to hardware structure 8101 * @byte_offset: byte offset to write 8102 * @dev_addr: device address 8103 * @data: value to write 8104 * 8105 * Performs byte write operation over I2C interface at 8106 * a specified device address. 8107 **/ 8108s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8109 u8 dev_addr, u8 data) 8110{ 8111 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8112 struct i2c_client *this_client = adapter->i2c_client; 8113 s32 status; 8114 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8115 8116 if (!this_client) 8117 return E1000_ERR_I2C; 8118 8119 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) 8120 return E1000_ERR_SWFW_SYNC; 8121 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8122 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8123 8124 if (status) 8125 return E1000_ERR_I2C; 8126 else 8127 return E1000_SUCCESS; 8128 8129} 8130 8131int igb_reinit_queues(struct igb_adapter *adapter) 8132{ 8133 struct net_device *netdev = adapter->netdev; 8134 struct pci_dev *pdev = adapter->pdev; 8135 int err = 0; 8136 8137 if (netif_running(netdev)) 8138 igb_close(netdev); 8139 8140 igb_reset_interrupt_capability(adapter); 8141 8142 if (igb_init_interrupt_scheme(adapter, true)) { 8143 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8144 return -ENOMEM; 8145 } 8146 8147 if (netif_running(netdev)) 8148 err = igb_open(netdev); 8149 8150 return err; 8151} 8152/* igb_main.c */ 8153