igb_main.c revision ed4420a3b412b09cc60d6e3d662428b7e6c36e90
1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2014 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, see <http://www.gnu.org/licenses/>. 17 18 The full GNU General Public License is included in this distribution in 19 the file called "COPYING". 20 21 Contact Information: 22 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 23 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 25*******************************************************************************/ 26 27#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 28 29#include <linux/module.h> 30#include <linux/types.h> 31#include <linux/init.h> 32#include <linux/bitops.h> 33#include <linux/vmalloc.h> 34#include <linux/pagemap.h> 35#include <linux/netdevice.h> 36#include <linux/ipv6.h> 37#include <linux/slab.h> 38#include <net/checksum.h> 39#include <net/ip6_checksum.h> 40#include <linux/net_tstamp.h> 41#include <linux/mii.h> 42#include <linux/ethtool.h> 43#include <linux/if.h> 44#include <linux/if_vlan.h> 45#include <linux/pci.h> 46#include <linux/pci-aspm.h> 47#include <linux/delay.h> 48#include <linux/interrupt.h> 49#include <linux/ip.h> 50#include <linux/tcp.h> 51#include <linux/sctp.h> 52#include <linux/if_ether.h> 53#include <linux/aer.h> 54#include <linux/prefetch.h> 55#include <linux/pm_runtime.h> 56#ifdef CONFIG_IGB_DCA 57#include <linux/dca.h> 58#endif 59#include <linux/i2c.h> 60#include "igb.h" 61 62#define MAJ 5 63#define MIN 0 64#define BUILD 5 65#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \ 66__stringify(BUILD) "-k" 67char igb_driver_name[] = "igb"; 68char igb_driver_version[] = DRV_VERSION; 69static const char igb_driver_string[] = 70 "Intel(R) Gigabit Ethernet Network Driver"; 71static const char igb_copyright[] = 72 "Copyright (c) 2007-2014 Intel Corporation."; 73 74static const struct e1000_info *igb_info_tbl[] = { 75 [board_82575] = &e1000_82575_info, 76}; 77 78static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = { 79 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_1GBPS) }, 80 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_SGMII) }, 81 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I354_BACKPLANE_2_5GBPS) }, 82 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I211_COPPER), board_82575 }, 83 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER), board_82575 }, 84 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_FIBER), board_82575 }, 85 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES), board_82575 }, 86 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SGMII), board_82575 }, 87 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_COPPER_FLASHLESS), board_82575 }, 88 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I210_SERDES_FLASHLESS), board_82575 }, 89 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 }, 90 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 }, 91 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 }, 92 { PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 }, 93 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 }, 94 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 }, 95 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 }, 96 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 }, 97 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 }, 98 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 }, 99 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 }, 100 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 }, 101 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 }, 102 { PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 }, 103 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 }, 104 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 }, 105 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 }, 106 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 }, 107 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 }, 108 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 }, 109 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 }, 110 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 }, 111 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 }, 112 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 }, 113 { PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 }, 114 /* required last entry */ 115 {0, } 116}; 117 118MODULE_DEVICE_TABLE(pci, igb_pci_tbl); 119 120void igb_reset(struct igb_adapter *); 121static int igb_setup_all_tx_resources(struct igb_adapter *); 122static int igb_setup_all_rx_resources(struct igb_adapter *); 123static void igb_free_all_tx_resources(struct igb_adapter *); 124static void igb_free_all_rx_resources(struct igb_adapter *); 125static void igb_setup_mrqc(struct igb_adapter *); 126static int igb_probe(struct pci_dev *, const struct pci_device_id *); 127static void igb_remove(struct pci_dev *pdev); 128static int igb_sw_init(struct igb_adapter *); 129static int igb_open(struct net_device *); 130static int igb_close(struct net_device *); 131static void igb_configure(struct igb_adapter *); 132static void igb_configure_tx(struct igb_adapter *); 133static void igb_configure_rx(struct igb_adapter *); 134static void igb_clean_all_tx_rings(struct igb_adapter *); 135static void igb_clean_all_rx_rings(struct igb_adapter *); 136static void igb_clean_tx_ring(struct igb_ring *); 137static void igb_clean_rx_ring(struct igb_ring *); 138static void igb_set_rx_mode(struct net_device *); 139static void igb_update_phy_info(unsigned long); 140static void igb_watchdog(unsigned long); 141static void igb_watchdog_task(struct work_struct *); 142static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *); 143static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev, 144 struct rtnl_link_stats64 *stats); 145static int igb_change_mtu(struct net_device *, int); 146static int igb_set_mac(struct net_device *, void *); 147static void igb_set_uta(struct igb_adapter *adapter); 148static irqreturn_t igb_intr(int irq, void *); 149static irqreturn_t igb_intr_msi(int irq, void *); 150static irqreturn_t igb_msix_other(int irq, void *); 151static irqreturn_t igb_msix_ring(int irq, void *); 152#ifdef CONFIG_IGB_DCA 153static void igb_update_dca(struct igb_q_vector *); 154static void igb_setup_dca(struct igb_adapter *); 155#endif /* CONFIG_IGB_DCA */ 156static int igb_poll(struct napi_struct *, int); 157static bool igb_clean_tx_irq(struct igb_q_vector *); 158static bool igb_clean_rx_irq(struct igb_q_vector *, int); 159static int igb_ioctl(struct net_device *, struct ifreq *, int cmd); 160static void igb_tx_timeout(struct net_device *); 161static void igb_reset_task(struct work_struct *); 162static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features); 163static int igb_vlan_rx_add_vid(struct net_device *, __be16, u16); 164static int igb_vlan_rx_kill_vid(struct net_device *, __be16, u16); 165static void igb_restore_vlan(struct igb_adapter *); 166static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8); 167static void igb_ping_all_vfs(struct igb_adapter *); 168static void igb_msg_task(struct igb_adapter *); 169static void igb_vmm_control(struct igb_adapter *); 170static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *); 171static void igb_restore_vf_multicasts(struct igb_adapter *adapter); 172static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac); 173static int igb_ndo_set_vf_vlan(struct net_device *netdev, 174 int vf, u16 vlan, u8 qos); 175static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate); 176static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 177 bool setting); 178static int igb_ndo_get_vf_config(struct net_device *netdev, int vf, 179 struct ifla_vf_info *ivi); 180static void igb_check_vf_rate_limit(struct igb_adapter *); 181 182#ifdef CONFIG_PCI_IOV 183static int igb_vf_configure(struct igb_adapter *adapter, int vf); 184static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs); 185#endif 186 187#ifdef CONFIG_PM 188#ifdef CONFIG_PM_SLEEP 189static int igb_suspend(struct device *); 190#endif 191static int igb_resume(struct device *); 192#ifdef CONFIG_PM_RUNTIME 193static int igb_runtime_suspend(struct device *dev); 194static int igb_runtime_resume(struct device *dev); 195static int igb_runtime_idle(struct device *dev); 196#endif 197static const struct dev_pm_ops igb_pm_ops = { 198 SET_SYSTEM_SLEEP_PM_OPS(igb_suspend, igb_resume) 199 SET_RUNTIME_PM_OPS(igb_runtime_suspend, igb_runtime_resume, 200 igb_runtime_idle) 201}; 202#endif 203static void igb_shutdown(struct pci_dev *); 204static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs); 205#ifdef CONFIG_IGB_DCA 206static int igb_notify_dca(struct notifier_block *, unsigned long, void *); 207static struct notifier_block dca_notifier = { 208 .notifier_call = igb_notify_dca, 209 .next = NULL, 210 .priority = 0 211}; 212#endif 213#ifdef CONFIG_NET_POLL_CONTROLLER 214/* for netdump / net console */ 215static void igb_netpoll(struct net_device *); 216#endif 217#ifdef CONFIG_PCI_IOV 218static unsigned int max_vfs = 0; 219module_param(max_vfs, uint, 0); 220MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate " 221 "per physical function"); 222#endif /* CONFIG_PCI_IOV */ 223 224static pci_ers_result_t igb_io_error_detected(struct pci_dev *, 225 pci_channel_state_t); 226static pci_ers_result_t igb_io_slot_reset(struct pci_dev *); 227static void igb_io_resume(struct pci_dev *); 228 229static const struct pci_error_handlers igb_err_handler = { 230 .error_detected = igb_io_error_detected, 231 .slot_reset = igb_io_slot_reset, 232 .resume = igb_io_resume, 233}; 234 235static void igb_init_dmac(struct igb_adapter *adapter, u32 pba); 236 237static struct pci_driver igb_driver = { 238 .name = igb_driver_name, 239 .id_table = igb_pci_tbl, 240 .probe = igb_probe, 241 .remove = igb_remove, 242#ifdef CONFIG_PM 243 .driver.pm = &igb_pm_ops, 244#endif 245 .shutdown = igb_shutdown, 246 .sriov_configure = igb_pci_sriov_configure, 247 .err_handler = &igb_err_handler 248}; 249 250MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>"); 251MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver"); 252MODULE_LICENSE("GPL"); 253MODULE_VERSION(DRV_VERSION); 254 255#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK) 256static int debug = -1; 257module_param(debug, int, 0); 258MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); 259 260struct igb_reg_info { 261 u32 ofs; 262 char *name; 263}; 264 265static const struct igb_reg_info igb_reg_info_tbl[] = { 266 267 /* General Registers */ 268 {E1000_CTRL, "CTRL"}, 269 {E1000_STATUS, "STATUS"}, 270 {E1000_CTRL_EXT, "CTRL_EXT"}, 271 272 /* Interrupt Registers */ 273 {E1000_ICR, "ICR"}, 274 275 /* RX Registers */ 276 {E1000_RCTL, "RCTL"}, 277 {E1000_RDLEN(0), "RDLEN"}, 278 {E1000_RDH(0), "RDH"}, 279 {E1000_RDT(0), "RDT"}, 280 {E1000_RXDCTL(0), "RXDCTL"}, 281 {E1000_RDBAL(0), "RDBAL"}, 282 {E1000_RDBAH(0), "RDBAH"}, 283 284 /* TX Registers */ 285 {E1000_TCTL, "TCTL"}, 286 {E1000_TDBAL(0), "TDBAL"}, 287 {E1000_TDBAH(0), "TDBAH"}, 288 {E1000_TDLEN(0), "TDLEN"}, 289 {E1000_TDH(0), "TDH"}, 290 {E1000_TDT(0), "TDT"}, 291 {E1000_TXDCTL(0), "TXDCTL"}, 292 {E1000_TDFH, "TDFH"}, 293 {E1000_TDFT, "TDFT"}, 294 {E1000_TDFHS, "TDFHS"}, 295 {E1000_TDFPC, "TDFPC"}, 296 297 /* List Terminator */ 298 {} 299}; 300 301/* igb_regdump - register printout routine */ 302static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo) 303{ 304 int n = 0; 305 char rname[16]; 306 u32 regs[8]; 307 308 switch (reginfo->ofs) { 309 case E1000_RDLEN(0): 310 for (n = 0; n < 4; n++) 311 regs[n] = rd32(E1000_RDLEN(n)); 312 break; 313 case E1000_RDH(0): 314 for (n = 0; n < 4; n++) 315 regs[n] = rd32(E1000_RDH(n)); 316 break; 317 case E1000_RDT(0): 318 for (n = 0; n < 4; n++) 319 regs[n] = rd32(E1000_RDT(n)); 320 break; 321 case E1000_RXDCTL(0): 322 for (n = 0; n < 4; n++) 323 regs[n] = rd32(E1000_RXDCTL(n)); 324 break; 325 case E1000_RDBAL(0): 326 for (n = 0; n < 4; n++) 327 regs[n] = rd32(E1000_RDBAL(n)); 328 break; 329 case E1000_RDBAH(0): 330 for (n = 0; n < 4; n++) 331 regs[n] = rd32(E1000_RDBAH(n)); 332 break; 333 case E1000_TDBAL(0): 334 for (n = 0; n < 4; n++) 335 regs[n] = rd32(E1000_RDBAL(n)); 336 break; 337 case E1000_TDBAH(0): 338 for (n = 0; n < 4; n++) 339 regs[n] = rd32(E1000_TDBAH(n)); 340 break; 341 case E1000_TDLEN(0): 342 for (n = 0; n < 4; n++) 343 regs[n] = rd32(E1000_TDLEN(n)); 344 break; 345 case E1000_TDH(0): 346 for (n = 0; n < 4; n++) 347 regs[n] = rd32(E1000_TDH(n)); 348 break; 349 case E1000_TDT(0): 350 for (n = 0; n < 4; n++) 351 regs[n] = rd32(E1000_TDT(n)); 352 break; 353 case E1000_TXDCTL(0): 354 for (n = 0; n < 4; n++) 355 regs[n] = rd32(E1000_TXDCTL(n)); 356 break; 357 default: 358 pr_info("%-15s %08x\n", reginfo->name, rd32(reginfo->ofs)); 359 return; 360 } 361 362 snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]"); 363 pr_info("%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1], 364 regs[2], regs[3]); 365} 366 367/* igb_dump - Print registers, Tx-rings and Rx-rings */ 368static void igb_dump(struct igb_adapter *adapter) 369{ 370 struct net_device *netdev = adapter->netdev; 371 struct e1000_hw *hw = &adapter->hw; 372 struct igb_reg_info *reginfo; 373 struct igb_ring *tx_ring; 374 union e1000_adv_tx_desc *tx_desc; 375 struct my_u0 { u64 a; u64 b; } *u0; 376 struct igb_ring *rx_ring; 377 union e1000_adv_rx_desc *rx_desc; 378 u32 staterr; 379 u16 i, n; 380 381 if (!netif_msg_hw(adapter)) 382 return; 383 384 /* Print netdevice Info */ 385 if (netdev) { 386 dev_info(&adapter->pdev->dev, "Net device Info\n"); 387 pr_info("Device Name state trans_start " 388 "last_rx\n"); 389 pr_info("%-15s %016lX %016lX %016lX\n", netdev->name, 390 netdev->state, netdev->trans_start, netdev->last_rx); 391 } 392 393 /* Print Registers */ 394 dev_info(&adapter->pdev->dev, "Register Dump\n"); 395 pr_info(" Register Name Value\n"); 396 for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl; 397 reginfo->name; reginfo++) { 398 igb_regdump(hw, reginfo); 399 } 400 401 /* Print TX Ring Summary */ 402 if (!netdev || !netif_running(netdev)) 403 goto exit; 404 405 dev_info(&adapter->pdev->dev, "TX Rings Summary\n"); 406 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n"); 407 for (n = 0; n < adapter->num_tx_queues; n++) { 408 struct igb_tx_buffer *buffer_info; 409 tx_ring = adapter->tx_ring[n]; 410 buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean]; 411 pr_info(" %5d %5X %5X %016llX %04X %p %016llX\n", 412 n, tx_ring->next_to_use, tx_ring->next_to_clean, 413 (u64)dma_unmap_addr(buffer_info, dma), 414 dma_unmap_len(buffer_info, len), 415 buffer_info->next_to_watch, 416 (u64)buffer_info->time_stamp); 417 } 418 419 /* Print TX Rings */ 420 if (!netif_msg_tx_done(adapter)) 421 goto rx_ring_summary; 422 423 dev_info(&adapter->pdev->dev, "TX Rings Dump\n"); 424 425 /* Transmit Descriptor Formats 426 * 427 * Advanced Transmit Descriptor 428 * +--------------------------------------------------------------+ 429 * 0 | Buffer Address [63:0] | 430 * +--------------------------------------------------------------+ 431 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN | 432 * +--------------------------------------------------------------+ 433 * 63 46 45 40 39 38 36 35 32 31 24 15 0 434 */ 435 436 for (n = 0; n < adapter->num_tx_queues; n++) { 437 tx_ring = adapter->tx_ring[n]; 438 pr_info("------------------------------------\n"); 439 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index); 440 pr_info("------------------------------------\n"); 441 pr_info("T [desc] [address 63:0 ] [PlPOCIStDDM Ln] " 442 "[bi->dma ] leng ntw timestamp " 443 "bi->skb\n"); 444 445 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) { 446 const char *next_desc; 447 struct igb_tx_buffer *buffer_info; 448 tx_desc = IGB_TX_DESC(tx_ring, i); 449 buffer_info = &tx_ring->tx_buffer_info[i]; 450 u0 = (struct my_u0 *)tx_desc; 451 if (i == tx_ring->next_to_use && 452 i == tx_ring->next_to_clean) 453 next_desc = " NTC/U"; 454 else if (i == tx_ring->next_to_use) 455 next_desc = " NTU"; 456 else if (i == tx_ring->next_to_clean) 457 next_desc = " NTC"; 458 else 459 next_desc = ""; 460 461 pr_info("T [0x%03X] %016llX %016llX %016llX" 462 " %04X %p %016llX %p%s\n", i, 463 le64_to_cpu(u0->a), 464 le64_to_cpu(u0->b), 465 (u64)dma_unmap_addr(buffer_info, dma), 466 dma_unmap_len(buffer_info, len), 467 buffer_info->next_to_watch, 468 (u64)buffer_info->time_stamp, 469 buffer_info->skb, next_desc); 470 471 if (netif_msg_pktdata(adapter) && buffer_info->skb) 472 print_hex_dump(KERN_INFO, "", 473 DUMP_PREFIX_ADDRESS, 474 16, 1, buffer_info->skb->data, 475 dma_unmap_len(buffer_info, len), 476 true); 477 } 478 } 479 480 /* Print RX Rings Summary */ 481rx_ring_summary: 482 dev_info(&adapter->pdev->dev, "RX Rings Summary\n"); 483 pr_info("Queue [NTU] [NTC]\n"); 484 for (n = 0; n < adapter->num_rx_queues; n++) { 485 rx_ring = adapter->rx_ring[n]; 486 pr_info(" %5d %5X %5X\n", 487 n, rx_ring->next_to_use, rx_ring->next_to_clean); 488 } 489 490 /* Print RX Rings */ 491 if (!netif_msg_rx_status(adapter)) 492 goto exit; 493 494 dev_info(&adapter->pdev->dev, "RX Rings Dump\n"); 495 496 /* Advanced Receive Descriptor (Read) Format 497 * 63 1 0 498 * +-----------------------------------------------------+ 499 * 0 | Packet Buffer Address [63:1] |A0/NSE| 500 * +----------------------------------------------+------+ 501 * 8 | Header Buffer Address [63:1] | DD | 502 * +-----------------------------------------------------+ 503 * 504 * 505 * Advanced Receive Descriptor (Write-Back) Format 506 * 507 * 63 48 47 32 31 30 21 20 17 16 4 3 0 508 * +------------------------------------------------------+ 509 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS | 510 * | Checksum Ident | | | | Type | Type | 511 * +------------------------------------------------------+ 512 * 8 | VLAN Tag | Length | Extended Error | Extended Status | 513 * +------------------------------------------------------+ 514 * 63 48 47 32 31 20 19 0 515 */ 516 517 for (n = 0; n < adapter->num_rx_queues; n++) { 518 rx_ring = adapter->rx_ring[n]; 519 pr_info("------------------------------------\n"); 520 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index); 521 pr_info("------------------------------------\n"); 522 pr_info("R [desc] [ PktBuf A0] [ HeadBuf DD] " 523 "[bi->dma ] [bi->skb] <-- Adv Rx Read format\n"); 524 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] -----" 525 "----------- [bi->skb] <-- Adv Rx Write-Back format\n"); 526 527 for (i = 0; i < rx_ring->count; i++) { 528 const char *next_desc; 529 struct igb_rx_buffer *buffer_info; 530 buffer_info = &rx_ring->rx_buffer_info[i]; 531 rx_desc = IGB_RX_DESC(rx_ring, i); 532 u0 = (struct my_u0 *)rx_desc; 533 staterr = le32_to_cpu(rx_desc->wb.upper.status_error); 534 535 if (i == rx_ring->next_to_use) 536 next_desc = " NTU"; 537 else if (i == rx_ring->next_to_clean) 538 next_desc = " NTC"; 539 else 540 next_desc = ""; 541 542 if (staterr & E1000_RXD_STAT_DD) { 543 /* Descriptor Done */ 544 pr_info("%s[0x%03X] %016llX %016llX ---------------- %s\n", 545 "RWB", i, 546 le64_to_cpu(u0->a), 547 le64_to_cpu(u0->b), 548 next_desc); 549 } else { 550 pr_info("%s[0x%03X] %016llX %016llX %016llX %s\n", 551 "R ", i, 552 le64_to_cpu(u0->a), 553 le64_to_cpu(u0->b), 554 (u64)buffer_info->dma, 555 next_desc); 556 557 if (netif_msg_pktdata(adapter) && 558 buffer_info->dma && buffer_info->page) { 559 print_hex_dump(KERN_INFO, "", 560 DUMP_PREFIX_ADDRESS, 561 16, 1, 562 page_address(buffer_info->page) + 563 buffer_info->page_offset, 564 IGB_RX_BUFSZ, true); 565 } 566 } 567 } 568 } 569 570exit: 571 return; 572} 573 574/** 575 * igb_get_i2c_data - Reads the I2C SDA data bit 576 * @hw: pointer to hardware structure 577 * @i2cctl: Current value of I2CCTL register 578 * 579 * Returns the I2C data bit value 580 **/ 581static int igb_get_i2c_data(void *data) 582{ 583 struct igb_adapter *adapter = (struct igb_adapter *)data; 584 struct e1000_hw *hw = &adapter->hw; 585 s32 i2cctl = rd32(E1000_I2CPARAMS); 586 587 return ((i2cctl & E1000_I2C_DATA_IN) != 0); 588} 589 590/** 591 * igb_set_i2c_data - Sets the I2C data bit 592 * @data: pointer to hardware structure 593 * @state: I2C data value (0 or 1) to set 594 * 595 * Sets the I2C data bit 596 **/ 597static void igb_set_i2c_data(void *data, int state) 598{ 599 struct igb_adapter *adapter = (struct igb_adapter *)data; 600 struct e1000_hw *hw = &adapter->hw; 601 s32 i2cctl = rd32(E1000_I2CPARAMS); 602 603 if (state) 604 i2cctl |= E1000_I2C_DATA_OUT; 605 else 606 i2cctl &= ~E1000_I2C_DATA_OUT; 607 608 i2cctl &= ~E1000_I2C_DATA_OE_N; 609 i2cctl |= E1000_I2C_CLK_OE_N; 610 wr32(E1000_I2CPARAMS, i2cctl); 611 wrfl(); 612 613} 614 615/** 616 * igb_set_i2c_clk - Sets the I2C SCL clock 617 * @data: pointer to hardware structure 618 * @state: state to set clock 619 * 620 * Sets the I2C clock line to state 621 **/ 622static void igb_set_i2c_clk(void *data, int state) 623{ 624 struct igb_adapter *adapter = (struct igb_adapter *)data; 625 struct e1000_hw *hw = &adapter->hw; 626 s32 i2cctl = rd32(E1000_I2CPARAMS); 627 628 if (state) { 629 i2cctl |= E1000_I2C_CLK_OUT; 630 i2cctl &= ~E1000_I2C_CLK_OE_N; 631 } else { 632 i2cctl &= ~E1000_I2C_CLK_OUT; 633 i2cctl &= ~E1000_I2C_CLK_OE_N; 634 } 635 wr32(E1000_I2CPARAMS, i2cctl); 636 wrfl(); 637} 638 639/** 640 * igb_get_i2c_clk - Gets the I2C SCL clock state 641 * @data: pointer to hardware structure 642 * 643 * Gets the I2C clock state 644 **/ 645static int igb_get_i2c_clk(void *data) 646{ 647 struct igb_adapter *adapter = (struct igb_adapter *)data; 648 struct e1000_hw *hw = &adapter->hw; 649 s32 i2cctl = rd32(E1000_I2CPARAMS); 650 651 return ((i2cctl & E1000_I2C_CLK_IN) != 0); 652} 653 654static const struct i2c_algo_bit_data igb_i2c_algo = { 655 .setsda = igb_set_i2c_data, 656 .setscl = igb_set_i2c_clk, 657 .getsda = igb_get_i2c_data, 658 .getscl = igb_get_i2c_clk, 659 .udelay = 5, 660 .timeout = 20, 661}; 662 663/** 664 * igb_get_hw_dev - return device 665 * @hw: pointer to hardware structure 666 * 667 * used by hardware layer to print debugging information 668 **/ 669struct net_device *igb_get_hw_dev(struct e1000_hw *hw) 670{ 671 struct igb_adapter *adapter = hw->back; 672 return adapter->netdev; 673} 674 675/** 676 * igb_init_module - Driver Registration Routine 677 * 678 * igb_init_module is the first routine called when the driver is 679 * loaded. All it does is register with the PCI subsystem. 680 **/ 681static int __init igb_init_module(void) 682{ 683 int ret; 684 pr_info("%s - version %s\n", 685 igb_driver_string, igb_driver_version); 686 687 pr_info("%s\n", igb_copyright); 688 689#ifdef CONFIG_IGB_DCA 690 dca_register_notify(&dca_notifier); 691#endif 692 ret = pci_register_driver(&igb_driver); 693 return ret; 694} 695 696module_init(igb_init_module); 697 698/** 699 * igb_exit_module - Driver Exit Cleanup Routine 700 * 701 * igb_exit_module is called just before the driver is removed 702 * from memory. 703 **/ 704static void __exit igb_exit_module(void) 705{ 706#ifdef CONFIG_IGB_DCA 707 dca_unregister_notify(&dca_notifier); 708#endif 709 pci_unregister_driver(&igb_driver); 710} 711 712module_exit(igb_exit_module); 713 714#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1)) 715/** 716 * igb_cache_ring_register - Descriptor ring to register mapping 717 * @adapter: board private structure to initialize 718 * 719 * Once we know the feature-set enabled for the device, we'll cache 720 * the register offset the descriptor ring is assigned to. 721 **/ 722static void igb_cache_ring_register(struct igb_adapter *adapter) 723{ 724 int i = 0, j = 0; 725 u32 rbase_offset = adapter->vfs_allocated_count; 726 727 switch (adapter->hw.mac.type) { 728 case e1000_82576: 729 /* The queues are allocated for virtualization such that VF 0 730 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc. 731 * In order to avoid collision we start at the first free queue 732 * and continue consuming queues in the same sequence 733 */ 734 if (adapter->vfs_allocated_count) { 735 for (; i < adapter->rss_queues; i++) 736 adapter->rx_ring[i]->reg_idx = rbase_offset + 737 Q_IDX_82576(i); 738 } 739 case e1000_82575: 740 case e1000_82580: 741 case e1000_i350: 742 case e1000_i354: 743 case e1000_i210: 744 case e1000_i211: 745 default: 746 for (; i < adapter->num_rx_queues; i++) 747 adapter->rx_ring[i]->reg_idx = rbase_offset + i; 748 for (; j < adapter->num_tx_queues; j++) 749 adapter->tx_ring[j]->reg_idx = rbase_offset + j; 750 break; 751 } 752} 753 754u32 igb_rd32(struct e1000_hw *hw, u32 reg) 755{ 756 struct igb_adapter *igb = container_of(hw, struct igb_adapter, hw); 757 u8 __iomem *hw_addr = ACCESS_ONCE(hw->hw_addr); 758 u32 value = 0; 759 760 if (E1000_REMOVED(hw_addr)) 761 return ~value; 762 763 value = readl(&hw_addr[reg]); 764 765 /* reads should not return all F's */ 766 if (!(~value) && (!reg || !(~readl(hw_addr)))) { 767 struct net_device *netdev = igb->netdev; 768 hw->hw_addr = NULL; 769 netif_device_detach(netdev); 770 netdev_err(netdev, "PCIe link lost, device now detached\n"); 771 } 772 773 return value; 774} 775 776/** 777 * igb_write_ivar - configure ivar for given MSI-X vector 778 * @hw: pointer to the HW structure 779 * @msix_vector: vector number we are allocating to a given ring 780 * @index: row index of IVAR register to write within IVAR table 781 * @offset: column offset of in IVAR, should be multiple of 8 782 * 783 * This function is intended to handle the writing of the IVAR register 784 * for adapters 82576 and newer. The IVAR table consists of 2 columns, 785 * each containing an cause allocation for an Rx and Tx ring, and a 786 * variable number of rows depending on the number of queues supported. 787 **/ 788static void igb_write_ivar(struct e1000_hw *hw, int msix_vector, 789 int index, int offset) 790{ 791 u32 ivar = array_rd32(E1000_IVAR0, index); 792 793 /* clear any bits that are currently set */ 794 ivar &= ~((u32)0xFF << offset); 795 796 /* write vector and valid bit */ 797 ivar |= (msix_vector | E1000_IVAR_VALID) << offset; 798 799 array_wr32(E1000_IVAR0, index, ivar); 800} 801 802#define IGB_N0_QUEUE -1 803static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector) 804{ 805 struct igb_adapter *adapter = q_vector->adapter; 806 struct e1000_hw *hw = &adapter->hw; 807 int rx_queue = IGB_N0_QUEUE; 808 int tx_queue = IGB_N0_QUEUE; 809 u32 msixbm = 0; 810 811 if (q_vector->rx.ring) 812 rx_queue = q_vector->rx.ring->reg_idx; 813 if (q_vector->tx.ring) 814 tx_queue = q_vector->tx.ring->reg_idx; 815 816 switch (hw->mac.type) { 817 case e1000_82575: 818 /* The 82575 assigns vectors using a bitmask, which matches the 819 * bitmask for the EICR/EIMS/EIMC registers. To assign one 820 * or more queues to a vector, we write the appropriate bits 821 * into the MSIXBM register for that vector. 822 */ 823 if (rx_queue > IGB_N0_QUEUE) 824 msixbm = E1000_EICR_RX_QUEUE0 << rx_queue; 825 if (tx_queue > IGB_N0_QUEUE) 826 msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue; 827 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) && msix_vector == 0) 828 msixbm |= E1000_EIMS_OTHER; 829 array_wr32(E1000_MSIXBM(0), msix_vector, msixbm); 830 q_vector->eims_value = msixbm; 831 break; 832 case e1000_82576: 833 /* 82576 uses a table that essentially consists of 2 columns 834 * with 8 rows. The ordering is column-major so we use the 835 * lower 3 bits as the row index, and the 4th bit as the 836 * column offset. 837 */ 838 if (rx_queue > IGB_N0_QUEUE) 839 igb_write_ivar(hw, msix_vector, 840 rx_queue & 0x7, 841 (rx_queue & 0x8) << 1); 842 if (tx_queue > IGB_N0_QUEUE) 843 igb_write_ivar(hw, msix_vector, 844 tx_queue & 0x7, 845 ((tx_queue & 0x8) << 1) + 8); 846 q_vector->eims_value = 1 << msix_vector; 847 break; 848 case e1000_82580: 849 case e1000_i350: 850 case e1000_i354: 851 case e1000_i210: 852 case e1000_i211: 853 /* On 82580 and newer adapters the scheme is similar to 82576 854 * however instead of ordering column-major we have things 855 * ordered row-major. So we traverse the table by using 856 * bit 0 as the column offset, and the remaining bits as the 857 * row index. 858 */ 859 if (rx_queue > IGB_N0_QUEUE) 860 igb_write_ivar(hw, msix_vector, 861 rx_queue >> 1, 862 (rx_queue & 0x1) << 4); 863 if (tx_queue > IGB_N0_QUEUE) 864 igb_write_ivar(hw, msix_vector, 865 tx_queue >> 1, 866 ((tx_queue & 0x1) << 4) + 8); 867 q_vector->eims_value = 1 << msix_vector; 868 break; 869 default: 870 BUG(); 871 break; 872 } 873 874 /* add q_vector eims value to global eims_enable_mask */ 875 adapter->eims_enable_mask |= q_vector->eims_value; 876 877 /* configure q_vector to set itr on first interrupt */ 878 q_vector->set_itr = 1; 879} 880 881/** 882 * igb_configure_msix - Configure MSI-X hardware 883 * @adapter: board private structure to initialize 884 * 885 * igb_configure_msix sets up the hardware to properly 886 * generate MSI-X interrupts. 887 **/ 888static void igb_configure_msix(struct igb_adapter *adapter) 889{ 890 u32 tmp; 891 int i, vector = 0; 892 struct e1000_hw *hw = &adapter->hw; 893 894 adapter->eims_enable_mask = 0; 895 896 /* set vector for other causes, i.e. link changes */ 897 switch (hw->mac.type) { 898 case e1000_82575: 899 tmp = rd32(E1000_CTRL_EXT); 900 /* enable MSI-X PBA support*/ 901 tmp |= E1000_CTRL_EXT_PBA_CLR; 902 903 /* Auto-Mask interrupts upon ICR read. */ 904 tmp |= E1000_CTRL_EXT_EIAME; 905 tmp |= E1000_CTRL_EXT_IRCA; 906 907 wr32(E1000_CTRL_EXT, tmp); 908 909 /* enable msix_other interrupt */ 910 array_wr32(E1000_MSIXBM(0), vector++, E1000_EIMS_OTHER); 911 adapter->eims_other = E1000_EIMS_OTHER; 912 913 break; 914 915 case e1000_82576: 916 case e1000_82580: 917 case e1000_i350: 918 case e1000_i354: 919 case e1000_i210: 920 case e1000_i211: 921 /* Turn on MSI-X capability first, or our settings 922 * won't stick. And it will take days to debug. 923 */ 924 wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE | 925 E1000_GPIE_PBA | E1000_GPIE_EIAME | 926 E1000_GPIE_NSICR); 927 928 /* enable msix_other interrupt */ 929 adapter->eims_other = 1 << vector; 930 tmp = (vector++ | E1000_IVAR_VALID) << 8; 931 932 wr32(E1000_IVAR_MISC, tmp); 933 break; 934 default: 935 /* do nothing, since nothing else supports MSI-X */ 936 break; 937 } /* switch (hw->mac.type) */ 938 939 adapter->eims_enable_mask |= adapter->eims_other; 940 941 for (i = 0; i < adapter->num_q_vectors; i++) 942 igb_assign_vector(adapter->q_vector[i], vector++); 943 944 wrfl(); 945} 946 947/** 948 * igb_request_msix - Initialize MSI-X interrupts 949 * @adapter: board private structure to initialize 950 * 951 * igb_request_msix allocates MSI-X vectors and requests interrupts from the 952 * kernel. 953 **/ 954static int igb_request_msix(struct igb_adapter *adapter) 955{ 956 struct net_device *netdev = adapter->netdev; 957 struct e1000_hw *hw = &adapter->hw; 958 int i, err = 0, vector = 0, free_vector = 0; 959 960 err = request_irq(adapter->msix_entries[vector].vector, 961 igb_msix_other, 0, netdev->name, adapter); 962 if (err) 963 goto err_out; 964 965 for (i = 0; i < adapter->num_q_vectors; i++) { 966 struct igb_q_vector *q_vector = adapter->q_vector[i]; 967 968 vector++; 969 970 q_vector->itr_register = hw->hw_addr + E1000_EITR(vector); 971 972 if (q_vector->rx.ring && q_vector->tx.ring) 973 sprintf(q_vector->name, "%s-TxRx-%u", netdev->name, 974 q_vector->rx.ring->queue_index); 975 else if (q_vector->tx.ring) 976 sprintf(q_vector->name, "%s-tx-%u", netdev->name, 977 q_vector->tx.ring->queue_index); 978 else if (q_vector->rx.ring) 979 sprintf(q_vector->name, "%s-rx-%u", netdev->name, 980 q_vector->rx.ring->queue_index); 981 else 982 sprintf(q_vector->name, "%s-unused", netdev->name); 983 984 err = request_irq(adapter->msix_entries[vector].vector, 985 igb_msix_ring, 0, q_vector->name, 986 q_vector); 987 if (err) 988 goto err_free; 989 } 990 991 igb_configure_msix(adapter); 992 return 0; 993 994err_free: 995 /* free already assigned IRQs */ 996 free_irq(adapter->msix_entries[free_vector++].vector, adapter); 997 998 vector--; 999 for (i = 0; i < vector; i++) { 1000 free_irq(adapter->msix_entries[free_vector++].vector, 1001 adapter->q_vector[i]); 1002 } 1003err_out: 1004 return err; 1005} 1006 1007/** 1008 * igb_free_q_vector - Free memory allocated for specific interrupt vector 1009 * @adapter: board private structure to initialize 1010 * @v_idx: Index of vector to be freed 1011 * 1012 * This function frees the memory allocated to the q_vector. 1013 **/ 1014static void igb_free_q_vector(struct igb_adapter *adapter, int v_idx) 1015{ 1016 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1017 1018 adapter->q_vector[v_idx] = NULL; 1019 1020 /* igb_get_stats64() might access the rings on this vector, 1021 * we must wait a grace period before freeing it. 1022 */ 1023 kfree_rcu(q_vector, rcu); 1024} 1025 1026/** 1027 * igb_reset_q_vector - Reset config for interrupt vector 1028 * @adapter: board private structure to initialize 1029 * @v_idx: Index of vector to be reset 1030 * 1031 * If NAPI is enabled it will delete any references to the 1032 * NAPI struct. This is preparation for igb_free_q_vector. 1033 **/ 1034static void igb_reset_q_vector(struct igb_adapter *adapter, int v_idx) 1035{ 1036 struct igb_q_vector *q_vector = adapter->q_vector[v_idx]; 1037 1038 /* Coming from igb_set_interrupt_capability, the vectors are not yet 1039 * allocated. So, q_vector is NULL so we should stop here. 1040 */ 1041 if (!q_vector) 1042 return; 1043 1044 if (q_vector->tx.ring) 1045 adapter->tx_ring[q_vector->tx.ring->queue_index] = NULL; 1046 1047 if (q_vector->rx.ring) 1048 adapter->tx_ring[q_vector->rx.ring->queue_index] = NULL; 1049 1050 netif_napi_del(&q_vector->napi); 1051 1052} 1053 1054static void igb_reset_interrupt_capability(struct igb_adapter *adapter) 1055{ 1056 int v_idx = adapter->num_q_vectors; 1057 1058 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1059 pci_disable_msix(adapter->pdev); 1060 else if (adapter->flags & IGB_FLAG_HAS_MSI) 1061 pci_disable_msi(adapter->pdev); 1062 1063 while (v_idx--) 1064 igb_reset_q_vector(adapter, v_idx); 1065} 1066 1067/** 1068 * igb_free_q_vectors - Free memory allocated for interrupt vectors 1069 * @adapter: board private structure to initialize 1070 * 1071 * This function frees the memory allocated to the q_vectors. In addition if 1072 * NAPI is enabled it will delete any references to the NAPI struct prior 1073 * to freeing the q_vector. 1074 **/ 1075static void igb_free_q_vectors(struct igb_adapter *adapter) 1076{ 1077 int v_idx = adapter->num_q_vectors; 1078 1079 adapter->num_tx_queues = 0; 1080 adapter->num_rx_queues = 0; 1081 adapter->num_q_vectors = 0; 1082 1083 while (v_idx--) { 1084 igb_reset_q_vector(adapter, v_idx); 1085 igb_free_q_vector(adapter, v_idx); 1086 } 1087} 1088 1089/** 1090 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts 1091 * @adapter: board private structure to initialize 1092 * 1093 * This function resets the device so that it has 0 Rx queues, Tx queues, and 1094 * MSI-X interrupts allocated. 1095 */ 1096static void igb_clear_interrupt_scheme(struct igb_adapter *adapter) 1097{ 1098 igb_free_q_vectors(adapter); 1099 igb_reset_interrupt_capability(adapter); 1100} 1101 1102/** 1103 * igb_set_interrupt_capability - set MSI or MSI-X if supported 1104 * @adapter: board private structure to initialize 1105 * @msix: boolean value of MSIX capability 1106 * 1107 * Attempt to configure interrupts using the best available 1108 * capabilities of the hardware and kernel. 1109 **/ 1110static void igb_set_interrupt_capability(struct igb_adapter *adapter, bool msix) 1111{ 1112 int err; 1113 int numvecs, i; 1114 1115 if (!msix) 1116 goto msi_only; 1117 adapter->flags |= IGB_FLAG_HAS_MSIX; 1118 1119 /* Number of supported queues. */ 1120 adapter->num_rx_queues = adapter->rss_queues; 1121 if (adapter->vfs_allocated_count) 1122 adapter->num_tx_queues = 1; 1123 else 1124 adapter->num_tx_queues = adapter->rss_queues; 1125 1126 /* start with one vector for every Rx queue */ 1127 numvecs = adapter->num_rx_queues; 1128 1129 /* if Tx handler is separate add 1 for every Tx queue */ 1130 if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS)) 1131 numvecs += adapter->num_tx_queues; 1132 1133 /* store the number of vectors reserved for queues */ 1134 adapter->num_q_vectors = numvecs; 1135 1136 /* add 1 vector for link status interrupts */ 1137 numvecs++; 1138 for (i = 0; i < numvecs; i++) 1139 adapter->msix_entries[i].entry = i; 1140 1141 err = pci_enable_msix_range(adapter->pdev, 1142 adapter->msix_entries, 1143 numvecs, 1144 numvecs); 1145 if (err > 0) 1146 return; 1147 1148 igb_reset_interrupt_capability(adapter); 1149 1150 /* If we can't do MSI-X, try MSI */ 1151msi_only: 1152 adapter->flags &= ~IGB_FLAG_HAS_MSIX; 1153#ifdef CONFIG_PCI_IOV 1154 /* disable SR-IOV for non MSI-X configurations */ 1155 if (adapter->vf_data) { 1156 struct e1000_hw *hw = &adapter->hw; 1157 /* disable iov and allow time for transactions to clear */ 1158 pci_disable_sriov(adapter->pdev); 1159 msleep(500); 1160 1161 kfree(adapter->vf_data); 1162 adapter->vf_data = NULL; 1163 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 1164 wrfl(); 1165 msleep(100); 1166 dev_info(&adapter->pdev->dev, "IOV Disabled\n"); 1167 } 1168#endif 1169 adapter->vfs_allocated_count = 0; 1170 adapter->rss_queues = 1; 1171 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 1172 adapter->num_rx_queues = 1; 1173 adapter->num_tx_queues = 1; 1174 adapter->num_q_vectors = 1; 1175 if (!pci_enable_msi(adapter->pdev)) 1176 adapter->flags |= IGB_FLAG_HAS_MSI; 1177} 1178 1179static void igb_add_ring(struct igb_ring *ring, 1180 struct igb_ring_container *head) 1181{ 1182 head->ring = ring; 1183 head->count++; 1184} 1185 1186/** 1187 * igb_alloc_q_vector - Allocate memory for a single interrupt vector 1188 * @adapter: board private structure to initialize 1189 * @v_count: q_vectors allocated on adapter, used for ring interleaving 1190 * @v_idx: index of vector in adapter struct 1191 * @txr_count: total number of Tx rings to allocate 1192 * @txr_idx: index of first Tx ring to allocate 1193 * @rxr_count: total number of Rx rings to allocate 1194 * @rxr_idx: index of first Rx ring to allocate 1195 * 1196 * We allocate one q_vector. If allocation fails we return -ENOMEM. 1197 **/ 1198static int igb_alloc_q_vector(struct igb_adapter *adapter, 1199 int v_count, int v_idx, 1200 int txr_count, int txr_idx, 1201 int rxr_count, int rxr_idx) 1202{ 1203 struct igb_q_vector *q_vector; 1204 struct igb_ring *ring; 1205 int ring_count, size; 1206 1207 /* igb only supports 1 Tx and/or 1 Rx queue per vector */ 1208 if (txr_count > 1 || rxr_count > 1) 1209 return -ENOMEM; 1210 1211 ring_count = txr_count + rxr_count; 1212 size = sizeof(struct igb_q_vector) + 1213 (sizeof(struct igb_ring) * ring_count); 1214 1215 /* allocate q_vector and rings */ 1216 q_vector = adapter->q_vector[v_idx]; 1217 if (!q_vector) 1218 q_vector = kzalloc(size, GFP_KERNEL); 1219 if (!q_vector) 1220 return -ENOMEM; 1221 1222 /* initialize NAPI */ 1223 netif_napi_add(adapter->netdev, &q_vector->napi, 1224 igb_poll, 64); 1225 1226 /* tie q_vector and adapter together */ 1227 adapter->q_vector[v_idx] = q_vector; 1228 q_vector->adapter = adapter; 1229 1230 /* initialize work limits */ 1231 q_vector->tx.work_limit = adapter->tx_work_limit; 1232 1233 /* initialize ITR configuration */ 1234 q_vector->itr_register = adapter->hw.hw_addr + E1000_EITR(0); 1235 q_vector->itr_val = IGB_START_ITR; 1236 1237 /* initialize pointer to rings */ 1238 ring = q_vector->ring; 1239 1240 /* intialize ITR */ 1241 if (rxr_count) { 1242 /* rx or rx/tx vector */ 1243 if (!adapter->rx_itr_setting || adapter->rx_itr_setting > 3) 1244 q_vector->itr_val = adapter->rx_itr_setting; 1245 } else { 1246 /* tx only vector */ 1247 if (!adapter->tx_itr_setting || adapter->tx_itr_setting > 3) 1248 q_vector->itr_val = adapter->tx_itr_setting; 1249 } 1250 1251 if (txr_count) { 1252 /* assign generic ring traits */ 1253 ring->dev = &adapter->pdev->dev; 1254 ring->netdev = adapter->netdev; 1255 1256 /* configure backlink on ring */ 1257 ring->q_vector = q_vector; 1258 1259 /* update q_vector Tx values */ 1260 igb_add_ring(ring, &q_vector->tx); 1261 1262 /* For 82575, context index must be unique per ring. */ 1263 if (adapter->hw.mac.type == e1000_82575) 1264 set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags); 1265 1266 /* apply Tx specific ring traits */ 1267 ring->count = adapter->tx_ring_count; 1268 ring->queue_index = txr_idx; 1269 1270 u64_stats_init(&ring->tx_syncp); 1271 u64_stats_init(&ring->tx_syncp2); 1272 1273 /* assign ring to adapter */ 1274 adapter->tx_ring[txr_idx] = ring; 1275 1276 /* push pointer to next ring */ 1277 ring++; 1278 } 1279 1280 if (rxr_count) { 1281 /* assign generic ring traits */ 1282 ring->dev = &adapter->pdev->dev; 1283 ring->netdev = adapter->netdev; 1284 1285 /* configure backlink on ring */ 1286 ring->q_vector = q_vector; 1287 1288 /* update q_vector Rx values */ 1289 igb_add_ring(ring, &q_vector->rx); 1290 1291 /* set flag indicating ring supports SCTP checksum offload */ 1292 if (adapter->hw.mac.type >= e1000_82576) 1293 set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags); 1294 1295 /* 1296 * On i350, i354, i210, and i211, loopback VLAN packets 1297 * have the tag byte-swapped. 1298 */ 1299 if (adapter->hw.mac.type >= e1000_i350) 1300 set_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &ring->flags); 1301 1302 /* apply Rx specific ring traits */ 1303 ring->count = adapter->rx_ring_count; 1304 ring->queue_index = rxr_idx; 1305 1306 u64_stats_init(&ring->rx_syncp); 1307 1308 /* assign ring to adapter */ 1309 adapter->rx_ring[rxr_idx] = ring; 1310 } 1311 1312 return 0; 1313} 1314 1315 1316/** 1317 * igb_alloc_q_vectors - Allocate memory for interrupt vectors 1318 * @adapter: board private structure to initialize 1319 * 1320 * We allocate one q_vector per queue interrupt. If allocation fails we 1321 * return -ENOMEM. 1322 **/ 1323static int igb_alloc_q_vectors(struct igb_adapter *adapter) 1324{ 1325 int q_vectors = adapter->num_q_vectors; 1326 int rxr_remaining = adapter->num_rx_queues; 1327 int txr_remaining = adapter->num_tx_queues; 1328 int rxr_idx = 0, txr_idx = 0, v_idx = 0; 1329 int err; 1330 1331 if (q_vectors >= (rxr_remaining + txr_remaining)) { 1332 for (; rxr_remaining; v_idx++) { 1333 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1334 0, 0, 1, rxr_idx); 1335 1336 if (err) 1337 goto err_out; 1338 1339 /* update counts and index */ 1340 rxr_remaining--; 1341 rxr_idx++; 1342 } 1343 } 1344 1345 for (; v_idx < q_vectors; v_idx++) { 1346 int rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - v_idx); 1347 int tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - v_idx); 1348 err = igb_alloc_q_vector(adapter, q_vectors, v_idx, 1349 tqpv, txr_idx, rqpv, rxr_idx); 1350 1351 if (err) 1352 goto err_out; 1353 1354 /* update counts and index */ 1355 rxr_remaining -= rqpv; 1356 txr_remaining -= tqpv; 1357 rxr_idx++; 1358 txr_idx++; 1359 } 1360 1361 return 0; 1362 1363err_out: 1364 adapter->num_tx_queues = 0; 1365 adapter->num_rx_queues = 0; 1366 adapter->num_q_vectors = 0; 1367 1368 while (v_idx--) 1369 igb_free_q_vector(adapter, v_idx); 1370 1371 return -ENOMEM; 1372} 1373 1374/** 1375 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors 1376 * @adapter: board private structure to initialize 1377 * @msix: boolean value of MSIX capability 1378 * 1379 * This function initializes the interrupts and allocates all of the queues. 1380 **/ 1381static int igb_init_interrupt_scheme(struct igb_adapter *adapter, bool msix) 1382{ 1383 struct pci_dev *pdev = adapter->pdev; 1384 int err; 1385 1386 igb_set_interrupt_capability(adapter, msix); 1387 1388 err = igb_alloc_q_vectors(adapter); 1389 if (err) { 1390 dev_err(&pdev->dev, "Unable to allocate memory for vectors\n"); 1391 goto err_alloc_q_vectors; 1392 } 1393 1394 igb_cache_ring_register(adapter); 1395 1396 return 0; 1397 1398err_alloc_q_vectors: 1399 igb_reset_interrupt_capability(adapter); 1400 return err; 1401} 1402 1403/** 1404 * igb_request_irq - initialize interrupts 1405 * @adapter: board private structure to initialize 1406 * 1407 * Attempts to configure interrupts using the best available 1408 * capabilities of the hardware and kernel. 1409 **/ 1410static int igb_request_irq(struct igb_adapter *adapter) 1411{ 1412 struct net_device *netdev = adapter->netdev; 1413 struct pci_dev *pdev = adapter->pdev; 1414 int err = 0; 1415 1416 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1417 err = igb_request_msix(adapter); 1418 if (!err) 1419 goto request_done; 1420 /* fall back to MSI */ 1421 igb_free_all_tx_resources(adapter); 1422 igb_free_all_rx_resources(adapter); 1423 1424 igb_clear_interrupt_scheme(adapter); 1425 err = igb_init_interrupt_scheme(adapter, false); 1426 if (err) 1427 goto request_done; 1428 1429 igb_setup_all_tx_resources(adapter); 1430 igb_setup_all_rx_resources(adapter); 1431 igb_configure(adapter); 1432 } 1433 1434 igb_assign_vector(adapter->q_vector[0], 0); 1435 1436 if (adapter->flags & IGB_FLAG_HAS_MSI) { 1437 err = request_irq(pdev->irq, igb_intr_msi, 0, 1438 netdev->name, adapter); 1439 if (!err) 1440 goto request_done; 1441 1442 /* fall back to legacy interrupts */ 1443 igb_reset_interrupt_capability(adapter); 1444 adapter->flags &= ~IGB_FLAG_HAS_MSI; 1445 } 1446 1447 err = request_irq(pdev->irq, igb_intr, IRQF_SHARED, 1448 netdev->name, adapter); 1449 1450 if (err) 1451 dev_err(&pdev->dev, "Error %d getting interrupt\n", 1452 err); 1453 1454request_done: 1455 return err; 1456} 1457 1458static void igb_free_irq(struct igb_adapter *adapter) 1459{ 1460 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1461 int vector = 0, i; 1462 1463 free_irq(adapter->msix_entries[vector++].vector, adapter); 1464 1465 for (i = 0; i < adapter->num_q_vectors; i++) 1466 free_irq(adapter->msix_entries[vector++].vector, 1467 adapter->q_vector[i]); 1468 } else { 1469 free_irq(adapter->pdev->irq, adapter); 1470 } 1471} 1472 1473/** 1474 * igb_irq_disable - Mask off interrupt generation on the NIC 1475 * @adapter: board private structure 1476 **/ 1477static void igb_irq_disable(struct igb_adapter *adapter) 1478{ 1479 struct e1000_hw *hw = &adapter->hw; 1480 1481 /* we need to be careful when disabling interrupts. The VFs are also 1482 * mapped into these registers and so clearing the bits can cause 1483 * issues on the VF drivers so we only need to clear what we set 1484 */ 1485 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1486 u32 regval = rd32(E1000_EIAM); 1487 wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask); 1488 wr32(E1000_EIMC, adapter->eims_enable_mask); 1489 regval = rd32(E1000_EIAC); 1490 wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask); 1491 } 1492 1493 wr32(E1000_IAM, 0); 1494 wr32(E1000_IMC, ~0); 1495 wrfl(); 1496 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1497 int i; 1498 for (i = 0; i < adapter->num_q_vectors; i++) 1499 synchronize_irq(adapter->msix_entries[i].vector); 1500 } else { 1501 synchronize_irq(adapter->pdev->irq); 1502 } 1503} 1504 1505/** 1506 * igb_irq_enable - Enable default interrupt generation settings 1507 * @adapter: board private structure 1508 **/ 1509static void igb_irq_enable(struct igb_adapter *adapter) 1510{ 1511 struct e1000_hw *hw = &adapter->hw; 1512 1513 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 1514 u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC | E1000_IMS_DRSTA; 1515 u32 regval = rd32(E1000_EIAC); 1516 wr32(E1000_EIAC, regval | adapter->eims_enable_mask); 1517 regval = rd32(E1000_EIAM); 1518 wr32(E1000_EIAM, regval | adapter->eims_enable_mask); 1519 wr32(E1000_EIMS, adapter->eims_enable_mask); 1520 if (adapter->vfs_allocated_count) { 1521 wr32(E1000_MBVFIMR, 0xFF); 1522 ims |= E1000_IMS_VMMB; 1523 } 1524 wr32(E1000_IMS, ims); 1525 } else { 1526 wr32(E1000_IMS, IMS_ENABLE_MASK | 1527 E1000_IMS_DRSTA); 1528 wr32(E1000_IAM, IMS_ENABLE_MASK | 1529 E1000_IMS_DRSTA); 1530 } 1531} 1532 1533static void igb_update_mng_vlan(struct igb_adapter *adapter) 1534{ 1535 struct e1000_hw *hw = &adapter->hw; 1536 u16 vid = adapter->hw.mng_cookie.vlan_id; 1537 u16 old_vid = adapter->mng_vlan_id; 1538 1539 if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) { 1540 /* add VID to filter table */ 1541 igb_vfta_set(hw, vid, true); 1542 adapter->mng_vlan_id = vid; 1543 } else { 1544 adapter->mng_vlan_id = IGB_MNG_VLAN_NONE; 1545 } 1546 1547 if ((old_vid != (u16)IGB_MNG_VLAN_NONE) && 1548 (vid != old_vid) && 1549 !test_bit(old_vid, adapter->active_vlans)) { 1550 /* remove VID from filter table */ 1551 igb_vfta_set(hw, old_vid, false); 1552 } 1553} 1554 1555/** 1556 * igb_release_hw_control - release control of the h/w to f/w 1557 * @adapter: address of board private structure 1558 * 1559 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit. 1560 * For ASF and Pass Through versions of f/w this means that the 1561 * driver is no longer loaded. 1562 **/ 1563static void igb_release_hw_control(struct igb_adapter *adapter) 1564{ 1565 struct e1000_hw *hw = &adapter->hw; 1566 u32 ctrl_ext; 1567 1568 /* Let firmware take over control of h/w */ 1569 ctrl_ext = rd32(E1000_CTRL_EXT); 1570 wr32(E1000_CTRL_EXT, 1571 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD); 1572} 1573 1574/** 1575 * igb_get_hw_control - get control of the h/w from f/w 1576 * @adapter: address of board private structure 1577 * 1578 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit. 1579 * For ASF and Pass Through versions of f/w this means that 1580 * the driver is loaded. 1581 **/ 1582static void igb_get_hw_control(struct igb_adapter *adapter) 1583{ 1584 struct e1000_hw *hw = &adapter->hw; 1585 u32 ctrl_ext; 1586 1587 /* Let firmware know the driver has taken over */ 1588 ctrl_ext = rd32(E1000_CTRL_EXT); 1589 wr32(E1000_CTRL_EXT, 1590 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD); 1591} 1592 1593/** 1594 * igb_configure - configure the hardware for RX and TX 1595 * @adapter: private board structure 1596 **/ 1597static void igb_configure(struct igb_adapter *adapter) 1598{ 1599 struct net_device *netdev = adapter->netdev; 1600 int i; 1601 1602 igb_get_hw_control(adapter); 1603 igb_set_rx_mode(netdev); 1604 1605 igb_restore_vlan(adapter); 1606 1607 igb_setup_tctl(adapter); 1608 igb_setup_mrqc(adapter); 1609 igb_setup_rctl(adapter); 1610 1611 igb_configure_tx(adapter); 1612 igb_configure_rx(adapter); 1613 1614 igb_rx_fifo_flush_82575(&adapter->hw); 1615 1616 /* call igb_desc_unused which always leaves 1617 * at least 1 descriptor unused to make sure 1618 * next_to_use != next_to_clean 1619 */ 1620 for (i = 0; i < adapter->num_rx_queues; i++) { 1621 struct igb_ring *ring = adapter->rx_ring[i]; 1622 igb_alloc_rx_buffers(ring, igb_desc_unused(ring)); 1623 } 1624} 1625 1626/** 1627 * igb_power_up_link - Power up the phy/serdes link 1628 * @adapter: address of board private structure 1629 **/ 1630void igb_power_up_link(struct igb_adapter *adapter) 1631{ 1632 igb_reset_phy(&adapter->hw); 1633 1634 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1635 igb_power_up_phy_copper(&adapter->hw); 1636 else 1637 igb_power_up_serdes_link_82575(&adapter->hw); 1638} 1639 1640/** 1641 * igb_power_down_link - Power down the phy/serdes link 1642 * @adapter: address of board private structure 1643 */ 1644static void igb_power_down_link(struct igb_adapter *adapter) 1645{ 1646 if (adapter->hw.phy.media_type == e1000_media_type_copper) 1647 igb_power_down_phy_copper_82575(&adapter->hw); 1648 else 1649 igb_shutdown_serdes_link_82575(&adapter->hw); 1650} 1651 1652/** 1653 * Detect and switch function for Media Auto Sense 1654 * @adapter: address of the board private structure 1655 **/ 1656static void igb_check_swap_media(struct igb_adapter *adapter) 1657{ 1658 struct e1000_hw *hw = &adapter->hw; 1659 u32 ctrl_ext, connsw; 1660 bool swap_now = false; 1661 1662 ctrl_ext = rd32(E1000_CTRL_EXT); 1663 connsw = rd32(E1000_CONNSW); 1664 1665 /* need to live swap if current media is copper and we have fiber/serdes 1666 * to go to. 1667 */ 1668 1669 if ((hw->phy.media_type == e1000_media_type_copper) && 1670 (!(connsw & E1000_CONNSW_AUTOSENSE_EN))) { 1671 swap_now = true; 1672 } else if (!(connsw & E1000_CONNSW_SERDESD)) { 1673 /* copper signal takes time to appear */ 1674 if (adapter->copper_tries < 4) { 1675 adapter->copper_tries++; 1676 connsw |= E1000_CONNSW_AUTOSENSE_CONF; 1677 wr32(E1000_CONNSW, connsw); 1678 return; 1679 } else { 1680 adapter->copper_tries = 0; 1681 if ((connsw & E1000_CONNSW_PHYSD) && 1682 (!(connsw & E1000_CONNSW_PHY_PDN))) { 1683 swap_now = true; 1684 connsw &= ~E1000_CONNSW_AUTOSENSE_CONF; 1685 wr32(E1000_CONNSW, connsw); 1686 } 1687 } 1688 } 1689 1690 if (!swap_now) 1691 return; 1692 1693 switch (hw->phy.media_type) { 1694 case e1000_media_type_copper: 1695 netdev_info(adapter->netdev, 1696 "MAS: changing media to fiber/serdes\n"); 1697 ctrl_ext |= 1698 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1699 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1700 adapter->copper_tries = 0; 1701 break; 1702 case e1000_media_type_internal_serdes: 1703 case e1000_media_type_fiber: 1704 netdev_info(adapter->netdev, 1705 "MAS: changing media to copper\n"); 1706 ctrl_ext &= 1707 ~E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES; 1708 adapter->flags |= IGB_FLAG_MEDIA_RESET; 1709 break; 1710 default: 1711 /* shouldn't get here during regular operation */ 1712 netdev_err(adapter->netdev, 1713 "AMS: Invalid media type found, returning\n"); 1714 break; 1715 } 1716 wr32(E1000_CTRL_EXT, ctrl_ext); 1717} 1718 1719/** 1720 * igb_up - Open the interface and prepare it to handle traffic 1721 * @adapter: board private structure 1722 **/ 1723int igb_up(struct igb_adapter *adapter) 1724{ 1725 struct e1000_hw *hw = &adapter->hw; 1726 int i; 1727 1728 /* hardware has been reset, we need to reload some things */ 1729 igb_configure(adapter); 1730 1731 clear_bit(__IGB_DOWN, &adapter->state); 1732 1733 for (i = 0; i < adapter->num_q_vectors; i++) 1734 napi_enable(&(adapter->q_vector[i]->napi)); 1735 1736 if (adapter->flags & IGB_FLAG_HAS_MSIX) 1737 igb_configure_msix(adapter); 1738 else 1739 igb_assign_vector(adapter->q_vector[0], 0); 1740 1741 /* Clear any pending interrupts. */ 1742 rd32(E1000_ICR); 1743 igb_irq_enable(adapter); 1744 1745 /* notify VFs that reset has been completed */ 1746 if (adapter->vfs_allocated_count) { 1747 u32 reg_data = rd32(E1000_CTRL_EXT); 1748 reg_data |= E1000_CTRL_EXT_PFRSTD; 1749 wr32(E1000_CTRL_EXT, reg_data); 1750 } 1751 1752 netif_tx_start_all_queues(adapter->netdev); 1753 1754 /* start the watchdog. */ 1755 hw->mac.get_link_status = 1; 1756 schedule_work(&adapter->watchdog_task); 1757 1758 if ((adapter->flags & IGB_FLAG_EEE) && 1759 (!hw->dev_spec._82575.eee_disable)) 1760 adapter->eee_advert = MDIO_EEE_100TX | MDIO_EEE_1000T; 1761 1762 return 0; 1763} 1764 1765void igb_down(struct igb_adapter *adapter) 1766{ 1767 struct net_device *netdev = adapter->netdev; 1768 struct e1000_hw *hw = &adapter->hw; 1769 u32 tctl, rctl; 1770 int i; 1771 1772 /* signal that we're down so the interrupt handler does not 1773 * reschedule our watchdog timer 1774 */ 1775 set_bit(__IGB_DOWN, &adapter->state); 1776 1777 /* disable receives in the hardware */ 1778 rctl = rd32(E1000_RCTL); 1779 wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN); 1780 /* flush and sleep below */ 1781 1782 netif_tx_stop_all_queues(netdev); 1783 1784 /* disable transmits in the hardware */ 1785 tctl = rd32(E1000_TCTL); 1786 tctl &= ~E1000_TCTL_EN; 1787 wr32(E1000_TCTL, tctl); 1788 /* flush both disables and wait for them to finish */ 1789 wrfl(); 1790 msleep(10); 1791 1792 igb_irq_disable(adapter); 1793 1794 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 1795 1796 for (i = 0; i < adapter->num_q_vectors; i++) { 1797 napi_synchronize(&(adapter->q_vector[i]->napi)); 1798 napi_disable(&(adapter->q_vector[i]->napi)); 1799 } 1800 1801 1802 del_timer_sync(&adapter->watchdog_timer); 1803 del_timer_sync(&adapter->phy_info_timer); 1804 1805 netif_carrier_off(netdev); 1806 1807 /* record the stats before reset*/ 1808 spin_lock(&adapter->stats64_lock); 1809 igb_update_stats(adapter, &adapter->stats64); 1810 spin_unlock(&adapter->stats64_lock); 1811 1812 adapter->link_speed = 0; 1813 adapter->link_duplex = 0; 1814 1815 if (!pci_channel_offline(adapter->pdev)) 1816 igb_reset(adapter); 1817 igb_clean_all_tx_rings(adapter); 1818 igb_clean_all_rx_rings(adapter); 1819#ifdef CONFIG_IGB_DCA 1820 1821 /* since we reset the hardware DCA settings were cleared */ 1822 igb_setup_dca(adapter); 1823#endif 1824} 1825 1826void igb_reinit_locked(struct igb_adapter *adapter) 1827{ 1828 WARN_ON(in_interrupt()); 1829 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 1830 msleep(1); 1831 igb_down(adapter); 1832 igb_up(adapter); 1833 clear_bit(__IGB_RESETTING, &adapter->state); 1834} 1835 1836/** igb_enable_mas - Media Autosense re-enable after swap 1837 * 1838 * @adapter: adapter struct 1839 **/ 1840static s32 igb_enable_mas(struct igb_adapter *adapter) 1841{ 1842 struct e1000_hw *hw = &adapter->hw; 1843 u32 connsw; 1844 s32 ret_val = 0; 1845 1846 connsw = rd32(E1000_CONNSW); 1847 if (!(hw->phy.media_type == e1000_media_type_copper)) 1848 return ret_val; 1849 1850 /* configure for SerDes media detect */ 1851 if (!(connsw & E1000_CONNSW_SERDESD)) { 1852 connsw |= E1000_CONNSW_ENRGSRC; 1853 connsw |= E1000_CONNSW_AUTOSENSE_EN; 1854 wr32(E1000_CONNSW, connsw); 1855 wrfl(); 1856 } else if (connsw & E1000_CONNSW_SERDESD) { 1857 /* already SerDes, no need to enable anything */ 1858 return ret_val; 1859 } else { 1860 netdev_info(adapter->netdev, 1861 "MAS: Unable to configure feature, disabling..\n"); 1862 adapter->flags &= ~IGB_FLAG_MAS_ENABLE; 1863 } 1864 return ret_val; 1865} 1866 1867void igb_reset(struct igb_adapter *adapter) 1868{ 1869 struct pci_dev *pdev = adapter->pdev; 1870 struct e1000_hw *hw = &adapter->hw; 1871 struct e1000_mac_info *mac = &hw->mac; 1872 struct e1000_fc_info *fc = &hw->fc; 1873 u32 pba = 0, tx_space, min_tx_space, min_rx_space, hwm; 1874 1875 /* Repartition Pba for greater than 9k mtu 1876 * To take effect CTRL.RST is required. 1877 */ 1878 switch (mac->type) { 1879 case e1000_i350: 1880 case e1000_i354: 1881 case e1000_82580: 1882 pba = rd32(E1000_RXPBS); 1883 pba = igb_rxpbs_adjust_82580(pba); 1884 break; 1885 case e1000_82576: 1886 pba = rd32(E1000_RXPBS); 1887 pba &= E1000_RXPBS_SIZE_MASK_82576; 1888 break; 1889 case e1000_82575: 1890 case e1000_i210: 1891 case e1000_i211: 1892 default: 1893 pba = E1000_PBA_34K; 1894 break; 1895 } 1896 1897 if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) && 1898 (mac->type < e1000_82576)) { 1899 /* adjust PBA for jumbo frames */ 1900 wr32(E1000_PBA, pba); 1901 1902 /* To maintain wire speed transmits, the Tx FIFO should be 1903 * large enough to accommodate two full transmit packets, 1904 * rounded up to the next 1KB and expressed in KB. Likewise, 1905 * the Rx FIFO should be large enough to accommodate at least 1906 * one full receive packet and is similarly rounded up and 1907 * expressed in KB. 1908 */ 1909 pba = rd32(E1000_PBA); 1910 /* upper 16 bits has Tx packet buffer allocation size in KB */ 1911 tx_space = pba >> 16; 1912 /* lower 16 bits has Rx packet buffer allocation size in KB */ 1913 pba &= 0xffff; 1914 /* the Tx fifo also stores 16 bytes of information about the Tx 1915 * but don't include ethernet FCS because hardware appends it 1916 */ 1917 min_tx_space = (adapter->max_frame_size + 1918 sizeof(union e1000_adv_tx_desc) - 1919 ETH_FCS_LEN) * 2; 1920 min_tx_space = ALIGN(min_tx_space, 1024); 1921 min_tx_space >>= 10; 1922 /* software strips receive CRC, so leave room for it */ 1923 min_rx_space = adapter->max_frame_size; 1924 min_rx_space = ALIGN(min_rx_space, 1024); 1925 min_rx_space >>= 10; 1926 1927 /* If current Tx allocation is less than the min Tx FIFO size, 1928 * and the min Tx FIFO size is less than the current Rx FIFO 1929 * allocation, take space away from current Rx allocation 1930 */ 1931 if (tx_space < min_tx_space && 1932 ((min_tx_space - tx_space) < pba)) { 1933 pba = pba - (min_tx_space - tx_space); 1934 1935 /* if short on Rx space, Rx wins and must trump Tx 1936 * adjustment 1937 */ 1938 if (pba < min_rx_space) 1939 pba = min_rx_space; 1940 } 1941 wr32(E1000_PBA, pba); 1942 } 1943 1944 /* flow control settings */ 1945 /* The high water mark must be low enough to fit one full frame 1946 * (or the size used for early receive) above it in the Rx FIFO. 1947 * Set it to the lower of: 1948 * - 90% of the Rx FIFO size, or 1949 * - the full Rx FIFO size minus one full frame 1950 */ 1951 hwm = min(((pba << 10) * 9 / 10), 1952 ((pba << 10) - 2 * adapter->max_frame_size)); 1953 1954 fc->high_water = hwm & 0xFFFFFFF0; /* 16-byte granularity */ 1955 fc->low_water = fc->high_water - 16; 1956 fc->pause_time = 0xFFFF; 1957 fc->send_xon = 1; 1958 fc->current_mode = fc->requested_mode; 1959 1960 /* disable receive for all VFs and wait one second */ 1961 if (adapter->vfs_allocated_count) { 1962 int i; 1963 for (i = 0 ; i < adapter->vfs_allocated_count; i++) 1964 adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC; 1965 1966 /* ping all the active vfs to let them know we are going down */ 1967 igb_ping_all_vfs(adapter); 1968 1969 /* disable transmits and receives */ 1970 wr32(E1000_VFRE, 0); 1971 wr32(E1000_VFTE, 0); 1972 } 1973 1974 /* Allow time for pending master requests to run */ 1975 hw->mac.ops.reset_hw(hw); 1976 wr32(E1000_WUC, 0); 1977 1978 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 1979 /* need to resetup here after media swap */ 1980 adapter->ei.get_invariants(hw); 1981 adapter->flags &= ~IGB_FLAG_MEDIA_RESET; 1982 } 1983 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 1984 if (igb_enable_mas(adapter)) 1985 dev_err(&pdev->dev, 1986 "Error enabling Media Auto Sense\n"); 1987 } 1988 if (hw->mac.ops.init_hw(hw)) 1989 dev_err(&pdev->dev, "Hardware Error\n"); 1990 1991 /* Flow control settings reset on hardware reset, so guarantee flow 1992 * control is off when forcing speed. 1993 */ 1994 if (!hw->mac.autoneg) 1995 igb_force_mac_fc(hw); 1996 1997 igb_init_dmac(adapter, pba); 1998#ifdef CONFIG_IGB_HWMON 1999 /* Re-initialize the thermal sensor on i350 devices. */ 2000 if (!test_bit(__IGB_DOWN, &adapter->state)) { 2001 if (mac->type == e1000_i350 && hw->bus.func == 0) { 2002 /* If present, re-initialize the external thermal sensor 2003 * interface. 2004 */ 2005 if (adapter->ets) 2006 mac->ops.init_thermal_sensor_thresh(hw); 2007 } 2008 } 2009#endif 2010 /* Re-establish EEE setting */ 2011 if (hw->phy.media_type == e1000_media_type_copper) { 2012 switch (mac->type) { 2013 case e1000_i350: 2014 case e1000_i210: 2015 case e1000_i211: 2016 igb_set_eee_i350(hw); 2017 break; 2018 case e1000_i354: 2019 igb_set_eee_i354(hw); 2020 break; 2021 default: 2022 break; 2023 } 2024 } 2025 if (!netif_running(adapter->netdev)) 2026 igb_power_down_link(adapter); 2027 2028 igb_update_mng_vlan(adapter); 2029 2030 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */ 2031 wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE); 2032 2033 /* Re-enable PTP, where applicable. */ 2034 igb_ptp_reset(adapter); 2035 2036 igb_get_phy_info(hw); 2037} 2038 2039static netdev_features_t igb_fix_features(struct net_device *netdev, 2040 netdev_features_t features) 2041{ 2042 /* Since there is no support for separate Rx/Tx vlan accel 2043 * enable/disable make sure Tx flag is always in same state as Rx. 2044 */ 2045 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2046 features |= NETIF_F_HW_VLAN_CTAG_TX; 2047 else 2048 features &= ~NETIF_F_HW_VLAN_CTAG_TX; 2049 2050 return features; 2051} 2052 2053static int igb_set_features(struct net_device *netdev, 2054 netdev_features_t features) 2055{ 2056 netdev_features_t changed = netdev->features ^ features; 2057 struct igb_adapter *adapter = netdev_priv(netdev); 2058 2059 if (changed & NETIF_F_HW_VLAN_CTAG_RX) 2060 igb_vlan_mode(netdev, features); 2061 2062 if (!(changed & NETIF_F_RXALL)) 2063 return 0; 2064 2065 netdev->features = features; 2066 2067 if (netif_running(netdev)) 2068 igb_reinit_locked(adapter); 2069 else 2070 igb_reset(adapter); 2071 2072 return 0; 2073} 2074 2075static const struct net_device_ops igb_netdev_ops = { 2076 .ndo_open = igb_open, 2077 .ndo_stop = igb_close, 2078 .ndo_start_xmit = igb_xmit_frame, 2079 .ndo_get_stats64 = igb_get_stats64, 2080 .ndo_set_rx_mode = igb_set_rx_mode, 2081 .ndo_set_mac_address = igb_set_mac, 2082 .ndo_change_mtu = igb_change_mtu, 2083 .ndo_do_ioctl = igb_ioctl, 2084 .ndo_tx_timeout = igb_tx_timeout, 2085 .ndo_validate_addr = eth_validate_addr, 2086 .ndo_vlan_rx_add_vid = igb_vlan_rx_add_vid, 2087 .ndo_vlan_rx_kill_vid = igb_vlan_rx_kill_vid, 2088 .ndo_set_vf_mac = igb_ndo_set_vf_mac, 2089 .ndo_set_vf_vlan = igb_ndo_set_vf_vlan, 2090 .ndo_set_vf_tx_rate = igb_ndo_set_vf_bw, 2091 .ndo_set_vf_spoofchk = igb_ndo_set_vf_spoofchk, 2092 .ndo_get_vf_config = igb_ndo_get_vf_config, 2093#ifdef CONFIG_NET_POLL_CONTROLLER 2094 .ndo_poll_controller = igb_netpoll, 2095#endif 2096 .ndo_fix_features = igb_fix_features, 2097 .ndo_set_features = igb_set_features, 2098}; 2099 2100/** 2101 * igb_set_fw_version - Configure version string for ethtool 2102 * @adapter: adapter struct 2103 **/ 2104void igb_set_fw_version(struct igb_adapter *adapter) 2105{ 2106 struct e1000_hw *hw = &adapter->hw; 2107 struct e1000_fw_version fw; 2108 2109 igb_get_fw_version(hw, &fw); 2110 2111 switch (hw->mac.type) { 2112 case e1000_i210: 2113 case e1000_i211: 2114 if (!(igb_get_flash_presence_i210(hw))) { 2115 snprintf(adapter->fw_version, 2116 sizeof(adapter->fw_version), 2117 "%2d.%2d-%d", 2118 fw.invm_major, fw.invm_minor, 2119 fw.invm_img_type); 2120 break; 2121 } 2122 /* fall through */ 2123 default: 2124 /* if option is rom valid, display its version too */ 2125 if (fw.or_valid) { 2126 snprintf(adapter->fw_version, 2127 sizeof(adapter->fw_version), 2128 "%d.%d, 0x%08x, %d.%d.%d", 2129 fw.eep_major, fw.eep_minor, fw.etrack_id, 2130 fw.or_major, fw.or_build, fw.or_patch); 2131 /* no option rom */ 2132 } else if (fw.etrack_id != 0X0000) { 2133 snprintf(adapter->fw_version, 2134 sizeof(adapter->fw_version), 2135 "%d.%d, 0x%08x", 2136 fw.eep_major, fw.eep_minor, fw.etrack_id); 2137 } else { 2138 snprintf(adapter->fw_version, 2139 sizeof(adapter->fw_version), 2140 "%d.%d.%d", 2141 fw.eep_major, fw.eep_minor, fw.eep_build); 2142 } 2143 break; 2144 } 2145 return; 2146} 2147 2148/** 2149 * igb_init_mas - init Media Autosense feature if enabled in the NVM 2150 * 2151 * @adapter: adapter struct 2152 **/ 2153static void igb_init_mas(struct igb_adapter *adapter) 2154{ 2155 struct e1000_hw *hw = &adapter->hw; 2156 u16 eeprom_data; 2157 2158 hw->nvm.ops.read(hw, NVM_COMPAT, 1, &eeprom_data); 2159 switch (hw->bus.func) { 2160 case E1000_FUNC_0: 2161 if (eeprom_data & IGB_MAS_ENABLE_0) { 2162 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2163 netdev_info(adapter->netdev, 2164 "MAS: Enabling Media Autosense for port %d\n", 2165 hw->bus.func); 2166 } 2167 break; 2168 case E1000_FUNC_1: 2169 if (eeprom_data & IGB_MAS_ENABLE_1) { 2170 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2171 netdev_info(adapter->netdev, 2172 "MAS: Enabling Media Autosense for port %d\n", 2173 hw->bus.func); 2174 } 2175 break; 2176 case E1000_FUNC_2: 2177 if (eeprom_data & IGB_MAS_ENABLE_2) { 2178 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2179 netdev_info(adapter->netdev, 2180 "MAS: Enabling Media Autosense for port %d\n", 2181 hw->bus.func); 2182 } 2183 break; 2184 case E1000_FUNC_3: 2185 if (eeprom_data & IGB_MAS_ENABLE_3) { 2186 adapter->flags |= IGB_FLAG_MAS_ENABLE; 2187 netdev_info(adapter->netdev, 2188 "MAS: Enabling Media Autosense for port %d\n", 2189 hw->bus.func); 2190 } 2191 break; 2192 default: 2193 /* Shouldn't get here */ 2194 netdev_err(adapter->netdev, 2195 "MAS: Invalid port configuration, returning\n"); 2196 break; 2197 } 2198} 2199 2200/** 2201 * igb_init_i2c - Init I2C interface 2202 * @adapter: pointer to adapter structure 2203 **/ 2204static s32 igb_init_i2c(struct igb_adapter *adapter) 2205{ 2206 s32 status = E1000_SUCCESS; 2207 2208 /* I2C interface supported on i350 devices */ 2209 if (adapter->hw.mac.type != e1000_i350) 2210 return E1000_SUCCESS; 2211 2212 /* Initialize the i2c bus which is controlled by the registers. 2213 * This bus will use the i2c_algo_bit structue that implements 2214 * the protocol through toggling of the 4 bits in the register. 2215 */ 2216 adapter->i2c_adap.owner = THIS_MODULE; 2217 adapter->i2c_algo = igb_i2c_algo; 2218 adapter->i2c_algo.data = adapter; 2219 adapter->i2c_adap.algo_data = &adapter->i2c_algo; 2220 adapter->i2c_adap.dev.parent = &adapter->pdev->dev; 2221 strlcpy(adapter->i2c_adap.name, "igb BB", 2222 sizeof(adapter->i2c_adap.name)); 2223 status = i2c_bit_add_bus(&adapter->i2c_adap); 2224 return status; 2225} 2226 2227/** 2228 * igb_probe - Device Initialization Routine 2229 * @pdev: PCI device information struct 2230 * @ent: entry in igb_pci_tbl 2231 * 2232 * Returns 0 on success, negative on failure 2233 * 2234 * igb_probe initializes an adapter identified by a pci_dev structure. 2235 * The OS initialization, configuring of the adapter private structure, 2236 * and a hardware reset occur. 2237 **/ 2238static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 2239{ 2240 struct net_device *netdev; 2241 struct igb_adapter *adapter; 2242 struct e1000_hw *hw; 2243 u16 eeprom_data = 0; 2244 s32 ret_val; 2245 static int global_quad_port_a; /* global quad port a indication */ 2246 const struct e1000_info *ei = igb_info_tbl[ent->driver_data]; 2247 int err, pci_using_dac; 2248 u8 part_str[E1000_PBANUM_LENGTH]; 2249 2250 /* Catch broken hardware that put the wrong VF device ID in 2251 * the PCIe SR-IOV capability. 2252 */ 2253 if (pdev->is_virtfn) { 2254 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n", 2255 pci_name(pdev), pdev->vendor, pdev->device); 2256 return -EINVAL; 2257 } 2258 2259 err = pci_enable_device_mem(pdev); 2260 if (err) 2261 return err; 2262 2263 pci_using_dac = 0; 2264 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 2265 if (!err) { 2266 pci_using_dac = 1; 2267 } else { 2268 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2269 if (err) { 2270 dev_err(&pdev->dev, 2271 "No usable DMA configuration, aborting\n"); 2272 goto err_dma; 2273 } 2274 } 2275 2276 err = pci_request_selected_regions(pdev, pci_select_bars(pdev, 2277 IORESOURCE_MEM), 2278 igb_driver_name); 2279 if (err) 2280 goto err_pci_reg; 2281 2282 pci_enable_pcie_error_reporting(pdev); 2283 2284 pci_set_master(pdev); 2285 pci_save_state(pdev); 2286 2287 err = -ENOMEM; 2288 netdev = alloc_etherdev_mq(sizeof(struct igb_adapter), 2289 IGB_MAX_TX_QUEUES); 2290 if (!netdev) 2291 goto err_alloc_etherdev; 2292 2293 SET_NETDEV_DEV(netdev, &pdev->dev); 2294 2295 pci_set_drvdata(pdev, netdev); 2296 adapter = netdev_priv(netdev); 2297 adapter->netdev = netdev; 2298 adapter->pdev = pdev; 2299 hw = &adapter->hw; 2300 hw->back = adapter; 2301 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE); 2302 2303 err = -EIO; 2304 hw->hw_addr = pci_iomap(pdev, 0, 0); 2305 if (!hw->hw_addr) 2306 goto err_ioremap; 2307 2308 netdev->netdev_ops = &igb_netdev_ops; 2309 igb_set_ethtool_ops(netdev); 2310 netdev->watchdog_timeo = 5 * HZ; 2311 2312 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1); 2313 2314 netdev->mem_start = pci_resource_start(pdev, 0); 2315 netdev->mem_end = pci_resource_end(pdev, 0); 2316 2317 /* PCI config space info */ 2318 hw->vendor_id = pdev->vendor; 2319 hw->device_id = pdev->device; 2320 hw->revision_id = pdev->revision; 2321 hw->subsystem_vendor_id = pdev->subsystem_vendor; 2322 hw->subsystem_device_id = pdev->subsystem_device; 2323 2324 /* Copy the default MAC, PHY and NVM function pointers */ 2325 memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops)); 2326 memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops)); 2327 memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops)); 2328 /* Initialize skew-specific constants */ 2329 err = ei->get_invariants(hw); 2330 if (err) 2331 goto err_sw_init; 2332 2333 /* setup the private structure */ 2334 err = igb_sw_init(adapter); 2335 if (err) 2336 goto err_sw_init; 2337 2338 igb_get_bus_info_pcie(hw); 2339 2340 hw->phy.autoneg_wait_to_complete = false; 2341 2342 /* Copper options */ 2343 if (hw->phy.media_type == e1000_media_type_copper) { 2344 hw->phy.mdix = AUTO_ALL_MODES; 2345 hw->phy.disable_polarity_correction = false; 2346 hw->phy.ms_type = e1000_ms_hw_default; 2347 } 2348 2349 if (igb_check_reset_block(hw)) 2350 dev_info(&pdev->dev, 2351 "PHY reset is blocked due to SOL/IDER session.\n"); 2352 2353 /* features is initialized to 0 in allocation, it might have bits 2354 * set by igb_sw_init so we should use an or instead of an 2355 * assignment. 2356 */ 2357 netdev->features |= NETIF_F_SG | 2358 NETIF_F_IP_CSUM | 2359 NETIF_F_IPV6_CSUM | 2360 NETIF_F_TSO | 2361 NETIF_F_TSO6 | 2362 NETIF_F_RXHASH | 2363 NETIF_F_RXCSUM | 2364 NETIF_F_HW_VLAN_CTAG_RX | 2365 NETIF_F_HW_VLAN_CTAG_TX; 2366 2367 /* copy netdev features into list of user selectable features */ 2368 netdev->hw_features |= netdev->features; 2369 netdev->hw_features |= NETIF_F_RXALL; 2370 2371 /* set this bit last since it cannot be part of hw_features */ 2372 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2373 2374 netdev->vlan_features |= NETIF_F_TSO | 2375 NETIF_F_TSO6 | 2376 NETIF_F_IP_CSUM | 2377 NETIF_F_IPV6_CSUM | 2378 NETIF_F_SG; 2379 2380 netdev->priv_flags |= IFF_SUPP_NOFCS; 2381 2382 if (pci_using_dac) { 2383 netdev->features |= NETIF_F_HIGHDMA; 2384 netdev->vlan_features |= NETIF_F_HIGHDMA; 2385 } 2386 2387 if (hw->mac.type >= e1000_82576) { 2388 netdev->hw_features |= NETIF_F_SCTP_CSUM; 2389 netdev->features |= NETIF_F_SCTP_CSUM; 2390 } 2391 2392 netdev->priv_flags |= IFF_UNICAST_FLT; 2393 2394 adapter->en_mng_pt = igb_enable_mng_pass_thru(hw); 2395 2396 /* before reading the NVM, reset the controller to put the device in a 2397 * known good starting state 2398 */ 2399 hw->mac.ops.reset_hw(hw); 2400 2401 /* make sure the NVM is good , i211/i210 parts can have special NVM 2402 * that doesn't contain a checksum 2403 */ 2404 switch (hw->mac.type) { 2405 case e1000_i210: 2406 case e1000_i211: 2407 if (igb_get_flash_presence_i210(hw)) { 2408 if (hw->nvm.ops.validate(hw) < 0) { 2409 dev_err(&pdev->dev, 2410 "The NVM Checksum Is Not Valid\n"); 2411 err = -EIO; 2412 goto err_eeprom; 2413 } 2414 } 2415 break; 2416 default: 2417 if (hw->nvm.ops.validate(hw) < 0) { 2418 dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n"); 2419 err = -EIO; 2420 goto err_eeprom; 2421 } 2422 break; 2423 } 2424 2425 /* copy the MAC address out of the NVM */ 2426 if (hw->mac.ops.read_mac_addr(hw)) 2427 dev_err(&pdev->dev, "NVM Read Error\n"); 2428 2429 memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len); 2430 2431 if (!is_valid_ether_addr(netdev->dev_addr)) { 2432 dev_err(&pdev->dev, "Invalid MAC Address\n"); 2433 err = -EIO; 2434 goto err_eeprom; 2435 } 2436 2437 /* get firmware version for ethtool -i */ 2438 igb_set_fw_version(adapter); 2439 2440 setup_timer(&adapter->watchdog_timer, igb_watchdog, 2441 (unsigned long) adapter); 2442 setup_timer(&adapter->phy_info_timer, igb_update_phy_info, 2443 (unsigned long) adapter); 2444 2445 INIT_WORK(&adapter->reset_task, igb_reset_task); 2446 INIT_WORK(&adapter->watchdog_task, igb_watchdog_task); 2447 2448 /* Initialize link properties that are user-changeable */ 2449 adapter->fc_autoneg = true; 2450 hw->mac.autoneg = true; 2451 hw->phy.autoneg_advertised = 0x2f; 2452 2453 hw->fc.requested_mode = e1000_fc_default; 2454 hw->fc.current_mode = e1000_fc_default; 2455 2456 igb_validate_mdi_setting(hw); 2457 2458 /* By default, support wake on port A */ 2459 if (hw->bus.func == 0) 2460 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2461 2462 /* Check the NVM for wake support on non-port A ports */ 2463 if (hw->mac.type >= e1000_82580) 2464 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A + 2465 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1, 2466 &eeprom_data); 2467 else if (hw->bus.func == 1) 2468 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data); 2469 2470 if (eeprom_data & IGB_EEPROM_APME) 2471 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2472 2473 /* now that we have the eeprom settings, apply the special cases where 2474 * the eeprom may be wrong or the board simply won't support wake on 2475 * lan on a particular port 2476 */ 2477 switch (pdev->device) { 2478 case E1000_DEV_ID_82575GB_QUAD_COPPER: 2479 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2480 break; 2481 case E1000_DEV_ID_82575EB_FIBER_SERDES: 2482 case E1000_DEV_ID_82576_FIBER: 2483 case E1000_DEV_ID_82576_SERDES: 2484 /* Wake events only supported on port A for dual fiber 2485 * regardless of eeprom setting 2486 */ 2487 if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1) 2488 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2489 break; 2490 case E1000_DEV_ID_82576_QUAD_COPPER: 2491 case E1000_DEV_ID_82576_QUAD_COPPER_ET2: 2492 /* if quad port adapter, disable WoL on all but port A */ 2493 if (global_quad_port_a != 0) 2494 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2495 else 2496 adapter->flags |= IGB_FLAG_QUAD_PORT_A; 2497 /* Reset for multiple quad port adapters */ 2498 if (++global_quad_port_a == 4) 2499 global_quad_port_a = 0; 2500 break; 2501 default: 2502 /* If the device can't wake, don't set software support */ 2503 if (!device_can_wakeup(&adapter->pdev->dev)) 2504 adapter->flags &= ~IGB_FLAG_WOL_SUPPORTED; 2505 } 2506 2507 /* initialize the wol settings based on the eeprom settings */ 2508 if (adapter->flags & IGB_FLAG_WOL_SUPPORTED) 2509 adapter->wol |= E1000_WUFC_MAG; 2510 2511 /* Some vendors want WoL disabled by default, but still supported */ 2512 if ((hw->mac.type == e1000_i350) && 2513 (pdev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 2514 adapter->flags |= IGB_FLAG_WOL_SUPPORTED; 2515 adapter->wol = 0; 2516 } 2517 2518 device_set_wakeup_enable(&adapter->pdev->dev, 2519 adapter->flags & IGB_FLAG_WOL_SUPPORTED); 2520 2521 /* reset the hardware with the new settings */ 2522 igb_reset(adapter); 2523 2524 /* Init the I2C interface */ 2525 err = igb_init_i2c(adapter); 2526 if (err) { 2527 dev_err(&pdev->dev, "failed to init i2c interface\n"); 2528 goto err_eeprom; 2529 } 2530 2531 /* let the f/w know that the h/w is now under the control of the 2532 * driver. */ 2533 igb_get_hw_control(adapter); 2534 2535 strcpy(netdev->name, "eth%d"); 2536 err = register_netdev(netdev); 2537 if (err) 2538 goto err_register; 2539 2540 /* carrier off reporting is important to ethtool even BEFORE open */ 2541 netif_carrier_off(netdev); 2542 2543#ifdef CONFIG_IGB_DCA 2544 if (dca_add_requester(&pdev->dev) == 0) { 2545 adapter->flags |= IGB_FLAG_DCA_ENABLED; 2546 dev_info(&pdev->dev, "DCA enabled\n"); 2547 igb_setup_dca(adapter); 2548 } 2549 2550#endif 2551#ifdef CONFIG_IGB_HWMON 2552 /* Initialize the thermal sensor on i350 devices. */ 2553 if (hw->mac.type == e1000_i350 && hw->bus.func == 0) { 2554 u16 ets_word; 2555 2556 /* Read the NVM to determine if this i350 device supports an 2557 * external thermal sensor. 2558 */ 2559 hw->nvm.ops.read(hw, NVM_ETS_CFG, 1, &ets_word); 2560 if (ets_word != 0x0000 && ets_word != 0xFFFF) 2561 adapter->ets = true; 2562 else 2563 adapter->ets = false; 2564 if (igb_sysfs_init(adapter)) 2565 dev_err(&pdev->dev, 2566 "failed to allocate sysfs resources\n"); 2567 } else { 2568 adapter->ets = false; 2569 } 2570#endif 2571 /* Check if Media Autosense is enabled */ 2572 adapter->ei = *ei; 2573 if (hw->dev_spec._82575.mas_capable) 2574 igb_init_mas(adapter); 2575 2576 /* do hw tstamp init after resetting */ 2577 igb_ptp_init(adapter); 2578 2579 dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n"); 2580 /* print bus type/speed/width info, not applicable to i354 */ 2581 if (hw->mac.type != e1000_i354) { 2582 dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n", 2583 netdev->name, 2584 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" : 2585 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" : 2586 "unknown"), 2587 ((hw->bus.width == e1000_bus_width_pcie_x4) ? 2588 "Width x4" : 2589 (hw->bus.width == e1000_bus_width_pcie_x2) ? 2590 "Width x2" : 2591 (hw->bus.width == e1000_bus_width_pcie_x1) ? 2592 "Width x1" : "unknown"), netdev->dev_addr); 2593 } 2594 2595 if ((hw->mac.type >= e1000_i210 || 2596 igb_get_flash_presence_i210(hw))) { 2597 ret_val = igb_read_part_string(hw, part_str, 2598 E1000_PBANUM_LENGTH); 2599 } else { 2600 ret_val = -E1000_ERR_INVM_VALUE_NOT_FOUND; 2601 } 2602 2603 if (ret_val) 2604 strcpy(part_str, "Unknown"); 2605 dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str); 2606 dev_info(&pdev->dev, 2607 "Using %s interrupts. %d rx queue(s), %d tx queue(s)\n", 2608 (adapter->flags & IGB_FLAG_HAS_MSIX) ? "MSI-X" : 2609 (adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy", 2610 adapter->num_rx_queues, adapter->num_tx_queues); 2611 if (hw->phy.media_type == e1000_media_type_copper) { 2612 switch (hw->mac.type) { 2613 case e1000_i350: 2614 case e1000_i210: 2615 case e1000_i211: 2616 /* Enable EEE for internal copper PHY devices */ 2617 err = igb_set_eee_i350(hw); 2618 if ((!err) && 2619 (!hw->dev_spec._82575.eee_disable)) { 2620 adapter->eee_advert = 2621 MDIO_EEE_100TX | MDIO_EEE_1000T; 2622 adapter->flags |= IGB_FLAG_EEE; 2623 } 2624 break; 2625 case e1000_i354: 2626 if ((rd32(E1000_CTRL_EXT) & 2627 E1000_CTRL_EXT_LINK_MODE_SGMII)) { 2628 err = igb_set_eee_i354(hw); 2629 if ((!err) && 2630 (!hw->dev_spec._82575.eee_disable)) { 2631 adapter->eee_advert = 2632 MDIO_EEE_100TX | MDIO_EEE_1000T; 2633 adapter->flags |= IGB_FLAG_EEE; 2634 } 2635 } 2636 break; 2637 default: 2638 break; 2639 } 2640 } 2641 pm_runtime_put_noidle(&pdev->dev); 2642 return 0; 2643 2644err_register: 2645 igb_release_hw_control(adapter); 2646 memset(&adapter->i2c_adap, 0, sizeof(adapter->i2c_adap)); 2647err_eeprom: 2648 if (!igb_check_reset_block(hw)) 2649 igb_reset_phy(hw); 2650 2651 if (hw->flash_address) 2652 iounmap(hw->flash_address); 2653err_sw_init: 2654 igb_clear_interrupt_scheme(adapter); 2655 iounmap(hw->hw_addr); 2656err_ioremap: 2657 free_netdev(netdev); 2658err_alloc_etherdev: 2659 pci_release_selected_regions(pdev, 2660 pci_select_bars(pdev, IORESOURCE_MEM)); 2661err_pci_reg: 2662err_dma: 2663 pci_disable_device(pdev); 2664 return err; 2665} 2666 2667#ifdef CONFIG_PCI_IOV 2668static int igb_disable_sriov(struct pci_dev *pdev) 2669{ 2670 struct net_device *netdev = pci_get_drvdata(pdev); 2671 struct igb_adapter *adapter = netdev_priv(netdev); 2672 struct e1000_hw *hw = &adapter->hw; 2673 2674 /* reclaim resources allocated to VFs */ 2675 if (adapter->vf_data) { 2676 /* disable iov and allow time for transactions to clear */ 2677 if (pci_vfs_assigned(pdev)) { 2678 dev_warn(&pdev->dev, 2679 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n"); 2680 return -EPERM; 2681 } else { 2682 pci_disable_sriov(pdev); 2683 msleep(500); 2684 } 2685 2686 kfree(adapter->vf_data); 2687 adapter->vf_data = NULL; 2688 adapter->vfs_allocated_count = 0; 2689 wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ); 2690 wrfl(); 2691 msleep(100); 2692 dev_info(&pdev->dev, "IOV Disabled\n"); 2693 2694 /* Re-enable DMA Coalescing flag since IOV is turned off */ 2695 adapter->flags |= IGB_FLAG_DMAC; 2696 } 2697 2698 return 0; 2699} 2700 2701static int igb_enable_sriov(struct pci_dev *pdev, int num_vfs) 2702{ 2703 struct net_device *netdev = pci_get_drvdata(pdev); 2704 struct igb_adapter *adapter = netdev_priv(netdev); 2705 int old_vfs = pci_num_vf(pdev); 2706 int err = 0; 2707 int i; 2708 2709 if (!(adapter->flags & IGB_FLAG_HAS_MSIX) || num_vfs > 7) { 2710 err = -EPERM; 2711 goto out; 2712 } 2713 if (!num_vfs) 2714 goto out; 2715 2716 if (old_vfs) { 2717 dev_info(&pdev->dev, "%d pre-allocated VFs found - override max_vfs setting of %d\n", 2718 old_vfs, max_vfs); 2719 adapter->vfs_allocated_count = old_vfs; 2720 } else 2721 adapter->vfs_allocated_count = num_vfs; 2722 2723 adapter->vf_data = kcalloc(adapter->vfs_allocated_count, 2724 sizeof(struct vf_data_storage), GFP_KERNEL); 2725 2726 /* if allocation failed then we do not support SR-IOV */ 2727 if (!adapter->vf_data) { 2728 adapter->vfs_allocated_count = 0; 2729 dev_err(&pdev->dev, 2730 "Unable to allocate memory for VF Data Storage\n"); 2731 err = -ENOMEM; 2732 goto out; 2733 } 2734 2735 /* only call pci_enable_sriov() if no VFs are allocated already */ 2736 if (!old_vfs) { 2737 err = pci_enable_sriov(pdev, adapter->vfs_allocated_count); 2738 if (err) 2739 goto err_out; 2740 } 2741 dev_info(&pdev->dev, "%d VFs allocated\n", 2742 adapter->vfs_allocated_count); 2743 for (i = 0; i < adapter->vfs_allocated_count; i++) 2744 igb_vf_configure(adapter, i); 2745 2746 /* DMA Coalescing is not supported in IOV mode. */ 2747 adapter->flags &= ~IGB_FLAG_DMAC; 2748 goto out; 2749 2750err_out: 2751 kfree(adapter->vf_data); 2752 adapter->vf_data = NULL; 2753 adapter->vfs_allocated_count = 0; 2754out: 2755 return err; 2756} 2757 2758#endif 2759/** 2760 * igb_remove_i2c - Cleanup I2C interface 2761 * @adapter: pointer to adapter structure 2762 **/ 2763static void igb_remove_i2c(struct igb_adapter *adapter) 2764{ 2765 /* free the adapter bus structure */ 2766 i2c_del_adapter(&adapter->i2c_adap); 2767} 2768 2769/** 2770 * igb_remove - Device Removal Routine 2771 * @pdev: PCI device information struct 2772 * 2773 * igb_remove is called by the PCI subsystem to alert the driver 2774 * that it should release a PCI device. The could be caused by a 2775 * Hot-Plug event, or because the driver is going to be removed from 2776 * memory. 2777 **/ 2778static void igb_remove(struct pci_dev *pdev) 2779{ 2780 struct net_device *netdev = pci_get_drvdata(pdev); 2781 struct igb_adapter *adapter = netdev_priv(netdev); 2782 struct e1000_hw *hw = &adapter->hw; 2783 2784 pm_runtime_get_noresume(&pdev->dev); 2785#ifdef CONFIG_IGB_HWMON 2786 igb_sysfs_exit(adapter); 2787#endif 2788 igb_remove_i2c(adapter); 2789 igb_ptp_stop(adapter); 2790 /* The watchdog timer may be rescheduled, so explicitly 2791 * disable watchdog from being rescheduled. 2792 */ 2793 set_bit(__IGB_DOWN, &adapter->state); 2794 del_timer_sync(&adapter->watchdog_timer); 2795 del_timer_sync(&adapter->phy_info_timer); 2796 2797 cancel_work_sync(&adapter->reset_task); 2798 cancel_work_sync(&adapter->watchdog_task); 2799 2800#ifdef CONFIG_IGB_DCA 2801 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 2802 dev_info(&pdev->dev, "DCA disabled\n"); 2803 dca_remove_requester(&pdev->dev); 2804 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 2805 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 2806 } 2807#endif 2808 2809 /* Release control of h/w to f/w. If f/w is AMT enabled, this 2810 * would have already happened in close and is redundant. 2811 */ 2812 igb_release_hw_control(adapter); 2813 2814 unregister_netdev(netdev); 2815 2816 igb_clear_interrupt_scheme(adapter); 2817 2818#ifdef CONFIG_PCI_IOV 2819 igb_disable_sriov(pdev); 2820#endif 2821 2822 iounmap(hw->hw_addr); 2823 if (hw->flash_address) 2824 iounmap(hw->flash_address); 2825 pci_release_selected_regions(pdev, 2826 pci_select_bars(pdev, IORESOURCE_MEM)); 2827 2828 kfree(adapter->shadow_vfta); 2829 free_netdev(netdev); 2830 2831 pci_disable_pcie_error_reporting(pdev); 2832 2833 pci_disable_device(pdev); 2834} 2835 2836/** 2837 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space 2838 * @adapter: board private structure to initialize 2839 * 2840 * This function initializes the vf specific data storage and then attempts to 2841 * allocate the VFs. The reason for ordering it this way is because it is much 2842 * mor expensive time wise to disable SR-IOV than it is to allocate and free 2843 * the memory for the VFs. 2844 **/ 2845static void igb_probe_vfs(struct igb_adapter *adapter) 2846{ 2847#ifdef CONFIG_PCI_IOV 2848 struct pci_dev *pdev = adapter->pdev; 2849 struct e1000_hw *hw = &adapter->hw; 2850 2851 /* Virtualization features not supported on i210 family. */ 2852 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) 2853 return; 2854 2855 pci_sriov_set_totalvfs(pdev, 7); 2856 igb_pci_enable_sriov(pdev, max_vfs); 2857 2858#endif /* CONFIG_PCI_IOV */ 2859} 2860 2861static void igb_init_queue_configuration(struct igb_adapter *adapter) 2862{ 2863 struct e1000_hw *hw = &adapter->hw; 2864 u32 max_rss_queues; 2865 2866 /* Determine the maximum number of RSS queues supported. */ 2867 switch (hw->mac.type) { 2868 case e1000_i211: 2869 max_rss_queues = IGB_MAX_RX_QUEUES_I211; 2870 break; 2871 case e1000_82575: 2872 case e1000_i210: 2873 max_rss_queues = IGB_MAX_RX_QUEUES_82575; 2874 break; 2875 case e1000_i350: 2876 /* I350 cannot do RSS and SR-IOV at the same time */ 2877 if (!!adapter->vfs_allocated_count) { 2878 max_rss_queues = 1; 2879 break; 2880 } 2881 /* fall through */ 2882 case e1000_82576: 2883 if (!!adapter->vfs_allocated_count) { 2884 max_rss_queues = 2; 2885 break; 2886 } 2887 /* fall through */ 2888 case e1000_82580: 2889 case e1000_i354: 2890 default: 2891 max_rss_queues = IGB_MAX_RX_QUEUES; 2892 break; 2893 } 2894 2895 adapter->rss_queues = min_t(u32, max_rss_queues, num_online_cpus()); 2896 2897 /* Determine if we need to pair queues. */ 2898 switch (hw->mac.type) { 2899 case e1000_82575: 2900 case e1000_i211: 2901 /* Device supports enough interrupts without queue pairing. */ 2902 break; 2903 case e1000_82576: 2904 /* If VFs are going to be allocated with RSS queues then we 2905 * should pair the queues in order to conserve interrupts due 2906 * to limited supply. 2907 */ 2908 if ((adapter->rss_queues > 1) && 2909 (adapter->vfs_allocated_count > 6)) 2910 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2911 /* fall through */ 2912 case e1000_82580: 2913 case e1000_i350: 2914 case e1000_i354: 2915 case e1000_i210: 2916 default: 2917 /* If rss_queues > half of max_rss_queues, pair the queues in 2918 * order to conserve interrupts due to limited supply. 2919 */ 2920 if (adapter->rss_queues > (max_rss_queues / 2)) 2921 adapter->flags |= IGB_FLAG_QUEUE_PAIRS; 2922 break; 2923 } 2924} 2925 2926/** 2927 * igb_sw_init - Initialize general software structures (struct igb_adapter) 2928 * @adapter: board private structure to initialize 2929 * 2930 * igb_sw_init initializes the Adapter private data structure. 2931 * Fields are initialized based on PCI device information and 2932 * OS network device settings (MTU size). 2933 **/ 2934static int igb_sw_init(struct igb_adapter *adapter) 2935{ 2936 struct e1000_hw *hw = &adapter->hw; 2937 struct net_device *netdev = adapter->netdev; 2938 struct pci_dev *pdev = adapter->pdev; 2939 2940 pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word); 2941 2942 /* set default ring sizes */ 2943 adapter->tx_ring_count = IGB_DEFAULT_TXD; 2944 adapter->rx_ring_count = IGB_DEFAULT_RXD; 2945 2946 /* set default ITR values */ 2947 adapter->rx_itr_setting = IGB_DEFAULT_ITR; 2948 adapter->tx_itr_setting = IGB_DEFAULT_ITR; 2949 2950 /* set default work limits */ 2951 adapter->tx_work_limit = IGB_DEFAULT_TX_WORK; 2952 2953 adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + 2954 VLAN_HLEN; 2955 adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 2956 2957 spin_lock_init(&adapter->stats64_lock); 2958#ifdef CONFIG_PCI_IOV 2959 switch (hw->mac.type) { 2960 case e1000_82576: 2961 case e1000_i350: 2962 if (max_vfs > 7) { 2963 dev_warn(&pdev->dev, 2964 "Maximum of 7 VFs per PF, using max\n"); 2965 max_vfs = adapter->vfs_allocated_count = 7; 2966 } else 2967 adapter->vfs_allocated_count = max_vfs; 2968 if (adapter->vfs_allocated_count) 2969 dev_warn(&pdev->dev, 2970 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n"); 2971 break; 2972 default: 2973 break; 2974 } 2975#endif /* CONFIG_PCI_IOV */ 2976 2977 igb_init_queue_configuration(adapter); 2978 2979 /* Setup and initialize a copy of the hw vlan table array */ 2980 adapter->shadow_vfta = kcalloc(E1000_VLAN_FILTER_TBL_SIZE, sizeof(u32), 2981 GFP_ATOMIC); 2982 2983 /* This call may decrease the number of queues */ 2984 if (igb_init_interrupt_scheme(adapter, true)) { 2985 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 2986 return -ENOMEM; 2987 } 2988 2989 igb_probe_vfs(adapter); 2990 2991 /* Explicitly disable IRQ since the NIC can be in any state. */ 2992 igb_irq_disable(adapter); 2993 2994 if (hw->mac.type >= e1000_i350) 2995 adapter->flags &= ~IGB_FLAG_DMAC; 2996 2997 set_bit(__IGB_DOWN, &adapter->state); 2998 return 0; 2999} 3000 3001/** 3002 * igb_open - Called when a network interface is made active 3003 * @netdev: network interface device structure 3004 * 3005 * Returns 0 on success, negative value on failure 3006 * 3007 * The open entry point is called when a network interface is made 3008 * active by the system (IFF_UP). At this point all resources needed 3009 * for transmit and receive operations are allocated, the interrupt 3010 * handler is registered with the OS, the watchdog timer is started, 3011 * and the stack is notified that the interface is ready. 3012 **/ 3013static int __igb_open(struct net_device *netdev, bool resuming) 3014{ 3015 struct igb_adapter *adapter = netdev_priv(netdev); 3016 struct e1000_hw *hw = &adapter->hw; 3017 struct pci_dev *pdev = adapter->pdev; 3018 int err; 3019 int i; 3020 3021 /* disallow open during test */ 3022 if (test_bit(__IGB_TESTING, &adapter->state)) { 3023 WARN_ON(resuming); 3024 return -EBUSY; 3025 } 3026 3027 if (!resuming) 3028 pm_runtime_get_sync(&pdev->dev); 3029 3030 netif_carrier_off(netdev); 3031 3032 /* allocate transmit descriptors */ 3033 err = igb_setup_all_tx_resources(adapter); 3034 if (err) 3035 goto err_setup_tx; 3036 3037 /* allocate receive descriptors */ 3038 err = igb_setup_all_rx_resources(adapter); 3039 if (err) 3040 goto err_setup_rx; 3041 3042 igb_power_up_link(adapter); 3043 3044 /* before we allocate an interrupt, we must be ready to handle it. 3045 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt 3046 * as soon as we call pci_request_irq, so we have to setup our 3047 * clean_rx handler before we do so. 3048 */ 3049 igb_configure(adapter); 3050 3051 err = igb_request_irq(adapter); 3052 if (err) 3053 goto err_req_irq; 3054 3055 /* Notify the stack of the actual queue counts. */ 3056 err = netif_set_real_num_tx_queues(adapter->netdev, 3057 adapter->num_tx_queues); 3058 if (err) 3059 goto err_set_queues; 3060 3061 err = netif_set_real_num_rx_queues(adapter->netdev, 3062 adapter->num_rx_queues); 3063 if (err) 3064 goto err_set_queues; 3065 3066 /* From here on the code is the same as igb_up() */ 3067 clear_bit(__IGB_DOWN, &adapter->state); 3068 3069 for (i = 0; i < adapter->num_q_vectors; i++) 3070 napi_enable(&(adapter->q_vector[i]->napi)); 3071 3072 /* Clear any pending interrupts. */ 3073 rd32(E1000_ICR); 3074 3075 igb_irq_enable(adapter); 3076 3077 /* notify VFs that reset has been completed */ 3078 if (adapter->vfs_allocated_count) { 3079 u32 reg_data = rd32(E1000_CTRL_EXT); 3080 reg_data |= E1000_CTRL_EXT_PFRSTD; 3081 wr32(E1000_CTRL_EXT, reg_data); 3082 } 3083 3084 netif_tx_start_all_queues(netdev); 3085 3086 if (!resuming) 3087 pm_runtime_put(&pdev->dev); 3088 3089 /* start the watchdog. */ 3090 hw->mac.get_link_status = 1; 3091 schedule_work(&adapter->watchdog_task); 3092 3093 return 0; 3094 3095err_set_queues: 3096 igb_free_irq(adapter); 3097err_req_irq: 3098 igb_release_hw_control(adapter); 3099 igb_power_down_link(adapter); 3100 igb_free_all_rx_resources(adapter); 3101err_setup_rx: 3102 igb_free_all_tx_resources(adapter); 3103err_setup_tx: 3104 igb_reset(adapter); 3105 if (!resuming) 3106 pm_runtime_put(&pdev->dev); 3107 3108 return err; 3109} 3110 3111static int igb_open(struct net_device *netdev) 3112{ 3113 return __igb_open(netdev, false); 3114} 3115 3116/** 3117 * igb_close - Disables a network interface 3118 * @netdev: network interface device structure 3119 * 3120 * Returns 0, this is not allowed to fail 3121 * 3122 * The close entry point is called when an interface is de-activated 3123 * by the OS. The hardware is still under the driver's control, but 3124 * needs to be disabled. A global MAC reset is issued to stop the 3125 * hardware, and all transmit and receive resources are freed. 3126 **/ 3127static int __igb_close(struct net_device *netdev, bool suspending) 3128{ 3129 struct igb_adapter *adapter = netdev_priv(netdev); 3130 struct pci_dev *pdev = adapter->pdev; 3131 3132 WARN_ON(test_bit(__IGB_RESETTING, &adapter->state)); 3133 3134 if (!suspending) 3135 pm_runtime_get_sync(&pdev->dev); 3136 3137 igb_down(adapter); 3138 igb_free_irq(adapter); 3139 3140 igb_free_all_tx_resources(adapter); 3141 igb_free_all_rx_resources(adapter); 3142 3143 if (!suspending) 3144 pm_runtime_put_sync(&pdev->dev); 3145 return 0; 3146} 3147 3148static int igb_close(struct net_device *netdev) 3149{ 3150 return __igb_close(netdev, false); 3151} 3152 3153/** 3154 * igb_setup_tx_resources - allocate Tx resources (Descriptors) 3155 * @tx_ring: tx descriptor ring (for a specific queue) to setup 3156 * 3157 * Return 0 on success, negative on failure 3158 **/ 3159int igb_setup_tx_resources(struct igb_ring *tx_ring) 3160{ 3161 struct device *dev = tx_ring->dev; 3162 int size; 3163 3164 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3165 3166 tx_ring->tx_buffer_info = vzalloc(size); 3167 if (!tx_ring->tx_buffer_info) 3168 goto err; 3169 3170 /* round up to nearest 4K */ 3171 tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc); 3172 tx_ring->size = ALIGN(tx_ring->size, 4096); 3173 3174 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size, 3175 &tx_ring->dma, GFP_KERNEL); 3176 if (!tx_ring->desc) 3177 goto err; 3178 3179 tx_ring->next_to_use = 0; 3180 tx_ring->next_to_clean = 0; 3181 3182 return 0; 3183 3184err: 3185 vfree(tx_ring->tx_buffer_info); 3186 tx_ring->tx_buffer_info = NULL; 3187 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n"); 3188 return -ENOMEM; 3189} 3190 3191/** 3192 * igb_setup_all_tx_resources - wrapper to allocate Tx resources 3193 * (Descriptors) for all queues 3194 * @adapter: board private structure 3195 * 3196 * Return 0 on success, negative on failure 3197 **/ 3198static int igb_setup_all_tx_resources(struct igb_adapter *adapter) 3199{ 3200 struct pci_dev *pdev = adapter->pdev; 3201 int i, err = 0; 3202 3203 for (i = 0; i < adapter->num_tx_queues; i++) { 3204 err = igb_setup_tx_resources(adapter->tx_ring[i]); 3205 if (err) { 3206 dev_err(&pdev->dev, 3207 "Allocation for Tx Queue %u failed\n", i); 3208 for (i--; i >= 0; i--) 3209 igb_free_tx_resources(adapter->tx_ring[i]); 3210 break; 3211 } 3212 } 3213 3214 return err; 3215} 3216 3217/** 3218 * igb_setup_tctl - configure the transmit control registers 3219 * @adapter: Board private structure 3220 **/ 3221void igb_setup_tctl(struct igb_adapter *adapter) 3222{ 3223 struct e1000_hw *hw = &adapter->hw; 3224 u32 tctl; 3225 3226 /* disable queue 0 which is enabled by default on 82575 and 82576 */ 3227 wr32(E1000_TXDCTL(0), 0); 3228 3229 /* Program the Transmit Control Register */ 3230 tctl = rd32(E1000_TCTL); 3231 tctl &= ~E1000_TCTL_CT; 3232 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | 3233 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT); 3234 3235 igb_config_collision_dist(hw); 3236 3237 /* Enable transmits */ 3238 tctl |= E1000_TCTL_EN; 3239 3240 wr32(E1000_TCTL, tctl); 3241} 3242 3243/** 3244 * igb_configure_tx_ring - Configure transmit ring after Reset 3245 * @adapter: board private structure 3246 * @ring: tx ring to configure 3247 * 3248 * Configure a transmit ring after a reset. 3249 **/ 3250void igb_configure_tx_ring(struct igb_adapter *adapter, 3251 struct igb_ring *ring) 3252{ 3253 struct e1000_hw *hw = &adapter->hw; 3254 u32 txdctl = 0; 3255 u64 tdba = ring->dma; 3256 int reg_idx = ring->reg_idx; 3257 3258 /* disable the queue */ 3259 wr32(E1000_TXDCTL(reg_idx), 0); 3260 wrfl(); 3261 mdelay(10); 3262 3263 wr32(E1000_TDLEN(reg_idx), 3264 ring->count * sizeof(union e1000_adv_tx_desc)); 3265 wr32(E1000_TDBAL(reg_idx), 3266 tdba & 0x00000000ffffffffULL); 3267 wr32(E1000_TDBAH(reg_idx), tdba >> 32); 3268 3269 ring->tail = hw->hw_addr + E1000_TDT(reg_idx); 3270 wr32(E1000_TDH(reg_idx), 0); 3271 writel(0, ring->tail); 3272 3273 txdctl |= IGB_TX_PTHRESH; 3274 txdctl |= IGB_TX_HTHRESH << 8; 3275 txdctl |= IGB_TX_WTHRESH << 16; 3276 3277 txdctl |= E1000_TXDCTL_QUEUE_ENABLE; 3278 wr32(E1000_TXDCTL(reg_idx), txdctl); 3279} 3280 3281/** 3282 * igb_configure_tx - Configure transmit Unit after Reset 3283 * @adapter: board private structure 3284 * 3285 * Configure the Tx unit of the MAC after a reset. 3286 **/ 3287static void igb_configure_tx(struct igb_adapter *adapter) 3288{ 3289 int i; 3290 3291 for (i = 0; i < adapter->num_tx_queues; i++) 3292 igb_configure_tx_ring(adapter, adapter->tx_ring[i]); 3293} 3294 3295/** 3296 * igb_setup_rx_resources - allocate Rx resources (Descriptors) 3297 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 3298 * 3299 * Returns 0 on success, negative on failure 3300 **/ 3301int igb_setup_rx_resources(struct igb_ring *rx_ring) 3302{ 3303 struct device *dev = rx_ring->dev; 3304 int size; 3305 3306 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3307 3308 rx_ring->rx_buffer_info = vzalloc(size); 3309 if (!rx_ring->rx_buffer_info) 3310 goto err; 3311 3312 /* Round up to nearest 4K */ 3313 rx_ring->size = rx_ring->count * sizeof(union e1000_adv_rx_desc); 3314 rx_ring->size = ALIGN(rx_ring->size, 4096); 3315 3316 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size, 3317 &rx_ring->dma, GFP_KERNEL); 3318 if (!rx_ring->desc) 3319 goto err; 3320 3321 rx_ring->next_to_alloc = 0; 3322 rx_ring->next_to_clean = 0; 3323 rx_ring->next_to_use = 0; 3324 3325 return 0; 3326 3327err: 3328 vfree(rx_ring->rx_buffer_info); 3329 rx_ring->rx_buffer_info = NULL; 3330 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n"); 3331 return -ENOMEM; 3332} 3333 3334/** 3335 * igb_setup_all_rx_resources - wrapper to allocate Rx resources 3336 * (Descriptors) for all queues 3337 * @adapter: board private structure 3338 * 3339 * Return 0 on success, negative on failure 3340 **/ 3341static int igb_setup_all_rx_resources(struct igb_adapter *adapter) 3342{ 3343 struct pci_dev *pdev = adapter->pdev; 3344 int i, err = 0; 3345 3346 for (i = 0; i < adapter->num_rx_queues; i++) { 3347 err = igb_setup_rx_resources(adapter->rx_ring[i]); 3348 if (err) { 3349 dev_err(&pdev->dev, 3350 "Allocation for Rx Queue %u failed\n", i); 3351 for (i--; i >= 0; i--) 3352 igb_free_rx_resources(adapter->rx_ring[i]); 3353 break; 3354 } 3355 } 3356 3357 return err; 3358} 3359 3360/** 3361 * igb_setup_mrqc - configure the multiple receive queue control registers 3362 * @adapter: Board private structure 3363 **/ 3364static void igb_setup_mrqc(struct igb_adapter *adapter) 3365{ 3366 struct e1000_hw *hw = &adapter->hw; 3367 u32 mrqc, rxcsum; 3368 u32 j, num_rx_queues; 3369 static const u32 rsskey[10] = { 0xDA565A6D, 0xC20E5B25, 0x3D256741, 3370 0xB08FA343, 0xCB2BCAD0, 0xB4307BAE, 3371 0xA32DCB77, 0x0CF23080, 0x3BB7426A, 3372 0xFA01ACBE }; 3373 3374 /* Fill out hash function seeds */ 3375 for (j = 0; j < 10; j++) 3376 wr32(E1000_RSSRK(j), rsskey[j]); 3377 3378 num_rx_queues = adapter->rss_queues; 3379 3380 switch (hw->mac.type) { 3381 case e1000_82576: 3382 /* 82576 supports 2 RSS queues for SR-IOV */ 3383 if (adapter->vfs_allocated_count) 3384 num_rx_queues = 2; 3385 break; 3386 default: 3387 break; 3388 } 3389 3390 if (adapter->rss_indir_tbl_init != num_rx_queues) { 3391 for (j = 0; j < IGB_RETA_SIZE; j++) 3392 adapter->rss_indir_tbl[j] = (j * num_rx_queues) / IGB_RETA_SIZE; 3393 adapter->rss_indir_tbl_init = num_rx_queues; 3394 } 3395 igb_write_rss_indir_tbl(adapter); 3396 3397 /* Disable raw packet checksumming so that RSS hash is placed in 3398 * descriptor on writeback. No need to enable TCP/UDP/IP checksum 3399 * offloads as they are enabled by default 3400 */ 3401 rxcsum = rd32(E1000_RXCSUM); 3402 rxcsum |= E1000_RXCSUM_PCSD; 3403 3404 if (adapter->hw.mac.type >= e1000_82576) 3405 /* Enable Receive Checksum Offload for SCTP */ 3406 rxcsum |= E1000_RXCSUM_CRCOFL; 3407 3408 /* Don't need to set TUOFL or IPOFL, they default to 1 */ 3409 wr32(E1000_RXCSUM, rxcsum); 3410 3411 /* Generate RSS hash based on packet types, TCP/UDP 3412 * port numbers and/or IPv4/v6 src and dst addresses 3413 */ 3414 mrqc = E1000_MRQC_RSS_FIELD_IPV4 | 3415 E1000_MRQC_RSS_FIELD_IPV4_TCP | 3416 E1000_MRQC_RSS_FIELD_IPV6 | 3417 E1000_MRQC_RSS_FIELD_IPV6_TCP | 3418 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX; 3419 3420 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV4_UDP) 3421 mrqc |= E1000_MRQC_RSS_FIELD_IPV4_UDP; 3422 if (adapter->flags & IGB_FLAG_RSS_FIELD_IPV6_UDP) 3423 mrqc |= E1000_MRQC_RSS_FIELD_IPV6_UDP; 3424 3425 /* If VMDq is enabled then we set the appropriate mode for that, else 3426 * we default to RSS so that an RSS hash is calculated per packet even 3427 * if we are only using one queue 3428 */ 3429 if (adapter->vfs_allocated_count) { 3430 if (hw->mac.type > e1000_82575) { 3431 /* Set the default pool for the PF's first queue */ 3432 u32 vtctl = rd32(E1000_VT_CTL); 3433 vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK | 3434 E1000_VT_CTL_DISABLE_DEF_POOL); 3435 vtctl |= adapter->vfs_allocated_count << 3436 E1000_VT_CTL_DEFAULT_POOL_SHIFT; 3437 wr32(E1000_VT_CTL, vtctl); 3438 } 3439 if (adapter->rss_queues > 1) 3440 mrqc |= E1000_MRQC_ENABLE_VMDQ_RSS_2Q; 3441 else 3442 mrqc |= E1000_MRQC_ENABLE_VMDQ; 3443 } else { 3444 if (hw->mac.type != e1000_i211) 3445 mrqc |= E1000_MRQC_ENABLE_RSS_4Q; 3446 } 3447 igb_vmm_control(adapter); 3448 3449 wr32(E1000_MRQC, mrqc); 3450} 3451 3452/** 3453 * igb_setup_rctl - configure the receive control registers 3454 * @adapter: Board private structure 3455 **/ 3456void igb_setup_rctl(struct igb_adapter *adapter) 3457{ 3458 struct e1000_hw *hw = &adapter->hw; 3459 u32 rctl; 3460 3461 rctl = rd32(E1000_RCTL); 3462 3463 rctl &= ~(3 << E1000_RCTL_MO_SHIFT); 3464 rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC); 3465 3466 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF | 3467 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT); 3468 3469 /* enable stripping of CRC. It's unlikely this will break BMC 3470 * redirection as it did with e1000. Newer features require 3471 * that the HW strips the CRC. 3472 */ 3473 rctl |= E1000_RCTL_SECRC; 3474 3475 /* disable store bad packets and clear size bits. */ 3476 rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256); 3477 3478 /* enable LPE to prevent packets larger than max_frame_size */ 3479 rctl |= E1000_RCTL_LPE; 3480 3481 /* disable queue 0 to prevent tail write w/o re-config */ 3482 wr32(E1000_RXDCTL(0), 0); 3483 3484 /* Attention!!! For SR-IOV PF driver operations you must enable 3485 * queue drop for all VF and PF queues to prevent head of line blocking 3486 * if an un-trusted VF does not provide descriptors to hardware. 3487 */ 3488 if (adapter->vfs_allocated_count) { 3489 /* set all queue drop enable bits */ 3490 wr32(E1000_QDE, ALL_QUEUES); 3491 } 3492 3493 /* This is useful for sniffing bad packets. */ 3494 if (adapter->netdev->features & NETIF_F_RXALL) { 3495 /* UPE and MPE will be handled by normal PROMISC logic 3496 * in e1000e_set_rx_mode 3497 */ 3498 rctl |= (E1000_RCTL_SBP | /* Receive bad packets */ 3499 E1000_RCTL_BAM | /* RX All Bcast Pkts */ 3500 E1000_RCTL_PMCF); /* RX All MAC Ctrl Pkts */ 3501 3502 rctl &= ~(E1000_RCTL_VFE | /* Disable VLAN filter */ 3503 E1000_RCTL_DPF | /* Allow filtered pause */ 3504 E1000_RCTL_CFIEN); /* Dis VLAN CFIEN Filter */ 3505 /* Do not mess with E1000_CTRL_VME, it affects transmit as well, 3506 * and that breaks VLANs. 3507 */ 3508 } 3509 3510 wr32(E1000_RCTL, rctl); 3511} 3512 3513static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size, 3514 int vfn) 3515{ 3516 struct e1000_hw *hw = &adapter->hw; 3517 u32 vmolr; 3518 3519 /* if it isn't the PF check to see if VFs are enabled and 3520 * increase the size to support vlan tags 3521 */ 3522 if (vfn < adapter->vfs_allocated_count && 3523 adapter->vf_data[vfn].vlans_enabled) 3524 size += VLAN_TAG_SIZE; 3525 3526 vmolr = rd32(E1000_VMOLR(vfn)); 3527 vmolr &= ~E1000_VMOLR_RLPML_MASK; 3528 vmolr |= size | E1000_VMOLR_LPE; 3529 wr32(E1000_VMOLR(vfn), vmolr); 3530 3531 return 0; 3532} 3533 3534/** 3535 * igb_rlpml_set - set maximum receive packet size 3536 * @adapter: board private structure 3537 * 3538 * Configure maximum receivable packet size. 3539 **/ 3540static void igb_rlpml_set(struct igb_adapter *adapter) 3541{ 3542 u32 max_frame_size = adapter->max_frame_size; 3543 struct e1000_hw *hw = &adapter->hw; 3544 u16 pf_id = adapter->vfs_allocated_count; 3545 3546 if (pf_id) { 3547 igb_set_vf_rlpml(adapter, max_frame_size, pf_id); 3548 /* If we're in VMDQ or SR-IOV mode, then set global RLPML 3549 * to our max jumbo frame size, in case we need to enable 3550 * jumbo frames on one of the rings later. 3551 * This will not pass over-length frames into the default 3552 * queue because it's gated by the VMOLR.RLPML. 3553 */ 3554 max_frame_size = MAX_JUMBO_FRAME_SIZE; 3555 } 3556 3557 wr32(E1000_RLPML, max_frame_size); 3558} 3559 3560static inline void igb_set_vmolr(struct igb_adapter *adapter, 3561 int vfn, bool aupe) 3562{ 3563 struct e1000_hw *hw = &adapter->hw; 3564 u32 vmolr; 3565 3566 /* This register exists only on 82576 and newer so if we are older then 3567 * we should exit and do nothing 3568 */ 3569 if (hw->mac.type < e1000_82576) 3570 return; 3571 3572 vmolr = rd32(E1000_VMOLR(vfn)); 3573 vmolr |= E1000_VMOLR_STRVLAN; /* Strip vlan tags */ 3574 if (hw->mac.type == e1000_i350) { 3575 u32 dvmolr; 3576 3577 dvmolr = rd32(E1000_DVMOLR(vfn)); 3578 dvmolr |= E1000_DVMOLR_STRVLAN; 3579 wr32(E1000_DVMOLR(vfn), dvmolr); 3580 } 3581 if (aupe) 3582 vmolr |= E1000_VMOLR_AUPE; /* Accept untagged packets */ 3583 else 3584 vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */ 3585 3586 /* clear all bits that might not be set */ 3587 vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE); 3588 3589 if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count) 3590 vmolr |= E1000_VMOLR_RSSE; /* enable RSS */ 3591 /* for VMDq only allow the VFs and pool 0 to accept broadcast and 3592 * multicast packets 3593 */ 3594 if (vfn <= adapter->vfs_allocated_count) 3595 vmolr |= E1000_VMOLR_BAM; /* Accept broadcast */ 3596 3597 wr32(E1000_VMOLR(vfn), vmolr); 3598} 3599 3600/** 3601 * igb_configure_rx_ring - Configure a receive ring after Reset 3602 * @adapter: board private structure 3603 * @ring: receive ring to be configured 3604 * 3605 * Configure the Rx unit of the MAC after a reset. 3606 **/ 3607void igb_configure_rx_ring(struct igb_adapter *adapter, 3608 struct igb_ring *ring) 3609{ 3610 struct e1000_hw *hw = &adapter->hw; 3611 u64 rdba = ring->dma; 3612 int reg_idx = ring->reg_idx; 3613 u32 srrctl = 0, rxdctl = 0; 3614 3615 /* disable the queue */ 3616 wr32(E1000_RXDCTL(reg_idx), 0); 3617 3618 /* Set DMA base address registers */ 3619 wr32(E1000_RDBAL(reg_idx), 3620 rdba & 0x00000000ffffffffULL); 3621 wr32(E1000_RDBAH(reg_idx), rdba >> 32); 3622 wr32(E1000_RDLEN(reg_idx), 3623 ring->count * sizeof(union e1000_adv_rx_desc)); 3624 3625 /* initialize head and tail */ 3626 ring->tail = hw->hw_addr + E1000_RDT(reg_idx); 3627 wr32(E1000_RDH(reg_idx), 0); 3628 writel(0, ring->tail); 3629 3630 /* set descriptor configuration */ 3631 srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT; 3632 srrctl |= IGB_RX_BUFSZ >> E1000_SRRCTL_BSIZEPKT_SHIFT; 3633 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF; 3634 if (hw->mac.type >= e1000_82580) 3635 srrctl |= E1000_SRRCTL_TIMESTAMP; 3636 /* Only set Drop Enable if we are supporting multiple queues */ 3637 if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1) 3638 srrctl |= E1000_SRRCTL_DROP_EN; 3639 3640 wr32(E1000_SRRCTL(reg_idx), srrctl); 3641 3642 /* set filtering for VMDQ pools */ 3643 igb_set_vmolr(adapter, reg_idx & 0x7, true); 3644 3645 rxdctl |= IGB_RX_PTHRESH; 3646 rxdctl |= IGB_RX_HTHRESH << 8; 3647 rxdctl |= IGB_RX_WTHRESH << 16; 3648 3649 /* enable receive descriptor fetching */ 3650 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE; 3651 wr32(E1000_RXDCTL(reg_idx), rxdctl); 3652} 3653 3654/** 3655 * igb_configure_rx - Configure receive Unit after Reset 3656 * @adapter: board private structure 3657 * 3658 * Configure the Rx unit of the MAC after a reset. 3659 **/ 3660static void igb_configure_rx(struct igb_adapter *adapter) 3661{ 3662 int i; 3663 3664 /* set UTA to appropriate mode */ 3665 igb_set_uta(adapter); 3666 3667 /* set the correct pool for the PF default MAC address in entry 0 */ 3668 igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0, 3669 adapter->vfs_allocated_count); 3670 3671 /* Setup the HW Rx Head and Tail Descriptor Pointers and 3672 * the Base and Length of the Rx Descriptor Ring 3673 */ 3674 for (i = 0; i < adapter->num_rx_queues; i++) 3675 igb_configure_rx_ring(adapter, adapter->rx_ring[i]); 3676} 3677 3678/** 3679 * igb_free_tx_resources - Free Tx Resources per Queue 3680 * @tx_ring: Tx descriptor ring for a specific queue 3681 * 3682 * Free all transmit software resources 3683 **/ 3684void igb_free_tx_resources(struct igb_ring *tx_ring) 3685{ 3686 igb_clean_tx_ring(tx_ring); 3687 3688 vfree(tx_ring->tx_buffer_info); 3689 tx_ring->tx_buffer_info = NULL; 3690 3691 /* if not set, then don't free */ 3692 if (!tx_ring->desc) 3693 return; 3694 3695 dma_free_coherent(tx_ring->dev, tx_ring->size, 3696 tx_ring->desc, tx_ring->dma); 3697 3698 tx_ring->desc = NULL; 3699} 3700 3701/** 3702 * igb_free_all_tx_resources - Free Tx Resources for All Queues 3703 * @adapter: board private structure 3704 * 3705 * Free all transmit software resources 3706 **/ 3707static void igb_free_all_tx_resources(struct igb_adapter *adapter) 3708{ 3709 int i; 3710 3711 for (i = 0; i < adapter->num_tx_queues; i++) 3712 igb_free_tx_resources(adapter->tx_ring[i]); 3713} 3714 3715void igb_unmap_and_free_tx_resource(struct igb_ring *ring, 3716 struct igb_tx_buffer *tx_buffer) 3717{ 3718 if (tx_buffer->skb) { 3719 dev_kfree_skb_any(tx_buffer->skb); 3720 if (dma_unmap_len(tx_buffer, len)) 3721 dma_unmap_single(ring->dev, 3722 dma_unmap_addr(tx_buffer, dma), 3723 dma_unmap_len(tx_buffer, len), 3724 DMA_TO_DEVICE); 3725 } else if (dma_unmap_len(tx_buffer, len)) { 3726 dma_unmap_page(ring->dev, 3727 dma_unmap_addr(tx_buffer, dma), 3728 dma_unmap_len(tx_buffer, len), 3729 DMA_TO_DEVICE); 3730 } 3731 tx_buffer->next_to_watch = NULL; 3732 tx_buffer->skb = NULL; 3733 dma_unmap_len_set(tx_buffer, len, 0); 3734 /* buffer_info must be completely set up in the transmit path */ 3735} 3736 3737/** 3738 * igb_clean_tx_ring - Free Tx Buffers 3739 * @tx_ring: ring to be cleaned 3740 **/ 3741static void igb_clean_tx_ring(struct igb_ring *tx_ring) 3742{ 3743 struct igb_tx_buffer *buffer_info; 3744 unsigned long size; 3745 u16 i; 3746 3747 if (!tx_ring->tx_buffer_info) 3748 return; 3749 /* Free all the Tx ring sk_buffs */ 3750 3751 for (i = 0; i < tx_ring->count; i++) { 3752 buffer_info = &tx_ring->tx_buffer_info[i]; 3753 igb_unmap_and_free_tx_resource(tx_ring, buffer_info); 3754 } 3755 3756 netdev_tx_reset_queue(txring_txq(tx_ring)); 3757 3758 size = sizeof(struct igb_tx_buffer) * tx_ring->count; 3759 memset(tx_ring->tx_buffer_info, 0, size); 3760 3761 /* Zero out the descriptor ring */ 3762 memset(tx_ring->desc, 0, tx_ring->size); 3763 3764 tx_ring->next_to_use = 0; 3765 tx_ring->next_to_clean = 0; 3766} 3767 3768/** 3769 * igb_clean_all_tx_rings - Free Tx Buffers for all queues 3770 * @adapter: board private structure 3771 **/ 3772static void igb_clean_all_tx_rings(struct igb_adapter *adapter) 3773{ 3774 int i; 3775 3776 for (i = 0; i < adapter->num_tx_queues; i++) 3777 igb_clean_tx_ring(adapter->tx_ring[i]); 3778} 3779 3780/** 3781 * igb_free_rx_resources - Free Rx Resources 3782 * @rx_ring: ring to clean the resources from 3783 * 3784 * Free all receive software resources 3785 **/ 3786void igb_free_rx_resources(struct igb_ring *rx_ring) 3787{ 3788 igb_clean_rx_ring(rx_ring); 3789 3790 vfree(rx_ring->rx_buffer_info); 3791 rx_ring->rx_buffer_info = NULL; 3792 3793 /* if not set, then don't free */ 3794 if (!rx_ring->desc) 3795 return; 3796 3797 dma_free_coherent(rx_ring->dev, rx_ring->size, 3798 rx_ring->desc, rx_ring->dma); 3799 3800 rx_ring->desc = NULL; 3801} 3802 3803/** 3804 * igb_free_all_rx_resources - Free Rx Resources for All Queues 3805 * @adapter: board private structure 3806 * 3807 * Free all receive software resources 3808 **/ 3809static void igb_free_all_rx_resources(struct igb_adapter *adapter) 3810{ 3811 int i; 3812 3813 for (i = 0; i < adapter->num_rx_queues; i++) 3814 igb_free_rx_resources(adapter->rx_ring[i]); 3815} 3816 3817/** 3818 * igb_clean_rx_ring - Free Rx Buffers per Queue 3819 * @rx_ring: ring to free buffers from 3820 **/ 3821static void igb_clean_rx_ring(struct igb_ring *rx_ring) 3822{ 3823 unsigned long size; 3824 u16 i; 3825 3826 if (rx_ring->skb) 3827 dev_kfree_skb(rx_ring->skb); 3828 rx_ring->skb = NULL; 3829 3830 if (!rx_ring->rx_buffer_info) 3831 return; 3832 3833 /* Free all the Rx ring sk_buffs */ 3834 for (i = 0; i < rx_ring->count; i++) { 3835 struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i]; 3836 3837 if (!buffer_info->page) 3838 continue; 3839 3840 dma_unmap_page(rx_ring->dev, 3841 buffer_info->dma, 3842 PAGE_SIZE, 3843 DMA_FROM_DEVICE); 3844 __free_page(buffer_info->page); 3845 3846 buffer_info->page = NULL; 3847 } 3848 3849 size = sizeof(struct igb_rx_buffer) * rx_ring->count; 3850 memset(rx_ring->rx_buffer_info, 0, size); 3851 3852 /* Zero out the descriptor ring */ 3853 memset(rx_ring->desc, 0, rx_ring->size); 3854 3855 rx_ring->next_to_alloc = 0; 3856 rx_ring->next_to_clean = 0; 3857 rx_ring->next_to_use = 0; 3858} 3859 3860/** 3861 * igb_clean_all_rx_rings - Free Rx Buffers for all queues 3862 * @adapter: board private structure 3863 **/ 3864static void igb_clean_all_rx_rings(struct igb_adapter *adapter) 3865{ 3866 int i; 3867 3868 for (i = 0; i < adapter->num_rx_queues; i++) 3869 igb_clean_rx_ring(adapter->rx_ring[i]); 3870} 3871 3872/** 3873 * igb_set_mac - Change the Ethernet Address of the NIC 3874 * @netdev: network interface device structure 3875 * @p: pointer to an address structure 3876 * 3877 * Returns 0 on success, negative on failure 3878 **/ 3879static int igb_set_mac(struct net_device *netdev, void *p) 3880{ 3881 struct igb_adapter *adapter = netdev_priv(netdev); 3882 struct e1000_hw *hw = &adapter->hw; 3883 struct sockaddr *addr = p; 3884 3885 if (!is_valid_ether_addr(addr->sa_data)) 3886 return -EADDRNOTAVAIL; 3887 3888 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len); 3889 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len); 3890 3891 /* set the correct pool for the new PF MAC address in entry 0 */ 3892 igb_rar_set_qsel(adapter, hw->mac.addr, 0, 3893 adapter->vfs_allocated_count); 3894 3895 return 0; 3896} 3897 3898/** 3899 * igb_write_mc_addr_list - write multicast addresses to MTA 3900 * @netdev: network interface device structure 3901 * 3902 * Writes multicast address list to the MTA hash table. 3903 * Returns: -ENOMEM on failure 3904 * 0 on no addresses written 3905 * X on writing X addresses to MTA 3906 **/ 3907static int igb_write_mc_addr_list(struct net_device *netdev) 3908{ 3909 struct igb_adapter *adapter = netdev_priv(netdev); 3910 struct e1000_hw *hw = &adapter->hw; 3911 struct netdev_hw_addr *ha; 3912 u8 *mta_list; 3913 int i; 3914 3915 if (netdev_mc_empty(netdev)) { 3916 /* nothing to program, so clear mc list */ 3917 igb_update_mc_addr_list(hw, NULL, 0); 3918 igb_restore_vf_multicasts(adapter); 3919 return 0; 3920 } 3921 3922 mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC); 3923 if (!mta_list) 3924 return -ENOMEM; 3925 3926 /* The shared function expects a packed array of only addresses. */ 3927 i = 0; 3928 netdev_for_each_mc_addr(ha, netdev) 3929 memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN); 3930 3931 igb_update_mc_addr_list(hw, mta_list, i); 3932 kfree(mta_list); 3933 3934 return netdev_mc_count(netdev); 3935} 3936 3937/** 3938 * igb_write_uc_addr_list - write unicast addresses to RAR table 3939 * @netdev: network interface device structure 3940 * 3941 * Writes unicast address list to the RAR table. 3942 * Returns: -ENOMEM on failure/insufficient address space 3943 * 0 on no addresses written 3944 * X on writing X addresses to the RAR table 3945 **/ 3946static int igb_write_uc_addr_list(struct net_device *netdev) 3947{ 3948 struct igb_adapter *adapter = netdev_priv(netdev); 3949 struct e1000_hw *hw = &adapter->hw; 3950 unsigned int vfn = adapter->vfs_allocated_count; 3951 unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1); 3952 int count = 0; 3953 3954 /* return ENOMEM indicating insufficient memory for addresses */ 3955 if (netdev_uc_count(netdev) > rar_entries) 3956 return -ENOMEM; 3957 3958 if (!netdev_uc_empty(netdev) && rar_entries) { 3959 struct netdev_hw_addr *ha; 3960 3961 netdev_for_each_uc_addr(ha, netdev) { 3962 if (!rar_entries) 3963 break; 3964 igb_rar_set_qsel(adapter, ha->addr, 3965 rar_entries--, 3966 vfn); 3967 count++; 3968 } 3969 } 3970 /* write the addresses in reverse order to avoid write combining */ 3971 for (; rar_entries > 0 ; rar_entries--) { 3972 wr32(E1000_RAH(rar_entries), 0); 3973 wr32(E1000_RAL(rar_entries), 0); 3974 } 3975 wrfl(); 3976 3977 return count; 3978} 3979 3980/** 3981 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set 3982 * @netdev: network interface device structure 3983 * 3984 * The set_rx_mode entry point is called whenever the unicast or multicast 3985 * address lists or the network interface flags are updated. This routine is 3986 * responsible for configuring the hardware for proper unicast, multicast, 3987 * promiscuous mode, and all-multi behavior. 3988 **/ 3989static void igb_set_rx_mode(struct net_device *netdev) 3990{ 3991 struct igb_adapter *adapter = netdev_priv(netdev); 3992 struct e1000_hw *hw = &adapter->hw; 3993 unsigned int vfn = adapter->vfs_allocated_count; 3994 u32 rctl, vmolr = 0; 3995 int count; 3996 3997 /* Check for Promiscuous and All Multicast modes */ 3998 rctl = rd32(E1000_RCTL); 3999 4000 /* clear the effected bits */ 4001 rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE); 4002 4003 if (netdev->flags & IFF_PROMISC) { 4004 /* retain VLAN HW filtering if in VT mode */ 4005 if (adapter->vfs_allocated_count) 4006 rctl |= E1000_RCTL_VFE; 4007 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE); 4008 vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME); 4009 } else { 4010 if (netdev->flags & IFF_ALLMULTI) { 4011 rctl |= E1000_RCTL_MPE; 4012 vmolr |= E1000_VMOLR_MPME; 4013 } else { 4014 /* Write addresses to the MTA, if the attempt fails 4015 * then we should just turn on promiscuous mode so 4016 * that we can at least receive multicast traffic 4017 */ 4018 count = igb_write_mc_addr_list(netdev); 4019 if (count < 0) { 4020 rctl |= E1000_RCTL_MPE; 4021 vmolr |= E1000_VMOLR_MPME; 4022 } else if (count) { 4023 vmolr |= E1000_VMOLR_ROMPE; 4024 } 4025 } 4026 /* Write addresses to available RAR registers, if there is not 4027 * sufficient space to store all the addresses then enable 4028 * unicast promiscuous mode 4029 */ 4030 count = igb_write_uc_addr_list(netdev); 4031 if (count < 0) { 4032 rctl |= E1000_RCTL_UPE; 4033 vmolr |= E1000_VMOLR_ROPE; 4034 } 4035 rctl |= E1000_RCTL_VFE; 4036 } 4037 wr32(E1000_RCTL, rctl); 4038 4039 /* In order to support SR-IOV and eventually VMDq it is necessary to set 4040 * the VMOLR to enable the appropriate modes. Without this workaround 4041 * we will have issues with VLAN tag stripping not being done for frames 4042 * that are only arriving because we are the default pool 4043 */ 4044 if ((hw->mac.type < e1000_82576) || (hw->mac.type > e1000_i350)) 4045 return; 4046 4047 vmolr |= rd32(E1000_VMOLR(vfn)) & 4048 ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE); 4049 wr32(E1000_VMOLR(vfn), vmolr); 4050 igb_restore_vf_multicasts(adapter); 4051} 4052 4053static void igb_check_wvbr(struct igb_adapter *adapter) 4054{ 4055 struct e1000_hw *hw = &adapter->hw; 4056 u32 wvbr = 0; 4057 4058 switch (hw->mac.type) { 4059 case e1000_82576: 4060 case e1000_i350: 4061 if (!(wvbr = rd32(E1000_WVBR))) 4062 return; 4063 break; 4064 default: 4065 break; 4066 } 4067 4068 adapter->wvbr |= wvbr; 4069} 4070 4071#define IGB_STAGGERED_QUEUE_OFFSET 8 4072 4073static void igb_spoof_check(struct igb_adapter *adapter) 4074{ 4075 int j; 4076 4077 if (!adapter->wvbr) 4078 return; 4079 4080 for(j = 0; j < adapter->vfs_allocated_count; j++) { 4081 if (adapter->wvbr & (1 << j) || 4082 adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) { 4083 dev_warn(&adapter->pdev->dev, 4084 "Spoof event(s) detected on VF %d\n", j); 4085 adapter->wvbr &= 4086 ~((1 << j) | 4087 (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))); 4088 } 4089 } 4090} 4091 4092/* Need to wait a few seconds after link up to get diagnostic information from 4093 * the phy 4094 */ 4095static void igb_update_phy_info(unsigned long data) 4096{ 4097 struct igb_adapter *adapter = (struct igb_adapter *) data; 4098 igb_get_phy_info(&adapter->hw); 4099} 4100 4101/** 4102 * igb_has_link - check shared code for link and determine up/down 4103 * @adapter: pointer to driver private info 4104 **/ 4105bool igb_has_link(struct igb_adapter *adapter) 4106{ 4107 struct e1000_hw *hw = &adapter->hw; 4108 bool link_active = false; 4109 4110 /* get_link_status is set on LSC (link status) interrupt or 4111 * rx sequence error interrupt. get_link_status will stay 4112 * false until the e1000_check_for_link establishes link 4113 * for copper adapters ONLY 4114 */ 4115 switch (hw->phy.media_type) { 4116 case e1000_media_type_copper: 4117 if (!hw->mac.get_link_status) 4118 return true; 4119 case e1000_media_type_internal_serdes: 4120 hw->mac.ops.check_for_link(hw); 4121 link_active = !hw->mac.get_link_status; 4122 break; 4123 default: 4124 case e1000_media_type_unknown: 4125 break; 4126 } 4127 4128 if (((hw->mac.type == e1000_i210) || 4129 (hw->mac.type == e1000_i211)) && 4130 (hw->phy.id == I210_I_PHY_ID)) { 4131 if (!netif_carrier_ok(adapter->netdev)) { 4132 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4133 } else if (!(adapter->flags & IGB_FLAG_NEED_LINK_UPDATE)) { 4134 adapter->flags |= IGB_FLAG_NEED_LINK_UPDATE; 4135 adapter->link_check_timeout = jiffies; 4136 } 4137 } 4138 4139 return link_active; 4140} 4141 4142static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event) 4143{ 4144 bool ret = false; 4145 u32 ctrl_ext, thstat; 4146 4147 /* check for thermal sensor event on i350 copper only */ 4148 if (hw->mac.type == e1000_i350) { 4149 thstat = rd32(E1000_THSTAT); 4150 ctrl_ext = rd32(E1000_CTRL_EXT); 4151 4152 if ((hw->phy.media_type == e1000_media_type_copper) && 4153 !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) 4154 ret = !!(thstat & event); 4155 } 4156 4157 return ret; 4158} 4159 4160/** 4161 * igb_watchdog - Timer Call-back 4162 * @data: pointer to adapter cast into an unsigned long 4163 **/ 4164static void igb_watchdog(unsigned long data) 4165{ 4166 struct igb_adapter *adapter = (struct igb_adapter *)data; 4167 /* Do the rest outside of interrupt context */ 4168 schedule_work(&adapter->watchdog_task); 4169} 4170 4171static void igb_watchdog_task(struct work_struct *work) 4172{ 4173 struct igb_adapter *adapter = container_of(work, 4174 struct igb_adapter, 4175 watchdog_task); 4176 struct e1000_hw *hw = &adapter->hw; 4177 struct e1000_phy_info *phy = &hw->phy; 4178 struct net_device *netdev = adapter->netdev; 4179 u32 link; 4180 int i; 4181 u32 connsw; 4182 4183 link = igb_has_link(adapter); 4184 4185 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) { 4186 if (time_after(jiffies, (adapter->link_check_timeout + HZ))) 4187 adapter->flags &= ~IGB_FLAG_NEED_LINK_UPDATE; 4188 else 4189 link = false; 4190 } 4191 4192 /* Force link down if we have fiber to swap to */ 4193 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4194 if (hw->phy.media_type == e1000_media_type_copper) { 4195 connsw = rd32(E1000_CONNSW); 4196 if (!(connsw & E1000_CONNSW_AUTOSENSE_EN)) 4197 link = 0; 4198 } 4199 } 4200 if (link) { 4201 /* Perform a reset if the media type changed. */ 4202 if (hw->dev_spec._82575.media_changed) { 4203 hw->dev_spec._82575.media_changed = false; 4204 adapter->flags |= IGB_FLAG_MEDIA_RESET; 4205 igb_reset(adapter); 4206 } 4207 /* Cancel scheduled suspend requests. */ 4208 pm_runtime_resume(netdev->dev.parent); 4209 4210 if (!netif_carrier_ok(netdev)) { 4211 u32 ctrl; 4212 hw->mac.ops.get_speed_and_duplex(hw, 4213 &adapter->link_speed, 4214 &adapter->link_duplex); 4215 4216 ctrl = rd32(E1000_CTRL); 4217 /* Links status message must follow this format */ 4218 printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s " 4219 "Duplex, Flow Control: %s\n", 4220 netdev->name, 4221 adapter->link_speed, 4222 adapter->link_duplex == FULL_DUPLEX ? 4223 "Full" : "Half", 4224 (ctrl & E1000_CTRL_TFCE) && 4225 (ctrl & E1000_CTRL_RFCE) ? "RX/TX" : 4226 (ctrl & E1000_CTRL_RFCE) ? "RX" : 4227 (ctrl & E1000_CTRL_TFCE) ? "TX" : "None"); 4228 4229 /* disable EEE if enabled */ 4230 if ((adapter->flags & IGB_FLAG_EEE) && 4231 (adapter->link_duplex == HALF_DUPLEX)) { 4232 dev_info(&adapter->pdev->dev, 4233 "EEE Disabled: unsupported at half duplex. Re-enable using ethtool when at full duplex.\n"); 4234 adapter->hw.dev_spec._82575.eee_disable = true; 4235 adapter->flags &= ~IGB_FLAG_EEE; 4236 } 4237 4238 /* check if SmartSpeed worked */ 4239 igb_check_downshift(hw); 4240 if (phy->speed_downgraded) 4241 netdev_warn(netdev, "Link Speed was downgraded by SmartSpeed\n"); 4242 4243 /* check for thermal sensor event */ 4244 if (igb_thermal_sensor_event(hw, 4245 E1000_THSTAT_LINK_THROTTLE)) { 4246 netdev_info(netdev, "The network adapter link " 4247 "speed was downshifted because it " 4248 "overheated\n"); 4249 } 4250 4251 /* adjust timeout factor according to speed/duplex */ 4252 adapter->tx_timeout_factor = 1; 4253 switch (adapter->link_speed) { 4254 case SPEED_10: 4255 adapter->tx_timeout_factor = 14; 4256 break; 4257 case SPEED_100: 4258 /* maybe add some timeout factor ? */ 4259 break; 4260 } 4261 4262 netif_carrier_on(netdev); 4263 4264 igb_ping_all_vfs(adapter); 4265 igb_check_vf_rate_limit(adapter); 4266 4267 /* link state has changed, schedule phy info update */ 4268 if (!test_bit(__IGB_DOWN, &adapter->state)) 4269 mod_timer(&adapter->phy_info_timer, 4270 round_jiffies(jiffies + 2 * HZ)); 4271 } 4272 } else { 4273 if (netif_carrier_ok(netdev)) { 4274 adapter->link_speed = 0; 4275 adapter->link_duplex = 0; 4276 4277 /* check for thermal sensor event */ 4278 if (igb_thermal_sensor_event(hw, 4279 E1000_THSTAT_PWR_DOWN)) { 4280 netdev_err(netdev, "The network adapter was " 4281 "stopped because it overheated\n"); 4282 } 4283 4284 /* Links status message must follow this format */ 4285 printk(KERN_INFO "igb: %s NIC Link is Down\n", 4286 netdev->name); 4287 netif_carrier_off(netdev); 4288 4289 igb_ping_all_vfs(adapter); 4290 4291 /* link state has changed, schedule phy info update */ 4292 if (!test_bit(__IGB_DOWN, &adapter->state)) 4293 mod_timer(&adapter->phy_info_timer, 4294 round_jiffies(jiffies + 2 * HZ)); 4295 4296 /* link is down, time to check for alternate media */ 4297 if (adapter->flags & IGB_FLAG_MAS_ENABLE) { 4298 igb_check_swap_media(adapter); 4299 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4300 schedule_work(&adapter->reset_task); 4301 /* return immediately */ 4302 return; 4303 } 4304 } 4305 pm_schedule_suspend(netdev->dev.parent, 4306 MSEC_PER_SEC * 5); 4307 4308 /* also check for alternate media here */ 4309 } else if (!netif_carrier_ok(netdev) && 4310 (adapter->flags & IGB_FLAG_MAS_ENABLE)) { 4311 igb_check_swap_media(adapter); 4312 if (adapter->flags & IGB_FLAG_MEDIA_RESET) { 4313 schedule_work(&adapter->reset_task); 4314 /* return immediately */ 4315 return; 4316 } 4317 } 4318 } 4319 4320 spin_lock(&adapter->stats64_lock); 4321 igb_update_stats(adapter, &adapter->stats64); 4322 spin_unlock(&adapter->stats64_lock); 4323 4324 for (i = 0; i < adapter->num_tx_queues; i++) { 4325 struct igb_ring *tx_ring = adapter->tx_ring[i]; 4326 if (!netif_carrier_ok(netdev)) { 4327 /* We've lost link, so the controller stops DMA, 4328 * but we've got queued Tx work that's never going 4329 * to get done, so reset controller to flush Tx. 4330 * (Do the reset outside of interrupt context). 4331 */ 4332 if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) { 4333 adapter->tx_timeout_count++; 4334 schedule_work(&adapter->reset_task); 4335 /* return immediately since reset is imminent */ 4336 return; 4337 } 4338 } 4339 4340 /* Force detection of hung controller every watchdog period */ 4341 set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 4342 } 4343 4344 /* Cause software interrupt to ensure Rx ring is cleaned */ 4345 if (adapter->flags & IGB_FLAG_HAS_MSIX) { 4346 u32 eics = 0; 4347 for (i = 0; i < adapter->num_q_vectors; i++) 4348 eics |= adapter->q_vector[i]->eims_value; 4349 wr32(E1000_EICS, eics); 4350 } else { 4351 wr32(E1000_ICS, E1000_ICS_RXDMT0); 4352 } 4353 4354 igb_spoof_check(adapter); 4355 igb_ptp_rx_hang(adapter); 4356 4357 /* Reset the timer */ 4358 if (!test_bit(__IGB_DOWN, &adapter->state)) { 4359 if (adapter->flags & IGB_FLAG_NEED_LINK_UPDATE) 4360 mod_timer(&adapter->watchdog_timer, 4361 round_jiffies(jiffies + HZ)); 4362 else 4363 mod_timer(&adapter->watchdog_timer, 4364 round_jiffies(jiffies + 2 * HZ)); 4365 } 4366} 4367 4368enum latency_range { 4369 lowest_latency = 0, 4370 low_latency = 1, 4371 bulk_latency = 2, 4372 latency_invalid = 255 4373}; 4374 4375/** 4376 * igb_update_ring_itr - update the dynamic ITR value based on packet size 4377 * @q_vector: pointer to q_vector 4378 * 4379 * Stores a new ITR value based on strictly on packet size. This 4380 * algorithm is less sophisticated than that used in igb_update_itr, 4381 * due to the difficulty of synchronizing statistics across multiple 4382 * receive rings. The divisors and thresholds used by this function 4383 * were determined based on theoretical maximum wire speed and testing 4384 * data, in order to minimize response time while increasing bulk 4385 * throughput. 4386 * This functionality is controlled by ethtool's coalescing settings. 4387 * NOTE: This function is called only when operating in a multiqueue 4388 * receive environment. 4389 **/ 4390static void igb_update_ring_itr(struct igb_q_vector *q_vector) 4391{ 4392 int new_val = q_vector->itr_val; 4393 int avg_wire_size = 0; 4394 struct igb_adapter *adapter = q_vector->adapter; 4395 unsigned int packets; 4396 4397 /* For non-gigabit speeds, just fix the interrupt rate at 4000 4398 * ints/sec - ITR timer value of 120 ticks. 4399 */ 4400 if (adapter->link_speed != SPEED_1000) { 4401 new_val = IGB_4K_ITR; 4402 goto set_itr_val; 4403 } 4404 4405 packets = q_vector->rx.total_packets; 4406 if (packets) 4407 avg_wire_size = q_vector->rx.total_bytes / packets; 4408 4409 packets = q_vector->tx.total_packets; 4410 if (packets) 4411 avg_wire_size = max_t(u32, avg_wire_size, 4412 q_vector->tx.total_bytes / packets); 4413 4414 /* if avg_wire_size isn't set no work was done */ 4415 if (!avg_wire_size) 4416 goto clear_counts; 4417 4418 /* Add 24 bytes to size to account for CRC, preamble, and gap */ 4419 avg_wire_size += 24; 4420 4421 /* Don't starve jumbo frames */ 4422 avg_wire_size = min(avg_wire_size, 3000); 4423 4424 /* Give a little boost to mid-size frames */ 4425 if ((avg_wire_size > 300) && (avg_wire_size < 1200)) 4426 new_val = avg_wire_size / 3; 4427 else 4428 new_val = avg_wire_size / 2; 4429 4430 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4431 if (new_val < IGB_20K_ITR && 4432 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4433 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4434 new_val = IGB_20K_ITR; 4435 4436set_itr_val: 4437 if (new_val != q_vector->itr_val) { 4438 q_vector->itr_val = new_val; 4439 q_vector->set_itr = 1; 4440 } 4441clear_counts: 4442 q_vector->rx.total_bytes = 0; 4443 q_vector->rx.total_packets = 0; 4444 q_vector->tx.total_bytes = 0; 4445 q_vector->tx.total_packets = 0; 4446} 4447 4448/** 4449 * igb_update_itr - update the dynamic ITR value based on statistics 4450 * @q_vector: pointer to q_vector 4451 * @ring_container: ring info to update the itr for 4452 * 4453 * Stores a new ITR value based on packets and byte 4454 * counts during the last interrupt. The advantage of per interrupt 4455 * computation is faster updates and more accurate ITR for the current 4456 * traffic pattern. Constants in this function were computed 4457 * based on theoretical maximum wire speed and thresholds were set based 4458 * on testing data as well as attempting to minimize response time 4459 * while increasing bulk throughput. 4460 * This functionality is controlled by ethtool's coalescing settings. 4461 * NOTE: These calculations are only valid when operating in a single- 4462 * queue environment. 4463 **/ 4464static void igb_update_itr(struct igb_q_vector *q_vector, 4465 struct igb_ring_container *ring_container) 4466{ 4467 unsigned int packets = ring_container->total_packets; 4468 unsigned int bytes = ring_container->total_bytes; 4469 u8 itrval = ring_container->itr; 4470 4471 /* no packets, exit with status unchanged */ 4472 if (packets == 0) 4473 return; 4474 4475 switch (itrval) { 4476 case lowest_latency: 4477 /* handle TSO and jumbo frames */ 4478 if (bytes/packets > 8000) 4479 itrval = bulk_latency; 4480 else if ((packets < 5) && (bytes > 512)) 4481 itrval = low_latency; 4482 break; 4483 case low_latency: /* 50 usec aka 20000 ints/s */ 4484 if (bytes > 10000) { 4485 /* this if handles the TSO accounting */ 4486 if (bytes/packets > 8000) { 4487 itrval = bulk_latency; 4488 } else if ((packets < 10) || ((bytes/packets) > 1200)) { 4489 itrval = bulk_latency; 4490 } else if ((packets > 35)) { 4491 itrval = lowest_latency; 4492 } 4493 } else if (bytes/packets > 2000) { 4494 itrval = bulk_latency; 4495 } else if (packets <= 2 && bytes < 512) { 4496 itrval = lowest_latency; 4497 } 4498 break; 4499 case bulk_latency: /* 250 usec aka 4000 ints/s */ 4500 if (bytes > 25000) { 4501 if (packets > 35) 4502 itrval = low_latency; 4503 } else if (bytes < 1500) { 4504 itrval = low_latency; 4505 } 4506 break; 4507 } 4508 4509 /* clear work counters since we have the values we need */ 4510 ring_container->total_bytes = 0; 4511 ring_container->total_packets = 0; 4512 4513 /* write updated itr to ring container */ 4514 ring_container->itr = itrval; 4515} 4516 4517static void igb_set_itr(struct igb_q_vector *q_vector) 4518{ 4519 struct igb_adapter *adapter = q_vector->adapter; 4520 u32 new_itr = q_vector->itr_val; 4521 u8 current_itr = 0; 4522 4523 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */ 4524 if (adapter->link_speed != SPEED_1000) { 4525 current_itr = 0; 4526 new_itr = IGB_4K_ITR; 4527 goto set_itr_now; 4528 } 4529 4530 igb_update_itr(q_vector, &q_vector->tx); 4531 igb_update_itr(q_vector, &q_vector->rx); 4532 4533 current_itr = max(q_vector->rx.itr, q_vector->tx.itr); 4534 4535 /* conservative mode (itr 3) eliminates the lowest_latency setting */ 4536 if (current_itr == lowest_latency && 4537 ((q_vector->rx.ring && adapter->rx_itr_setting == 3) || 4538 (!q_vector->rx.ring && adapter->tx_itr_setting == 3))) 4539 current_itr = low_latency; 4540 4541 switch (current_itr) { 4542 /* counts and packets in update_itr are dependent on these numbers */ 4543 case lowest_latency: 4544 new_itr = IGB_70K_ITR; /* 70,000 ints/sec */ 4545 break; 4546 case low_latency: 4547 new_itr = IGB_20K_ITR; /* 20,000 ints/sec */ 4548 break; 4549 case bulk_latency: 4550 new_itr = IGB_4K_ITR; /* 4,000 ints/sec */ 4551 break; 4552 default: 4553 break; 4554 } 4555 4556set_itr_now: 4557 if (new_itr != q_vector->itr_val) { 4558 /* this attempts to bias the interrupt rate towards Bulk 4559 * by adding intermediate steps when interrupt rate is 4560 * increasing 4561 */ 4562 new_itr = new_itr > q_vector->itr_val ? 4563 max((new_itr * q_vector->itr_val) / 4564 (new_itr + (q_vector->itr_val >> 2)), 4565 new_itr) : new_itr; 4566 /* Don't write the value here; it resets the adapter's 4567 * internal timer, and causes us to delay far longer than 4568 * we should between interrupts. Instead, we write the ITR 4569 * value at the beginning of the next interrupt so the timing 4570 * ends up being correct. 4571 */ 4572 q_vector->itr_val = new_itr; 4573 q_vector->set_itr = 1; 4574 } 4575} 4576 4577static void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens, 4578 u32 type_tucmd, u32 mss_l4len_idx) 4579{ 4580 struct e1000_adv_tx_context_desc *context_desc; 4581 u16 i = tx_ring->next_to_use; 4582 4583 context_desc = IGB_TX_CTXTDESC(tx_ring, i); 4584 4585 i++; 4586 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0; 4587 4588 /* set bits to identify this as an advanced context descriptor */ 4589 type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT; 4590 4591 /* For 82575, context index must be unique per ring. */ 4592 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4593 mss_l4len_idx |= tx_ring->reg_idx << 4; 4594 4595 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens); 4596 context_desc->seqnum_seed = 0; 4597 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd); 4598 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx); 4599} 4600 4601static int igb_tso(struct igb_ring *tx_ring, 4602 struct igb_tx_buffer *first, 4603 u8 *hdr_len) 4604{ 4605 struct sk_buff *skb = first->skb; 4606 u32 vlan_macip_lens, type_tucmd; 4607 u32 mss_l4len_idx, l4len; 4608 4609 if (skb->ip_summed != CHECKSUM_PARTIAL) 4610 return 0; 4611 4612 if (!skb_is_gso(skb)) 4613 return 0; 4614 4615 if (skb_header_cloned(skb)) { 4616 int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC); 4617 if (err) 4618 return err; 4619 } 4620 4621 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */ 4622 type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP; 4623 4624 if (first->protocol == htons(ETH_P_IP)) { 4625 struct iphdr *iph = ip_hdr(skb); 4626 iph->tot_len = 0; 4627 iph->check = 0; 4628 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr, 4629 iph->daddr, 0, 4630 IPPROTO_TCP, 4631 0); 4632 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4633 first->tx_flags |= IGB_TX_FLAGS_TSO | 4634 IGB_TX_FLAGS_CSUM | 4635 IGB_TX_FLAGS_IPV4; 4636 } else if (skb_is_gso_v6(skb)) { 4637 ipv6_hdr(skb)->payload_len = 0; 4638 tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr, 4639 &ipv6_hdr(skb)->daddr, 4640 0, IPPROTO_TCP, 0); 4641 first->tx_flags |= IGB_TX_FLAGS_TSO | 4642 IGB_TX_FLAGS_CSUM; 4643 } 4644 4645 /* compute header lengths */ 4646 l4len = tcp_hdrlen(skb); 4647 *hdr_len = skb_transport_offset(skb) + l4len; 4648 4649 /* update gso size and bytecount with header size */ 4650 first->gso_segs = skb_shinfo(skb)->gso_segs; 4651 first->bytecount += (first->gso_segs - 1) * *hdr_len; 4652 4653 /* MSS L4LEN IDX */ 4654 mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT; 4655 mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT; 4656 4657 /* VLAN MACLEN IPLEN */ 4658 vlan_macip_lens = skb_network_header_len(skb); 4659 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4660 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4661 4662 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4663 4664 return 1; 4665} 4666 4667static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first) 4668{ 4669 struct sk_buff *skb = first->skb; 4670 u32 vlan_macip_lens = 0; 4671 u32 mss_l4len_idx = 0; 4672 u32 type_tucmd = 0; 4673 4674 if (skb->ip_summed != CHECKSUM_PARTIAL) { 4675 if (!(first->tx_flags & IGB_TX_FLAGS_VLAN)) 4676 return; 4677 } else { 4678 u8 l4_hdr = 0; 4679 switch (first->protocol) { 4680 case htons(ETH_P_IP): 4681 vlan_macip_lens |= skb_network_header_len(skb); 4682 type_tucmd |= E1000_ADVTXD_TUCMD_IPV4; 4683 l4_hdr = ip_hdr(skb)->protocol; 4684 break; 4685 case htons(ETH_P_IPV6): 4686 vlan_macip_lens |= skb_network_header_len(skb); 4687 l4_hdr = ipv6_hdr(skb)->nexthdr; 4688 break; 4689 default: 4690 if (unlikely(net_ratelimit())) { 4691 dev_warn(tx_ring->dev, 4692 "partial checksum but proto=%x!\n", 4693 first->protocol); 4694 } 4695 break; 4696 } 4697 4698 switch (l4_hdr) { 4699 case IPPROTO_TCP: 4700 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP; 4701 mss_l4len_idx = tcp_hdrlen(skb) << 4702 E1000_ADVTXD_L4LEN_SHIFT; 4703 break; 4704 case IPPROTO_SCTP: 4705 type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP; 4706 mss_l4len_idx = sizeof(struct sctphdr) << 4707 E1000_ADVTXD_L4LEN_SHIFT; 4708 break; 4709 case IPPROTO_UDP: 4710 mss_l4len_idx = sizeof(struct udphdr) << 4711 E1000_ADVTXD_L4LEN_SHIFT; 4712 break; 4713 default: 4714 if (unlikely(net_ratelimit())) { 4715 dev_warn(tx_ring->dev, 4716 "partial checksum but l4 proto=%x!\n", 4717 l4_hdr); 4718 } 4719 break; 4720 } 4721 4722 /* update TX checksum flag */ 4723 first->tx_flags |= IGB_TX_FLAGS_CSUM; 4724 } 4725 4726 vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT; 4727 vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK; 4728 4729 igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx); 4730} 4731 4732#define IGB_SET_FLAG(_input, _flag, _result) \ 4733 ((_flag <= _result) ? \ 4734 ((u32)(_input & _flag) * (_result / _flag)) : \ 4735 ((u32)(_input & _flag) / (_flag / _result))) 4736 4737static u32 igb_tx_cmd_type(struct sk_buff *skb, u32 tx_flags) 4738{ 4739 /* set type for advanced descriptor with frame checksum insertion */ 4740 u32 cmd_type = E1000_ADVTXD_DTYP_DATA | 4741 E1000_ADVTXD_DCMD_DEXT | 4742 E1000_ADVTXD_DCMD_IFCS; 4743 4744 /* set HW vlan bit if vlan is present */ 4745 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_VLAN, 4746 (E1000_ADVTXD_DCMD_VLE)); 4747 4748 /* set segmentation bits for TSO */ 4749 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSO, 4750 (E1000_ADVTXD_DCMD_TSE)); 4751 4752 /* set timestamp bit if present */ 4753 cmd_type |= IGB_SET_FLAG(tx_flags, IGB_TX_FLAGS_TSTAMP, 4754 (E1000_ADVTXD_MAC_TSTAMP)); 4755 4756 /* insert frame checksum */ 4757 cmd_type ^= IGB_SET_FLAG(skb->no_fcs, 1, E1000_ADVTXD_DCMD_IFCS); 4758 4759 return cmd_type; 4760} 4761 4762static void igb_tx_olinfo_status(struct igb_ring *tx_ring, 4763 union e1000_adv_tx_desc *tx_desc, 4764 u32 tx_flags, unsigned int paylen) 4765{ 4766 u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT; 4767 4768 /* 82575 requires a unique index per ring */ 4769 if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags)) 4770 olinfo_status |= tx_ring->reg_idx << 4; 4771 4772 /* insert L4 checksum */ 4773 olinfo_status |= IGB_SET_FLAG(tx_flags, 4774 IGB_TX_FLAGS_CSUM, 4775 (E1000_TXD_POPTS_TXSM << 8)); 4776 4777 /* insert IPv4 checksum */ 4778 olinfo_status |= IGB_SET_FLAG(tx_flags, 4779 IGB_TX_FLAGS_IPV4, 4780 (E1000_TXD_POPTS_IXSM << 8)); 4781 4782 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status); 4783} 4784 4785static void igb_tx_map(struct igb_ring *tx_ring, 4786 struct igb_tx_buffer *first, 4787 const u8 hdr_len) 4788{ 4789 struct sk_buff *skb = first->skb; 4790 struct igb_tx_buffer *tx_buffer; 4791 union e1000_adv_tx_desc *tx_desc; 4792 struct skb_frag_struct *frag; 4793 dma_addr_t dma; 4794 unsigned int data_len, size; 4795 u32 tx_flags = first->tx_flags; 4796 u32 cmd_type = igb_tx_cmd_type(skb, tx_flags); 4797 u16 i = tx_ring->next_to_use; 4798 4799 tx_desc = IGB_TX_DESC(tx_ring, i); 4800 4801 igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len); 4802 4803 size = skb_headlen(skb); 4804 data_len = skb->data_len; 4805 4806 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE); 4807 4808 tx_buffer = first; 4809 4810 for (frag = &skb_shinfo(skb)->frags[0];; frag++) { 4811 if (dma_mapping_error(tx_ring->dev, dma)) 4812 goto dma_error; 4813 4814 /* record length, and DMA address */ 4815 dma_unmap_len_set(tx_buffer, len, size); 4816 dma_unmap_addr_set(tx_buffer, dma, dma); 4817 4818 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4819 4820 while (unlikely(size > IGB_MAX_DATA_PER_TXD)) { 4821 tx_desc->read.cmd_type_len = 4822 cpu_to_le32(cmd_type ^ IGB_MAX_DATA_PER_TXD); 4823 4824 i++; 4825 tx_desc++; 4826 if (i == tx_ring->count) { 4827 tx_desc = IGB_TX_DESC(tx_ring, 0); 4828 i = 0; 4829 } 4830 tx_desc->read.olinfo_status = 0; 4831 4832 dma += IGB_MAX_DATA_PER_TXD; 4833 size -= IGB_MAX_DATA_PER_TXD; 4834 4835 tx_desc->read.buffer_addr = cpu_to_le64(dma); 4836 } 4837 4838 if (likely(!data_len)) 4839 break; 4840 4841 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size); 4842 4843 i++; 4844 tx_desc++; 4845 if (i == tx_ring->count) { 4846 tx_desc = IGB_TX_DESC(tx_ring, 0); 4847 i = 0; 4848 } 4849 tx_desc->read.olinfo_status = 0; 4850 4851 size = skb_frag_size(frag); 4852 data_len -= size; 4853 4854 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, 4855 size, DMA_TO_DEVICE); 4856 4857 tx_buffer = &tx_ring->tx_buffer_info[i]; 4858 } 4859 4860 /* write last descriptor with RS and EOP bits */ 4861 cmd_type |= size | IGB_TXD_DCMD; 4862 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type); 4863 4864 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount); 4865 4866 /* set the timestamp */ 4867 first->time_stamp = jiffies; 4868 4869 /* Force memory writes to complete before letting h/w know there 4870 * are new descriptors to fetch. (Only applicable for weak-ordered 4871 * memory model archs, such as IA-64). 4872 * 4873 * We also need this memory barrier to make certain all of the 4874 * status bits have been updated before next_to_watch is written. 4875 */ 4876 wmb(); 4877 4878 /* set next_to_watch value indicating a packet is present */ 4879 first->next_to_watch = tx_desc; 4880 4881 i++; 4882 if (i == tx_ring->count) 4883 i = 0; 4884 4885 tx_ring->next_to_use = i; 4886 4887 writel(i, tx_ring->tail); 4888 4889 /* we need this if more than one processor can write to our tail 4890 * at a time, it synchronizes IO on IA64/Altix systems 4891 */ 4892 mmiowb(); 4893 4894 return; 4895 4896dma_error: 4897 dev_err(tx_ring->dev, "TX DMA map failed\n"); 4898 4899 /* clear dma mappings for failed tx_buffer_info map */ 4900 for (;;) { 4901 tx_buffer = &tx_ring->tx_buffer_info[i]; 4902 igb_unmap_and_free_tx_resource(tx_ring, tx_buffer); 4903 if (tx_buffer == first) 4904 break; 4905 if (i == 0) 4906 i = tx_ring->count; 4907 i--; 4908 } 4909 4910 tx_ring->next_to_use = i; 4911} 4912 4913static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4914{ 4915 struct net_device *netdev = tx_ring->netdev; 4916 4917 netif_stop_subqueue(netdev, tx_ring->queue_index); 4918 4919 /* Herbert's original patch had: 4920 * smp_mb__after_netif_stop_queue(); 4921 * but since that doesn't exist yet, just open code it. 4922 */ 4923 smp_mb(); 4924 4925 /* We need to check again in a case another CPU has just 4926 * made room available. 4927 */ 4928 if (igb_desc_unused(tx_ring) < size) 4929 return -EBUSY; 4930 4931 /* A reprieve! */ 4932 netif_wake_subqueue(netdev, tx_ring->queue_index); 4933 4934 u64_stats_update_begin(&tx_ring->tx_syncp2); 4935 tx_ring->tx_stats.restart_queue2++; 4936 u64_stats_update_end(&tx_ring->tx_syncp2); 4937 4938 return 0; 4939} 4940 4941static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size) 4942{ 4943 if (igb_desc_unused(tx_ring) >= size) 4944 return 0; 4945 return __igb_maybe_stop_tx(tx_ring, size); 4946} 4947 4948netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb, 4949 struct igb_ring *tx_ring) 4950{ 4951 struct igb_tx_buffer *first; 4952 int tso; 4953 u32 tx_flags = 0; 4954 u16 count = TXD_USE_COUNT(skb_headlen(skb)); 4955 __be16 protocol = vlan_get_protocol(skb); 4956 u8 hdr_len = 0; 4957 4958 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD, 4959 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD, 4960 * + 2 desc gap to keep tail from touching head, 4961 * + 1 desc for context descriptor, 4962 * otherwise try next time 4963 */ 4964 if (NETDEV_FRAG_PAGE_MAX_SIZE > IGB_MAX_DATA_PER_TXD) { 4965 unsigned short f; 4966 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++) 4967 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size); 4968 } else { 4969 count += skb_shinfo(skb)->nr_frags; 4970 } 4971 4972 if (igb_maybe_stop_tx(tx_ring, count + 3)) { 4973 /* this is a hard error */ 4974 return NETDEV_TX_BUSY; 4975 } 4976 4977 /* record the location of the first descriptor for this packet */ 4978 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use]; 4979 first->skb = skb; 4980 first->bytecount = skb->len; 4981 first->gso_segs = 1; 4982 4983 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) { 4984 struct igb_adapter *adapter = netdev_priv(tx_ring->netdev); 4985 4986 if (!test_and_set_bit_lock(__IGB_PTP_TX_IN_PROGRESS, 4987 &adapter->state)) { 4988 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4989 tx_flags |= IGB_TX_FLAGS_TSTAMP; 4990 4991 adapter->ptp_tx_skb = skb_get(skb); 4992 adapter->ptp_tx_start = jiffies; 4993 if (adapter->hw.mac.type == e1000_82576) 4994 schedule_work(&adapter->ptp_tx_work); 4995 } 4996 } 4997 4998 skb_tx_timestamp(skb); 4999 5000 if (vlan_tx_tag_present(skb)) { 5001 tx_flags |= IGB_TX_FLAGS_VLAN; 5002 tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT); 5003 } 5004 5005 /* record initial flags and protocol */ 5006 first->tx_flags = tx_flags; 5007 first->protocol = protocol; 5008 5009 tso = igb_tso(tx_ring, first, &hdr_len); 5010 if (tso < 0) 5011 goto out_drop; 5012 else if (!tso) 5013 igb_tx_csum(tx_ring, first); 5014 5015 igb_tx_map(tx_ring, first, hdr_len); 5016 5017 /* Make sure there is space in the ring for the next send. */ 5018 igb_maybe_stop_tx(tx_ring, DESC_NEEDED); 5019 5020 return NETDEV_TX_OK; 5021 5022out_drop: 5023 igb_unmap_and_free_tx_resource(tx_ring, first); 5024 5025 return NETDEV_TX_OK; 5026} 5027 5028static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter, 5029 struct sk_buff *skb) 5030{ 5031 unsigned int r_idx = skb->queue_mapping; 5032 5033 if (r_idx >= adapter->num_tx_queues) 5034 r_idx = r_idx % adapter->num_tx_queues; 5035 5036 return adapter->tx_ring[r_idx]; 5037} 5038 5039static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, 5040 struct net_device *netdev) 5041{ 5042 struct igb_adapter *adapter = netdev_priv(netdev); 5043 5044 if (test_bit(__IGB_DOWN, &adapter->state)) { 5045 dev_kfree_skb_any(skb); 5046 return NETDEV_TX_OK; 5047 } 5048 5049 if (skb->len <= 0) { 5050 dev_kfree_skb_any(skb); 5051 return NETDEV_TX_OK; 5052 } 5053 5054 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb 5055 * in order to meet this minimum size requirement. 5056 */ 5057 if (unlikely(skb->len < 17)) { 5058 if (skb_pad(skb, 17 - skb->len)) 5059 return NETDEV_TX_OK; 5060 skb->len = 17; 5061 skb_set_tail_pointer(skb, 17); 5062 } 5063 5064 return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb)); 5065} 5066 5067/** 5068 * igb_tx_timeout - Respond to a Tx Hang 5069 * @netdev: network interface device structure 5070 **/ 5071static void igb_tx_timeout(struct net_device *netdev) 5072{ 5073 struct igb_adapter *adapter = netdev_priv(netdev); 5074 struct e1000_hw *hw = &adapter->hw; 5075 5076 /* Do the reset outside of interrupt context */ 5077 adapter->tx_timeout_count++; 5078 5079 if (hw->mac.type >= e1000_82580) 5080 hw->dev_spec._82575.global_device_reset = true; 5081 5082 schedule_work(&adapter->reset_task); 5083 wr32(E1000_EICS, 5084 (adapter->eims_enable_mask & ~adapter->eims_other)); 5085} 5086 5087static void igb_reset_task(struct work_struct *work) 5088{ 5089 struct igb_adapter *adapter; 5090 adapter = container_of(work, struct igb_adapter, reset_task); 5091 5092 igb_dump(adapter); 5093 netdev_err(adapter->netdev, "Reset adapter\n"); 5094 igb_reinit_locked(adapter); 5095} 5096 5097/** 5098 * igb_get_stats64 - Get System Network Statistics 5099 * @netdev: network interface device structure 5100 * @stats: rtnl_link_stats64 pointer 5101 **/ 5102static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev, 5103 struct rtnl_link_stats64 *stats) 5104{ 5105 struct igb_adapter *adapter = netdev_priv(netdev); 5106 5107 spin_lock(&adapter->stats64_lock); 5108 igb_update_stats(adapter, &adapter->stats64); 5109 memcpy(stats, &adapter->stats64, sizeof(*stats)); 5110 spin_unlock(&adapter->stats64_lock); 5111 5112 return stats; 5113} 5114 5115/** 5116 * igb_change_mtu - Change the Maximum Transfer Unit 5117 * @netdev: network interface device structure 5118 * @new_mtu: new value for maximum frame size 5119 * 5120 * Returns 0 on success, negative on failure 5121 **/ 5122static int igb_change_mtu(struct net_device *netdev, int new_mtu) 5123{ 5124 struct igb_adapter *adapter = netdev_priv(netdev); 5125 struct pci_dev *pdev = adapter->pdev; 5126 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 5127 5128 if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) { 5129 dev_err(&pdev->dev, "Invalid MTU setting\n"); 5130 return -EINVAL; 5131 } 5132 5133#define MAX_STD_JUMBO_FRAME_SIZE 9238 5134 if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) { 5135 dev_err(&pdev->dev, "MTU > 9216 not supported.\n"); 5136 return -EINVAL; 5137 } 5138 5139 /* adjust max frame to be at least the size of a standard frame */ 5140 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 5141 max_frame = ETH_FRAME_LEN + ETH_FCS_LEN; 5142 5143 while (test_and_set_bit(__IGB_RESETTING, &adapter->state)) 5144 msleep(1); 5145 5146 /* igb_down has a dependency on max_frame_size */ 5147 adapter->max_frame_size = max_frame; 5148 5149 if (netif_running(netdev)) 5150 igb_down(adapter); 5151 5152 dev_info(&pdev->dev, "changing MTU from %d to %d\n", 5153 netdev->mtu, new_mtu); 5154 netdev->mtu = new_mtu; 5155 5156 if (netif_running(netdev)) 5157 igb_up(adapter); 5158 else 5159 igb_reset(adapter); 5160 5161 clear_bit(__IGB_RESETTING, &adapter->state); 5162 5163 return 0; 5164} 5165 5166/** 5167 * igb_update_stats - Update the board statistics counters 5168 * @adapter: board private structure 5169 **/ 5170void igb_update_stats(struct igb_adapter *adapter, 5171 struct rtnl_link_stats64 *net_stats) 5172{ 5173 struct e1000_hw *hw = &adapter->hw; 5174 struct pci_dev *pdev = adapter->pdev; 5175 u32 reg, mpc; 5176 u16 phy_tmp; 5177 int i; 5178 u64 bytes, packets; 5179 unsigned int start; 5180 u64 _bytes, _packets; 5181 5182#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF 5183 5184 /* Prevent stats update while adapter is being reset, or if the pci 5185 * connection is down. 5186 */ 5187 if (adapter->link_speed == 0) 5188 return; 5189 if (pci_channel_offline(pdev)) 5190 return; 5191 5192 bytes = 0; 5193 packets = 0; 5194 5195 rcu_read_lock(); 5196 for (i = 0; i < adapter->num_rx_queues; i++) { 5197 u32 rqdpc = rd32(E1000_RQDPC(i)); 5198 struct igb_ring *ring = adapter->rx_ring[i]; 5199 5200 if (rqdpc) { 5201 ring->rx_stats.drops += rqdpc; 5202 net_stats->rx_fifo_errors += rqdpc; 5203 } 5204 5205 do { 5206 start = u64_stats_fetch_begin_irq(&ring->rx_syncp); 5207 _bytes = ring->rx_stats.bytes; 5208 _packets = ring->rx_stats.packets; 5209 } while (u64_stats_fetch_retry_irq(&ring->rx_syncp, start)); 5210 bytes += _bytes; 5211 packets += _packets; 5212 } 5213 5214 net_stats->rx_bytes = bytes; 5215 net_stats->rx_packets = packets; 5216 5217 bytes = 0; 5218 packets = 0; 5219 for (i = 0; i < adapter->num_tx_queues; i++) { 5220 struct igb_ring *ring = adapter->tx_ring[i]; 5221 do { 5222 start = u64_stats_fetch_begin_irq(&ring->tx_syncp); 5223 _bytes = ring->tx_stats.bytes; 5224 _packets = ring->tx_stats.packets; 5225 } while (u64_stats_fetch_retry_irq(&ring->tx_syncp, start)); 5226 bytes += _bytes; 5227 packets += _packets; 5228 } 5229 net_stats->tx_bytes = bytes; 5230 net_stats->tx_packets = packets; 5231 rcu_read_unlock(); 5232 5233 /* read stats registers */ 5234 adapter->stats.crcerrs += rd32(E1000_CRCERRS); 5235 adapter->stats.gprc += rd32(E1000_GPRC); 5236 adapter->stats.gorc += rd32(E1000_GORCL); 5237 rd32(E1000_GORCH); /* clear GORCL */ 5238 adapter->stats.bprc += rd32(E1000_BPRC); 5239 adapter->stats.mprc += rd32(E1000_MPRC); 5240 adapter->stats.roc += rd32(E1000_ROC); 5241 5242 adapter->stats.prc64 += rd32(E1000_PRC64); 5243 adapter->stats.prc127 += rd32(E1000_PRC127); 5244 adapter->stats.prc255 += rd32(E1000_PRC255); 5245 adapter->stats.prc511 += rd32(E1000_PRC511); 5246 adapter->stats.prc1023 += rd32(E1000_PRC1023); 5247 adapter->stats.prc1522 += rd32(E1000_PRC1522); 5248 adapter->stats.symerrs += rd32(E1000_SYMERRS); 5249 adapter->stats.sec += rd32(E1000_SEC); 5250 5251 mpc = rd32(E1000_MPC); 5252 adapter->stats.mpc += mpc; 5253 net_stats->rx_fifo_errors += mpc; 5254 adapter->stats.scc += rd32(E1000_SCC); 5255 adapter->stats.ecol += rd32(E1000_ECOL); 5256 adapter->stats.mcc += rd32(E1000_MCC); 5257 adapter->stats.latecol += rd32(E1000_LATECOL); 5258 adapter->stats.dc += rd32(E1000_DC); 5259 adapter->stats.rlec += rd32(E1000_RLEC); 5260 adapter->stats.xonrxc += rd32(E1000_XONRXC); 5261 adapter->stats.xontxc += rd32(E1000_XONTXC); 5262 adapter->stats.xoffrxc += rd32(E1000_XOFFRXC); 5263 adapter->stats.xofftxc += rd32(E1000_XOFFTXC); 5264 adapter->stats.fcruc += rd32(E1000_FCRUC); 5265 adapter->stats.gptc += rd32(E1000_GPTC); 5266 adapter->stats.gotc += rd32(E1000_GOTCL); 5267 rd32(E1000_GOTCH); /* clear GOTCL */ 5268 adapter->stats.rnbc += rd32(E1000_RNBC); 5269 adapter->stats.ruc += rd32(E1000_RUC); 5270 adapter->stats.rfc += rd32(E1000_RFC); 5271 adapter->stats.rjc += rd32(E1000_RJC); 5272 adapter->stats.tor += rd32(E1000_TORH); 5273 adapter->stats.tot += rd32(E1000_TOTH); 5274 adapter->stats.tpr += rd32(E1000_TPR); 5275 5276 adapter->stats.ptc64 += rd32(E1000_PTC64); 5277 adapter->stats.ptc127 += rd32(E1000_PTC127); 5278 adapter->stats.ptc255 += rd32(E1000_PTC255); 5279 adapter->stats.ptc511 += rd32(E1000_PTC511); 5280 adapter->stats.ptc1023 += rd32(E1000_PTC1023); 5281 adapter->stats.ptc1522 += rd32(E1000_PTC1522); 5282 5283 adapter->stats.mptc += rd32(E1000_MPTC); 5284 adapter->stats.bptc += rd32(E1000_BPTC); 5285 5286 adapter->stats.tpt += rd32(E1000_TPT); 5287 adapter->stats.colc += rd32(E1000_COLC); 5288 5289 adapter->stats.algnerrc += rd32(E1000_ALGNERRC); 5290 /* read internal phy specific stats */ 5291 reg = rd32(E1000_CTRL_EXT); 5292 if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) { 5293 adapter->stats.rxerrc += rd32(E1000_RXERRC); 5294 5295 /* this stat has invalid values on i210/i211 */ 5296 if ((hw->mac.type != e1000_i210) && 5297 (hw->mac.type != e1000_i211)) 5298 adapter->stats.tncrs += rd32(E1000_TNCRS); 5299 } 5300 5301 adapter->stats.tsctc += rd32(E1000_TSCTC); 5302 adapter->stats.tsctfc += rd32(E1000_TSCTFC); 5303 5304 adapter->stats.iac += rd32(E1000_IAC); 5305 adapter->stats.icrxoc += rd32(E1000_ICRXOC); 5306 adapter->stats.icrxptc += rd32(E1000_ICRXPTC); 5307 adapter->stats.icrxatc += rd32(E1000_ICRXATC); 5308 adapter->stats.ictxptc += rd32(E1000_ICTXPTC); 5309 adapter->stats.ictxatc += rd32(E1000_ICTXATC); 5310 adapter->stats.ictxqec += rd32(E1000_ICTXQEC); 5311 adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC); 5312 adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC); 5313 5314 /* Fill out the OS statistics structure */ 5315 net_stats->multicast = adapter->stats.mprc; 5316 net_stats->collisions = adapter->stats.colc; 5317 5318 /* Rx Errors */ 5319 5320 /* RLEC on some newer hardware can be incorrect so build 5321 * our own version based on RUC and ROC 5322 */ 5323 net_stats->rx_errors = adapter->stats.rxerrc + 5324 adapter->stats.crcerrs + adapter->stats.algnerrc + 5325 adapter->stats.ruc + adapter->stats.roc + 5326 adapter->stats.cexterr; 5327 net_stats->rx_length_errors = adapter->stats.ruc + 5328 adapter->stats.roc; 5329 net_stats->rx_crc_errors = adapter->stats.crcerrs; 5330 net_stats->rx_frame_errors = adapter->stats.algnerrc; 5331 net_stats->rx_missed_errors = adapter->stats.mpc; 5332 5333 /* Tx Errors */ 5334 net_stats->tx_errors = adapter->stats.ecol + 5335 adapter->stats.latecol; 5336 net_stats->tx_aborted_errors = adapter->stats.ecol; 5337 net_stats->tx_window_errors = adapter->stats.latecol; 5338 net_stats->tx_carrier_errors = adapter->stats.tncrs; 5339 5340 /* Tx Dropped needs to be maintained elsewhere */ 5341 5342 /* Phy Stats */ 5343 if (hw->phy.media_type == e1000_media_type_copper) { 5344 if ((adapter->link_speed == SPEED_1000) && 5345 (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) { 5346 phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK; 5347 adapter->phy_stats.idle_errors += phy_tmp; 5348 } 5349 } 5350 5351 /* Management Stats */ 5352 adapter->stats.mgptc += rd32(E1000_MGTPTC); 5353 adapter->stats.mgprc += rd32(E1000_MGTPRC); 5354 adapter->stats.mgpdc += rd32(E1000_MGTPDC); 5355 5356 /* OS2BMC Stats */ 5357 reg = rd32(E1000_MANC); 5358 if (reg & E1000_MANC_EN_BMC2OS) { 5359 adapter->stats.o2bgptc += rd32(E1000_O2BGPTC); 5360 adapter->stats.o2bspc += rd32(E1000_O2BSPC); 5361 adapter->stats.b2ospc += rd32(E1000_B2OSPC); 5362 adapter->stats.b2ogprc += rd32(E1000_B2OGPRC); 5363 } 5364} 5365 5366static irqreturn_t igb_msix_other(int irq, void *data) 5367{ 5368 struct igb_adapter *adapter = data; 5369 struct e1000_hw *hw = &adapter->hw; 5370 u32 icr = rd32(E1000_ICR); 5371 /* reading ICR causes bit 31 of EICR to be cleared */ 5372 5373 if (icr & E1000_ICR_DRSTA) 5374 schedule_work(&adapter->reset_task); 5375 5376 if (icr & E1000_ICR_DOUTSYNC) { 5377 /* HW is reporting DMA is out of sync */ 5378 adapter->stats.doosync++; 5379 /* The DMA Out of Sync is also indication of a spoof event 5380 * in IOV mode. Check the Wrong VM Behavior register to 5381 * see if it is really a spoof event. 5382 */ 5383 igb_check_wvbr(adapter); 5384 } 5385 5386 /* Check for a mailbox event */ 5387 if (icr & E1000_ICR_VMMB) 5388 igb_msg_task(adapter); 5389 5390 if (icr & E1000_ICR_LSC) { 5391 hw->mac.get_link_status = 1; 5392 /* guard against interrupt when we're going down */ 5393 if (!test_bit(__IGB_DOWN, &adapter->state)) 5394 mod_timer(&adapter->watchdog_timer, jiffies + 1); 5395 } 5396 5397 if (icr & E1000_ICR_TS) { 5398 u32 tsicr = rd32(E1000_TSICR); 5399 5400 if (tsicr & E1000_TSICR_TXTS) { 5401 /* acknowledge the interrupt */ 5402 wr32(E1000_TSICR, E1000_TSICR_TXTS); 5403 /* retrieve hardware timestamp */ 5404 schedule_work(&adapter->ptp_tx_work); 5405 } 5406 } 5407 5408 wr32(E1000_EIMS, adapter->eims_other); 5409 5410 return IRQ_HANDLED; 5411} 5412 5413static void igb_write_itr(struct igb_q_vector *q_vector) 5414{ 5415 struct igb_adapter *adapter = q_vector->adapter; 5416 u32 itr_val = q_vector->itr_val & 0x7FFC; 5417 5418 if (!q_vector->set_itr) 5419 return; 5420 5421 if (!itr_val) 5422 itr_val = 0x4; 5423 5424 if (adapter->hw.mac.type == e1000_82575) 5425 itr_val |= itr_val << 16; 5426 else 5427 itr_val |= E1000_EITR_CNT_IGNR; 5428 5429 writel(itr_val, q_vector->itr_register); 5430 q_vector->set_itr = 0; 5431} 5432 5433static irqreturn_t igb_msix_ring(int irq, void *data) 5434{ 5435 struct igb_q_vector *q_vector = data; 5436 5437 /* Write the ITR value calculated from the previous interrupt. */ 5438 igb_write_itr(q_vector); 5439 5440 napi_schedule(&q_vector->napi); 5441 5442 return IRQ_HANDLED; 5443} 5444 5445#ifdef CONFIG_IGB_DCA 5446static void igb_update_tx_dca(struct igb_adapter *adapter, 5447 struct igb_ring *tx_ring, 5448 int cpu) 5449{ 5450 struct e1000_hw *hw = &adapter->hw; 5451 u32 txctrl = dca3_get_tag(tx_ring->dev, cpu); 5452 5453 if (hw->mac.type != e1000_82575) 5454 txctrl <<= E1000_DCA_TXCTRL_CPUID_SHIFT; 5455 5456 /* We can enable relaxed ordering for reads, but not writes when 5457 * DCA is enabled. This is due to a known issue in some chipsets 5458 * which will cause the DCA tag to be cleared. 5459 */ 5460 txctrl |= E1000_DCA_TXCTRL_DESC_RRO_EN | 5461 E1000_DCA_TXCTRL_DATA_RRO_EN | 5462 E1000_DCA_TXCTRL_DESC_DCA_EN; 5463 5464 wr32(E1000_DCA_TXCTRL(tx_ring->reg_idx), txctrl); 5465} 5466 5467static void igb_update_rx_dca(struct igb_adapter *adapter, 5468 struct igb_ring *rx_ring, 5469 int cpu) 5470{ 5471 struct e1000_hw *hw = &adapter->hw; 5472 u32 rxctrl = dca3_get_tag(&adapter->pdev->dev, cpu); 5473 5474 if (hw->mac.type != e1000_82575) 5475 rxctrl <<= E1000_DCA_RXCTRL_CPUID_SHIFT; 5476 5477 /* We can enable relaxed ordering for reads, but not writes when 5478 * DCA is enabled. This is due to a known issue in some chipsets 5479 * which will cause the DCA tag to be cleared. 5480 */ 5481 rxctrl |= E1000_DCA_RXCTRL_DESC_RRO_EN | 5482 E1000_DCA_RXCTRL_DESC_DCA_EN; 5483 5484 wr32(E1000_DCA_RXCTRL(rx_ring->reg_idx), rxctrl); 5485} 5486 5487static void igb_update_dca(struct igb_q_vector *q_vector) 5488{ 5489 struct igb_adapter *adapter = q_vector->adapter; 5490 int cpu = get_cpu(); 5491 5492 if (q_vector->cpu == cpu) 5493 goto out_no_update; 5494 5495 if (q_vector->tx.ring) 5496 igb_update_tx_dca(adapter, q_vector->tx.ring, cpu); 5497 5498 if (q_vector->rx.ring) 5499 igb_update_rx_dca(adapter, q_vector->rx.ring, cpu); 5500 5501 q_vector->cpu = cpu; 5502out_no_update: 5503 put_cpu(); 5504} 5505 5506static void igb_setup_dca(struct igb_adapter *adapter) 5507{ 5508 struct e1000_hw *hw = &adapter->hw; 5509 int i; 5510 5511 if (!(adapter->flags & IGB_FLAG_DCA_ENABLED)) 5512 return; 5513 5514 /* Always use CB2 mode, difference is masked in the CB driver. */ 5515 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2); 5516 5517 for (i = 0; i < adapter->num_q_vectors; i++) { 5518 adapter->q_vector[i]->cpu = -1; 5519 igb_update_dca(adapter->q_vector[i]); 5520 } 5521} 5522 5523static int __igb_notify_dca(struct device *dev, void *data) 5524{ 5525 struct net_device *netdev = dev_get_drvdata(dev); 5526 struct igb_adapter *adapter = netdev_priv(netdev); 5527 struct pci_dev *pdev = adapter->pdev; 5528 struct e1000_hw *hw = &adapter->hw; 5529 unsigned long event = *(unsigned long *)data; 5530 5531 switch (event) { 5532 case DCA_PROVIDER_ADD: 5533 /* if already enabled, don't do it again */ 5534 if (adapter->flags & IGB_FLAG_DCA_ENABLED) 5535 break; 5536 if (dca_add_requester(dev) == 0) { 5537 adapter->flags |= IGB_FLAG_DCA_ENABLED; 5538 dev_info(&pdev->dev, "DCA enabled\n"); 5539 igb_setup_dca(adapter); 5540 break; 5541 } 5542 /* Fall Through since DCA is disabled. */ 5543 case DCA_PROVIDER_REMOVE: 5544 if (adapter->flags & IGB_FLAG_DCA_ENABLED) { 5545 /* without this a class_device is left 5546 * hanging around in the sysfs model 5547 */ 5548 dca_remove_requester(dev); 5549 dev_info(&pdev->dev, "DCA disabled\n"); 5550 adapter->flags &= ~IGB_FLAG_DCA_ENABLED; 5551 wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE); 5552 } 5553 break; 5554 } 5555 5556 return 0; 5557} 5558 5559static int igb_notify_dca(struct notifier_block *nb, unsigned long event, 5560 void *p) 5561{ 5562 int ret_val; 5563 5564 ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event, 5565 __igb_notify_dca); 5566 5567 return ret_val ? NOTIFY_BAD : NOTIFY_DONE; 5568} 5569#endif /* CONFIG_IGB_DCA */ 5570 5571#ifdef CONFIG_PCI_IOV 5572static int igb_vf_configure(struct igb_adapter *adapter, int vf) 5573{ 5574 unsigned char mac_addr[ETH_ALEN]; 5575 5576 eth_zero_addr(mac_addr); 5577 igb_set_vf_mac(adapter, vf, mac_addr); 5578 5579 /* By default spoof check is enabled for all VFs */ 5580 adapter->vf_data[vf].spoofchk_enabled = true; 5581 5582 return 0; 5583} 5584 5585#endif 5586static void igb_ping_all_vfs(struct igb_adapter *adapter) 5587{ 5588 struct e1000_hw *hw = &adapter->hw; 5589 u32 ping; 5590 int i; 5591 5592 for (i = 0 ; i < adapter->vfs_allocated_count; i++) { 5593 ping = E1000_PF_CONTROL_MSG; 5594 if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS) 5595 ping |= E1000_VT_MSGTYPE_CTS; 5596 igb_write_mbx(hw, &ping, 1, i); 5597 } 5598} 5599 5600static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5601{ 5602 struct e1000_hw *hw = &adapter->hw; 5603 u32 vmolr = rd32(E1000_VMOLR(vf)); 5604 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5605 5606 vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC | 5607 IGB_VF_FLAG_MULTI_PROMISC); 5608 vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5609 5610 if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) { 5611 vmolr |= E1000_VMOLR_MPME; 5612 vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC; 5613 *msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST; 5614 } else { 5615 /* if we have hashes and we are clearing a multicast promisc 5616 * flag we need to write the hashes to the MTA as this step 5617 * was previously skipped 5618 */ 5619 if (vf_data->num_vf_mc_hashes > 30) { 5620 vmolr |= E1000_VMOLR_MPME; 5621 } else if (vf_data->num_vf_mc_hashes) { 5622 int j; 5623 vmolr |= E1000_VMOLR_ROMPE; 5624 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5625 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5626 } 5627 } 5628 5629 wr32(E1000_VMOLR(vf), vmolr); 5630 5631 /* there are flags left unprocessed, likely not supported */ 5632 if (*msgbuf & E1000_VT_MSGINFO_MASK) 5633 return -EINVAL; 5634 5635 return 0; 5636} 5637 5638static int igb_set_vf_multicasts(struct igb_adapter *adapter, 5639 u32 *msgbuf, u32 vf) 5640{ 5641 int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5642 u16 *hash_list = (u16 *)&msgbuf[1]; 5643 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 5644 int i; 5645 5646 /* salt away the number of multicast addresses assigned 5647 * to this VF for later use to restore when the PF multi cast 5648 * list changes 5649 */ 5650 vf_data->num_vf_mc_hashes = n; 5651 5652 /* only up to 30 hash values supported */ 5653 if (n > 30) 5654 n = 30; 5655 5656 /* store the hashes for later use */ 5657 for (i = 0; i < n; i++) 5658 vf_data->vf_mc_hashes[i] = hash_list[i]; 5659 5660 /* Flush and reset the mta with the new values */ 5661 igb_set_rx_mode(adapter->netdev); 5662 5663 return 0; 5664} 5665 5666static void igb_restore_vf_multicasts(struct igb_adapter *adapter) 5667{ 5668 struct e1000_hw *hw = &adapter->hw; 5669 struct vf_data_storage *vf_data; 5670 int i, j; 5671 5672 for (i = 0; i < adapter->vfs_allocated_count; i++) { 5673 u32 vmolr = rd32(E1000_VMOLR(i)); 5674 vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME); 5675 5676 vf_data = &adapter->vf_data[i]; 5677 5678 if ((vf_data->num_vf_mc_hashes > 30) || 5679 (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) { 5680 vmolr |= E1000_VMOLR_MPME; 5681 } else if (vf_data->num_vf_mc_hashes) { 5682 vmolr |= E1000_VMOLR_ROMPE; 5683 for (j = 0; j < vf_data->num_vf_mc_hashes; j++) 5684 igb_mta_set(hw, vf_data->vf_mc_hashes[j]); 5685 } 5686 wr32(E1000_VMOLR(i), vmolr); 5687 } 5688} 5689 5690static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf) 5691{ 5692 struct e1000_hw *hw = &adapter->hw; 5693 u32 pool_mask, reg, vid; 5694 int i; 5695 5696 pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5697 5698 /* Find the vlan filter for this id */ 5699 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5700 reg = rd32(E1000_VLVF(i)); 5701 5702 /* remove the vf from the pool */ 5703 reg &= ~pool_mask; 5704 5705 /* if pool is empty then remove entry from vfta */ 5706 if (!(reg & E1000_VLVF_POOLSEL_MASK) && 5707 (reg & E1000_VLVF_VLANID_ENABLE)) { 5708 reg = 0; 5709 vid = reg & E1000_VLVF_VLANID_MASK; 5710 igb_vfta_set(hw, vid, false); 5711 } 5712 5713 wr32(E1000_VLVF(i), reg); 5714 } 5715 5716 adapter->vf_data[vf].vlans_enabled = 0; 5717} 5718 5719static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf) 5720{ 5721 struct e1000_hw *hw = &adapter->hw; 5722 u32 reg, i; 5723 5724 /* The vlvf table only exists on 82576 hardware and newer */ 5725 if (hw->mac.type < e1000_82576) 5726 return -1; 5727 5728 /* we only need to do this if VMDq is enabled */ 5729 if (!adapter->vfs_allocated_count) 5730 return -1; 5731 5732 /* Find the vlan filter for this id */ 5733 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5734 reg = rd32(E1000_VLVF(i)); 5735 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5736 vid == (reg & E1000_VLVF_VLANID_MASK)) 5737 break; 5738 } 5739 5740 if (add) { 5741 if (i == E1000_VLVF_ARRAY_SIZE) { 5742 /* Did not find a matching VLAN ID entry that was 5743 * enabled. Search for a free filter entry, i.e. 5744 * one without the enable bit set 5745 */ 5746 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5747 reg = rd32(E1000_VLVF(i)); 5748 if (!(reg & E1000_VLVF_VLANID_ENABLE)) 5749 break; 5750 } 5751 } 5752 if (i < E1000_VLVF_ARRAY_SIZE) { 5753 /* Found an enabled/available entry */ 5754 reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf); 5755 5756 /* if !enabled we need to set this up in vfta */ 5757 if (!(reg & E1000_VLVF_VLANID_ENABLE)) { 5758 /* add VID to filter table */ 5759 igb_vfta_set(hw, vid, true); 5760 reg |= E1000_VLVF_VLANID_ENABLE; 5761 } 5762 reg &= ~E1000_VLVF_VLANID_MASK; 5763 reg |= vid; 5764 wr32(E1000_VLVF(i), reg); 5765 5766 /* do not modify RLPML for PF devices */ 5767 if (vf >= adapter->vfs_allocated_count) 5768 return 0; 5769 5770 if (!adapter->vf_data[vf].vlans_enabled) { 5771 u32 size; 5772 reg = rd32(E1000_VMOLR(vf)); 5773 size = reg & E1000_VMOLR_RLPML_MASK; 5774 size += 4; 5775 reg &= ~E1000_VMOLR_RLPML_MASK; 5776 reg |= size; 5777 wr32(E1000_VMOLR(vf), reg); 5778 } 5779 5780 adapter->vf_data[vf].vlans_enabled++; 5781 } 5782 } else { 5783 if (i < E1000_VLVF_ARRAY_SIZE) { 5784 /* remove vf from the pool */ 5785 reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf)); 5786 /* if pool is empty then remove entry from vfta */ 5787 if (!(reg & E1000_VLVF_POOLSEL_MASK)) { 5788 reg = 0; 5789 igb_vfta_set(hw, vid, false); 5790 } 5791 wr32(E1000_VLVF(i), reg); 5792 5793 /* do not modify RLPML for PF devices */ 5794 if (vf >= adapter->vfs_allocated_count) 5795 return 0; 5796 5797 adapter->vf_data[vf].vlans_enabled--; 5798 if (!adapter->vf_data[vf].vlans_enabled) { 5799 u32 size; 5800 reg = rd32(E1000_VMOLR(vf)); 5801 size = reg & E1000_VMOLR_RLPML_MASK; 5802 size -= 4; 5803 reg &= ~E1000_VMOLR_RLPML_MASK; 5804 reg |= size; 5805 wr32(E1000_VMOLR(vf), reg); 5806 } 5807 } 5808 } 5809 return 0; 5810} 5811 5812static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf) 5813{ 5814 struct e1000_hw *hw = &adapter->hw; 5815 5816 if (vid) 5817 wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT)); 5818 else 5819 wr32(E1000_VMVIR(vf), 0); 5820} 5821 5822static int igb_ndo_set_vf_vlan(struct net_device *netdev, 5823 int vf, u16 vlan, u8 qos) 5824{ 5825 int err = 0; 5826 struct igb_adapter *adapter = netdev_priv(netdev); 5827 5828 if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7)) 5829 return -EINVAL; 5830 if (vlan || qos) { 5831 err = igb_vlvf_set(adapter, vlan, !!vlan, vf); 5832 if (err) 5833 goto out; 5834 igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf); 5835 igb_set_vmolr(adapter, vf, !vlan); 5836 adapter->vf_data[vf].pf_vlan = vlan; 5837 adapter->vf_data[vf].pf_qos = qos; 5838 dev_info(&adapter->pdev->dev, 5839 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf); 5840 if (test_bit(__IGB_DOWN, &adapter->state)) { 5841 dev_warn(&adapter->pdev->dev, 5842 "The VF VLAN has been set, but the PF device is not up.\n"); 5843 dev_warn(&adapter->pdev->dev, 5844 "Bring the PF device up before attempting to use the VF device.\n"); 5845 } 5846 } else { 5847 igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan, 5848 false, vf); 5849 igb_set_vmvir(adapter, vlan, vf); 5850 igb_set_vmolr(adapter, vf, true); 5851 adapter->vf_data[vf].pf_vlan = 0; 5852 adapter->vf_data[vf].pf_qos = 0; 5853 } 5854out: 5855 return err; 5856} 5857 5858static int igb_find_vlvf_entry(struct igb_adapter *adapter, int vid) 5859{ 5860 struct e1000_hw *hw = &adapter->hw; 5861 int i; 5862 u32 reg; 5863 5864 /* Find the vlan filter for this id */ 5865 for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) { 5866 reg = rd32(E1000_VLVF(i)); 5867 if ((reg & E1000_VLVF_VLANID_ENABLE) && 5868 vid == (reg & E1000_VLVF_VLANID_MASK)) 5869 break; 5870 } 5871 5872 if (i >= E1000_VLVF_ARRAY_SIZE) 5873 i = -1; 5874 5875 return i; 5876} 5877 5878static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf) 5879{ 5880 struct e1000_hw *hw = &adapter->hw; 5881 int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT; 5882 int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK); 5883 int err = 0; 5884 5885 /* If in promiscuous mode we need to make sure the PF also has 5886 * the VLAN filter set. 5887 */ 5888 if (add && (adapter->netdev->flags & IFF_PROMISC)) 5889 err = igb_vlvf_set(adapter, vid, add, 5890 adapter->vfs_allocated_count); 5891 if (err) 5892 goto out; 5893 5894 err = igb_vlvf_set(adapter, vid, add, vf); 5895 5896 if (err) 5897 goto out; 5898 5899 /* Go through all the checks to see if the VLAN filter should 5900 * be wiped completely. 5901 */ 5902 if (!add && (adapter->netdev->flags & IFF_PROMISC)) { 5903 u32 vlvf, bits; 5904 5905 int regndx = igb_find_vlvf_entry(adapter, vid); 5906 if (regndx < 0) 5907 goto out; 5908 /* See if any other pools are set for this VLAN filter 5909 * entry other than the PF. 5910 */ 5911 vlvf = bits = rd32(E1000_VLVF(regndx)); 5912 bits &= 1 << (E1000_VLVF_POOLSEL_SHIFT + 5913 adapter->vfs_allocated_count); 5914 /* If the filter was removed then ensure PF pool bit 5915 * is cleared if the PF only added itself to the pool 5916 * because the PF is in promiscuous mode. 5917 */ 5918 if ((vlvf & VLAN_VID_MASK) == vid && 5919 !test_bit(vid, adapter->active_vlans) && 5920 !bits) 5921 igb_vlvf_set(adapter, vid, add, 5922 adapter->vfs_allocated_count); 5923 } 5924 5925out: 5926 return err; 5927} 5928 5929static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf) 5930{ 5931 /* clear flags - except flag that indicates PF has set the MAC */ 5932 adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC; 5933 adapter->vf_data[vf].last_nack = jiffies; 5934 5935 /* reset offloads to defaults */ 5936 igb_set_vmolr(adapter, vf, true); 5937 5938 /* reset vlans for device */ 5939 igb_clear_vf_vfta(adapter, vf); 5940 if (adapter->vf_data[vf].pf_vlan) 5941 igb_ndo_set_vf_vlan(adapter->netdev, vf, 5942 adapter->vf_data[vf].pf_vlan, 5943 adapter->vf_data[vf].pf_qos); 5944 else 5945 igb_clear_vf_vfta(adapter, vf); 5946 5947 /* reset multicast table array for vf */ 5948 adapter->vf_data[vf].num_vf_mc_hashes = 0; 5949 5950 /* Flush and reset the mta with the new values */ 5951 igb_set_rx_mode(adapter->netdev); 5952} 5953 5954static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf) 5955{ 5956 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5957 5958 /* clear mac address as we were hotplug removed/added */ 5959 if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC)) 5960 eth_zero_addr(vf_mac); 5961 5962 /* process remaining reset events */ 5963 igb_vf_reset(adapter, vf); 5964} 5965 5966static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf) 5967{ 5968 struct e1000_hw *hw = &adapter->hw; 5969 unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses; 5970 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 5971 u32 reg, msgbuf[3]; 5972 u8 *addr = (u8 *)(&msgbuf[1]); 5973 5974 /* process all the same items cleared in a function level reset */ 5975 igb_vf_reset(adapter, vf); 5976 5977 /* set vf mac address */ 5978 igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf); 5979 5980 /* enable transmit and receive for vf */ 5981 reg = rd32(E1000_VFTE); 5982 wr32(E1000_VFTE, reg | (1 << vf)); 5983 reg = rd32(E1000_VFRE); 5984 wr32(E1000_VFRE, reg | (1 << vf)); 5985 5986 adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS; 5987 5988 /* reply to reset with ack and vf mac address */ 5989 msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK; 5990 memcpy(addr, vf_mac, ETH_ALEN); 5991 igb_write_mbx(hw, msgbuf, 3, vf); 5992} 5993 5994static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf) 5995{ 5996 /* The VF MAC Address is stored in a packed array of bytes 5997 * starting at the second 32 bit word of the msg array 5998 */ 5999 unsigned char *addr = (char *)&msg[1]; 6000 int err = -1; 6001 6002 if (is_valid_ether_addr(addr)) 6003 err = igb_set_vf_mac(adapter, vf, addr); 6004 6005 return err; 6006} 6007 6008static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf) 6009{ 6010 struct e1000_hw *hw = &adapter->hw; 6011 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6012 u32 msg = E1000_VT_MSGTYPE_NACK; 6013 6014 /* if device isn't clear to send it shouldn't be reading either */ 6015 if (!(vf_data->flags & IGB_VF_FLAG_CTS) && 6016 time_after(jiffies, vf_data->last_nack + (2 * HZ))) { 6017 igb_write_mbx(hw, &msg, 1, vf); 6018 vf_data->last_nack = jiffies; 6019 } 6020} 6021 6022static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf) 6023{ 6024 struct pci_dev *pdev = adapter->pdev; 6025 u32 msgbuf[E1000_VFMAILBOX_SIZE]; 6026 struct e1000_hw *hw = &adapter->hw; 6027 struct vf_data_storage *vf_data = &adapter->vf_data[vf]; 6028 s32 retval; 6029 6030 retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf); 6031 6032 if (retval) { 6033 /* if receive failed revoke VF CTS stats and restart init */ 6034 dev_err(&pdev->dev, "Error receiving message from VF\n"); 6035 vf_data->flags &= ~IGB_VF_FLAG_CTS; 6036 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6037 return; 6038 goto out; 6039 } 6040 6041 /* this is a message we already processed, do nothing */ 6042 if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK)) 6043 return; 6044 6045 /* until the vf completes a reset it should not be 6046 * allowed to start any configuration. 6047 */ 6048 if (msgbuf[0] == E1000_VF_RESET) { 6049 igb_vf_reset_msg(adapter, vf); 6050 return; 6051 } 6052 6053 if (!(vf_data->flags & IGB_VF_FLAG_CTS)) { 6054 if (!time_after(jiffies, vf_data->last_nack + (2 * HZ))) 6055 return; 6056 retval = -1; 6057 goto out; 6058 } 6059 6060 switch ((msgbuf[0] & 0xFFFF)) { 6061 case E1000_VF_SET_MAC_ADDR: 6062 retval = -EINVAL; 6063 if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC)) 6064 retval = igb_set_vf_mac_addr(adapter, msgbuf, vf); 6065 else 6066 dev_warn(&pdev->dev, 6067 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n", 6068 vf); 6069 break; 6070 case E1000_VF_SET_PROMISC: 6071 retval = igb_set_vf_promisc(adapter, msgbuf, vf); 6072 break; 6073 case E1000_VF_SET_MULTICAST: 6074 retval = igb_set_vf_multicasts(adapter, msgbuf, vf); 6075 break; 6076 case E1000_VF_SET_LPE: 6077 retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf); 6078 break; 6079 case E1000_VF_SET_VLAN: 6080 retval = -1; 6081 if (vf_data->pf_vlan) 6082 dev_warn(&pdev->dev, 6083 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n", 6084 vf); 6085 else 6086 retval = igb_set_vf_vlan(adapter, msgbuf, vf); 6087 break; 6088 default: 6089 dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]); 6090 retval = -1; 6091 break; 6092 } 6093 6094 msgbuf[0] |= E1000_VT_MSGTYPE_CTS; 6095out: 6096 /* notify the VF of the results of what it sent us */ 6097 if (retval) 6098 msgbuf[0] |= E1000_VT_MSGTYPE_NACK; 6099 else 6100 msgbuf[0] |= E1000_VT_MSGTYPE_ACK; 6101 6102 igb_write_mbx(hw, msgbuf, 1, vf); 6103} 6104 6105static void igb_msg_task(struct igb_adapter *adapter) 6106{ 6107 struct e1000_hw *hw = &adapter->hw; 6108 u32 vf; 6109 6110 for (vf = 0; vf < adapter->vfs_allocated_count; vf++) { 6111 /* process any reset requests */ 6112 if (!igb_check_for_rst(hw, vf)) 6113 igb_vf_reset_event(adapter, vf); 6114 6115 /* process any messages pending */ 6116 if (!igb_check_for_msg(hw, vf)) 6117 igb_rcv_msg_from_vf(adapter, vf); 6118 6119 /* process any acks */ 6120 if (!igb_check_for_ack(hw, vf)) 6121 igb_rcv_ack_from_vf(adapter, vf); 6122 } 6123} 6124 6125/** 6126 * igb_set_uta - Set unicast filter table address 6127 * @adapter: board private structure 6128 * 6129 * The unicast table address is a register array of 32-bit registers. 6130 * The table is meant to be used in a way similar to how the MTA is used 6131 * however due to certain limitations in the hardware it is necessary to 6132 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous 6133 * enable bit to allow vlan tag stripping when promiscuous mode is enabled 6134 **/ 6135static void igb_set_uta(struct igb_adapter *adapter) 6136{ 6137 struct e1000_hw *hw = &adapter->hw; 6138 int i; 6139 6140 /* The UTA table only exists on 82576 hardware and newer */ 6141 if (hw->mac.type < e1000_82576) 6142 return; 6143 6144 /* we only need to do this if VMDq is enabled */ 6145 if (!adapter->vfs_allocated_count) 6146 return; 6147 6148 for (i = 0; i < hw->mac.uta_reg_count; i++) 6149 array_wr32(E1000_UTA, i, ~0); 6150} 6151 6152/** 6153 * igb_intr_msi - Interrupt Handler 6154 * @irq: interrupt number 6155 * @data: pointer to a network interface device structure 6156 **/ 6157static irqreturn_t igb_intr_msi(int irq, void *data) 6158{ 6159 struct igb_adapter *adapter = data; 6160 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6161 struct e1000_hw *hw = &adapter->hw; 6162 /* read ICR disables interrupts using IAM */ 6163 u32 icr = rd32(E1000_ICR); 6164 6165 igb_write_itr(q_vector); 6166 6167 if (icr & E1000_ICR_DRSTA) 6168 schedule_work(&adapter->reset_task); 6169 6170 if (icr & E1000_ICR_DOUTSYNC) { 6171 /* HW is reporting DMA is out of sync */ 6172 adapter->stats.doosync++; 6173 } 6174 6175 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6176 hw->mac.get_link_status = 1; 6177 if (!test_bit(__IGB_DOWN, &adapter->state)) 6178 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6179 } 6180 6181 if (icr & E1000_ICR_TS) { 6182 u32 tsicr = rd32(E1000_TSICR); 6183 6184 if (tsicr & E1000_TSICR_TXTS) { 6185 /* acknowledge the interrupt */ 6186 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6187 /* retrieve hardware timestamp */ 6188 schedule_work(&adapter->ptp_tx_work); 6189 } 6190 } 6191 6192 napi_schedule(&q_vector->napi); 6193 6194 return IRQ_HANDLED; 6195} 6196 6197/** 6198 * igb_intr - Legacy Interrupt Handler 6199 * @irq: interrupt number 6200 * @data: pointer to a network interface device structure 6201 **/ 6202static irqreturn_t igb_intr(int irq, void *data) 6203{ 6204 struct igb_adapter *adapter = data; 6205 struct igb_q_vector *q_vector = adapter->q_vector[0]; 6206 struct e1000_hw *hw = &adapter->hw; 6207 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No 6208 * need for the IMC write 6209 */ 6210 u32 icr = rd32(E1000_ICR); 6211 6212 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is 6213 * not set, then the adapter didn't send an interrupt 6214 */ 6215 if (!(icr & E1000_ICR_INT_ASSERTED)) 6216 return IRQ_NONE; 6217 6218 igb_write_itr(q_vector); 6219 6220 if (icr & E1000_ICR_DRSTA) 6221 schedule_work(&adapter->reset_task); 6222 6223 if (icr & E1000_ICR_DOUTSYNC) { 6224 /* HW is reporting DMA is out of sync */ 6225 adapter->stats.doosync++; 6226 } 6227 6228 if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) { 6229 hw->mac.get_link_status = 1; 6230 /* guard against interrupt when we're going down */ 6231 if (!test_bit(__IGB_DOWN, &adapter->state)) 6232 mod_timer(&adapter->watchdog_timer, jiffies + 1); 6233 } 6234 6235 if (icr & E1000_ICR_TS) { 6236 u32 tsicr = rd32(E1000_TSICR); 6237 6238 if (tsicr & E1000_TSICR_TXTS) { 6239 /* acknowledge the interrupt */ 6240 wr32(E1000_TSICR, E1000_TSICR_TXTS); 6241 /* retrieve hardware timestamp */ 6242 schedule_work(&adapter->ptp_tx_work); 6243 } 6244 } 6245 6246 napi_schedule(&q_vector->napi); 6247 6248 return IRQ_HANDLED; 6249} 6250 6251static void igb_ring_irq_enable(struct igb_q_vector *q_vector) 6252{ 6253 struct igb_adapter *adapter = q_vector->adapter; 6254 struct e1000_hw *hw = &adapter->hw; 6255 6256 if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) || 6257 (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) { 6258 if ((adapter->num_q_vectors == 1) && !adapter->vf_data) 6259 igb_set_itr(q_vector); 6260 else 6261 igb_update_ring_itr(q_vector); 6262 } 6263 6264 if (!test_bit(__IGB_DOWN, &adapter->state)) { 6265 if (adapter->flags & IGB_FLAG_HAS_MSIX) 6266 wr32(E1000_EIMS, q_vector->eims_value); 6267 else 6268 igb_irq_enable(adapter); 6269 } 6270} 6271 6272/** 6273 * igb_poll - NAPI Rx polling callback 6274 * @napi: napi polling structure 6275 * @budget: count of how many packets we should handle 6276 **/ 6277static int igb_poll(struct napi_struct *napi, int budget) 6278{ 6279 struct igb_q_vector *q_vector = container_of(napi, 6280 struct igb_q_vector, 6281 napi); 6282 bool clean_complete = true; 6283 6284#ifdef CONFIG_IGB_DCA 6285 if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED) 6286 igb_update_dca(q_vector); 6287#endif 6288 if (q_vector->tx.ring) 6289 clean_complete = igb_clean_tx_irq(q_vector); 6290 6291 if (q_vector->rx.ring) 6292 clean_complete &= igb_clean_rx_irq(q_vector, budget); 6293 6294 /* If all work not completed, return budget and keep polling */ 6295 if (!clean_complete) 6296 return budget; 6297 6298 /* If not enough Rx work done, exit the polling mode */ 6299 napi_complete(napi); 6300 igb_ring_irq_enable(q_vector); 6301 6302 return 0; 6303} 6304 6305/** 6306 * igb_clean_tx_irq - Reclaim resources after transmit completes 6307 * @q_vector: pointer to q_vector containing needed info 6308 * 6309 * returns true if ring is completely cleaned 6310 **/ 6311static bool igb_clean_tx_irq(struct igb_q_vector *q_vector) 6312{ 6313 struct igb_adapter *adapter = q_vector->adapter; 6314 struct igb_ring *tx_ring = q_vector->tx.ring; 6315 struct igb_tx_buffer *tx_buffer; 6316 union e1000_adv_tx_desc *tx_desc; 6317 unsigned int total_bytes = 0, total_packets = 0; 6318 unsigned int budget = q_vector->tx.work_limit; 6319 unsigned int i = tx_ring->next_to_clean; 6320 6321 if (test_bit(__IGB_DOWN, &adapter->state)) 6322 return true; 6323 6324 tx_buffer = &tx_ring->tx_buffer_info[i]; 6325 tx_desc = IGB_TX_DESC(tx_ring, i); 6326 i -= tx_ring->count; 6327 6328 do { 6329 union e1000_adv_tx_desc *eop_desc = tx_buffer->next_to_watch; 6330 6331 /* if next_to_watch is not set then there is no work pending */ 6332 if (!eop_desc) 6333 break; 6334 6335 /* prevent any other reads prior to eop_desc */ 6336 read_barrier_depends(); 6337 6338 /* if DD is not set pending work has not been completed */ 6339 if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD))) 6340 break; 6341 6342 /* clear next_to_watch to prevent false hangs */ 6343 tx_buffer->next_to_watch = NULL; 6344 6345 /* update the statistics for this packet */ 6346 total_bytes += tx_buffer->bytecount; 6347 total_packets += tx_buffer->gso_segs; 6348 6349 /* free the skb */ 6350 dev_kfree_skb_any(tx_buffer->skb); 6351 6352 /* unmap skb header data */ 6353 dma_unmap_single(tx_ring->dev, 6354 dma_unmap_addr(tx_buffer, dma), 6355 dma_unmap_len(tx_buffer, len), 6356 DMA_TO_DEVICE); 6357 6358 /* clear tx_buffer data */ 6359 tx_buffer->skb = NULL; 6360 dma_unmap_len_set(tx_buffer, len, 0); 6361 6362 /* clear last DMA location and unmap remaining buffers */ 6363 while (tx_desc != eop_desc) { 6364 tx_buffer++; 6365 tx_desc++; 6366 i++; 6367 if (unlikely(!i)) { 6368 i -= tx_ring->count; 6369 tx_buffer = tx_ring->tx_buffer_info; 6370 tx_desc = IGB_TX_DESC(tx_ring, 0); 6371 } 6372 6373 /* unmap any remaining paged data */ 6374 if (dma_unmap_len(tx_buffer, len)) { 6375 dma_unmap_page(tx_ring->dev, 6376 dma_unmap_addr(tx_buffer, dma), 6377 dma_unmap_len(tx_buffer, len), 6378 DMA_TO_DEVICE); 6379 dma_unmap_len_set(tx_buffer, len, 0); 6380 } 6381 } 6382 6383 /* move us one more past the eop_desc for start of next pkt */ 6384 tx_buffer++; 6385 tx_desc++; 6386 i++; 6387 if (unlikely(!i)) { 6388 i -= tx_ring->count; 6389 tx_buffer = tx_ring->tx_buffer_info; 6390 tx_desc = IGB_TX_DESC(tx_ring, 0); 6391 } 6392 6393 /* issue prefetch for next Tx descriptor */ 6394 prefetch(tx_desc); 6395 6396 /* update budget accounting */ 6397 budget--; 6398 } while (likely(budget)); 6399 6400 netdev_tx_completed_queue(txring_txq(tx_ring), 6401 total_packets, total_bytes); 6402 i += tx_ring->count; 6403 tx_ring->next_to_clean = i; 6404 u64_stats_update_begin(&tx_ring->tx_syncp); 6405 tx_ring->tx_stats.bytes += total_bytes; 6406 tx_ring->tx_stats.packets += total_packets; 6407 u64_stats_update_end(&tx_ring->tx_syncp); 6408 q_vector->tx.total_bytes += total_bytes; 6409 q_vector->tx.total_packets += total_packets; 6410 6411 if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) { 6412 struct e1000_hw *hw = &adapter->hw; 6413 6414 /* Detect a transmit hang in hardware, this serializes the 6415 * check with the clearing of time_stamp and movement of i 6416 */ 6417 clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags); 6418 if (tx_buffer->next_to_watch && 6419 time_after(jiffies, tx_buffer->time_stamp + 6420 (adapter->tx_timeout_factor * HZ)) && 6421 !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) { 6422 6423 /* detected Tx unit hang */ 6424 dev_err(tx_ring->dev, 6425 "Detected Tx Unit Hang\n" 6426 " Tx Queue <%d>\n" 6427 " TDH <%x>\n" 6428 " TDT <%x>\n" 6429 " next_to_use <%x>\n" 6430 " next_to_clean <%x>\n" 6431 "buffer_info[next_to_clean]\n" 6432 " time_stamp <%lx>\n" 6433 " next_to_watch <%p>\n" 6434 " jiffies <%lx>\n" 6435 " desc.status <%x>\n", 6436 tx_ring->queue_index, 6437 rd32(E1000_TDH(tx_ring->reg_idx)), 6438 readl(tx_ring->tail), 6439 tx_ring->next_to_use, 6440 tx_ring->next_to_clean, 6441 tx_buffer->time_stamp, 6442 tx_buffer->next_to_watch, 6443 jiffies, 6444 tx_buffer->next_to_watch->wb.status); 6445 netif_stop_subqueue(tx_ring->netdev, 6446 tx_ring->queue_index); 6447 6448 /* we are about to reset, no point in enabling stuff */ 6449 return true; 6450 } 6451 } 6452 6453#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2) 6454 if (unlikely(total_packets && 6455 netif_carrier_ok(tx_ring->netdev) && 6456 igb_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD)) { 6457 /* Make sure that anybody stopping the queue after this 6458 * sees the new next_to_clean. 6459 */ 6460 smp_mb(); 6461 if (__netif_subqueue_stopped(tx_ring->netdev, 6462 tx_ring->queue_index) && 6463 !(test_bit(__IGB_DOWN, &adapter->state))) { 6464 netif_wake_subqueue(tx_ring->netdev, 6465 tx_ring->queue_index); 6466 6467 u64_stats_update_begin(&tx_ring->tx_syncp); 6468 tx_ring->tx_stats.restart_queue++; 6469 u64_stats_update_end(&tx_ring->tx_syncp); 6470 } 6471 } 6472 6473 return !!budget; 6474} 6475 6476/** 6477 * igb_reuse_rx_page - page flip buffer and store it back on the ring 6478 * @rx_ring: rx descriptor ring to store buffers on 6479 * @old_buff: donor buffer to have page reused 6480 * 6481 * Synchronizes page for reuse by the adapter 6482 **/ 6483static void igb_reuse_rx_page(struct igb_ring *rx_ring, 6484 struct igb_rx_buffer *old_buff) 6485{ 6486 struct igb_rx_buffer *new_buff; 6487 u16 nta = rx_ring->next_to_alloc; 6488 6489 new_buff = &rx_ring->rx_buffer_info[nta]; 6490 6491 /* update, and store next to alloc */ 6492 nta++; 6493 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0; 6494 6495 /* transfer page from old buffer to new buffer */ 6496 memcpy(new_buff, old_buff, sizeof(struct igb_rx_buffer)); 6497 6498 /* sync the buffer for use by the device */ 6499 dma_sync_single_range_for_device(rx_ring->dev, old_buff->dma, 6500 old_buff->page_offset, 6501 IGB_RX_BUFSZ, 6502 DMA_FROM_DEVICE); 6503} 6504 6505static bool igb_can_reuse_rx_page(struct igb_rx_buffer *rx_buffer, 6506 struct page *page, 6507 unsigned int truesize) 6508{ 6509 /* avoid re-using remote pages */ 6510 if (unlikely(page_to_nid(page) != numa_node_id())) 6511 return false; 6512 6513#if (PAGE_SIZE < 8192) 6514 /* if we are only owner of page we can reuse it */ 6515 if (unlikely(page_count(page) != 1)) 6516 return false; 6517 6518 /* flip page offset to other buffer */ 6519 rx_buffer->page_offset ^= IGB_RX_BUFSZ; 6520 6521 /* since we are the only owner of the page and we need to 6522 * increment it, just set the value to 2 in order to avoid 6523 * an unnecessary locked operation 6524 */ 6525 atomic_set(&page->_count, 2); 6526#else 6527 /* move offset up to the next cache line */ 6528 rx_buffer->page_offset += truesize; 6529 6530 if (rx_buffer->page_offset > (PAGE_SIZE - IGB_RX_BUFSZ)) 6531 return false; 6532 6533 /* bump ref count on page before it is given to the stack */ 6534 get_page(page); 6535#endif 6536 6537 return true; 6538} 6539 6540/** 6541 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff 6542 * @rx_ring: rx descriptor ring to transact packets on 6543 * @rx_buffer: buffer containing page to add 6544 * @rx_desc: descriptor containing length of buffer written by hardware 6545 * @skb: sk_buff to place the data into 6546 * 6547 * This function will add the data contained in rx_buffer->page to the skb. 6548 * This is done either through a direct copy if the data in the buffer is 6549 * less than the skb header size, otherwise it will just attach the page as 6550 * a frag to the skb. 6551 * 6552 * The function will then update the page offset if necessary and return 6553 * true if the buffer can be reused by the adapter. 6554 **/ 6555static bool igb_add_rx_frag(struct igb_ring *rx_ring, 6556 struct igb_rx_buffer *rx_buffer, 6557 union e1000_adv_rx_desc *rx_desc, 6558 struct sk_buff *skb) 6559{ 6560 struct page *page = rx_buffer->page; 6561 unsigned int size = le16_to_cpu(rx_desc->wb.upper.length); 6562#if (PAGE_SIZE < 8192) 6563 unsigned int truesize = IGB_RX_BUFSZ; 6564#else 6565 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES); 6566#endif 6567 6568 if ((size <= IGB_RX_HDR_LEN) && !skb_is_nonlinear(skb)) { 6569 unsigned char *va = page_address(page) + rx_buffer->page_offset; 6570 6571 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6572 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6573 va += IGB_TS_HDR_LEN; 6574 size -= IGB_TS_HDR_LEN; 6575 } 6576 6577 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long))); 6578 6579 /* we can reuse buffer as-is, just make sure it is local */ 6580 if (likely(page_to_nid(page) == numa_node_id())) 6581 return true; 6582 6583 /* this page cannot be reused so discard it */ 6584 put_page(page); 6585 return false; 6586 } 6587 6588 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page, 6589 rx_buffer->page_offset, size, truesize); 6590 6591 return igb_can_reuse_rx_page(rx_buffer, page, truesize); 6592} 6593 6594static struct sk_buff *igb_fetch_rx_buffer(struct igb_ring *rx_ring, 6595 union e1000_adv_rx_desc *rx_desc, 6596 struct sk_buff *skb) 6597{ 6598 struct igb_rx_buffer *rx_buffer; 6599 struct page *page; 6600 6601 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean]; 6602 6603 page = rx_buffer->page; 6604 prefetchw(page); 6605 6606 if (likely(!skb)) { 6607 void *page_addr = page_address(page) + 6608 rx_buffer->page_offset; 6609 6610 /* prefetch first cache line of first page */ 6611 prefetch(page_addr); 6612#if L1_CACHE_BYTES < 128 6613 prefetch(page_addr + L1_CACHE_BYTES); 6614#endif 6615 6616 /* allocate a skb to store the frags */ 6617 skb = netdev_alloc_skb_ip_align(rx_ring->netdev, 6618 IGB_RX_HDR_LEN); 6619 if (unlikely(!skb)) { 6620 rx_ring->rx_stats.alloc_failed++; 6621 return NULL; 6622 } 6623 6624 /* we will be copying header into skb->data in 6625 * pskb_may_pull so it is in our interest to prefetch 6626 * it now to avoid a possible cache miss 6627 */ 6628 prefetchw(skb->data); 6629 } 6630 6631 /* we are reusing so sync this buffer for CPU use */ 6632 dma_sync_single_range_for_cpu(rx_ring->dev, 6633 rx_buffer->dma, 6634 rx_buffer->page_offset, 6635 IGB_RX_BUFSZ, 6636 DMA_FROM_DEVICE); 6637 6638 /* pull page into skb */ 6639 if (igb_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) { 6640 /* hand second half of page back to the ring */ 6641 igb_reuse_rx_page(rx_ring, rx_buffer); 6642 } else { 6643 /* we are not reusing the buffer so unmap it */ 6644 dma_unmap_page(rx_ring->dev, rx_buffer->dma, 6645 PAGE_SIZE, DMA_FROM_DEVICE); 6646 } 6647 6648 /* clear contents of rx_buffer */ 6649 rx_buffer->page = NULL; 6650 6651 return skb; 6652} 6653 6654static inline void igb_rx_checksum(struct igb_ring *ring, 6655 union e1000_adv_rx_desc *rx_desc, 6656 struct sk_buff *skb) 6657{ 6658 skb_checksum_none_assert(skb); 6659 6660 /* Ignore Checksum bit is set */ 6661 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM)) 6662 return; 6663 6664 /* Rx checksum disabled via ethtool */ 6665 if (!(ring->netdev->features & NETIF_F_RXCSUM)) 6666 return; 6667 6668 /* TCP/UDP checksum error bit is set */ 6669 if (igb_test_staterr(rx_desc, 6670 E1000_RXDEXT_STATERR_TCPE | 6671 E1000_RXDEXT_STATERR_IPE)) { 6672 /* work around errata with sctp packets where the TCPE aka 6673 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc) 6674 * packets, (aka let the stack check the crc32c) 6675 */ 6676 if (!((skb->len == 60) && 6677 test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) { 6678 u64_stats_update_begin(&ring->rx_syncp); 6679 ring->rx_stats.csum_err++; 6680 u64_stats_update_end(&ring->rx_syncp); 6681 } 6682 /* let the stack verify checksum errors */ 6683 return; 6684 } 6685 /* It must be a TCP or UDP packet with a valid checksum */ 6686 if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS | 6687 E1000_RXD_STAT_UDPCS)) 6688 skb->ip_summed = CHECKSUM_UNNECESSARY; 6689 6690 dev_dbg(ring->dev, "cksum success: bits %08X\n", 6691 le32_to_cpu(rx_desc->wb.upper.status_error)); 6692} 6693 6694static inline void igb_rx_hash(struct igb_ring *ring, 6695 union e1000_adv_rx_desc *rx_desc, 6696 struct sk_buff *skb) 6697{ 6698 if (ring->netdev->features & NETIF_F_RXHASH) 6699 skb_set_hash(skb, 6700 le32_to_cpu(rx_desc->wb.lower.hi_dword.rss), 6701 PKT_HASH_TYPE_L3); 6702} 6703 6704/** 6705 * igb_is_non_eop - process handling of non-EOP buffers 6706 * @rx_ring: Rx ring being processed 6707 * @rx_desc: Rx descriptor for current buffer 6708 * @skb: current socket buffer containing buffer in progress 6709 * 6710 * This function updates next to clean. If the buffer is an EOP buffer 6711 * this function exits returning false, otherwise it will place the 6712 * sk_buff in the next buffer to be chained and return true indicating 6713 * that this is in fact a non-EOP buffer. 6714 **/ 6715static bool igb_is_non_eop(struct igb_ring *rx_ring, 6716 union e1000_adv_rx_desc *rx_desc) 6717{ 6718 u32 ntc = rx_ring->next_to_clean + 1; 6719 6720 /* fetch, update, and store next to clean */ 6721 ntc = (ntc < rx_ring->count) ? ntc : 0; 6722 rx_ring->next_to_clean = ntc; 6723 6724 prefetch(IGB_RX_DESC(rx_ring, ntc)); 6725 6726 if (likely(igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP))) 6727 return false; 6728 6729 return true; 6730} 6731 6732/** 6733 * igb_get_headlen - determine size of header for LRO/GRO 6734 * @data: pointer to the start of the headers 6735 * @max_len: total length of section to find headers in 6736 * 6737 * This function is meant to determine the length of headers that will 6738 * be recognized by hardware for LRO, and GRO offloads. The main 6739 * motivation of doing this is to only perform one pull for IPv4 TCP 6740 * packets so that we can do basic things like calculating the gso_size 6741 * based on the average data per packet. 6742 **/ 6743static unsigned int igb_get_headlen(unsigned char *data, 6744 unsigned int max_len) 6745{ 6746 union { 6747 unsigned char *network; 6748 /* l2 headers */ 6749 struct ethhdr *eth; 6750 struct vlan_hdr *vlan; 6751 /* l3 headers */ 6752 struct iphdr *ipv4; 6753 struct ipv6hdr *ipv6; 6754 } hdr; 6755 __be16 protocol; 6756 u8 nexthdr = 0; /* default to not TCP */ 6757 u8 hlen; 6758 6759 /* this should never happen, but better safe than sorry */ 6760 if (max_len < ETH_HLEN) 6761 return max_len; 6762 6763 /* initialize network frame pointer */ 6764 hdr.network = data; 6765 6766 /* set first protocol and move network header forward */ 6767 protocol = hdr.eth->h_proto; 6768 hdr.network += ETH_HLEN; 6769 6770 /* handle any vlan tag if present */ 6771 if (protocol == htons(ETH_P_8021Q)) { 6772 if ((hdr.network - data) > (max_len - VLAN_HLEN)) 6773 return max_len; 6774 6775 protocol = hdr.vlan->h_vlan_encapsulated_proto; 6776 hdr.network += VLAN_HLEN; 6777 } 6778 6779 /* handle L3 protocols */ 6780 if (protocol == htons(ETH_P_IP)) { 6781 if ((hdr.network - data) > (max_len - sizeof(struct iphdr))) 6782 return max_len; 6783 6784 /* access ihl as a u8 to avoid unaligned access on ia64 */ 6785 hlen = (hdr.network[0] & 0x0F) << 2; 6786 6787 /* verify hlen meets minimum size requirements */ 6788 if (hlen < sizeof(struct iphdr)) 6789 return hdr.network - data; 6790 6791 /* record next protocol if header is present */ 6792 if (!(hdr.ipv4->frag_off & htons(IP_OFFSET))) 6793 nexthdr = hdr.ipv4->protocol; 6794 } else if (protocol == htons(ETH_P_IPV6)) { 6795 if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr))) 6796 return max_len; 6797 6798 /* record next protocol */ 6799 nexthdr = hdr.ipv6->nexthdr; 6800 hlen = sizeof(struct ipv6hdr); 6801 } else { 6802 return hdr.network - data; 6803 } 6804 6805 /* relocate pointer to start of L4 header */ 6806 hdr.network += hlen; 6807 6808 /* finally sort out TCP */ 6809 if (nexthdr == IPPROTO_TCP) { 6810 if ((hdr.network - data) > (max_len - sizeof(struct tcphdr))) 6811 return max_len; 6812 6813 /* access doff as a u8 to avoid unaligned access on ia64 */ 6814 hlen = (hdr.network[12] & 0xF0) >> 2; 6815 6816 /* verify hlen meets minimum size requirements */ 6817 if (hlen < sizeof(struct tcphdr)) 6818 return hdr.network - data; 6819 6820 hdr.network += hlen; 6821 } else if (nexthdr == IPPROTO_UDP) { 6822 if ((hdr.network - data) > (max_len - sizeof(struct udphdr))) 6823 return max_len; 6824 6825 hdr.network += sizeof(struct udphdr); 6826 } 6827 6828 /* If everything has gone correctly hdr.network should be the 6829 * data section of the packet and will be the end of the header. 6830 * If not then it probably represents the end of the last recognized 6831 * header. 6832 */ 6833 if ((hdr.network - data) < max_len) 6834 return hdr.network - data; 6835 else 6836 return max_len; 6837} 6838 6839/** 6840 * igb_pull_tail - igb specific version of skb_pull_tail 6841 * @rx_ring: rx descriptor ring packet is being transacted on 6842 * @rx_desc: pointer to the EOP Rx descriptor 6843 * @skb: pointer to current skb being adjusted 6844 * 6845 * This function is an igb specific version of __pskb_pull_tail. The 6846 * main difference between this version and the original function is that 6847 * this function can make several assumptions about the state of things 6848 * that allow for significant optimizations versus the standard function. 6849 * As a result we can do things like drop a frag and maintain an accurate 6850 * truesize for the skb. 6851 */ 6852static void igb_pull_tail(struct igb_ring *rx_ring, 6853 union e1000_adv_rx_desc *rx_desc, 6854 struct sk_buff *skb) 6855{ 6856 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0]; 6857 unsigned char *va; 6858 unsigned int pull_len; 6859 6860 /* it is valid to use page_address instead of kmap since we are 6861 * working with pages allocated out of the lomem pool per 6862 * alloc_page(GFP_ATOMIC) 6863 */ 6864 va = skb_frag_address(frag); 6865 6866 if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) { 6867 /* retrieve timestamp from buffer */ 6868 igb_ptp_rx_pktstamp(rx_ring->q_vector, va, skb); 6869 6870 /* update pointers to remove timestamp header */ 6871 skb_frag_size_sub(frag, IGB_TS_HDR_LEN); 6872 frag->page_offset += IGB_TS_HDR_LEN; 6873 skb->data_len -= IGB_TS_HDR_LEN; 6874 skb->len -= IGB_TS_HDR_LEN; 6875 6876 /* move va to start of packet data */ 6877 va += IGB_TS_HDR_LEN; 6878 } 6879 6880 /* we need the header to contain the greater of either ETH_HLEN or 6881 * 60 bytes if the skb->len is less than 60 for skb_pad. 6882 */ 6883 pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN); 6884 6885 /* align pull length to size of long to optimize memcpy performance */ 6886 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long))); 6887 6888 /* update all of the pointers */ 6889 skb_frag_size_sub(frag, pull_len); 6890 frag->page_offset += pull_len; 6891 skb->data_len -= pull_len; 6892 skb->tail += pull_len; 6893} 6894 6895/** 6896 * igb_cleanup_headers - Correct corrupted or empty headers 6897 * @rx_ring: rx descriptor ring packet is being transacted on 6898 * @rx_desc: pointer to the EOP Rx descriptor 6899 * @skb: pointer to current skb being fixed 6900 * 6901 * Address the case where we are pulling data in on pages only 6902 * and as such no data is present in the skb header. 6903 * 6904 * In addition if skb is not at least 60 bytes we need to pad it so that 6905 * it is large enough to qualify as a valid Ethernet frame. 6906 * 6907 * Returns true if an error was encountered and skb was freed. 6908 **/ 6909static bool igb_cleanup_headers(struct igb_ring *rx_ring, 6910 union e1000_adv_rx_desc *rx_desc, 6911 struct sk_buff *skb) 6912{ 6913 if (unlikely((igb_test_staterr(rx_desc, 6914 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) { 6915 struct net_device *netdev = rx_ring->netdev; 6916 if (!(netdev->features & NETIF_F_RXALL)) { 6917 dev_kfree_skb_any(skb); 6918 return true; 6919 } 6920 } 6921 6922 /* place header in linear portion of buffer */ 6923 if (skb_is_nonlinear(skb)) 6924 igb_pull_tail(rx_ring, rx_desc, skb); 6925 6926 /* if skb_pad returns an error the skb was freed */ 6927 if (unlikely(skb->len < 60)) { 6928 int pad_len = 60 - skb->len; 6929 6930 if (skb_pad(skb, pad_len)) 6931 return true; 6932 __skb_put(skb, pad_len); 6933 } 6934 6935 return false; 6936} 6937 6938/** 6939 * igb_process_skb_fields - Populate skb header fields from Rx descriptor 6940 * @rx_ring: rx descriptor ring packet is being transacted on 6941 * @rx_desc: pointer to the EOP Rx descriptor 6942 * @skb: pointer to current skb being populated 6943 * 6944 * This function checks the ring, descriptor, and packet information in 6945 * order to populate the hash, checksum, VLAN, timestamp, protocol, and 6946 * other fields within the skb. 6947 **/ 6948static void igb_process_skb_fields(struct igb_ring *rx_ring, 6949 union e1000_adv_rx_desc *rx_desc, 6950 struct sk_buff *skb) 6951{ 6952 struct net_device *dev = rx_ring->netdev; 6953 6954 igb_rx_hash(rx_ring, rx_desc, skb); 6955 6956 igb_rx_checksum(rx_ring, rx_desc, skb); 6957 6958 igb_ptp_rx_hwtstamp(rx_ring, rx_desc, skb); 6959 6960 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) && 6961 igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) { 6962 u16 vid; 6963 if (igb_test_staterr(rx_desc, E1000_RXDEXT_STATERR_LB) && 6964 test_bit(IGB_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags)) 6965 vid = be16_to_cpu(rx_desc->wb.upper.vlan); 6966 else 6967 vid = le16_to_cpu(rx_desc->wb.upper.vlan); 6968 6969 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid); 6970 } 6971 6972 skb_record_rx_queue(skb, rx_ring->queue_index); 6973 6974 skb->protocol = eth_type_trans(skb, rx_ring->netdev); 6975} 6976 6977static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, const int budget) 6978{ 6979 struct igb_ring *rx_ring = q_vector->rx.ring; 6980 struct sk_buff *skb = rx_ring->skb; 6981 unsigned int total_bytes = 0, total_packets = 0; 6982 u16 cleaned_count = igb_desc_unused(rx_ring); 6983 6984 while (likely(total_packets < budget)) { 6985 union e1000_adv_rx_desc *rx_desc; 6986 6987 /* return some buffers to hardware, one at a time is too slow */ 6988 if (cleaned_count >= IGB_RX_BUFFER_WRITE) { 6989 igb_alloc_rx_buffers(rx_ring, cleaned_count); 6990 cleaned_count = 0; 6991 } 6992 6993 rx_desc = IGB_RX_DESC(rx_ring, rx_ring->next_to_clean); 6994 6995 if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) 6996 break; 6997 6998 /* This memory barrier is needed to keep us from reading 6999 * any other fields out of the rx_desc until we know the 7000 * RXD_STAT_DD bit is set 7001 */ 7002 rmb(); 7003 7004 /* retrieve a buffer from the ring */ 7005 skb = igb_fetch_rx_buffer(rx_ring, rx_desc, skb); 7006 7007 /* exit if we failed to retrieve a buffer */ 7008 if (!skb) 7009 break; 7010 7011 cleaned_count++; 7012 7013 /* fetch next buffer in frame if non-eop */ 7014 if (igb_is_non_eop(rx_ring, rx_desc)) 7015 continue; 7016 7017 /* verify the packet layout is correct */ 7018 if (igb_cleanup_headers(rx_ring, rx_desc, skb)) { 7019 skb = NULL; 7020 continue; 7021 } 7022 7023 /* probably a little skewed due to removing CRC */ 7024 total_bytes += skb->len; 7025 7026 /* populate checksum, timestamp, VLAN, and protocol */ 7027 igb_process_skb_fields(rx_ring, rx_desc, skb); 7028 7029 napi_gro_receive(&q_vector->napi, skb); 7030 7031 /* reset skb pointer */ 7032 skb = NULL; 7033 7034 /* update budget accounting */ 7035 total_packets++; 7036 } 7037 7038 /* place incomplete frames back on ring for completion */ 7039 rx_ring->skb = skb; 7040 7041 u64_stats_update_begin(&rx_ring->rx_syncp); 7042 rx_ring->rx_stats.packets += total_packets; 7043 rx_ring->rx_stats.bytes += total_bytes; 7044 u64_stats_update_end(&rx_ring->rx_syncp); 7045 q_vector->rx.total_packets += total_packets; 7046 q_vector->rx.total_bytes += total_bytes; 7047 7048 if (cleaned_count) 7049 igb_alloc_rx_buffers(rx_ring, cleaned_count); 7050 7051 return (total_packets < budget); 7052} 7053 7054static bool igb_alloc_mapped_page(struct igb_ring *rx_ring, 7055 struct igb_rx_buffer *bi) 7056{ 7057 struct page *page = bi->page; 7058 dma_addr_t dma; 7059 7060 /* since we are recycling buffers we should seldom need to alloc */ 7061 if (likely(page)) 7062 return true; 7063 7064 /* alloc new page for storage */ 7065 page = __skb_alloc_page(GFP_ATOMIC | __GFP_COLD, NULL); 7066 if (unlikely(!page)) { 7067 rx_ring->rx_stats.alloc_failed++; 7068 return false; 7069 } 7070 7071 /* map page for use */ 7072 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 7073 7074 /* if mapping failed free memory back to system since 7075 * there isn't much point in holding memory we can't use 7076 */ 7077 if (dma_mapping_error(rx_ring->dev, dma)) { 7078 __free_page(page); 7079 7080 rx_ring->rx_stats.alloc_failed++; 7081 return false; 7082 } 7083 7084 bi->dma = dma; 7085 bi->page = page; 7086 bi->page_offset = 0; 7087 7088 return true; 7089} 7090 7091/** 7092 * igb_alloc_rx_buffers - Replace used receive buffers; packet split 7093 * @adapter: address of board private structure 7094 **/ 7095void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count) 7096{ 7097 union e1000_adv_rx_desc *rx_desc; 7098 struct igb_rx_buffer *bi; 7099 u16 i = rx_ring->next_to_use; 7100 7101 /* nothing to do */ 7102 if (!cleaned_count) 7103 return; 7104 7105 rx_desc = IGB_RX_DESC(rx_ring, i); 7106 bi = &rx_ring->rx_buffer_info[i]; 7107 i -= rx_ring->count; 7108 7109 do { 7110 if (!igb_alloc_mapped_page(rx_ring, bi)) 7111 break; 7112 7113 /* Refresh the desc even if buffer_addrs didn't change 7114 * because each write-back erases this info. 7115 */ 7116 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset); 7117 7118 rx_desc++; 7119 bi++; 7120 i++; 7121 if (unlikely(!i)) { 7122 rx_desc = IGB_RX_DESC(rx_ring, 0); 7123 bi = rx_ring->rx_buffer_info; 7124 i -= rx_ring->count; 7125 } 7126 7127 /* clear the hdr_addr for the next_to_use descriptor */ 7128 rx_desc->read.hdr_addr = 0; 7129 7130 cleaned_count--; 7131 } while (cleaned_count); 7132 7133 i += rx_ring->count; 7134 7135 if (rx_ring->next_to_use != i) { 7136 /* record the next descriptor to use */ 7137 rx_ring->next_to_use = i; 7138 7139 /* update next to alloc since we have filled the ring */ 7140 rx_ring->next_to_alloc = i; 7141 7142 /* Force memory writes to complete before letting h/w 7143 * know there are new descriptors to fetch. (Only 7144 * applicable for weak-ordered memory model archs, 7145 * such as IA-64). 7146 */ 7147 wmb(); 7148 writel(i, rx_ring->tail); 7149 } 7150} 7151 7152/** 7153 * igb_mii_ioctl - 7154 * @netdev: 7155 * @ifreq: 7156 * @cmd: 7157 **/ 7158static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7159{ 7160 struct igb_adapter *adapter = netdev_priv(netdev); 7161 struct mii_ioctl_data *data = if_mii(ifr); 7162 7163 if (adapter->hw.phy.media_type != e1000_media_type_copper) 7164 return -EOPNOTSUPP; 7165 7166 switch (cmd) { 7167 case SIOCGMIIPHY: 7168 data->phy_id = adapter->hw.phy.addr; 7169 break; 7170 case SIOCGMIIREG: 7171 if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, 7172 &data->val_out)) 7173 return -EIO; 7174 break; 7175 case SIOCSMIIREG: 7176 default: 7177 return -EOPNOTSUPP; 7178 } 7179 return 0; 7180} 7181 7182/** 7183 * igb_ioctl - 7184 * @netdev: 7185 * @ifreq: 7186 * @cmd: 7187 **/ 7188static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 7189{ 7190 switch (cmd) { 7191 case SIOCGMIIPHY: 7192 case SIOCGMIIREG: 7193 case SIOCSMIIREG: 7194 return igb_mii_ioctl(netdev, ifr, cmd); 7195 case SIOCGHWTSTAMP: 7196 return igb_ptp_get_ts_config(netdev, ifr); 7197 case SIOCSHWTSTAMP: 7198 return igb_ptp_set_ts_config(netdev, ifr); 7199 default: 7200 return -EOPNOTSUPP; 7201 } 7202} 7203 7204s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7205{ 7206 struct igb_adapter *adapter = hw->back; 7207 7208 if (pcie_capability_read_word(adapter->pdev, reg, value)) 7209 return -E1000_ERR_CONFIG; 7210 7211 return 0; 7212} 7213 7214s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value) 7215{ 7216 struct igb_adapter *adapter = hw->back; 7217 7218 if (pcie_capability_write_word(adapter->pdev, reg, *value)) 7219 return -E1000_ERR_CONFIG; 7220 7221 return 0; 7222} 7223 7224static void igb_vlan_mode(struct net_device *netdev, netdev_features_t features) 7225{ 7226 struct igb_adapter *adapter = netdev_priv(netdev); 7227 struct e1000_hw *hw = &adapter->hw; 7228 u32 ctrl, rctl; 7229 bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX); 7230 7231 if (enable) { 7232 /* enable VLAN tag insert/strip */ 7233 ctrl = rd32(E1000_CTRL); 7234 ctrl |= E1000_CTRL_VME; 7235 wr32(E1000_CTRL, ctrl); 7236 7237 /* Disable CFI check */ 7238 rctl = rd32(E1000_RCTL); 7239 rctl &= ~E1000_RCTL_CFIEN; 7240 wr32(E1000_RCTL, rctl); 7241 } else { 7242 /* disable VLAN tag insert/strip */ 7243 ctrl = rd32(E1000_CTRL); 7244 ctrl &= ~E1000_CTRL_VME; 7245 wr32(E1000_CTRL, ctrl); 7246 } 7247 7248 igb_rlpml_set(adapter); 7249} 7250 7251static int igb_vlan_rx_add_vid(struct net_device *netdev, 7252 __be16 proto, u16 vid) 7253{ 7254 struct igb_adapter *adapter = netdev_priv(netdev); 7255 struct e1000_hw *hw = &adapter->hw; 7256 int pf_id = adapter->vfs_allocated_count; 7257 7258 /* attempt to add filter to vlvf array */ 7259 igb_vlvf_set(adapter, vid, true, pf_id); 7260 7261 /* add the filter since PF can receive vlans w/o entry in vlvf */ 7262 igb_vfta_set(hw, vid, true); 7263 7264 set_bit(vid, adapter->active_vlans); 7265 7266 return 0; 7267} 7268 7269static int igb_vlan_rx_kill_vid(struct net_device *netdev, 7270 __be16 proto, u16 vid) 7271{ 7272 struct igb_adapter *adapter = netdev_priv(netdev); 7273 struct e1000_hw *hw = &adapter->hw; 7274 int pf_id = adapter->vfs_allocated_count; 7275 s32 err; 7276 7277 /* remove vlan from VLVF table array */ 7278 err = igb_vlvf_set(adapter, vid, false, pf_id); 7279 7280 /* if vid was not present in VLVF just remove it from table */ 7281 if (err) 7282 igb_vfta_set(hw, vid, false); 7283 7284 clear_bit(vid, adapter->active_vlans); 7285 7286 return 0; 7287} 7288 7289static void igb_restore_vlan(struct igb_adapter *adapter) 7290{ 7291 u16 vid; 7292 7293 igb_vlan_mode(adapter->netdev, adapter->netdev->features); 7294 7295 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID) 7296 igb_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid); 7297} 7298 7299int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx) 7300{ 7301 struct pci_dev *pdev = adapter->pdev; 7302 struct e1000_mac_info *mac = &adapter->hw.mac; 7303 7304 mac->autoneg = 0; 7305 7306 /* Make sure dplx is at most 1 bit and lsb of speed is not set 7307 * for the switch() below to work 7308 */ 7309 if ((spd & 1) || (dplx & ~1)) 7310 goto err_inval; 7311 7312 /* Fiber NIC's only allow 1000 gbps Full duplex 7313 * and 100Mbps Full duplex for 100baseFx sfp 7314 */ 7315 if (adapter->hw.phy.media_type == e1000_media_type_internal_serdes) { 7316 switch (spd + dplx) { 7317 case SPEED_10 + DUPLEX_HALF: 7318 case SPEED_10 + DUPLEX_FULL: 7319 case SPEED_100 + DUPLEX_HALF: 7320 goto err_inval; 7321 default: 7322 break; 7323 } 7324 } 7325 7326 switch (spd + dplx) { 7327 case SPEED_10 + DUPLEX_HALF: 7328 mac->forced_speed_duplex = ADVERTISE_10_HALF; 7329 break; 7330 case SPEED_10 + DUPLEX_FULL: 7331 mac->forced_speed_duplex = ADVERTISE_10_FULL; 7332 break; 7333 case SPEED_100 + DUPLEX_HALF: 7334 mac->forced_speed_duplex = ADVERTISE_100_HALF; 7335 break; 7336 case SPEED_100 + DUPLEX_FULL: 7337 mac->forced_speed_duplex = ADVERTISE_100_FULL; 7338 break; 7339 case SPEED_1000 + DUPLEX_FULL: 7340 mac->autoneg = 1; 7341 adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL; 7342 break; 7343 case SPEED_1000 + DUPLEX_HALF: /* not supported */ 7344 default: 7345 goto err_inval; 7346 } 7347 7348 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */ 7349 adapter->hw.phy.mdix = AUTO_ALL_MODES; 7350 7351 return 0; 7352 7353err_inval: 7354 dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n"); 7355 return -EINVAL; 7356} 7357 7358static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake, 7359 bool runtime) 7360{ 7361 struct net_device *netdev = pci_get_drvdata(pdev); 7362 struct igb_adapter *adapter = netdev_priv(netdev); 7363 struct e1000_hw *hw = &adapter->hw; 7364 u32 ctrl, rctl, status; 7365 u32 wufc = runtime ? E1000_WUFC_LNKC : adapter->wol; 7366#ifdef CONFIG_PM 7367 int retval = 0; 7368#endif 7369 7370 netif_device_detach(netdev); 7371 7372 if (netif_running(netdev)) 7373 __igb_close(netdev, true); 7374 7375 igb_clear_interrupt_scheme(adapter); 7376 7377#ifdef CONFIG_PM 7378 retval = pci_save_state(pdev); 7379 if (retval) 7380 return retval; 7381#endif 7382 7383 status = rd32(E1000_STATUS); 7384 if (status & E1000_STATUS_LU) 7385 wufc &= ~E1000_WUFC_LNKC; 7386 7387 if (wufc) { 7388 igb_setup_rctl(adapter); 7389 igb_set_rx_mode(netdev); 7390 7391 /* turn on all-multi mode if wake on multicast is enabled */ 7392 if (wufc & E1000_WUFC_MC) { 7393 rctl = rd32(E1000_RCTL); 7394 rctl |= E1000_RCTL_MPE; 7395 wr32(E1000_RCTL, rctl); 7396 } 7397 7398 ctrl = rd32(E1000_CTRL); 7399 /* advertise wake from D3Cold */ 7400 #define E1000_CTRL_ADVD3WUC 0x00100000 7401 /* phy power management enable */ 7402 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 7403 ctrl |= E1000_CTRL_ADVD3WUC; 7404 wr32(E1000_CTRL, ctrl); 7405 7406 /* Allow time for pending master requests to run */ 7407 igb_disable_pcie_master(hw); 7408 7409 wr32(E1000_WUC, E1000_WUC_PME_EN); 7410 wr32(E1000_WUFC, wufc); 7411 } else { 7412 wr32(E1000_WUC, 0); 7413 wr32(E1000_WUFC, 0); 7414 } 7415 7416 *enable_wake = wufc || adapter->en_mng_pt; 7417 if (!*enable_wake) 7418 igb_power_down_link(adapter); 7419 else 7420 igb_power_up_link(adapter); 7421 7422 /* Release control of h/w to f/w. If f/w is AMT enabled, this 7423 * would have already happened in close and is redundant. 7424 */ 7425 igb_release_hw_control(adapter); 7426 7427 pci_disable_device(pdev); 7428 7429 return 0; 7430} 7431 7432#ifdef CONFIG_PM 7433#ifdef CONFIG_PM_SLEEP 7434static int igb_suspend(struct device *dev) 7435{ 7436 int retval; 7437 bool wake; 7438 struct pci_dev *pdev = to_pci_dev(dev); 7439 7440 retval = __igb_shutdown(pdev, &wake, 0); 7441 if (retval) 7442 return retval; 7443 7444 if (wake) { 7445 pci_prepare_to_sleep(pdev); 7446 } else { 7447 pci_wake_from_d3(pdev, false); 7448 pci_set_power_state(pdev, PCI_D3hot); 7449 } 7450 7451 return 0; 7452} 7453#endif /* CONFIG_PM_SLEEP */ 7454 7455static int igb_resume(struct device *dev) 7456{ 7457 struct pci_dev *pdev = to_pci_dev(dev); 7458 struct net_device *netdev = pci_get_drvdata(pdev); 7459 struct igb_adapter *adapter = netdev_priv(netdev); 7460 struct e1000_hw *hw = &adapter->hw; 7461 u32 err; 7462 7463 pci_set_power_state(pdev, PCI_D0); 7464 pci_restore_state(pdev); 7465 pci_save_state(pdev); 7466 7467 err = pci_enable_device_mem(pdev); 7468 if (err) { 7469 dev_err(&pdev->dev, 7470 "igb: Cannot enable PCI device from suspend\n"); 7471 return err; 7472 } 7473 pci_set_master(pdev); 7474 7475 pci_enable_wake(pdev, PCI_D3hot, 0); 7476 pci_enable_wake(pdev, PCI_D3cold, 0); 7477 7478 if (igb_init_interrupt_scheme(adapter, true)) { 7479 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7480 return -ENOMEM; 7481 } 7482 7483 igb_reset(adapter); 7484 7485 /* let the f/w know that the h/w is now under the control of the 7486 * driver. 7487 */ 7488 igb_get_hw_control(adapter); 7489 7490 wr32(E1000_WUS, ~0); 7491 7492 if (netdev->flags & IFF_UP) { 7493 rtnl_lock(); 7494 err = __igb_open(netdev, true); 7495 rtnl_unlock(); 7496 if (err) 7497 return err; 7498 } 7499 7500 netif_device_attach(netdev); 7501 return 0; 7502} 7503 7504#ifdef CONFIG_PM_RUNTIME 7505static int igb_runtime_idle(struct device *dev) 7506{ 7507 struct pci_dev *pdev = to_pci_dev(dev); 7508 struct net_device *netdev = pci_get_drvdata(pdev); 7509 struct igb_adapter *adapter = netdev_priv(netdev); 7510 7511 if (!igb_has_link(adapter)) 7512 pm_schedule_suspend(dev, MSEC_PER_SEC * 5); 7513 7514 return -EBUSY; 7515} 7516 7517static int igb_runtime_suspend(struct device *dev) 7518{ 7519 struct pci_dev *pdev = to_pci_dev(dev); 7520 int retval; 7521 bool wake; 7522 7523 retval = __igb_shutdown(pdev, &wake, 1); 7524 if (retval) 7525 return retval; 7526 7527 if (wake) { 7528 pci_prepare_to_sleep(pdev); 7529 } else { 7530 pci_wake_from_d3(pdev, false); 7531 pci_set_power_state(pdev, PCI_D3hot); 7532 } 7533 7534 return 0; 7535} 7536 7537static int igb_runtime_resume(struct device *dev) 7538{ 7539 return igb_resume(dev); 7540} 7541#endif /* CONFIG_PM_RUNTIME */ 7542#endif 7543 7544static void igb_shutdown(struct pci_dev *pdev) 7545{ 7546 bool wake; 7547 7548 __igb_shutdown(pdev, &wake, 0); 7549 7550 if (system_state == SYSTEM_POWER_OFF) { 7551 pci_wake_from_d3(pdev, wake); 7552 pci_set_power_state(pdev, PCI_D3hot); 7553 } 7554} 7555 7556#ifdef CONFIG_PCI_IOV 7557static int igb_sriov_reinit(struct pci_dev *dev) 7558{ 7559 struct net_device *netdev = pci_get_drvdata(dev); 7560 struct igb_adapter *adapter = netdev_priv(netdev); 7561 struct pci_dev *pdev = adapter->pdev; 7562 7563 rtnl_lock(); 7564 7565 if (netif_running(netdev)) 7566 igb_close(netdev); 7567 7568 igb_clear_interrupt_scheme(adapter); 7569 7570 igb_init_queue_configuration(adapter); 7571 7572 if (igb_init_interrupt_scheme(adapter, true)) { 7573 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 7574 return -ENOMEM; 7575 } 7576 7577 if (netif_running(netdev)) 7578 igb_open(netdev); 7579 7580 rtnl_unlock(); 7581 7582 return 0; 7583} 7584 7585static int igb_pci_disable_sriov(struct pci_dev *dev) 7586{ 7587 int err = igb_disable_sriov(dev); 7588 7589 if (!err) 7590 err = igb_sriov_reinit(dev); 7591 7592 return err; 7593} 7594 7595static int igb_pci_enable_sriov(struct pci_dev *dev, int num_vfs) 7596{ 7597 int err = igb_enable_sriov(dev, num_vfs); 7598 7599 if (err) 7600 goto out; 7601 7602 err = igb_sriov_reinit(dev); 7603 if (!err) 7604 return num_vfs; 7605 7606out: 7607 return err; 7608} 7609 7610#endif 7611static int igb_pci_sriov_configure(struct pci_dev *dev, int num_vfs) 7612{ 7613#ifdef CONFIG_PCI_IOV 7614 if (num_vfs == 0) 7615 return igb_pci_disable_sriov(dev); 7616 else 7617 return igb_pci_enable_sriov(dev, num_vfs); 7618#endif 7619 return 0; 7620} 7621 7622#ifdef CONFIG_NET_POLL_CONTROLLER 7623/* Polling 'interrupt' - used by things like netconsole to send skbs 7624 * without having to re-enable interrupts. It's not called while 7625 * the interrupt routine is executing. 7626 */ 7627static void igb_netpoll(struct net_device *netdev) 7628{ 7629 struct igb_adapter *adapter = netdev_priv(netdev); 7630 struct e1000_hw *hw = &adapter->hw; 7631 struct igb_q_vector *q_vector; 7632 int i; 7633 7634 for (i = 0; i < adapter->num_q_vectors; i++) { 7635 q_vector = adapter->q_vector[i]; 7636 if (adapter->flags & IGB_FLAG_HAS_MSIX) 7637 wr32(E1000_EIMC, q_vector->eims_value); 7638 else 7639 igb_irq_disable(adapter); 7640 napi_schedule(&q_vector->napi); 7641 } 7642} 7643#endif /* CONFIG_NET_POLL_CONTROLLER */ 7644 7645/** 7646 * igb_io_error_detected - called when PCI error is detected 7647 * @pdev: Pointer to PCI device 7648 * @state: The current pci connection state 7649 * 7650 * This function is called after a PCI bus error affecting 7651 * this device has been detected. 7652 **/ 7653static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev, 7654 pci_channel_state_t state) 7655{ 7656 struct net_device *netdev = pci_get_drvdata(pdev); 7657 struct igb_adapter *adapter = netdev_priv(netdev); 7658 7659 netif_device_detach(netdev); 7660 7661 if (state == pci_channel_io_perm_failure) 7662 return PCI_ERS_RESULT_DISCONNECT; 7663 7664 if (netif_running(netdev)) 7665 igb_down(adapter); 7666 pci_disable_device(pdev); 7667 7668 /* Request a slot slot reset. */ 7669 return PCI_ERS_RESULT_NEED_RESET; 7670} 7671 7672/** 7673 * igb_io_slot_reset - called after the pci bus has been reset. 7674 * @pdev: Pointer to PCI device 7675 * 7676 * Restart the card from scratch, as if from a cold-boot. Implementation 7677 * resembles the first-half of the igb_resume routine. 7678 **/ 7679static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev) 7680{ 7681 struct net_device *netdev = pci_get_drvdata(pdev); 7682 struct igb_adapter *adapter = netdev_priv(netdev); 7683 struct e1000_hw *hw = &adapter->hw; 7684 pci_ers_result_t result; 7685 int err; 7686 7687 if (pci_enable_device_mem(pdev)) { 7688 dev_err(&pdev->dev, 7689 "Cannot re-enable PCI device after reset.\n"); 7690 result = PCI_ERS_RESULT_DISCONNECT; 7691 } else { 7692 pci_set_master(pdev); 7693 pci_restore_state(pdev); 7694 pci_save_state(pdev); 7695 7696 pci_enable_wake(pdev, PCI_D3hot, 0); 7697 pci_enable_wake(pdev, PCI_D3cold, 0); 7698 7699 igb_reset(adapter); 7700 wr32(E1000_WUS, ~0); 7701 result = PCI_ERS_RESULT_RECOVERED; 7702 } 7703 7704 err = pci_cleanup_aer_uncorrect_error_status(pdev); 7705 if (err) { 7706 dev_err(&pdev->dev, 7707 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", 7708 err); 7709 /* non-fatal, continue */ 7710 } 7711 7712 return result; 7713} 7714 7715/** 7716 * igb_io_resume - called when traffic can start flowing again. 7717 * @pdev: Pointer to PCI device 7718 * 7719 * This callback is called when the error recovery driver tells us that 7720 * its OK to resume normal operation. Implementation resembles the 7721 * second-half of the igb_resume routine. 7722 */ 7723static void igb_io_resume(struct pci_dev *pdev) 7724{ 7725 struct net_device *netdev = pci_get_drvdata(pdev); 7726 struct igb_adapter *adapter = netdev_priv(netdev); 7727 7728 if (netif_running(netdev)) { 7729 if (igb_up(adapter)) { 7730 dev_err(&pdev->dev, "igb_up failed after reset\n"); 7731 return; 7732 } 7733 } 7734 7735 netif_device_attach(netdev); 7736 7737 /* let the f/w know that the h/w is now under the control of the 7738 * driver. 7739 */ 7740 igb_get_hw_control(adapter); 7741} 7742 7743static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index, 7744 u8 qsel) 7745{ 7746 u32 rar_low, rar_high; 7747 struct e1000_hw *hw = &adapter->hw; 7748 7749 /* HW expects these in little endian so we reverse the byte order 7750 * from network order (big endian) to little endian 7751 */ 7752 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) | 7753 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 7754 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8)); 7755 7756 /* Indicate to hardware the Address is Valid. */ 7757 rar_high |= E1000_RAH_AV; 7758 7759 if (hw->mac.type == e1000_82575) 7760 rar_high |= E1000_RAH_POOL_1 * qsel; 7761 else 7762 rar_high |= E1000_RAH_POOL_1 << qsel; 7763 7764 wr32(E1000_RAL(index), rar_low); 7765 wrfl(); 7766 wr32(E1000_RAH(index), rar_high); 7767 wrfl(); 7768} 7769 7770static int igb_set_vf_mac(struct igb_adapter *adapter, 7771 int vf, unsigned char *mac_addr) 7772{ 7773 struct e1000_hw *hw = &adapter->hw; 7774 /* VF MAC addresses start at end of receive addresses and moves 7775 * towards the first, as a result a collision should not be possible 7776 */ 7777 int rar_entry = hw->mac.rar_entry_count - (vf + 1); 7778 7779 memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN); 7780 7781 igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf); 7782 7783 return 0; 7784} 7785 7786static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 7787{ 7788 struct igb_adapter *adapter = netdev_priv(netdev); 7789 if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count)) 7790 return -EINVAL; 7791 adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC; 7792 dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf); 7793 dev_info(&adapter->pdev->dev, 7794 "Reload the VF driver to make this change effective."); 7795 if (test_bit(__IGB_DOWN, &adapter->state)) { 7796 dev_warn(&adapter->pdev->dev, 7797 "The VF MAC address has been set, but the PF device is not up.\n"); 7798 dev_warn(&adapter->pdev->dev, 7799 "Bring the PF device up before attempting to use the VF device.\n"); 7800 } 7801 return igb_set_vf_mac(adapter, vf, mac); 7802} 7803 7804static int igb_link_mbps(int internal_link_speed) 7805{ 7806 switch (internal_link_speed) { 7807 case SPEED_100: 7808 return 100; 7809 case SPEED_1000: 7810 return 1000; 7811 default: 7812 return 0; 7813 } 7814} 7815 7816static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate, 7817 int link_speed) 7818{ 7819 int rf_dec, rf_int; 7820 u32 bcnrc_val; 7821 7822 if (tx_rate != 0) { 7823 /* Calculate the rate factor values to set */ 7824 rf_int = link_speed / tx_rate; 7825 rf_dec = (link_speed - (rf_int * tx_rate)); 7826 rf_dec = (rf_dec * (1 << E1000_RTTBCNRC_RF_INT_SHIFT)) / 7827 tx_rate; 7828 7829 bcnrc_val = E1000_RTTBCNRC_RS_ENA; 7830 bcnrc_val |= ((rf_int << E1000_RTTBCNRC_RF_INT_SHIFT) & 7831 E1000_RTTBCNRC_RF_INT_MASK); 7832 bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK); 7833 } else { 7834 bcnrc_val = 0; 7835 } 7836 7837 wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */ 7838 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM 7839 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported. 7840 */ 7841 wr32(E1000_RTTBCNRM, 0x14); 7842 wr32(E1000_RTTBCNRC, bcnrc_val); 7843} 7844 7845static void igb_check_vf_rate_limit(struct igb_adapter *adapter) 7846{ 7847 int actual_link_speed, i; 7848 bool reset_rate = false; 7849 7850 /* VF TX rate limit was not set or not supported */ 7851 if ((adapter->vf_rate_link_speed == 0) || 7852 (adapter->hw.mac.type != e1000_82576)) 7853 return; 7854 7855 actual_link_speed = igb_link_mbps(adapter->link_speed); 7856 if (actual_link_speed != adapter->vf_rate_link_speed) { 7857 reset_rate = true; 7858 adapter->vf_rate_link_speed = 0; 7859 dev_info(&adapter->pdev->dev, 7860 "Link speed has been changed. VF Transmit rate is disabled\n"); 7861 } 7862 7863 for (i = 0; i < adapter->vfs_allocated_count; i++) { 7864 if (reset_rate) 7865 adapter->vf_data[i].tx_rate = 0; 7866 7867 igb_set_vf_rate_limit(&adapter->hw, i, 7868 adapter->vf_data[i].tx_rate, 7869 actual_link_speed); 7870 } 7871} 7872 7873static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate) 7874{ 7875 struct igb_adapter *adapter = netdev_priv(netdev); 7876 struct e1000_hw *hw = &adapter->hw; 7877 int actual_link_speed; 7878 7879 if (hw->mac.type != e1000_82576) 7880 return -EOPNOTSUPP; 7881 7882 actual_link_speed = igb_link_mbps(adapter->link_speed); 7883 if ((vf >= adapter->vfs_allocated_count) || 7884 (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) || 7885 (tx_rate < 0) || (tx_rate > actual_link_speed)) 7886 return -EINVAL; 7887 7888 adapter->vf_rate_link_speed = actual_link_speed; 7889 adapter->vf_data[vf].tx_rate = (u16)tx_rate; 7890 igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed); 7891 7892 return 0; 7893} 7894 7895static int igb_ndo_set_vf_spoofchk(struct net_device *netdev, int vf, 7896 bool setting) 7897{ 7898 struct igb_adapter *adapter = netdev_priv(netdev); 7899 struct e1000_hw *hw = &adapter->hw; 7900 u32 reg_val, reg_offset; 7901 7902 if (!adapter->vfs_allocated_count) 7903 return -EOPNOTSUPP; 7904 7905 if (vf >= adapter->vfs_allocated_count) 7906 return -EINVAL; 7907 7908 reg_offset = (hw->mac.type == e1000_82576) ? E1000_DTXSWC : E1000_TXSWC; 7909 reg_val = rd32(reg_offset); 7910 if (setting) 7911 reg_val |= ((1 << vf) | 7912 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7913 else 7914 reg_val &= ~((1 << vf) | 7915 (1 << (vf + E1000_DTXSWC_VLAN_SPOOF_SHIFT))); 7916 wr32(reg_offset, reg_val); 7917 7918 adapter->vf_data[vf].spoofchk_enabled = setting; 7919 return E1000_SUCCESS; 7920} 7921 7922static int igb_ndo_get_vf_config(struct net_device *netdev, 7923 int vf, struct ifla_vf_info *ivi) 7924{ 7925 struct igb_adapter *adapter = netdev_priv(netdev); 7926 if (vf >= adapter->vfs_allocated_count) 7927 return -EINVAL; 7928 ivi->vf = vf; 7929 memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN); 7930 ivi->tx_rate = adapter->vf_data[vf].tx_rate; 7931 ivi->vlan = adapter->vf_data[vf].pf_vlan; 7932 ivi->qos = adapter->vf_data[vf].pf_qos; 7933 ivi->spoofchk = adapter->vf_data[vf].spoofchk_enabled; 7934 return 0; 7935} 7936 7937static void igb_vmm_control(struct igb_adapter *adapter) 7938{ 7939 struct e1000_hw *hw = &adapter->hw; 7940 u32 reg; 7941 7942 switch (hw->mac.type) { 7943 case e1000_82575: 7944 case e1000_i210: 7945 case e1000_i211: 7946 case e1000_i354: 7947 default: 7948 /* replication is not supported for 82575 */ 7949 return; 7950 case e1000_82576: 7951 /* notify HW that the MAC is adding vlan tags */ 7952 reg = rd32(E1000_DTXCTL); 7953 reg |= E1000_DTXCTL_VLAN_ADDED; 7954 wr32(E1000_DTXCTL, reg); 7955 case e1000_82580: 7956 /* enable replication vlan tag stripping */ 7957 reg = rd32(E1000_RPLOLR); 7958 reg |= E1000_RPLOLR_STRVLAN; 7959 wr32(E1000_RPLOLR, reg); 7960 case e1000_i350: 7961 /* none of the above registers are supported by i350 */ 7962 break; 7963 } 7964 7965 if (adapter->vfs_allocated_count) { 7966 igb_vmdq_set_loopback_pf(hw, true); 7967 igb_vmdq_set_replication_pf(hw, true); 7968 igb_vmdq_set_anti_spoofing_pf(hw, true, 7969 adapter->vfs_allocated_count); 7970 } else { 7971 igb_vmdq_set_loopback_pf(hw, false); 7972 igb_vmdq_set_replication_pf(hw, false); 7973 } 7974} 7975 7976static void igb_init_dmac(struct igb_adapter *adapter, u32 pba) 7977{ 7978 struct e1000_hw *hw = &adapter->hw; 7979 u32 dmac_thr; 7980 u16 hwm; 7981 7982 if (hw->mac.type > e1000_82580) { 7983 if (adapter->flags & IGB_FLAG_DMAC) { 7984 u32 reg; 7985 7986 /* force threshold to 0. */ 7987 wr32(E1000_DMCTXTH, 0); 7988 7989 /* DMA Coalescing high water mark needs to be greater 7990 * than the Rx threshold. Set hwm to PBA - max frame 7991 * size in 16B units, capping it at PBA - 6KB. 7992 */ 7993 hwm = 64 * pba - adapter->max_frame_size / 16; 7994 if (hwm < 64 * (pba - 6)) 7995 hwm = 64 * (pba - 6); 7996 reg = rd32(E1000_FCRTC); 7997 reg &= ~E1000_FCRTC_RTH_COAL_MASK; 7998 reg |= ((hwm << E1000_FCRTC_RTH_COAL_SHIFT) 7999 & E1000_FCRTC_RTH_COAL_MASK); 8000 wr32(E1000_FCRTC, reg); 8001 8002 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max 8003 * frame size, capping it at PBA - 10KB. 8004 */ 8005 dmac_thr = pba - adapter->max_frame_size / 512; 8006 if (dmac_thr < pba - 10) 8007 dmac_thr = pba - 10; 8008 reg = rd32(E1000_DMACR); 8009 reg &= ~E1000_DMACR_DMACTHR_MASK; 8010 reg |= ((dmac_thr << E1000_DMACR_DMACTHR_SHIFT) 8011 & E1000_DMACR_DMACTHR_MASK); 8012 8013 /* transition to L0x or L1 if available..*/ 8014 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK); 8015 8016 /* watchdog timer= +-1000 usec in 32usec intervals */ 8017 reg |= (1000 >> 5); 8018 8019 /* Disable BMC-to-OS Watchdog Enable */ 8020 if (hw->mac.type != e1000_i354) 8021 reg &= ~E1000_DMACR_DC_BMC2OSW_EN; 8022 8023 wr32(E1000_DMACR, reg); 8024 8025 /* no lower threshold to disable 8026 * coalescing(smart fifb)-UTRESH=0 8027 */ 8028 wr32(E1000_DMCRTRH, 0); 8029 8030 reg = (IGB_DMCTLX_DCFLUSH_DIS | 0x4); 8031 8032 wr32(E1000_DMCTLX, reg); 8033 8034 /* free space in tx packet buffer to wake from 8035 * DMA coal 8036 */ 8037 wr32(E1000_DMCTXTH, (IGB_MIN_TXPBSIZE - 8038 (IGB_TX_BUF_4096 + adapter->max_frame_size)) >> 6); 8039 8040 /* make low power state decision controlled 8041 * by DMA coal 8042 */ 8043 reg = rd32(E1000_PCIEMISC); 8044 reg &= ~E1000_PCIEMISC_LX_DECISION; 8045 wr32(E1000_PCIEMISC, reg); 8046 } /* endif adapter->dmac is not disabled */ 8047 } else if (hw->mac.type == e1000_82580) { 8048 u32 reg = rd32(E1000_PCIEMISC); 8049 wr32(E1000_PCIEMISC, reg & ~E1000_PCIEMISC_LX_DECISION); 8050 wr32(E1000_DMACR, 0); 8051 } 8052} 8053 8054/** 8055 * igb_read_i2c_byte - Reads 8 bit word over I2C 8056 * @hw: pointer to hardware structure 8057 * @byte_offset: byte offset to read 8058 * @dev_addr: device address 8059 * @data: value read 8060 * 8061 * Performs byte read operation over I2C interface at 8062 * a specified device address. 8063 **/ 8064s32 igb_read_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8065 u8 dev_addr, u8 *data) 8066{ 8067 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8068 struct i2c_client *this_client = adapter->i2c_client; 8069 s32 status; 8070 u16 swfw_mask = 0; 8071 8072 if (!this_client) 8073 return E1000_ERR_I2C; 8074 8075 swfw_mask = E1000_SWFW_PHY0_SM; 8076 8077 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) 8078 != E1000_SUCCESS) 8079 return E1000_ERR_SWFW_SYNC; 8080 8081 status = i2c_smbus_read_byte_data(this_client, byte_offset); 8082 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8083 8084 if (status < 0) 8085 return E1000_ERR_I2C; 8086 else { 8087 *data = status; 8088 return E1000_SUCCESS; 8089 } 8090} 8091 8092/** 8093 * igb_write_i2c_byte - Writes 8 bit word over I2C 8094 * @hw: pointer to hardware structure 8095 * @byte_offset: byte offset to write 8096 * @dev_addr: device address 8097 * @data: value to write 8098 * 8099 * Performs byte write operation over I2C interface at 8100 * a specified device address. 8101 **/ 8102s32 igb_write_i2c_byte(struct e1000_hw *hw, u8 byte_offset, 8103 u8 dev_addr, u8 data) 8104{ 8105 struct igb_adapter *adapter = container_of(hw, struct igb_adapter, hw); 8106 struct i2c_client *this_client = adapter->i2c_client; 8107 s32 status; 8108 u16 swfw_mask = E1000_SWFW_PHY0_SM; 8109 8110 if (!this_client) 8111 return E1000_ERR_I2C; 8112 8113 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) 8114 return E1000_ERR_SWFW_SYNC; 8115 status = i2c_smbus_write_byte_data(this_client, byte_offset, data); 8116 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 8117 8118 if (status) 8119 return E1000_ERR_I2C; 8120 else 8121 return E1000_SUCCESS; 8122 8123} 8124 8125int igb_reinit_queues(struct igb_adapter *adapter) 8126{ 8127 struct net_device *netdev = adapter->netdev; 8128 struct pci_dev *pdev = adapter->pdev; 8129 int err = 0; 8130 8131 if (netif_running(netdev)) 8132 igb_close(netdev); 8133 8134 igb_reset_interrupt_capability(adapter); 8135 8136 if (igb_init_interrupt_scheme(adapter, true)) { 8137 dev_err(&pdev->dev, "Unable to allocate memory for queues\n"); 8138 return -ENOMEM; 8139 } 8140 8141 if (netif_running(netdev)) 8142 err = igb_open(netdev); 8143 8144 return err; 8145} 8146/* igb_main.c */ 8147