igb_ptp.c revision 167f3f71c7e31da56c907b7363a36667a59dde85
1/* PTP Hardware Clock (PHC) driver for the Intel 82576 and 82580 2 * 3 * Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License along 16 * with this program; if not, write to the Free Software Foundation, Inc., 17 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 18 */ 19#include <linux/module.h> 20#include <linux/device.h> 21#include <linux/pci.h> 22#include <linux/ptp_classify.h> 23 24#include "igb.h" 25 26#define INCVALUE_MASK 0x7fffffff 27#define ISGN 0x80000000 28 29/* The 82580 timesync updates the system timer every 8ns by 8ns, 30 * and this update value cannot be reprogrammed. 31 * 32 * Neither the 82576 nor the 82580 offer registers wide enough to hold 33 * nanoseconds time values for very long. For the 82580, SYSTIM always 34 * counts nanoseconds, but the upper 24 bits are not availible. The 35 * frequency is adjusted by changing the 32 bit fractional nanoseconds 36 * register, TIMINCA. 37 * 38 * For the 82576, the SYSTIM register time unit is affect by the 39 * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this 40 * field are needed to provide the nominal 16 nanosecond period, 41 * leaving 19 bits for fractional nanoseconds. 42 * 43 * We scale the NIC clock cycle by a large factor so that relatively 44 * small clock corrections can be added or subtracted at each clock 45 * tick. The drawbacks of a large factor are a) that the clock 46 * register overflows more quickly (not such a big deal) and b) that 47 * the increment per tick has to fit into 24 bits. As a result we 48 * need to use a shift of 19 so we can fit a value of 16 into the 49 * TIMINCA register. 50 * 51 * 52 * SYSTIMH SYSTIML 53 * +--------------+ +---+---+------+ 54 * 82576 | 32 | | 8 | 5 | 19 | 55 * +--------------+ +---+---+------+ 56 * \________ 45 bits _______/ fract 57 * 58 * +----------+---+ +--------------+ 59 * 82580 | 24 | 8 | | 32 | 60 * +----------+---+ +--------------+ 61 * reserved \______ 40 bits _____/ 62 * 63 * 64 * The 45 bit 82576 SYSTIM overflows every 65 * 2^45 * 10^-9 / 3600 = 9.77 hours. 66 * 67 * The 40 bit 82580 SYSTIM overflows every 68 * 2^40 * 10^-9 / 60 = 18.3 minutes. 69 */ 70 71#define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9) 72#define IGB_PTP_TX_TIMEOUT (HZ * 15) 73#define INCPERIOD_82576 (1 << E1000_TIMINCA_16NS_SHIFT) 74#define INCVALUE_82576_MASK ((1 << E1000_TIMINCA_16NS_SHIFT) - 1) 75#define INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT) 76#define IGB_NBITS_82580 40 77 78static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter); 79 80/* SYSTIM read access for the 82576 */ 81static cycle_t igb_ptp_read_82576(const struct cyclecounter *cc) 82{ 83 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 84 struct e1000_hw *hw = &igb->hw; 85 u64 val; 86 u32 lo, hi; 87 88 lo = rd32(E1000_SYSTIML); 89 hi = rd32(E1000_SYSTIMH); 90 91 val = ((u64) hi) << 32; 92 val |= lo; 93 94 return val; 95} 96 97/* SYSTIM read access for the 82580 */ 98static cycle_t igb_ptp_read_82580(const struct cyclecounter *cc) 99{ 100 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc); 101 struct e1000_hw *hw = &igb->hw; 102 u32 lo, hi; 103 u64 val; 104 105 /* The timestamp latches on lowest register read. For the 82580 106 * the lowest register is SYSTIMR instead of SYSTIML. However we only 107 * need to provide nanosecond resolution, so we just ignore it. 108 */ 109 rd32(E1000_SYSTIMR); 110 lo = rd32(E1000_SYSTIML); 111 hi = rd32(E1000_SYSTIMH); 112 113 val = ((u64) hi) << 32; 114 val |= lo; 115 116 return val; 117} 118 119/* SYSTIM read access for I210/I211 */ 120static void igb_ptp_read_i210(struct igb_adapter *adapter, struct timespec *ts) 121{ 122 struct e1000_hw *hw = &adapter->hw; 123 u32 sec, nsec; 124 125 /* The timestamp latches on lowest register read. For I210/I211, the 126 * lowest register is SYSTIMR. Since we only need to provide nanosecond 127 * resolution, we can ignore it. 128 */ 129 rd32(E1000_SYSTIMR); 130 nsec = rd32(E1000_SYSTIML); 131 sec = rd32(E1000_SYSTIMH); 132 133 ts->tv_sec = sec; 134 ts->tv_nsec = nsec; 135} 136 137static void igb_ptp_write_i210(struct igb_adapter *adapter, 138 const struct timespec *ts) 139{ 140 struct e1000_hw *hw = &adapter->hw; 141 142 /* Writing the SYSTIMR register is not necessary as it only provides 143 * sub-nanosecond resolution. 144 */ 145 wr32(E1000_SYSTIML, ts->tv_nsec); 146 wr32(E1000_SYSTIMH, ts->tv_sec); 147} 148 149/** 150 * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp 151 * @adapter: board private structure 152 * @hwtstamps: timestamp structure to update 153 * @systim: unsigned 64bit system time value. 154 * 155 * We need to convert the system time value stored in the RX/TXSTMP registers 156 * into a hwtstamp which can be used by the upper level timestamping functions. 157 * 158 * The 'tmreg_lock' spinlock is used to protect the consistency of the 159 * system time value. This is needed because reading the 64 bit time 160 * value involves reading two (or three) 32 bit registers. The first 161 * read latches the value. Ditto for writing. 162 * 163 * In addition, here have extended the system time with an overflow 164 * counter in software. 165 **/ 166static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter, 167 struct skb_shared_hwtstamps *hwtstamps, 168 u64 systim) 169{ 170 unsigned long flags; 171 u64 ns; 172 173 switch (adapter->hw.mac.type) { 174 case e1000_82576: 175 case e1000_82580: 176 case e1000_i354: 177 case e1000_i350: 178 spin_lock_irqsave(&adapter->tmreg_lock, flags); 179 180 ns = timecounter_cyc2time(&adapter->tc, systim); 181 182 spin_unlock_irqrestore(&adapter->tmreg_lock, flags); 183 184 memset(hwtstamps, 0, sizeof(*hwtstamps)); 185 hwtstamps->hwtstamp = ns_to_ktime(ns); 186 break; 187 case e1000_i210: 188 case e1000_i211: 189 memset(hwtstamps, 0, sizeof(*hwtstamps)); 190 /* Upper 32 bits contain s, lower 32 bits contain ns. */ 191 hwtstamps->hwtstamp = ktime_set(systim >> 32, 192 systim & 0xFFFFFFFF); 193 break; 194 default: 195 break; 196 } 197} 198 199/* PTP clock operations */ 200static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb) 201{ 202 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 203 ptp_caps); 204 struct e1000_hw *hw = &igb->hw; 205 int neg_adj = 0; 206 u64 rate; 207 u32 incvalue; 208 209 if (ppb < 0) { 210 neg_adj = 1; 211 ppb = -ppb; 212 } 213 rate = ppb; 214 rate <<= 14; 215 rate = div_u64(rate, 1953125); 216 217 incvalue = 16 << IGB_82576_TSYNC_SHIFT; 218 219 if (neg_adj) 220 incvalue -= rate; 221 else 222 incvalue += rate; 223 224 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK)); 225 226 return 0; 227} 228 229static int igb_ptp_adjfreq_82580(struct ptp_clock_info *ptp, s32 ppb) 230{ 231 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 232 ptp_caps); 233 struct e1000_hw *hw = &igb->hw; 234 int neg_adj = 0; 235 u64 rate; 236 u32 inca; 237 238 if (ppb < 0) { 239 neg_adj = 1; 240 ppb = -ppb; 241 } 242 rate = ppb; 243 rate <<= 26; 244 rate = div_u64(rate, 1953125); 245 246 inca = rate & INCVALUE_MASK; 247 if (neg_adj) 248 inca |= ISGN; 249 250 wr32(E1000_TIMINCA, inca); 251 252 return 0; 253} 254 255static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta) 256{ 257 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 258 ptp_caps); 259 unsigned long flags; 260 s64 now; 261 262 spin_lock_irqsave(&igb->tmreg_lock, flags); 263 264 now = timecounter_read(&igb->tc); 265 now += delta; 266 timecounter_init(&igb->tc, &igb->cc, now); 267 268 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 269 270 return 0; 271} 272 273static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta) 274{ 275 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 276 ptp_caps); 277 unsigned long flags; 278 struct timespec now, then = ns_to_timespec(delta); 279 280 spin_lock_irqsave(&igb->tmreg_lock, flags); 281 282 igb_ptp_read_i210(igb, &now); 283 now = timespec_add(now, then); 284 igb_ptp_write_i210(igb, (const struct timespec *)&now); 285 286 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 287 288 return 0; 289} 290 291static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp, 292 struct timespec *ts) 293{ 294 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 295 ptp_caps); 296 unsigned long flags; 297 u64 ns; 298 u32 remainder; 299 300 spin_lock_irqsave(&igb->tmreg_lock, flags); 301 302 ns = timecounter_read(&igb->tc); 303 304 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 305 306 ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder); 307 ts->tv_nsec = remainder; 308 309 return 0; 310} 311 312static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp, 313 struct timespec *ts) 314{ 315 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 316 ptp_caps); 317 unsigned long flags; 318 319 spin_lock_irqsave(&igb->tmreg_lock, flags); 320 321 igb_ptp_read_i210(igb, ts); 322 323 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 324 325 return 0; 326} 327 328static int igb_ptp_settime_82576(struct ptp_clock_info *ptp, 329 const struct timespec *ts) 330{ 331 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 332 ptp_caps); 333 unsigned long flags; 334 u64 ns; 335 336 ns = ts->tv_sec * 1000000000ULL; 337 ns += ts->tv_nsec; 338 339 spin_lock_irqsave(&igb->tmreg_lock, flags); 340 341 timecounter_init(&igb->tc, &igb->cc, ns); 342 343 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 344 345 return 0; 346} 347 348static int igb_ptp_settime_i210(struct ptp_clock_info *ptp, 349 const struct timespec *ts) 350{ 351 struct igb_adapter *igb = container_of(ptp, struct igb_adapter, 352 ptp_caps); 353 unsigned long flags; 354 355 spin_lock_irqsave(&igb->tmreg_lock, flags); 356 357 igb_ptp_write_i210(igb, ts); 358 359 spin_unlock_irqrestore(&igb->tmreg_lock, flags); 360 361 return 0; 362} 363 364static int igb_ptp_enable(struct ptp_clock_info *ptp, 365 struct ptp_clock_request *rq, int on) 366{ 367 return -EOPNOTSUPP; 368} 369 370/** 371 * igb_ptp_tx_work 372 * @work: pointer to work struct 373 * 374 * This work function polls the TSYNCTXCTL valid bit to determine when a 375 * timestamp has been taken for the current stored skb. 376 **/ 377static void igb_ptp_tx_work(struct work_struct *work) 378{ 379 struct igb_adapter *adapter = container_of(work, struct igb_adapter, 380 ptp_tx_work); 381 struct e1000_hw *hw = &adapter->hw; 382 u32 tsynctxctl; 383 384 if (!adapter->ptp_tx_skb) 385 return; 386 387 if (time_is_before_jiffies(adapter->ptp_tx_start + 388 IGB_PTP_TX_TIMEOUT)) { 389 dev_kfree_skb_any(adapter->ptp_tx_skb); 390 adapter->ptp_tx_skb = NULL; 391 adapter->tx_hwtstamp_timeouts++; 392 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang"); 393 return; 394 } 395 396 tsynctxctl = rd32(E1000_TSYNCTXCTL); 397 if (tsynctxctl & E1000_TSYNCTXCTL_VALID) 398 igb_ptp_tx_hwtstamp(adapter); 399 else 400 /* reschedule to check later */ 401 schedule_work(&adapter->ptp_tx_work); 402} 403 404static void igb_ptp_overflow_check(struct work_struct *work) 405{ 406 struct igb_adapter *igb = 407 container_of(work, struct igb_adapter, ptp_overflow_work.work); 408 struct timespec ts; 409 410 igb->ptp_caps.gettime(&igb->ptp_caps, &ts); 411 412 pr_debug("igb overflow check at %ld.%09lu\n", ts.tv_sec, ts.tv_nsec); 413 414 schedule_delayed_work(&igb->ptp_overflow_work, 415 IGB_SYSTIM_OVERFLOW_PERIOD); 416} 417 418/** 419 * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched 420 * @adapter: private network adapter structure 421 * 422 * This watchdog task is scheduled to detect error case where hardware has 423 * dropped an Rx packet that was timestamped when the ring is full. The 424 * particular error is rare but leaves the device in a state unable to timestamp 425 * any future packets. 426 **/ 427void igb_ptp_rx_hang(struct igb_adapter *adapter) 428{ 429 struct e1000_hw *hw = &adapter->hw; 430 struct igb_ring *rx_ring; 431 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL); 432 unsigned long rx_event; 433 int n; 434 435 if (hw->mac.type != e1000_82576) 436 return; 437 438 /* If we don't have a valid timestamp in the registers, just update the 439 * timeout counter and exit 440 */ 441 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) { 442 adapter->last_rx_ptp_check = jiffies; 443 return; 444 } 445 446 /* Determine the most recent watchdog or rx_timestamp event */ 447 rx_event = adapter->last_rx_ptp_check; 448 for (n = 0; n < adapter->num_rx_queues; n++) { 449 rx_ring = adapter->rx_ring[n]; 450 if (time_after(rx_ring->last_rx_timestamp, rx_event)) 451 rx_event = rx_ring->last_rx_timestamp; 452 } 453 454 /* Only need to read the high RXSTMP register to clear the lock */ 455 if (time_is_before_jiffies(rx_event + 5 * HZ)) { 456 rd32(E1000_RXSTMPH); 457 adapter->last_rx_ptp_check = jiffies; 458 adapter->rx_hwtstamp_cleared++; 459 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang"); 460 } 461} 462 463/** 464 * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp 465 * @adapter: Board private structure. 466 * 467 * If we were asked to do hardware stamping and such a time stamp is 468 * available, then it must have been for this skb here because we only 469 * allow only one such packet into the queue. 470 **/ 471static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter) 472{ 473 struct e1000_hw *hw = &adapter->hw; 474 struct skb_shared_hwtstamps shhwtstamps; 475 u64 regval; 476 477 regval = rd32(E1000_TXSTMPL); 478 regval |= (u64)rd32(E1000_TXSTMPH) << 32; 479 480 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval); 481 skb_tstamp_tx(adapter->ptp_tx_skb, &shhwtstamps); 482 dev_kfree_skb_any(adapter->ptp_tx_skb); 483 adapter->ptp_tx_skb = NULL; 484} 485 486/** 487 * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp 488 * @q_vector: Pointer to interrupt specific structure 489 * @va: Pointer to address containing Rx buffer 490 * @skb: Buffer containing timestamp and packet 491 * 492 * This function is meant to retrieve a timestamp from the first buffer of an 493 * incoming frame. The value is stored in little endian format starting on 494 * byte 8. 495 **/ 496void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, 497 unsigned char *va, 498 struct sk_buff *skb) 499{ 500 __le64 *regval = (__le64 *)va; 501 502 /* The timestamp is recorded in little endian format. 503 * DWORD: 0 1 2 3 504 * Field: Reserved Reserved SYSTIML SYSTIMH 505 */ 506 igb_ptp_systim_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb), 507 le64_to_cpu(regval[1])); 508} 509 510/** 511 * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register 512 * @q_vector: Pointer to interrupt specific structure 513 * @skb: Buffer containing timestamp and packet 514 * 515 * This function is meant to retrieve a timestamp from the internal registers 516 * of the adapter and store it in the skb. 517 **/ 518void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, 519 struct sk_buff *skb) 520{ 521 struct igb_adapter *adapter = q_vector->adapter; 522 struct e1000_hw *hw = &adapter->hw; 523 u64 regval; 524 525 /* If this bit is set, then the RX registers contain the time stamp. No 526 * other packet will be time stamped until we read these registers, so 527 * read the registers to make them available again. Because only one 528 * packet can be time stamped at a time, we know that the register 529 * values must belong to this one here and therefore we don't need to 530 * compare any of the additional attributes stored for it. 531 * 532 * If nothing went wrong, then it should have a shared tx_flags that we 533 * can turn into a skb_shared_hwtstamps. 534 */ 535 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID)) 536 return; 537 538 regval = rd32(E1000_RXSTMPL); 539 regval |= (u64)rd32(E1000_RXSTMPH) << 32; 540 541 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval); 542} 543 544/** 545 * igb_ptp_hwtstamp_ioctl - control hardware time stamping 546 * @netdev: 547 * @ifreq: 548 * @cmd: 549 * 550 * Outgoing time stamping can be enabled and disabled. Play nice and 551 * disable it when requested, although it shouldn't case any overhead 552 * when no packet needs it. At most one packet in the queue may be 553 * marked for time stamping, otherwise it would be impossible to tell 554 * for sure to which packet the hardware time stamp belongs. 555 * 556 * Incoming time stamping has to be configured via the hardware 557 * filters. Not all combinations are supported, in particular event 558 * type has to be specified. Matching the kind of event packet is 559 * not supported, with the exception of "all V2 events regardless of 560 * level 2 or 4". 561 **/ 562int igb_ptp_hwtstamp_ioctl(struct net_device *netdev, 563 struct ifreq *ifr, int cmd) 564{ 565 struct igb_adapter *adapter = netdev_priv(netdev); 566 struct e1000_hw *hw = &adapter->hw; 567 struct hwtstamp_config config; 568 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED; 569 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 570 u32 tsync_rx_cfg = 0; 571 bool is_l4 = false; 572 bool is_l2 = false; 573 u32 regval; 574 575 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 576 return -EFAULT; 577 578 /* reserved for future extensions */ 579 if (config.flags) 580 return -EINVAL; 581 582 switch (config.tx_type) { 583 case HWTSTAMP_TX_OFF: 584 tsync_tx_ctl = 0; 585 case HWTSTAMP_TX_ON: 586 break; 587 default: 588 return -ERANGE; 589 } 590 591 switch (config.rx_filter) { 592 case HWTSTAMP_FILTER_NONE: 593 tsync_rx_ctl = 0; 594 break; 595 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 596 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 597 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE; 598 is_l4 = true; 599 break; 600 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 601 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1; 602 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE; 603 is_l4 = true; 604 break; 605 case HWTSTAMP_FILTER_PTP_V2_EVENT: 606 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 607 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 608 case HWTSTAMP_FILTER_PTP_V2_SYNC: 609 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 610 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 611 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 612 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 613 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 614 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2; 615 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 616 is_l2 = true; 617 is_l4 = true; 618 break; 619 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 620 case HWTSTAMP_FILTER_ALL: 621 /* 82576 cannot timestamp all packets, which it needs to do to 622 * support both V1 Sync and Delay_Req messages 623 */ 624 if (hw->mac.type != e1000_82576) { 625 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 626 config.rx_filter = HWTSTAMP_FILTER_ALL; 627 break; 628 } 629 /* fall through */ 630 default: 631 config.rx_filter = HWTSTAMP_FILTER_NONE; 632 return -ERANGE; 633 } 634 635 if (hw->mac.type == e1000_82575) { 636 if (tsync_rx_ctl | tsync_tx_ctl) 637 return -EINVAL; 638 return 0; 639 } 640 641 /* Per-packet timestamping only works if all packets are 642 * timestamped, so enable timestamping in all packets as 643 * long as one Rx filter was configured. 644 */ 645 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) { 646 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED; 647 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL; 648 config.rx_filter = HWTSTAMP_FILTER_ALL; 649 is_l2 = true; 650 is_l4 = true; 651 652 if ((hw->mac.type == e1000_i210) || 653 (hw->mac.type == e1000_i211)) { 654 regval = rd32(E1000_RXPBS); 655 regval |= E1000_RXPBS_CFG_TS_EN; 656 wr32(E1000_RXPBS, regval); 657 } 658 } 659 660 /* enable/disable TX */ 661 regval = rd32(E1000_TSYNCTXCTL); 662 regval &= ~E1000_TSYNCTXCTL_ENABLED; 663 regval |= tsync_tx_ctl; 664 wr32(E1000_TSYNCTXCTL, regval); 665 666 /* enable/disable RX */ 667 regval = rd32(E1000_TSYNCRXCTL); 668 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK); 669 regval |= tsync_rx_ctl; 670 wr32(E1000_TSYNCRXCTL, regval); 671 672 /* define which PTP packets are time stamped */ 673 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg); 674 675 /* define ethertype filter for timestamped packets */ 676 if (is_l2) 677 wr32(E1000_ETQF(3), 678 (E1000_ETQF_FILTER_ENABLE | /* enable filter */ 679 E1000_ETQF_1588 | /* enable timestamping */ 680 ETH_P_1588)); /* 1588 eth protocol type */ 681 else 682 wr32(E1000_ETQF(3), 0); 683 684 /* L4 Queue Filter[3]: filter by destination port and protocol */ 685 if (is_l4) { 686 u32 ftqf = (IPPROTO_UDP /* UDP */ 687 | E1000_FTQF_VF_BP /* VF not compared */ 688 | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */ 689 | E1000_FTQF_MASK); /* mask all inputs */ 690 ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */ 691 692 wr32(E1000_IMIR(3), htons(PTP_EV_PORT)); 693 wr32(E1000_IMIREXT(3), 694 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP)); 695 if (hw->mac.type == e1000_82576) { 696 /* enable source port check */ 697 wr32(E1000_SPQF(3), htons(PTP_EV_PORT)); 698 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP; 699 } 700 wr32(E1000_FTQF(3), ftqf); 701 } else { 702 wr32(E1000_FTQF(3), E1000_FTQF_MASK); 703 } 704 wrfl(); 705 706 /* clear TX/RX time stamp registers, just to be sure */ 707 regval = rd32(E1000_TXSTMPL); 708 regval = rd32(E1000_TXSTMPH); 709 regval = rd32(E1000_RXSTMPL); 710 regval = rd32(E1000_RXSTMPH); 711 712 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 713 -EFAULT : 0; 714} 715 716void igb_ptp_init(struct igb_adapter *adapter) 717{ 718 struct e1000_hw *hw = &adapter->hw; 719 struct net_device *netdev = adapter->netdev; 720 721 switch (hw->mac.type) { 722 case e1000_82576: 723 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 724 adapter->ptp_caps.owner = THIS_MODULE; 725 adapter->ptp_caps.max_adj = 999999881; 726 adapter->ptp_caps.n_ext_ts = 0; 727 adapter->ptp_caps.pps = 0; 728 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576; 729 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 730 adapter->ptp_caps.gettime = igb_ptp_gettime_82576; 731 adapter->ptp_caps.settime = igb_ptp_settime_82576; 732 adapter->ptp_caps.enable = igb_ptp_enable; 733 adapter->cc.read = igb_ptp_read_82576; 734 adapter->cc.mask = CLOCKSOURCE_MASK(64); 735 adapter->cc.mult = 1; 736 adapter->cc.shift = IGB_82576_TSYNC_SHIFT; 737 /* Dial the nominal frequency. */ 738 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 739 break; 740 case e1000_82580: 741 case e1000_i354: 742 case e1000_i350: 743 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 744 adapter->ptp_caps.owner = THIS_MODULE; 745 adapter->ptp_caps.max_adj = 62499999; 746 adapter->ptp_caps.n_ext_ts = 0; 747 adapter->ptp_caps.pps = 0; 748 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; 749 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576; 750 adapter->ptp_caps.gettime = igb_ptp_gettime_82576; 751 adapter->ptp_caps.settime = igb_ptp_settime_82576; 752 adapter->ptp_caps.enable = igb_ptp_enable; 753 adapter->cc.read = igb_ptp_read_82580; 754 adapter->cc.mask = CLOCKSOURCE_MASK(IGB_NBITS_82580); 755 adapter->cc.mult = 1; 756 adapter->cc.shift = 0; 757 /* Enable the timer functions by clearing bit 31. */ 758 wr32(E1000_TSAUXC, 0x0); 759 break; 760 case e1000_i210: 761 case e1000_i211: 762 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr); 763 adapter->ptp_caps.owner = THIS_MODULE; 764 adapter->ptp_caps.max_adj = 62499999; 765 adapter->ptp_caps.n_ext_ts = 0; 766 adapter->ptp_caps.pps = 0; 767 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82580; 768 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210; 769 adapter->ptp_caps.gettime = igb_ptp_gettime_i210; 770 adapter->ptp_caps.settime = igb_ptp_settime_i210; 771 adapter->ptp_caps.enable = igb_ptp_enable; 772 /* Enable the timer functions by clearing bit 31. */ 773 wr32(E1000_TSAUXC, 0x0); 774 break; 775 default: 776 adapter->ptp_clock = NULL; 777 return; 778 } 779 780 wrfl(); 781 782 spin_lock_init(&adapter->tmreg_lock); 783 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work); 784 785 /* Initialize the clock and overflow work for devices that need it. */ 786 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 787 struct timespec ts = ktime_to_timespec(ktime_get_real()); 788 789 igb_ptp_settime_i210(&adapter->ptp_caps, &ts); 790 } else { 791 timecounter_init(&adapter->tc, &adapter->cc, 792 ktime_to_ns(ktime_get_real())); 793 794 INIT_DELAYED_WORK(&adapter->ptp_overflow_work, 795 igb_ptp_overflow_check); 796 797 schedule_delayed_work(&adapter->ptp_overflow_work, 798 IGB_SYSTIM_OVERFLOW_PERIOD); 799 } 800 801 /* Initialize the time sync interrupts for devices that support it. */ 802 if (hw->mac.type >= e1000_82580) { 803 wr32(E1000_TSIM, E1000_TSIM_TXTS); 804 wr32(E1000_IMS, E1000_IMS_TS); 805 } 806 807 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps, 808 &adapter->pdev->dev); 809 if (IS_ERR(adapter->ptp_clock)) { 810 adapter->ptp_clock = NULL; 811 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n"); 812 } else { 813 dev_info(&adapter->pdev->dev, "added PHC on %s\n", 814 adapter->netdev->name); 815 adapter->flags |= IGB_FLAG_PTP; 816 } 817} 818 819/** 820 * igb_ptp_stop - Disable PTP device and stop the overflow check. 821 * @adapter: Board private structure. 822 * 823 * This function stops the PTP support and cancels the delayed work. 824 **/ 825void igb_ptp_stop(struct igb_adapter *adapter) 826{ 827 switch (adapter->hw.mac.type) { 828 case e1000_82576: 829 case e1000_82580: 830 case e1000_i354: 831 case e1000_i350: 832 cancel_delayed_work_sync(&adapter->ptp_overflow_work); 833 break; 834 case e1000_i210: 835 case e1000_i211: 836 /* No delayed work to cancel. */ 837 break; 838 default: 839 return; 840 } 841 842 cancel_work_sync(&adapter->ptp_tx_work); 843 if (adapter->ptp_tx_skb) { 844 dev_kfree_skb_any(adapter->ptp_tx_skb); 845 adapter->ptp_tx_skb = NULL; 846 } 847 848 if (adapter->ptp_clock) { 849 ptp_clock_unregister(adapter->ptp_clock); 850 dev_info(&adapter->pdev->dev, "removed PHC on %s\n", 851 adapter->netdev->name); 852 adapter->flags &= ~IGB_FLAG_PTP; 853 } 854} 855 856/** 857 * igb_ptp_reset - Re-enable the adapter for PTP following a reset. 858 * @adapter: Board private structure. 859 * 860 * This function handles the reset work required to re-enable the PTP device. 861 **/ 862void igb_ptp_reset(struct igb_adapter *adapter) 863{ 864 struct e1000_hw *hw = &adapter->hw; 865 866 if (!(adapter->flags & IGB_FLAG_PTP)) 867 return; 868 869 switch (adapter->hw.mac.type) { 870 case e1000_82576: 871 /* Dial the nominal frequency. */ 872 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576); 873 break; 874 case e1000_82580: 875 case e1000_i354: 876 case e1000_i350: 877 case e1000_i210: 878 case e1000_i211: 879 /* Enable the timer functions and interrupts. */ 880 wr32(E1000_TSAUXC, 0x0); 881 wr32(E1000_TSIM, E1000_TSIM_TXTS); 882 wr32(E1000_IMS, E1000_IMS_TS); 883 break; 884 default: 885 /* No work to do. */ 886 return; 887 } 888 889 /* Re-initialize the timer. */ 890 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) { 891 struct timespec ts = ktime_to_timespec(ktime_get_real()); 892 893 igb_ptp_settime_i210(&adapter->ptp_caps, &ts); 894 } else { 895 timecounter_init(&adapter->tc, &adapter->cc, 896 ktime_to_ns(ktime_get_real())); 897 } 898} 899