qlcnic_83xx_hw.h revision 4e60ac46414b2815d6e37e76fe6e3fb6dc4843c7 
1#ifndef __QLCNIC_83XX_HW_H
2#define __QLCNIC_83XX_HW_H
3
4#include <linux/types.h>
5#include <linux/etherdevice.h>
6#include "qlcnic_hw.h"
7
8/* Directly mapped registers */
9#define QLC_83XX_CRB_WIN_BASE		0x3800
10#define QLC_83XX_CRB_WIN_FUNC(f)	(QLC_83XX_CRB_WIN_BASE+((f)*4))
11#define QLC_83XX_SEM_LOCK_BASE		0x3840
12#define QLC_83XX_SEM_UNLOCK_BASE	0x3844
13#define QLC_83XX_SEM_LOCK_FUNC(f)	(QLC_83XX_SEM_LOCK_BASE+((f)*8))
14#define QLC_83XX_SEM_UNLOCK_FUNC(f)	(QLC_83XX_SEM_UNLOCK_BASE+((f)*8))
15#define QLC_83XX_LINK_STATE(f)		(0x3698+((f) > 7 ? 4 : 0))
16#define QLC_83XX_LINK_SPEED(f)		(0x36E0+(((f) >> 2) * 4))
17#define QLC_83XX_LINK_SPEED_FACTOR	10
18#define QLC_83xx_FUNC_VAL(v, f)	((v) & (1 << (f * 4)))
19#define QLC_83XX_INTX_PTR		0x38C0
20#define QLC_83XX_INTX_TRGR		0x38C4
21#define QLC_83XX_INTX_MASK		0x38C8
22
23#define QLC_83XX_DRV_LOCK_WAIT_COUNTER			100
24#define QLC_83XX_DRV_LOCK_WAIT_DELAY			20
25#define QLC_83XX_NEED_DRV_LOCK_RECOVERY		1
26#define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS		2
27#define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT		3
28#define QLC_83XX_DRV_LOCK_RECOVERY_DELAY		200
29#define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK		0x3
30
31#define QLC_83XX_NO_NIC_RESOURCE	0x5
32#define QLC_83XX_MAC_PRESENT		0xC
33#define QLC_83XX_MAC_ABSENT		0xD
34
35
36#define QLC_83XX_FLASH_SECTOR_SIZE		(64 * 1024)
37
38/* PEG status definitions */
39#define QLC_83XX_CMDPEG_COMPLETE		0xff01
40#define QLC_83XX_VALID_INTX_BIT30(val)		((val) & BIT_30)
41#define QLC_83XX_VALID_INTX_BIT31(val)		((val) & BIT_31)
42#define QLC_83XX_INTX_FUNC(val)		((val) & 0xFF)
43#define QLC_83XX_LEGACY_INTX_MAX_RETRY		100
44#define QLC_83XX_LEGACY_INTX_DELAY		4
45#define QLC_83XX_REG_DESC			1
46#define QLC_83XX_LRO_DESC			2
47#define QLC_83XX_CTRL_DESC			3
48#define QLC_83XX_FW_CAPABILITY_TSO		BIT_6
49#define QLC_83XX_FW_CAP_LRO_MSS		BIT_17
50#define QLC_83XX_HOST_RDS_MODE_UNIQUE		0
51#define QLC_83XX_HOST_SDS_MBX_IDX		8
52
53#define QLCNIC_HOST_RDS_MBX_IDX			88
54#define QLCNIC_MAX_RING_SETS			8
55
56/* Pause control registers */
57#define QLC_83XX_SRE_SHIM_REG		0x0D200284
58#define QLC_83XX_PORT0_THRESHOLD	0x0B2003A4
59#define QLC_83XX_PORT1_THRESHOLD	0x0B2013A4
60#define QLC_83XX_PORT0_TC_MC_REG	0x0B200388
61#define QLC_83XX_PORT1_TC_MC_REG	0x0B201388
62#define QLC_83XX_PORT0_TC_STATS		0x0B20039C
63#define QLC_83XX_PORT1_TC_STATS		0x0B20139C
64#define QLC_83XX_PORT2_IFB_THRESHOLD	0x0B200704
65#define QLC_83XX_PORT3_IFB_THRESHOLD	0x0B201704
66
67/* Peg PC status registers */
68#define QLC_83XX_CRB_PEG_NET_0		0x3400003c
69#define QLC_83XX_CRB_PEG_NET_1		0x3410003c
70#define QLC_83XX_CRB_PEG_NET_2		0x3420003c
71#define QLC_83XX_CRB_PEG_NET_3		0x3430003c
72#define QLC_83XX_CRB_PEG_NET_4		0x34b0003c
73
74/* Firmware image definitions */
75#define QLC_83XX_BOOTLOADER_FLASH_ADDR	0x10000
76#define QLC_83XX_FW_FILE_NAME		"83xx_fw.bin"
77#define QLC_83XX_BOOT_FROM_FLASH	0
78#define QLC_83XX_BOOT_FROM_FILE		0x12345678
79
80#define QLC_83XX_MAX_RESET_SEQ_ENTRIES	16
81
82struct qlcnic_intrpt_config {
83	u8	type;
84	u8	enabled;
85	u16	id;
86	u32	src;
87};
88
89struct qlcnic_macvlan_mbx {
90	u8	mac[ETH_ALEN];
91	u16	vlan;
92};
93
94struct qlc_83xx_fw_info {
95	const struct firmware	*fw;
96	u16	major_fw_version;
97	u8	minor_fw_version;
98	u8	sub_fw_version;
99	u8	fw_build_num;
100	u8	load_from_file;
101};
102
103struct qlc_83xx_reset {
104	struct qlc_83xx_reset_hdr *hdr;
105	int	seq_index;
106	int	seq_error;
107	int	array_index;
108	u32	array[QLC_83XX_MAX_RESET_SEQ_ENTRIES];
109	u8	*buff;
110	u8	*stop_offset;
111	u8	*start_offset;
112	u8	*init_offset;
113	u8	seq_end;
114	u8	template_end;
115};
116
117#define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY		0x1
118#define QLC_83XX_IDC_GRACEFULL_RESET			0x2
119#define QLC_83XX_IDC_TIMESTAMP				0
120#define QLC_83XX_IDC_DURATION				1
121#define QLC_83XX_IDC_INIT_TIMEOUT_SECS			30
122#define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS		10
123#define QLC_83XX_IDC_RESET_TIMEOUT_SECS		10
124#define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS		20
125#define QLC_83XX_IDC_FW_POLL_DELAY			(1 * HZ)
126#define QLC_83XX_IDC_FW_FAIL_THRESH			2
127#define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO	8
128#define QLC_83XX_IDC_MAX_CNA_FUNCTIONS			16
129#define QLC_83XX_IDC_MAJOR_VERSION			1
130#define QLC_83XX_IDC_MINOR_VERSION			0
131#define QLC_83XX_IDC_FLASH_PARAM_ADDR			0x3e8020
132
133/* Mailbox process AEN count */
134#define QLC_83XX_MBX_AEN_CNT 5
135
136struct qlcnic_adapter;
137struct qlc_83xx_idc {
138	int (*state_entry) (struct qlcnic_adapter *);
139	u64		sec_counter;
140	u64		delay;
141	unsigned long	status;
142	int		err_code;
143	int		collect_dump;
144	u8		curr_state;
145	u8		prev_state;
146	u8		vnic_state;
147	u8		vnic_wait_limit;
148	u8		quiesce_req;
149	char		**name;
150};
151
152/* Mailbox process AEN count */
153#define QLC_83XX_IDC_COMP_AEN			3
154#define QLC_83XX_MBX_AEN_CNT			5
155#define QLC_83XX_MODULE_LOADED			1
156#define QLC_83XX_MBX_READY			2
157#define QLC_83XX_MBX_AEN_ACK			3
158#define QLC_83XX_SFP_PRESENT(data)		((data) & 3)
159#define QLC_83XX_SFP_ERR(data)			(((data) >> 2) & 3)
160#define QLC_83XX_SFP_MODULE_TYPE(data)		(((data) >> 4) & 0x1F)
161#define QLC_83XX_SFP_CU_LENGTH(data)		(LSB((data) >> 16))
162#define QLC_83XX_SFP_TX_FAULT(data)		((data) & BIT_10)
163#define QLC_83XX_SFP_10G_CAPABLE(data)		((data) & BIT_11)
164#define QLC_83XX_LINK_STATS(data)		((data) & BIT_0)
165#define QLC_83XX_CURRENT_LINK_SPEED(data)	(((data) >> 3) & 7)
166#define QLC_83XX_LINK_PAUSE(data)		(((data) >> 6) & 3)
167#define QLC_83XX_LINK_LB(data)			(((data) >> 8) & 7)
168#define QLC_83XX_LINK_FEC(data)		((data) & BIT_12)
169#define QLC_83XX_LINK_EEE(data)		((data) & BIT_13)
170#define QLC_83XX_DCBX(data)			(((data) >> 28) & 7)
171#define QLC_83XX_AUTONEG(data)			((data) & BIT_15)
172#define QLC_83XX_CFG_STD_PAUSE			(1 << 5)
173#define QLC_83XX_CFG_STD_TX_PAUSE		(1 << 20)
174#define QLC_83XX_CFG_STD_RX_PAUSE		(2 << 20)
175#define QLC_83XX_CFG_STD_TX_RX_PAUSE		(3 << 20)
176#define QLC_83XX_ENABLE_AUTONEG		(1 << 15)
177#define QLC_83XX_CFG_LOOPBACK_HSS		(2 << 1)
178#define QLC_83XX_CFG_LOOPBACK_PHY		(3 << 1)
179#define QLC_83XX_CFG_LOOPBACK_EXT		(4 << 1)
180
181/* LED configuration settings */
182#define QLC_83XX_ENABLE_BEACON		0xe
183#define QLC_83XX_LED_RATE		0xff
184#define QLC_83XX_LED_ACT		(1 << 10)
185#define QLC_83XX_LED_MOD		(0 << 13)
186#define QLC_83XX_LED_CONFIG	(QLC_83XX_LED_RATE | QLC_83XX_LED_ACT |	\
187				 QLC_83XX_LED_MOD)
188
189#define QLC_83XX_10M_LINK	1
190#define QLC_83XX_100M_LINK	2
191#define QLC_83XX_1G_LINK	3
192#define QLC_83XX_10G_LINK	4
193#define QLC_83XX_STAT_TX	3
194#define QLC_83XX_STAT_RX	2
195#define QLC_83XX_STAT_MAC	1
196#define QLC_83XX_TX_STAT_REGS	14
197#define QLC_83XX_RX_STAT_REGS	40
198#define QLC_83XX_MAC_STAT_REGS	80
199
200#define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN)	(0x3 & ((VAL) >> (FN * 2)))
201#define QLC_83XX_SET_FUNC_OPMODE(VAL, FN)	((VAL) << (FN * 2))
202#define QLC_83XX_DEFAULT_OPMODE			0x55555555
203#define QLC_83XX_PRIVLEGED_FUNC			0x1
204#define QLC_83XX_VIRTUAL_FUNC				0x2
205
206#define QLC_83XX_LB_MAX_FILTERS			2048
207#define QLC_83XX_LB_BUCKET_SIZE			256
208#define QLC_83XX_MINIMUM_VECTOR			3
209
210#define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val)	(val & 0x80000000)
211#define QLC_83XX_GET_LRO_CAPABILITY(val)		(val & 0x20)
212#define QLC_83XX_GET_LSO_CAPABILITY(val)		(val & 0x40)
213#define QLC_83XX_GET_LSO_CAPABILITY(val)		(val & 0x40)
214#define QLC_83XX_GET_HW_LRO_CAPABILITY(val)		(val & 0x400)
215#define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val)	(val & 0x4000)
216#define QLC_83XX_VIRTUAL_NIC_MODE			0xFF
217#define QLC_83XX_DEFAULT_MODE				0x0
218#define QLCNIC_BRDTYPE_83XX_10G			0x0083
219
220#define QLC_83XX_FLASH_SPI_STATUS		0x2808E010
221#define QLC_83XX_FLASH_SPI_CONTROL		0x2808E014
222#define QLC_83XX_FLASH_STATUS			0x42100004
223#define QLC_83XX_FLASH_CONTROL			0x42110004
224#define QLC_83XX_FLASH_ADDR			0x42110008
225#define QLC_83XX_FLASH_WRDATA			0x4211000C
226#define QLC_83XX_FLASH_RDDATA			0x42110018
227#define QLC_83XX_FLASH_DIRECT_WINDOW		0x42110030
228#define QLC_83XX_FLASH_DIRECT_DATA(DATA)	(0x42150000 | (0x0000FFFF&DATA))
229#define QLC_83XX_FLASH_SECTOR_ERASE_CMD	0xdeadbeef
230#define QLC_83XX_FLASH_WRITE_CMD		0xdacdacda
231#define QLC_83XX_FLASH_BULK_WRITE_CMD		0xcadcadca
232#define QLC_83XX_FLASH_READ_RETRY_COUNT	5000
233#define QLC_83XX_FLASH_STATUS_READY		0x6
234#define QLC_83XX_FLASH_BULK_WRITE_MIN		2
235#define QLC_83XX_FLASH_BULK_WRITE_MAX		64
236#define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY	1
237#define QLC_83XX_ERASE_MODE			1
238#define QLC_83XX_WRITE_MODE			2
239#define QLC_83XX_BULK_WRITE_MODE		3
240#define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG	0xFD0100
241#define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG	0xFD0300
242#define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL	0xFD009F
243#define QLC_83XX_FLASH_OEM_ERASE_SIG		0xFD03D8
244#define QLC_83XX_FLASH_OEM_WRITE_SIG		0xFD0101
245#define QLC_83XX_FLASH_OEM_READ_SIG		0xFD0005
246#define QLC_83XX_FLASH_ADDR_TEMP_VAL		0x00800000
247#define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL	0x00800001
248#define QLC_83XX_FLASH_WRDATA_DEF		0x0
249#define QLC_83XX_FLASH_READ_CTRL		0x3F
250#define QLC_83XX_FLASH_SPI_CTRL		0x4
251#define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL	0x2
252#define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL	0x5
253#define QLC_83XX_FLASH_LAST_ERASE_MS_VAL	0x3D
254#define QLC_83XX_FLASH_FIRST_MS_PATTERN	0x43
255#define QLC_83XX_FLASH_SECOND_MS_PATTERN	0x7F
256#define QLC_83XX_FLASH_LAST_MS_PATTERN		0x7D
257#define QLC_83xx_FLASH_MAX_WAIT_USEC		100
258#define QLC_83XX_FLASH_LOCK_TIMEOUT		10000
259
260/* Additional registers in 83xx */
261enum qlc_83xx_ext_regs {
262	QLCNIC_GLOBAL_RESET = 0,
263	QLCNIC_WILDCARD,
264	QLCNIC_INFORMANT,
265	QLCNIC_HOST_MBX_CTRL,
266	QLCNIC_FW_MBX_CTRL,
267	QLCNIC_BOOTLOADER_ADDR,
268	QLCNIC_BOOTLOADER_SIZE,
269	QLCNIC_FW_IMAGE_ADDR,
270	QLCNIC_MBX_INTR_ENBL,
271	QLCNIC_DEF_INT_MASK,
272	QLCNIC_DEF_INT_ID,
273	QLC_83XX_IDC_MAJ_VERSION,
274	QLC_83XX_IDC_DEV_STATE,
275	QLC_83XX_IDC_DRV_PRESENCE,
276	QLC_83XX_IDC_DRV_ACK,
277	QLC_83XX_IDC_CTRL,
278	QLC_83XX_IDC_DRV_AUDIT,
279	QLC_83XX_IDC_MIN_VERSION,
280	QLC_83XX_RECOVER_DRV_LOCK,
281	QLC_83XX_IDC_PF_0,
282	QLC_83XX_IDC_PF_1,
283	QLC_83XX_IDC_PF_2,
284	QLC_83XX_IDC_PF_3,
285	QLC_83XX_IDC_PF_4,
286	QLC_83XX_IDC_PF_5,
287	QLC_83XX_IDC_PF_6,
288	QLC_83XX_IDC_PF_7,
289	QLC_83XX_IDC_PF_8,
290	QLC_83XX_IDC_PF_9,
291	QLC_83XX_IDC_PF_10,
292	QLC_83XX_IDC_PF_11,
293	QLC_83XX_IDC_PF_12,
294	QLC_83XX_IDC_PF_13,
295	QLC_83XX_IDC_PF_14,
296	QLC_83XX_IDC_PF_15,
297	QLC_83XX_IDC_DEV_PARTITION_INFO_1,
298	QLC_83XX_IDC_DEV_PARTITION_INFO_2,
299	QLC_83XX_DRV_OP_MODE,
300	QLC_83XX_VNIC_STATE,
301	QLC_83XX_DRV_LOCK,
302	QLC_83XX_DRV_UNLOCK,
303	QLC_83XX_DRV_LOCK_ID,
304	QLC_83XX_ASIC_TEMP,
305};
306
307/* 83xx funcitons */
308int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *);
309int qlcnic_83xx_mbx_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *);
310int qlcnic_83xx_setup_intr(struct qlcnic_adapter *, u8);
311void qlcnic_83xx_get_func_no(struct qlcnic_adapter *);
312int qlcnic_83xx_cam_lock(struct qlcnic_adapter *);
313void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *);
314int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32);
315void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *);
316void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *);
317void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
318void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t);
319int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong);
320int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32);
321void qlcnic_83xx_process_rcv_diag(struct qlcnic_adapter *, int, u64 []);
322int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32);
323int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8);
324int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8);
325int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int);
326int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int);
327int qlcnic_83xx_config_intr_coalesce(struct qlcnic_adapter *);
328void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *, u64 *, __le16);
329int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *);
330int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *);
331void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *, int);
332
333int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *);
334void qlcnic_83xx_napi_del(struct qlcnic_adapter *);
335void qlcnic_83xx_napi_enable(struct qlcnic_adapter *);
336void qlcnic_83xx_napi_disable(struct qlcnic_adapter *);
337int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32);
338void qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32);
339int qlcnic_ind_rd(struct qlcnic_adapter *, u32);
340void qlcnic_83xx_get_stats(struct qlcnic_adapter *,
341			   struct ethtool_stats *, u64 *);
342int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *);
343int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *,
344			      struct qlcnic_host_tx_ring *, int);
345int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8);
346int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int);
347void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *);
348int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool);
349int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, __le16, u8);
350int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *);
351void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8,
352			       struct qlcnic_cmd_args *);
353int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *,
354			       struct qlcnic_adapter *, u32);
355void qlcnic_free_mbx_args(struct qlcnic_cmd_args *);
356void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *,
357			  struct qlcnic_info *);
358void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *);
359irqreturn_t qlcnic_83xx_handle_aen(int, void *);
360int qlcnic_83xx_get_port_info(struct qlcnic_adapter *);
361void qlcnic_83xx_enable_mbx_intrpt(struct qlcnic_adapter *);
362irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *);
363irqreturn_t qlcnic_83xx_tmp_intr(int, void *);
364void qlcnic_83xx_enable_intr(struct qlcnic_adapter *,
365			     struct qlcnic_host_sds_ring *);
366void qlcnic_83xx_check_vf(struct qlcnic_adapter *,
367			  const struct pci_device_id *);
368void qlcnic_83xx_process_aen(struct qlcnic_adapter *);
369int qlcnic_83xx_get_port_config(struct qlcnic_adapter *);
370int qlcnic_83xx_set_port_config(struct qlcnic_adapter *);
371int qlcnic_enable_eswitch(struct qlcnic_adapter *, u8, u8);
372int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *);
373int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *);
374int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *);
375void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *);
376void qlcnic_83xx_register_map(struct qlcnic_hardware_context *);
377void qlcnic_83xx_idc_aen_work(struct work_struct *);
378void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int);
379
380int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32);
381int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int);
382int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *);
383int qlcnic_83xx_lock_flash(struct qlcnic_adapter *);
384void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *);
385int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *);
386int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int);
387int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *);
388int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *);
389int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int);
390int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *,
391				      u32, u8 *, int);
392int qlcnic_83xx_init(struct qlcnic_adapter *);
393int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *);
394int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev);
395void qlcnic_83xx_idc_poll_dev_state(struct work_struct *);
396int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *);
397void qlcnic_83xx_idc_exit(struct qlcnic_adapter *);
398void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32);
399int qlcnic_83xx_lock_driver(struct qlcnic_adapter *);
400void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *);
401int qlcnic_83xx_set_default_offload_settings(struct qlcnic_adapter *);
402int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32);
403int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *);
404int qlcnic_83xx_enable_vnic_mode(struct qlcnic_adapter *, int);
405int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *, int);
406int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *);
407int qlcnic_83xx_get_vnic_vport_info(struct qlcnic_adapter *,
408				    struct qlcnic_info *, u8);
409int qlcnic_83xx_get_vnic_pf_info(struct qlcnic_adapter *, struct qlcnic_info *);
410
411void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *);
412#endif
413