qlcnic_83xx_hw.h revision 58945e1bd6e7ed8d3637c655ebdfdc34fa996456
1/* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8#ifndef __QLCNIC_83XX_HW_H 9#define __QLCNIC_83XX_HW_H 10 11#include <linux/types.h> 12#include <linux/etherdevice.h> 13#include "qlcnic_hw.h" 14 15#define QLCNIC_83XX_BAR0_LENGTH 0x4000 16 17/* Directly mapped registers */ 18#define QLC_83XX_CRB_WIN_BASE 0x3800 19#define QLC_83XX_CRB_WIN_FUNC(f) (QLC_83XX_CRB_WIN_BASE+((f)*4)) 20#define QLC_83XX_SEM_LOCK_BASE 0x3840 21#define QLC_83XX_SEM_UNLOCK_BASE 0x3844 22#define QLC_83XX_SEM_LOCK_FUNC(f) (QLC_83XX_SEM_LOCK_BASE+((f)*8)) 23#define QLC_83XX_SEM_UNLOCK_FUNC(f) (QLC_83XX_SEM_UNLOCK_BASE+((f)*8)) 24#define QLC_83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0)) 25#define QLC_83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4)) 26#define QLC_83XX_LINK_SPEED_FACTOR 10 27#define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4))) 28#define QLC_83XX_INTX_PTR 0x38C0 29#define QLC_83XX_INTX_TRGR 0x38C4 30#define QLC_83XX_INTX_MASK 0x38C8 31 32#define QLC_83XX_DRV_LOCK_WAIT_COUNTER 100 33#define QLC_83XX_DRV_LOCK_WAIT_DELAY 20 34#define QLC_83XX_NEED_DRV_LOCK_RECOVERY 1 35#define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS 2 36#define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT 3 37#define QLC_83XX_DRV_LOCK_RECOVERY_DELAY 200 38#define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK 0x3 39#define QLC_83XX_LB_WAIT_COUNT 250 40#define QLC_83XX_LB_MSLEEP_COUNT 20 41#define QLC_83XX_NO_NIC_RESOURCE 0x5 42#define QLC_83XX_MAC_PRESENT 0xC 43#define QLC_83XX_MAC_ABSENT 0xD 44 45 46#define QLC_83XX_FLASH_SECTOR_SIZE (64 * 1024) 47 48/* PEG status definitions */ 49#define QLC_83XX_CMDPEG_COMPLETE 0xff01 50#define QLC_83XX_VALID_INTX_BIT30(val) ((val) & BIT_30) 51#define QLC_83XX_VALID_INTX_BIT31(val) ((val) & BIT_31) 52#define QLC_83XX_INTX_FUNC(val) ((val) & 0xFF) 53#define QLC_83XX_LEGACY_INTX_MAX_RETRY 100 54#define QLC_83XX_LEGACY_INTX_DELAY 4 55#define QLC_83XX_REG_DESC 1 56#define QLC_83XX_LRO_DESC 2 57#define QLC_83XX_CTRL_DESC 3 58#define QLC_83XX_FW_CAPABILITY_TSO BIT_6 59#define QLC_83XX_FW_CAP_LRO_MSS BIT_17 60#define QLC_83XX_HOST_RDS_MODE_UNIQUE 0 61#define QLC_83XX_HOST_SDS_MBX_IDX 8 62 63#define QLCNIC_HOST_RDS_MBX_IDX 88 64#define QLCNIC_MAX_RING_SETS 8 65 66/* Pause control registers */ 67#define QLC_83XX_SRE_SHIM_REG 0x0D200284 68#define QLC_83XX_PORT0_THRESHOLD 0x0B2003A4 69#define QLC_83XX_PORT1_THRESHOLD 0x0B2013A4 70#define QLC_83XX_PORT0_TC_MC_REG 0x0B200388 71#define QLC_83XX_PORT1_TC_MC_REG 0x0B201388 72#define QLC_83XX_PORT0_TC_STATS 0x0B20039C 73#define QLC_83XX_PORT1_TC_STATS 0x0B20139C 74#define QLC_83XX_PORT2_IFB_THRESHOLD 0x0B200704 75#define QLC_83XX_PORT3_IFB_THRESHOLD 0x0B201704 76 77/* Peg PC status registers */ 78#define QLC_83XX_CRB_PEG_NET_0 0x3400003c 79#define QLC_83XX_CRB_PEG_NET_1 0x3410003c 80#define QLC_83XX_CRB_PEG_NET_2 0x3420003c 81#define QLC_83XX_CRB_PEG_NET_3 0x3430003c 82#define QLC_83XX_CRB_PEG_NET_4 0x34b0003c 83 84/* Firmware image definitions */ 85#define QLC_83XX_BOOTLOADER_FLASH_ADDR 0x10000 86#define QLC_83XX_FW_FILE_NAME "83xx_fw.bin" 87#define QLC_83XX_BOOT_FROM_FLASH 0 88#define QLC_83XX_BOOT_FROM_FILE 0x12345678 89 90#define QLC_83XX_MAX_RESET_SEQ_ENTRIES 16 91 92#define QLC_83XX_MBX_POST_BC_OP 0x1 93#define QLC_83XX_MBX_COMPLETION 0x0 94#define QLC_83XX_MBX_REQUEST 0x1 95 96#define QLC_83XX_MBX_TIMEOUT (5 * HZ) 97#define QLC_83XX_MBX_CMD_LOOP 5000000 98 99/* status descriptor mailbox data 100 * @phy_addr_{low|high}: physical address of buffer 101 * @sds_ring_size: buffer size 102 * @intrpt_id: interrupt id 103 * @intrpt_val: source of interrupt 104 */ 105struct qlcnic_sds_mbx { 106 u32 phy_addr_low; 107 u32 phy_addr_high; 108 u32 rsvd1[4]; 109#if defined(__LITTLE_ENDIAN) 110 u16 sds_ring_size; 111 u16 rsvd2; 112 u16 rsvd3[2]; 113 u16 intrpt_id; 114 u8 intrpt_val; 115 u8 rsvd4; 116#elif defined(__BIG_ENDIAN) 117 u16 rsvd2; 118 u16 sds_ring_size; 119 u16 rsvd3[2]; 120 u8 rsvd4; 121 u8 intrpt_val; 122 u16 intrpt_id; 123#endif 124 u32 rsvd5; 125} __packed; 126 127/* receive descriptor buffer data 128 * phy_addr_reg_{low|high}: physical address of regular buffer 129 * phy_addr_jmb_{low|high}: physical address of jumbo buffer 130 * reg_ring_sz: size of regular buffer 131 * reg_ring_len: no. of entries in regular buffer 132 * jmb_ring_len: no. of entries in jumbo buffer 133 * jmb_ring_sz: size of jumbo buffer 134 */ 135struct qlcnic_rds_mbx { 136 u32 phy_addr_reg_low; 137 u32 phy_addr_reg_high; 138 u32 phy_addr_jmb_low; 139 u32 phy_addr_jmb_high; 140#if defined(__LITTLE_ENDIAN) 141 u16 reg_ring_sz; 142 u16 reg_ring_len; 143 u16 jmb_ring_sz; 144 u16 jmb_ring_len; 145#elif defined(__BIG_ENDIAN) 146 u16 reg_ring_len; 147 u16 reg_ring_sz; 148 u16 jmb_ring_len; 149 u16 jmb_ring_sz; 150#endif 151} __packed; 152 153/* host producers for regular and jumbo rings */ 154struct __host_producer_mbx { 155 u32 reg_buf; 156 u32 jmb_buf; 157} __packed; 158 159/* Receive context mailbox data outbox registers 160 * @state: state of the context 161 * @vport_id: virtual port id 162 * @context_id: receive context id 163 * @num_pci_func: number of pci functions of the port 164 * @phy_port: physical port id 165 */ 166struct qlcnic_rcv_mbx_out { 167#if defined(__LITTLE_ENDIAN) 168 u8 rcv_num; 169 u8 sts_num; 170 u16 ctx_id; 171 u8 state; 172 u8 num_pci_func; 173 u8 phy_port; 174 u8 vport_id; 175#elif defined(__BIG_ENDIAN) 176 u16 ctx_id; 177 u8 sts_num; 178 u8 rcv_num; 179 u8 vport_id; 180 u8 phy_port; 181 u8 num_pci_func; 182 u8 state; 183#endif 184 u32 host_csmr[QLCNIC_MAX_RING_SETS]; 185 struct __host_producer_mbx host_prod[QLCNIC_MAX_RING_SETS]; 186} __packed; 187 188struct qlcnic_add_rings_mbx_out { 189#if defined(__LITTLE_ENDIAN) 190 u8 rcv_num; 191 u8 sts_num; 192 u16 ctx_id; 193#elif defined(__BIG_ENDIAN) 194 u16 ctx_id; 195 u8 sts_num; 196 u8 rcv_num; 197#endif 198 u32 host_csmr[QLCNIC_MAX_RING_SETS]; 199 struct __host_producer_mbx host_prod[QLCNIC_MAX_RING_SETS]; 200} __packed; 201 202/* Transmit context mailbox inbox registers 203 * @phys_addr_{low|high}: DMA address of the transmit buffer 204 * @cnsmr_index_{low|high}: host consumer index 205 * @size: legth of transmit buffer ring 206 * @intr_id: interrput id 207 * @src: src of interrupt 208 */ 209struct qlcnic_tx_mbx { 210 u32 phys_addr_low; 211 u32 phys_addr_high; 212 u32 cnsmr_index_low; 213 u32 cnsmr_index_high; 214#if defined(__LITTLE_ENDIAN) 215 u16 size; 216 u16 intr_id; 217 u8 src; 218 u8 rsvd[3]; 219#elif defined(__BIG_ENDIAN) 220 u16 intr_id; 221 u16 size; 222 u8 rsvd[3]; 223 u8 src; 224#endif 225} __packed; 226 227/* Transmit context mailbox outbox registers 228 * @host_prod: host producer index 229 * @ctx_id: transmit context id 230 * @state: state of the transmit context 231 */ 232 233struct qlcnic_tx_mbx_out { 234 u32 host_prod; 235#if defined(__LITTLE_ENDIAN) 236 u16 ctx_id; 237 u8 state; 238 u8 rsvd; 239#elif defined(__BIG_ENDIAN) 240 u8 rsvd; 241 u8 state; 242 u16 ctx_id; 243#endif 244} __packed; 245 246struct qlcnic_intrpt_config { 247 u8 type; 248 u8 enabled; 249 u16 id; 250 u32 src; 251}; 252 253struct qlcnic_macvlan_mbx { 254#if defined(__LITTLE_ENDIAN) 255 u8 mac_addr0; 256 u8 mac_addr1; 257 u8 mac_addr2; 258 u8 mac_addr3; 259 u8 mac_addr4; 260 u8 mac_addr5; 261 u16 vlan; 262#elif defined(__BIG_ENDIAN) 263 u8 mac_addr3; 264 u8 mac_addr2; 265 u8 mac_addr1; 266 u8 mac_addr0; 267 u16 vlan; 268 u8 mac_addr5; 269 u8 mac_addr4; 270#endif 271}; 272 273struct qlc_83xx_fw_info { 274 const struct firmware *fw; 275 u16 major_fw_version; 276 u8 minor_fw_version; 277 u8 sub_fw_version; 278 u8 fw_build_num; 279 u8 load_from_file; 280}; 281 282struct qlc_83xx_reset { 283 struct qlc_83xx_reset_hdr *hdr; 284 int seq_index; 285 int seq_error; 286 int array_index; 287 u32 array[QLC_83XX_MAX_RESET_SEQ_ENTRIES]; 288 u8 *buff; 289 u8 *stop_offset; 290 u8 *start_offset; 291 u8 *init_offset; 292 u8 seq_end; 293 u8 template_end; 294}; 295 296#define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY 0x1 297#define QLC_83XX_IDC_GRACEFULL_RESET 0x2 298#define QLC_83XX_IDC_TIMESTAMP 0 299#define QLC_83XX_IDC_DURATION 1 300#define QLC_83XX_IDC_INIT_TIMEOUT_SECS 30 301#define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS 10 302#define QLC_83XX_IDC_RESET_TIMEOUT_SECS 10 303#define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS 20 304#define QLC_83XX_IDC_FW_POLL_DELAY (1 * HZ) 305#define QLC_83XX_IDC_FW_FAIL_THRESH 2 306#define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO 8 307#define QLC_83XX_IDC_MAX_CNA_FUNCTIONS 16 308#define QLC_83XX_IDC_MAJOR_VERSION 1 309#define QLC_83XX_IDC_MINOR_VERSION 0 310#define QLC_83XX_IDC_FLASH_PARAM_ADDR 0x3e8020 311 312struct qlcnic_adapter; 313struct qlc_83xx_idc { 314 int (*state_entry) (struct qlcnic_adapter *); 315 u64 sec_counter; 316 u64 delay; 317 unsigned long status; 318 int err_code; 319 int collect_dump; 320 u8 curr_state; 321 u8 prev_state; 322 u8 vnic_state; 323 u8 vnic_wait_limit; 324 u8 quiesce_req; 325 u8 delay_reset; 326 char **name; 327}; 328 329/* Device States */ 330enum qlcnic_83xx_states { 331 QLC_83XX_IDC_DEV_UNKNOWN, 332 QLC_83XX_IDC_DEV_COLD, 333 QLC_83XX_IDC_DEV_INIT, 334 QLC_83XX_IDC_DEV_READY, 335 QLC_83XX_IDC_DEV_NEED_RESET, 336 QLC_83XX_IDC_DEV_NEED_QUISCENT, 337 QLC_83XX_IDC_DEV_FAILED, 338 QLC_83XX_IDC_DEV_QUISCENT 339}; 340 341#define QLCNIC_MBX_RSP(reg) LSW(reg) 342#define QLCNIC_MBX_NUM_REGS(reg) (MSW(reg) & 0x1FF) 343#define QLCNIC_MBX_STATUS(reg) (((reg) >> 25) & 0x7F) 344#define QLCNIC_MBX_HOST(ahw, i) ((ahw)->pci_base0 + ((i) * 4)) 345#define QLCNIC_MBX_FW(ahw, i) ((ahw)->pci_base0 + 0x800 + ((i) * 4)) 346 347/* Mailbox process AEN count */ 348#define QLC_83XX_IDC_COMP_AEN 3 349#define QLC_83XX_MBX_AEN_CNT 5 350#define QLC_83XX_MODULE_LOADED 1 351#define QLC_83XX_MBX_READY 2 352#define QLC_83XX_MBX_AEN_ACK 3 353#define QLC_83XX_SFP_PRESENT(data) ((data) & 3) 354#define QLC_83XX_SFP_ERR(data) (((data) >> 2) & 3) 355#define QLC_83XX_SFP_MODULE_TYPE(data) (((data) >> 4) & 0x1F) 356#define QLC_83XX_SFP_CU_LENGTH(data) (LSB((data) >> 16)) 357#define QLC_83XX_SFP_TX_FAULT(data) ((data) & BIT_10) 358#define QLC_83XX_SFP_10G_CAPABLE(data) ((data) & BIT_11) 359#define QLC_83XX_LINK_STATS(data) ((data) & BIT_0) 360#define QLC_83XX_CURRENT_LINK_SPEED(data) (((data) >> 3) & 7) 361#define QLC_83XX_LINK_PAUSE(data) (((data) >> 6) & 3) 362#define QLC_83XX_LINK_LB(data) (((data) >> 8) & 7) 363#define QLC_83XX_LINK_FEC(data) ((data) & BIT_12) 364#define QLC_83XX_LINK_EEE(data) ((data) & BIT_13) 365#define QLC_83XX_DCBX(data) (((data) >> 28) & 7) 366#define QLC_83XX_AUTONEG(data) ((data) & BIT_15) 367#define QLC_83XX_CFG_STD_PAUSE (1 << 5) 368#define QLC_83XX_CFG_STD_TX_PAUSE (1 << 20) 369#define QLC_83XX_CFG_STD_RX_PAUSE (2 << 20) 370#define QLC_83XX_CFG_STD_TX_RX_PAUSE (3 << 20) 371#define QLC_83XX_ENABLE_AUTONEG (1 << 15) 372#define QLC_83XX_CFG_LOOPBACK_HSS (2 << 1) 373#define QLC_83XX_CFG_LOOPBACK_PHY (3 << 1) 374#define QLC_83XX_CFG_LOOPBACK_EXT (4 << 1) 375 376/* LED configuration settings */ 377#define QLC_83XX_ENABLE_BEACON 0xe 378#define QLC_83XX_LED_RATE 0xff 379#define QLC_83XX_LED_ACT (1 << 10) 380#define QLC_83XX_LED_MOD (0 << 13) 381#define QLC_83XX_LED_CONFIG (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \ 382 QLC_83XX_LED_MOD) 383 384#define QLC_83XX_10M_LINK 1 385#define QLC_83XX_100M_LINK 2 386#define QLC_83XX_1G_LINK 3 387#define QLC_83XX_10G_LINK 4 388#define QLC_83XX_STAT_TX 3 389#define QLC_83XX_STAT_RX 2 390#define QLC_83XX_STAT_MAC 1 391#define QLC_83XX_TX_STAT_REGS 14 392#define QLC_83XX_RX_STAT_REGS 40 393#define QLC_83XX_MAC_STAT_REGS 94 394 395#define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2))) 396#define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2)) 397#define QLC_83XX_DEFAULT_OPMODE 0x55555555 398#define QLC_83XX_PRIVLEGED_FUNC 0x1 399#define QLC_83XX_VIRTUAL_FUNC 0x2 400 401#define QLC_83XX_LB_MAX_FILTERS 2048 402#define QLC_83XX_LB_BUCKET_SIZE 256 403#define QLC_83XX_MINIMUM_VECTOR 3 404#define QLC_83XX_MAX_MC_COUNT 38 405#define QLC_83XX_MAX_UC_COUNT 4096 406 407#define QLC_83XX_PVID_STRIP_CAPABILITY BIT_22 408#define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val) (val & 0x80000000) 409#define QLC_83XX_GET_LRO_CAPABILITY(val) (val & 0x20) 410#define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40) 411#define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40) 412#define QLC_83XX_GET_HW_LRO_CAPABILITY(val) (val & 0x400) 413#define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000) 414#define QLC_83XX_GET_FW_LRO_MSS_CAPABILITY(val) (val & 0x20000) 415#define QLC_83XX_VIRTUAL_NIC_MODE 0xFF 416#define QLC_83XX_DEFAULT_MODE 0x0 417#define QLC_83XX_SRIOV_MODE 0x1 418#define QLCNIC_BRDTYPE_83XX_10G 0x0083 419 420#define QLC_83XX_FLASH_SPI_STATUS 0x2808E010 421#define QLC_83XX_FLASH_SPI_CONTROL 0x2808E014 422#define QLC_83XX_FLASH_STATUS 0x42100004 423#define QLC_83XX_FLASH_CONTROL 0x42110004 424#define QLC_83XX_FLASH_ADDR 0x42110008 425#define QLC_83XX_FLASH_WRDATA 0x4211000C 426#define QLC_83XX_FLASH_RDDATA 0x42110018 427#define QLC_83XX_FLASH_DIRECT_WINDOW 0x42110030 428#define QLC_83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA)) 429#define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef 430#define QLC_83XX_FLASH_WRITE_CMD 0xdacdacda 431#define QLC_83XX_FLASH_BULK_WRITE_CMD 0xcadcadca 432#define QLC_83XX_FLASH_READ_RETRY_COUNT 5000 433#define QLC_83XX_FLASH_STATUS_READY 0x6 434#define QLC_83XX_FLASH_WRITE_MIN 2 435#define QLC_83XX_FLASH_WRITE_MAX 64 436#define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY 1 437#define QLC_83XX_ERASE_MODE 1 438#define QLC_83XX_WRITE_MODE 2 439#define QLC_83XX_BULK_WRITE_MODE 3 440#define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG 0xFD0100 441#define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG 0xFD0300 442#define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL 0xFD009F 443#define QLC_83XX_FLASH_OEM_ERASE_SIG 0xFD03D8 444#define QLC_83XX_FLASH_OEM_WRITE_SIG 0xFD0101 445#define QLC_83XX_FLASH_OEM_READ_SIG 0xFD0005 446#define QLC_83XX_FLASH_ADDR_TEMP_VAL 0x00800000 447#define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL 0x00800001 448#define QLC_83XX_FLASH_WRDATA_DEF 0x0 449#define QLC_83XX_FLASH_READ_CTRL 0x3F 450#define QLC_83XX_FLASH_SPI_CTRL 0x4 451#define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL 0x2 452#define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL 0x5 453#define QLC_83XX_FLASH_LAST_ERASE_MS_VAL 0x3D 454#define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43 455#define QLC_83XX_FLASH_SECOND_MS_PATTERN 0x7F 456#define QLC_83XX_FLASH_LAST_MS_PATTERN 0x7D 457#define QLC_83xx_FLASH_MAX_WAIT_USEC 100 458#define QLC_83XX_FLASH_LOCK_TIMEOUT 10000 459 460enum qlc_83xx_mbx_cmd_type { 461 QLC_83XX_MBX_CMD_WAIT = 0, 462 QLC_83XX_MBX_CMD_NO_WAIT, 463 QLC_83XX_MBX_CMD_BUSY_WAIT, 464}; 465 466enum qlc_83xx_mbx_response_states { 467 QLC_83XX_MBX_RESPONSE_WAIT = 0, 468 QLC_83XX_MBX_RESPONSE_ARRIVED, 469}; 470 471#define QLC_83XX_MBX_RESPONSE_FAILED 0x2 472#define QLC_83XX_MBX_RESPONSE_UNKNOWN 0x3 473 474/* Additional registers in 83xx */ 475enum qlc_83xx_ext_regs { 476 QLCNIC_GLOBAL_RESET = 0, 477 QLCNIC_WILDCARD, 478 QLCNIC_INFORMANT, 479 QLCNIC_HOST_MBX_CTRL, 480 QLCNIC_FW_MBX_CTRL, 481 QLCNIC_BOOTLOADER_ADDR, 482 QLCNIC_BOOTLOADER_SIZE, 483 QLCNIC_FW_IMAGE_ADDR, 484 QLCNIC_MBX_INTR_ENBL, 485 QLCNIC_DEF_INT_MASK, 486 QLCNIC_DEF_INT_ID, 487 QLC_83XX_IDC_MAJ_VERSION, 488 QLC_83XX_IDC_DEV_STATE, 489 QLC_83XX_IDC_DRV_PRESENCE, 490 QLC_83XX_IDC_DRV_ACK, 491 QLC_83XX_IDC_CTRL, 492 QLC_83XX_IDC_DRV_AUDIT, 493 QLC_83XX_IDC_MIN_VERSION, 494 QLC_83XX_RECOVER_DRV_LOCK, 495 QLC_83XX_IDC_PF_0, 496 QLC_83XX_IDC_PF_1, 497 QLC_83XX_IDC_PF_2, 498 QLC_83XX_IDC_PF_3, 499 QLC_83XX_IDC_PF_4, 500 QLC_83XX_IDC_PF_5, 501 QLC_83XX_IDC_PF_6, 502 QLC_83XX_IDC_PF_7, 503 QLC_83XX_IDC_PF_8, 504 QLC_83XX_IDC_PF_9, 505 QLC_83XX_IDC_PF_10, 506 QLC_83XX_IDC_PF_11, 507 QLC_83XX_IDC_PF_12, 508 QLC_83XX_IDC_PF_13, 509 QLC_83XX_IDC_PF_14, 510 QLC_83XX_IDC_PF_15, 511 QLC_83XX_IDC_DEV_PARTITION_INFO_1, 512 QLC_83XX_IDC_DEV_PARTITION_INFO_2, 513 QLC_83XX_DRV_OP_MODE, 514 QLC_83XX_VNIC_STATE, 515 QLC_83XX_DRV_LOCK, 516 QLC_83XX_DRV_UNLOCK, 517 QLC_83XX_DRV_LOCK_ID, 518 QLC_83XX_ASIC_TEMP, 519}; 520 521/* 83xx funcitons */ 522int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *); 523int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *, struct qlcnic_cmd_args *); 524int qlcnic_83xx_setup_intr(struct qlcnic_adapter *, u8); 525void qlcnic_83xx_get_func_no(struct qlcnic_adapter *); 526int qlcnic_83xx_cam_lock(struct qlcnic_adapter *); 527void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *); 528int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32); 529void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *); 530void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *); 531void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t); 532void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t); 533int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong, int *); 534int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32); 535void qlcnic_83xx_process_rcv_diag(struct qlcnic_adapter *, int, u64 []); 536int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32); 537int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8); 538int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8); 539int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int); 540int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int); 541int qlcnic_83xx_config_intr_coalesce(struct qlcnic_adapter *); 542void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *, u64 *, u16); 543int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *); 544int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *); 545void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *, int); 546 547int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *); 548void qlcnic_83xx_napi_del(struct qlcnic_adapter *); 549void qlcnic_83xx_napi_enable(struct qlcnic_adapter *); 550void qlcnic_83xx_napi_disable(struct qlcnic_adapter *); 551int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32); 552void qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32); 553int qlcnic_ind_rd(struct qlcnic_adapter *, u32); 554int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *); 555int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *, 556 struct qlcnic_host_tx_ring *, int); 557void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *); 558void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *, 559 struct qlcnic_host_tx_ring *); 560int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8); 561int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int); 562void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *); 563int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool); 564int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8); 565int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *); 566void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8, 567 struct qlcnic_cmd_args *); 568int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *, 569 struct qlcnic_adapter *, u32); 570void qlcnic_free_mbx_args(struct qlcnic_cmd_args *); 571void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *, 572 struct qlcnic_info *); 573void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *); 574irqreturn_t qlcnic_83xx_handle_aen(int, void *); 575int qlcnic_83xx_get_port_info(struct qlcnic_adapter *); 576void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *); 577void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *); 578irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *); 579irqreturn_t qlcnic_83xx_intr(int, void *); 580irqreturn_t qlcnic_83xx_tmp_intr(int, void *); 581void qlcnic_83xx_enable_intr(struct qlcnic_adapter *, 582 struct qlcnic_host_sds_ring *); 583void qlcnic_83xx_disable_intr(struct qlcnic_adapter *, 584 struct qlcnic_host_sds_ring *); 585void qlcnic_83xx_check_vf(struct qlcnic_adapter *, 586 const struct pci_device_id *); 587void __qlcnic_83xx_process_aen(struct qlcnic_adapter *); 588int qlcnic_83xx_get_port_config(struct qlcnic_adapter *); 589int qlcnic_83xx_set_port_config(struct qlcnic_adapter *); 590int qlcnic_enable_eswitch(struct qlcnic_adapter *, u8, u8); 591int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *); 592int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *); 593int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *); 594void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *); 595void qlcnic_83xx_register_map(struct qlcnic_hardware_context *); 596void qlcnic_83xx_idc_aen_work(struct work_struct *); 597void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int); 598 599int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32); 600int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int); 601int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *); 602int qlcnic_83xx_lock_flash(struct qlcnic_adapter *); 603void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *); 604int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *); 605int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int); 606int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *); 607int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *); 608int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int); 609int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *, 610 u32, u8 *, int); 611int qlcnic_83xx_init(struct qlcnic_adapter *, int); 612int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *); 613int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev); 614void qlcnic_83xx_idc_poll_dev_state(struct work_struct *); 615int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *); 616void qlcnic_83xx_idc_exit(struct qlcnic_adapter *); 617void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32); 618int qlcnic_83xx_lock_driver(struct qlcnic_adapter *); 619void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *); 620int qlcnic_83xx_set_default_offload_settings(struct qlcnic_adapter *); 621int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32); 622int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *); 623int qlcnic_83xx_enable_vnic_mode(struct qlcnic_adapter *, int); 624int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *, int); 625int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *); 626int qlcnic_83xx_get_vnic_vport_info(struct qlcnic_adapter *, 627 struct qlcnic_info *, u8); 628int qlcnic_83xx_get_vnic_pf_info(struct qlcnic_adapter *, struct qlcnic_info *); 629 630void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *); 631void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data); 632int qlcnic_83xx_get_settings(struct qlcnic_adapter *, struct ethtool_cmd *); 633int qlcnic_83xx_set_settings(struct qlcnic_adapter *, struct ethtool_cmd *); 634void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *, 635 struct ethtool_pauseparam *); 636int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *, 637 struct ethtool_pauseparam *); 638int qlcnic_83xx_test_link(struct qlcnic_adapter *); 639int qlcnic_83xx_reg_test(struct qlcnic_adapter *); 640int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *); 641int qlcnic_83xx_get_registers(struct qlcnic_adapter *, u32 *); 642int qlcnic_83xx_loopback_test(struct net_device *, u8); 643int qlcnic_83xx_interrupt_test(struct net_device *); 644int qlcnic_83xx_set_led(struct net_device *, enum ethtool_phys_id_state); 645int qlcnic_83xx_flash_test(struct qlcnic_adapter *); 646int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *); 647int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *); 648void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *); 649void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *); 650void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *); 651int qlcnic_83xx_shutdown(struct pci_dev *); 652int qlcnic_83xx_resume(struct qlcnic_adapter *); 653int qlcnic_83xx_idc_init(struct qlcnic_adapter *); 654int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *); 655int qlcnic_83xx_set_vnic_opmode(struct qlcnic_adapter *); 656int qlcnic_83xx_check_vnic_state(struct qlcnic_adapter *); 657#endif 658