qlcnic_83xx_hw.h revision a04315893db0dbdf490e2d284d3aef0f01762b54
1/* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8#ifndef __QLCNIC_83XX_HW_H 9#define __QLCNIC_83XX_HW_H 10 11#include <linux/types.h> 12#include <linux/etherdevice.h> 13#include "qlcnic_hw.h" 14 15#define QLCNIC_83XX_BAR0_LENGTH 0x4000 16 17/* Directly mapped registers */ 18#define QLC_83XX_CRB_WIN_BASE 0x3800 19#define QLC_83XX_CRB_WIN_FUNC(f) (QLC_83XX_CRB_WIN_BASE+((f)*4)) 20#define QLC_83XX_SEM_LOCK_BASE 0x3840 21#define QLC_83XX_SEM_UNLOCK_BASE 0x3844 22#define QLC_83XX_SEM_LOCK_FUNC(f) (QLC_83XX_SEM_LOCK_BASE+((f)*8)) 23#define QLC_83XX_SEM_UNLOCK_FUNC(f) (QLC_83XX_SEM_UNLOCK_BASE+((f)*8)) 24#define QLC_83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0)) 25#define QLC_83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4)) 26#define QLC_83XX_LINK_SPEED_FACTOR 10 27#define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4))) 28#define QLC_83XX_INTX_PTR 0x38C0 29#define QLC_83XX_INTX_TRGR 0x38C4 30#define QLC_83XX_INTX_MASK 0x38C8 31 32#define QLC_83XX_DRV_LOCK_WAIT_COUNTER 100 33#define QLC_83XX_DRV_LOCK_WAIT_DELAY 20 34#define QLC_83XX_NEED_DRV_LOCK_RECOVERY 1 35#define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS 2 36#define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT 3 37#define QLC_83XX_DRV_LOCK_RECOVERY_DELAY 200 38#define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK 0x3 39#define QLC_83XX_LB_WAIT_COUNT 250 40#define QLC_83XX_LB_MSLEEP_COUNT 20 41#define QLC_83XX_NO_NIC_RESOURCE 0x5 42#define QLC_83XX_MAC_PRESENT 0xC 43#define QLC_83XX_MAC_ABSENT 0xD 44 45 46#define QLC_83XX_FLASH_SECTOR_SIZE (64 * 1024) 47 48/* PEG status definitions */ 49#define QLC_83XX_CMDPEG_COMPLETE 0xff01 50#define QLC_83XX_VALID_INTX_BIT30(val) ((val) & BIT_30) 51#define QLC_83XX_VALID_INTX_BIT31(val) ((val) & BIT_31) 52#define QLC_83XX_INTX_FUNC(val) ((val) & 0xFF) 53#define QLC_83XX_LEGACY_INTX_MAX_RETRY 100 54#define QLC_83XX_LEGACY_INTX_DELAY 4 55#define QLC_83XX_REG_DESC 1 56#define QLC_83XX_LRO_DESC 2 57#define QLC_83XX_CTRL_DESC 3 58#define QLC_83XX_FW_CAPABILITY_TSO BIT_6 59#define QLC_83XX_FW_CAP_LRO_MSS BIT_17 60#define QLC_83XX_HOST_RDS_MODE_UNIQUE 0 61#define QLC_83XX_HOST_SDS_MBX_IDX 8 62 63#define QLCNIC_HOST_RDS_MBX_IDX 88 64 65/* Pause control registers */ 66#define QLC_83XX_SRE_SHIM_REG 0x0D200284 67#define QLC_83XX_PORT0_THRESHOLD 0x0B2003A4 68#define QLC_83XX_PORT1_THRESHOLD 0x0B2013A4 69#define QLC_83XX_PORT0_TC_MC_REG 0x0B200388 70#define QLC_83XX_PORT1_TC_MC_REG 0x0B201388 71#define QLC_83XX_PORT0_TC_STATS 0x0B20039C 72#define QLC_83XX_PORT1_TC_STATS 0x0B20139C 73#define QLC_83XX_PORT2_IFB_THRESHOLD 0x0B200704 74#define QLC_83XX_PORT3_IFB_THRESHOLD 0x0B201704 75 76/* Peg PC status registers */ 77#define QLC_83XX_CRB_PEG_NET_0 0x3400003c 78#define QLC_83XX_CRB_PEG_NET_1 0x3410003c 79#define QLC_83XX_CRB_PEG_NET_2 0x3420003c 80#define QLC_83XX_CRB_PEG_NET_3 0x3430003c 81#define QLC_83XX_CRB_PEG_NET_4 0x34b0003c 82 83/* Firmware image definitions */ 84#define QLC_83XX_BOOTLOADER_FLASH_ADDR 0x10000 85#define QLC_83XX_FW_FILE_NAME "83xx_fw.bin" 86#define QLC_84XX_FW_FILE_NAME "84xx_fw.bin" 87#define QLC_83XX_BOOT_FROM_FLASH 0 88#define QLC_83XX_BOOT_FROM_FILE 0x12345678 89 90#define QLC_FW_FILE_NAME_LEN 20 91#define QLC_83XX_MAX_RESET_SEQ_ENTRIES 16 92 93#define QLC_83XX_MBX_POST_BC_OP 0x1 94#define QLC_83XX_MBX_COMPLETION 0x0 95#define QLC_83XX_MBX_REQUEST 0x1 96 97#define QLC_83XX_MBX_TIMEOUT (5 * HZ) 98#define QLC_83XX_MBX_CMD_LOOP 5000000 99 100/* status descriptor mailbox data 101 * @phy_addr_{low|high}: physical address of buffer 102 * @sds_ring_size: buffer size 103 * @intrpt_id: interrupt id 104 * @intrpt_val: source of interrupt 105 */ 106struct qlcnic_sds_mbx { 107 u32 phy_addr_low; 108 u32 phy_addr_high; 109 u32 rsvd1[4]; 110#if defined(__LITTLE_ENDIAN) 111 u16 sds_ring_size; 112 u16 rsvd2; 113 u16 rsvd3[2]; 114 u16 intrpt_id; 115 u8 intrpt_val; 116 u8 rsvd4; 117#elif defined(__BIG_ENDIAN) 118 u16 rsvd2; 119 u16 sds_ring_size; 120 u16 rsvd3[2]; 121 u8 rsvd4; 122 u8 intrpt_val; 123 u16 intrpt_id; 124#endif 125 u32 rsvd5; 126} __packed; 127 128/* receive descriptor buffer data 129 * phy_addr_reg_{low|high}: physical address of regular buffer 130 * phy_addr_jmb_{low|high}: physical address of jumbo buffer 131 * reg_ring_sz: size of regular buffer 132 * reg_ring_len: no. of entries in regular buffer 133 * jmb_ring_len: no. of entries in jumbo buffer 134 * jmb_ring_sz: size of jumbo buffer 135 */ 136struct qlcnic_rds_mbx { 137 u32 phy_addr_reg_low; 138 u32 phy_addr_reg_high; 139 u32 phy_addr_jmb_low; 140 u32 phy_addr_jmb_high; 141#if defined(__LITTLE_ENDIAN) 142 u16 reg_ring_sz; 143 u16 reg_ring_len; 144 u16 jmb_ring_sz; 145 u16 jmb_ring_len; 146#elif defined(__BIG_ENDIAN) 147 u16 reg_ring_len; 148 u16 reg_ring_sz; 149 u16 jmb_ring_len; 150 u16 jmb_ring_sz; 151#endif 152} __packed; 153 154/* host producers for regular and jumbo rings */ 155struct __host_producer_mbx { 156 u32 reg_buf; 157 u32 jmb_buf; 158} __packed; 159 160/* Receive context mailbox data outbox registers 161 * @state: state of the context 162 * @vport_id: virtual port id 163 * @context_id: receive context id 164 * @num_pci_func: number of pci functions of the port 165 * @phy_port: physical port id 166 */ 167struct qlcnic_rcv_mbx_out { 168#if defined(__LITTLE_ENDIAN) 169 u8 rcv_num; 170 u8 sts_num; 171 u16 ctx_id; 172 u8 state; 173 u8 num_pci_func; 174 u8 phy_port; 175 u8 vport_id; 176#elif defined(__BIG_ENDIAN) 177 u16 ctx_id; 178 u8 sts_num; 179 u8 rcv_num; 180 u8 vport_id; 181 u8 phy_port; 182 u8 num_pci_func; 183 u8 state; 184#endif 185 u32 host_csmr[QLCNIC_MAX_SDS_RINGS]; 186 struct __host_producer_mbx host_prod[QLCNIC_MAX_SDS_RINGS]; 187} __packed; 188 189struct qlcnic_add_rings_mbx_out { 190#if defined(__LITTLE_ENDIAN) 191 u8 rcv_num; 192 u8 sts_num; 193 u16 ctx_id; 194#elif defined(__BIG_ENDIAN) 195 u16 ctx_id; 196 u8 sts_num; 197 u8 rcv_num; 198#endif 199 u32 host_csmr[QLCNIC_MAX_SDS_RINGS]; 200 struct __host_producer_mbx host_prod[QLCNIC_MAX_SDS_RINGS]; 201} __packed; 202 203/* Transmit context mailbox inbox registers 204 * @phys_addr_{low|high}: DMA address of the transmit buffer 205 * @cnsmr_index_{low|high}: host consumer index 206 * @size: legth of transmit buffer ring 207 * @intr_id: interrput id 208 * @src: src of interrupt 209 */ 210struct qlcnic_tx_mbx { 211 u32 phys_addr_low; 212 u32 phys_addr_high; 213 u32 cnsmr_index_low; 214 u32 cnsmr_index_high; 215#if defined(__LITTLE_ENDIAN) 216 u16 size; 217 u16 intr_id; 218 u8 src; 219 u8 rsvd[3]; 220#elif defined(__BIG_ENDIAN) 221 u16 intr_id; 222 u16 size; 223 u8 rsvd[3]; 224 u8 src; 225#endif 226} __packed; 227 228/* Transmit context mailbox outbox registers 229 * @host_prod: host producer index 230 * @ctx_id: transmit context id 231 * @state: state of the transmit context 232 */ 233 234struct qlcnic_tx_mbx_out { 235 u32 host_prod; 236#if defined(__LITTLE_ENDIAN) 237 u16 ctx_id; 238 u8 state; 239 u8 rsvd; 240#elif defined(__BIG_ENDIAN) 241 u8 rsvd; 242 u8 state; 243 u16 ctx_id; 244#endif 245} __packed; 246 247struct qlcnic_intrpt_config { 248 u8 type; 249 u8 enabled; 250 u16 id; 251 u32 src; 252}; 253 254struct qlcnic_macvlan_mbx { 255#if defined(__LITTLE_ENDIAN) 256 u8 mac_addr0; 257 u8 mac_addr1; 258 u8 mac_addr2; 259 u8 mac_addr3; 260 u8 mac_addr4; 261 u8 mac_addr5; 262 u16 vlan; 263#elif defined(__BIG_ENDIAN) 264 u8 mac_addr3; 265 u8 mac_addr2; 266 u8 mac_addr1; 267 u8 mac_addr0; 268 u16 vlan; 269 u8 mac_addr5; 270 u8 mac_addr4; 271#endif 272}; 273 274struct qlc_83xx_fw_info { 275 const struct firmware *fw; 276 char fw_file_name[QLC_FW_FILE_NAME_LEN]; 277}; 278 279struct qlc_83xx_reset { 280 struct qlc_83xx_reset_hdr *hdr; 281 int seq_index; 282 int seq_error; 283 int array_index; 284 u32 array[QLC_83XX_MAX_RESET_SEQ_ENTRIES]; 285 u8 *buff; 286 u8 *stop_offset; 287 u8 *start_offset; 288 u8 *init_offset; 289 u8 seq_end; 290 u8 template_end; 291}; 292 293#define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY 0x1 294#define QLC_83XX_IDC_GRACEFULL_RESET 0x2 295#define QLC_83XX_IDC_DISABLE_FW_DUMP 0x4 296#define QLC_83XX_IDC_TIMESTAMP 0 297#define QLC_83XX_IDC_DURATION 1 298#define QLC_83XX_IDC_INIT_TIMEOUT_SECS 30 299#define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS 10 300#define QLC_83XX_IDC_RESET_TIMEOUT_SECS 10 301#define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS 20 302#define QLC_83XX_IDC_FW_POLL_DELAY (1 * HZ) 303#define QLC_83XX_IDC_FW_FAIL_THRESH 2 304#define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO 8 305#define QLC_83XX_IDC_MAX_CNA_FUNCTIONS 16 306#define QLC_83XX_IDC_MAJOR_VERSION 1 307#define QLC_83XX_IDC_MINOR_VERSION 0 308#define QLC_83XX_IDC_FLASH_PARAM_ADDR 0x3e8020 309 310struct qlcnic_adapter; 311struct qlc_83xx_idc { 312 int (*state_entry) (struct qlcnic_adapter *); 313 u64 sec_counter; 314 u64 delay; 315 unsigned long status; 316 int err_code; 317 int collect_dump; 318 u8 curr_state; 319 u8 prev_state; 320 u8 vnic_state; 321 u8 vnic_wait_limit; 322 u8 quiesce_req; 323 u8 delay_reset; 324 char **name; 325}; 326 327enum qlcnic_vlan_operations { 328 QLC_VLAN_ADD = 0, 329 QLC_VLAN_DELETE 330}; 331 332/* Device States */ 333enum qlcnic_83xx_states { 334 QLC_83XX_IDC_DEV_UNKNOWN, 335 QLC_83XX_IDC_DEV_COLD, 336 QLC_83XX_IDC_DEV_INIT, 337 QLC_83XX_IDC_DEV_READY, 338 QLC_83XX_IDC_DEV_NEED_RESET, 339 QLC_83XX_IDC_DEV_NEED_QUISCENT, 340 QLC_83XX_IDC_DEV_FAILED, 341 QLC_83XX_IDC_DEV_QUISCENT 342}; 343 344#define QLCNIC_MBX_RSP(reg) LSW(reg) 345#define QLCNIC_MBX_NUM_REGS(reg) (MSW(reg) & 0x1FF) 346#define QLCNIC_MBX_STATUS(reg) (((reg) >> 25) & 0x7F) 347#define QLCNIC_MBX_HOST(ahw, i) ((ahw)->pci_base0 + ((i) * 4)) 348#define QLCNIC_MBX_FW(ahw, i) ((ahw)->pci_base0 + 0x800 + ((i) * 4)) 349 350/* Mailbox process AEN count */ 351#define QLC_83XX_IDC_COMP_AEN 3 352#define QLC_83XX_MBX_AEN_CNT 5 353#define QLC_83XX_MODULE_LOADED 1 354#define QLC_83XX_MBX_READY 2 355#define QLC_83XX_MBX_AEN_ACK 3 356#define QLC_83XX_SFP_PRESENT(data) ((data) & 3) 357#define QLC_83XX_SFP_ERR(data) (((data) >> 2) & 3) 358#define QLC_83XX_SFP_MODULE_TYPE(data) (((data) >> 4) & 0x1F) 359#define QLC_83XX_SFP_CU_LENGTH(data) (LSB((data) >> 16)) 360#define QLC_83XX_SFP_TX_FAULT(data) ((data) & BIT_10) 361#define QLC_83XX_SFP_10G_CAPABLE(data) ((data) & BIT_11) 362#define QLC_83XX_LINK_STATS(data) ((data) & BIT_0) 363#define QLC_83XX_CURRENT_LINK_SPEED(data) (((data) >> 3) & 7) 364#define QLC_83XX_LINK_PAUSE(data) (((data) >> 6) & 3) 365#define QLC_83XX_LINK_LB(data) (((data) >> 8) & 7) 366#define QLC_83XX_LINK_FEC(data) ((data) & BIT_12) 367#define QLC_83XX_LINK_EEE(data) ((data) & BIT_13) 368#define QLC_83XX_DCBX(data) (((data) >> 28) & 7) 369#define QLC_83XX_AUTONEG(data) ((data) & BIT_15) 370#define QLC_83XX_TX_PAUSE 0x10 371#define QLC_83XX_RX_PAUSE 0x20 372#define QLC_83XX_TX_RX_PAUSE 0x30 373#define QLC_83XX_CFG_STD_PAUSE (1 << 5) 374#define QLC_83XX_CFG_STD_TX_PAUSE (1 << 20) 375#define QLC_83XX_CFG_STD_RX_PAUSE (2 << 20) 376#define QLC_83XX_CFG_STD_TX_RX_PAUSE (3 << 20) 377#define QLC_83XX_ENABLE_AUTONEG (1 << 15) 378#define QLC_83XX_CFG_LOOPBACK_HSS (2 << 1) 379#define QLC_83XX_CFG_LOOPBACK_PHY (3 << 1) 380#define QLC_83XX_CFG_LOOPBACK_EXT (4 << 1) 381 382/* LED configuration settings */ 383#define QLC_83XX_ENABLE_BEACON 0xe 384#define QLC_83XX_BEACON_ON 1 385#define QLC_83XX_BEACON_OFF 0 386#define QLC_83XX_LED_RATE 0xff 387#define QLC_83XX_LED_ACT (1 << 10) 388#define QLC_83XX_LED_MOD (0 << 13) 389#define QLC_83XX_LED_CONFIG (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \ 390 QLC_83XX_LED_MOD) 391 392#define QLC_83XX_10M_LINK 1 393#define QLC_83XX_100M_LINK 2 394#define QLC_83XX_1G_LINK 3 395#define QLC_83XX_10G_LINK 4 396#define QLC_83XX_STAT_TX 3 397#define QLC_83XX_STAT_RX 2 398#define QLC_83XX_STAT_MAC 1 399#define QLC_83XX_TX_STAT_REGS 14 400#define QLC_83XX_RX_STAT_REGS 40 401#define QLC_83XX_MAC_STAT_REGS 94 402 403#define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2))) 404#define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2)) 405#define QLC_83XX_DEFAULT_OPMODE 0x55555555 406#define QLC_83XX_PRIVLEGED_FUNC 0x1 407#define QLC_83XX_VIRTUAL_FUNC 0x2 408 409#define QLC_83XX_LB_MAX_FILTERS 2048 410#define QLC_83XX_LB_BUCKET_SIZE 256 411#define QLC_83XX_MINIMUM_VECTOR 3 412#define QLC_83XX_MAX_MC_COUNT 38 413#define QLC_83XX_MAX_UC_COUNT 4096 414 415#define QLC_83XX_PVID_STRIP_CAPABILITY BIT_22 416#define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val) (val & 0x80000000) 417#define QLC_83XX_GET_LRO_CAPABILITY(val) (val & 0x20) 418#define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40) 419#define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40) 420#define QLC_83XX_GET_HW_LRO_CAPABILITY(val) (val & 0x400) 421#define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000) 422#define QLC_83XX_GET_FW_LRO_MSS_CAPABILITY(val) (val & 0x20000) 423#define QLC_83XX_ESWITCH_CAPABILITY BIT_23 424#define QLC_83XX_SRIOV_MODE 0x1 425#define QLCNIC_BRDTYPE_83XX_10G 0x0083 426 427#define QLC_83XX_FLASH_SPI_STATUS 0x2808E010 428#define QLC_83XX_FLASH_SPI_CONTROL 0x2808E014 429#define QLC_83XX_FLASH_STATUS 0x42100004 430#define QLC_83XX_FLASH_CONTROL 0x42110004 431#define QLC_83XX_FLASH_ADDR 0x42110008 432#define QLC_83XX_FLASH_WRDATA 0x4211000C 433#define QLC_83XX_FLASH_RDDATA 0x42110018 434#define QLC_83XX_FLASH_DIRECT_WINDOW 0x42110030 435#define QLC_83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA)) 436#define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef 437#define QLC_83XX_FLASH_WRITE_CMD 0xdacdacda 438#define QLC_83XX_FLASH_BULK_WRITE_CMD 0xcadcadca 439#define QLC_83XX_FLASH_READ_RETRY_COUNT 5000 440#define QLC_83XX_FLASH_STATUS_READY 0x6 441#define QLC_83XX_FLASH_WRITE_MIN 2 442#define QLC_83XX_FLASH_WRITE_MAX 64 443#define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY 1 444#define QLC_83XX_ERASE_MODE 1 445#define QLC_83XX_WRITE_MODE 2 446#define QLC_83XX_BULK_WRITE_MODE 3 447#define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG 0xFD0100 448#define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG 0xFD0300 449#define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL 0xFD009F 450#define QLC_83XX_FLASH_OEM_ERASE_SIG 0xFD03D8 451#define QLC_83XX_FLASH_OEM_WRITE_SIG 0xFD0101 452#define QLC_83XX_FLASH_OEM_READ_SIG 0xFD0005 453#define QLC_83XX_FLASH_ADDR_TEMP_VAL 0x00800000 454#define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL 0x00800001 455#define QLC_83XX_FLASH_WRDATA_DEF 0x0 456#define QLC_83XX_FLASH_READ_CTRL 0x3F 457#define QLC_83XX_FLASH_SPI_CTRL 0x4 458#define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL 0x2 459#define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL 0x5 460#define QLC_83XX_FLASH_LAST_ERASE_MS_VAL 0x3D 461#define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43 462#define QLC_83XX_FLASH_SECOND_MS_PATTERN 0x7F 463#define QLC_83XX_FLASH_LAST_MS_PATTERN 0x7D 464#define QLC_83xx_FLASH_MAX_WAIT_USEC 100 465#define QLC_83XX_FLASH_LOCK_TIMEOUT 10000 466 467enum qlc_83xx_mbx_cmd_type { 468 QLC_83XX_MBX_CMD_WAIT = 0, 469 QLC_83XX_MBX_CMD_NO_WAIT, 470 QLC_83XX_MBX_CMD_BUSY_WAIT, 471}; 472 473enum qlc_83xx_mbx_response_states { 474 QLC_83XX_MBX_RESPONSE_WAIT = 0, 475 QLC_83XX_MBX_RESPONSE_ARRIVED, 476}; 477 478#define QLC_83XX_MBX_RESPONSE_FAILED 0x2 479#define QLC_83XX_MBX_RESPONSE_UNKNOWN 0x3 480 481/* Additional registers in 83xx */ 482enum qlc_83xx_ext_regs { 483 QLCNIC_GLOBAL_RESET = 0, 484 QLCNIC_WILDCARD, 485 QLCNIC_INFORMANT, 486 QLCNIC_HOST_MBX_CTRL, 487 QLCNIC_FW_MBX_CTRL, 488 QLCNIC_BOOTLOADER_ADDR, 489 QLCNIC_BOOTLOADER_SIZE, 490 QLCNIC_FW_IMAGE_ADDR, 491 QLCNIC_MBX_INTR_ENBL, 492 QLCNIC_DEF_INT_MASK, 493 QLCNIC_DEF_INT_ID, 494 QLC_83XX_IDC_MAJ_VERSION, 495 QLC_83XX_IDC_DEV_STATE, 496 QLC_83XX_IDC_DRV_PRESENCE, 497 QLC_83XX_IDC_DRV_ACK, 498 QLC_83XX_IDC_CTRL, 499 QLC_83XX_IDC_DRV_AUDIT, 500 QLC_83XX_IDC_MIN_VERSION, 501 QLC_83XX_RECOVER_DRV_LOCK, 502 QLC_83XX_IDC_PF_0, 503 QLC_83XX_IDC_PF_1, 504 QLC_83XX_IDC_PF_2, 505 QLC_83XX_IDC_PF_3, 506 QLC_83XX_IDC_PF_4, 507 QLC_83XX_IDC_PF_5, 508 QLC_83XX_IDC_PF_6, 509 QLC_83XX_IDC_PF_7, 510 QLC_83XX_IDC_PF_8, 511 QLC_83XX_IDC_PF_9, 512 QLC_83XX_IDC_PF_10, 513 QLC_83XX_IDC_PF_11, 514 QLC_83XX_IDC_PF_12, 515 QLC_83XX_IDC_PF_13, 516 QLC_83XX_IDC_PF_14, 517 QLC_83XX_IDC_PF_15, 518 QLC_83XX_IDC_DEV_PARTITION_INFO_1, 519 QLC_83XX_IDC_DEV_PARTITION_INFO_2, 520 QLC_83XX_DRV_OP_MODE, 521 QLC_83XX_VNIC_STATE, 522 QLC_83XX_DRV_LOCK, 523 QLC_83XX_DRV_UNLOCK, 524 QLC_83XX_DRV_LOCK_ID, 525 QLC_83XX_ASIC_TEMP, 526}; 527 528/* Initialize/Stop NIC command bit definitions */ 529#define QLC_REGISTER_DCB_AEN BIT_1 530#define QLC_REGISTER_LB_IDC BIT_0 531#define QLC_INIT_FW_RESOURCES BIT_31 532 533/* 83xx funcitons */ 534int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *); 535int qlcnic_83xx_issue_cmd(struct qlcnic_adapter *, struct qlcnic_cmd_args *); 536int qlcnic_83xx_setup_intr(struct qlcnic_adapter *); 537void qlcnic_83xx_get_func_no(struct qlcnic_adapter *); 538int qlcnic_83xx_cam_lock(struct qlcnic_adapter *); 539void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *); 540int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32); 541void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *); 542void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *); 543void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t); 544void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t); 545int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong, int *); 546int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32); 547void qlcnic_83xx_process_rcv_diag(struct qlcnic_adapter *, int, u64 []); 548int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32); 549int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8); 550int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8); 551int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int); 552int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int); 553int qlcnic_83xx_config_intr_coalesce(struct qlcnic_adapter *); 554void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *, u64 *, u16); 555int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *); 556int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *); 557void qlcnic_83xx_initialize_nic(struct qlcnic_adapter *, int); 558 559int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *); 560void qlcnic_83xx_napi_del(struct qlcnic_adapter *); 561void qlcnic_83xx_napi_enable(struct qlcnic_adapter *); 562void qlcnic_83xx_napi_disable(struct qlcnic_adapter *); 563int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32); 564void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *); 565void qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32); 566int qlcnic_ind_rd(struct qlcnic_adapter *, u32); 567int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *); 568int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *, 569 struct qlcnic_host_tx_ring *, int); 570void qlcnic_83xx_del_rx_ctx(struct qlcnic_adapter *); 571void qlcnic_83xx_del_tx_ctx(struct qlcnic_adapter *, 572 struct qlcnic_host_tx_ring *); 573int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8); 574int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int); 575void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *); 576int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool); 577int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, u16, u8); 578int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *, u8); 579void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8, 580 struct qlcnic_cmd_args *); 581int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *, 582 struct qlcnic_adapter *, u32); 583void qlcnic_free_mbx_args(struct qlcnic_cmd_args *); 584void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *, 585 struct qlcnic_info *); 586void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *); 587irqreturn_t qlcnic_83xx_handle_aen(int, void *); 588int qlcnic_83xx_get_port_info(struct qlcnic_adapter *); 589void qlcnic_83xx_enable_mbx_interrupt(struct qlcnic_adapter *); 590void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *); 591irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *); 592irqreturn_t qlcnic_83xx_intr(int, void *); 593irqreturn_t qlcnic_83xx_tmp_intr(int, void *); 594void qlcnic_83xx_enable_intr(struct qlcnic_adapter *, 595 struct qlcnic_host_sds_ring *); 596void qlcnic_83xx_disable_intr(struct qlcnic_adapter *, 597 struct qlcnic_host_sds_ring *); 598void qlcnic_83xx_check_vf(struct qlcnic_adapter *, 599 const struct pci_device_id *); 600void __qlcnic_83xx_process_aen(struct qlcnic_adapter *); 601int qlcnic_83xx_get_port_config(struct qlcnic_adapter *); 602int qlcnic_83xx_set_port_config(struct qlcnic_adapter *); 603int qlcnic_enable_eswitch(struct qlcnic_adapter *, u8, u8); 604int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *); 605int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *); 606int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *); 607void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *); 608void qlcnic_83xx_register_map(struct qlcnic_hardware_context *); 609void qlcnic_83xx_idc_aen_work(struct work_struct *); 610void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int); 611 612int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32); 613int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int); 614int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *); 615int qlcnic_83xx_lock_flash(struct qlcnic_adapter *); 616void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *); 617int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *); 618int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int); 619int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *); 620int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *); 621int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int); 622int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *, 623 u32, u8 *, int); 624int qlcnic_83xx_init(struct qlcnic_adapter *, int); 625int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *); 626int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev); 627void qlcnic_83xx_idc_poll_dev_state(struct work_struct *); 628int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *); 629void qlcnic_83xx_idc_exit(struct qlcnic_adapter *); 630void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32); 631int qlcnic_83xx_lock_driver(struct qlcnic_adapter *); 632void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *); 633int qlcnic_83xx_set_default_offload_settings(struct qlcnic_adapter *); 634int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32); 635int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *); 636int qlcnic_83xx_enable_vnic_mode(struct qlcnic_adapter *, int); 637int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *, int); 638int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *); 639int qlcnic_83xx_get_vnic_vport_info(struct qlcnic_adapter *, 640 struct qlcnic_info *, u8); 641int qlcnic_83xx_get_vnic_pf_info(struct qlcnic_adapter *, struct qlcnic_info *); 642int qlcnic_83xx_set_port_eswitch_status(struct qlcnic_adapter *, int, int *); 643 644void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *); 645void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data); 646int qlcnic_83xx_get_settings(struct qlcnic_adapter *, struct ethtool_cmd *); 647int qlcnic_83xx_set_settings(struct qlcnic_adapter *, struct ethtool_cmd *); 648void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *, 649 struct ethtool_pauseparam *); 650int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *, 651 struct ethtool_pauseparam *); 652int qlcnic_83xx_test_link(struct qlcnic_adapter *); 653int qlcnic_83xx_reg_test(struct qlcnic_adapter *); 654int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *); 655int qlcnic_83xx_get_registers(struct qlcnic_adapter *, u32 *); 656int qlcnic_83xx_loopback_test(struct net_device *, u8); 657int qlcnic_83xx_interrupt_test(struct net_device *); 658int qlcnic_83xx_set_led(struct net_device *, enum ethtool_phys_id_state); 659int qlcnic_83xx_flash_test(struct qlcnic_adapter *); 660int qlcnic_83xx_enable_flash_write(struct qlcnic_adapter *); 661int qlcnic_83xx_disable_flash_write(struct qlcnic_adapter *); 662void qlcnic_83xx_enable_mbx_poll(struct qlcnic_adapter *); 663void qlcnic_83xx_disable_mbx_poll(struct qlcnic_adapter *); 664void qlcnic_83xx_set_mac_filter_count(struct qlcnic_adapter *); 665int qlcnic_83xx_shutdown(struct pci_dev *); 666int qlcnic_83xx_resume(struct qlcnic_adapter *); 667int qlcnic_83xx_idc_init(struct qlcnic_adapter *); 668int qlcnic_83xx_idc_reattach_driver(struct qlcnic_adapter *); 669int qlcnic_83xx_set_vnic_opmode(struct qlcnic_adapter *); 670int qlcnic_83xx_check_vnic_state(struct qlcnic_adapter *); 671void qlcnic_83xx_aer_stop_poll_work(struct qlcnic_adapter *); 672int qlcnic_83xx_aer_reset(struct qlcnic_adapter *); 673void qlcnic_83xx_aer_start_poll_work(struct qlcnic_adapter *); 674pci_ers_result_t qlcnic_83xx_io_error_detected(struct pci_dev *, 675 pci_channel_state_t); 676pci_ers_result_t qlcnic_83xx_io_slot_reset(struct pci_dev *); 677void qlcnic_83xx_io_resume(struct pci_dev *); 678void qlcnic_83xx_stop_hw(struct qlcnic_adapter *); 679#endif 680