qlcnic_83xx_hw.h revision a96227e66f0a0361d96885042629bf60eb6a4b39
1/* 2 * QLogic qlcnic NIC Driver 3 * Copyright (c) 2009-2013 QLogic Corporation 4 * 5 * See LICENSE.qlcnic for copyright and licensing details. 6 */ 7 8#ifndef __QLCNIC_83XX_HW_H 9#define __QLCNIC_83XX_HW_H 10 11#include <linux/types.h> 12#include <linux/etherdevice.h> 13#include "qlcnic_hw.h" 14 15/* Directly mapped registers */ 16#define QLC_83XX_CRB_WIN_BASE 0x3800 17#define QLC_83XX_CRB_WIN_FUNC(f) (QLC_83XX_CRB_WIN_BASE+((f)*4)) 18#define QLC_83XX_SEM_LOCK_BASE 0x3840 19#define QLC_83XX_SEM_UNLOCK_BASE 0x3844 20#define QLC_83XX_SEM_LOCK_FUNC(f) (QLC_83XX_SEM_LOCK_BASE+((f)*8)) 21#define QLC_83XX_SEM_UNLOCK_FUNC(f) (QLC_83XX_SEM_UNLOCK_BASE+((f)*8)) 22#define QLC_83XX_LINK_STATE(f) (0x3698+((f) > 7 ? 4 : 0)) 23#define QLC_83XX_LINK_SPEED(f) (0x36E0+(((f) >> 2) * 4)) 24#define QLC_83XX_LINK_SPEED_FACTOR 10 25#define QLC_83xx_FUNC_VAL(v, f) ((v) & (1 << (f * 4))) 26#define QLC_83XX_INTX_PTR 0x38C0 27#define QLC_83XX_INTX_TRGR 0x38C4 28#define QLC_83XX_INTX_MASK 0x38C8 29 30#define QLC_83XX_DRV_LOCK_WAIT_COUNTER 100 31#define QLC_83XX_DRV_LOCK_WAIT_DELAY 20 32#define QLC_83XX_NEED_DRV_LOCK_RECOVERY 1 33#define QLC_83XX_DRV_LOCK_RECOVERY_IN_PROGRESS 2 34#define QLC_83XX_MAX_DRV_LOCK_RECOVERY_ATTEMPT 3 35#define QLC_83XX_DRV_LOCK_RECOVERY_DELAY 200 36#define QLC_83XX_DRV_LOCK_RECOVERY_STATUS_MASK 0x3 37 38#define QLC_83XX_NO_NIC_RESOURCE 0x5 39#define QLC_83XX_MAC_PRESENT 0xC 40#define QLC_83XX_MAC_ABSENT 0xD 41 42 43#define QLC_83XX_FLASH_SECTOR_SIZE (64 * 1024) 44 45/* PEG status definitions */ 46#define QLC_83XX_CMDPEG_COMPLETE 0xff01 47#define QLC_83XX_VALID_INTX_BIT30(val) ((val) & BIT_30) 48#define QLC_83XX_VALID_INTX_BIT31(val) ((val) & BIT_31) 49#define QLC_83XX_INTX_FUNC(val) ((val) & 0xFF) 50#define QLC_83XX_LEGACY_INTX_MAX_RETRY 100 51#define QLC_83XX_LEGACY_INTX_DELAY 4 52#define QLC_83XX_REG_DESC 1 53#define QLC_83XX_LRO_DESC 2 54#define QLC_83XX_CTRL_DESC 3 55#define QLC_83XX_FW_CAPABILITY_TSO BIT_6 56#define QLC_83XX_FW_CAP_LRO_MSS BIT_17 57#define QLC_83XX_HOST_RDS_MODE_UNIQUE 0 58#define QLC_83XX_HOST_SDS_MBX_IDX 8 59 60#define QLCNIC_HOST_RDS_MBX_IDX 88 61#define QLCNIC_MAX_RING_SETS 8 62 63/* Pause control registers */ 64#define QLC_83XX_SRE_SHIM_REG 0x0D200284 65#define QLC_83XX_PORT0_THRESHOLD 0x0B2003A4 66#define QLC_83XX_PORT1_THRESHOLD 0x0B2013A4 67#define QLC_83XX_PORT0_TC_MC_REG 0x0B200388 68#define QLC_83XX_PORT1_TC_MC_REG 0x0B201388 69#define QLC_83XX_PORT0_TC_STATS 0x0B20039C 70#define QLC_83XX_PORT1_TC_STATS 0x0B20139C 71#define QLC_83XX_PORT2_IFB_THRESHOLD 0x0B200704 72#define QLC_83XX_PORT3_IFB_THRESHOLD 0x0B201704 73 74/* Peg PC status registers */ 75#define QLC_83XX_CRB_PEG_NET_0 0x3400003c 76#define QLC_83XX_CRB_PEG_NET_1 0x3410003c 77#define QLC_83XX_CRB_PEG_NET_2 0x3420003c 78#define QLC_83XX_CRB_PEG_NET_3 0x3430003c 79#define QLC_83XX_CRB_PEG_NET_4 0x34b0003c 80 81/* Firmware image definitions */ 82#define QLC_83XX_BOOTLOADER_FLASH_ADDR 0x10000 83#define QLC_83XX_FW_FILE_NAME "83xx_fw.bin" 84#define QLC_83XX_BOOT_FROM_FLASH 0 85#define QLC_83XX_BOOT_FROM_FILE 0x12345678 86 87#define QLC_83XX_MAX_RESET_SEQ_ENTRIES 16 88 89struct qlcnic_intrpt_config { 90 u8 type; 91 u8 enabled; 92 u16 id; 93 u32 src; 94}; 95 96struct qlcnic_macvlan_mbx { 97#if defined(__LITTLE_ENDIAN) 98 u8 mac_addr0; 99 u8 mac_addr1; 100 u8 mac_addr2; 101 u8 mac_addr3; 102 u8 mac_addr4; 103 u8 mac_addr5; 104 u16 vlan; 105#elif defined(__BIG_ENDIAN) 106 u8 mac_addr3; 107 u8 mac_addr2; 108 u8 mac_addr1; 109 u8 mac_addr0; 110 u16 vlan; 111 u8 mac_addr5; 112 u8 mac_addr4; 113#endif 114}; 115 116struct qlc_83xx_fw_info { 117 const struct firmware *fw; 118 u16 major_fw_version; 119 u8 minor_fw_version; 120 u8 sub_fw_version; 121 u8 fw_build_num; 122 u8 load_from_file; 123}; 124 125struct qlc_83xx_reset { 126 struct qlc_83xx_reset_hdr *hdr; 127 int seq_index; 128 int seq_error; 129 int array_index; 130 u32 array[QLC_83XX_MAX_RESET_SEQ_ENTRIES]; 131 u8 *buff; 132 u8 *stop_offset; 133 u8 *start_offset; 134 u8 *init_offset; 135 u8 seq_end; 136 u8 template_end; 137}; 138 139#define QLC_83XX_IDC_DISABLE_FW_RESET_RECOVERY 0x1 140#define QLC_83XX_IDC_GRACEFULL_RESET 0x2 141#define QLC_83XX_IDC_TIMESTAMP 0 142#define QLC_83XX_IDC_DURATION 1 143#define QLC_83XX_IDC_INIT_TIMEOUT_SECS 30 144#define QLC_83XX_IDC_RESET_ACK_TIMEOUT_SECS 10 145#define QLC_83XX_IDC_RESET_TIMEOUT_SECS 10 146#define QLC_83XX_IDC_QUIESCE_ACK_TIMEOUT_SECS 20 147#define QLC_83XX_IDC_FW_POLL_DELAY (1 * HZ) 148#define QLC_83XX_IDC_FW_FAIL_THRESH 2 149#define QLC_83XX_IDC_MAX_FUNC_PER_PARTITION_INFO 8 150#define QLC_83XX_IDC_MAX_CNA_FUNCTIONS 16 151#define QLC_83XX_IDC_MAJOR_VERSION 1 152#define QLC_83XX_IDC_MINOR_VERSION 0 153#define QLC_83XX_IDC_FLASH_PARAM_ADDR 0x3e8020 154 155struct qlcnic_adapter; 156struct qlc_83xx_idc { 157 int (*state_entry) (struct qlcnic_adapter *); 158 u64 sec_counter; 159 u64 delay; 160 unsigned long status; 161 int err_code; 162 int collect_dump; 163 u8 curr_state; 164 u8 prev_state; 165 u8 vnic_state; 166 u8 vnic_wait_limit; 167 u8 quiesce_req; 168 char **name; 169}; 170 171#define QLCNIC_MBX_RSP(reg) LSW(reg) 172#define QLCNIC_MBX_NUM_REGS(reg) (MSW(reg) & 0x1FF) 173#define QLCNIC_MBX_STATUS(reg) (((reg) >> 25) & 0x7F) 174#define QLCNIC_MBX_HOST(ahw, i) ((ahw)->pci_base0 + ((i) * 4)) 175#define QLCNIC_MBX_FW(ahw, i) ((ahw)->pci_base0 + 0x800 + ((i) * 4)) 176 177/* Mailbox process AEN count */ 178#define QLC_83XX_IDC_COMP_AEN 3 179#define QLC_83XX_MBX_AEN_CNT 5 180#define QLC_83XX_MODULE_LOADED 1 181#define QLC_83XX_MBX_READY 2 182#define QLC_83XX_MBX_AEN_ACK 3 183#define QLC_83XX_SFP_PRESENT(data) ((data) & 3) 184#define QLC_83XX_SFP_ERR(data) (((data) >> 2) & 3) 185#define QLC_83XX_SFP_MODULE_TYPE(data) (((data) >> 4) & 0x1F) 186#define QLC_83XX_SFP_CU_LENGTH(data) (LSB((data) >> 16)) 187#define QLC_83XX_SFP_TX_FAULT(data) ((data) & BIT_10) 188#define QLC_83XX_SFP_10G_CAPABLE(data) ((data) & BIT_11) 189#define QLC_83XX_LINK_STATS(data) ((data) & BIT_0) 190#define QLC_83XX_CURRENT_LINK_SPEED(data) (((data) >> 3) & 7) 191#define QLC_83XX_LINK_PAUSE(data) (((data) >> 6) & 3) 192#define QLC_83XX_LINK_LB(data) (((data) >> 8) & 7) 193#define QLC_83XX_LINK_FEC(data) ((data) & BIT_12) 194#define QLC_83XX_LINK_EEE(data) ((data) & BIT_13) 195#define QLC_83XX_DCBX(data) (((data) >> 28) & 7) 196#define QLC_83XX_AUTONEG(data) ((data) & BIT_15) 197#define QLC_83XX_CFG_STD_PAUSE (1 << 5) 198#define QLC_83XX_CFG_STD_TX_PAUSE (1 << 20) 199#define QLC_83XX_CFG_STD_RX_PAUSE (2 << 20) 200#define QLC_83XX_CFG_STD_TX_RX_PAUSE (3 << 20) 201#define QLC_83XX_ENABLE_AUTONEG (1 << 15) 202#define QLC_83XX_CFG_LOOPBACK_HSS (2 << 1) 203#define QLC_83XX_CFG_LOOPBACK_PHY (3 << 1) 204#define QLC_83XX_CFG_LOOPBACK_EXT (4 << 1) 205 206/* LED configuration settings */ 207#define QLC_83XX_ENABLE_BEACON 0xe 208#define QLC_83XX_LED_RATE 0xff 209#define QLC_83XX_LED_ACT (1 << 10) 210#define QLC_83XX_LED_MOD (0 << 13) 211#define QLC_83XX_LED_CONFIG (QLC_83XX_LED_RATE | QLC_83XX_LED_ACT | \ 212 QLC_83XX_LED_MOD) 213 214#define QLC_83XX_10M_LINK 1 215#define QLC_83XX_100M_LINK 2 216#define QLC_83XX_1G_LINK 3 217#define QLC_83XX_10G_LINK 4 218#define QLC_83XX_STAT_TX 3 219#define QLC_83XX_STAT_RX 2 220#define QLC_83XX_STAT_MAC 1 221#define QLC_83XX_TX_STAT_REGS 14 222#define QLC_83XX_RX_STAT_REGS 40 223#define QLC_83XX_MAC_STAT_REGS 80 224 225#define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2))) 226#define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2)) 227#define QLC_83XX_DEFAULT_OPMODE 0x55555555 228#define QLC_83XX_PRIVLEGED_FUNC 0x1 229#define QLC_83XX_VIRTUAL_FUNC 0x2 230 231#define QLC_83XX_LB_MAX_FILTERS 2048 232#define QLC_83XX_LB_BUCKET_SIZE 256 233#define QLC_83XX_MINIMUM_VECTOR 3 234 235#define QLC_83XX_GET_FUNC_MODE_FROM_NPAR_INFO(val) (val & 0x80000000) 236#define QLC_83XX_GET_LRO_CAPABILITY(val) (val & 0x20) 237#define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40) 238#define QLC_83XX_GET_LSO_CAPABILITY(val) (val & 0x40) 239#define QLC_83XX_GET_HW_LRO_CAPABILITY(val) (val & 0x400) 240#define QLC_83XX_GET_VLAN_ALIGN_CAPABILITY(val) (val & 0x4000) 241#define QLC_83XX_GET_FW_LRO_MSS_CAPABILITY(val) (val & 0x20000) 242#define QLC_83XX_VIRTUAL_NIC_MODE 0xFF 243#define QLC_83XX_DEFAULT_MODE 0x0 244#define QLCNIC_BRDTYPE_83XX_10G 0x0083 245 246#define QLC_83XX_FLASH_SPI_STATUS 0x2808E010 247#define QLC_83XX_FLASH_SPI_CONTROL 0x2808E014 248#define QLC_83XX_FLASH_STATUS 0x42100004 249#define QLC_83XX_FLASH_CONTROL 0x42110004 250#define QLC_83XX_FLASH_ADDR 0x42110008 251#define QLC_83XX_FLASH_WRDATA 0x4211000C 252#define QLC_83XX_FLASH_RDDATA 0x42110018 253#define QLC_83XX_FLASH_DIRECT_WINDOW 0x42110030 254#define QLC_83XX_FLASH_DIRECT_DATA(DATA) (0x42150000 | (0x0000FFFF&DATA)) 255#define QLC_83XX_FLASH_SECTOR_ERASE_CMD 0xdeadbeef 256#define QLC_83XX_FLASH_WRITE_CMD 0xdacdacda 257#define QLC_83XX_FLASH_BULK_WRITE_CMD 0xcadcadca 258#define QLC_83XX_FLASH_READ_RETRY_COUNT 5000 259#define QLC_83XX_FLASH_STATUS_READY 0x6 260#define QLC_83XX_FLASH_BULK_WRITE_MIN 2 261#define QLC_83XX_FLASH_BULK_WRITE_MAX 64 262#define QLC_83XX_FLASH_STATUS_REG_POLL_DELAY 1 263#define QLC_83XX_ERASE_MODE 1 264#define QLC_83XX_WRITE_MODE 2 265#define QLC_83XX_BULK_WRITE_MODE 3 266#define QLC_83XX_FLASH_FDT_WRITE_DEF_SIG 0xFD0100 267#define QLC_83XX_FLASH_FDT_ERASE_DEF_SIG 0xFD0300 268#define QLC_83XX_FLASH_FDT_READ_MFG_ID_VAL 0xFD009F 269#define QLC_83XX_FLASH_OEM_ERASE_SIG 0xFD03D8 270#define QLC_83XX_FLASH_OEM_WRITE_SIG 0xFD0101 271#define QLC_83XX_FLASH_OEM_READ_SIG 0xFD0005 272#define QLC_83XX_FLASH_ADDR_TEMP_VAL 0x00800000 273#define QLC_83XX_FLASH_ADDR_SECOND_TEMP_VAL 0x00800001 274#define QLC_83XX_FLASH_WRDATA_DEF 0x0 275#define QLC_83XX_FLASH_READ_CTRL 0x3F 276#define QLC_83XX_FLASH_SPI_CTRL 0x4 277#define QLC_83XX_FLASH_FIRST_ERASE_MS_VAL 0x2 278#define QLC_83XX_FLASH_SECOND_ERASE_MS_VAL 0x5 279#define QLC_83XX_FLASH_LAST_ERASE_MS_VAL 0x3D 280#define QLC_83XX_FLASH_FIRST_MS_PATTERN 0x43 281#define QLC_83XX_FLASH_SECOND_MS_PATTERN 0x7F 282#define QLC_83XX_FLASH_LAST_MS_PATTERN 0x7D 283#define QLC_83xx_FLASH_MAX_WAIT_USEC 100 284#define QLC_83XX_FLASH_LOCK_TIMEOUT 10000 285 286/* Additional registers in 83xx */ 287enum qlc_83xx_ext_regs { 288 QLCNIC_GLOBAL_RESET = 0, 289 QLCNIC_WILDCARD, 290 QLCNIC_INFORMANT, 291 QLCNIC_HOST_MBX_CTRL, 292 QLCNIC_FW_MBX_CTRL, 293 QLCNIC_BOOTLOADER_ADDR, 294 QLCNIC_BOOTLOADER_SIZE, 295 QLCNIC_FW_IMAGE_ADDR, 296 QLCNIC_MBX_INTR_ENBL, 297 QLCNIC_DEF_INT_MASK, 298 QLCNIC_DEF_INT_ID, 299 QLC_83XX_IDC_MAJ_VERSION, 300 QLC_83XX_IDC_DEV_STATE, 301 QLC_83XX_IDC_DRV_PRESENCE, 302 QLC_83XX_IDC_DRV_ACK, 303 QLC_83XX_IDC_CTRL, 304 QLC_83XX_IDC_DRV_AUDIT, 305 QLC_83XX_IDC_MIN_VERSION, 306 QLC_83XX_RECOVER_DRV_LOCK, 307 QLC_83XX_IDC_PF_0, 308 QLC_83XX_IDC_PF_1, 309 QLC_83XX_IDC_PF_2, 310 QLC_83XX_IDC_PF_3, 311 QLC_83XX_IDC_PF_4, 312 QLC_83XX_IDC_PF_5, 313 QLC_83XX_IDC_PF_6, 314 QLC_83XX_IDC_PF_7, 315 QLC_83XX_IDC_PF_8, 316 QLC_83XX_IDC_PF_9, 317 QLC_83XX_IDC_PF_10, 318 QLC_83XX_IDC_PF_11, 319 QLC_83XX_IDC_PF_12, 320 QLC_83XX_IDC_PF_13, 321 QLC_83XX_IDC_PF_14, 322 QLC_83XX_IDC_PF_15, 323 QLC_83XX_IDC_DEV_PARTITION_INFO_1, 324 QLC_83XX_IDC_DEV_PARTITION_INFO_2, 325 QLC_83XX_DRV_OP_MODE, 326 QLC_83XX_VNIC_STATE, 327 QLC_83XX_DRV_LOCK, 328 QLC_83XX_DRV_UNLOCK, 329 QLC_83XX_DRV_LOCK_ID, 330 QLC_83XX_ASIC_TEMP, 331}; 332 333/* 83xx funcitons */ 334int qlcnic_83xx_get_fw_version(struct qlcnic_adapter *); 335int qlcnic_83xx_mbx_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *); 336int qlcnic_83xx_setup_intr(struct qlcnic_adapter *, u8); 337void qlcnic_83xx_get_func_no(struct qlcnic_adapter *); 338int qlcnic_83xx_cam_lock(struct qlcnic_adapter *); 339void qlcnic_83xx_cam_unlock(struct qlcnic_adapter *); 340int qlcnic_send_ctrl_op(struct qlcnic_adapter *, struct qlcnic_cmd_args *, u32); 341void qlcnic_83xx_add_sysfs(struct qlcnic_adapter *); 342void qlcnic_83xx_remove_sysfs(struct qlcnic_adapter *); 343void qlcnic_83xx_write_crb(struct qlcnic_adapter *, char *, loff_t, size_t); 344void qlcnic_83xx_read_crb(struct qlcnic_adapter *, char *, loff_t, size_t); 345int qlcnic_83xx_rd_reg_indirect(struct qlcnic_adapter *, ulong); 346int qlcnic_83xx_wrt_reg_indirect(struct qlcnic_adapter *, ulong, u32); 347void qlcnic_83xx_process_rcv_diag(struct qlcnic_adapter *, int, u64 []); 348int qlcnic_83xx_nic_set_promisc(struct qlcnic_adapter *, u32); 349int qlcnic_83xx_set_lb_mode(struct qlcnic_adapter *, u8); 350int qlcnic_83xx_clear_lb_mode(struct qlcnic_adapter *, u8); 351int qlcnic_83xx_config_hw_lro(struct qlcnic_adapter *, int); 352int qlcnic_83xx_config_rss(struct qlcnic_adapter *, int); 353int qlcnic_83xx_config_intr_coalesce(struct qlcnic_adapter *); 354void qlcnic_83xx_change_l2_filter(struct qlcnic_adapter *, u64 *, __le16); 355int qlcnic_83xx_get_pci_info(struct qlcnic_adapter *, struct qlcnic_pci_info *); 356int qlcnic_83xx_set_nic_info(struct qlcnic_adapter *, struct qlcnic_info *); 357void qlcnic_83xx_register_nic_idc_func(struct qlcnic_adapter *, int); 358 359int qlcnic_83xx_napi_add(struct qlcnic_adapter *, struct net_device *); 360void qlcnic_83xx_napi_del(struct qlcnic_adapter *); 361void qlcnic_83xx_napi_enable(struct qlcnic_adapter *); 362void qlcnic_83xx_napi_disable(struct qlcnic_adapter *); 363int qlcnic_83xx_config_led(struct qlcnic_adapter *, u32, u32); 364void qlcnic_ind_wr(struct qlcnic_adapter *, u32, u32); 365int qlcnic_ind_rd(struct qlcnic_adapter *, u32); 366int qlcnic_83xx_create_rx_ctx(struct qlcnic_adapter *); 367int qlcnic_83xx_create_tx_ctx(struct qlcnic_adapter *, 368 struct qlcnic_host_tx_ring *, int); 369int qlcnic_83xx_get_nic_info(struct qlcnic_adapter *, struct qlcnic_info *, u8); 370int qlcnic_83xx_setup_link_event(struct qlcnic_adapter *, int); 371void qlcnic_83xx_process_rcv_ring_diag(struct qlcnic_host_sds_ring *); 372int qlcnic_83xx_config_intrpt(struct qlcnic_adapter *, bool); 373int qlcnic_83xx_sre_macaddr_change(struct qlcnic_adapter *, u8 *, __le16, u8); 374int qlcnic_83xx_get_mac_address(struct qlcnic_adapter *, u8 *); 375void qlcnic_83xx_configure_mac(struct qlcnic_adapter *, u8 *, u8, 376 struct qlcnic_cmd_args *); 377int qlcnic_83xx_alloc_mbx_args(struct qlcnic_cmd_args *, 378 struct qlcnic_adapter *, u32); 379void qlcnic_free_mbx_args(struct qlcnic_cmd_args *); 380void qlcnic_set_npar_data(struct qlcnic_adapter *, const struct qlcnic_info *, 381 struct qlcnic_info *); 382void qlcnic_83xx_config_intr_coal(struct qlcnic_adapter *); 383irqreturn_t qlcnic_83xx_handle_aen(int, void *); 384int qlcnic_83xx_get_port_info(struct qlcnic_adapter *); 385void qlcnic_83xx_enable_mbx_intrpt(struct qlcnic_adapter *); 386irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *); 387irqreturn_t qlcnic_83xx_intr(int, void *); 388irqreturn_t qlcnic_83xx_tmp_intr(int, void *); 389void qlcnic_83xx_enable_intr(struct qlcnic_adapter *, 390 struct qlcnic_host_sds_ring *); 391void qlcnic_83xx_disable_intr(struct qlcnic_adapter *, 392 struct qlcnic_host_sds_ring *); 393void qlcnic_83xx_check_vf(struct qlcnic_adapter *, 394 const struct pci_device_id *); 395void qlcnic_83xx_process_aen(struct qlcnic_adapter *); 396int qlcnic_83xx_get_port_config(struct qlcnic_adapter *); 397int qlcnic_83xx_set_port_config(struct qlcnic_adapter *); 398int qlcnic_enable_eswitch(struct qlcnic_adapter *, u8, u8); 399int qlcnic_83xx_get_nic_configuration(struct qlcnic_adapter *); 400int qlcnic_83xx_config_default_opmode(struct qlcnic_adapter *); 401int qlcnic_83xx_setup_mbx_intr(struct qlcnic_adapter *); 402void qlcnic_83xx_free_mbx_intr(struct qlcnic_adapter *); 403void qlcnic_83xx_register_map(struct qlcnic_hardware_context *); 404void qlcnic_83xx_idc_aen_work(struct work_struct *); 405void qlcnic_83xx_config_ipaddr(struct qlcnic_adapter *, __be32, int); 406 407int qlcnic_83xx_erase_flash_sector(struct qlcnic_adapter *, u32); 408int qlcnic_83xx_flash_bulk_write(struct qlcnic_adapter *, u32, u32 *, int); 409int qlcnic_83xx_flash_write32(struct qlcnic_adapter *, u32, u32 *); 410int qlcnic_83xx_lock_flash(struct qlcnic_adapter *); 411void qlcnic_83xx_unlock_flash(struct qlcnic_adapter *); 412int qlcnic_83xx_save_flash_status(struct qlcnic_adapter *); 413int qlcnic_83xx_restore_flash_status(struct qlcnic_adapter *, int); 414int qlcnic_83xx_read_flash_mfg_id(struct qlcnic_adapter *); 415int qlcnic_83xx_read_flash_descriptor_table(struct qlcnic_adapter *); 416int qlcnic_83xx_flash_read32(struct qlcnic_adapter *, u32, u8 *, int); 417int qlcnic_83xx_lockless_flash_read32(struct qlcnic_adapter *, 418 u32, u8 *, int); 419int qlcnic_83xx_init(struct qlcnic_adapter *); 420int qlcnic_83xx_idc_ready_state_entry(struct qlcnic_adapter *); 421int qlcnic_83xx_check_hw_status(struct qlcnic_adapter *p_dev); 422void qlcnic_83xx_idc_poll_dev_state(struct work_struct *); 423int qlcnic_83xx_get_reset_instruction_template(struct qlcnic_adapter *); 424void qlcnic_83xx_idc_exit(struct qlcnic_adapter *); 425void qlcnic_83xx_idc_request_reset(struct qlcnic_adapter *, u32); 426int qlcnic_83xx_lock_driver(struct qlcnic_adapter *); 427void qlcnic_83xx_unlock_driver(struct qlcnic_adapter *); 428int qlcnic_83xx_set_default_offload_settings(struct qlcnic_adapter *); 429int qlcnic_83xx_ms_mem_write128(struct qlcnic_adapter *, u64, u32 *, u32); 430int qlcnic_83xx_idc_vnic_pf_entry(struct qlcnic_adapter *); 431int qlcnic_83xx_enable_vnic_mode(struct qlcnic_adapter *, int); 432int qlcnic_83xx_disable_vnic_mode(struct qlcnic_adapter *, int); 433int qlcnic_83xx_config_vnic_opmode(struct qlcnic_adapter *); 434int qlcnic_83xx_get_vnic_vport_info(struct qlcnic_adapter *, 435 struct qlcnic_info *, u8); 436int qlcnic_83xx_get_vnic_pf_info(struct qlcnic_adapter *, struct qlcnic_info *); 437 438void qlcnic_83xx_get_minidump_template(struct qlcnic_adapter *); 439void qlcnic_83xx_get_stats(struct qlcnic_adapter *adapter, u64 *data); 440int qlcnic_83xx_get_settings(struct qlcnic_adapter *); 441int qlcnic_83xx_set_settings(struct qlcnic_adapter *, struct ethtool_cmd *); 442void qlcnic_83xx_get_pauseparam(struct qlcnic_adapter *, 443 struct ethtool_pauseparam *); 444int qlcnic_83xx_set_pauseparam(struct qlcnic_adapter *, 445 struct ethtool_pauseparam *); 446int qlcnic_83xx_test_link(struct qlcnic_adapter *); 447int qlcnic_83xx_reg_test(struct qlcnic_adapter *); 448int qlcnic_83xx_get_regs_len(struct qlcnic_adapter *); 449int qlcnic_83xx_get_registers(struct qlcnic_adapter *, u32 *); 450int qlcnic_83xx_loopback_test(struct net_device *, u8); 451int qlcnic_83xx_interrupt_test(struct net_device *); 452int qlcnic_83xx_flash_test(struct qlcnic_adapter *); 453#endif 454