sh_eth.c revision 0c9eb5b931c3da3a79faa889b903dc7bd318203c
1/* 2 * SuperH Ethernet device driver 3 * 4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu 5 * Copyright (C) 2008-2013 Renesas Solutions Corp. 6 * Copyright (C) 2013 Cogent Embedded, Inc. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * You should have received a copy of the GNU General Public License along with 17 * this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * The full GNU General Public License is included in this distribution in 21 * the file called "COPYING". 22 */ 23 24#include <linux/init.h> 25#include <linux/module.h> 26#include <linux/kernel.h> 27#include <linux/spinlock.h> 28#include <linux/interrupt.h> 29#include <linux/dma-mapping.h> 30#include <linux/etherdevice.h> 31#include <linux/delay.h> 32#include <linux/platform_device.h> 33#include <linux/mdio-bitbang.h> 34#include <linux/netdevice.h> 35#include <linux/phy.h> 36#include <linux/cache.h> 37#include <linux/io.h> 38#include <linux/pm_runtime.h> 39#include <linux/slab.h> 40#include <linux/ethtool.h> 41#include <linux/if_vlan.h> 42#include <linux/clk.h> 43#include <linux/sh_eth.h> 44 45#include "sh_eth.h" 46 47#define SH_ETH_DEF_MSG_ENABLE \ 48 (NETIF_MSG_LINK | \ 49 NETIF_MSG_TIMER | \ 50 NETIF_MSG_RX_ERR| \ 51 NETIF_MSG_TX_ERR) 52 53static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { 54 [EDSR] = 0x0000, 55 [EDMR] = 0x0400, 56 [EDTRR] = 0x0408, 57 [EDRRR] = 0x0410, 58 [EESR] = 0x0428, 59 [EESIPR] = 0x0430, 60 [TDLAR] = 0x0010, 61 [TDFAR] = 0x0014, 62 [TDFXR] = 0x0018, 63 [TDFFR] = 0x001c, 64 [RDLAR] = 0x0030, 65 [RDFAR] = 0x0034, 66 [RDFXR] = 0x0038, 67 [RDFFR] = 0x003c, 68 [TRSCER] = 0x0438, 69 [RMFCR] = 0x0440, 70 [TFTR] = 0x0448, 71 [FDR] = 0x0450, 72 [RMCR] = 0x0458, 73 [RPADIR] = 0x0460, 74 [FCFTR] = 0x0468, 75 [CSMR] = 0x04E4, 76 77 [ECMR] = 0x0500, 78 [ECSR] = 0x0510, 79 [ECSIPR] = 0x0518, 80 [PIR] = 0x0520, 81 [PSR] = 0x0528, 82 [PIPR] = 0x052c, 83 [RFLR] = 0x0508, 84 [APR] = 0x0554, 85 [MPR] = 0x0558, 86 [PFTCR] = 0x055c, 87 [PFRCR] = 0x0560, 88 [TPAUSER] = 0x0564, 89 [GECMR] = 0x05b0, 90 [BCULR] = 0x05b4, 91 [MAHR] = 0x05c0, 92 [MALR] = 0x05c8, 93 [TROCR] = 0x0700, 94 [CDCR] = 0x0708, 95 [LCCR] = 0x0710, 96 [CEFCR] = 0x0740, 97 [FRECR] = 0x0748, 98 [TSFRCR] = 0x0750, 99 [TLFRCR] = 0x0758, 100 [RFCR] = 0x0760, 101 [CERCR] = 0x0768, 102 [CEECR] = 0x0770, 103 [MAFCR] = 0x0778, 104 [RMII_MII] = 0x0790, 105 106 [ARSTR] = 0x0000, 107 [TSU_CTRST] = 0x0004, 108 [TSU_FWEN0] = 0x0010, 109 [TSU_FWEN1] = 0x0014, 110 [TSU_FCM] = 0x0018, 111 [TSU_BSYSL0] = 0x0020, 112 [TSU_BSYSL1] = 0x0024, 113 [TSU_PRISL0] = 0x0028, 114 [TSU_PRISL1] = 0x002c, 115 [TSU_FWSL0] = 0x0030, 116 [TSU_FWSL1] = 0x0034, 117 [TSU_FWSLC] = 0x0038, 118 [TSU_QTAG0] = 0x0040, 119 [TSU_QTAG1] = 0x0044, 120 [TSU_FWSR] = 0x0050, 121 [TSU_FWINMK] = 0x0054, 122 [TSU_ADQT0] = 0x0048, 123 [TSU_ADQT1] = 0x004c, 124 [TSU_VTAG0] = 0x0058, 125 [TSU_VTAG1] = 0x005c, 126 [TSU_ADSBSY] = 0x0060, 127 [TSU_TEN] = 0x0064, 128 [TSU_POST1] = 0x0070, 129 [TSU_POST2] = 0x0074, 130 [TSU_POST3] = 0x0078, 131 [TSU_POST4] = 0x007c, 132 [TSU_ADRH0] = 0x0100, 133 [TSU_ADRL0] = 0x0104, 134 [TSU_ADRH31] = 0x01f8, 135 [TSU_ADRL31] = 0x01fc, 136 137 [TXNLCR0] = 0x0080, 138 [TXALCR0] = 0x0084, 139 [RXNLCR0] = 0x0088, 140 [RXALCR0] = 0x008c, 141 [FWNLCR0] = 0x0090, 142 [FWALCR0] = 0x0094, 143 [TXNLCR1] = 0x00a0, 144 [TXALCR1] = 0x00a0, 145 [RXNLCR1] = 0x00a8, 146 [RXALCR1] = 0x00ac, 147 [FWNLCR1] = 0x00b0, 148 [FWALCR1] = 0x00b4, 149}; 150 151static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = { 152 [ECMR] = 0x0300, 153 [RFLR] = 0x0308, 154 [ECSR] = 0x0310, 155 [ECSIPR] = 0x0318, 156 [PIR] = 0x0320, 157 [PSR] = 0x0328, 158 [RDMLR] = 0x0340, 159 [IPGR] = 0x0350, 160 [APR] = 0x0354, 161 [MPR] = 0x0358, 162 [RFCF] = 0x0360, 163 [TPAUSER] = 0x0364, 164 [TPAUSECR] = 0x0368, 165 [MAHR] = 0x03c0, 166 [MALR] = 0x03c8, 167 [TROCR] = 0x03d0, 168 [CDCR] = 0x03d4, 169 [LCCR] = 0x03d8, 170 [CNDCR] = 0x03dc, 171 [CEFCR] = 0x03e4, 172 [FRECR] = 0x03e8, 173 [TSFRCR] = 0x03ec, 174 [TLFRCR] = 0x03f0, 175 [RFCR] = 0x03f4, 176 [MAFCR] = 0x03f8, 177 178 [EDMR] = 0x0200, 179 [EDTRR] = 0x0208, 180 [EDRRR] = 0x0210, 181 [TDLAR] = 0x0218, 182 [RDLAR] = 0x0220, 183 [EESR] = 0x0228, 184 [EESIPR] = 0x0230, 185 [TRSCER] = 0x0238, 186 [RMFCR] = 0x0240, 187 [TFTR] = 0x0248, 188 [FDR] = 0x0250, 189 [RMCR] = 0x0258, 190 [TFUCR] = 0x0264, 191 [RFOCR] = 0x0268, 192 [RMIIMODE] = 0x026c, 193 [FCFTR] = 0x0270, 194 [TRIMD] = 0x027c, 195}; 196 197static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { 198 [ECMR] = 0x0100, 199 [RFLR] = 0x0108, 200 [ECSR] = 0x0110, 201 [ECSIPR] = 0x0118, 202 [PIR] = 0x0120, 203 [PSR] = 0x0128, 204 [RDMLR] = 0x0140, 205 [IPGR] = 0x0150, 206 [APR] = 0x0154, 207 [MPR] = 0x0158, 208 [TPAUSER] = 0x0164, 209 [RFCF] = 0x0160, 210 [TPAUSECR] = 0x0168, 211 [BCFRR] = 0x016c, 212 [MAHR] = 0x01c0, 213 [MALR] = 0x01c8, 214 [TROCR] = 0x01d0, 215 [CDCR] = 0x01d4, 216 [LCCR] = 0x01d8, 217 [CNDCR] = 0x01dc, 218 [CEFCR] = 0x01e4, 219 [FRECR] = 0x01e8, 220 [TSFRCR] = 0x01ec, 221 [TLFRCR] = 0x01f0, 222 [RFCR] = 0x01f4, 223 [MAFCR] = 0x01f8, 224 [RTRATE] = 0x01fc, 225 226 [EDMR] = 0x0000, 227 [EDTRR] = 0x0008, 228 [EDRRR] = 0x0010, 229 [TDLAR] = 0x0018, 230 [RDLAR] = 0x0020, 231 [EESR] = 0x0028, 232 [EESIPR] = 0x0030, 233 [TRSCER] = 0x0038, 234 [RMFCR] = 0x0040, 235 [TFTR] = 0x0048, 236 [FDR] = 0x0050, 237 [RMCR] = 0x0058, 238 [TFUCR] = 0x0064, 239 [RFOCR] = 0x0068, 240 [FCFTR] = 0x0070, 241 [RPADIR] = 0x0078, 242 [TRIMD] = 0x007c, 243 [RBWAR] = 0x00c8, 244 [RDFAR] = 0x00cc, 245 [TBRAR] = 0x00d4, 246 [TDFAR] = 0x00d8, 247}; 248 249static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = { 250 [ECMR] = 0x0160, 251 [ECSR] = 0x0164, 252 [ECSIPR] = 0x0168, 253 [PIR] = 0x016c, 254 [MAHR] = 0x0170, 255 [MALR] = 0x0174, 256 [RFLR] = 0x0178, 257 [PSR] = 0x017c, 258 [TROCR] = 0x0180, 259 [CDCR] = 0x0184, 260 [LCCR] = 0x0188, 261 [CNDCR] = 0x018c, 262 [CEFCR] = 0x0194, 263 [FRECR] = 0x0198, 264 [TSFRCR] = 0x019c, 265 [TLFRCR] = 0x01a0, 266 [RFCR] = 0x01a4, 267 [MAFCR] = 0x01a8, 268 [IPGR] = 0x01b4, 269 [APR] = 0x01b8, 270 [MPR] = 0x01bc, 271 [TPAUSER] = 0x01c4, 272 [BCFR] = 0x01cc, 273 274 [ARSTR] = 0x0000, 275 [TSU_CTRST] = 0x0004, 276 [TSU_FWEN0] = 0x0010, 277 [TSU_FWEN1] = 0x0014, 278 [TSU_FCM] = 0x0018, 279 [TSU_BSYSL0] = 0x0020, 280 [TSU_BSYSL1] = 0x0024, 281 [TSU_PRISL0] = 0x0028, 282 [TSU_PRISL1] = 0x002c, 283 [TSU_FWSL0] = 0x0030, 284 [TSU_FWSL1] = 0x0034, 285 [TSU_FWSLC] = 0x0038, 286 [TSU_QTAGM0] = 0x0040, 287 [TSU_QTAGM1] = 0x0044, 288 [TSU_ADQT0] = 0x0048, 289 [TSU_ADQT1] = 0x004c, 290 [TSU_FWSR] = 0x0050, 291 [TSU_FWINMK] = 0x0054, 292 [TSU_ADSBSY] = 0x0060, 293 [TSU_TEN] = 0x0064, 294 [TSU_POST1] = 0x0070, 295 [TSU_POST2] = 0x0074, 296 [TSU_POST3] = 0x0078, 297 [TSU_POST4] = 0x007c, 298 299 [TXNLCR0] = 0x0080, 300 [TXALCR0] = 0x0084, 301 [RXNLCR0] = 0x0088, 302 [RXALCR0] = 0x008c, 303 [FWNLCR0] = 0x0090, 304 [FWALCR0] = 0x0094, 305 [TXNLCR1] = 0x00a0, 306 [TXALCR1] = 0x00a0, 307 [RXNLCR1] = 0x00a8, 308 [RXALCR1] = 0x00ac, 309 [FWNLCR1] = 0x00b0, 310 [FWALCR1] = 0x00b4, 311 312 [TSU_ADRH0] = 0x0100, 313 [TSU_ADRL0] = 0x0104, 314 [TSU_ADRL31] = 0x01fc, 315}; 316 317static int sh_eth_is_gether(struct sh_eth_private *mdp) 318{ 319 if (mdp->reg_offset == sh_eth_offset_gigabit) 320 return 1; 321 else 322 return 0; 323} 324 325static void sh_eth_select_mii(struct net_device *ndev) 326{ 327 u32 value = 0x0; 328 struct sh_eth_private *mdp = netdev_priv(ndev); 329 330 switch (mdp->phy_interface) { 331 case PHY_INTERFACE_MODE_GMII: 332 value = 0x2; 333 break; 334 case PHY_INTERFACE_MODE_MII: 335 value = 0x1; 336 break; 337 case PHY_INTERFACE_MODE_RMII: 338 value = 0x0; 339 break; 340 default: 341 pr_warn("PHY interface mode was not setup. Set to MII.\n"); 342 value = 0x1; 343 break; 344 } 345 346 sh_eth_write(ndev, value, RMII_MII); 347} 348 349static void sh_eth_set_duplex(struct net_device *ndev) 350{ 351 struct sh_eth_private *mdp = netdev_priv(ndev); 352 353 if (mdp->duplex) /* Full */ 354 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR); 355 else /* Half */ 356 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR); 357} 358 359/* There is CPU dependent code */ 360static void sh_eth_set_rate_r8a777x(struct net_device *ndev) 361{ 362 struct sh_eth_private *mdp = netdev_priv(ndev); 363 364 switch (mdp->speed) { 365 case 10: /* 10BASE */ 366 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_ELB, ECMR); 367 break; 368 case 100:/* 100BASE */ 369 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_ELB, ECMR); 370 break; 371 default: 372 break; 373 } 374} 375 376/* R8A7778/9 */ 377static struct sh_eth_cpu_data r8a777x_data = { 378 .set_duplex = sh_eth_set_duplex, 379 .set_rate = sh_eth_set_rate_r8a777x, 380 381 .register_type = SH_ETH_REG_FAST_RCAR, 382 383 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 384 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 385 .eesipr_value = 0x01ff009f, 386 387 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 388 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 389 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 390 EESR_ECI, 391 392 .apr = 1, 393 .mpr = 1, 394 .tpauser = 1, 395 .hw_swap = 1, 396}; 397 398/* R8A7790 */ 399static struct sh_eth_cpu_data r8a7790_data = { 400 .set_duplex = sh_eth_set_duplex, 401 .set_rate = sh_eth_set_rate_r8a777x, 402 403 .register_type = SH_ETH_REG_FAST_RCAR, 404 405 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 406 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 407 .eesipr_value = 0x01ff009f, 408 409 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 410 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 411 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 412 EESR_ECI, 413 414 .apr = 1, 415 .mpr = 1, 416 .tpauser = 1, 417 .hw_swap = 1, 418 .rmiimode = 1, 419 .shift_rd0 = 1, 420}; 421 422static void sh_eth_set_rate_sh7724(struct net_device *ndev) 423{ 424 struct sh_eth_private *mdp = netdev_priv(ndev); 425 426 switch (mdp->speed) { 427 case 10: /* 10BASE */ 428 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR); 429 break; 430 case 100:/* 100BASE */ 431 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR); 432 break; 433 default: 434 break; 435 } 436} 437 438/* SH7724 */ 439static struct sh_eth_cpu_data sh7724_data = { 440 .set_duplex = sh_eth_set_duplex, 441 .set_rate = sh_eth_set_rate_sh7724, 442 443 .register_type = SH_ETH_REG_FAST_SH4, 444 445 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD, 446 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP, 447 .eesipr_value = 0x01ff009f, 448 449 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 450 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 451 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 452 EESR_ECI, 453 454 .apr = 1, 455 .mpr = 1, 456 .tpauser = 1, 457 .hw_swap = 1, 458 .rpadir = 1, 459 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */ 460}; 461 462static void sh_eth_set_rate_sh7757(struct net_device *ndev) 463{ 464 struct sh_eth_private *mdp = netdev_priv(ndev); 465 466 switch (mdp->speed) { 467 case 10: /* 10BASE */ 468 sh_eth_write(ndev, 0, RTRATE); 469 break; 470 case 100:/* 100BASE */ 471 sh_eth_write(ndev, 1, RTRATE); 472 break; 473 default: 474 break; 475 } 476} 477 478/* SH7757 */ 479static struct sh_eth_cpu_data sh7757_data = { 480 .set_duplex = sh_eth_set_duplex, 481 .set_rate = sh_eth_set_rate_sh7757, 482 483 .register_type = SH_ETH_REG_FAST_SH4, 484 485 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 486 .rmcr_value = RMCR_RNC, 487 488 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO, 489 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | 490 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | 491 EESR_ECI, 492 493 .irq_flags = IRQF_SHARED, 494 .apr = 1, 495 .mpr = 1, 496 .tpauser = 1, 497 .hw_swap = 1, 498 .no_ade = 1, 499 .rpadir = 1, 500 .rpadir_value = 2 << 16, 501}; 502 503#define SH_GIGA_ETH_BASE 0xfee00000UL 504#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8) 505#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0) 506static void sh_eth_chip_reset_giga(struct net_device *ndev) 507{ 508 int i; 509 unsigned long mahr[2], malr[2]; 510 511 /* save MAHR and MALR */ 512 for (i = 0; i < 2; i++) { 513 malr[i] = ioread32((void *)GIGA_MALR(i)); 514 mahr[i] = ioread32((void *)GIGA_MAHR(i)); 515 } 516 517 /* reset device */ 518 iowrite32(ARSTR_ARSTR, (void *)(SH_GIGA_ETH_BASE + 0x1800)); 519 mdelay(1); 520 521 /* restore MAHR and MALR */ 522 for (i = 0; i < 2; i++) { 523 iowrite32(malr[i], (void *)GIGA_MALR(i)); 524 iowrite32(mahr[i], (void *)GIGA_MAHR(i)); 525 } 526} 527 528static void sh_eth_set_rate_giga(struct net_device *ndev) 529{ 530 struct sh_eth_private *mdp = netdev_priv(ndev); 531 532 switch (mdp->speed) { 533 case 10: /* 10BASE */ 534 sh_eth_write(ndev, 0x00000000, GECMR); 535 break; 536 case 100:/* 100BASE */ 537 sh_eth_write(ndev, 0x00000010, GECMR); 538 break; 539 case 1000: /* 1000BASE */ 540 sh_eth_write(ndev, 0x00000020, GECMR); 541 break; 542 default: 543 break; 544 } 545} 546 547/* SH7757(GETHERC) */ 548static struct sh_eth_cpu_data sh7757_data_giga = { 549 .chip_reset = sh_eth_chip_reset_giga, 550 .set_duplex = sh_eth_set_duplex, 551 .set_rate = sh_eth_set_rate_giga, 552 553 .register_type = SH_ETH_REG_GIGABIT, 554 555 .ecsr_value = ECSR_ICD | ECSR_MPD, 556 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 557 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 558 559 .tx_check = EESR_TC1 | EESR_FTC, 560 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 561 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 562 EESR_TDE | EESR_ECI, 563 .fdr_value = 0x0000072f, 564 .rmcr_value = RMCR_RNC, 565 566 .irq_flags = IRQF_SHARED, 567 .apr = 1, 568 .mpr = 1, 569 .tpauser = 1, 570 .bculr = 1, 571 .hw_swap = 1, 572 .rpadir = 1, 573 .rpadir_value = 2 << 16, 574 .no_trimd = 1, 575 .no_ade = 1, 576 .tsu = 1, 577}; 578 579static void sh_eth_chip_reset(struct net_device *ndev) 580{ 581 struct sh_eth_private *mdp = netdev_priv(ndev); 582 583 /* reset device */ 584 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 585 mdelay(1); 586} 587 588static void sh_eth_set_rate_gether(struct net_device *ndev) 589{ 590 struct sh_eth_private *mdp = netdev_priv(ndev); 591 592 switch (mdp->speed) { 593 case 10: /* 10BASE */ 594 sh_eth_write(ndev, GECMR_10, GECMR); 595 break; 596 case 100:/* 100BASE */ 597 sh_eth_write(ndev, GECMR_100, GECMR); 598 break; 599 case 1000: /* 1000BASE */ 600 sh_eth_write(ndev, GECMR_1000, GECMR); 601 break; 602 default: 603 break; 604 } 605} 606 607/* SH7734 */ 608static struct sh_eth_cpu_data sh7734_data = { 609 .chip_reset = sh_eth_chip_reset, 610 .set_duplex = sh_eth_set_duplex, 611 .set_rate = sh_eth_set_rate_gether, 612 613 .register_type = SH_ETH_REG_GIGABIT, 614 615 .ecsr_value = ECSR_ICD | ECSR_MPD, 616 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 617 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 618 619 .tx_check = EESR_TC1 | EESR_FTC, 620 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 621 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 622 EESR_TDE | EESR_ECI, 623 624 .apr = 1, 625 .mpr = 1, 626 .tpauser = 1, 627 .bculr = 1, 628 .hw_swap = 1, 629 .no_trimd = 1, 630 .no_ade = 1, 631 .tsu = 1, 632 .hw_crc = 1, 633 .select_mii = 1, 634}; 635 636/* SH7763 */ 637static struct sh_eth_cpu_data sh7763_data = { 638 .chip_reset = sh_eth_chip_reset, 639 .set_duplex = sh_eth_set_duplex, 640 .set_rate = sh_eth_set_rate_gether, 641 642 .register_type = SH_ETH_REG_GIGABIT, 643 644 .ecsr_value = ECSR_ICD | ECSR_MPD, 645 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 646 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 647 648 .tx_check = EESR_TC1 | EESR_FTC, 649 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \ 650 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \ 651 EESR_ECI, 652 653 .apr = 1, 654 .mpr = 1, 655 .tpauser = 1, 656 .bculr = 1, 657 .hw_swap = 1, 658 .no_trimd = 1, 659 .no_ade = 1, 660 .tsu = 1, 661 .irq_flags = IRQF_SHARED, 662}; 663 664static void sh_eth_chip_reset_r8a7740(struct net_device *ndev) 665{ 666 struct sh_eth_private *mdp = netdev_priv(ndev); 667 668 /* reset device */ 669 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR); 670 mdelay(1); 671 672 sh_eth_select_mii(ndev); 673} 674 675/* R8A7740 */ 676static struct sh_eth_cpu_data r8a7740_data = { 677 .chip_reset = sh_eth_chip_reset_r8a7740, 678 .set_duplex = sh_eth_set_duplex, 679 .set_rate = sh_eth_set_rate_gether, 680 681 .register_type = SH_ETH_REG_GIGABIT, 682 683 .ecsr_value = ECSR_ICD | ECSR_MPD, 684 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP, 685 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 686 687 .tx_check = EESR_TC1 | EESR_FTC, 688 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | 689 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE | 690 EESR_TDE | EESR_ECI, 691 .fdr_value = 0x0000070f, 692 .rmcr_value = RMCR_RNC, 693 694 .apr = 1, 695 .mpr = 1, 696 .tpauser = 1, 697 .bculr = 1, 698 .hw_swap = 1, 699 .rpadir = 1, 700 .rpadir_value = 2 << 16, 701 .no_trimd = 1, 702 .no_ade = 1, 703 .tsu = 1, 704 .select_mii = 1, 705 .shift_rd0 = 1, 706}; 707 708static struct sh_eth_cpu_data sh7619_data = { 709 .register_type = SH_ETH_REG_FAST_SH3_SH2, 710 711 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 712 713 .apr = 1, 714 .mpr = 1, 715 .tpauser = 1, 716 .hw_swap = 1, 717}; 718 719static struct sh_eth_cpu_data sh771x_data = { 720 .register_type = SH_ETH_REG_FAST_SH3_SH2, 721 722 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff, 723 .tsu = 1, 724}; 725 726static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd) 727{ 728 if (!cd->ecsr_value) 729 cd->ecsr_value = DEFAULT_ECSR_INIT; 730 731 if (!cd->ecsipr_value) 732 cd->ecsipr_value = DEFAULT_ECSIPR_INIT; 733 734 if (!cd->fcftr_value) 735 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \ 736 DEFAULT_FIFO_F_D_RFD; 737 738 if (!cd->fdr_value) 739 cd->fdr_value = DEFAULT_FDR_INIT; 740 741 if (!cd->rmcr_value) 742 cd->rmcr_value = DEFAULT_RMCR_VALUE; 743 744 if (!cd->tx_check) 745 cd->tx_check = DEFAULT_TX_CHECK; 746 747 if (!cd->eesr_err_check) 748 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK; 749} 750 751static int sh_eth_check_reset(struct net_device *ndev) 752{ 753 int ret = 0; 754 int cnt = 100; 755 756 while (cnt > 0) { 757 if (!(sh_eth_read(ndev, EDMR) & 0x3)) 758 break; 759 mdelay(1); 760 cnt--; 761 } 762 if (cnt <= 0) { 763 pr_err("Device reset failed\n"); 764 ret = -ETIMEDOUT; 765 } 766 return ret; 767} 768 769static int sh_eth_reset(struct net_device *ndev) 770{ 771 struct sh_eth_private *mdp = netdev_priv(ndev); 772 int ret = 0; 773 774 if (sh_eth_is_gether(mdp)) { 775 sh_eth_write(ndev, EDSR_ENALL, EDSR); 776 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, 777 EDMR); 778 779 ret = sh_eth_check_reset(ndev); 780 if (ret) 781 goto out; 782 783 /* Table Init */ 784 sh_eth_write(ndev, 0x0, TDLAR); 785 sh_eth_write(ndev, 0x0, TDFAR); 786 sh_eth_write(ndev, 0x0, TDFXR); 787 sh_eth_write(ndev, 0x0, TDFFR); 788 sh_eth_write(ndev, 0x0, RDLAR); 789 sh_eth_write(ndev, 0x0, RDFAR); 790 sh_eth_write(ndev, 0x0, RDFXR); 791 sh_eth_write(ndev, 0x0, RDFFR); 792 793 /* Reset HW CRC register */ 794 if (mdp->cd->hw_crc) 795 sh_eth_write(ndev, 0x0, CSMR); 796 797 /* Select MII mode */ 798 if (mdp->cd->select_mii) 799 sh_eth_select_mii(ndev); 800 } else { 801 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, 802 EDMR); 803 mdelay(3); 804 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, 805 EDMR); 806 } 807 808out: 809 return ret; 810} 811 812#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE) 813static void sh_eth_set_receive_align(struct sk_buff *skb) 814{ 815 int reserve; 816 817 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1)); 818 if (reserve) 819 skb_reserve(skb, reserve); 820} 821#else 822static void sh_eth_set_receive_align(struct sk_buff *skb) 823{ 824 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN); 825} 826#endif 827 828 829/* CPU <-> EDMAC endian convert */ 830static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x) 831{ 832 switch (mdp->edmac_endian) { 833 case EDMAC_LITTLE_ENDIAN: 834 return cpu_to_le32(x); 835 case EDMAC_BIG_ENDIAN: 836 return cpu_to_be32(x); 837 } 838 return x; 839} 840 841static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x) 842{ 843 switch (mdp->edmac_endian) { 844 case EDMAC_LITTLE_ENDIAN: 845 return le32_to_cpu(x); 846 case EDMAC_BIG_ENDIAN: 847 return be32_to_cpu(x); 848 } 849 return x; 850} 851 852/* 853 * Program the hardware MAC address from dev->dev_addr. 854 */ 855static void update_mac_address(struct net_device *ndev) 856{ 857 sh_eth_write(ndev, 858 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) | 859 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR); 860 sh_eth_write(ndev, 861 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR); 862} 863 864/* 865 * Get MAC address from SuperH MAC address register 866 * 867 * SuperH's Ethernet device doesn't have 'ROM' to MAC address. 868 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g). 869 * When you want use this device, you must set MAC address in bootloader. 870 * 871 */ 872static void read_mac_address(struct net_device *ndev, unsigned char *mac) 873{ 874 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) { 875 memcpy(ndev->dev_addr, mac, ETH_ALEN); 876 } else { 877 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24); 878 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF; 879 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF; 880 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF); 881 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF; 882 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF); 883 } 884} 885 886static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp) 887{ 888 if (sh_eth_is_gether(mdp)) 889 return EDTRR_TRNS_GETHER; 890 else 891 return EDTRR_TRNS_ETHER; 892} 893 894struct bb_info { 895 void (*set_gate)(void *addr); 896 struct mdiobb_ctrl ctrl; 897 void *addr; 898 u32 mmd_msk;/* MMD */ 899 u32 mdo_msk; 900 u32 mdi_msk; 901 u32 mdc_msk; 902}; 903 904/* PHY bit set */ 905static void bb_set(void *addr, u32 msk) 906{ 907 iowrite32(ioread32(addr) | msk, addr); 908} 909 910/* PHY bit clear */ 911static void bb_clr(void *addr, u32 msk) 912{ 913 iowrite32((ioread32(addr) & ~msk), addr); 914} 915 916/* PHY bit read */ 917static int bb_read(void *addr, u32 msk) 918{ 919 return (ioread32(addr) & msk) != 0; 920} 921 922/* Data I/O pin control */ 923static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit) 924{ 925 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 926 927 if (bitbang->set_gate) 928 bitbang->set_gate(bitbang->addr); 929 930 if (bit) 931 bb_set(bitbang->addr, bitbang->mmd_msk); 932 else 933 bb_clr(bitbang->addr, bitbang->mmd_msk); 934} 935 936/* Set bit data*/ 937static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit) 938{ 939 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 940 941 if (bitbang->set_gate) 942 bitbang->set_gate(bitbang->addr); 943 944 if (bit) 945 bb_set(bitbang->addr, bitbang->mdo_msk); 946 else 947 bb_clr(bitbang->addr, bitbang->mdo_msk); 948} 949 950/* Get bit data*/ 951static int sh_get_mdio(struct mdiobb_ctrl *ctrl) 952{ 953 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 954 955 if (bitbang->set_gate) 956 bitbang->set_gate(bitbang->addr); 957 958 return bb_read(bitbang->addr, bitbang->mdi_msk); 959} 960 961/* MDC pin control */ 962static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit) 963{ 964 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl); 965 966 if (bitbang->set_gate) 967 bitbang->set_gate(bitbang->addr); 968 969 if (bit) 970 bb_set(bitbang->addr, bitbang->mdc_msk); 971 else 972 bb_clr(bitbang->addr, bitbang->mdc_msk); 973} 974 975/* mdio bus control struct */ 976static struct mdiobb_ops bb_ops = { 977 .owner = THIS_MODULE, 978 .set_mdc = sh_mdc_ctrl, 979 .set_mdio_dir = sh_mmd_ctrl, 980 .set_mdio_data = sh_set_mdio, 981 .get_mdio_data = sh_get_mdio, 982}; 983 984/* free skb and descriptor buffer */ 985static void sh_eth_ring_free(struct net_device *ndev) 986{ 987 struct sh_eth_private *mdp = netdev_priv(ndev); 988 int i; 989 990 /* Free Rx skb ringbuffer */ 991 if (mdp->rx_skbuff) { 992 for (i = 0; i < mdp->num_rx_ring; i++) { 993 if (mdp->rx_skbuff[i]) 994 dev_kfree_skb(mdp->rx_skbuff[i]); 995 } 996 } 997 kfree(mdp->rx_skbuff); 998 mdp->rx_skbuff = NULL; 999 1000 /* Free Tx skb ringbuffer */ 1001 if (mdp->tx_skbuff) { 1002 for (i = 0; i < mdp->num_tx_ring; i++) { 1003 if (mdp->tx_skbuff[i]) 1004 dev_kfree_skb(mdp->tx_skbuff[i]); 1005 } 1006 } 1007 kfree(mdp->tx_skbuff); 1008 mdp->tx_skbuff = NULL; 1009} 1010 1011/* format skb and descriptor buffer */ 1012static void sh_eth_ring_format(struct net_device *ndev) 1013{ 1014 struct sh_eth_private *mdp = netdev_priv(ndev); 1015 int i; 1016 struct sk_buff *skb; 1017 struct sh_eth_rxdesc *rxdesc = NULL; 1018 struct sh_eth_txdesc *txdesc = NULL; 1019 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring; 1020 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring; 1021 1022 mdp->cur_rx = mdp->cur_tx = 0; 1023 mdp->dirty_rx = mdp->dirty_tx = 0; 1024 1025 memset(mdp->rx_ring, 0, rx_ringsize); 1026 1027 /* build Rx ring buffer */ 1028 for (i = 0; i < mdp->num_rx_ring; i++) { 1029 /* skb */ 1030 mdp->rx_skbuff[i] = NULL; 1031 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 1032 mdp->rx_skbuff[i] = skb; 1033 if (skb == NULL) 1034 break; 1035 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 1036 DMA_FROM_DEVICE); 1037 sh_eth_set_receive_align(skb); 1038 1039 /* RX descriptor */ 1040 rxdesc = &mdp->rx_ring[i]; 1041 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 1042 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1043 1044 /* The size of the buffer is 16 byte boundary. */ 1045 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 1046 /* Rx descriptor address set */ 1047 if (i == 0) { 1048 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR); 1049 if (sh_eth_is_gether(mdp)) 1050 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR); 1051 } 1052 } 1053 1054 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring); 1055 1056 /* Mark the last entry as wrapping the ring. */ 1057 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL); 1058 1059 memset(mdp->tx_ring, 0, tx_ringsize); 1060 1061 /* build Tx ring buffer */ 1062 for (i = 0; i < mdp->num_tx_ring; i++) { 1063 mdp->tx_skbuff[i] = NULL; 1064 txdesc = &mdp->tx_ring[i]; 1065 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1066 txdesc->buffer_length = 0; 1067 if (i == 0) { 1068 /* Tx descriptor address set */ 1069 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR); 1070 if (sh_eth_is_gether(mdp)) 1071 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR); 1072 } 1073 } 1074 1075 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1076} 1077 1078/* Get skb and descriptor buffer */ 1079static int sh_eth_ring_init(struct net_device *ndev) 1080{ 1081 struct sh_eth_private *mdp = netdev_priv(ndev); 1082 int rx_ringsize, tx_ringsize, ret = 0; 1083 1084 /* 1085 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the 1086 * card needs room to do 8 byte alignment, +2 so we can reserve 1087 * the first 2 bytes, and +16 gets room for the status word from the 1088 * card. 1089 */ 1090 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : 1091 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16)); 1092 if (mdp->cd->rpadir) 1093 mdp->rx_buf_sz += NET_IP_ALIGN; 1094 1095 /* Allocate RX and TX skb rings */ 1096 mdp->rx_skbuff = kmalloc_array(mdp->num_rx_ring, 1097 sizeof(*mdp->rx_skbuff), GFP_KERNEL); 1098 if (!mdp->rx_skbuff) { 1099 ret = -ENOMEM; 1100 return ret; 1101 } 1102 1103 mdp->tx_skbuff = kmalloc_array(mdp->num_tx_ring, 1104 sizeof(*mdp->tx_skbuff), GFP_KERNEL); 1105 if (!mdp->tx_skbuff) { 1106 ret = -ENOMEM; 1107 goto skb_ring_free; 1108 } 1109 1110 /* Allocate all Rx descriptors. */ 1111 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1112 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma, 1113 GFP_KERNEL); 1114 if (!mdp->rx_ring) { 1115 ret = -ENOMEM; 1116 goto desc_ring_free; 1117 } 1118 1119 mdp->dirty_rx = 0; 1120 1121 /* Allocate all Tx descriptors. */ 1122 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1123 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma, 1124 GFP_KERNEL); 1125 if (!mdp->tx_ring) { 1126 ret = -ENOMEM; 1127 goto desc_ring_free; 1128 } 1129 return ret; 1130 1131desc_ring_free: 1132 /* free DMA buffer */ 1133 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma); 1134 1135skb_ring_free: 1136 /* Free Rx and Tx skb ring buffer */ 1137 sh_eth_ring_free(ndev); 1138 mdp->tx_ring = NULL; 1139 mdp->rx_ring = NULL; 1140 1141 return ret; 1142} 1143 1144static void sh_eth_free_dma_buffer(struct sh_eth_private *mdp) 1145{ 1146 int ringsize; 1147 1148 if (mdp->rx_ring) { 1149 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring; 1150 dma_free_coherent(NULL, ringsize, mdp->rx_ring, 1151 mdp->rx_desc_dma); 1152 mdp->rx_ring = NULL; 1153 } 1154 1155 if (mdp->tx_ring) { 1156 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring; 1157 dma_free_coherent(NULL, ringsize, mdp->tx_ring, 1158 mdp->tx_desc_dma); 1159 mdp->tx_ring = NULL; 1160 } 1161} 1162 1163static int sh_eth_dev_init(struct net_device *ndev, bool start) 1164{ 1165 int ret = 0; 1166 struct sh_eth_private *mdp = netdev_priv(ndev); 1167 u32 val; 1168 1169 /* Soft Reset */ 1170 ret = sh_eth_reset(ndev); 1171 if (ret) 1172 goto out; 1173 1174 if (mdp->cd->rmiimode) 1175 sh_eth_write(ndev, 0x1, RMIIMODE); 1176 1177 /* Descriptor format */ 1178 sh_eth_ring_format(ndev); 1179 if (mdp->cd->rpadir) 1180 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR); 1181 1182 /* all sh_eth int mask */ 1183 sh_eth_write(ndev, 0, EESIPR); 1184 1185#if defined(__LITTLE_ENDIAN) 1186 if (mdp->cd->hw_swap) 1187 sh_eth_write(ndev, EDMR_EL, EDMR); 1188 else 1189#endif 1190 sh_eth_write(ndev, 0, EDMR); 1191 1192 /* FIFO size set */ 1193 sh_eth_write(ndev, mdp->cd->fdr_value, FDR); 1194 sh_eth_write(ndev, 0, TFTR); 1195 1196 /* Frame recv control */ 1197 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR); 1198 1199 sh_eth_write(ndev, DESC_I_RINT8 | DESC_I_RINT5 | DESC_I_TINT2, TRSCER); 1200 1201 if (mdp->cd->bculr) 1202 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */ 1203 1204 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR); 1205 1206 if (!mdp->cd->no_trimd) 1207 sh_eth_write(ndev, 0, TRIMD); 1208 1209 /* Recv frame limit set register */ 1210 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, 1211 RFLR); 1212 1213 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR); 1214 if (start) 1215 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1216 1217 /* PAUSE Prohibition */ 1218 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) | 1219 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE; 1220 1221 sh_eth_write(ndev, val, ECMR); 1222 1223 if (mdp->cd->set_rate) 1224 mdp->cd->set_rate(ndev); 1225 1226 /* E-MAC Status Register clear */ 1227 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR); 1228 1229 /* E-MAC Interrupt Enable register */ 1230 if (start) 1231 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR); 1232 1233 /* Set MAC address */ 1234 update_mac_address(ndev); 1235 1236 /* mask reset */ 1237 if (mdp->cd->apr) 1238 sh_eth_write(ndev, APR_AP, APR); 1239 if (mdp->cd->mpr) 1240 sh_eth_write(ndev, MPR_MP, MPR); 1241 if (mdp->cd->tpauser) 1242 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER); 1243 1244 if (start) { 1245 /* Setting the Rx mode will start the Rx process. */ 1246 sh_eth_write(ndev, EDRRR_R, EDRRR); 1247 1248 netif_start_queue(ndev); 1249 } 1250 1251out: 1252 return ret; 1253} 1254 1255/* free Tx skb function */ 1256static int sh_eth_txfree(struct net_device *ndev) 1257{ 1258 struct sh_eth_private *mdp = netdev_priv(ndev); 1259 struct sh_eth_txdesc *txdesc; 1260 int freeNum = 0; 1261 int entry = 0; 1262 1263 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) { 1264 entry = mdp->dirty_tx % mdp->num_tx_ring; 1265 txdesc = &mdp->tx_ring[entry]; 1266 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT)) 1267 break; 1268 /* Free the original skb. */ 1269 if (mdp->tx_skbuff[entry]) { 1270 dma_unmap_single(&ndev->dev, txdesc->addr, 1271 txdesc->buffer_length, DMA_TO_DEVICE); 1272 dev_kfree_skb_irq(mdp->tx_skbuff[entry]); 1273 mdp->tx_skbuff[entry] = NULL; 1274 freeNum++; 1275 } 1276 txdesc->status = cpu_to_edmac(mdp, TD_TFP); 1277 if (entry >= mdp->num_tx_ring - 1) 1278 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE); 1279 1280 ndev->stats.tx_packets++; 1281 ndev->stats.tx_bytes += txdesc->buffer_length; 1282 } 1283 return freeNum; 1284} 1285 1286/* Packet receive function */ 1287static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota) 1288{ 1289 struct sh_eth_private *mdp = netdev_priv(ndev); 1290 struct sh_eth_rxdesc *rxdesc; 1291 1292 int entry = mdp->cur_rx % mdp->num_rx_ring; 1293 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx; 1294 struct sk_buff *skb; 1295 int exceeded = 0; 1296 u16 pkt_len = 0; 1297 u32 desc_status; 1298 1299 rxdesc = &mdp->rx_ring[entry]; 1300 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) { 1301 desc_status = edmac_to_cpu(mdp, rxdesc->status); 1302 pkt_len = rxdesc->frame_length; 1303 1304 if (--boguscnt < 0) 1305 break; 1306 1307 if (*quota <= 0) { 1308 exceeded = 1; 1309 break; 1310 } 1311 (*quota)--; 1312 1313 if (!(desc_status & RDFEND)) 1314 ndev->stats.rx_length_errors++; 1315 1316 /* 1317 * In case of almost all GETHER/ETHERs, the Receive Frame State 1318 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to 1319 * bit 0. However, in case of the R8A7740's GETHER, the RFS 1320 * bits are from bit 25 to bit 16. So, the driver needs right 1321 * shifting by 16. 1322 */ 1323 if (mdp->cd->shift_rd0) 1324 desc_status >>= 16; 1325 1326 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 | 1327 RD_RFS5 | RD_RFS6 | RD_RFS10)) { 1328 ndev->stats.rx_errors++; 1329 if (desc_status & RD_RFS1) 1330 ndev->stats.rx_crc_errors++; 1331 if (desc_status & RD_RFS2) 1332 ndev->stats.rx_frame_errors++; 1333 if (desc_status & RD_RFS3) 1334 ndev->stats.rx_length_errors++; 1335 if (desc_status & RD_RFS4) 1336 ndev->stats.rx_length_errors++; 1337 if (desc_status & RD_RFS6) 1338 ndev->stats.rx_missed_errors++; 1339 if (desc_status & RD_RFS10) 1340 ndev->stats.rx_over_errors++; 1341 } else { 1342 if (!mdp->cd->hw_swap) 1343 sh_eth_soft_swap( 1344 phys_to_virt(ALIGN(rxdesc->addr, 4)), 1345 pkt_len + 2); 1346 skb = mdp->rx_skbuff[entry]; 1347 mdp->rx_skbuff[entry] = NULL; 1348 if (mdp->cd->rpadir) 1349 skb_reserve(skb, NET_IP_ALIGN); 1350 dma_sync_single_for_cpu(&ndev->dev, rxdesc->addr, 1351 mdp->rx_buf_sz, 1352 DMA_FROM_DEVICE); 1353 skb_put(skb, pkt_len); 1354 skb->protocol = eth_type_trans(skb, ndev); 1355 netif_receive_skb(skb); 1356 ndev->stats.rx_packets++; 1357 ndev->stats.rx_bytes += pkt_len; 1358 } 1359 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT); 1360 entry = (++mdp->cur_rx) % mdp->num_rx_ring; 1361 rxdesc = &mdp->rx_ring[entry]; 1362 } 1363 1364 /* Refill the Rx ring buffers. */ 1365 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) { 1366 entry = mdp->dirty_rx % mdp->num_rx_ring; 1367 rxdesc = &mdp->rx_ring[entry]; 1368 /* The size of the buffer is 16 byte boundary. */ 1369 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16); 1370 1371 if (mdp->rx_skbuff[entry] == NULL) { 1372 skb = netdev_alloc_skb(ndev, mdp->rx_buf_sz); 1373 mdp->rx_skbuff[entry] = skb; 1374 if (skb == NULL) 1375 break; /* Better luck next round. */ 1376 dma_map_single(&ndev->dev, skb->data, mdp->rx_buf_sz, 1377 DMA_FROM_DEVICE); 1378 sh_eth_set_receive_align(skb); 1379 1380 skb_checksum_none_assert(skb); 1381 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4)); 1382 } 1383 if (entry >= mdp->num_rx_ring - 1) 1384 rxdesc->status |= 1385 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL); 1386 else 1387 rxdesc->status |= 1388 cpu_to_edmac(mdp, RD_RACT | RD_RFP); 1389 } 1390 1391 /* Restart Rx engine if stopped. */ 1392 /* If we don't need to check status, don't. -KDU */ 1393 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) { 1394 /* fix the values for the next receiving if RDE is set */ 1395 if (intr_status & EESR_RDE) 1396 mdp->cur_rx = mdp->dirty_rx = 1397 (sh_eth_read(ndev, RDFAR) - 1398 sh_eth_read(ndev, RDLAR)) >> 4; 1399 sh_eth_write(ndev, EDRRR_R, EDRRR); 1400 } 1401 1402 return exceeded; 1403} 1404 1405static void sh_eth_rcv_snd_disable(struct net_device *ndev) 1406{ 1407 /* disable tx and rx */ 1408 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & 1409 ~(ECMR_RE | ECMR_TE), ECMR); 1410} 1411 1412static void sh_eth_rcv_snd_enable(struct net_device *ndev) 1413{ 1414 /* enable tx and rx */ 1415 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | 1416 (ECMR_RE | ECMR_TE), ECMR); 1417} 1418 1419/* error control function */ 1420static void sh_eth_error(struct net_device *ndev, int intr_status) 1421{ 1422 struct sh_eth_private *mdp = netdev_priv(ndev); 1423 u32 felic_stat; 1424 u32 link_stat; 1425 u32 mask; 1426 1427 if (intr_status & EESR_ECI) { 1428 felic_stat = sh_eth_read(ndev, ECSR); 1429 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */ 1430 if (felic_stat & ECSR_ICD) 1431 ndev->stats.tx_carrier_errors++; 1432 if (felic_stat & ECSR_LCHNG) { 1433 /* Link Changed */ 1434 if (mdp->cd->no_psr || mdp->no_ether_link) { 1435 goto ignore_link; 1436 } else { 1437 link_stat = (sh_eth_read(ndev, PSR)); 1438 if (mdp->ether_link_active_low) 1439 link_stat = ~link_stat; 1440 } 1441 if (!(link_stat & PHY_ST_LINK)) 1442 sh_eth_rcv_snd_disable(ndev); 1443 else { 1444 /* Link Up */ 1445 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) & 1446 ~DMAC_M_ECI, EESIPR); 1447 /*clear int */ 1448 sh_eth_write(ndev, sh_eth_read(ndev, ECSR), 1449 ECSR); 1450 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) | 1451 DMAC_M_ECI, EESIPR); 1452 /* enable tx and rx */ 1453 sh_eth_rcv_snd_enable(ndev); 1454 } 1455 } 1456 } 1457 1458ignore_link: 1459 if (intr_status & EESR_TWB) { 1460 /* Unused write back interrupt */ 1461 if (intr_status & EESR_TABT) { /* Transmit Abort int */ 1462 ndev->stats.tx_aborted_errors++; 1463 if (netif_msg_tx_err(mdp)) 1464 dev_err(&ndev->dev, "Transmit Abort\n"); 1465 } 1466 } 1467 1468 if (intr_status & EESR_RABT) { 1469 /* Receive Abort int */ 1470 if (intr_status & EESR_RFRMER) { 1471 /* Receive Frame Overflow int */ 1472 ndev->stats.rx_frame_errors++; 1473 if (netif_msg_rx_err(mdp)) 1474 dev_err(&ndev->dev, "Receive Abort\n"); 1475 } 1476 } 1477 1478 if (intr_status & EESR_TDE) { 1479 /* Transmit Descriptor Empty int */ 1480 ndev->stats.tx_fifo_errors++; 1481 if (netif_msg_tx_err(mdp)) 1482 dev_err(&ndev->dev, "Transmit Descriptor Empty\n"); 1483 } 1484 1485 if (intr_status & EESR_TFE) { 1486 /* FIFO under flow */ 1487 ndev->stats.tx_fifo_errors++; 1488 if (netif_msg_tx_err(mdp)) 1489 dev_err(&ndev->dev, "Transmit FIFO Under flow\n"); 1490 } 1491 1492 if (intr_status & EESR_RDE) { 1493 /* Receive Descriptor Empty int */ 1494 ndev->stats.rx_over_errors++; 1495 1496 if (netif_msg_rx_err(mdp)) 1497 dev_err(&ndev->dev, "Receive Descriptor Empty\n"); 1498 } 1499 1500 if (intr_status & EESR_RFE) { 1501 /* Receive FIFO Overflow int */ 1502 ndev->stats.rx_fifo_errors++; 1503 if (netif_msg_rx_err(mdp)) 1504 dev_err(&ndev->dev, "Receive FIFO Overflow\n"); 1505 } 1506 1507 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) { 1508 /* Address Error */ 1509 ndev->stats.tx_fifo_errors++; 1510 if (netif_msg_tx_err(mdp)) 1511 dev_err(&ndev->dev, "Address Error\n"); 1512 } 1513 1514 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE; 1515 if (mdp->cd->no_ade) 1516 mask &= ~EESR_ADE; 1517 if (intr_status & mask) { 1518 /* Tx error */ 1519 u32 edtrr = sh_eth_read(ndev, EDTRR); 1520 /* dmesg */ 1521 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ", 1522 intr_status, mdp->cur_tx); 1523 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n", 1524 mdp->dirty_tx, (u32) ndev->state, edtrr); 1525 /* dirty buffer free */ 1526 sh_eth_txfree(ndev); 1527 1528 /* SH7712 BUG */ 1529 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) { 1530 /* tx dma start */ 1531 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 1532 } 1533 /* wakeup */ 1534 netif_wake_queue(ndev); 1535 } 1536} 1537 1538static irqreturn_t sh_eth_interrupt(int irq, void *netdev) 1539{ 1540 struct net_device *ndev = netdev; 1541 struct sh_eth_private *mdp = netdev_priv(ndev); 1542 struct sh_eth_cpu_data *cd = mdp->cd; 1543 irqreturn_t ret = IRQ_NONE; 1544 unsigned long intr_status, intr_enable; 1545 1546 spin_lock(&mdp->lock); 1547 1548 /* Get interrupt status */ 1549 intr_status = sh_eth_read(ndev, EESR); 1550 /* Mask it with the interrupt mask, forcing ECI interrupt to be always 1551 * enabled since it's the one that comes thru regardless of the mask, 1552 * and we need to fully handle it in sh_eth_error() in order to quench 1553 * it as it doesn't get cleared by just writing 1 to the ECI bit... 1554 */ 1555 intr_enable = sh_eth_read(ndev, EESIPR); 1556 intr_status &= intr_enable | DMAC_M_ECI; 1557 if (intr_status & (EESR_RX_CHECK | cd->tx_check | cd->eesr_err_check)) 1558 ret = IRQ_HANDLED; 1559 else 1560 goto other_irq; 1561 1562 if (intr_status & EESR_RX_CHECK) { 1563 if (napi_schedule_prep(&mdp->napi)) { 1564 /* Mask Rx interrupts */ 1565 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK, 1566 EESIPR); 1567 __napi_schedule(&mdp->napi); 1568 } else { 1569 dev_warn(&ndev->dev, 1570 "ignoring interrupt, status 0x%08lx, mask 0x%08lx.\n", 1571 intr_status, intr_enable); 1572 } 1573 } 1574 1575 /* Tx Check */ 1576 if (intr_status & cd->tx_check) { 1577 /* Clear Tx interrupts */ 1578 sh_eth_write(ndev, intr_status & cd->tx_check, EESR); 1579 1580 sh_eth_txfree(ndev); 1581 netif_wake_queue(ndev); 1582 } 1583 1584 if (intr_status & cd->eesr_err_check) { 1585 /* Clear error interrupts */ 1586 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR); 1587 1588 sh_eth_error(ndev, intr_status); 1589 } 1590 1591other_irq: 1592 spin_unlock(&mdp->lock); 1593 1594 return ret; 1595} 1596 1597static int sh_eth_poll(struct napi_struct *napi, int budget) 1598{ 1599 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private, 1600 napi); 1601 struct net_device *ndev = napi->dev; 1602 int quota = budget; 1603 unsigned long intr_status; 1604 1605 for (;;) { 1606 intr_status = sh_eth_read(ndev, EESR); 1607 if (!(intr_status & EESR_RX_CHECK)) 1608 break; 1609 /* Clear Rx interrupts */ 1610 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR); 1611 1612 if (sh_eth_rx(ndev, intr_status, "a)) 1613 goto out; 1614 } 1615 1616 napi_complete(napi); 1617 1618 /* Reenable Rx interrupts */ 1619 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1620out: 1621 return budget - quota; 1622} 1623 1624/* PHY state control function */ 1625static void sh_eth_adjust_link(struct net_device *ndev) 1626{ 1627 struct sh_eth_private *mdp = netdev_priv(ndev); 1628 struct phy_device *phydev = mdp->phydev; 1629 int new_state = 0; 1630 1631 if (phydev->link) { 1632 if (phydev->duplex != mdp->duplex) { 1633 new_state = 1; 1634 mdp->duplex = phydev->duplex; 1635 if (mdp->cd->set_duplex) 1636 mdp->cd->set_duplex(ndev); 1637 } 1638 1639 if (phydev->speed != mdp->speed) { 1640 new_state = 1; 1641 mdp->speed = phydev->speed; 1642 if (mdp->cd->set_rate) 1643 mdp->cd->set_rate(ndev); 1644 } 1645 if (!mdp->link) { 1646 sh_eth_write(ndev, 1647 (sh_eth_read(ndev, ECMR) & ~ECMR_TXF), ECMR); 1648 new_state = 1; 1649 mdp->link = phydev->link; 1650 if (mdp->cd->no_psr || mdp->no_ether_link) 1651 sh_eth_rcv_snd_enable(ndev); 1652 } 1653 } else if (mdp->link) { 1654 new_state = 1; 1655 mdp->link = 0; 1656 mdp->speed = 0; 1657 mdp->duplex = -1; 1658 if (mdp->cd->no_psr || mdp->no_ether_link) 1659 sh_eth_rcv_snd_disable(ndev); 1660 } 1661 1662 if (new_state && netif_msg_link(mdp)) 1663 phy_print_status(phydev); 1664} 1665 1666/* PHY init function */ 1667static int sh_eth_phy_init(struct net_device *ndev) 1668{ 1669 struct sh_eth_private *mdp = netdev_priv(ndev); 1670 char phy_id[MII_BUS_ID_SIZE + 3]; 1671 struct phy_device *phydev = NULL; 1672 1673 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, 1674 mdp->mii_bus->id , mdp->phy_id); 1675 1676 mdp->link = 0; 1677 mdp->speed = 0; 1678 mdp->duplex = -1; 1679 1680 /* Try connect to PHY */ 1681 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link, 1682 mdp->phy_interface); 1683 if (IS_ERR(phydev)) { 1684 dev_err(&ndev->dev, "phy_connect failed\n"); 1685 return PTR_ERR(phydev); 1686 } 1687 1688 dev_info(&ndev->dev, "attached phy %i to driver %s\n", 1689 phydev->addr, phydev->drv->name); 1690 1691 mdp->phydev = phydev; 1692 1693 return 0; 1694} 1695 1696/* PHY control start function */ 1697static int sh_eth_phy_start(struct net_device *ndev) 1698{ 1699 struct sh_eth_private *mdp = netdev_priv(ndev); 1700 int ret; 1701 1702 ret = sh_eth_phy_init(ndev); 1703 if (ret) 1704 return ret; 1705 1706 /* reset phy - this also wakes it from PDOWN */ 1707 ret = phy_init_hw(mdp->phydev); 1708 if (ret) 1709 return ret; 1710 1711 phy_start(mdp->phydev); 1712 1713 return 0; 1714} 1715 1716static int sh_eth_get_settings(struct net_device *ndev, 1717 struct ethtool_cmd *ecmd) 1718{ 1719 struct sh_eth_private *mdp = netdev_priv(ndev); 1720 unsigned long flags; 1721 int ret; 1722 1723 spin_lock_irqsave(&mdp->lock, flags); 1724 ret = phy_ethtool_gset(mdp->phydev, ecmd); 1725 spin_unlock_irqrestore(&mdp->lock, flags); 1726 1727 return ret; 1728} 1729 1730static int sh_eth_set_settings(struct net_device *ndev, 1731 struct ethtool_cmd *ecmd) 1732{ 1733 struct sh_eth_private *mdp = netdev_priv(ndev); 1734 unsigned long flags; 1735 int ret; 1736 1737 spin_lock_irqsave(&mdp->lock, flags); 1738 1739 /* disable tx and rx */ 1740 sh_eth_rcv_snd_disable(ndev); 1741 1742 ret = phy_ethtool_sset(mdp->phydev, ecmd); 1743 if (ret) 1744 goto error_exit; 1745 1746 if (ecmd->duplex == DUPLEX_FULL) 1747 mdp->duplex = 1; 1748 else 1749 mdp->duplex = 0; 1750 1751 if (mdp->cd->set_duplex) 1752 mdp->cd->set_duplex(ndev); 1753 1754error_exit: 1755 mdelay(1); 1756 1757 /* enable tx and rx */ 1758 sh_eth_rcv_snd_enable(ndev); 1759 1760 spin_unlock_irqrestore(&mdp->lock, flags); 1761 1762 return ret; 1763} 1764 1765static int sh_eth_nway_reset(struct net_device *ndev) 1766{ 1767 struct sh_eth_private *mdp = netdev_priv(ndev); 1768 unsigned long flags; 1769 int ret; 1770 1771 spin_lock_irqsave(&mdp->lock, flags); 1772 ret = phy_start_aneg(mdp->phydev); 1773 spin_unlock_irqrestore(&mdp->lock, flags); 1774 1775 return ret; 1776} 1777 1778static u32 sh_eth_get_msglevel(struct net_device *ndev) 1779{ 1780 struct sh_eth_private *mdp = netdev_priv(ndev); 1781 return mdp->msg_enable; 1782} 1783 1784static void sh_eth_set_msglevel(struct net_device *ndev, u32 value) 1785{ 1786 struct sh_eth_private *mdp = netdev_priv(ndev); 1787 mdp->msg_enable = value; 1788} 1789 1790static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = { 1791 "rx_current", "tx_current", 1792 "rx_dirty", "tx_dirty", 1793}; 1794#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats) 1795 1796static int sh_eth_get_sset_count(struct net_device *netdev, int sset) 1797{ 1798 switch (sset) { 1799 case ETH_SS_STATS: 1800 return SH_ETH_STATS_LEN; 1801 default: 1802 return -EOPNOTSUPP; 1803 } 1804} 1805 1806static void sh_eth_get_ethtool_stats(struct net_device *ndev, 1807 struct ethtool_stats *stats, u64 *data) 1808{ 1809 struct sh_eth_private *mdp = netdev_priv(ndev); 1810 int i = 0; 1811 1812 /* device-specific stats */ 1813 data[i++] = mdp->cur_rx; 1814 data[i++] = mdp->cur_tx; 1815 data[i++] = mdp->dirty_rx; 1816 data[i++] = mdp->dirty_tx; 1817} 1818 1819static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 1820{ 1821 switch (stringset) { 1822 case ETH_SS_STATS: 1823 memcpy(data, *sh_eth_gstrings_stats, 1824 sizeof(sh_eth_gstrings_stats)); 1825 break; 1826 } 1827} 1828 1829static void sh_eth_get_ringparam(struct net_device *ndev, 1830 struct ethtool_ringparam *ring) 1831{ 1832 struct sh_eth_private *mdp = netdev_priv(ndev); 1833 1834 ring->rx_max_pending = RX_RING_MAX; 1835 ring->tx_max_pending = TX_RING_MAX; 1836 ring->rx_pending = mdp->num_rx_ring; 1837 ring->tx_pending = mdp->num_tx_ring; 1838} 1839 1840static int sh_eth_set_ringparam(struct net_device *ndev, 1841 struct ethtool_ringparam *ring) 1842{ 1843 struct sh_eth_private *mdp = netdev_priv(ndev); 1844 int ret; 1845 1846 if (ring->tx_pending > TX_RING_MAX || 1847 ring->rx_pending > RX_RING_MAX || 1848 ring->tx_pending < TX_RING_MIN || 1849 ring->rx_pending < RX_RING_MIN) 1850 return -EINVAL; 1851 if (ring->rx_mini_pending || ring->rx_jumbo_pending) 1852 return -EINVAL; 1853 1854 if (netif_running(ndev)) { 1855 netif_tx_disable(ndev); 1856 /* Disable interrupts by clearing the interrupt mask. */ 1857 sh_eth_write(ndev, 0x0000, EESIPR); 1858 /* Stop the chip's Tx and Rx processes. */ 1859 sh_eth_write(ndev, 0, EDTRR); 1860 sh_eth_write(ndev, 0, EDRRR); 1861 synchronize_irq(ndev->irq); 1862 } 1863 1864 /* Free all the skbuffs in the Rx queue. */ 1865 sh_eth_ring_free(ndev); 1866 /* Free DMA buffer */ 1867 sh_eth_free_dma_buffer(mdp); 1868 1869 /* Set new parameters */ 1870 mdp->num_rx_ring = ring->rx_pending; 1871 mdp->num_tx_ring = ring->tx_pending; 1872 1873 ret = sh_eth_ring_init(ndev); 1874 if (ret < 0) { 1875 dev_err(&ndev->dev, "%s: sh_eth_ring_init failed.\n", __func__); 1876 return ret; 1877 } 1878 ret = sh_eth_dev_init(ndev, false); 1879 if (ret < 0) { 1880 dev_err(&ndev->dev, "%s: sh_eth_dev_init failed.\n", __func__); 1881 return ret; 1882 } 1883 1884 if (netif_running(ndev)) { 1885 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR); 1886 /* Setting the Rx mode will start the Rx process. */ 1887 sh_eth_write(ndev, EDRRR_R, EDRRR); 1888 netif_wake_queue(ndev); 1889 } 1890 1891 return 0; 1892} 1893 1894static const struct ethtool_ops sh_eth_ethtool_ops = { 1895 .get_settings = sh_eth_get_settings, 1896 .set_settings = sh_eth_set_settings, 1897 .nway_reset = sh_eth_nway_reset, 1898 .get_msglevel = sh_eth_get_msglevel, 1899 .set_msglevel = sh_eth_set_msglevel, 1900 .get_link = ethtool_op_get_link, 1901 .get_strings = sh_eth_get_strings, 1902 .get_ethtool_stats = sh_eth_get_ethtool_stats, 1903 .get_sset_count = sh_eth_get_sset_count, 1904 .get_ringparam = sh_eth_get_ringparam, 1905 .set_ringparam = sh_eth_set_ringparam, 1906}; 1907 1908/* network device open function */ 1909static int sh_eth_open(struct net_device *ndev) 1910{ 1911 int ret = 0; 1912 struct sh_eth_private *mdp = netdev_priv(ndev); 1913 1914 pm_runtime_get_sync(&mdp->pdev->dev); 1915 1916 napi_enable(&mdp->napi); 1917 1918 ret = request_irq(ndev->irq, sh_eth_interrupt, 1919 mdp->cd->irq_flags, ndev->name, ndev); 1920 if (ret) { 1921 dev_err(&ndev->dev, "Can not assign IRQ number\n"); 1922 goto out_napi_off; 1923 } 1924 1925 /* Descriptor set */ 1926 ret = sh_eth_ring_init(ndev); 1927 if (ret) 1928 goto out_free_irq; 1929 1930 /* device init */ 1931 ret = sh_eth_dev_init(ndev, true); 1932 if (ret) 1933 goto out_free_irq; 1934 1935 /* PHY control start*/ 1936 ret = sh_eth_phy_start(ndev); 1937 if (ret) 1938 goto out_free_irq; 1939 1940 return ret; 1941 1942out_free_irq: 1943 free_irq(ndev->irq, ndev); 1944out_napi_off: 1945 napi_disable(&mdp->napi); 1946 pm_runtime_put_sync(&mdp->pdev->dev); 1947 return ret; 1948} 1949 1950/* Timeout function */ 1951static void sh_eth_tx_timeout(struct net_device *ndev) 1952{ 1953 struct sh_eth_private *mdp = netdev_priv(ndev); 1954 struct sh_eth_rxdesc *rxdesc; 1955 int i; 1956 1957 netif_stop_queue(ndev); 1958 1959 if (netif_msg_timer(mdp)) 1960 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x," 1961 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR)); 1962 1963 /* tx_errors count up */ 1964 ndev->stats.tx_errors++; 1965 1966 /* Free all the skbuffs in the Rx queue. */ 1967 for (i = 0; i < mdp->num_rx_ring; i++) { 1968 rxdesc = &mdp->rx_ring[i]; 1969 rxdesc->status = 0; 1970 rxdesc->addr = 0xBADF00D0; 1971 if (mdp->rx_skbuff[i]) 1972 dev_kfree_skb(mdp->rx_skbuff[i]); 1973 mdp->rx_skbuff[i] = NULL; 1974 } 1975 for (i = 0; i < mdp->num_tx_ring; i++) { 1976 if (mdp->tx_skbuff[i]) 1977 dev_kfree_skb(mdp->tx_skbuff[i]); 1978 mdp->tx_skbuff[i] = NULL; 1979 } 1980 1981 /* device init */ 1982 sh_eth_dev_init(ndev, true); 1983} 1984 1985/* Packet transmit function */ 1986static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev) 1987{ 1988 struct sh_eth_private *mdp = netdev_priv(ndev); 1989 struct sh_eth_txdesc *txdesc; 1990 u32 entry; 1991 unsigned long flags; 1992 1993 spin_lock_irqsave(&mdp->lock, flags); 1994 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) { 1995 if (!sh_eth_txfree(ndev)) { 1996 if (netif_msg_tx_queued(mdp)) 1997 dev_warn(&ndev->dev, "TxFD exhausted.\n"); 1998 netif_stop_queue(ndev); 1999 spin_unlock_irqrestore(&mdp->lock, flags); 2000 return NETDEV_TX_BUSY; 2001 } 2002 } 2003 spin_unlock_irqrestore(&mdp->lock, flags); 2004 2005 entry = mdp->cur_tx % mdp->num_tx_ring; 2006 mdp->tx_skbuff[entry] = skb; 2007 txdesc = &mdp->tx_ring[entry]; 2008 /* soft swap. */ 2009 if (!mdp->cd->hw_swap) 2010 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)), 2011 skb->len + 2); 2012 txdesc->addr = dma_map_single(&ndev->dev, skb->data, skb->len, 2013 DMA_TO_DEVICE); 2014 if (skb->len < ETHERSMALL) 2015 txdesc->buffer_length = ETHERSMALL; 2016 else 2017 txdesc->buffer_length = skb->len; 2018 2019 if (entry >= mdp->num_tx_ring - 1) 2020 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE); 2021 else 2022 txdesc->status |= cpu_to_edmac(mdp, TD_TACT); 2023 2024 mdp->cur_tx++; 2025 2026 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp))) 2027 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR); 2028 2029 return NETDEV_TX_OK; 2030} 2031 2032/* device close function */ 2033static int sh_eth_close(struct net_device *ndev) 2034{ 2035 struct sh_eth_private *mdp = netdev_priv(ndev); 2036 2037 netif_stop_queue(ndev); 2038 2039 /* Disable interrupts by clearing the interrupt mask. */ 2040 sh_eth_write(ndev, 0x0000, EESIPR); 2041 2042 /* Stop the chip's Tx and Rx processes. */ 2043 sh_eth_write(ndev, 0, EDTRR); 2044 sh_eth_write(ndev, 0, EDRRR); 2045 2046 /* PHY Disconnect */ 2047 if (mdp->phydev) { 2048 phy_stop(mdp->phydev); 2049 phy_disconnect(mdp->phydev); 2050 } 2051 2052 free_irq(ndev->irq, ndev); 2053 2054 napi_disable(&mdp->napi); 2055 2056 /* Free all the skbuffs in the Rx queue. */ 2057 sh_eth_ring_free(ndev); 2058 2059 /* free DMA buffer */ 2060 sh_eth_free_dma_buffer(mdp); 2061 2062 pm_runtime_put_sync(&mdp->pdev->dev); 2063 2064 return 0; 2065} 2066 2067static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev) 2068{ 2069 struct sh_eth_private *mdp = netdev_priv(ndev); 2070 2071 pm_runtime_get_sync(&mdp->pdev->dev); 2072 2073 ndev->stats.tx_dropped += sh_eth_read(ndev, TROCR); 2074 sh_eth_write(ndev, 0, TROCR); /* (write clear) */ 2075 ndev->stats.collisions += sh_eth_read(ndev, CDCR); 2076 sh_eth_write(ndev, 0, CDCR); /* (write clear) */ 2077 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR); 2078 sh_eth_write(ndev, 0, LCCR); /* (write clear) */ 2079 if (sh_eth_is_gether(mdp)) { 2080 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR); 2081 sh_eth_write(ndev, 0, CERCR); /* (write clear) */ 2082 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR); 2083 sh_eth_write(ndev, 0, CEECR); /* (write clear) */ 2084 } else { 2085 ndev->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR); 2086 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */ 2087 } 2088 pm_runtime_put_sync(&mdp->pdev->dev); 2089 2090 return &ndev->stats; 2091} 2092 2093/* ioctl to device function */ 2094static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, 2095 int cmd) 2096{ 2097 struct sh_eth_private *mdp = netdev_priv(ndev); 2098 struct phy_device *phydev = mdp->phydev; 2099 2100 if (!netif_running(ndev)) 2101 return -EINVAL; 2102 2103 if (!phydev) 2104 return -ENODEV; 2105 2106 return phy_mii_ioctl(phydev, rq, cmd); 2107} 2108 2109/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */ 2110static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp, 2111 int entry) 2112{ 2113 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4); 2114} 2115 2116static u32 sh_eth_tsu_get_post_mask(int entry) 2117{ 2118 return 0x0f << (28 - ((entry % 8) * 4)); 2119} 2120 2121static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry) 2122{ 2123 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4)); 2124} 2125 2126static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev, 2127 int entry) 2128{ 2129 struct sh_eth_private *mdp = netdev_priv(ndev); 2130 u32 tmp; 2131 void *reg_offset; 2132 2133 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2134 tmp = ioread32(reg_offset); 2135 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset); 2136} 2137 2138static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev, 2139 int entry) 2140{ 2141 struct sh_eth_private *mdp = netdev_priv(ndev); 2142 u32 post_mask, ref_mask, tmp; 2143 void *reg_offset; 2144 2145 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry); 2146 post_mask = sh_eth_tsu_get_post_mask(entry); 2147 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask; 2148 2149 tmp = ioread32(reg_offset); 2150 iowrite32(tmp & ~post_mask, reg_offset); 2151 2152 /* If other port enables, the function returns "true" */ 2153 return tmp & ref_mask; 2154} 2155 2156static int sh_eth_tsu_busy(struct net_device *ndev) 2157{ 2158 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100; 2159 struct sh_eth_private *mdp = netdev_priv(ndev); 2160 2161 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) { 2162 udelay(10); 2163 timeout--; 2164 if (timeout <= 0) { 2165 dev_err(&ndev->dev, "%s: timeout\n", __func__); 2166 return -ETIMEDOUT; 2167 } 2168 } 2169 2170 return 0; 2171} 2172 2173static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg, 2174 const u8 *addr) 2175{ 2176 u32 val; 2177 2178 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3]; 2179 iowrite32(val, reg); 2180 if (sh_eth_tsu_busy(ndev) < 0) 2181 return -EBUSY; 2182 2183 val = addr[4] << 8 | addr[5]; 2184 iowrite32(val, reg + 4); 2185 if (sh_eth_tsu_busy(ndev) < 0) 2186 return -EBUSY; 2187 2188 return 0; 2189} 2190 2191static void sh_eth_tsu_read_entry(void *reg, u8 *addr) 2192{ 2193 u32 val; 2194 2195 val = ioread32(reg); 2196 addr[0] = (val >> 24) & 0xff; 2197 addr[1] = (val >> 16) & 0xff; 2198 addr[2] = (val >> 8) & 0xff; 2199 addr[3] = val & 0xff; 2200 val = ioread32(reg + 4); 2201 addr[4] = (val >> 8) & 0xff; 2202 addr[5] = val & 0xff; 2203} 2204 2205 2206static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr) 2207{ 2208 struct sh_eth_private *mdp = netdev_priv(ndev); 2209 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2210 int i; 2211 u8 c_addr[ETH_ALEN]; 2212 2213 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2214 sh_eth_tsu_read_entry(reg_offset, c_addr); 2215 if (memcmp(addr, c_addr, ETH_ALEN) == 0) 2216 return i; 2217 } 2218 2219 return -ENOENT; 2220} 2221 2222static int sh_eth_tsu_find_empty(struct net_device *ndev) 2223{ 2224 u8 blank[ETH_ALEN]; 2225 int entry; 2226 2227 memset(blank, 0, sizeof(blank)); 2228 entry = sh_eth_tsu_find_entry(ndev, blank); 2229 return (entry < 0) ? -ENOMEM : entry; 2230} 2231 2232static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev, 2233 int entry) 2234{ 2235 struct sh_eth_private *mdp = netdev_priv(ndev); 2236 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2237 int ret; 2238 u8 blank[ETH_ALEN]; 2239 2240 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) & 2241 ~(1 << (31 - entry)), TSU_TEN); 2242 2243 memset(blank, 0, sizeof(blank)); 2244 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank); 2245 if (ret < 0) 2246 return ret; 2247 return 0; 2248} 2249 2250static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr) 2251{ 2252 struct sh_eth_private *mdp = netdev_priv(ndev); 2253 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2254 int i, ret; 2255 2256 if (!mdp->cd->tsu) 2257 return 0; 2258 2259 i = sh_eth_tsu_find_entry(ndev, addr); 2260 if (i < 0) { 2261 /* No entry found, create one */ 2262 i = sh_eth_tsu_find_empty(ndev); 2263 if (i < 0) 2264 return -ENOMEM; 2265 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr); 2266 if (ret < 0) 2267 return ret; 2268 2269 /* Enable the entry */ 2270 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) | 2271 (1 << (31 - i)), TSU_TEN); 2272 } 2273 2274 /* Entry found or created, enable POST */ 2275 sh_eth_tsu_enable_cam_entry_post(ndev, i); 2276 2277 return 0; 2278} 2279 2280static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr) 2281{ 2282 struct sh_eth_private *mdp = netdev_priv(ndev); 2283 int i, ret; 2284 2285 if (!mdp->cd->tsu) 2286 return 0; 2287 2288 i = sh_eth_tsu_find_entry(ndev, addr); 2289 if (i) { 2290 /* Entry found */ 2291 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2292 goto done; 2293 2294 /* Disable the entry if both ports was disabled */ 2295 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2296 if (ret < 0) 2297 return ret; 2298 } 2299done: 2300 return 0; 2301} 2302 2303static int sh_eth_tsu_purge_all(struct net_device *ndev) 2304{ 2305 struct sh_eth_private *mdp = netdev_priv(ndev); 2306 int i, ret; 2307 2308 if (unlikely(!mdp->cd->tsu)) 2309 return 0; 2310 2311 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) { 2312 if (sh_eth_tsu_disable_cam_entry_post(ndev, i)) 2313 continue; 2314 2315 /* Disable the entry if both ports was disabled */ 2316 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i); 2317 if (ret < 0) 2318 return ret; 2319 } 2320 2321 return 0; 2322} 2323 2324static void sh_eth_tsu_purge_mcast(struct net_device *ndev) 2325{ 2326 struct sh_eth_private *mdp = netdev_priv(ndev); 2327 u8 addr[ETH_ALEN]; 2328 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0); 2329 int i; 2330 2331 if (unlikely(!mdp->cd->tsu)) 2332 return; 2333 2334 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) { 2335 sh_eth_tsu_read_entry(reg_offset, addr); 2336 if (is_multicast_ether_addr(addr)) 2337 sh_eth_tsu_del_entry(ndev, addr); 2338 } 2339} 2340 2341/* Multicast reception directions set */ 2342static void sh_eth_set_multicast_list(struct net_device *ndev) 2343{ 2344 struct sh_eth_private *mdp = netdev_priv(ndev); 2345 u32 ecmr_bits; 2346 int mcast_all = 0; 2347 unsigned long flags; 2348 2349 spin_lock_irqsave(&mdp->lock, flags); 2350 /* 2351 * Initial condition is MCT = 1, PRM = 0. 2352 * Depending on ndev->flags, set PRM or clear MCT 2353 */ 2354 ecmr_bits = (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) | ECMR_MCT; 2355 2356 if (!(ndev->flags & IFF_MULTICAST)) { 2357 sh_eth_tsu_purge_mcast(ndev); 2358 mcast_all = 1; 2359 } 2360 if (ndev->flags & IFF_ALLMULTI) { 2361 sh_eth_tsu_purge_mcast(ndev); 2362 ecmr_bits &= ~ECMR_MCT; 2363 mcast_all = 1; 2364 } 2365 2366 if (ndev->flags & IFF_PROMISC) { 2367 sh_eth_tsu_purge_all(ndev); 2368 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM; 2369 } else if (mdp->cd->tsu) { 2370 struct netdev_hw_addr *ha; 2371 netdev_for_each_mc_addr(ha, ndev) { 2372 if (mcast_all && is_multicast_ether_addr(ha->addr)) 2373 continue; 2374 2375 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) { 2376 if (!mcast_all) { 2377 sh_eth_tsu_purge_mcast(ndev); 2378 ecmr_bits &= ~ECMR_MCT; 2379 mcast_all = 1; 2380 } 2381 } 2382 } 2383 } else { 2384 /* Normal, unicast/broadcast-only mode. */ 2385 ecmr_bits = (ecmr_bits & ~ECMR_PRM) | ECMR_MCT; 2386 } 2387 2388 /* update the ethernet mode */ 2389 sh_eth_write(ndev, ecmr_bits, ECMR); 2390 2391 spin_unlock_irqrestore(&mdp->lock, flags); 2392} 2393 2394static int sh_eth_get_vtag_index(struct sh_eth_private *mdp) 2395{ 2396 if (!mdp->port) 2397 return TSU_VTAG0; 2398 else 2399 return TSU_VTAG1; 2400} 2401 2402static int sh_eth_vlan_rx_add_vid(struct net_device *ndev, 2403 __be16 proto, u16 vid) 2404{ 2405 struct sh_eth_private *mdp = netdev_priv(ndev); 2406 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2407 2408 if (unlikely(!mdp->cd->tsu)) 2409 return -EPERM; 2410 2411 /* No filtering if vid = 0 */ 2412 if (!vid) 2413 return 0; 2414 2415 mdp->vlan_num_ids++; 2416 2417 /* 2418 * The controller has one VLAN tag HW filter. So, if the filter is 2419 * already enabled, the driver disables it and the filte 2420 */ 2421 if (mdp->vlan_num_ids > 1) { 2422 /* disable VLAN filter */ 2423 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2424 return 0; 2425 } 2426 2427 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK), 2428 vtag_reg_index); 2429 2430 return 0; 2431} 2432 2433static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev, 2434 __be16 proto, u16 vid) 2435{ 2436 struct sh_eth_private *mdp = netdev_priv(ndev); 2437 int vtag_reg_index = sh_eth_get_vtag_index(mdp); 2438 2439 if (unlikely(!mdp->cd->tsu)) 2440 return -EPERM; 2441 2442 /* No filtering if vid = 0 */ 2443 if (!vid) 2444 return 0; 2445 2446 mdp->vlan_num_ids--; 2447 sh_eth_tsu_write(mdp, 0, vtag_reg_index); 2448 2449 return 0; 2450} 2451 2452/* SuperH's TSU register init function */ 2453static void sh_eth_tsu_init(struct sh_eth_private *mdp) 2454{ 2455 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */ 2456 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */ 2457 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */ 2458 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0); 2459 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1); 2460 sh_eth_tsu_write(mdp, 0, TSU_PRISL0); 2461 sh_eth_tsu_write(mdp, 0, TSU_PRISL1); 2462 sh_eth_tsu_write(mdp, 0, TSU_FWSL0); 2463 sh_eth_tsu_write(mdp, 0, TSU_FWSL1); 2464 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); 2465 if (sh_eth_is_gether(mdp)) { 2466 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ 2467 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */ 2468 } else { 2469 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */ 2470 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */ 2471 } 2472 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ 2473 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ 2474 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ 2475 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */ 2476 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */ 2477 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */ 2478 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */ 2479} 2480 2481/* MDIO bus release function */ 2482static int sh_mdio_release(struct net_device *ndev) 2483{ 2484 struct mii_bus *bus = dev_get_drvdata(&ndev->dev); 2485 2486 /* unregister mdio bus */ 2487 mdiobus_unregister(bus); 2488 2489 /* remove mdio bus info from net_device */ 2490 dev_set_drvdata(&ndev->dev, NULL); 2491 2492 /* free bitbang info */ 2493 free_mdio_bitbang(bus); 2494 2495 return 0; 2496} 2497 2498/* MDIO bus init function */ 2499static int sh_mdio_init(struct net_device *ndev, int id, 2500 struct sh_eth_plat_data *pd) 2501{ 2502 int ret, i; 2503 struct bb_info *bitbang; 2504 struct sh_eth_private *mdp = netdev_priv(ndev); 2505 2506 /* create bit control struct for PHY */ 2507 bitbang = devm_kzalloc(&ndev->dev, sizeof(struct bb_info), 2508 GFP_KERNEL); 2509 if (!bitbang) { 2510 ret = -ENOMEM; 2511 goto out; 2512 } 2513 2514 /* bitbang init */ 2515 bitbang->addr = mdp->addr + mdp->reg_offset[PIR]; 2516 bitbang->set_gate = pd->set_mdio_gate; 2517 bitbang->mdi_msk = PIR_MDI; 2518 bitbang->mdo_msk = PIR_MDO; 2519 bitbang->mmd_msk = PIR_MMD; 2520 bitbang->mdc_msk = PIR_MDC; 2521 bitbang->ctrl.ops = &bb_ops; 2522 2523 /* MII controller setting */ 2524 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl); 2525 if (!mdp->mii_bus) { 2526 ret = -ENOMEM; 2527 goto out; 2528 } 2529 2530 /* Hook up MII support for ethtool */ 2531 mdp->mii_bus->name = "sh_mii"; 2532 mdp->mii_bus->parent = &ndev->dev; 2533 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 2534 mdp->pdev->name, id); 2535 2536 /* PHY IRQ */ 2537 mdp->mii_bus->irq = devm_kzalloc(&ndev->dev, 2538 sizeof(int) * PHY_MAX_ADDR, 2539 GFP_KERNEL); 2540 if (!mdp->mii_bus->irq) { 2541 ret = -ENOMEM; 2542 goto out_free_bus; 2543 } 2544 2545 for (i = 0; i < PHY_MAX_ADDR; i++) 2546 mdp->mii_bus->irq[i] = PHY_POLL; 2547 2548 /* register mdio bus */ 2549 ret = mdiobus_register(mdp->mii_bus); 2550 if (ret) 2551 goto out_free_bus; 2552 2553 dev_set_drvdata(&ndev->dev, mdp->mii_bus); 2554 2555 return 0; 2556 2557out_free_bus: 2558 free_mdio_bitbang(mdp->mii_bus); 2559 2560out: 2561 return ret; 2562} 2563 2564static const u16 *sh_eth_get_register_offset(int register_type) 2565{ 2566 const u16 *reg_offset = NULL; 2567 2568 switch (register_type) { 2569 case SH_ETH_REG_GIGABIT: 2570 reg_offset = sh_eth_offset_gigabit; 2571 break; 2572 case SH_ETH_REG_FAST_RCAR: 2573 reg_offset = sh_eth_offset_fast_rcar; 2574 break; 2575 case SH_ETH_REG_FAST_SH4: 2576 reg_offset = sh_eth_offset_fast_sh4; 2577 break; 2578 case SH_ETH_REG_FAST_SH3_SH2: 2579 reg_offset = sh_eth_offset_fast_sh3_sh2; 2580 break; 2581 default: 2582 pr_err("Unknown register type (%d)\n", register_type); 2583 break; 2584 } 2585 2586 return reg_offset; 2587} 2588 2589static const struct net_device_ops sh_eth_netdev_ops = { 2590 .ndo_open = sh_eth_open, 2591 .ndo_stop = sh_eth_close, 2592 .ndo_start_xmit = sh_eth_start_xmit, 2593 .ndo_get_stats = sh_eth_get_stats, 2594 .ndo_tx_timeout = sh_eth_tx_timeout, 2595 .ndo_do_ioctl = sh_eth_do_ioctl, 2596 .ndo_validate_addr = eth_validate_addr, 2597 .ndo_set_mac_address = eth_mac_addr, 2598 .ndo_change_mtu = eth_change_mtu, 2599}; 2600 2601static const struct net_device_ops sh_eth_netdev_ops_tsu = { 2602 .ndo_open = sh_eth_open, 2603 .ndo_stop = sh_eth_close, 2604 .ndo_start_xmit = sh_eth_start_xmit, 2605 .ndo_get_stats = sh_eth_get_stats, 2606 .ndo_set_rx_mode = sh_eth_set_multicast_list, 2607 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid, 2608 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid, 2609 .ndo_tx_timeout = sh_eth_tx_timeout, 2610 .ndo_do_ioctl = sh_eth_do_ioctl, 2611 .ndo_validate_addr = eth_validate_addr, 2612 .ndo_set_mac_address = eth_mac_addr, 2613 .ndo_change_mtu = eth_change_mtu, 2614}; 2615 2616static int sh_eth_drv_probe(struct platform_device *pdev) 2617{ 2618 int ret, devno = 0; 2619 struct resource *res; 2620 struct net_device *ndev = NULL; 2621 struct sh_eth_private *mdp = NULL; 2622 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev); 2623 const struct platform_device_id *id = platform_get_device_id(pdev); 2624 2625 /* get base addr */ 2626 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2627 if (unlikely(res == NULL)) { 2628 dev_err(&pdev->dev, "invalid resource\n"); 2629 ret = -EINVAL; 2630 goto out; 2631 } 2632 2633 ndev = alloc_etherdev(sizeof(struct sh_eth_private)); 2634 if (!ndev) { 2635 ret = -ENOMEM; 2636 goto out; 2637 } 2638 2639 /* The sh Ether-specific entries in the device structure. */ 2640 ndev->base_addr = res->start; 2641 devno = pdev->id; 2642 if (devno < 0) 2643 devno = 0; 2644 2645 ndev->dma = -1; 2646 ret = platform_get_irq(pdev, 0); 2647 if (ret < 0) { 2648 ret = -ENODEV; 2649 goto out_release; 2650 } 2651 ndev->irq = ret; 2652 2653 SET_NETDEV_DEV(ndev, &pdev->dev); 2654 2655 mdp = netdev_priv(ndev); 2656 mdp->num_tx_ring = TX_RING_SIZE; 2657 mdp->num_rx_ring = RX_RING_SIZE; 2658 mdp->addr = devm_ioremap_resource(&pdev->dev, res); 2659 if (IS_ERR(mdp->addr)) { 2660 ret = PTR_ERR(mdp->addr); 2661 goto out_release; 2662 } 2663 2664 spin_lock_init(&mdp->lock); 2665 mdp->pdev = pdev; 2666 pm_runtime_enable(&pdev->dev); 2667 pm_runtime_resume(&pdev->dev); 2668 2669 if (!pd) { 2670 dev_err(&pdev->dev, "no platform data\n"); 2671 ret = -EINVAL; 2672 goto out_release; 2673 } 2674 2675 /* get PHY ID */ 2676 mdp->phy_id = pd->phy; 2677 mdp->phy_interface = pd->phy_interface; 2678 /* EDMAC endian */ 2679 mdp->edmac_endian = pd->edmac_endian; 2680 mdp->no_ether_link = pd->no_ether_link; 2681 mdp->ether_link_active_low = pd->ether_link_active_low; 2682 2683 /* set cpu data */ 2684 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data; 2685 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type); 2686 sh_eth_set_default_cpu_data(mdp->cd); 2687 2688 /* set function */ 2689 if (mdp->cd->tsu) 2690 ndev->netdev_ops = &sh_eth_netdev_ops_tsu; 2691 else 2692 ndev->netdev_ops = &sh_eth_netdev_ops; 2693 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops); 2694 ndev->watchdog_timeo = TX_TIMEOUT; 2695 2696 /* debug message level */ 2697 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE; 2698 2699 /* read and set MAC address */ 2700 read_mac_address(ndev, pd->mac_addr); 2701 if (!is_valid_ether_addr(ndev->dev_addr)) { 2702 dev_warn(&pdev->dev, 2703 "no valid MAC address supplied, using a random one.\n"); 2704 eth_hw_addr_random(ndev); 2705 } 2706 2707 /* ioremap the TSU registers */ 2708 if (mdp->cd->tsu) { 2709 struct resource *rtsu; 2710 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2711 mdp->tsu_addr = devm_ioremap_resource(&pdev->dev, rtsu); 2712 if (IS_ERR(mdp->tsu_addr)) { 2713 ret = PTR_ERR(mdp->tsu_addr); 2714 goto out_release; 2715 } 2716 mdp->port = devno % 2; 2717 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER; 2718 } 2719 2720 /* initialize first or needed device */ 2721 if (!devno || pd->needs_init) { 2722 if (mdp->cd->chip_reset) 2723 mdp->cd->chip_reset(ndev); 2724 2725 if (mdp->cd->tsu) { 2726 /* TSU init (Init only)*/ 2727 sh_eth_tsu_init(mdp); 2728 } 2729 } 2730 2731 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64); 2732 2733 /* network device register */ 2734 ret = register_netdev(ndev); 2735 if (ret) 2736 goto out_napi_del; 2737 2738 /* mdio bus init */ 2739 ret = sh_mdio_init(ndev, pdev->id, pd); 2740 if (ret) 2741 goto out_unregister; 2742 2743 /* print device information */ 2744 pr_info("Base address at 0x%x, %pM, IRQ %d.\n", 2745 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq); 2746 2747 platform_set_drvdata(pdev, ndev); 2748 2749 return ret; 2750 2751out_unregister: 2752 unregister_netdev(ndev); 2753 2754out_napi_del: 2755 netif_napi_del(&mdp->napi); 2756 2757out_release: 2758 /* net_dev free */ 2759 if (ndev) 2760 free_netdev(ndev); 2761 2762out: 2763 return ret; 2764} 2765 2766static int sh_eth_drv_remove(struct platform_device *pdev) 2767{ 2768 struct net_device *ndev = platform_get_drvdata(pdev); 2769 struct sh_eth_private *mdp = netdev_priv(ndev); 2770 2771 sh_mdio_release(ndev); 2772 unregister_netdev(ndev); 2773 netif_napi_del(&mdp->napi); 2774 pm_runtime_disable(&pdev->dev); 2775 free_netdev(ndev); 2776 2777 return 0; 2778} 2779 2780#ifdef CONFIG_PM 2781static int sh_eth_runtime_nop(struct device *dev) 2782{ 2783 /* 2784 * Runtime PM callback shared between ->runtime_suspend() 2785 * and ->runtime_resume(). Simply returns success. 2786 * 2787 * This driver re-initializes all registers after 2788 * pm_runtime_get_sync() anyway so there is no need 2789 * to save and restore registers here. 2790 */ 2791 return 0; 2792} 2793 2794static const struct dev_pm_ops sh_eth_dev_pm_ops = { 2795 .runtime_suspend = sh_eth_runtime_nop, 2796 .runtime_resume = sh_eth_runtime_nop, 2797}; 2798#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops) 2799#else 2800#define SH_ETH_PM_OPS NULL 2801#endif 2802 2803static struct platform_device_id sh_eth_id_table[] = { 2804 { "sh7619-ether", (kernel_ulong_t)&sh7619_data }, 2805 { "sh771x-ether", (kernel_ulong_t)&sh771x_data }, 2806 { "sh7724-ether", (kernel_ulong_t)&sh7724_data }, 2807 { "sh7734-gether", (kernel_ulong_t)&sh7734_data }, 2808 { "sh7757-ether", (kernel_ulong_t)&sh7757_data }, 2809 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga }, 2810 { "sh7763-gether", (kernel_ulong_t)&sh7763_data }, 2811 { "r8a7740-gether", (kernel_ulong_t)&r8a7740_data }, 2812 { "r8a777x-ether", (kernel_ulong_t)&r8a777x_data }, 2813 { "r8a7790-ether", (kernel_ulong_t)&r8a7790_data }, 2814 { } 2815}; 2816MODULE_DEVICE_TABLE(platform, sh_eth_id_table); 2817 2818static struct platform_driver sh_eth_driver = { 2819 .probe = sh_eth_drv_probe, 2820 .remove = sh_eth_drv_remove, 2821 .id_table = sh_eth_id_table, 2822 .driver = { 2823 .name = CARDNAME, 2824 .pm = SH_ETH_PM_OPS, 2825 }, 2826}; 2827 2828module_platform_driver(sh_eth_driver); 2829 2830MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda"); 2831MODULE_DESCRIPTION("Renesas SuperH Ethernet driver"); 2832MODULE_LICENSE("GPL v2"); 2833